From: Gabe Teeger <gabe.tee...@amd.com>
[what]
Graphics hang observed with 3 displays connected to DP2.0 mst dock.
[why]
There's a mismatch in dml and dc between the assignments of hpo link
encoders.
[how]
Add a new array in dml that tracks the current mapping of HPO stream
encoders to HPO link encoders in dc.
Cc: sta...@vger.kernel.org
Reviewed-by: Sung joon Kim <sungjoon....@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>
Signed-off-by: Gabe Teeger <gabe.tee...@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahf...@amd.com>
---
.../amd/display/dc/dml2/dml2_internal_types.h | 2 +-
.../display/dc/dml2/dml2_translation_helper.c | 67 +++++++++----------
.../display/dc/dml2/dml2_translation_helper.h | 2 +-
.../gpu/drm/amd/display/dc/dml2/dml2_utils.c | 12 +---
4 files changed, 34 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h
index 3ba184be25d3..140ec01545db 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h
@@ -101,7 +101,7 @@ struct dml2_wrapper_scratch {
struct dml2_dml_to_dc_pipe_mapping dml_to_dc_pipe_mapping;
bool enable_flexible_pipe_mapping;
bool plane_duplicate_exists;
- unsigned int dp2_mst_stream_count;
+ int hpo_stream_to_link_encoder_mapping[MAX_HPO_DP2_ENCODERS];
};
struct dml2_helper_det_policy_scratch {
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index 7e39873832bf..bde4250853b1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -733,8 +733,7 @@ static void
populate_dml_timing_cfg_from_stream_state(struct dml_timing_cfg_st *
}
static void populate_dml_output_cfg_from_stream_state(struct dml_output_cfg_st
*out, unsigned int location,
- const struct dc_stream_state *in, const struct
pipe_ctx *pipe,
- unsigned int dp2_mst_stream_count)
+ const struct dc_stream_state *in, const struct
pipe_ctx *pipe, struct dml2_context *dml2)
{
unsigned int output_bpc;
@@ -747,8 +746,8 @@ static void
populate_dml_output_cfg_from_stream_state(struct dml_output_cfg_st *
case SIGNAL_TYPE_DISPLAY_PORT_MST:
case SIGNAL_TYPE_DISPLAY_PORT:
out->OutputEncoder[location] = dml_dp;
- if (is_dp2p0_output_encoder(pipe, dp2_mst_stream_count))
- out->OutputEncoder[location] = dml_dp2p0;
+ if
(dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location] != -1)
+
out->OutputEncoder[dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location]]
= dml_dp2p0;
break;
case SIGNAL_TYPE_EDP:
out->OutputEncoder[location] = dml_edp;
@@ -1199,36 +1198,6 @@ static void
dml2_populate_pipe_to_plane_index_mapping(struct dml2_context *dml2,
}
}
-static unsigned int calculate_dp2_mst_stream_count(struct dc_state *context)
-{
- int i, j;
- unsigned int dp2_mst_stream_count = 0;
-
- for (i = 0; i < context->stream_count; i++) {
- struct dc_stream_state *stream = context->streams[i];
-
- if (!stream || stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
- continue;
-
- for (j = 0; j < MAX_PIPES; j++) {
- struct pipe_ctx *pipe_ctx =
&context->res_ctx.pipe_ctx[j];
-
- if (!pipe_ctx || !pipe_ctx->stream)
- continue;
-
- if (stream != pipe_ctx->stream)
- continue;
-
- if (pipe_ctx->stream_res.hpo_dp_stream_enc &&
pipe_ctx->link_res.hpo_dp_link_enc) {
- dp2_mst_stream_count++;
- break;
- }
- }
- }
-
- return dp2_mst_stream_count;
-}
-
static void populate_dml_writeback_cfg_from_stream_state(struct
dml_writeback_cfg_st *out,
unsigned int location, const struct dc_stream_state *in)
{
@@ -1269,6 +1238,30 @@ static void
populate_dml_writeback_cfg_from_stream_state(struct dml_writeback_cf
}
}
}
+
+static void dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index(struct
dml2_context *dml2, struct dc_state *context)
+{
+ int i;
+ struct pipe_ctx *current_pipe_context;
+
+ /* Scratch gets reset to zero in dml, but link encoder instance can be
zero, so reset to -1 */
+ for (i = 0; i < MAX_HPO_DP2_ENCODERS; i++) {
+ dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[i] = -1;
+ }
+
+ /* If an HPO stream encoder is allocated to a pipe, get the instance of
it's allocated HPO Link encoder */
+ for (i = 0; i < MAX_PIPES; i++) {
+ current_pipe_context = &context->res_ctx.pipe_ctx[i];
+ if (current_pipe_context->stream &&
+ current_pipe_context->stream_res.hpo_dp_stream_enc &&
+ current_pipe_context->link_res.hpo_dp_link_enc &&
+ dc_is_dp_signal(current_pipe_context->stream->signal)) {
+
dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[current_pipe_context->stream_res.hpo_dp_stream_enc->inst]
=
+
current_pipe_context->link_res.hpo_dp_link_enc->inst;
+ }
+ }
+}
+
void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct
dc_state *context, struct dml_display_cfg_st *dml_dispcfg)
{
int i = 0, j = 0, k = 0;
@@ -1291,8 +1284,8 @@ void map_dc_state_into_dml_display_cfg(struct
dml2_context *dml2, struct dc_stat
if (dml2->v20.dml_core_ctx.ip.hostvm_enable)
dml2->v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal =
dml_prefetch_support_uclk_fclk_and_stutter;
- dml2->v20.scratch.dp2_mst_stream_count =
calculate_dp2_mst_stream_count(context);
dml2_populate_pipe_to_plane_index_mapping(dml2, context);
+ dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index(dml2, context);
for (i = 0; i < context->stream_count; i++) {
current_pipe_context = NULL;
@@ -1313,7 +1306,7 @@ void map_dc_state_into_dml_display_cfg(struct
dml2_context *dml2, struct dc_stat
ASSERT(disp_cfg_stream_location >= 0 &&
disp_cfg_stream_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing,
disp_cfg_stream_location, context->streams[i]);
- populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output,
disp_cfg_stream_location, context->streams[i], current_pipe_context,
dml2->v20.scratch.dp2_mst_stream_count);
+ populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output,
disp_cfg_stream_location, context->streams[i], current_pipe_context, dml2);
/*Call site for populate_dml_writeback_cfg_from_stream_state*/
populate_dml_writeback_cfg_from_stream_state(&dml_dispcfg->writeback,
disp_cfg_stream_location, context->streams[i]);
@@ -1378,7 +1371,7 @@ void map_dc_state_into_dml_display_cfg(struct
dml2_context *dml2, struct dc_stat
if (j >= 1) {
populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing,
disp_cfg_plane_location, context->streams[i]);
-
populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output,
disp_cfg_plane_location, context->streams[i], current_pipe_context,
dml2->v20.scratch.dp2_mst_stream_count);
+
populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output,
disp_cfg_plane_location, context->streams[i], current_pipe_context, dml2);
switch
(context->streams[i]->debug.force_odm_combine_segments) {
case 2:
dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_plane_location] =
dml_odm_use_policy_combine_2to1;
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h
index 55659b22d87f..d764773938f4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h
@@ -36,6 +36,6 @@ void dml2_translate_socbb_params(const struct dc *in_dc,
struct soc_bounding_box
void dml2_translate_soc_states(const struct dc *in_dc, struct soc_states_st
*out, int num_states);
void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct
dc_state *context, struct dml_display_cfg_st *dml_dispcfg);
void dml2_update_pipe_ctx_dchub_regs(struct _vcs_dpi_dml_display_rq_regs_st
*rq_regs, struct _vcs_dpi_dml_display_dlg_regs_st *disp_dlg_regs, struct
_vcs_dpi_dml_display_ttu_regs_st *disp_ttu_regs, struct pipe_ctx *out);
-bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe, unsigned int
dp2_mst_stream_count);
+bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe);
#endif //__DML2_TRANSLATION_HELPER_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c
index 9e8ff3a9718e..9a33158b63bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c
@@ -153,7 +153,7 @@ unsigned int
dml2_util_get_maximum_odm_combine_for_output(bool force_odm_4to1, e
}
}
-bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx, unsigned int
dp2_mst_stream_count)
+bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx)
{
if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
return false;
@@ -161,14 +161,6 @@ bool is_dp2p0_output_encoder(const struct pipe_ctx
*pipe_ctx, unsigned int dp2_m
/* If this assert is hit then we have a link encoder dynamic management
issue */
ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ?
pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);
- /* Count MST hubs once by treating only 1st remote sink in topology as
an encoder */
- if (pipe_ctx->stream->link && pipe_ctx->stream->link->remote_sinks[0]
&& dp2_mst_stream_count > 1) {
- return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
- pipe_ctx->link_res.hpo_dp_link_enc &&
- dc_is_dp_signal(pipe_ctx->stream->signal) &&
- (pipe_ctx->stream->link->remote_sinks[0]->sink_id ==
pipe_ctx->stream->sink->sink_id));
- }
-
return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
pipe_ctx->link_res.hpo_dp_link_enc &&
dc_is_dp_signal(pipe_ctx->stream->signal));
@@ -181,7 +173,7 @@ bool is_dtbclk_required(const struct dc *dc, struct
dc_state *context)
for (i = 0; i < dc->res_pool->pipe_count; i++) {
if (!context->res_ctx.pipe_ctx[i].stream)
continue;
- if (is_dp2p0_output_encoder(&context->res_ctx.pipe_ctx[i],
context->bw_ctx.dml2->v20.scratch.dp2_mst_stream_count))
+ if (is_dp2p0_output_encoder(&context->res_ctx.pipe_ctx[i]))
return true;
}
return false;
--
2.46.0
