[AMD Official Use Only - General]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Lazar, Lijo
Sent: Wednesday, October 4, 2023 21:21
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
Subject: [PATCH 4/4] Documentation/amdgpu: Add
[AMD Official Use Only - General]
Series is:
Reviewed-by: Alex Deucher
From: Lazar, Lijo
Sent: Wednesday, October 4, 2023 3:39 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
Subject: [PATCH v2 1/5] drm/amdgpu: Move package type en
Hi Dave, Daniel,
Fixes for 6.6.
The following changes since commit 8a749fd1a8720d4619c91c8b6e7528c0a355c0aa:
Linux 6.6-rc4 (2023-10-01 14:15:13 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-6.6-2023-10-04
for you to fetch
[AMD Official Use Only - General]
Hmm... thinking about it more, will it override the profile mode/workload for
0xC8 or 0xCC SKU as well. In another words, does it mean the pmfw fix is
general to all the 13_0_0 SKUs.
Other than that, the patch looks good to me.
Regards,
Hawking
-Original
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Wednesday, October 4, 2023 23:34
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Liu, Kun
Subject: [PATCH] drm/amdgpu: Enable SMU 13
[AMD Official Use Only - General]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Lazar, Lijo
Sent: Wednesday, October 4, 2023 15:40
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Deucher, Alexander
Subject: [PATCH v2 5/5] D
Hi,
On Sun, Oct 01, 2023 at 07:00:11PM -0500, Mario Limonciello wrote:
> Let me try to add more detail.
>
> This is an OEM system that has 3 USB type C ports. It's an Intel system,
> but this doesn't matter for the issue.
> * when ucsi_acpi is not loaded there are no power supplies in the system
On Wed, Oct 4, 2023 at 5:42 PM Mario Limonciello
wrote:
>
> For pptable structs that use flexible array sizes, use flexible arrays.
>
> Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/2036742
> Signed-off-by: Mario Limonciello
Acked-by: Alex Deucher
> ---
> From this bug report ther
[AMD Official Use Only - General]
Reviewed-by: Qingqing Zhuo
-Original Message-
From: Siqueira, Rodrigo
Sent: Wednesday, October 4, 2023 5:21 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Wentland, Harry
; Li, Sun peng (Leo) ; Siqueira,
Rodrigo ; Pillai, Aurabindo
; Z
On 10/4/2023 1:47 PM, Felix Kuehling wrote:
On 2023-10-03 19:31, Xiaogang.Chen wrote:
From: Xiaogang Chen
This patch implements partial migration in gpu page fault according
to migration
granularity(default 2MB) and not split svm range in cpu page fault
handling.
A svm range may include p
[AMD Official Use Only - General]
Reviewed-by: Qingqing Zhuo
-Original Message-
From: Siqueira, Rodrigo
Sent: Wednesday, October 4, 2023 5:21 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Wentland, Harry
; Li, Sun peng (Leo) ; Siqueira,
Rodrigo ; Pillai, Aurabindo
; Z
On 2023-09-18 06:32, Christian König wrote:
Am 08.09.23 um 18:04 schrieb Shashank Sharma:
To support oversubscription, MES FW expects WPTR BOs to
be mapped into GART, before they are submitted to usermode
queues. This patch adds a function for the same.
V4: fix the wptr value before mapping l
On 2023-09-08 12:04, Shashank Sharma wrote:
From: Alex Deucher
This patch intorduces new UAPI/IOCTL for usermode graphics
queue. The userspace app will fill this structure and request
the graphics driver to add a graphics work queue for it. The
output of this UAPI is a queue id.
This UAPI ma
From: Sung Joon Kim
[why]
There are cases where more than 1 stream can be mapped to the same
surface. DML2.0 does not seem to handle these cases.
[how]
Make sure to account for the stream id when deriving the plane id. By
doing this, each plane id will be unique based on the stream id.
Reviewed
From: Gabe Teeger
[what]
does_configuration_meet_sw_policies check was not done in the
validate_only portion of dml2, so some unsupported modes were passing bw
validation, only to fail the same check later in validate_and_build. now
we add the check to validate_only.
Also add line in dcn35_resou
From: Taimur Hassan
Rework dml2_map_dc_pipes to keep the logic clean.
Reviewed-by: Chaitanya Dhere
Acked-by: Qingqing Zhuo
Signed-off-by: Qingqing Zhuo
Signed-off-by: Taimur Hassan
---
.../amd/display/dc/dml2/dml2_dc_resource_mgmt.c | 9 +
.../gpu/drm/amd/display/dc/dml2/dml2_utils
From: Daniel Miess
Update DML2 with replay vblank logic found in DML1.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Daniel Miess
Signed-off-by: Qingqing Zhuo
---
.../amd/display/dc/dml2/display_mode_core.c | 25 ---
1 file changed, 22 insertions(+), 3 d
From: Charlene Liu
dc->dml2_options.use_native_pstate_optimization flag will make driver
use dcn32 legacy_svp_drr related tuning. Set this to false fixed the
stutter underflow issue also based on HW suggest disable ODM by default
and let DML choose it.
Reviewed-by: Zhan Liu
Acked-by: Qingqing Z
From: Saaem Rizvi
[Why]
There are certain cases during a transition to ODM that might cause
corruption on the display. This occurs when we choose certain pipes in a
particular state.
[How]
We now will store the pipe indexes of the any pipes that might be
problematic to switch to during an ODM tr
From: Taimur Hassan
[Why & How]
DML2 did not carry over DML1 logic that splits pipe for stero timings. Pipe
splitting is needed in this case to pass stereo tests.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Qingqing Zhuo
Signed-off-by: Taimur Hassan
---
.../drm/amd/disp
From: Sung Joon Kim
[why]
Surface height/width for Chroma has another variable that it should be
intialized to, chroma_size. Fixing this will help pass DML2.0 validation
for YCbCr420 tests, DCHB006.109,129, DCHB014.011,012.
[how]
Assign SurfaceHeight/WidthC to chroma_size.height/width
Reviewed-
From: Sung Joon Kim
[why]
Regression from DML1.0 where we use differen DET buffer sizes for each
pipe. From the spec, we need to use DET buffer size of 384 kb for each
pipe
[how]
Ensure to use 384 kb DET buffer sizes for each available pipe.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
S
From: Charlene Liu
Add z8 watermarks to struct for later ASIC use.
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c | 2 ++
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.h | 2 ++
drivers/gpu/drm/am
For some reason, the dml code is not guarded under CONFIG_DRM_AMD_DC_FP
in the Makefile. This commit moves the dml code under the DC_FP guard.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/Makefile | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers
From: Qingqing Zhuo
Enable DML2 for DCN35.
Changes since V1:
- Remove hard coded values
Acked-by: Harry Wentland
Signed-off-by: Alex Deucher
Signed-off-by: Roman Li
Signed-off-by: Qingqing Zhuo
---
.../drm/amd/display/dc/dcn35/dcn35_resource.c | 13 +--
.../dc/dml2/display_mode_core_struct
dce_calcs does not have FPU operations, and it is required for DCE and
DCN. Remove this file from the DML folder and add it to the basic folder
visible for DCE and DCN.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/basics/Makefile | 7 ++-
.../amd/display/dc/
The custom_float file does not have any FPU operation, so it should be
inside DML. This commit moves the file to the basic folder.
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/basics/Makefile| 3 +-
.../dc/{dml/calcs => basics}/custom_float.c | 90 +++
dr
bw_fixed does not need any FPU operation, and it is used on DCE and DCN.
For this reason, this commit moves bw_fixed to the basic folder outside
DML.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/basics/Makefile | 3 ++-
.../amd/display/dc/{dml/calcs => basics}/bw_fixe
This patchset introduces a new version of DML that will be used for some
already available ASIC based on DCN3x and future devices. This new
version of the DML is more reliable, provide a better programming model
for hardware/software, and is more flexible for creating new tools for
automation/valid
On 9/21/23 10:15, Sebastian Andrzej Siewior wrote:
Hi,
I stumbled uppon the amdgpu driver via a bugzilla report. The actual fix
is #4 + #5 and the rest was made while looking at the code.
Sebastian
I have applied the series, thanks!
--
Hamza
On 9/21/23 08:15, Sebastian Andrzej Siewior wrote:
Hi,
I stumbled uppon the amdgpu driver via a bugzilla report. The actual fix
is #4 + #5 and the rest was made while looking at the code.
Sebastian
Hi Sebastian,
Thanks a lot for this patchset. We tested it on multiple devices, and
ever
For pptable structs that use flexible array sizes, use flexible arrays.
Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/2036742
Signed-off-by: Mario Limonciello
---
>From this bug report there are more to fix
.../gpu/drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h| 12 ++--
1 fi
For pptable structs that use flexible array sizes, use flexible arrays.
Suggested-by: Felix Held
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2894
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/radeon/pptable.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/d
For pptable structs that use flexible array sizes, use flexible arrays.
Suggested-by: Felix Held
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2874
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/include/pptable.h | 4 ++--
drivers/gpu/drm/amd/pm/powerplay/hwmgr
On 2023-10-03 19:31, Xiaogang.Chen wrote:
From: Xiaogang Chen
This patch implements partial migration in gpu page fault according to migration
granularity(default 2MB) and not split svm range in cpu page fault handling.
A svm range may include pages from both system ram and vram of one gpu no
[AMD Official Use Only - General]
Reviewed-by: Harish Kasiviswanathan
-Original Message-
From: amd-gfx On Behalf Of Jay Cornwall
Sent: Wednesday, October 4, 2023 12:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: Cornwall, Jay ; Tudor, Alexandru
Subject: [PATCH] drm/amdgpu: Improve MES re
[AMD Official Use Only - General]
On 2023-10-03 17:37, Felix Kuehling wrote:
On 2023-10-03 16:50, Philip Yang wrote:
If there is no VRAM domain, bo_node is NULL and this causes crash.
Refactor the change, and use the module parameter as higher privilege.
Need another patch to support override P
On 2023-10-03 19:29, Kees Cook wrote:
> Prepare for the coming implementation by GCC and Clang of the __counted_by
> attribute. Flexible array members annotated with __counted_by can have
> their accesses bounds-checked at run-time via CONFIG_UBSAN_BOUNDS (for
> array indexing) and CONFIG_FORTIFY_S
As dc_set_power_state() no longer allocates memory, it's not necessary
to have return types and check return code as it can't fail anymore.
Change it back to `void`.
Signed-off-by: Mario Limonciello
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 +
drivers/gpu/drm/amd/
Linux PM core has a prepare() callback run before suspend.
If the system is under high memory pressure, the resources may need
to be evicted into swap instead. If the storage backing for swap
is offlined during the suspend() step then such a call may fail.
So duplicate this step into prepare() t
If there is memory pressure at suspend time then dynamically
allocating a large structure as part of DC suspend code will
fail.
Instead re-use the same structure and clear all members except
those that should be maintained.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2362
Signed-off-by:
At suspend time if there is memory pressure then dynamically allocating
memory will cause failures that don't clean up properly when trying
suspend a second time.
Move the bigger memory allocations into Linux PM prepare() callback and
drop allocations that aren't really needed in DC code.
v1:
ht
On 10/4/2023 10:29 PM, Felix Kuehling wrote:
On 2023-10-04 12:16, Arvind Yadav wrote:
This patch is to align the absolute doorbell offset
based on the doorbell's size. So that doorbell offset
will be aligned for both 32 bit and 64 bit.
v2:
- Addressed the review comment from Felix.
v3:
- Add
On 2023-10-04 12:16, Arvind Yadav wrote:
This patch is to align the absolute doorbell offset
based on the doorbell's size. So that doorbell offset
will be aligned for both 32 bit and 64 bit.
v2:
- Addressed the review comment from Felix.
v3:
- Adding doorbell_size as parameter to get db absolu
[AMD Official Use Only - General]
> From: Daniel Miess
>
> [Why]
> eDPs fail to light up with seamless boot enabled
>
> [How]
> When seamless boot is enabled don't configure dpms_off
> in disable_vbios_mode_if_required.
>
> Reviewed-by: Charlene Liu
> Cc: Mario Limonciello
> Cc: Alex Deucher
>
This patch is to align the absolute doorbell offset
based on the doorbell's size. So that doorbell offset
will be aligned for both 32 bit and 64 bit.
v2:
- Addressed the review comment from Felix.
v3:
- Adding doorbell_size as parameter to get db absolute offset.
Cc: Christian Koenig
Cc: Alex De
Here, passing db_size in byte to find the doorbell's
absolute offset for both 32-bit and 64-bit doorbell sizes.
So that doorbell offset will be aligned based on the doorbell
size.
v3:
- Adding db_size as parameter to get db absolute offset.
Cc: Christian Koenig
Cc: Alex Deucher
Signed-off-by: S
On older chips, the absolute doorbell offset within
the doorbell page is based on the queue ID.
KFD is using queue ID and doorbell size to get an
absolute doorbell offset in userspace.
Here, adding db_size in byte to find the doorbell's
absolute offset for both 32-bit and 64-bit doorbell sizes.
So
When MES is oversubscribed it may not frequently check for new
command submissions from driver if the scheduling load is high.
Response latency as high as 5 seconds has been observed.
Enable a flag which adds a check for new commands between
scheduling quantums.
Signed-off-by: Jay Cornwall
Cc: A
From: Kun Liu
When ROCm is active enable additional SMU 13.0.0 optimizations.
This reuses the unused powersave profile on PMFW.
v2: move to the swsmu code since we need both bits active in
the workload mask.
Signed-off-by: Alex Deucher
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c|
On Wed, Oct 4, 2023 at 10:51 AM Alex Deucher wrote:
>
> On Wed, Oct 4, 2023 at 10:46 AM Wang, Yang(Kevin)
> wrote:
> >
> > Hi Alex,
> >
> > why need to switch profile twice for smu 13.0.0 ? in idle state : set
> > compute profile then set power save profile?
> > Afaik, Pmfw always uses the last
Am 03.10.23 um 21:07 schrieb Alex Deucher:
When ROCm is active enable additional SMU 13.0.0 optimizations.
This reuses the unused powersave profile on PMFW.
Signed-off-by: Alex Deucher
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 8
1 file changed,
On Wed, Oct 4, 2023 at 10:46 AM Wang, Yang(Kevin)
wrote:
>
> Hi Alex,
>
> why need to switch profile twice for smu 13.0.0 ? in idle state : set compute
> profile then set power save profile?
> Afaik, Pmfw always uses the last set result to represent the current profile.
> But it shouldn't affect
Hi Alex,
why need to switch profile twice for smu 13.0.0 ? in idle state : set compute
profile then set power save profile?
Afaik, Pmfw always uses the last set result to represent the current profile.
But it shouldn't affect the results. Anyway.
Reviewed-by: Yang Wang
Best Regards,
Kevin
---
Ping?
On Tue, Oct 3, 2023 at 6:47 PM Alex Deucher wrote:
>
> When ROCm is active enable additional SMU 13.0.0 optimizations.
> This reuses the unused powersave profile on PMFW.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 8
> 1 file changed, 8 i
Hi Christian,
Thank you for explaining, I understand it now.
Regards,
Sathish
On 10/4/2023 7:23 PM, Christian König wrote:
Hi Sathish,
an ack from a maintainer basically means "go ahead, push it to a
branch" (in this case to amd-staging-drm-next).
A reviewed-by means "I've verified the te
Hi Sathish,
an ack from a maintainer basically means "go ahead, push it to a branch"
(in this case to amd-staging-drm-next).
A reviewed-by means "I've verified the technical background and think
that this is correct".
A RB is indeed better, but not always necessary.
Regards,
Christian.
Am
Add support to read Manufacturer Name and FRU File Id fields. Also add
sysfs device attributes for external usage.
Signed-off-by: Lijo Lazar
---
.../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c| 52 +--
.../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h| 2 +
2 files changed, 51 inser
Keep FRU related information together in a separate structure.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 3 ++
.../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c| 46 +++
.../gpu/drm/amd/amd
Add documentation for the newly added manufacturer and fru_id attributes
in sysfs.
Signed-off-by: Lijo Lazar
---
Documentation/gpu/amdgpu/driver-misc.rst | 12
.../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c| 19 +++
2 files changed, 31 insertions(+)
diff --git
From: Yang Wang
v1:
enable GFX v9.4.3 FRU device to query board information.
v2:
use MP1 version to identify different asic
Signed-off-by: Yang Wang
Reviewed-by: Lijo Lazar
Acked-by: Alex Deucher
---
.../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c| 48 +++
1 file changed, 29
On Sat, 30 Sep 2023, Shyam Sundar S K wrote:
> AMD PMF driver loads the PMF TA (Trusted Application) into the AMD
> ASP's (AMD Security Processor) TEE (Trusted Execution Environment).
>
> PMF Trusted Application is a secured firmware placed under
> /lib/firmware/amdtee gets loaded only when the T
On Sat, 30 Sep 2023, Shyam Sundar S K wrote:
> AMD PMF driver loads the PMF TA (Trusted Application) into the AMD
> ASP's (AMD Security Processor) TEE (Trusted Execution Environment).
>
> PMF Trusted Application is a secured firmware placed under
> /lib/firmware/amdtee gets loaded only when the T
On Sat, 30 Sep 2023, Shyam Sundar S K wrote:
> Sometimes policy binary retrieved from the BIOS maybe incorrect that can
> end up in failing to enable the Smart PC solution feature.
>
> Use print_hex_dump_debug() to dump the policy binary in hex, so that we
> debug the issues related to the binary
On Sat, 30 Sep 2023, Shyam Sundar S K wrote:
> PMF driver sends constant inputs to TA which its gets via the other
> subsystems in the kernel. To debug certain TA issues knowing what inputs
> being sent to TA becomes critical. Add debug facility to the driver which
> can isolate Smart PC and TA re
On Sat, 30 Sep 2023, Shyam Sundar S K wrote:
> PMF driver based on the output actions from the TA can request to update
> the system states like entering s0i3, lock screen etc. by generating
> an uevent. Based on the udev rules set in the userspace the event id
> matching the uevent shall get upda
On 2023-10-03 15:53:41 [-0400], Harry Wentland wrote:
> On 2023-09-21 10:15, Sebastian Andrzej Siewior wrote:
> > This is a revert of the commit mentioned below while it is not wrong, as
> > in the kernel will explode, having migrate_disable() here it is
> > complete waste of resources.
> >
> > Ad
On Sat, 30 Sep 2023, Shyam Sundar S K wrote:
> PMF Policy binary is a encrypted and signed binary that will be part
> of the BIOS. PMF driver via the ACPI interface checks the existence
> of Smart PC bit. If the advertised bit is found, PMF driver walks
> the acpi namespace to find out the policy
On 2023-10-03 15:54:58 [-0400], Harry Wentland wrote:
> On 2023-10-02 06:58, Sebastian Andrzej Siewior wrote:
> > On 2023-09-22 07:33:26 [+0200], Christian König wrote:
> >> Am 21.09.23 um 16:15 schrieb Sebastian Andrzej Siewior:
> >>> Hi,
> >>>
> >>> I stumbled uppon the amdgpu driver via a bugzil
On Sat, 30 Sep 2023, Shyam Sundar S K wrote:
> In the current code, the metrics table information was required only
> for auto-mode or CnQF at a given time. Hence keeping the return type
> of amd_pmf_set_dram_addr() as static made sense.
>
> But with the addition of Smart PC builder feature, the
On Sat, 30 Sep 2023, Shyam Sundar S K wrote:
> In order to provide GPU inputs to TA for the Smart PC solution to work, we
> need to have interface between the PMF driver and the AMDGPU driver.
>
> Add the initial code path for get interface from AMDGPU.
>
> Co-developed-by: Mario Limonciello
>
On Sat, 30 Sep 2023, Shyam Sundar S K wrote:
> PMF driver sends changing inputs from each subystem to TA for evaluating
> the conditions in the policy binary.
>
> Add initial support of plumbing in the PMF driver for Smart PC to get
> information from other subsystems in the kernel.
>
> Signed-o
On Sat, 30 Sep 2023, Shyam Sundar S K wrote:
> PMF TA (Trusted Application) loads via the TEE environment into the
> AMD ASP.
>
> PMF-TA supports two commands:
> 1) Init: Initialize the TA with the PMF Smart PC policy binary and
> start the policy engine. A policy is a combination of inputs and
>
On Sat, 30 Sep 2023, Shyam Sundar S K wrote:
> PMF TA (Trusted Application) loads via the TEE environment into the
> AMD ASP.
>
> PMF-TA supports two commands:
> 1) Init: Initialize the TA with the PMF Smart PC policy binary and
> start the policy engine. A policy is a combination of inputs and
>
On Fri, Sep 29, 2023 at 1:50 PM Shashank Sharma wrote:
>
>
> On 20/09/2023 17:21, Alex Deucher wrote:
> > On Fri, Sep 8, 2023 at 12:45 PM Shashank Sharma
> > wrote:
> >> The FW expects us to allocate at least one page as context
> >> space to process gang, process, GDS and FW related work.
> >>
On 2023-10-03 15:54, Harry Wentland wrote:
> On 2023-10-02 06:58, Sebastian Andrzej Siewior wrote:
>> On 2023-09-22 07:33:26 [+0200], Christian König wrote:
>>> Am 21.09.23 um 16:15 schrieb Sebastian Andrzej Siewior:
Hi,
I stumbled uppon the amdgpu driver via a bugzilla report. Th
On 10/3/23 15:53, Harry Wentland wrote:
On 2023-09-21 10:15, Sebastian Andrzej Siewior wrote:
This is a revert of the commit mentioned below while it is not wrong, as
in the kernel will explode, having migrate_disable() here it is
complete waste of resources.
Additionally commit message is plai
From: Aric Cyr
This version brings along following fixes:
- Refactor DPG test pattern logic for ODM cases
- Refactor HWSS into component folder
- Revert "drm/amd/display: Add a check for idle power optimization"
- Revert "drm/amd/display: remove duplicated edp relink to fastboot
- Update cursor l
From: George Shen
[Why]
Enabling DPG causes HUBP to stay in blank constantly. If DPG is enabled
while an MCLK switch is taking place with SubVP, it will cause the MCLK
to never complete. This is because SubVP MCLK switch relies a HUBP
VLine interrupt, which will never occur when HUBP is constantl
From: George Shen
[Why]
Current DPG test pattern logic does not account for ODM configuration
changes after test pattern has already been programmed. For example, if
ODM2:1 is enabled after test pattern is already being output, the second
pipe is not programmed to output test pattern, causing hal
From: Daniel Miess
[Why]
eDPs fail to light up with seamless boot enabled
[How]
When seamless boot is enabled don't configure dpms_off
in disable_vbios_mode_if_required.
Reviewed-by: Charlene Liu
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Tom Chung
Signed-of
From: Mounika Adhuri
[why]
Rename hw_sequencer to hwseq.
Move all hwseq files to unique
folder hwss.
[how]
creating hwss repo in dc, and moved the dcnxx_hwseq.c
and .h files into corresponding new folders inside the hwss
and cleared the linkage errors by adding relative paths
in the Makefile.tem
From: Alvin Lee
[Why]
Latest FPO sequence is causing intermittent hangs
[How]
Update the FPO sequence
Reviewed-by: Saaem Rizvi
Acked-by: Tom Chung
Signed-off-by: Alvin Lee
---
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 21 ---
.../drm/amd/display/dc/dcn32/dcn32_hwseq.c
From: Sung Joon Kim
Revert commit 0ca0151b9902 ("drm/amd/display: Add a check for idle power
optimization")
Because it cause Freesync and S4 regression
Reviewed-by: Aric Cyr
Acked-by: Tom Chung
Signed-off-by: Sung Joon Kim
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 20 +
From: Nicholas Kazlauskas
[Why]
These functions can be called from high IRQ levels and the OS will hang
if it tries to use a usleep_highres or a msleep.
[How]
Replace the fsleep with a udelay.
Reviewed-by: Aric Cyr
Acked-by: Tom Chung
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/a
From: Alvin Lee
[Why&How]
For determining the cursor size limit, use the same checks that
are used for determining SW cursor fallback instead of only
using SubVP
Reviewed-by: Aric Cyr
Acked-by: Tom Chung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 ++--
..
From: Muhammad Ahmed
[why]
Need to use real clock table
[How]
Update the clock table
Reviewed-by: Charlene Liu
Acked-by: Tom Chung
Signed-off-by: Muhammad Ahmed
---
.../drm/amd/display/dc/dcn35/dcn35_resource.c | 3 ++-
.../drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 24 +--
From: Duncan Ma
[Why]
Whenever stream changes because of new
pipe arrangements such as ODM. The new
stream mask is not reflected in DMCUB.
The mismatch in stream mask is blocking ips
entry in some scenarios.
[How]
Whenever stream arrangement changes,
update stream mask and notify DMCUB.
Review
From: Aric Cyr
Revert commit a0b8a2c85d1b ("drm/amd/display: remove duplicated edp relink to
fastboot")
Because it cause 4k EDP not light up on boot
Reviewed-by: Tom Chung
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Tom Chung
Signed-off-by: Aric Cyr
---
dr
From: Max Tseng
Fine tune the Vmin clock value
Reviewed-by: Robin Chen
Acked-by: Tom Chung
Signed-off-by: Max Tseng
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c | 8 +++-
2 files changed, 8 insertions(+), 2 de
From: Charlene Liu
[why]
pmfw header file updated, need align with data structure.
[How]
Update the data structure.
Reviewed-by: Sung joon Kim
Acked-by: Tom Chung
Signed-off-by: Charlene Liu
---
.../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 214 --
.../amd/display/dc/clk_m
From: Muhammad Ansari
[WHY]
FreeSync spec requires PB8 and PB12 to be set to nominal
refresh rate regardless of fixed rate or variable
[HOW]
Removed the condition that checks and overwrites max refresh rate
and set PB8/PB12 to be set to max refresh rate always
Reviewed-by: Anthony Koo
Acked-by
From: Sung Joon Kim
[why]
It's important to make sure SMU messages
are logged by default to improve debugging for
power optimization use cases.
[how]
Change logs to warnings when SMU message
returns non-success id.
Reviewed-by: Charlene Liu
Acked-by: Tom Chung
Signed-off-by: Sung Joon Kim
--
This DC patchset brings improvements in multiple areas. In summary, we have:
- Refactor DPG test pattern logic for ODM cases
- Refactor HWSS into component folder
- Revert "drm/amd/display: Add a check for idle power optimization"
- Revert "drm/amd/display: remove duplicated edp relink to fastboot
Am 02.10.23 um 22:21 schrieb Rajneesh Bhardwaj:
To allow bigger allocations specially on systems such as GFXIP 9.4.3
that use GTT memory for VRAM allocations, relax the limits to
maximize ROCm allocations.
Reviewed-by: Felix Kuehling
Signed-off-by: Rajneesh Bhardwaj
Acked-by: Christian König
Add documentation for board info sysfs attribute.
Signed-off-by: Lijo Lazar
Reviewed-by: Alex Deucher
---
Documentation/gpu/amdgpu/driver-misc.rst | 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16
2 files changed, 22 insertions(+)
diff --git a/Documentation/gpu/a
Add a sysfs attribute which shows the board form factor like OAM or
CEM.
Signed-off-by: Lijo Lazar
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 57 ++
1 file changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/d
Add support to query package types supported in smuio v13.0 ASICs.
Signed-off-by: Lijo Lazar
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c
b/drivers/gpu
Expand support to get other board types like OAM or CEM.
Signed-off-by: Lijo Lazar
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/smuio_v13_0_3.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v13_0_3.c
b/drivers/gpu/drm/amd/amdgpu/smuio_v1
Move definition of package type to amdgpu_smuio header and add new
package types for CEM and OAM.
Signed-off-by: Lijo Lazar
---
v2: Move definition to amdgpu_smuio.h instead of amdgpu.h (Christian/Hawking)
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_
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