From: Qingqing Zhuo <qingqing.z...@amd.com>
Enable DML2 for DCN35.
Changes since V1:
- Remove hard coded values
Acked-by: Harry Wentland <harry.wentl...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Roman Li <roman...@amd.com>
Signed-off-by: Qingqing Zhuo <qingqing.z...@amd.com>
---
.../drm/amd/display/dc/dcn35/dcn35_resource.c | 13 +--
.../dc/dml2/display_mode_core_structs.h | 2 +
.../gpu/drm/amd/display/dc/dml2/dml2_policy.c | 7 ++
.../display/dc/dml2/dml2_translation_helper.c | 89 ++++++++++++++++++-
.../drm/amd/display/dc/dml2/dml2_wrapper.c | 6 ++
5 files changed, 110 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
index 693c7ba4b34d..2fa876d9e1f7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
@@ -31,7 +31,7 @@
#include "resource.h"
#include "include/irq_service_interface.h"
#include "dcn35_resource.h"
-/*#include "dml2/dml2_wrapper.h"*/
+#include "dml2/dml2_wrapper.h"
#include "dcn20/dcn20_resource.h"
#include "dcn30/dcn30_resource.h"
@@ -729,7 +729,7 @@ static const struct dc_debug_options debug_defaults_drv = {
},
.seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
.enable_z9_disable_interface = true, /* Allow support for the PMFW
interface for disable Z9*/
- /* .using_dml2 = true, */
+ .using_dml2 = true,
.support_eDP1_5 = true,
.enable_hpo_pg_support = false,
.enable_legacy_fast_update = true,
@@ -1694,7 +1694,7 @@ static bool dcn35_validate_bandwidth(struct dc *dc,
{
bool out = false;
- /*out = dml2_validate(dc, context, fast_validate);*/
+ out = dml2_validate(dc, context, fast_validate);
return out;
}
@@ -2067,18 +2067,19 @@ static bool dcn35_resource_construct(
dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
-#if 0
+
dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
dc->dml2_options.use_native_pstate_optimization = false;
dc->dml2_options.use_native_soc_bb_construction = true;
+ if (dc->config.EnableMinDispClkODM)
+ dc->dml2_options.minimize_dispclk_using_odm = true;
dc->dml2_options.callbacks.dc = dc;
dc->dml2_options.callbacks.build_scaling_params =
&resource_build_scaling_params;
dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch
= &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
- dc->dml2_options.callbacks.acquire_secondary_pipe_for_mpc_odm =
&dc_resource_acquire_secondary_pipe_for_mpc_odm;
+ dc->dml2_options.callbacks.acquire_secondary_pipe_for_mpc_odm =
&dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy;
dc->dml2_options.max_segments_per_hubp = 18;
dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
-#endif
if (dc->config.sdpif_request_limit_words_per_umc == 0)
dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h
b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h
index d2e1510a504f..c2fa28ff57ab 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h
@@ -32,6 +32,8 @@ enum dml_project_id {
dml_project_default = 1,
dml_project_dcn32 = dml_project_default,
dml_project_dcn321 = 2,
+ dml_project_dcn35 = 3,
+ dml_project_dcn351 = 4,
};
enum dml_prefetch_modes {
dml_prefetch_support_uclk_fclk_and_stutter_if_possible = 0,
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c
index 0c71a8aa5587..f8e9aa32ceab 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c
@@ -298,4 +298,11 @@ void build_unoptimized_policy_settings(enum dml_project_id
project, struct dml_m
policy->SynchronizeDRRDisplaysForUCLKPStateChangeFinal = true;
policy->AssumeModeSupportAtMaxPwrStateEvenDRAMClockChangeNotSupported =
true; // TOREVIEW: What does this mean?
policy->AssumeModeSupportAtMaxPwrStateEvenFClockChangeNotSupported =
true; // TOREVIEW: What does this mean?
+ if (project == dml_project_dcn35 ||
+ project == dml_project_dcn351) {
+ policy->DCCProgrammingAssumesScanDirectionUnknownFinal = false;
+ policy->EnhancedPrefetchScheduleAccelerationFinal = 0;
+ policy->AllowForPStateChangeOrStutterInVBlankFinal =
dml_prefetch_support_uclk_fclk_and_stutter_if_possible; /*new*/
+ policy->UseOnlyMaxPrefetchModes = 1;
+ }
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index 353f22a6b7f8..de58c7b867e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -103,6 +103,76 @@ void dml2_init_ip_params(struct dml2_context *dml2, const
struct dc *in_dc, stru
out->max_num_dp2p0_streams = 4;
break;
+ case dml_project_dcn35:
+ case dml_project_dcn351:
+ out->rob_buffer_size_kbytes = 64;
+ out->config_return_buffer_size_in_kbytes = 1792;
+ out->compressed_buffer_segment_size_in_kbytes = 64;
+ out->meta_fifo_size_in_kentries = 32;
+ out->zero_size_buffer_entries = 512;
+ out->pixel_chunk_size_kbytes = 8;
+ out->alpha_pixel_chunk_size_kbytes = 4;
+ out->min_pixel_chunk_size_bytes = 1024;
+ out->meta_chunk_size_kbytes = 2;
+ out->min_meta_chunk_size_bytes = 256;
+ out->writeback_chunk_size_kbytes = 8;
+ out->dpte_buffer_size_in_pte_reqs_luma = 68;
+ out->dpte_buffer_size_in_pte_reqs_chroma = 36;
+ out->dcc_meta_buffer_size_bytes = 6272;
+ out->gpuvm_enable = 1;
+ out->hostvm_enable = 1;
+ out->gpuvm_max_page_table_levels = 1;
+ out->hostvm_max_page_table_levels = 2;
+ out->num_dsc = 4;
+ out->maximum_dsc_bits_per_component = 12;
+ out->maximum_pixels_per_line_per_dsc_unit = 6016;
+ out->dsc422_native_support = 1;
+ out->line_buffer_size_bits = 986880;
+ out->dcc_supported = 1;
+ out->max_line_buffer_lines = 32;
+ out->writeback_interface_buffer_size_kbytes = 90;
+ out->max_num_dpp = 4;
+ out->max_num_otg = 4;
+ out->max_num_hdmi_frl_outputs = 1;
+ out->max_num_dp2p0_outputs = 2;
+ out->max_num_dp2p0_streams = 4;
+ out->max_num_wb = 1;
+
+ out->max_dchub_pscl_bw_pix_per_clk = 4;
+ out->max_pscl_lb_bw_pix_per_clk = 2;
+ out->max_lb_vscl_bw_pix_per_clk = 4;
+ out->max_vscl_hscl_bw_pix_per_clk = 4;
+ out->max_hscl_ratio = 6;
+ out->max_vscl_ratio = 6;
+ out->max_hscl_taps = 8;
+ out->max_vscl_taps = 8;
+ out->dispclk_ramp_margin_percent = 1.11;
+
+ out->dppclk_delay_subtotal = 47;
+ out->dppclk_delay_scl = 50;
+ out->dppclk_delay_scl_lb_only = 16;
+ out->dppclk_delay_cnvc_formatter = 28;
+ out->dppclk_delay_cnvc_cursor = 6;
+ out->dispclk_delay_subtotal = 125;
+
+ out->dynamic_metadata_vm_enabled = false;
+ out->max_inter_dcn_tile_repeaters = 8;
+ out->cursor_buffer_size = 16; // kBytes
+ out->cursor_chunk_size = 2; // kBytes
+
+ out->writeback_line_buffer_buffer_size = 0;
+ out->writeback_max_hscl_ratio = 1;
+ out->writeback_max_vscl_ratio = 1;
+ out->writeback_min_hscl_ratio = 1;
+ out->writeback_min_vscl_ratio = 1;
+ out->writeback_max_hscl_taps = 1;
+ out->writeback_max_vscl_taps = 1;
+ out->ptoi_supported = 0;
+
+ out->vblank_nom_default_us = 668; /*not in dml, but in
programming guide, hard coded in dml2_translate_ip_params*/
+ out->config_return_buffer_segment_size_in_kbytes = 64;
/*required, but not exist,, hard coded in dml2_translate_ip_params*/
+ break;
+
}
}
@@ -155,6 +225,17 @@ void dml2_init_socbb_params(struct dml2_context *dml2,
const struct dc *in_dc, s
out->smn_latency_us = 0;
break;
+ case dml_project_dcn35:
+ out->num_chans = 4;
+ out->round_trip_ping_latency_dcfclk_cycles = 106;
+ out->smn_latency_us = 2;
+ break;
+
+ case dml_project_dcn351:
+ out->num_chans = 16;
+ out->round_trip_ping_latency_dcfclk_cycles = 1100;
+ out->smn_latency_us = 2;
+ break;
}
/* ---Overrides if available--- */
if (dml2->config.bbox_overrides.dram_num_chan)
@@ -255,7 +336,6 @@ void dml2_init_soc_states(struct dml2_context *dml2, const
struct dc *in_dc,
p->in_states->state_array[1].dcfclk_mhz = 1434.0;
p->in_states->state_array[1].dram_speed_mts = 1000 *
transactions_per_mem_clock;
break;
-
}
/* Override from passed values, mainly for debugging purposes, if
available */
@@ -287,6 +367,13 @@ void dml2_init_soc_states(struct dml2_context *dml2, const
struct dc *in_dc,
p->dcfclk_stas_mhz[2] = 906;
p->dcfclk_stas_mhz[3] = 1324;
p->dcfclk_stas_mhz[4] = p->in_states->state_array[1].dcfclk_mhz;
+ } else if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&
+ dml2->v20.dml_core_ctx.project != dml_project_dcn351) {
+ p->dcfclk_stas_mhz[0] = 300;
+ p->dcfclk_stas_mhz[1] = 615;
+ p->dcfclk_stas_mhz[2] = 906;
+ p->dcfclk_stas_mhz[3] = 1324;
+ p->dcfclk_stas_mhz[4] = 1500;
}
/* Copy clocks tables entries, if available */
if (dml2->config.bbox_overrides.clks_table.num_states) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
index aed3e4200254..e4f2f3eb9b32 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
@@ -694,6 +694,12 @@ bool dml2_create(const struct dc *in_dc, const struct
dml2_configuration_options
(*dml2)->config = *config;
switch (in_dc->ctx->dce_version) {
+ case DCN_VERSION_3_5:
+ (*dml2)->v20.dml_core_ctx.project = dml_project_dcn35;
+ break;
+ case DCN_VERSION_3_51:
+ (*dml2)->v20.dml_core_ctx.project = dml_project_dcn351;
+ break;
case DCN_VERSION_3_2:
(*dml2)->v20.dml_core_ctx.project = dml_project_dcn32;
break;
--
2.40.1
