From: Charlene Liu <charlene....@amd.com>
dc->dml2_options.use_native_pstate_optimization flag will make driver
use dcn32 legacy_svp_drr related tuning. Set this to false fixed the
stutter underflow issue also based on HW suggest disable ODM by default
and let DML choose it.
Reviewed-by: Zhan Liu <zhan....@amd.com>
Acked-by: Qingqing Zhuo <qingqing.z...@amd.com>
Signed-off-by: Qingqing Zhuo <qingqing.z...@amd.com>
Signed-off-by: Charlene Liu <charlene....@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c | 7 +++----
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c | 8 ++++++--
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
index e2f3ddb3f225..2283daa45318 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
@@ -733,8 +733,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.support_eDP1_5 = true,
.enable_hpo_pg_support = false,
.enable_legacy_fast_update = true,
- .disable_stutter = true,
- .enable_single_display_2to1_odm_policy = true,
+ .enable_single_display_2to1_odm_policy = false,
.disable_idle_power_optimizations = true,
.dmcub_emulation = false,
.disable_boot_optimizations = false,
@@ -1835,6 +1834,7 @@ static bool dcn35_resource_construct(
/* Use pipe context based otg sync logic */
dc->config.use_pipe_ctx_sync_logic = true;
+ dc->config.use_default_clock_table = true;
/* read VBIOS LTTPR caps */
{
if (ctx->dc_bios->funcs->get_lttpr_caps) {
@@ -2065,11 +2065,10 @@ static bool dcn35_resource_construct(
dc->cap_funcs = cap_funcs;
-
dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
- dc->dml2_options.use_native_pstate_optimization = false;
+ dc->dml2_options.use_native_pstate_optimization = true;
dc->dml2_options.use_native_soc_bb_construction = true;
if (dc->config.EnableMinDispClkODM)
dc->dml2_options.minimize_dispclk_using_odm = true;
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
index 552d5cffce2d..11c131f6cf26 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
@@ -67,8 +67,12 @@ static void map_hw_resources(struct dml2_context *dml2,
in_out_display_cfg->hw.DPPPerSurface[i] =
mode_support_info->DPPPerSurface[i];
in_out_display_cfg->hw.DSCEnabled[i] =
mode_support_info->DSCEnabled[i];
in_out_display_cfg->hw.NumberOfDSCSlices[i] =
mode_support_info->NumberOfDSCSlices[i];
- in_out_display_cfg->hw.DLGRefClkFreqMHz = 50;
-
+ in_out_display_cfg->hw.DLGRefClkFreqMHz = 24;
+ if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&
+ dml2->v20.dml_core_ctx.project != dml_project_dcn351) {
+ /*dGPU default as 50Mhz*/
+ in_out_display_cfg->hw.DLGRefClkFreqMHz = 50;
+ }
for (j = 0; j < mode_support_info->DPPPerSurface[i]; j++) {
dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[num_pipes] =
dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i];
dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[num_pipes]
= true;
--
2.40.1
