From: jiadozhu
This is a standalone test case used for software mcbp on gfx9.
Build and open two consoles to run:
build/bin/vkpreemption s gfx=draws:100,priority:high,delay:0
build/bin/vkpreemption c gfx=draws:100,priority:low,delay:0
The result is printed on the console of the server si
From: Aric Cyr
Acked-by: Stylon Wang
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 3cb8cf065204..85ebeaa2de18 100644
--- a/driv
From: Dillon Varone
[Description]
When compressed buffer allocation changes, optimized required flag should be
set to trigger an update in optimize bandwidth.
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 7 +
From: Nicholas Kazlauskas
[Why]
It's currently tied to Z10 support, and is required for Z10, but
we can still support Z10 display off without PSR.
We currently need to skip the PSR CRTC disable to prevent stuttering
and underflow from occuring during PSR-SU.
[How]
Add a debug option to allow sp
From: Zhongwei
[Why]
The input UrgentLatency in CalculateUrgentBurstFactor
of prefect check is wrong.
[How]
Correct to the correct one to keep same as HW formula
Reviewed-by: Charlene Liu
Acked-by: Stylon Wang
Signed-off-by: Zhongwei
---
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode
From: Charlene Liu
[why]
HW register bit define changed.
Reviewed-by: Zhan Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Stylon Wang
Signed-off-by: Charlene Liu
---
.../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 40 +++
.../drm/amd/display/dc/dcn31/dcn31_hwseq.h| 4 ++
From: Alvin Lee
[Description]
- Ensure dc_commit_streams returns the correct return code so any
failures can be handled properly in DM layer
- If set timings fail and we have to remove MPO planes, do so
unconditionally but make sure to mark for removal so we report
the VSYNC and prevent tim
From: Paul Hsieh
[Why]
There is no DDC_6 pin on new asic cause the mapping table is
incorrect. When app try to access DDC_VGA port, driver read
an invalid ddc pin status and report engine busy.
[How]
Add dummy DDC_6 pin to align gpio structure.
Reviewed-by: Alvin Lee
Acked-by: Stylon Wang
Sig
From: Dillon Varone
[Description]
If validating for max voltage level (therefore max clocks) always pass over
the DET swath fill latency hiding check.
Reviewed-by: Alvin Lee
Acked-by: Stylon Wang
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
From: Dillon Varone
[Description]
When subvp is in use, main pipes should block unintended natural uclk pstate
changes to prevent disruption to the state machine.
Reviewed-by: Alvin Lee
Acked-by: Stylon Wang
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
From: Michael Strauss
[WHY]
Low dscclk in high vlevels blocks some DSC modes.
[HOW]
Update dscclk to 1/3 of dispclk.
Reviewed-by: Charlene Liu
Acked-by: Stylon Wang
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 6 +++---
1 file changed, 3 insertio
From: David Galiffi
[Why]
It is not enabled for DCN3.0.1, 3.0.2, 3.0.3.
[How]
Add `dc->caps.dp_hdmi21_pcon_support = true` to these DCN versions.
Reviewed-by: Martin Leung
Acked-by: Stylon Wang
Signed-off-by: David Galiffi
---
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 2 ++
From: Dmytro Laktyushkin
Seamless boot requires VBIOS to select dig matching to link order wise. A
significant
amount of dal logic makes assumption we are using preferred dig for eDP and if
this
isn't the case then seamless boot is not supported.
Reviewed-by: Martin Leung
Acked-by: Stylon Wan
From: Aurabindo Pillai
[Why&How]
If the timing generator isnt running, it does not make sense to trigger
a sync on the corresponding OTG. Check this condition before starting.
Otherwise, this will cause error like:
*ERROR* GSL: Timeout on reset trigger!
Fixes: 8c7924bdb0fe ("drm/amd/display: Di
From: Chris Park
[Why]
DTB DTO is programmed more correctly during
link enable. Programming them on CLK update
which may arrive frequently and sporadically
per flip throws off DTB DTO.
[How]
Remove DTB DTO programming on clock update.
Reviewed-by: Alvin Lee
Acked-by: Jasdeep Dhillon
Signed-o
This DC patchset brings improvements in multiple areas. In summary, we have:
* Improvements on PSR-SU
* Improvements and fixes on DML calculation
* Fix on Dynamic Refresh Rate for DCN 3.1.4
* Fix on DC commit streams
* Fix on DDC GPIO pin
* Fix on Sub-ViewPort
* Fix on DSC
* Enable DP HDMI 2.1 PCO
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 13ee7ef407cfcf63f4f047460ac5bb6ba5a3447d Add linux-next specific
files for 20221129
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202211041320.coq8eelj-...@intel.com
https
[AMD Official Use Only - General]
For the series, Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Zhang, Hawking
Sent: Wednesday, November 30, 2022 09:28
To: 'Jack Xiao' ; amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack
Subject: RE: [PATCH 2/2] drm/amdgpu/mes11: enabl
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Jack Xiao
Sent: Wednesday, November 30, 2022 08:44
To: amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack
Subject: [PATCH 2/2] drm/amdgpu/mes11: enable reg active poll
On 2022-10-31 12:23, Jonathan Kim wrote:
Allow the debugger to query additional info based on an exception code.
For device exceptions, it's currently only memory violation information.
For process exceptions, it's currently only runtime information.
Queue exception only report the queue exceptio
On 2022-10-31 12:23, Jonathan Kim wrote:
Allow the debugger to a single query queue, device and process exception
in a FIFO manner.
The implementation is not really FIFO because the order in which events
are returned is independent of the order in which they were raised. Just
remove the FIF
Update the api def of mes11.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/include/mes_v11_api_def.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/mes_v11_api_def.h
b/drivers/gpu/drm/amd/include/mes_v11_api_def.h
index 7e85cdc5bd34..dc69
Enable reg active poll in mes11.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 02ad84a1526a..a3e7062b7f77 100644
--- a/drivers/gpu/drm/
On 2022-10-31 12:23, Jonathan Kim wrote:
Allow the debugger to set single memory and single ALU operations.
Some exceptions are imprecise (memory violations, address watch) in the
sense that a trap occurs only when the exception interrupt occurs and
not at the non-halting faulty instruction.
On 2022-10-31 12:23, Jonathan Kim wrote:
Shader read, write and atomic memory operations can be alerted to the
debugger as an address watch exception.
Allow the debugger to pass in a watch point to a particular memory
address per device.
Note that there exists only 4 watch points per devices
ThispatchisReviewed-by:JamesZhu
On 2022-11-29 19:02, Leo Liu wrote:
So that uses PSP to initialize HW.
Fixes: 0c2c02b6 (drm/amdgpu/vcn: add firmware support for dimgrey_cavefish)
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 3 +++
1 file changed, 3 insertions(+)
dif
So that uses PSP to initialize HW.
Fixes: 0c2c02b6 (drm/amdgpu/vcn: add firmware support for dimgrey_cavefish)
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd
On 2022-10-31 12:23, Jonathan Kim wrote:
In order to inspect waves from the saved context at any point during a
debug session, the debugger must be able to preempt queues to trigger
context save by suspending them.
On queue suspend, the KFD will copy the context save header information
so that
On 2022-10-31 12:23, Jonathan Kim wrote:
This operation allows the debugger to override the enabled HW
exceptions on the device.
On debug devices that only support the debugging of a single process,
the HW exceptions are global and set through the SPI_GDBG_TRAP_MASK
register.
Because they are gl
On 2022-11-25 05:21, Christian König wrote:
Instead of a single worker going over the list of delete BOs in regular
intervals use a per BO worker which blocks for the resv object and
locking of the BO.
This not only simplifies the handling massively, but also results in
much better response time
This fixes DMCU initialization in APU GPU passthrough. The
DMCU needs the GPU physical address, not the CPU physical
address. This ends up working out on bare metal because
we always use the physical address, but doesn't work in
passthrough because the addresses are different.
Signed-off-by: Ale
On Fri, 25 Nov 2022 at 11:14, Tvrtko Ursulin
wrote:
>
>
> + Matt
>
> On 25/11/2022 10:21, Christian König wrote:
> > TTM is just wrapping core DMA functionality here, remove the mid-layer.
> > No functional change.
> >
> > Signed-off-by: Christian König
> > ---
> > drivers/gpu/drm/i915/gem/i915
Once these patches land, can we revert these changes?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0c85c067c9d9d7a1b2cc2e01a236d5d0d4a872b5
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=192039f12233c9063d040266e7c98188c7c89dec
Alex
On Tue, Nov 29, 2022 at 11:05:28AM -0500, Alex Deucher wrote:
> On Tue, Nov 29, 2022 at 10:59 AM Mikhail Krylov wrote:
> >
> > On Tue, Nov 29, 2022 at 09:44:19AM -0500, Alex Deucher wrote:
> > > On Mon, Nov 28, 2022 at 3:48 PM Mikhail Krylov wrote:
> > > >
> > > > On Mon, Nov 28, 2022 at 09:50:50
On Tue, Nov 29, 2022 at 09:44:19AM -0500, Alex Deucher wrote:
> On Mon, Nov 28, 2022 at 3:48 PM Mikhail Krylov wrote:
> >
> > On Mon, Nov 28, 2022 at 09:50:50AM -0500, Alex Deucher wrote:
> >
> > >>> [excessive quoting removed]
> >
> > >> So, is there any progress on this issue? I do understand it
On Tue, Nov 29, 2022 at 10:59 AM Mikhail Krylov wrote:
>
> On Tue, Nov 29, 2022 at 09:44:19AM -0500, Alex Deucher wrote:
> > On Mon, Nov 28, 2022 at 3:48 PM Mikhail Krylov wrote:
> > >
> > > On Mon, Nov 28, 2022 at 09:50:50AM -0500, Alex Deucher wrote:
> > >
> > > >>> [excessive quoting removed]
Applied. Thanks!
Alex
On Tue, Nov 29, 2022 at 2:49 AM Konstantin Meskhidze
wrote:
>
> This commit fixes logic error in function 'amdgpu_hw_ip_info':
>- value 'uvd' might be 'vcn'.
>
> Signed-off-by: Konstantin Meskhidze
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 ++--
> 1 fil
On Tue, Nov 29, 2022 at 10:15 AM Marek Marczykowski-Górecki
wrote:
>
> On Tue, Nov 29, 2022 at 09:32:54AM -0500, Alex Deucher wrote:
> > On Mon, Nov 28, 2022 at 8:59 PM Demi Marie Obenour
> > wrote:
> > >
> > > On Mon, Nov 28, 2022 at 11:18:00AM -0500, Alex Deucher wrote:
> > > > On Mon, Nov 28,
On Tue, Nov 29, 2022 at 09:32:54AM -0500, Alex Deucher wrote:
> On Mon, Nov 28, 2022 at 8:59 PM Demi Marie Obenour
> wrote:
> >
> > On Mon, Nov 28, 2022 at 11:18:00AM -0500, Alex Deucher wrote:
> > > On Mon, Nov 28, 2022 at 2:18 AM Demi Marie Obenour
> > > wrote:
> > > >
> > > > Dear Christian:
>
On Mon, Nov 28, 2022 at 3:48 PM Mikhail Krylov wrote:
>
> On Mon, Nov 28, 2022 at 09:50:50AM -0500, Alex Deucher wrote:
>
> >>> [excessive quoting removed]
>
> >> So, is there any progress on this issue? I do understand it's not a high
> >> priority one, and today I've checked it on 6.0 kernel, an
On Mon, Nov 28, 2022 at 8:59 PM Demi Marie Obenour
wrote:
>
> On Mon, Nov 28, 2022 at 11:18:00AM -0500, Alex Deucher wrote:
> > On Mon, Nov 28, 2022 at 2:18 AM Demi Marie Obenour
> > wrote:
> > >
> > > Dear Christian:
> > >
> > > What is the status of the AMDGPU work for Xen dom0? That was menti
On Fri, Nov 25, 2022 at 12:52 PM André Almeida wrote:
>
> From: Shashank Sharma
>
> Add a sysfs event to notify userspace about GPU resets providing:
> - PID that triggered the GPU reset, if any. Resets can happen from
> kernel threads as well, in that case no PID is provided
> - Information ab
Am 29.11.22 um 14:14 schrieb Pan, Xinhui:
[AMD Official Use Only - General]
comments line.
发件人: Koenig, Christian
发送时间: 2022年11月29日 20:07
收件人: Pan, Xinhui; amd-gfx@lists.freedesktop.org
抄送: dan...@ffwll.ch; matthew.a...@intel.com; dri-de...@lists.freede
[AMD Official Use Only - General]
comments line.
发件人: Koenig, Christian
发送时间: 2022年11月29日 20:07
收件人: Pan, Xinhui; amd-gfx@lists.freedesktop.org
抄送: dan...@ffwll.ch; matthew.a...@intel.com; dri-de...@lists.freedesktop.org;
linux-ker...@vger.kernel.org; Pa
Currently drm-buddy does not have full knowledge of continuous memory.
Adding a new member leaf_link which links all leaf blocks in asceding
order. Finding continuous memory within this leaf_link is easier.
Say, memory of order 3 can be combined with corresponding memory of
order 3 or 2+2 or 1+2+
Am 29.11.22 um 12:54 schrieb Pan, Xinhui:
[AMD Official Use Only - General]
comments inline.
发件人: Koenig, Christian
发送时间: 2022年11月29日 19:32
收件人: Pan, Xinhui; amd-gfx@lists.freedesktop.org
抄送: dan...@ffwll.ch; matthew.a...@intel.com; dri-de...@lists.free
[AMD Official Use Only - General]
comments inline.
发件人: Koenig, Christian
发送时间: 2022年11月29日 19:32
收件人: Pan, Xinhui; amd-gfx@lists.freedesktop.org
抄送: dan...@ffwll.ch; matthew.a...@intel.com; dri-de...@lists.freedesktop.org;
linux-ker...@vger.kernel.org;
Am 29.11.22 um 08:10 schrieb jiadong@amd.com:
From: "Jiadong.Zhu"
The software ring is created to support priority context while there is only
one hardware queue for gfx.
Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple software
Am 29.11.22 um 11:56 schrieb xinhui pan:
Currently drm-buddy does not have full knowledge of continuous memory.
Lets consider scenario below.
order 1:L R
order 0: LL LR RL RR
for order 1 allocation, it can offer L or R or LR+RL.
For now, we only implement L or R
[AMD Official Use Only - General]
In one ROCM + gdm restart test,
find_continuous_blocks() succeed with ratio 35%.
the cod coverage report is below.
7723998 : if (order-- == min_order) {
773 352 : if (!(flags &
DR
Currently drm-buddy does not have full knowledge of continuous memory.
Lets consider scenario below.
order 1:L R
order 0: LL LR RL RR
for order 1 allocation, it can offer L or R or LR+RL.
For now, we only implement L or R case for continuous memory allocation.
So t
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Zhou1, Tao
Sent: Tuesday, November 29, 2022 15:56
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
Cc: Zhou1, Tao
Subject: [PATCH] drm/amdgpu: enable VCN RAS poison for VCN v4.0
Co
Hi Xinhui,
Am 29.11.22 um 03:11 schrieb Pan, Xinhui:
[AMD Official Use Only - General]
What I am thinking is that
Hi Chris,
For continuous memory allocation, of course the blocks are in ascending order.
For non-continuous memory allocation, the allocated memory might be continuous
while the
This patch fixes potential memory leakage and seg fault
in _gpuvm_import_dmabuf() function
Signed-off-by: Konstantin Meskhidze
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.
This commit fixes logic error in function 'amdgpu_hw_ip_info':
- value 'uvd' might be 'vcn'.
Signed-off-by: Konstantin Meskhidze
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/d
On Mon, Nov 28, 2022 at 11:18:00AM -0500, Alex Deucher wrote:
> On Mon, Nov 28, 2022 at 2:18 AM Demi Marie Obenour
> wrote:
> >
> > Dear Christian:
> >
> > What is the status of the AMDGPU work for Xen dom0? That was mentioned in
> > https://lore.kernel.org/dri-devel/b2dec9b3-03a7-e7ac-306e-1da02
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