To remove duplication for GFX11 as well, use the common MQD manager
functions defined in kfd_mqd_manager.c for all version of managers
Signed-off-by: Shiwu Zhang
Acked-by: Felix Kuehling
Reviewed-by: Mukul Joshi
---
.../gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 85 +++
1 file
From: Alex Hung
[Why & How]
This fixes kernel errors when IGT disables primary planes during the
tests kms_universal_plane::functional_test_pipe/pageflip_test_pipe.
Acked-by: Wayne Lin
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 12
1 file
From: Charlene Liu
[why]
num_dsc is 3 for dcn314 based on HW capablity.
Reviewed-by: Martin Leung
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/am
From: Aric Cyr
This version brings along following fixes:
- Fix urgent latency override for DCN32/DCN321
- Correct hostvm flag in DCN31
- Added new Asic Id for DCN301
- Adjust to 2 phys in DCN301
- Update dummy P-state search to use DCN32 DML
- Increase dcn315 pstate change latency
- Disable OTG
From: Wenjing Liu
[Why]
There is a coding error when moving dp disable link phy to
hw sequencer, where the receiver power control is missed during
this refactor.
[how]
1. Add back missing receiver power control in disable link phy.
2. minor modifications to ensure there is no undesired sequence
From: Charlene Liu
[why]
update hw dccg based on HW delta, and reuse common src code
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Dmytro Laktyushkin
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 1 +
.../drm/amd/display/dc/dcn201/dcn20
From: muansari
[WHY]
The Vstartup position should be as late as possible to
maximize power saving with the current. Calculation of
Vstartup in DML does not take into account as SDP signal.
[HOW]
Made necessary changes to calculate the correct Vstartup
position in DML to account for AS SDP
* Over
From: Alvin Lee
[Why & How]
If we find that DML requires pipe split, run through
DML again because the DET allocation per pipe must
be re-assigned.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 26 +-
.../
From: Robin Chen
[Why]
The Sink device string ID1/ID2 use 5 bytes instead of 6 bytes,
so the driver should compare the first 5 bytes only.
Reviewed-by: Anthony Koo
Acked-by: Wayne Lin
Signed-off-by: Robin Chen
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 7 ---
drivers/g
From: Josip Pavic
[Why & How]
Extend existing OTG state collection function to include the vertical
interrupt 1 state.
Reviewed-by: Aric Cyr
Acked-by: Wayne Lin
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 6 ++
drivers/gpu/drm/amd/display/dc/dcn10/d
From: Daniel Miess
[Why]
DP DSC compliance failing for dcn314 due to ICH_RESET_AT_END_OF_LINE
shift and mask being missing
[How]
Add in shift and mask for ICH_RESET_AT_END_OF_LINE
Reviewed-by: Nicholas Kazlauskas
Acked-by: Wayne Lin
Signed-off-by: Daniel Miess
---
.../gpu/drm/amd/display/dc
From: Josip Pavic
[Why & How]
Increase width of some variables to avoid comparing integers of
different widths
Reviewed-by: Alvin Lee
Acked-by: Wayne Lin
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c| 2 +-
drivers/gpu/drm/amd/display/dc/dcn32/
From: Jaehyun Chung
[Why]
v1_5 display object table has no way for connectors to
indicate which slot they are a part of, resulting in additional
empty slots to appear in EDID management UI.
[How]
Assume that all connectors belong to the same slot.
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Sign
From: Rodrigo Siqueira
[Why and How]
We are hitting k1/k2 assert when we are using a virtual signal in the
test; as a result, we are failing some automated tests with a false
positive. This commit addresses this issue by ignoring the assert
condition if we use SIGNAL_TYPE_VIRTUAL.
Reviewed-by: A
From: Nicholas Kazlauskas
[Why]
This shouldn't trigger during tiled display hotplug/unplug but it does
because one of the tiles can end up with a NULL plane state.
This also doesn't guard against the hang that it was originally trying
to resolve, and can instead cause DIO corruption due to OTG s
From: Aurabindo Pillai
[Why and How]
Enable committing subvp config through DMCUB for DCN32
Reviewed-by: Alvin Lee
Acked-by: Wayne Lin
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/a
From: Dmytro Laktyushkin
[Why & How]
Update after new measurment came in
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Signed-off-by: Dmytro Laktyushkin
---
.../dc/clk_mgr/dcn315/dcn315_clk_mgr.c| 22 ---
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drive
From: Alvin Lee
[Why & How]
We should not allocate any DET for the phantom pipes.
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
.../amd/display/dc/dcn32/dcn32_resource_helpers.c| 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/driver
From: Cruise Hung
[Why]
When USB4 DP link training failed and fell back to lower link rate,
the time slot calculation uses the verified_link_cap.
And the verified_link_cap was not updated to the new one.
It caused the wrong VC payload time-slot was allocated.
[How]
Updated verified_link_cap with
From: George Shen
[Why]
Current DCN3.2 logic for finding the dummy P-state index uses the
DCN3.0 DML validation function instead of DCN3.2 DML.
This can result in either unexpected DML VBA values, or unexpected
dummy P-state index to be used.
[How]
Update the dummy P-state logic to use DCN3.2 D
From: Sherry Wang
[Why]
Hostvm should be enabled/disabled accordding to
the status of riommu_active, but hostvm always
be disabled on DCN31 which causes underflow
[How]
Set correct hostvm flag on DCN31
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Sherry Wang
---
drivers/gpu/
From: Pavle Kotarac
[WHY]
Adding new asic id for dcn301
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Pavle Kotarac
---
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
b/dr
From: Charlene Liu
[why]
Expose few dchubbun functions in dcn31 and dcn32 to leverage.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
---
.../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 2 +-
.../drm/amd/display/dc/dcn31/dcn31_hubbub.h | 2 ++
.../drm/amd
From: Meenakshikumar Somasundaram
[Why]
During hot plug of specific 5K tiled display, sometimes both the tiles
are not synchronized resulting in distortion. The reason is that otgs of
both the tiles goes out of sync when otg workaround (dcnxxx_disable_otg_wa)
is applied for bandwidth optimization
From: Pavle Kotarac
[WHY]
New dcn301 has 2 less phys
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Pavle Kotarac
---
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc
From: George Shen
[Why]
The urgent latency override is useful when debugging issues
relating to underflow.
Current overridden variable is not correct and has no effect
on DCN3.2 and DCN3.21 DML calculations.
[How]
For DCN3.2 and DCN3.21, override the correct urgent latency
variable when boundin
From: Ian Chen
[Why & How]
Move extra panel power sequencer settings into panel_cofig struct.
Reviewed-by: Anthony Koo
Acked-by: Wayne Lin
Signed-off-by: Ian Chen
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 11 +++-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +++---
.../g
From: Alvin Lee
[Why & How]
Uncomment SubVP pipe split assignment in driver since FW headers
are now promoted
Reviewed-by: Martin Leung
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers
From: zhikzhai
[why]
We have minimal pipe split transition method to avoid pipe
allocation outage.However, this method will invoke audio setup
which cause audio output stuck once pipe reallocate.
[how]
skip audio setup for pipelines which audio stream has been enabled
Reviewed-by: Charlene Liu
From: Aric Cyr
This version brings along following fixes:
- Port DCN30 420 logic to DCN32
- Remove some unused definitions from DCN32/321
- Remove dp dig pixle rate div policy from dcn314
- Fix dcn315 reading of memory channel count and width
- Fix SubVP and ODM relevant issues
- Fix pipe split,
From: Anthony Koo
- Handle pipe split case for SubVP:
Pass in pipe split index for main and phantom pipes
Reviewed-by: Aric Cyr
Acked-by: Wayne Lin
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff -
From: Hugo Hu
[Why]
The desktop plane and full-screen game plane may have different
gamut remap coefficients, if switching between desktop and
full-screen game without updating the gamut remap will cause
incorrect color.
[How]
Update gamut remap if planes change.
Reviewed-by: Dmytro Laktyushkin
From: Alvin Lee
[Why and How]
- For driver disable cases in current implementation, if P-State
is unsupported or still supported by firmware, we force it
supported by DCN.
- SubVP now needs to be included in this case along with FPO.
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Signed-off-by:
From: Alvin Lee
[Why and How]
For SubVP pipe split case, pass in split index for
main and phantom pipes to ensure that the P-State
sequence will force P-State for all required pipes.
Reviewed-by: Nevenko Stupar
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
drivers/gp
From: Alvin Lee
[Why and How]
- Don't skip bottom and next odm pipe when calculating
num ways for subvp
- Don't need to double cache lines for DCC (divide by 256)
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
.../drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 1
From: Wenjing Liu
[why]
Original change 8da78e248069 "drm/amd/display: Add
interface to track PHY state" was implemented by assuming stream's
dpms off is equivalent to PHY power off.
This assumption doesn't hold in following situations:
1. MST multiple stream scenario, where multiple streams are
From: Wenjing Liu
[why]
When user unplugs mst hubs, the current code will forcefully zero
entire mst payload allocation table structure stored in link before we
deallocate actual payload when disabling stream.
During the first disable stream sequence, we will use current mst
payload allocation t
From: Alvin Lee
[Why and How]
- Add a debug option for allocating extra way for cursor
- Remove usage of cache_cursor_addr since it's not gaurenteed
to be populated
- Include cursor size in MALL calculation if it exceeds the
DCN cursor buffer size (and don't need extra way for cursor)
Review
From: Alvin Lee
[Why and How]
- Only consider pixel rate div policy for DCN32+
Reviewed-by: Martin Leung
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
.../gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c | 16 ++--
.../gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h | 2 --
.../gpu/
From: Alvin Lee
[Why & How]
ODM seamless transitions require DIV_MODE_AUTO. However,
DIV_MODE_AUTO only works when all the horizontal timing params
are divisible by the ODM combine factor. Therefore, disable the
ODM 2:1 policy when the horizontal timing params are not divisible
by 2.
Reviewed-by
From: Michael Strauss
[WHY]
LTTPRs can in very rare instsances fail to increment DPCD LTTPR count.
This results in aux-i LTTPR requests to be sent to the wrong DPCD
address, which causes link training failure.
[HOW]
Override internal repeater count if fixed_vs flag is set for a given link
Revie
From: Leo Chen
[Why & How]
Added logs for panel delays, spread_spectrum_percentage,
and gpuclk_ss_percentage to facilitate debugging.
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Leo Chen
---
.../drm/amd/display/dc/bios/bios_parser2.c| 54 ++-
1 file chang
From: Dmytro Laktyushkin
[Why & How]
Correctly set ddr5 channel width to 8 bytes
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Signed-off-by: Dmytro Laktyushkin
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 3 +--
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 7 +
From: Leo Li
[Why]
DC makes use of layer_index (zpos) when picking the HW plane to enable
HW cursor on. However, some compositors will not attach zpos information
to each DRM plane. Consequently, in amdgpu, we default layer_index to 0
and do not update it.
This causes said DC logic to enable HW
From: Charlene Liu
[Why & How]
Support dramclk change latency change via debug option and add some
code isolation.
Reviewed-by: Martin Leung
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
---
.../drm/amd/display/dc/dml/dcn301/dcn301_fpu.c | 5 +
.../drm/amd/display/dc/dml/dcn31/dcn31_
From: Alvin Lee
[Why & How]
- Pipe split prediction previously only took into
account MPC split. We must also consider when
ODM combine is required, and when we apply ODM
combine by policy.
- Also re-work DET allocation function as it wasn't
properly splitting the DET per stream, per plane.
Rev
From: Aurabindo Pillai
[Why&How]
After reg offset initialization was switched to runtime rather than
compile time, some of the defintions are not needed anymore and can
be removed.
Acked-by: Wayne Lin
Signed-off-by: Aurabindo Pillai
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 23 -
From: Chris Park
[Why]
420 modes are limited by FMT buffer width of 4096
which requires multi-pipe support in form of ODM
combine. If 420 modes have greater HActive than
4096, the DML logic should accomodate whether
it should be rejected, or ODM combine 2:1 or 4:1
is triggered accordingly.
[How
Sorry for spamming..
Resend again due to network issues.
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
For DC version 3.2.203
- Port DCN30 420 logic to DCN32
- Remove some unused definitions from DCN32/321
- Remove dp dig pixle rate div policy from dcn314
- Fi
On 2022-09-13 22:34, Zhu, Jiadong wrote:
>> +
>> + r_rptr = amdgpu_ring_get_rptr(mux->real_ring);
>> + r_wptr = amdgpu_ring_get_wptr(mux->real_ring);
>> These names are very much the same to a human. How about writep and readp?
> r_rptr for real ring's read ptr differed from sw_rptr. Mayb
From: Alex Hung
[Why & How]
This fixes kernel errors when IGT disables primary planes during the
tests kms_universal_plane::functional_test_pipe/pageflip_test_pipe.
Acked-by: Wayne Lin
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 12
1 file
From: Charlene Liu
[why]
num_dsc is 3 for dcn314 based on HW capablity.
Reviewed-by: Martin Leung
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/am
From: Wenjing Liu
[Why]
There is a coding error when moving dp disable link phy to
hw sequencer, where the receiver power control is missed during
this refactor.
[how]
1. Add back missing receiver power control in disable link phy.
2. minor modifications to ensure there is no undesired sequence
From: Robin Chen
[Why]
The Sink device string ID1/ID2 use 5 bytes instead of 6 bytes,
so the driver should compare the first 5 bytes only.
Reviewed-by: Anthony Koo
Acked-by: Wayne Lin
Signed-off-by: Robin Chen
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 7 ---
drivers/g
From: Alvin Lee
[Why & How]
If we find that DML requires pipe split, run through
DML again because the DET allocation per pipe must
be re-assigned.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 26 +-
.../
From: Charlene Liu
[why]
update hw dccg based on HW delta, and reuse common src code
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Dmytro Laktyushkin
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 1 +
.../drm/amd/display/dc/dcn201/dcn20
From: Josip Pavic
[Why & How]
Extend existing OTG state collection function to include the vertical
interrupt 1 state.
Reviewed-by: Aric Cyr
Acked-by: Wayne Lin
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 6 ++
drivers/gpu/drm/amd/display/dc/dcn10/d
From: muansari
[WHY]
The Vstartup position should be as late as possible to
maximize power saving with the current. Calculation of
Vstartup in DML does not take into account as SDP signal.
[HOW]
Made necessary changes to calculate the correct Vstartup
position in DML to account for AS SDP
* Over
From: Daniel Miess
[Why]
DP DSC compliance failing for dcn314 due to ICH_RESET_AT_END_OF_LINE
shift and mask being missing
[How]
Add in shift and mask for ICH_RESET_AT_END_OF_LINE
Reviewed-by: Nicholas Kazlauskas
Acked-by: Wayne Lin
Signed-off-by: Daniel Miess
---
.../gpu/drm/amd/display/dc
From: Jaehyun Chung
[Why]
v1_5 display object table has no way for connectors to
indicate which slot they are a part of, resulting in additional
empty slots to appear in EDID management UI.
[How]
Assume that all connectors belong to the same slot.
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Sign
From: Nicholas Kazlauskas
[Why]
This shouldn't trigger during tiled display hotplug/unplug but it does
because one of the tiles can end up with a NULL plane state.
This also doesn't guard against the hang that it was originally trying
to resolve, and can instead cause DIO corruption due to OTG s
From: Aurabindo Pillai
[Why and How]
Enable committing subvp config through DMCUB for DCN32
Reviewed-by: Alvin Lee
Acked-by: Wayne Lin
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/a
From: Rodrigo Siqueira
[Why and How]
We are hitting k1/k2 assert when we are using a virtual signal in the
test; as a result, we are failing some automated tests with a false
positive. This commit addresses this issue by ignoring the assert
condition if we use SIGNAL_TYPE_VIRTUAL.
Reviewed-by: A
From: Alvin Lee
[Why & How]
We should not allocate any DET for the phantom pipes.
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
.../amd/display/dc/dcn32/dcn32_resource_helpers.c| 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/driver
From: Cruise Hung
[Why]
When USB4 DP link training failed and fell back to lower link rate,
the time slot calculation uses the verified_link_cap.
And the verified_link_cap was not updated to the new one.
It caused the wrong VC payload time-slot was allocated.
[How]
Updated verified_link_cap with
From: Dmytro Laktyushkin
[Why & How]
Update after new measurment came in
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Signed-off-by: Dmytro Laktyushkin
---
.../dc/clk_mgr/dcn315/dcn315_clk_mgr.c| 22 ---
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drive
From: Josip Pavic
[Why & How]
Increase width of some variables to avoid comparing integers of
different widths
Reviewed-by: Alvin Lee
Acked-by: Wayne Lin
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c| 2 +-
drivers/gpu/drm/amd/display/dc/dcn32/
From: Meenakshikumar Somasundaram
[Why]
During hot plug of specific 5K tiled display, sometimes both the tiles
are not synchronized resulting in distortion. The reason is that otgs of
both the tiles goes out of sync when otg workaround (dcnxxx_disable_otg_wa)
is applied for bandwidth optimization
From: George Shen
[Why]
Current DCN3.2 logic for finding the dummy P-state index uses the
DCN3.0 DML validation function instead of DCN3.2 DML.
This can result in either unexpected DML VBA values, or unexpected
dummy P-state index to be used.
[How]
Update the dummy P-state logic to use DCN3.2 D
From: Pavle Kotarac
[WHY]
New dcn301 has 2 less phys
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Pavle Kotarac
---
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc
From: Charlene Liu
[why]
Expose few dchubbun functions in dcn31 and dcn32 to leverage.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
---
.../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 2 +-
.../drm/amd/display/dc/dcn31/dcn31_hubbub.h | 2 ++
.../drm/amd
From: Pavle Kotarac
[WHY]
Adding new asic id for dcn301
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Pavle Kotarac
---
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
b/dr
From: Sherry Wang
[Why]
Hostvm should be enabled/disabled accordding to
the status of riommu_active, but hostvm always
be disabled on DCN31 which causes underflow
[How]
Set correct hostvm flag on DCN31
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Sherry Wang
---
drivers/gpu/
From: George Shen
[Why]
The urgent latency override is useful when debugging issues
relating to underflow.
Current overridden variable is not correct and has no effect
on DCN3.2 and DCN3.21 DML calculations.
[How]
For DCN3.2 and DCN3.21, override the correct urgent latency
variable when boundin
From: Alvin Lee
[Why & How]
Uncomment SubVP pipe split assignment in driver since FW headers
are now promoted
Reviewed-by: Martin Leung
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers
From: zhikzhai
[why]
We have minimal pipe split transition method to avoid pipe
allocation outage.However, this method will invoke audio setup
which cause audio output stuck once pipe reallocate.
[how]
skip audio setup for pipelines which audio stream has been enabled
Reviewed-by: Charlene Liu
From: Ian Chen
[Why & How]
Move extra panel power sequencer settings into panel_cofig struct.
Reviewed-by: Anthony Koo
Acked-by: Wayne Lin
Signed-off-by: Ian Chen
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 11 +++-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +++---
.../g
From: Hugo Hu
[Why]
The desktop plane and full-screen game plane may have different
gamut remap coefficients, if switching between desktop and
full-screen game without updating the gamut remap will cause
incorrect color.
[How]
Update gamut remap if planes change.
Reviewed-by: Dmytro Laktyushkin
From: Aric Cyr
This version brings along following fixes:
- Port DCN30 420 logic to DCN32
- Remove some unused definitions from DCN32/321
- Remove dp dig pixle rate div policy from dcn314
- Fix dcn315 reading of memory channel count and width
- Fix SubVP and ODM relevant issues
- Fix pipe split,
From: Anthony Koo
- Handle pipe split case for SubVP:
Pass in pipe split index for main and phantom pipes
Reviewed-by: Aric Cyr
Acked-by: Wayne Lin
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff -
From: Alvin Lee
[Why and How]
- Don't skip bottom and next odm pipe when calculating
num ways for subvp
- Don't need to double cache lines for DCC (divide by 256)
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
.../drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 1
From: Alvin Lee
[Why and How]
- For driver disable cases in current implementation, if P-State
is unsupported or still supported by firmware, we force it
supported by DCN.
- SubVP now needs to be included in this case along with FPO.
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Signed-off-by:
From: Alvin Lee
[Why and How]
For SubVP pipe split case, pass in split index for
main and phantom pipes to ensure that the P-State
sequence will force P-State for all required pipes.
Reviewed-by: Nevenko Stupar
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
drivers/gp
From: Alvin Lee
[Why and How]
- Add a debug option for allocating extra way for cursor
- Remove usage of cache_cursor_addr since it's not gaurenteed
to be populated
- Include cursor size in MALL calculation if it exceeds the
DCN cursor buffer size (and don't need extra way for cursor)
Review
From: Alvin Lee
[Why & How]
ODM seamless transitions require DIV_MODE_AUTO. However,
DIV_MODE_AUTO only works when all the horizontal timing params
are divisible by the ODM combine factor. Therefore, disable the
ODM 2:1 policy when the horizontal timing params are not divisible
by 2.
Reviewed-by
From: Wenjing Liu
[why]
When user unplugs mst hubs, the current code will forcefully zero
entire mst payload allocation table structure stored in link before we
deallocate actual payload when disabling stream.
During the first disable stream sequence, we will use current mst
payload allocation t
From: Leo Li
[Why]
DC makes use of layer_index (zpos) when picking the HW plane to enable
HW cursor on. However, some compositors will not attach zpos information
to each DRM plane. Consequently, in amdgpu, we default layer_index to 0
and do not update it.
This causes said DC logic to enable HW
From: Michael Strauss
[WHY]
LTTPRs can in very rare instsances fail to increment DPCD LTTPR count.
This results in aux-i LTTPR requests to be sent to the wrong DPCD
address, which causes link training failure.
[HOW]
Override internal repeater count if fixed_vs flag is set for a given link
Revie
From: Wenjing Liu
[why]
Original change 8da78e248069 "drm/amd/display: Add
interface to track PHY state" was implemented by assuming stream's
dpms off is equivalent to PHY power off.
This assumption doesn't hold in following situations:
1. MST multiple stream scenario, where multiple streams are
From: Dmytro Laktyushkin
[Why & How]
Correctly set ddr5 channel width to 8 bytes
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Signed-off-by: Dmytro Laktyushkin
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 3 +--
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 7 +
From: Alvin Lee
[Why and How]
- Only consider pixel rate div policy for DCN32+
Reviewed-by: Martin Leung
Acked-by: Wayne Lin
Signed-off-by: Alvin Lee
---
.../gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c | 16 ++--
.../gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h | 2 --
.../gpu/
From: Leo Chen
[Why & How]
Added logs for panel delays, spread_spectrum_percentage,
and gpuclk_ss_percentage to facilitate debugging.
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Leo Chen
---
.../drm/amd/display/dc/bios/bios_parser2.c| 54 ++-
1 file chang
From: Charlene Liu
[Why & How]
Support dramclk change latency change via debug option and add some
code isolation.
Reviewed-by: Martin Leung
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
---
.../drm/amd/display/dc/dml/dcn301/dcn301_fpu.c | 5 +
.../drm/amd/display/dc/dml/dcn31/dcn31_
From: Alvin Lee
[Why & How]
- Pipe split prediction previously only took into
account MPC split. We must also consider when
ODM combine is required, and when we apply ODM
combine by policy.
- Also re-work DET allocation function as it wasn't
properly splitting the DET per stream, per plane.
Rev
From: Aurabindo Pillai
[Why&How]
After reg offset initialization was switched to runtime rather than
compile time, some of the defintions are not needed anymore and can
be removed.
Acked-by: Wayne Lin
Signed-off-by: Aurabindo Pillai
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 23 -
From: Chris Park
[Why]
420 modes are limited by FMT buffer width of 4096
which requires multi-pipe support in form of ODM
combine. If 420 modes have greater HActive than
4096, the DML logic should accomodate whether
it should be rejected, or ODM combine 2:1 or 4:1
is triggered accordingly.
[How
Resend due to connection time out.
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
For DC version 3.2.203
- Port DCN30 420 logic to DCN32
- Remove some unused definitions from DCN32/321
- Remove dp dig pixle rate div policy from dcn314
- Fix dcn315 reading of me
From: George Shen
[Why]
Current DCN3.2 logic for finding the dummy P-state index uses the
DCN3.0 DML validation function instead of DCN3.2 DML.
This can result in either unexpected DML VBA values, or unexpected
dummy P-state index to be used.
[How]
Update the dummy P-state logic to use DCN3.2 D
From: Charlene Liu
[why]
Expose few dchubbun functions in dcn31 and dcn32 to leverage.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
---
.../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 2 +-
.../drm/amd/display/dc/dcn31/dcn31_hubbub.h | 2 ++
.../drm/amd
From: Pavle Kotarac
[WHY]
New dcn301 has 2 less phys
Reviewed-by: Charlene Liu
Acked-by: Wayne Lin
Signed-off-by: Pavle Kotarac
---
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc
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