From: Alvin Lee <alvin.l...@amd.com>
[Why and How]
- Add a debug option for allocating extra way for cursor
- Remove usage of cache_cursor_addr since it's not gaurenteed
to be populated
- Include cursor size in MALL calculation if it exceeds the
DCN cursor buffer size (and don't need extra way for cursor)
Reviewed-by: Aurabindo Pillai <aurabindo.pil...@amd.com>
Acked-by: Wayne Lin <wayne....@amd.com>
Signed-off-by: Alvin Lee <alvin.l...@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 10 ++++++----
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 1 +
.../gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 1 +
4 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 53b13beff0b2..af726ffeb0d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -832,6 +832,7 @@ struct dc_debug_options {
bool force_subvp_mclk_switch;
bool allow_sw_cursor_fallback;
unsigned int force_subvp_num_ways;
+ bool alloc_extra_way_for_cursor;
bool force_usr_allow;
/* uses value at boot and disables switch */
bool disable_dtb_ref_clk_switch;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index c6d2a05ded3d..931dcf3e5ada 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -304,7 +304,8 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc
*dc, struct dc_state *c
* using the max for calculation
*/
if (hubp->curs_attr.width > 0) {
- cursor_size = hubp->curs_attr.width *
hubp->curs_attr.height;
+ // Round cursor width to next multiple
of 64
+ cursor_size = (((hubp->curs_attr.width
+ 63) / 64) * 64) * hubp->curs_attr.height;
break;
}
}
@@ -325,7 +326,8 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc
*dc, struct dc_state *c
break;
}
- if (stream->cursor_position.enable &&
plane->address.grph.cursor_cache_addr.quad_part) {
+ if (stream->cursor_position.enable &&
!dc->debug.alloc_extra_way_for_cursor &&
+ cursor_size > 16384) {
cache_lines_used += dcn32_cache_lines_for_surface(dc,
cursor_size,
plane->address.grph.cursor_cache_addr.quad_part);
}
@@ -345,8 +347,8 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc
*dc, struct dc_state *c
plane = ctx->stream_status[i].plane_states[j];
if (stream->cursor_position.enable && plane &&
-
!plane->address.grph.cursor_cache_addr.quad_part &&
- cursor_size > 16384) {
+ dc->debug.alloc_extra_way_for_cursor &&
+ cursor_size > 16384) {
/* Cursor caching is not supported since it
won't be on the same line.
* So we need an extra line to accommodate it.
With large cursors and a single 4k monitor
* this case triggers corruption. If we're at
the edge, then dont trigger display refresh
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index d757d1638fa7..dad174a52449 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -720,6 +720,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.enable_single_display_2to1_odm_policy = true,
.enable_dp_dig_pixel_rate_div_policy = 1,
.allow_sw_cursor_fallback = false,
+ .alloc_extra_way_for_cursor = true,
};
static const struct dc_debug_options debug_defaults_diags = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 60bf6e1b2972..1068230f16ee 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -720,6 +720,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.enable_single_display_2to1_odm_policy = true,
.enable_dp_dig_pixel_rate_div_policy = 1,
.allow_sw_cursor_fallback = false,
+ .alloc_extra_way_for_cursor = true,
};
static const struct dc_debug_options debug_defaults_diags = {
--
2.37.3
