Reviewed-by: Roger He
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
Christian K?nig
Sent: Friday, December 22, 2017 2:06 AM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/ttm: drop the spin in delaye
On Monday 18 December 2017, Mario Kleiner wrote:
> From: Fredrik Höglund
>
> Tested by Mario on a Radeon HD 4000 series for the r600
> exa path, and on Radeon HD 5770 for the evergreen exa
> path.
>
> Reviewed-and-Tested-by: Mario Kleiner
> Cc: Fredrik Höglund
I think the only question is whe
On 12/19/2017 09:58 AM, Michel Dänzer wrote:
On 2017-12-18 11:36 PM, Mario Kleiner wrote:
The size of the X-Server pScreenPriv->PreAllocIndices
array allocated within xf86HandleColormaps() is given
by the given maxColors argument, but the range of
indices by which the PreAllocIndices array is in
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Rex Zhu
Sent: Thursday, December 21, 2017 5:41:36 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amd/pp: Get and save CZ/ST smu version
The smu firmware is loaded by the sbios on APUs
I really should've checked before sending these but with this patch I hang the
system on boot with Baffin. The rest of the patches in this set are kosher.
Just a heads-up for anyone thinking of picking this up.
Happy Holidays.
Harry
On 2017-12-21 05:08 PM, Harry Wentland wrote:
> From: Yongqia
From: Yongqiang Sun
Proper sequence should be:
disable backlight
dp blank
disable output
edp power off
In enable accelatate mode, all the encoder and controller
are disabled, so move disable eDP to the function is the
easiest way to implement.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Che
From: Yongqiang Sun
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/g
From: Tony Cheng
Signed-off-by: Tony Cheng
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 145909ace25d
Signed-off-by: Harry Wentland
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/displa
It would be useful to know which clocks are unsupported when logging an
error message about unsupported clocks.
Signed-off-by: Harry Wentland
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 5 -
1 file changed, 4 insertions(+), 1 delet
From: Andrew Jiang
We no longer change the plane state pointer for full updates, and as
such, we weren't setting the input transfer function and programming the
degamma registers when we are supposed to. Check for a full update, an
input TF change, or a gamma change in the update flags instead to
From: Yongqiang Sun
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 12
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 17 +
drivers/gpu/drm/amd/display/dc/dcn10
We've got a helper function to call dc_create_stream_for_sink and one
other place that calls it directly. Make sure we call the helper
functions always since we need to update a bunch of things in stream and
don't want to miss that.
Signed-off-by: Harry Wentland
Reviewed-by: Tony Cheng
Acked-by:
Signed-off-by: Harry Wentland
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc/core/dc_stre
Our APUs (Carrizo, Stoney, Raven) don't support it.
v2: Don't use is_apu as other ASICs might also not support it
Signed-off-by: Harry Wentland
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 5 +++--
drivers/gpu/drm/amd/display/d
Signed-off-by: Harry Wentland
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 ---
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 7 ---
drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h | 5 -
It might be good to understand why validate fails.
Signed-off-by: Harry Wentland
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdg
Signed-off-by: Harry Wentland
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_d
From: Yongqiang Sun
In case of some pipes are fused, pipe_idx should not
be used to program pipe regs. Instead of that, BE and FE
inst number should be used for reg index.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/calcs/d
From: Nikola Cornij
This will allow us to clean up resources on a stream as needed.
Signed-off-by: Nikola Cornij
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 +++
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 5 +
2 file
From: Roman Li
With FBC enabled there was a potential null-deref
on topology change due to hardcorded pipe index.
Signed-off-by: Roman Li
Reviewed-by: Harry Wentland
---
.../amd/display/dc/dce110/dce110_hw_sequencer.c| 23 ++
1 file changed, 19 insertions(+), 4 deletio
From: Yongqiang Sun
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/
* Don't block dual-link DVI modes (fix to light them up is pending)
* Make FBC allocation size dynamic
* Fix MST topology change problem
* Bunch of DCN fixes
Andrew Jiang (1):
drm/amd/display: Fix check for setting input TF
Charlene Liu (1):
drm/amd/display: PME sw wa to support waking AZ
From: Charlene Liu
Signed-off-by: Charlene Liu
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 12
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h| 3 ++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/g
From: Roman Li
After reworking FBC init for dynamic mem alloc
old FBC init code in DC became redundant.
Removing it.
Signed-off-by: Roman Li
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ---
drivers/gpu/drm/amd/display/dc/dc.h | 3 ---
From: Ken Chalmers
This allows Maximus emulation to more closely mirror actual silicon
execution.
* Enable pool->base.display_clock creation on Maximus.
* Enable rest of dce110_apply_ctx_to_hw on Maximus.
* Remove apply_ctx_to_hw_fpga (no longer necessary with the full
dce110_apply_ctx_to_hw e
This makes the check for HDMI and dual-link DVI a bit more
straightforward.
Signed-off-by: Harry Wentland
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +--
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 15
From: Roman Li
- FBC init reworked to alloc memory based on display mode.
- Removed asic-dependencies from dm
Signed-off-by: Roman Li
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 62 ---
1 file changed, 44 insert
From: "Jerry (Fangzhi) Zuo"
When topology changed and rehook up MST display to the same DP
connector, need to take care of drm_dp_mst_port object.
Due to the topology is changed, drm_dp_mst_port and corresponding
i2c_algorithm object could be NULL in such situation.
Signed-off-by: Jerry (Fangzh
From: Krunoslav Kovac
Signed-off-by: Krunoslav Kovac
Reviewed-by: Aric Cyr
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 6 +-
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 17 +---
.../amd/display/dc/dce110/dce110_hw_sequencer.c| 94 +++
From: Mikita Lipski
Verify that the stream is master - and program only the slave displays
Signed-off-by: Mikita Lipski
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc.c
From: Ken Chalmers
Maximus testing now defaults to a 700 MHz emulated dispclk
Signed-off-by: Ken Chalmers
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git
Hi Drake,
thanks for your extensive testing, solid test results, and help in tracking
bugs across multiple branches. These results are quite helpful.
If you have any questions don't hesitate to let us know.
Btw, great job you're doing with Endless OS. I've never tried it but I like
your approa
Thomas actually noticed that, but I didn't realized what he meant until
now.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 60bb5c12b568..84dfa2368a72 100644
-
Am 21.12.2017 um 18:09 schrieb Michel Dänzer:
On 2017-12-19 06:47 PM, Christian König wrote:
Yeah, that is a known issue which came to front again because Andrey's
patch is slightly buggy.
Please test and review the attached (only compile tested) fix for
Andrey's patch.
Still working on findin
On 2017-12-19 06:47 PM, Christian König wrote:
> Yeah, that is a known issue which came to front again because Andrey's
> patch is slightly buggy.
>
> Please test and review the attached (only compile tested) fix for
> Andrey's patch.
>
> Still working on finding the root cause, but so far didn't
Hi,
Thanks for the hard work on AMD DC development! Here are some new test
results - hope they are interesting/useful.
CONTEXT
We have been tracking DC for a while as we work with multiple products
where amdgpu previously was not able to support the HDMI audio output.
We are hoping to ship the
The smu firmware is loaded by the sbios on APUs, so query it
from the smu and save the smu fw version info that is reported
to userspace.
Change-Id: Ifce41405c0369610985881cea26e14b0525e4d25
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 2 ++
drivers/gpu/drm/amd/
printk format strings accepting a single subsequent argument
are shorter thus easier to read.
Instead of having format strings accepting 3 different arguments
pointing to first 3 bytes of the same buffer rewrite the format
string to accept only one argument - the buffer - with "%3ph"
specifier.
S
On Wed, Dec 20, 2017 at 08:54:33PM +0100, Christian König wrote:
> Am 20.12.2017 um 20:43 schrieb Daniel Vetter:
> > On Wed, Dec 20, 2017 at 6:20 PM, Li, Samuel wrote:
> > > Ping... can someone please review this patch?
> > Might be simpler to implement your own dma-buf backend instead of
> > goin
Hi Thomas:
Also I wonder what testing is being performed on these changes prior to
submission?
Vulkan CTS test with Per VM BO enabled.
After that, Command submit will not need to provide BO list it will use. It is
helpful for performance to CPU bound games.
The reason why we enable ev
Yeah, well as I wrote the PASID in hardware is only 16bits (or sometimes
even less).
So we need an ida or idr to manage them instead of just an incrementing
counter or otherwise we could wrap around rather quickly.
Thanks for the review,
Christian.
Am 21.12.2017 um 09:39 schrieb Chunming Zho
The patch itself is Reviewed-by: Chunming Zhou
Another question,
vice versa, Could PASID directly use fence context if we switch to use
fence context as client id? any bits limited in hw to present PASID?
Regards,
David Zhou
On 2017年12月21日 16:15, Christian König wrote:
The problem is PASID
Am 21.12.2017 um 08:58 schrieb Thomas Hellstrom:
What about
"Enable recursive locking at swapout time to make it possible to swap
out BOs that share the same reservation object."
Is "per VM BOs" an AMD specific name?
Yes, absolutely. It's even amdgpu specific, radeon uses the same
function
The problem is PASID would never work correctly, it is only 16bits and
so gets reused quite often.
But we introduced the client_id because we needed an unique 64bit
identifier which never repeats.
Felix probably didn't knew that when he added the comment.
Regards,
Christian.
Am 21.12.2017 u
On 12/21/2017 07:05 AM, He, Roger wrote:
-Original Message-
From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
Sent: Wednesday, December 20, 2017 9:36 PM
To: He, Roger ; amd-gfx@lists.freedesktop.org;
dri-de...@lists.freedesktop.org
Subject: Re: [PATCH 3/7] drm/ttm: use an
With a suitable commit log, LGTM.
Reviewed-by: Thomas Hellstrom
On 12/20/2017 11:34 AM, Roger He wrote:
Change-Id: I5279b5cd3560c4082b00f822219575a5f9c3808a
Signed-off-by: Roger He
---
drivers/gpu/drm/ttm/ttm_bo.c| 2 +-
drivers/gpu/drm/ttm/ttm_memory.c
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