Re: [USRP-users] big uhd.log

[Matis Alun via USRP-users]

Le 11/04/2018 à 02:16, Martin Braun via USRP-users a écrit :
> On 04/09/2018 02:48 PM, Matis Alun via USRP-users wrote:
>> Le 09/04/2018 à 23:20, Martin Braun via USRP-users a écrit :
>>> On 04/09/2018 07:35 AM, Matis Alun via USRP-users wrote:
 Hi everybody,

 I saw that a /tmp/uhd.log is created when running a sampling program and 
 it is becoming
 very large
 if the program runs during a long time.
 How can we disable the logging messages ?

 I tried to set the environment variable UHD_LOG_LEVEL or the pre-processor 
 -DUHD_LOG_LEVEL
 directive
 without any effect. Should I recompile all the UHD library with this flag ?

 I am using actually UHD 3.010.003.
>>> Matis,
>>>
>>> in order to enable file logging, you need UHD_LOG_FILE set. If you don't
>>> have the environment variable UHD_LOG_FILE set, you shouldn't be seeing
>>> a log file being generated.
>> This is strange: I have no such environment variable. If I set it to another 
>> value (like
>> /tmp/uhd2.log) -> uhd.log is created.
>> No effects if I change UHD_LOG_LEVEL too.
>>
>> It seems that another layer defines these variable ...
>> For your information, I run my system on Linux fedora 27
> How did you install UHD?
>
> -- M
I installed UHD using make install from a fresh download and compilation.(UHD 
3.010.003)
>
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[USRP-users] RFNoC support for maint branch

[Leandro Echevarría via USRP-users]

Hey everybody,

I was able to make an example block by installing uhd+gr-ettus with PyBombs
rfnoc-devel recipes, then using rfnocmodtool, generating .xml and .v files, and
then "compiling and installing" the block from the previously generated
makefiles.
I also included the block in the FPGA code, and uhd_usrp_probe finds it
without an issue.

The thing is this works only inside a sandboxed version of UHD (from branch
rfnoc-devel). If I run uhd_usrp_probe from my system version (compiled from
the last release of maint branch), the new block appears only as Block_0.

Is there any way for UHD v3.1.0.1 to recognize my block properly (beyond
its name, I'm of course intersted in it recognizing all its ports and
registers). I tried copying the .xml declaration file to
/usr/local/share/uhd/rfnoc/blocks/, but that doesn't seem to be enough.
Should I recompile some library? Or is there no other way than using
rfnoc-devel?

Thank you again,

Leo
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[USRP-users] Question about uhd_cal_tx_dc_offset

[Serge Malo via USRP-users]

Hi all,

In this Ettus UHD Manual page:
http://files.ettus.com/manual/page_calibration.html#calibration_self_utils

It is written to "*Disconnect* any external hardware from the RF antenna
ports" before executing the calibration tool.

Q: What is the exact reason for disconnecting external h/w from the RF
ports? Is it only to protect external devices from the strong signal
transmitted during the calibration? Could we leave passive elements
connected during calibration without affecting the result?

Q: Do you have a rough idea of how long the calibration is good for (a few
days vs a few months)?

Thanks,
Serge

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - -
*Serge Malo *
CDO & Co-founder, Skydel Solutions
Cell: 1-514-294-4017
www.skydelsolutions.com
Twitter: @skydelsol 
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[USRP-users] AD9361 in USRP B210

[Yeo Jin Kuang Alvin (IA) via USRP-users]

Hi all,

How do we set up the Ad9361_driver and ad9361 controls in the 
uhd/host/lib/usrp/common file for Ubuntu? What are the steps and prerequisites 
for this?

Thank you in advance!
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Re: [USRP-users] AD9361 in USRP B210

[Nick Foster via USRP-users]

What exactly do you want to do?

On Wed, Apr 11, 2018 at 6:33 PM Yeo Jin Kuang Alvin (IA) via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hi all,
>
>
>
> How do we set up the Ad9361_driver and ad9361 controls in the
> uhd/host/lib/usrp/common file for Ubuntu? What are the steps and
> prerequisites for this?
>
>
>
> Thank you in advance!
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>
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Re: [USRP-users] AD9361 in USRP B210

[Yeo Jin Kuang Alvin (IA) via USRP-users]

Hi,

I have the FPGA source code using Xilinx ISE 14.7, I want to output a signal 
out that is generated from the FPGA, however I suppose I have to control the 
AD9361 to get an output out to transmit unless I am wrong.

Thanks in advance!

From: Nick Foster [mailto:bistrom...@gmail.com]
Sent: Thursday, 12 April 2018 9:39 AM
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] AD9361 in USRP B210

What exactly do you want to do?

On Wed, Apr 11, 2018 at 6:33 PM Yeo Jin Kuang Alvin (IA) via USRP-users 
mailto:usrp-users@lists.ettus.com>> wrote:
Hi all,

How do we set up the Ad9361_driver and ad9361 controls in the 
uhd/host/lib/usrp/common file for Ubuntu? What are the steps and prerequisites 
for this?

Thank you in advance!
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Re: [USRP-users] Question about uhd_cal_tx_dc_offset

[Marcus D. Leech via USRP-users]

On 04/11/2018 09:08 PM, Serge Malo via USRP-users wrote:

Hi all,

In this Ettus UHD Manual page:
http://files.ettus.com/manual/page_calibration.html#calibration_self_utils

It is written to "*Disconnect*any external hardware from the RF 
antenna ports" before executing the calibration tool.


Q: What is the exact reason for disconnecting external h/w from the RF 
ports? Is it only to protect external devices from the strong signal 
transmitted during the calibration? Could we leave passive elements 
connected during calibration without affecting the result?
The calibration is sensitive to other things that could be leaking into 
the ports and disturbing the measurements.




Q: Do you have a rough idea of how long the calibration is good for (a 
few days vs a few months)?
I'm not sure that anyone has ever asked that question before. Certainly 
component-aging plays some role in shifting I/Q and DC-offset "balance", but
  I'm not sure about time-scales.   The other factor is 
temperature--things like fine-scale group delay can change on analog 
components with
  temperature, and unless the heating is uniform, it will be 
very-slightly different on different parts of the board.





Thanks,
Serge
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
- - - - - - - - - - - - - - -

*Serge Malo *
CDO & Co-founder, Skydel Solutions
Cell: 1-514-294-4017
www.skydelsolutions.com 
Twitter: @skydelsol 


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Re: [USRP-users] AD9361 in USRP B210

[Nick Foster via USRP-users]

The best option is probably to use existing UHD commands to set the gain,
frequency, master clock rate, etc., while modifying the image to generate
the transmit signal in the FPGA rather than in the host.

Nick

On Wed, Apr 11, 2018 at 6:41 PM Yeo Jin Kuang Alvin (IA) <
yjink...@dso.org.sg> wrote:

> Hi,
>
>
>
> I have the FPGA source code using Xilinx ISE 14.7, I want to output a
> signal out that is generated from the FPGA, however I suppose I have to
> control the AD9361 to get an output out to transmit unless I am wrong.
>
>
>
> Thanks in advance!
>
>
>
> *From:* Nick Foster [mailto:bistrom...@gmail.com]
> *Sent:* Thursday, 12 April 2018 9:39 AM
> *To:* Yeo Jin Kuang Alvin (IA)
> *Cc:* usrp-users@lists.ettus.com
> *Subject:* Re: [USRP-users] AD9361 in USRP B210
>
>
>
> What exactly do you want to do?
>
>
>
> On Wed, Apr 11, 2018 at 6:33 PM Yeo Jin Kuang Alvin (IA) via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
> Hi all,
>
>
>
> How do we set up the Ad9361_driver and ad9361 controls in the
> uhd/host/lib/usrp/common file for Ubuntu? What are the steps and
> prerequisites for this?
>
>
>
> Thank you in advance!
>
> ___
> USRP-users mailing list
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> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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[USRP-users] (no subject)

[Jason Matusiak via USRP-users]

I have been fighting for a day with issues on my N200s and N210s to no
avail. These were working units, but are giving me the following:
$ uhd_usrp_probe 
[INFO] [UHD] linux; GNU C++ version 4.8.5 20150623 (Red Hat 4.8.5-16);
Boost_105300; UHD_3.11.0.0-34-g4844f66d
[ERROR] [UHD] Exception caught in safe-call.
  in virtual usrp2_iface_impl::~usrp2_iface_impl()
  at /home/jmat/GR/src/uhd/host/lib/usrp/usrp2/usrp2_iface.cpp:81
this->lock_device(false); -> RuntimeError: 
Please update the firmware and FPGA images for your device.
See the application notes for USRP2/N-Series for instructions.
Expected protocol compatibility number [10 to 12], but got 7:
The firmware build is not compatible with the host code build.
Please run:

 "/home/jmat/GR/lib64/uhd/utils/uhd_images_downloader.py"
 "/home/jmat/GR/bin/uhd_image_loader" \
--args="type=usrp2,addr=192.168.10.2"

[INFO] [USRP2] Opening a USRP2/N-Series device...
[ERROR] [UHD] Exception caught in safe-call.
  in virtual usrp2_iface_impl::~usrp2_iface_impl()
  at /home/jmat/GR/src/uhd/host/lib/usrp/usrp2/usrp2_iface.cpp:81
this->lock_device(false); -> RuntimeError: 
Please update the firmware and FPGA images for your device.
See the application notes for USRP2/N-Series for instructions.
Expected protocol compatibility number [10 to 12], but got 7:
The firmware build is not compatible with the host code build.
Please run:

 "/home/jmat/GR/lib64/uhd/utils/uhd_images_downloader.py"
 "/home/jmat/GR/bin/uhd_image_loader" \
--args="type=usrp2,addr=192.168.10.2"

Error: RuntimeError: 
Please update the firmware and FPGA images for your device.
See the application notes for USRP2/N-Series for instructions.
Expected protocol compatibility number [10 to 12], but got 7:
The firmware build is not compatible with the host code build.
Please run:

 "/home/jmat/GR/lib64/uhd/utils/uhd_images_downloader.py"
 "/home/jmat/GR/bin/uhd_image_loader" \
--args="type=usrp2,addr=192.168.10.2"


I have this issue with a bunch of devices that have been sitting on my
shelf for a while. Is it too old to do the upgrade and I need to do
some sort of intermediate upgrade first? 

"./usrp_burn_mb_eeprom --args="addr=192.168.10.2" --read-all" gives the
same results as above.


Yet I also get this (which shows me that it can kind of see it):
$ uhd_find_devices 
[INFO] [UHD] linux; GNU C++ version 4.8.5 20150623 (Red Hat 4.8.5-16);
Boost_105300; UHD_3.11.0.0-34-g4844f66d
[ERROR] [UHD] Exception caught in safe-call.
  in virtual usrp2_iface_impl::~usrp2_iface_impl()
  at /home/jmat/GR/src/uhd/host/lib/usrp/usrp2/usrp2_iface.cpp:81
this->lock_device(false); -> RuntimeError: 
Please update the firmware and FPGA images for your device.
See the application notes for USRP2/N-Series for instructions.
Expected protocol compatibility number [10 to 12], but got 7:
The firmware build is not compatible with the host code build.
Please run:

 "/home/jmat/GR/lib64/uhd/utils/uhd_images_downloader.py"
 "/home/jmat/GR/bin/uhd_image_loader" \
--args="type=usrp2,addr=192.168.10.2"

--
-- UHD Device 0
--
Device Address:
serial: 
addr: 192.168.10.2
name: 
type: usrp2


Pings to its IP work fine. But when I run one of the commands and watch
it via wireshark, I see that every packet from my N210 is coming up
with a "ETHERNET FRAME CHECK SEQUENCE INCORRECT". That could be an
issue, or it could be something that always happens and I can ignore it
in this care.

Is there anyway to revive these units___
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Re: [USRP-users] AD9361 in USRP B210

[Yeo Jin Kuang Alvin (IA) via USRP-users]

Hi,

Sorry I am very new to all these, do you mean that I have to download visual 
studio to compile all the UHD .cpp and run them for the UHD commands? And for 
the FPGA image you talking about, is it the .bit file that is generated in the 
IMPACT?

Thank you in advance!

From: Nick Foster [mailto:bistrom...@gmail.com]
Sent: Thursday, 12 April 2018 12:04 PM
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] AD9361 in USRP B210

The best option is probably to use existing UHD commands to set the gain, 
frequency, master clock rate, etc., while modifying the image to generate the 
transmit signal in the FPGA rather than in the host.
Nick

On Wed, Apr 11, 2018 at 6:41 PM Yeo Jin Kuang Alvin (IA) 
mailto:yjink...@dso.org.sg>> wrote:
Hi,

I have the FPGA source code using Xilinx ISE 14.7, I want to output a signal 
out that is generated from the FPGA, however I suppose I have to control the 
AD9361 to get an output out to transmit unless I am wrong.

Thanks in advance!

From: Nick Foster [mailto:bistrom...@gmail.com]
Sent: Thursday, 12 April 2018 9:39 AM
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] AD9361 in USRP B210

What exactly do you want to do?

On Wed, Apr 11, 2018 at 6:33 PM Yeo Jin Kuang Alvin (IA) via USRP-users 
mailto:usrp-users@lists.ettus.com>> wrote:
Hi all,

How do we set up the Ad9361_driver and ad9361 controls in the 
uhd/host/lib/usrp/common file for Ubuntu? What are the steps and prerequisites 
for this?

Thank you in advance!
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Re: [USRP-users] AD9361 in USRP B210

[Nick Foster via USRP-users]

On Wed, Apr 11, 2018 at 10:15 PM Yeo Jin Kuang Alvin (IA) <
yjink...@dso.org.sg> wrote:

> Hi,
>
>
>
> Sorry I am very new to all these, do you mean that I have to download
> visual studio to compile all the UHD .cpp and run them for the UHD
> commands?
>

No, I mean that you can probably just get away with using UHD as-is with a
program you write (either in Python or C++) invoking a UHD device and
configuring it. There are many examples included in uhd/host/examples. If
you are lucky you might even get away with using one of the example
programs without modification, but I doubt it.


> And for the FPGA image you talking about, is it the .bit file that is
> generated in the IMPACT?
>

Yes.

You have a long learning curve ahead of you. It's a good idea at this point
to simply install UHD and get started using the B210 with some of the UHD
examples to see how it works in practice.

Nick


>
>
> Thank you in advance!
>
>
>
> *From:* Nick Foster [mailto:bistrom...@gmail.com]
> *Sent:* Thursday, 12 April 2018 12:04 PM
>
>
> *To:* Yeo Jin Kuang Alvin (IA)
> *Cc:* usrp-users@lists.ettus.com
> *Subject:* Re: [USRP-users] AD9361 in USRP B210
>
>
>
> The best option is probably to use existing UHD commands to set the gain,
> frequency, master clock rate, etc., while modifying the image to generate
> the transmit signal in the FPGA rather than in the host.
>
> Nick
>
>
>
> On Wed, Apr 11, 2018 at 6:41 PM Yeo Jin Kuang Alvin (IA) <
> yjink...@dso.org.sg> wrote:
>
> Hi,
>
>
>
> I have the FPGA source code using Xilinx ISE 14.7, I want to output a
> signal out that is generated from the FPGA, however I suppose I have to
> control the AD9361 to get an output out to transmit unless I am wrong.
>
>
>
> Thanks in advance!
>
>
>
> *From:* Nick Foster [mailto:bistrom...@gmail.com]
> *Sent:* Thursday, 12 April 2018 9:39 AM
> *To:* Yeo Jin Kuang Alvin (IA)
> *Cc:* usrp-users@lists.ettus.com
> *Subject:* Re: [USRP-users] AD9361 in USRP B210
>
>
>
> What exactly do you want to do?
>
>
>
> On Wed, Apr 11, 2018 at 6:33 PM Yeo Jin Kuang Alvin (IA) via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
> Hi all,
>
>
>
> How do we set up the Ad9361_driver and ad9361 controls in the
> uhd/host/lib/usrp/common file for Ubuntu? What are the steps and
> prerequisites for this?
>
>
>
> Thank you in advance!
>
> ___
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> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Re: [USRP-users] AD9361 in USRP B210

[Yeo Jin Kuang Alvin (IA) via USRP-users]

Hi,

Thank you! Btw will the FPGA image be ‘overlap’ after running the UHD software 
or they can both run concurrently?

Thank you in advance!

From: Nick Foster [mailto:bistrom...@gmail.com]
Sent: Thursday, 12 April 2018 1:28 PM
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] AD9361 in USRP B210

On Wed, Apr 11, 2018 at 10:15 PM Yeo Jin Kuang Alvin (IA) 
mailto:yjink...@dso.org.sg>> wrote:
Hi,

Sorry I am very new to all these, do you mean that I have to download visual 
studio to compile all the UHD .cpp and run them for the UHD commands?

No, I mean that you can probably just get away with using UHD as-is with a 
program you write (either in Python or C++) invoking a UHD device and 
configuring it. There are many examples included in uhd/host/examples. If you 
are lucky you might even get away with using one of the example programs 
without modification, but I doubt it.

And for the FPGA image you talking about, is it the .bit file that is generated 
in the IMPACT?

Yes.

You have a long learning curve ahead of you. It's a good idea at this point to 
simply install UHD and get started using the B210 with some of the UHD examples 
to see how it works in practice.
Nick


Thank you in advance!

From: Nick Foster [mailto:bistrom...@gmail.com]
Sent: Thursday, 12 April 2018 12:04 PM

To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] AD9361 in USRP B210

The best option is probably to use existing UHD commands to set the gain, 
frequency, master clock rate, etc., while modifying the image to generate the 
transmit signal in the FPGA rather than in the host.
Nick

On Wed, Apr 11, 2018 at 6:41 PM Yeo Jin Kuang Alvin (IA) 
mailto:yjink...@dso.org.sg>> wrote:
Hi,

I have the FPGA source code using Xilinx ISE 14.7, I want to output a signal 
out that is generated from the FPGA, however I suppose I have to control the 
AD9361 to get an output out to transmit unless I am wrong.

Thanks in advance!

From: Nick Foster [mailto:bistrom...@gmail.com]
Sent: Thursday, 12 April 2018 9:39 AM
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] AD9361 in USRP B210

What exactly do you want to do?

On Wed, Apr 11, 2018 at 6:33 PM Yeo Jin Kuang Alvin (IA) via USRP-users 
mailto:usrp-users@lists.ettus.com>> wrote:
Hi all,

How do we set up the Ad9361_driver and ad9361 controls in the 
uhd/host/lib/usrp/common file for Ubuntu? What are the steps and prerequisites 
for this?

Thank you in advance!
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Re: [USRP-users] AD9361 in USRP B210

[Nick Foster via USRP-users]

They are both necessary and serve completely separate and complementary
functions. At this point you are best served by reading the documentation.

Nick

On Wed, Apr 11, 2018, 10:33 PM Yeo Jin Kuang Alvin (IA) 
wrote:

> Hi,
>
>
>
> Thank you! Btw will the FPGA image be ‘overlap’ after running the UHD
> software or they can both run concurrently?
>
>
>
> Thank you in advance!
>
>
>
> *From:* Nick Foster [mailto:bistrom...@gmail.com]
> *Sent:* Thursday, 12 April 2018 1:28 PM
>
>
> *To:* Yeo Jin Kuang Alvin (IA)
> *Cc:* usrp-users@lists.ettus.com
> *Subject:* Re: [USRP-users] AD9361 in USRP B210
>
>
>
> On Wed, Apr 11, 2018 at 10:15 PM Yeo Jin Kuang Alvin (IA) <
> yjink...@dso.org.sg> wrote:
>
> Hi,
>
>
>
> Sorry I am very new to all these, do you mean that I have to download
> visual studio to compile all the UHD .cpp and run them for the UHD
> commands?
>
>
>
> No, I mean that you can probably just get away with using UHD as-is with a
> program you write (either in Python or C++) invoking a UHD device and
> configuring it. There are many examples included in uhd/host/examples. If
> you are lucky you might even get away with using one of the example
> programs without modification, but I doubt it.
>
>
>
> And for the FPGA image you talking about, is it the .bit file that is
> generated in the IMPACT?
>
>
>
> Yes.
>
> You have a long learning curve ahead of you. It's a good idea at this
> point to simply install UHD and get started using the B210 with some of the
> UHD examples to see how it works in practice.
>
> Nick
>
>
>
>
>
> Thank you in advance!
>
>
>
> *From:* Nick Foster [mailto:bistrom...@gmail.com]
> *Sent:* Thursday, 12 April 2018 12:04 PM
>
>
> *To:* Yeo Jin Kuang Alvin (IA)
> *Cc:* usrp-users@lists.ettus.com
> *Subject:* Re: [USRP-users] AD9361 in USRP B210
>
>
>
> The best option is probably to use existing UHD commands to set the gain,
> frequency, master clock rate, etc., while modifying the image to generate
> the transmit signal in the FPGA rather than in the host.
>
> Nick
>
>
>
> On Wed, Apr 11, 2018 at 6:41 PM Yeo Jin Kuang Alvin (IA) <
> yjink...@dso.org.sg> wrote:
>
> Hi,
>
>
>
> I have the FPGA source code using Xilinx ISE 14.7, I want to output a
> signal out that is generated from the FPGA, however I suppose I have to
> control the AD9361 to get an output out to transmit unless I am wrong.
>
>
>
> Thanks in advance!
>
>
>
> *From:* Nick Foster [mailto:bistrom...@gmail.com]
> *Sent:* Thursday, 12 April 2018 9:39 AM
> *To:* Yeo Jin Kuang Alvin (IA)
> *Cc:* usrp-users@lists.ettus.com
> *Subject:* Re: [USRP-users] AD9361 in USRP B210
>
>
>
> What exactly do you want to do?
>
>
>
> On Wed, Apr 11, 2018 at 6:33 PM Yeo Jin Kuang Alvin (IA) via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
> Hi all,
>
>
>
> How do we set up the Ad9361_driver and ad9361 controls in the
> uhd/host/lib/usrp/common file for Ubuntu? What are the steps and
> prerequisites for this?
>
>
>
> Thank you in advance!
>
> ___
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Re: [USRP-users] AD9361 in USRP B210

[Yeo Jin Kuang Alvin (IA) via USRP-users]

Thank you! :D

From: Nick Foster [mailto:bistrom...@gmail.com]
Sent: Thursday, 12 April 2018 1:38 PM
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] AD9361 in USRP B210

They are both necessary and serve completely separate and complementary 
functions. At this point you are best served by reading the documentation.

Nick
On Wed, Apr 11, 2018, 10:33 PM Yeo Jin Kuang Alvin (IA) 
mailto:yjink...@dso.org.sg>> wrote:
Hi,

Thank you! Btw will the FPGA image be ‘overlap’ after running the UHD software 
or they can both run concurrently?

Thank you in advance!

From: Nick Foster [mailto:bistrom...@gmail.com]
Sent: Thursday, 12 April 2018 1:28 PM

To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] AD9361 in USRP B210

On Wed, Apr 11, 2018 at 10:15 PM Yeo Jin Kuang Alvin (IA) 
mailto:yjink...@dso.org.sg>> wrote:
Hi,

Sorry I am very new to all these, do you mean that I have to download visual 
studio to compile all the UHD .cpp and run them for the UHD commands?

No, I mean that you can probably just get away with using UHD as-is with a 
program you write (either in Python or C++) invoking a UHD device and 
configuring it. There are many examples included in uhd/host/examples. If you 
are lucky you might even get away with using one of the example programs 
without modification, but I doubt it.

And for the FPGA image you talking about, is it the .bit file that is generated 
in the IMPACT?

Yes.

You have a long learning curve ahead of you. It's a good idea at this point to 
simply install UHD and get started using the B210 with some of the UHD examples 
to see how it works in practice.
Nick


Thank you in advance!

From: Nick Foster [mailto:bistrom...@gmail.com]
Sent: Thursday, 12 April 2018 12:04 PM

To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] AD9361 in USRP B210

The best option is probably to use existing UHD commands to set the gain, 
frequency, master clock rate, etc., while modifying the image to generate the 
transmit signal in the FPGA rather than in the host.
Nick

On Wed, Apr 11, 2018 at 6:41 PM Yeo Jin Kuang Alvin (IA) 
mailto:yjink...@dso.org.sg>> wrote:
Hi,

I have the FPGA source code using Xilinx ISE 14.7, I want to output a signal 
out that is generated from the FPGA, however I suppose I have to control the 
AD9361 to get an output out to transmit unless I am wrong.

Thanks in advance!

From: Nick Foster [mailto:bistrom...@gmail.com]
Sent: Thursday, 12 April 2018 9:39 AM
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] AD9361 in USRP B210

What exactly do you want to do?

On Wed, Apr 11, 2018 at 6:33 PM Yeo Jin Kuang Alvin (IA) via USRP-users 
mailto:usrp-users@lists.ettus.com>> wrote:
Hi all,

How do we set up the Ad9361_driver and ad9361 controls in the 
uhd/host/lib/usrp/common file for Ubuntu? What are the steps and prerequisites 
for this?

Thank you in advance!
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