[PATCH 0/4] FPGAs as Memory Technology Devices in U-Boot
As shown at a presentation in the recent OpenEmbedded Workshop,
it is possible to configure an FPGA in Passive Serial mode
using a standard SPI controller, each FPGA getting its own chipselect.
https://pretalx.com/openembedded-workshop-2023/talk/D3AQ3R/
This allows you to add the FPGA to the devicetree and to use standard MTD
commands, instead of the FPGA commands.
I.E: The SPI portion is
&spi1 {
u-boot,dm-spl;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
num-cs = <4>; /* Needed for GPIO cs */
cs-gpios =
<&gpio0 12 GPIO_ACTIVE_LOW>, /* D18,0:12 uart1_ctsn.spi1_cs0 */
<&gpio0 13 GPIO_ACTIVE_LOW>, /* D17,0:13 uart1_rtsn.spi1_cs1 */
<&gpio0 17 GPIO_ACTIVE_LOW>, /* K15,0:17 mii_txd2.spi1_cs2 */
<&gpio0 16 GPIO_ACTIVE_LOW>; /* J18,0:16 mii_txd3.spi1_cs3 */
spi-max-frequency = <1000>; ;
gpio_spi0: gpio_spi@0 {...}
gpio_spi1: gpio_spi@1 {...}
spi-fpga-cfg@2 {...} /* FPGA #1 */
spy-fpga-cfg@3 {...} /* FPGA #2 */
};
The FPGA part is.
spi-fpga-cfg@2 { /* Intel Cyclone 10, 10CL010 */
#address-cells = <1>;
#size-cells = <1>;
compatible = "intel,cyclone10";
reg = <2>; /* Chip select 2 */
spi-max-frequency = <1000>;
fpga = "spif"; /* Installed as /dev/spif */
config-size = <368011>;
nconfig-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; /* ,3:15 */
nstat-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* ,3:19 */
confd-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; /* ,3:18 */
crc-error-gpios= <&gpio2 1 GPIO_ACTIVE_HIGH>; /* ,2:01 */
partition@0 {
label = "spi-fpga";
reg = <0x000 0x8000>;
};
};
To configure the FPGA, you load the config info into RAM and write it to the
FPGA.
U-BOOT> mtd read spi1 ${loadaddr} 0 ${filesize} # read from SPI
U-BOOT> mtd write fpga0 ${loadaddr} 0 ${filesize} # configure FPGA
A driver will pulse the nCONFIG pin of the FPGA, do an SPI transfer
and then check the FPGA status outputs.
Since the MTD command set can be used (and is needed anyway)
the FPGA command set can be removed from the U-Boot both simplifying
the user interface and reducing code size of the u-boot image.
It relies on the (hopefully) existing SPI driver for the chip in u-boot
so it should be easy to use in most systems (as long as the H/W is designed for
it)
A linux driver, using the same principle would allow the FPGA to be
configured using a simple statement.
$ cat > /dev/fpga
The approach has been tested on a development board using an AM335x and 2 x
Cyclone 10.
The changes needed are
* adding the FPGA class in mtd-abi.h
* The "mtd" command hardwires the transfer to be RAW and no OOB.
* A driver wrapping the control signals around an SPI transfer
1.Claim SPI bus
2.Pulse nCONFIG low for 40 us,
3.Wait for nSTATUS high
4.Transfer bitstream using U-Boot SPI transfer
5.Release SPI bus
6.Wait until CONFIG_DONE (or error on nSTATUS)
[PATCH 1/4] include/mtd/mtd-abi.h: Add FPGA as MTD device
[PATCH 2/4] cmd/mtd.c: Support FPGAs in mtd command
[PATCH 3/4] mtd/fpga: add fpga directory to mtd (with Cyclone 10)
[PATCH 4/4] mtd/Kconfig,Makefile support FPGA
[PATCH 2/4] cmd/mtd.c: Support FPGAs in mtd command
From: Ulf Samuelsson
Signed-off-by: Ulf Samuelsson
---
cmd/mtd.c | 8
1 file changed, 8 insertions(+)
diff --git a/cmd/mtd.c b/cmd/mtd.c
index eb6e2d6892..09d5fdaa11 100644
--- a/cmd/mtd.c
+++ b/cmd/mtd.c
@@ -158,6 +158,9 @@ static void mtd_show_device(struct mtd_info *mtd)
case MTD_MLCNANDFLASH:
printf("MLC NAND flash\n");
break;
+ case MTD_FPGA:
+ printf("FPGA\n");
+ break;
case MTD_ABSENT:
default:
printf("Unknown\n");
@@ -275,6 +278,11 @@ static int do_mtd_io(struct cmd_tbl *cmdtp, int flag, int
argc,
raw = strstr(cmd, ".raw");
woob = strstr(cmd, ".oob");
write_empty_pages = !has_pages || strstr(cmd, ".dontskipff");
+ if (mtd->type == MTD_FPGA) {
+ raw = true;
+ woob = false;
+ write_empty_pages = true;
+ }
argc -= 2;
argv += 2;
--
2.17.1
[PATCH 1/4] include/mtd/mtd-abi.h: Add FPGA as MTD device
From: Ulf Samuelsson
Signed-off-by: Ulf Samuelsson
---
include/mtd/mtd-abi.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h
index ea244fbaeb..cd826b64dd 100644
--- a/include/mtd/mtd-abi.h
+++ b/include/mtd/mtd-abi.h
@@ -89,6 +89,7 @@ struct mtd_write_req {
#define MTD_DATAFLASH 6
#define MTD_UBIVOLUME 7
#define MTD_MLCNANDFLASH 8 /* MLC NAND (including TLC) */
+#defineMTD_FPGA9
#define MTD_WRITEABLE 0x400 /* Device is writeable */
#define MTD_BIT_WRITEABLE 0x800 /* Single bits can be flipped */
@@ -100,6 +101,7 @@ struct mtd_write_req {
#define MTD_CAP_RAM(MTD_WRITEABLE | MTD_BIT_WRITEABLE |
MTD_NO_ERASE)
#define MTD_CAP_NORFLASH (MTD_WRITEABLE | MTD_BIT_WRITEABLE)
#define MTD_CAP_NANDFLASH (MTD_WRITEABLE)
+#define MTD_CAP_FPGA (MTD_WRITEABLE | MTD_NO_ERASE)
/* Obsolete ECC byte placement modes (used with obsolete MEMGETOOBSEL) */
#define MTD_NANDECC_OFF0 // Switch off ECC (Not
recommended)
--
2.17.1
[PATCH 4/4] mtd/Kconfig,Makefile support FPGA
From: Ulf Samuelsson Signed-off-by: Ulf Samuelsson --- drivers/mtd/Kconfig | 2 ++ drivers/mtd/Makefile | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index af45ef00da..495211e314 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -238,6 +238,8 @@ config SYS_MAX_FLASH_BANKS_DETECT to reduce the effective number of flash bank, between 0 and CONFIG_SYS_MAX_FLASH_BANKS +source "drivers/mtd/fpga/Kconfig" + source "drivers/mtd/nand/Kconfig" config SYS_NAND_MAX_OOBFREE diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 3a78590aaa..d15ca24ec5 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -24,6 +24,7 @@ endif obj-y += nand/ obj-y += onenand/ obj-y += spi/ +obj-$(CONFIG_DM_SPI_FPGA) += fpga/ obj-$(CONFIG_MTD_UBI) += ubi/ #SPL/TPL build -- 2.17.1
[PATCH 3/4] mtd/fpga: add fpga directory to mtd (with Cyclone 10)
From: Ulf Samuelsson
Signed-off-by: Ulf Samuelsson
---
drivers/mtd/fpga/Kconfig | 47 ++
drivers/mtd/fpga/Makefile | 6 +
drivers/mtd/fpga/cyclone_10.c | 278 ++
3 files changed, 331 insertions(+)
create mode 100644 drivers/mtd/fpga/Kconfig
create mode 100644 drivers/mtd/fpga/Makefile
create mode 100644 drivers/mtd/fpga/cyclone_10.c
diff --git a/drivers/mtd/fpga/Kconfig b/drivers/mtd/fpga/Kconfig
new file mode 100644
index 00..e3aa8c4522
--- /dev/null
+++ b/drivers/mtd/fpga/Kconfig
@@ -0,0 +1,47 @@
+menu "SPI FPGA Support"
+
+config DM_SPI_FPGA
+ bool "Enable Driver Model for FPGA configuration"
+ depends on DM && DM_SPI
+ imply SPI_FPGA
+ help
+ Enable driver model for FPGAs configurable using SPI.
+ This SPI FPGA interface
+ (spi_fpga_probe(), spi_fpga_write(), etc.) is then
+ implemented by the SPI FPGA uclass.
+ There is one standard SPI FPGA driver which knows how to probe
+ chips supported by U-Boot. The uclass interface is defined in
+ include/spi_fpga.h
+ SPI and SPI FPGA must be enabled together
+ (it is not possible to use driver model for one and not the other).
+
+if DM_SPI_FPGA
+
+config SPI_FPGA_MTD
+ bool "SPI FPGA MTD support"
+ depends on MTD
+ help
+ Enable the MTD support for the FPGA SPI Passive Serial,
+ This allows mtd_write commands to load an FPGA using passive serial
+ If unsure, say N
+
+config SPI_FPGA_INTEL
+ bool "Intel/Altera FPGA Passive Serial configuration using SPI"
+ help
+ Add support for various Intel SPI FPGA chips
+
+config SPI_FPGA_XILINX
+ bool "Xilinx FPGA Passive Serial configuration using SPI"
+ help
+ Add support for various Xilinx FPGA chips
+
+config SPI_FPGA_CYCLONE10
+ bool "Cyclone 10 SPI FPGA MTD support"
+ depends on SPI_FPGA_MTD && SPI_FPGA_INTEL
+ help
+ Enable the MTD support for the Cyclone 10 FPGA
+ If unsure, say N
+
+endif
+
+endmenu # menu "SPI FPGA Support"
diff --git a/drivers/mtd/fpga/Makefile b/drivers/mtd/fpga/Makefile
new file mode 100644
index 00..2cf19fc7cf
--- /dev/null
+++ b/drivers/mtd/fpga/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+
+obj-$(CONFIG_SPI_FPGA_CYCLONE10) += cyclone_10.o
diff --git a/drivers/mtd/fpga/cyclone_10.c b/drivers/mtd/fpga/cyclone_10.c
new file mode 100644
index 00..41e273211e
--- /dev/null
+++ b/drivers/mtd/fpga/cyclone_10.c
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * MTD Driver for Passive Serial configuration of Cyclone 10
+ *
+ * Copyright (C) 2020 Bombardier Transportation
+ * Ulf Samuelsson
+ * Ulf Samuelsson
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+//#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * How many milliseconds from CONF_DONE high to enter user mode
+ * Datasheet says 650 us, Delay 2 ms to be safe...
+ */
+#defineUSER_MODE_DELAY 2
+
+struct cyc10_plat {
+ struct udevice *dev;
+ struct spi_slave*spi;
+ charname[8];
+ struct gpio_descnconfig;
+ struct gpio_descnstatus;
+ struct gpio_descconf_done;
+ struct gpio_desccrc_error;
+ u32 cs;
+ int flags;
+ int config_size;
+};
+
+static inline void write_nCONFIG(struct cyc10_plat *fpga, int value)
+{
+ dm_gpio_set_value(&fpga->nconfig, value);
+}
+
+static inline int read_nSTATUS(struct cyc10_plat *fpga)
+{
+ int val = dm_gpio_get_value(&fpga->nstatus);
+ if (val < 0) {
+ printf("%s: Failure reading nSTATUS; error=%d\n", fpga->name,
val);
+ }
+ return val;
+}
+
+static inline int read_CONFIG_DONE(struct cyc10_plat *fpga)
+{
+ int val = dm_gpio_get_value(&fpga->conf_done);
+ if (val < 0) {
+ printf("%s: Failure reading CONFIG_DONE; error=%d\n",
fpga->name, val);
+ }
+ return val;
+}
+
+static inline int read_CRC_ERROR(struct cyc10_plat *fpga)
+{
+ int val = dm_gpio_get_value(&fpga->crc_error);
+ if (val < 0) {
+ printf("%s: Failure reading CRC_ERROR; error=%d\n", fpga->name,
val);
+ }
+ return val;
+}
+
+/*
+ * Service routine to read status register until ready, or timeout occurs.
+ * Returns non-zero if error.
+ */
+static int cyc10_wait_until_conf_done(struct cyc10_plat *fpga)
+{
+ unsigned long timebase;
+
Re: [U-Boot] net/15
Synopsis: [U-Boot-Users] [Patch 1/1] Re-Submit: QE UEC: Add MII Commands State-Changed-From-To: feedback->closed State-Changed-By: BenWarren State-Changed-When: Fri, 08 Aug 2008 08:46:41 +0200 State-Changed-Why: Applied patch to net tree and requested pull to upstream ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/24: [PATCH] PHY: Add support for the M88E1121R Marvell chip.
Signed-off-by: Yuri Tikhonov <[EMAIL PROTECTED]>
Signed-off-by: Sergei Poselenov <[EMAIL PROTECTED]>
---
Added to GNATS database as unassigned-patches/24
>Responsible:patch-coord
>Message-Id: <[EMAIL PROTECTED]>
>In-Reply-To:
>References:
>Patch-Date: Fri Aug 15 15:42:08 +0200 2008
---
drivers/net/tsec.c | 50 ++
drivers/net/tsec.h |7 +++
2 files changed, 57 insertions(+), 0 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 6e0f2c6..fb5002d 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -1157,6 +1157,55 @@ struct phy_info phy_info_M88E1118 = {
},
};
+/*
+ * Since to access LED register we need do switch the page, we
+ * do LED configuring in the miim_read-like function as follows
+ */
+uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv)
+{
+ uint pg;
+
+ /* Switch the page to access the led register */
+ pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE);
+ write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE);
+
+ /* Configure leds */
+ write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL,
+ MIIM_88E1121_PHY_LED_DEF);
+
+ /* Restore the page pointer */
+ write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg);
+ return 0;
+}
+
+struct phy_info phy_info_M88E1121R = {
+ 0x01410cb,
+ "Marvell 88E1121R",
+ 4,
+ (struct phy_cmd[]){ /* config */
+ /* Reset and configure the PHY */
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+ {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+ /* Configure leds */
+ {MIIM_88E1121_PHY_LED_CTRL, miim_read,
+&mii_88E1121_set_led},
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ {MIIM_STATUS, miim_read, &mii_parse_link},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
+};
+
+
static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
{
uint mii_data = read_phy_reg(priv, mii_reg);
@@ -1522,6 +1571,7 @@ struct phy_info *phy_info[] = {
&phy_info_M88E1011S,
&phy_info_M88ES,
&phy_info_M88E1118,
+ &phy_info_M88E1121R,
&phy_info_M88E1145,
&phy_info_M88E1149S,
&phy_info_dm9161,
diff --git a/drivers/net/tsec.h b/drivers/net/tsec.h
index 6a2338b..fee5934 100644
--- a/drivers/net/tsec.h
+++ b/drivers/net/tsec.h
@@ -184,6 +184,13 @@
#define MIIM_88E_PHY_LED_DIRECT0x4100
#define MIIM_88E_PHY_LED_COMBINE 0x411C
+/* 88E1121 PHY LED Control Register */
+#define MIIM_88E1121_PHY_LED_CTRL 16
+#define MIIM_88E1121_PHY_LED_PAGE 3
+#define MIIM_88E1121_PHY_LED_DEF 0x0030
+
+#define MIIM_88E1121_PHY_PAGE 22
+
/* 88E1145 Extended PHY Specific Control Register */
#define MIIM_88E1145_PHY_EXT_CR 20
#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
--
1.5.6.1
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[U-Boot] unassigned-patches/23: [PATCH] RX 8025 RTC: analyze 12/24-hour mode flag in rtc_get().
Signed-off-by: Yuri Tikhonov <[EMAIL PROTECTED]> --- Added to GNATS database as unassigned-patches/23 >Responsible:patch-coord >Message-Id: <[EMAIL PROTECTED]> >In-Reply-To:<[EMAIL PROTECTED]> >References: <[EMAIL PROTECTED]> >Patch-Date: Fri Aug 15 15:42:09 +0200 2008 --- drivers/rtc/rx8025.c |6 +- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c index 64eafe5..6ba9df2 100644 --- a/drivers/rtc/rx8025.c +++ b/drivers/rtc/rx8025.c @@ -136,7 +136,11 @@ int rtc_get (struct rtc_time *tmp) tmp->tm_sec = bcd2bin (sec & 0x7F); tmp->tm_min = bcd2bin (min & 0x7F); - tmp->tm_hour = bcd2bin (hour & 0x3F); + if (rtc_read(RTC_CTL1_REG_ADDR) & RTC_CTL1_BIT_2412) + tmp->tm_hour = bcd2bin (hour & 0x3F); + else + tmp->tm_hour = bcd2bin (hour & 0x1F) % 12 + + ((hour & 0x20) ? 12 : 0); tmp->tm_mday = bcd2bin (mday & 0x3F); tmp->tm_mon = bcd2bin (mon & 0x1F); tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000); -- 1.5.6.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/25: [PATCH] USB EHCI: reset root hub
Some of multi-function USB controllers (e.g. ISP1562) allow root hub
resetting only via EHCI registers. So, this patch adds the corresponding
kind of reset to OHCI's hc_reset() if the newly introduced CONFIG_PCI_EHCI_DEVNO
option is set (e.g. for Socrates board).
Signed-off-by: Yuri Tikhonov <[EMAIL PROTECTED]>
---
Added to GNATS database as unassigned-patches/25
>Responsible:patch-coord
>Message-Id: <[EMAIL PROTECTED]>
>In-Reply-To:<[EMAIL PROTECTED]>
>References: <[EMAIL PROTECTED]> <[EMAIL PROTECTED]>
>Patch-Date: Fri Aug 15 15:42:10 +0200 2008
---
drivers/usb/usb_ohci.c | 31 +++
drivers/usb/usb_ohci.h |3 +++
include/configs/socrates.h |1 +
3 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/usb_ohci.c b/drivers/usb/usb_ohci.c
index fd60edb..0f5bd06 100644
--- a/drivers/usb/usb_ohci.c
+++ b/drivers/usb/usb_ohci.c
@@ -1571,11 +1571,42 @@ int submit_int_msg(struct usb_device *dev, unsigned
long pipe, void *buffer,
static int hc_reset (ohci_t *ohci)
{
+#ifdef CONFIG_PCI_EHCI_DEVNO
+ pci_dev_t pdev;
+ struct pci_device_id ehci_pci_ids[] = {
+ {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */
+ {0, 0}
+ };
+#endif
int timeout = 30;
int smm_timeout = 50; /* 0,5 sec */
dbg("%s\n", __FUNCTION__);
+#ifdef CONFIG_PCI_EHCI_DEVNO
+ /*
+* Some multi-function controllers (e.g. ISP1562) allow root hub
+* resetting via EHCI registers only.
+*/
+ pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO);
+ if (pdev != -1) {
+ u32 base;
+ int timeout = 1000;
+
+ pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
+ writel (readl(base + EHCI_USBCMD_OFF) | EHCI_USBCMD_HCRESET,
+ base + EHCI_USBCMD_OFF);
+
+ while (readl(base + EHCI_USBCMD_OFF) & EHCI_USBCMD_HCRESET) {
+ if (timeout-- <= 0) {
+ printf("USB RootHub reset timed out!");
+ break;
+ }
+ udelay(1);
+ }
+ } else
+ printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO);
+#endif
if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership
*/
info("USB HC TakeOver from SMM");
diff --git a/drivers/usb/usb_ohci.h b/drivers/usb/usb_ohci.h
index 380cb4c..7a04bf5 100644
--- a/drivers/usb/usb_ohci.h
+++ b/drivers/usb/usb_ohci.h
@@ -195,6 +195,9 @@ struct ohci_regs {
} roothub;
} __attribute((aligned(32)));
+/* Some EHCI controls */
+#define EHCI_USBCMD_OFF0x20
+#define EHCI_USBCMD_HCRESET(1 << 1)
/* OHCI CONTROL AND STATUS REGISTER MASKS */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 8a64942..fdc1557 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -403,6 +403,7 @@
#define CONFIG_USB_OHCI_NEW1
#define CONFIG_PCI_OHCI1
#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
+#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2)
#define CFG_USB_OHCI_MAX_ROOT_PORTS15
#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
#define CFG_OHCI_SWAP_REG_ACCESS 1
--
1.5.6.1
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[U-Boot] unassigned-patches/26: [PATCH] 85xx: socrates: Enable Lime support.
SET_TLB_ENTRY(1, CFG_LIME_BASE, CFG_LIME_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_64M, 1),
+
+ /*
* TLB 6: 64M Non-cacheable, guarded
* 0xe000_ 1M CCSRBAR
* 0xe200_ 16M PCI1 IO
diff --git a/board/socrates/upm_table.h b/board/socrates/upm_table.h
index ed8f887..2a89c96 100644
--- a/board/socrates/upm_table.h
+++ b/board/socrates/upm_table.h
@@ -52,4 +52,24 @@ static const unsigned int UPMTableA[] =
0xec00, 0xec00, 0xec00, 0xec01 /* Words 60 to 63
*/
};
+/* LIME UPM B Table Configuration Code */
+static unsigned int UPMTableB[] =
+{
+ 0x0ffefc00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3
*/
+ 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc04, 0x0c01, /* Words 4 to 7
*/
+ 0x0ffefc00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 8 to 11
*/
+ 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc04, 0x0ffcfc04, /* Words 12 to 15
*/
+ 0x0ffcfc04, 0x0ffcfc04, 0x0ffcfc04, 0x0ffcfc04, /* Words 16 to 19
*/
+ 0x0ffcfc04, 0x0ffcfc04, 0x0c00, 0xfc01, /* Words 20 to 23
*/
+ 0x0cfffc00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27
*/
+ 0x00fffc00, 0x00fffc00, 0x00fffc04, 0x0c01, /* Words 28 to 31
*/
+ 0x0cfffc00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 32 to 35
*/
+ 0x00fffc00, 0x00fffc00, 0x00fffc04, 0x00fffc04, /* Words 36 to 39
*/
+ 0x00fffc04, 0x00fffc04, 0x00fffc04, 0x00fffc04, /* Words 40 to 43
*/
+ 0x00fffc04, 0x00fffc04, 0x0c00, 0xfc01, /* Words 44 to 47
*/
+ 0xfc00, 0xfc00, 0xfc00, 0xfc00, /* Words 48 to 51
*/
+ 0xfc00, 0xfc00, 0xfc00, 0xfc00, /* Words 52 to 55
*/
+ 0xfc00, 0xfc00, 0xfc00, 0xfc01, /* Words 56 to 59
*/
+ 0xfc00, 0xfc00, 0xfc00, 0xfc01 /* Words 60 to 63
*/
+};
#endif
diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c
index 733d9a2..262963c 100644
--- a/drivers/video/mb862xx.c
+++ b/drivers/video/mb862xx.c
@@ -359,7 +359,8 @@ void *video_hw_init (void)
board_disp_init();
#endif
-#if defined(CONFIG_LWMON5) && !(CONFIG_POST & CFG_POST_SYSMON)
+#if (defined(CONFIG_LWMON5) || \
+ defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CFG_POST_SYSMON)
/* Lamp on */
board_backlight_switch (1);
#endif
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 43e0050..4c7308e 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -179,6 +179,26 @@
#define NAND_MAX_CHIPS 1
#define CONFIG_CMD_NAND
+/* LIME GDC */
+#define CFG_LIME_BASE 0xc800
+#define CFG_LIME_SIZE 0x0400 /* 64 MB*/
+#define CFG_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
+#define CFG_OR2_PRELIM 0xfc00 /* 64 MB*/
+
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_MB862xx
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define VIDEO_FB_16BPP_PIXEL_SWAP
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CFG_CONSOLE_IS_IN_ENV
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CFG_VIDEO_LOGO_MAX_SIZE(2 << 20) /* decompressed img */
+
/* Serial Port */
#define CONFIG_CONS_INDEX 1
@@ -221,6 +241,9 @@
#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
#define CFG_I2C_RTC_ADDR 0x32/* at address 0x32 */
+/* I2C W83782G HW-Monitoring IC */
+#define CFG_I2C_W83782G_ADDR 0x28/* W83782G address */
+
/* I2C temp sensor */
/* Socrates uses Maxim's DS75, which is compatible with LM75 */
#define CONFIG_DTT_LM751
@@ -317,6 +340,7 @@
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_BMP
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
--
1.5.6.1
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[U-Boot] unassigned-patches/22: [PATCH] Removed hardcoded MxMR loop value from upmconfig() for MPC85xx.
Signed-off-by: Sergei Poselenov <[EMAIL PROTECTED]>
---
Added to GNATS database as unassigned-patches/22
>Responsible:patch-coord
>Message-Id: <[EMAIL PROTECTED]>
>In-Reply-To:<[EMAIL PROTECTED]>
>References: <[EMAIL PROTECTED]> <[EMAIL PROTECTED]> <[EMAIL PROTECTED]>
>Patch-Date: Fri Aug 15 15:42:11 +0200 2008
---
cpu/mpc85xx/cpu.c | 16
1 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index bde8e56..eb041bb 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -288,16 +288,16 @@ int dma_xfer(void *dest, uint count, void *src) {
return dma_check();
}
#endif
+
/*
- * Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF)
- * are hardcoded as "1"."size" is the number or entries, not a sizeof.
+ * Configures a UPM. The function requires the respective MxMR to be set
+ * before calling this function. "size" is the number or entries, not a sizeof.
*/
void upmconfig (uint upm, uint * table, uint size)
{
int i, mdr, mad, old_mad = 0;
volatile u32 *mxmr;
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
- int loopval = 0x4440;
volatile u32 *brp,*orp;
volatile u8* dummy = NULL;
int upmmask;
@@ -325,8 +325,8 @@ void upmconfig (uint upm, uint * table, uint size)
i++, brp += 2, orp += 2) {
/* Look for a valid BR with selected UPM */
- if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) {
- dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT);
+ if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
+ dummy = (volatile u8*)(in_be32(brp) & BR_BA);
break;
}
}
@@ -338,7 +338,7 @@ void upmconfig (uint upm, uint * table, uint size)
for (i = 0; i < size; i++) {
/* 1 */
- out_be32(mxmr, loopval | 0x1000 | i); /* OP_WRITE */
+ out_be32(mxmr, (in_be32(mxmr) & 0x4fc0) | MxMR_OP_WARR |
i);
/* 2 */
out_be32(&lbc->mdr, table[i]);
/* 3 */
@@ -347,11 +347,11 @@ void upmconfig (uint upm, uint * table, uint size)
*(volatile u8 *)dummy = 0;
/* 5 */
do {
- mad = in_be32(mxmr) & 0x3f;
+ mad = in_be32(mxmr) & MxMR_MAD_MSK;
} while (mad <= old_mad && !(!mad && i == (size-1)));
old_mad = mad;
}
- out_be32(mxmr, loopval); /* OP_NORMAL */
+ out_be32(mxmr, (in_be32(mxmr) & 0x4fc0) | MxMR_OP_NORM);
}
#if defined(CONFIG_TSEC_ENET) || defined(CONFIGMPC85XX_FEC)
--
1.5.6.1
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[U-Boot] unassigned-patches/27: [PATCH] 85xx: Socrates: Major code update.
\
+ "ramdisk_addr=FE20\0" \
+ "fdt_addr_r=B0\0" \
+ "kernel_addr_r=20\0"\
+ "ramdisk_addr_r=40\0" \
+ "rootpath=/opt/eldk/ppc_85xxDP\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0"\
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0"\
+ "addcons=setenv bootargs $bootargs "\
+ "console=$consdev,$baudrate\0" \
"addip=setenv bootargs $bootargs " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
":$hostname:$netdev:off panic=1\0" \
- "addcons=setenv bootargs $bootargs "\
- "console=$consdev,$baudrate\0" \
- "flash_self=run ramargs addip addcons;" \
+ "boot_nor=run ramargs addcons;" \
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"\
- "flash_nfs=run nfsargs addip addcons;" \
- "bootm ${kernel_addr} - ${fdt_addr}\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
"tftp ${fdt_addr_r} ${fdt_file}; " \
"run nfsargs addip addcons;"\
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "fdt_file=$hostname/socrates.dtb\0" \
- "fdt_addr_r=B0\0" \
- "fdt_addr=FC1E\0" \
- "rootpath=/opt/eldk/ppc_85xxDP\0" \
- "kernel_addr=FC00\0"\
- "kernel_addr_r=20\0"\
- "ramdisk_addr=FC20\0" \
- "ramdisk_addr_r=40\0" \
- "load=tftp 10 $hostname/u-boot.bin\0" \
- "update=protect off fffc ;era fffc ;" \
- "cp.b 10 fffc 4;" \
+ "update_uboot=tftp 10 ${uboot_file};" \
+ "protect off fffa ;"\
+ "era fffa ;"\
+ "cp.b 10 fffa ${filesize};" \
+ "setenv filesize;saveenv\0" \
+ "update_kernel=tftp 10 ${bootfile};"\
+ "era fe00 fe1d;"\
+ "cp.b 10 fe00 ${filesize};" \
"setenv filesize;saveenv\0" \
- "upd=run load update\0" \
+ "update_fdt=tftp 10 ${fdt_file};" \
+ "era fe1e fe1f;"\
+ "cp.b 10 fe1e ${filesize};" \
+ "setenv filesize;saveenv\0" \
+ "update_initrd=tftp 10 ${initrd_file};" \
+ "era fe20 fe9f;"\
+ "cp.b 10 fe20 ${filesize};" \
+ "setenv filesize;saveenv\0" \
+ "clean_data=era fea0 fff5\0"\
+ "usbargs=setenv bootargs root=/dev/sda1 rw\0" \
+ "load_usb=usb start;" \
+ "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
+ "boot_usb=run load_usb usbargs addcons;"\
+ "bootm ${kernel_addr_r} - ${fdt_addr};" \
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"\
""
-#define CONFIG_BOOTCOMMAND "run flash_self"
+#define CONFIG_BOOTCOMMAND "run boot_nor"
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
@@ -410,14 +444,4 @@
#define CONFIG_DOS_PARTITION 1
#define CONFIG_USB_STORAGE 1
-/* FPGA and NAND */
-#define CFG_FPGA_BASE 0xc000
-#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
-#define CFG_OR3_PRELIM 0xfff0 /* 1 MB */
-
-#define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70)
-#define CFG_MAX_NAND_DEVICE1
-#define NAND_MAX_CHIPS 1
-#define CONFIG_CMD_NAND
-
#endif /* __CONFIG_H */
--
1.5.6.1
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Re: [U-Boot] net/25
Synopsis: [PATCH] USB EHCI: reset root hub Responsible-Changed-From-To: patch-coord->gu-net Responsible-Changed-By: dzu Responsible-Changed-When: Fri, 15 Aug 2008 15:51:19 +0200 Responsible-Changed-Why: Assign to custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] usb/25
Synopsis: [PATCH] USB EHCI: reset root hub Responsible-Changed-From-To: gu-net->gu-usb Responsible-Changed-By: dzu Responsible-Changed-When: Fri, 15 Aug 2008 15:52:01 +0200 Responsible-Changed-Why: Assign to correct custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mpc85xx/27
Synopsis: [PATCH] 85xx: Socrates: Major code update. Responsible-Changed-From-To: patch-coord->gu-mpc85xx Responsible-Changed-By: dzu Responsible-Changed-When: Fri, 15 Aug 2008 15:52:42 +0200 Responsible-Changed-Why: Assign to custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mpc85xx/22
Synopsis: [PATCH] Removed hardcoded MxMR loop value from upmconfig() for MPC85xx. Responsible-Changed-From-To: patch-coord->gu-mpc85xx Responsible-Changed-By: dzu Responsible-Changed-When: Fri, 15 Aug 2008 15:53:11 +0200 Responsible-Changed-Why: Assign to custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] net/24
Synopsis: [PATCH] PHY: Add support for the M88E1121R Marvell chip. Responsible-Changed-From-To: patch-coord->gu-net Responsible-Changed-By: dzu Responsible-Changed-When: Fri, 15 Aug 2008 15:53:42 +0200 Responsible-Changed-Why: Assign to custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mpc85xx/26
Synopsis: [PATCH] 85xx: socrates: Enable Lime support. Responsible-Changed-From-To: patch-coord->gu-mpc85xx Responsible-Changed-By: dzu Responsible-Changed-When: Fri, 15 Aug 2008 15:54:24 +0200 Responsible-Changed-Why: Assign to custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] common/23
Synopsis: [PATCH] RX 8025 RTC: analyze 12/24-hour mode flag in rtc_get(). Responsible-Changed-From-To: patch-coord->wd Responsible-Changed-By: dzu Responsible-Changed-When: Fri, 15 Aug 2008 16:23:20 +0200 Responsible-Changed-Why: Assign to prokect lead ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] unassigned-patches/8
Synopsis: [U-Boot-Users] [PATCH] I2C Monitor chip ADT7460 support State-Changed-From-To: open->closed State-Changed-By: dzu State-Changed-When: Mon, 01 Sep 2008 15:43:30 +0200 State-Changed-Why: Applied in commit d0039d4ed275e6ca09fb417895024ad02be118c4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] net/24
Synopsis: [PATCH] PHY: Add support for the M88E1121R Marvell chip. State-Changed-From-To: open->closed State-Changed-By: wd State-Changed-When: Wed, 03 Sep 2008 22:52:57 +0200 State-Changed-Why: Applied by commit d23dc394aa69093b6326ad917db04dc0d1aff3f8 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] common/23
Synopsis: [PATCH] RX 8025 RTC: analyze 12/24-hour mode flag in rtc_get(). State-Changed-From-To: open->closed State-Changed-By: wd State-Changed-When: Sat, 06 Sep 2008 01:23:16 +0200 State-Changed-Why: Applied as commit 5875d358f025c1b042d8a0f08384b756de7256c9 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] usb/25
Synopsis: [PATCH] USB EHCI: reset root hub State-Changed-From-To: open->closed State-Changed-By: wd State-Changed-When: Sat, 06 Sep 2008 01:26:27 +0200 State-Changed-Why: Applied (slightly modified) as commit e90fb6afab2c0c074dfb67bacb4de179eb188a24 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mpc85xx/14
Synopsis: [U-Boot-Users] [PATCH] Update Freescale 85xx boards to sys_eeprom.c State-Changed-From-To: open->closed State-Changed-By: AndyFleming State-Changed-When: Tue, 09 Sep 2008 03:53:16 +0200 State-Changed-Why: Applied ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mpc85xx/22
Synopsis: [PATCH] Removed hardcoded MxMR loop value from upmconfig() for MPC85xx. State-Changed-From-To: open->closed State-Changed-By: AndyFleming State-Changed-When: Tue, 09 Sep 2008 03:54:12 +0200 State-Changed-Why: Applied, with fuzz ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mpc85xx/26
Synopsis: [PATCH] 85xx: socrates: Enable Lime support. State-Changed-From-To: open->closed State-Changed-By: AndyFleming State-Changed-When: Tue, 09 Sep 2008 03:54:51 +0200 State-Changed-Why: Applied, thanks ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mpc85xx/27
Synopsis: [PATCH] 85xx: Socrates: Major code update. State-Changed-From-To: open->closed State-Changed-By: AndyFleming State-Changed-When: Tue, 09 Sep 2008 03:55:20 +0200 State-Changed-Why: applied, thanks ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/30: [PATCH] 85xx: socrates: Add support for new image format.
Signed-off-by: Detlev Zundel <[EMAIL PROTECTED]>
---
Added to GNATS database as unassigned-patches/30
>Responsible:patch-coord
>Message-Id: <[EMAIL PROTECTED]>
>In-Reply-To:<[EMAIL PROTECTED]>
>References: <[EMAIL PROTECTED]>
>Patch-Date: Thu Sep 11 15:34:58 +0200 2008
---
include/configs/socrates.h |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index a981a8f..94124cd 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -33,6 +33,11 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+/* new uImage format support */
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
+
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE*/
#define CONFIG_E5001 /* BOOKE e500 family*/
--
1.5.6.1
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[U-Boot] unassigned-patches/31: [PATCH] 85xx: socrates: autoprobe Lime chip
This patch is an attempt to implement autoprobing for the Lime
presence on the bus.
Configure GPCM for Lime CS2 and try to access chip ID registers.
Second read atempt delivers register values if the chip is present.
Signed-off-by: Anatolij Gustschin <[EMAIL PROTECTED]>
---
Added to GNATS database as unassigned-patches/31
>Responsible:patch-coord
>Message-Id: <[EMAIL PROTECTED]>
>In-Reply-To:
>References:
>Patch-Date: Thu Sep 11 15:34:57 +0200 2008
---
board/socrates/socrates.c | 58 +---
1 files changed, 43 insertions(+), 15 deletions(-)
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 73a2d9d..b9d9f08 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -36,12 +36,15 @@
#include
#include
#include
-
+#include
+#include
+#include
#include "upm_table.h"
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[]; /* FLASH chips info */
+extern GraphicDevice mb862xx;
void local_bus_init (void);
ulong flash_get_size (ulong base, int banknum);
@@ -174,11 +177,9 @@ void local_bus_init (void)
out_be32 (&lbc->mamr, 0x0); /* Use a customer-supplied value */
upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
- if (getenv("lime")) {
- /* Init UPMB for Lime controller access */
- out_be32 (&lbc->mbmr, 0x40); /* Use a customer-supplied
value */
- upmconfig (UPMB, (uint *)UPMTableB,
sizeof(UPMTableB)/sizeof(int));
- }
+ /* Init UPMB for Lime controller access */
+ out_be32 (&lbc->mbmr, 0x40); /* Use a customer-supplied value */
+ upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
}
#if defined(CONFIG_PCI)
@@ -245,7 +246,7 @@ ft_board_setup(void *blob, bd_t *bd)
val[i++] = gd->bd->bi_flashstart;
val[i++] = gd->bd->bi_flashsize;
- if (getenv("lime")) {
+ if (mb862xx.frameAdrs == CFG_LIME_BASE) {
/* Fixup LIME mapping */
val[i++] = 2; /* chip select number */
val[i++] = 0; /* always 0 */
@@ -267,10 +268,6 @@ ft_board_setup(void *blob, bd_t *bd)
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-#include
-#include
-#include
-
#define CFG_LIME_SRST ((CFG_LIME_BASE) + 0x01FC002C)
#define CFG_LIME_CCF ((CFG_LIME_BASE) + 0x01FC0038)
#define CFG_LIME_MMR ((CFG_LIME_BASE) + 0x01FCFFFC)
@@ -285,8 +282,6 @@ ft_board_setup(void *blob, bd_t *bd)
#define DEFAULT_BRIGHTNESS 25
#define BACKLIGHT_ENABLE (1 << 31)
-extern GraphicDevice mb862xx;
-
static const gdc_regs init_regs [] =
{
{0x0100, 0x00010f00},
@@ -313,11 +308,44 @@ const gdc_regs *board_get_regs (void)
return init_regs;
}
+#define CFG_LIME_CID ((CFG_LIME_BASE) + 0x01FC00F0)
+#define CFG_LIME_REV ((CFG_LIME_BASE) + 0x01FF8084)
+int lime_probe(void)
+{
+ volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
+ uint cfg_br2;
+ uint cfg_or2;
+ uint reg;
+
+ cfg_br2 = memctl->br2;
+ cfg_or2 = memctl->or2;
+
+ /* Configure GPCM for CS2 */
+ memctl->br2 = 0;
+ memctl->or2 = 0xfc000410;
+ memctl->br2 = (CFG_LIME_BASE) | 0x1901;
+
+ /* Try to access GDC ID/Revision registers */
+ reg = in_be32((void *)CFG_LIME_CID);
+ reg = in_be32((void *)CFG_LIME_CID);
+ if (reg == 0x303) {
+ reg = in_be32((void *)CFG_LIME_REV);
+ reg = in_be32((void *)CFG_LIME_REV);
+ reg = ((reg & ~0xff) == 0x20050100) ? 1 : 0;
+ } else
+ reg = 0;
+
+ /* Restore previous CS2 configuration */
+ memctl->br2 = 0;
+ memctl->or2 = cfg_or2;
+ memctl->br2 = cfg_br2;
+ return reg;
+}
+
/* Returns Lime base address */
unsigned int board_video_init (void)
{
-
- if (!getenv("lime"))
+ if (!lime_probe())
return 0;
/*
--
1.5.6.1
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Re: [U-Boot] mpc85xx/30
Synopsis: [PATCH] 85xx: socrates: Add support for new image format. Responsible-Changed-From-To: patch-coord->gu-mpc85xx Responsible-Changed-By: dzu Responsible-Changed-When: Thu, 11 Sep 2008 15:42:46 +0200 Responsible-Changed-Why: Assign to custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mpc85xx/31
Synopsis: [PATCH] 85xx: socrates: autoprobe Lime chip Responsible-Changed-From-To: patch-coord->gu-mpc85xx Responsible-Changed-By: dzu Responsible-Changed-When: Thu, 11 Sep 2008 15:43:18 +0200 Responsible-Changed-Why: Assign to custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mpc85xx/30
Synopsis: [PATCH] 85xx: socrates: Add support for new image format. State-Changed-From-To: open->closed State-Changed-By: wd State-Changed-When: Sat, 13 Sep 2008 02:09:41 +0200 State-Changed-Why: Applied as commit e99b607a5ec56ce66e0bcccb78480d5e16fb7bc5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mpc85xx/31
Synopsis: [PATCH] 85xx: socrates: autoprobe Lime chip State-Changed-From-To: open->closed State-Changed-By: wd State-Changed-When: Sat, 13 Sep 2008 02:10:19 +0200 State-Changed-Why: Applied as commit fb661ea444ae61de60520f66ae84cdb5dd5a3246 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/128: [PATCH] x86: minnowmax: add GPIO mapping support
Configure the pinctrl as it required to make some IO controllers
working (USB/UART/I2C/...).
The idea would be in the next version to modify the pch GPIO driver and
configure these pins through the device tree.
These modifications are ported from the coreboot project.
Signed-off-by: Gabriel Huau
---
Added to GNATS database as unassigned-patches/128
>Responsible:patch-coord
>Message-Id: <1424037328-31636-1-git-send-email-cont...@huau-gabriel.fr>
>In-Reply-To:
>References:
>Patch-Date: Sun Feb 15 22:55:28 +0100 2015
---
arch/x86/cpu/baytrail/Makefile| 1 +
arch/x86/cpu/baytrail/gpio.c | 206 +++
arch/x86/include/asm/arch-baytrail/gpio.h | 364 ++
arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++
arch/x86/include/asm/arch-baytrail/irq.h | 119 +
arch/x86/include/asm/arch-baytrail/irqroute.h | 67 +
arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++
arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++
board/intel/minnowmax/minnowmax.c | 212 +++
include/configs/minnowmax.h | 11 +
10 files changed, 1450 insertions(+)
create mode 100644 arch/x86/cpu/baytrail/gpio.c
create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h
create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h
create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h
create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h
create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h
diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
index 8914e8b..c20a616 100644
--- a/arch/x86/cpu/baytrail/Makefile
+++ b/arch/x86/cpu/baytrail/Makefile
@@ -8,3 +8,4 @@ obj-y += early_uart.o
obj-y += fsp_configs.o
obj-y += pci.o
obj-y += valleyview.o
+obj-y += gpio.o
diff --git a/arch/x86/cpu/baytrail/gpio.c b/arch/x86/cpu/baytrail/gpio.c
new file mode 100644
index 000..0ad41cc
--- /dev/null
+++ b/arch/x86/cpu/baytrail/gpio.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* GPIO-to-Pad LUTs */
+static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = {
+ 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */
+ 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */
+ 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */
+ 2, 5, 9 /* [24:26] */
+};
+
+static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = {
+ 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */
+ 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */
+ 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */
+ 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */
+ 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */
+ 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */
+ 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */
+ 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */
+ 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */
+ 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */
+ 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */
+ 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */
+ 106, 87, 91, 104, 97, 100 /* [96:101] */
+};
+
+static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = {
+ 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */
+ 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */
+ 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */
+ 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */
+ 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */
+ 52, 53, 59, 40 /* [40:43] */
+};
+
+/* GPIO bank descriptions */
+static const struct gpio_bank gpncore_bank = {
+ .gpio_count = GPNCORE_COUNT,
+ .gpio_to_pad = gpncore_gpio_to_pad,
+ .legacy_base = GP_LEGACY_BASE_NONE,
+ .pad_base = GPNCORE_PAD_BASE,
+ .has_wake_en = 0,
+ .gpio_f1_range_start = GPNCORE_GPIO_F1_RANGE_START,
+ .gpio_f1_range_end = GPNCORE_GPIO_F1_RANGE_END,
+};
+
+static const struct gpio_bank gpscore_bank = {
+ .gpio_count = GPSCORE_COUNT,
+ .gpio_to_pad = gpscore_gpio_to_pad,
+ .legacy_base = GPSCORE_LEGACY_BASE,
+ .pad_base = GPSCORE_PAD_BASE,
+ .has_wake_en = 0,
+ .gpio_f1_range_start = GPSCORE_GPIO_F1_RANGE_START,
+ .gpio_f1_range_end = GPSCORE_GPIO_F1_RANGE_END,
+};
+
+static const struct gpio_bank gpssus_bank = {
+ .gpio_count = GPSSUS_COUNT,
+ .gpio_to_pad = gpssus_gpio_to_pad,
+ .legacy_base = GPSSUS_LEGACY_BASE,
+ .pad_base = GPSSUS_PAD_BASE,
+ .has_wake_en = 1,
+ .gpio_f1_range_start = GPSSUS_GPIO_F1_RANGE_START,
+ .gpio_f1_range_end = GPSSUS_GPIO_F1_RANGE_END,
+};
+
+static void setup_gpios(const struct byt_gpio_ma
[U-Boot] unassigned-patches/131: Re: [PATCH] x86: minnowmax: add GPIO mapping support
Hi Gabriel,
On 15 February 2015 at 14:55, Gabriel Huau wrote:
> Configure the pinctrl as it required to make some IO controllers
> working (USB/UART/I2C/...).
> The idea would be in the next version to modify the pch GPIO driver and
> configure these pins through the device tree.
>
> These modifications are ported from the coreboot project.
>
> Signed-off-by: Gabriel Huau
Thanks for the patch!
I have mostly nits except for one comment about register access which
is different in U-Boot...
> ---
> arch/x86/cpu/baytrail/Makefile| 1 +
> arch/x86/cpu/baytrail/gpio.c | 206 +++
> arch/x86/include/asm/arch-baytrail/gpio.h | 364
> ++
> arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++
> arch/x86/include/asm/arch-baytrail/irq.h | 119 +
> arch/x86/include/asm/arch-baytrail/irqroute.h | 67 +
> arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++
> arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++
> board/intel/minnowmax/minnowmax.c | 212 +++
> include/configs/minnowmax.h | 11 +
> 10 files changed, 1450 insertions(+)
> create mode 100644 arch/x86/cpu/baytrail/gpio.c
> create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h
> create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h
> create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h
> create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h
> create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h
>
> diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
> index 8914e8b..c20a616 100644
> --- a/arch/x86/cpu/baytrail/Makefile
> +++ b/arch/x86/cpu/baytrail/Makefile
> @@ -8,3 +8,4 @@ obj-y += early_uart.o
> obj-y += fsp_configs.o
> obj-y += pci.o
> obj-y += valleyview.o
> +obj-y += gpio.o
Please keep in alphabetical order.
> diff --git a/arch/x86/cpu/baytrail/gpio.c b/arch/x86/cpu/baytrail/gpio.c
> new file mode 100644
> index 000..0ad41cc
> --- /dev/null
> +++ b/arch/x86/cpu/baytrail/gpio.c
> @@ -0,0 +1,206 @@
> +/*
> + * Copyright (c) 2012 The Chromium OS Authors.
Please add 'From coreboot ' here so people know where it came from.
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* GPIO-to-Pad LUTs */
> +static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = {
> + 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */
> + 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */
> + 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */
> + 2, 5, 9 /* [24:26] */
> +};
> +
> +static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = {
> + 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */
> + 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */
> + 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */
> + 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */
> + 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */
> + 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */
> + 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */
> + 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */
> + 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */
> + 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */
> + 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */
> + 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */
> + 106, 87, 91, 104, 97, 100 /* [96:101] */
> +};
> +
> +static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = {
> + 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */
> + 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */
> + 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */
> + 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */
> + 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */
> + 52, 53, 59, 40 /* [40:43] */
> +};
The above three tables are not quite lined up, but it looks like that
was your intention.
> +
> +/* GPIO bank descriptions */
> +static const struct gpio_bank gpncore_bank = {
> + .gpio_count = GPNCORE_COUNT,
> + .gpio_to_pad = gpncore_gpio_to_pad,
> + .legacy_base = GP_LEGACY_BASE_NONE,
> + .pad_base = GPNCORE_PAD_BASE,
> + .has_wake_en = 0,
> + .gpio_f1_range_start = GPNCORE_GPIO_F1_RANGE_START,
> + .gpio_f1_range_end = GPNCORE_GPIO_F1_RANGE_END,
> +};
> +
> +static const struct gpio_bank gpscore_bank = {
> + .gpio_count = GPSCORE_C
[U-Boot] unassigned-patches/139: [PATCH 1/4] x86: baytrail: fix the GPIOBASE address
Signed-off-by: Gabriel Huau --- Added to GNATS database as unassigned-patches/139 >Responsible:patch-coord >Message-Id: <1429805775-1809-2-git-send-email-cont...@huau-gabriel.fr> >In-Reply-To:<1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr> >References: <1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr> >Patch-Date: Thu Apr 23 18:16:12 +0200 2015 --- arch/x86/include/asm/arch-baytrail/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h index ab4e059..4e8987c 100644 --- a/arch/x86/include/asm/arch-baytrail/gpio.h +++ b/arch/x86/include/asm/arch-baytrail/gpio.h @@ -8,6 +8,6 @@ #define _X86_ARCH_GPIO_H_ /* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x44 +#define PCI_CFG_GPIOBASE 0x48 #endif /* _X86_ARCH_GPIO_H_ */ -- 2.1.4 ___________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/140: [PATCH 2/4] x86: minnowmax: add GPIO banks in the device tree
There is 6 banks:
4 banks for CORE: available in S0 mode
2 banks for SUS (Suspend): available in S0-S5 mode
Signed-off-by: Gabriel Huau
---
Added to GNATS database as unassigned-patches/140
>Responsible:patch-coord
>Message-Id: <1429805775-1809-3-git-send-email-cont...@huau-gabriel.fr>
>In-Reply-To:<1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr>
>References: <1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr>
>Patch-Date: Thu Apr 23 18:16:13 +0200 2015
---
arch/x86/dts/minnowmax.dts | 42 ++
1 file changed, 42 insertions(+)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 8f34369..c73e421 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -21,6 +21,48 @@
silent_console = <0>;
};
+ gpioa {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0 0x20>;
+ bank-name = "A";
+ };
+
+ gpiob {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x20 0x20>;
+ bank-name = "B";
+ };
+
+ gpioc {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x40 0x20>;
+ bank-name = "C";
+ };
+
+ gpiod {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x60 0x20>;
+ bank-name = "D";
+ };
+
+ gpioe {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x80 0x20>;
+ bank-name = "E";
+ };
+
+ gpiof {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0xA0 0x20>;
+ bank-name = "F";
+ };
+
chosen {
stdout-path = "/serial";
};
--
2.1.4
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[U-Boot] unassigned-patches/138: [PATCH 3/4] x86: gpio: add pinctrl support from the device tree
A set of properties has been defined for the device tree to select for
each pin the pull/func/default output configuration.
The offset for the PAD needs to be provided and if a GPIO needs to be
configured, his offset needs to be provided as well.
Here is an example:
pin_usb_host_en0@0 {
gpio-offset = <0x80 8>;
pad-offset = <0x260>;
mode-gpio;
output-value = <1>;
direction = ;
};
Signed-off-by: Gabriel Huau
---
Added to GNATS database as unassigned-patches/138
>Responsible:patch-coord
>Message-Id: <1429805775-1809-4-git-send-email-cont...@huau-gabriel.fr>
>In-Reply-To:<1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr>
>References: <1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr>
>Patch-Date: Thu Apr 23 18:16:14 +0200 2015
---
arch/x86/dts/minnowmax.dts| 21 +++
arch/x86/include/asm/arch-baytrail/gpio.h | 1 +
arch/x86/include/asm/gpio.h | 1 +
drivers/gpio/intel_ich6_gpio.c| 222 ++
include/dt-bindings/gpio/gpio.h | 20 +++
5 files changed, 239 insertions(+), 26 deletions(-)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index c73e421..3936e21 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include
+
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
@@ -21,6 +23,25 @@
silent_console = <0>;
};
+ pch_pinctrl {
+ compatible = "intel,ich6-pinctrl";
+ pin_usb_host_en0@0 {
+ gpio-offset = <0x80 8>;
+ pad-offset = <0x260>;
+ mode-gpio;
+ output-value = <1>;
+ direction = ;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = <0x80 9>;
+ pad-offset = <0x258>;
+ mode-gpio;
+ output-value = <1>;
+ direction = ;
+ };
+ };
+
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h
b/arch/x86/include/asm/arch-baytrail/gpio.h
index 4e8987c..85a65a8 100644
--- a/arch/x86/include/asm/arch-baytrail/gpio.h
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -9,5 +9,6 @@
/* Where in config space is the register that points to the GPIO registers? */
#define PCI_CFG_GPIOBASE 0x48
+#define PCI_CFG_IOBASE 0x4c
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7e679a0..a110d5b 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -44,21 +44,32 @@ struct ich6_bank_priv {
uint16_t lvl;
};
+#define GPIO_USESEL_OFFSET(x) (x)
+#define GPIO_IOSEL_OFFSET(x) (x + 4)
+#define GPIO_LVL_OFFSET(x) (x + 8)
+
+#define IOPAD_MODE_MASK0x7
+#define IOPAD_PULL_ASSIGN_MASK 0x3
+#define IOPAD_PULL_ASSIGN_SHIFT7
+#define IOPAD_PULL_STRENGTH_MASK 0x3
+#define IOPAD_PULL_STRENGTH_SHIFT 9
+
+static int __ich6_gpio_set_value(uint16_t base, unsigned offset, int value);
+static int __ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir);
+static int __ich6_gpio_set_function(uint16_t base, unsigned offset, int func);
+
/* TODO: Move this to device tree, or platform data */
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
{
gd->arch.gpio_map = map;
}
-static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
+static int gpio_ich6_get_base(unsigned long base)
{
- struct ich6_bank_platdata *plat = dev_get_platdata(dev);
pci_dev_t pci_dev; /* handle for 0:1f:0 */
u8 tmpbyte;
u16 tmpword;
u32 tmplong;
- u16 gpiobase;
- int offset;
/* Where should it be? */
pci_dev = PCI_BDF(0, 0x1f, 0);
@@ -123,9 +134,9 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
* while on the Ivybridge the bit0 is used to indicate it is an
* I/O space.
*/
- tmplong = x86_pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
+ tmplong = x86_pci_read_config32(pci_dev, base);
if (tmplong == 0x || tmplong == 0x) {
- debug(&quo
[U-Boot] unassigned-patches/141: [PATCH] x86: minnowmax: use the correct NOR in the configuration
The SPI NOR on the minnowboard max is a MICRON N25Q064A
Signed-off-by: Gabriel Huau
---
Added to GNATS database as unassigned-patches/141
>Responsible:patch-coord
>Message-Id: <1429805814-1892-1-git-send-email-cont...@huau-gabriel.fr>
>In-Reply-To:
>References:
>Patch-Date: Thu Apr 23 18:16:54 +0200 2015
---
include/configs/minnowmax.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 3c7b266..72393fa 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -43,7 +43,7 @@
#define CONFIG_SCSI_DEV_LIST\
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
-#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MMC
#define CONFIG_SDHCI
--
2.1.4
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[U-Boot] unassigned-patches/143: [PATCH 4/4] x86: minnowmax: initialize the pin-muxing from device tree
Signed-off-by: Gabriel Huau
---
Added to GNATS database as unassigned-patches/143
>Responsible:patch-coord
>Message-Id: <1429805775-1809-5-git-send-email-cont...@huau-gabriel.fr>
>In-Reply-To:<1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr>
>References: <1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr>
>Patch-Date: Thu Apr 23 18:16:15 +0200 2015
---
board/intel/minnowmax/minnowmax.c | 9 +
include/configs/minnowmax.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/board/intel/minnowmax/minnowmax.c
b/board/intel/minnowmax/minnowmax.c
index 6e82b16..60dd2bb 100644
--- a/board/intel/minnowmax/minnowmax.c
+++ b/board/intel/minnowmax/minnowmax.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include
#include
@@ -14,6 +15,14 @@
DECLARE_GLOBAL_DATA_PTR;
+int arch_early_init_r(void)
+{
+ /* do the pin-muxing */
+ gpio_ich6_pinctrl_init();
+
+ return 0;
+}
+
int board_early_init_f(void)
{
lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 823e051..3c7b266 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -15,6 +15,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_NR_DRAM_BANKS 1
--
2.1.4
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[U-Boot] unassigned-patches/142: [PATCH 0/4] x86: support of pin-muxing from device tree
This serie of patches adds the support of pin-muxing from the device tree through different properties. I have put two example to enable the USB Host on the minnowboard max. The support of the call to 'setup_pch_gpios' is still supported and only the minnowboard has been tested with the device tree implementation. Because the GPIO and IO base register ares different, I have also defined some proxy function to set the function/value and direction of the GPIO as the GPIO register can override some registers in the IO. Gabriel Huau (4): x86: baytrail: fix the GPIOBASE address x86: minnowmax: add GPIO banks in the device tree x86: gpio: add pinctrl support from the device tree x86: minnowmax: initialize the pin-muxing from device tree arch/x86/dts/minnowmax.dts| 63 + arch/x86/include/asm/arch-baytrail/gpio.h | 3 +- arch/x86/include/asm/gpio.h | 1 + board/intel/minnowmax/minnowmax.c | 9 ++ drivers/gpio/intel_ich6_gpio.c| 222 ++ include/configs/minnowmax.h | 1 + include/dt-bindings/gpio/gpio.h | 20 +++ 7 files changed, 292 insertions(+), 27 deletions(-) -- 2.1.4 --- Added to GNATS database as unassigned-patches/142 >Responsible:patch-coord >Message-Id: <1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr> >In-Reply-To: >References: >Patch-Date: Thu Apr 23 18:16:11 +0200 2015 _______ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/144: Re: [PATCH 3/4] x86: gpio: add pinctrl support from the device tree
Hi,
On 23 April 2015 at 10:16, Gabriel Huau wrote:
> A set of properties has been defined for the device tree to select for
> each pin the pull/func/default output configuration.
>
> The offset for the PAD needs to be provided and if a GPIO needs to be
> configured, his offset needs to be provided as well.
>
> Here is an example:
> pin_usb_host_en0@0 {
> gpio-offset = <0x80 8>;
> pad-offset = <0x260>;
> mode-gpio;
> output-value = <1>;
> direction = ;
> };
>
> Signed-off-by: Gabriel Huau
> ---
> arch/x86/dts/minnowmax.dts| 21 +++
> arch/x86/include/asm/arch-baytrail/gpio.h | 1 +
> arch/x86/include/asm/gpio.h | 1 +
> drivers/gpio/intel_ich6_gpio.c| 222
> ++
> include/dt-bindings/gpio/gpio.h | 20 +++
> 5 files changed, 239 insertions(+), 26 deletions(-)
>
> diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
> index c73e421..3936e21 100644
> --- a/arch/x86/dts/minnowmax.dts
> +++ b/arch/x86/dts/minnowmax.dts
> @@ -6,6 +6,8 @@
>
> /dts-v1/;
>
> +#include
> +
> /include/ "skeleton.dtsi"
> /include/ "serial.dtsi"
>
> @@ -21,6 +23,25 @@
> silent_console = <0>;
> };
>
> + pch_pinctrl {
> + compatible = "intel,ich6-pinctrl";
Make sure you use tabs for indenting here.
You should create a binding file to describe your binding - in
doc/device-tree-bindings.
> + pin_usb_host_en0@0 {
> + gpio-offset = <0x80 8>;
> + pad-offset = <0x260>;
> + mode-gpio;
> + output-value = <1>;
> + direction = ;
> + };
> +
> + pin_usb_host_en1@0 {
> + gpio-offset = <0x80 9>;
> + pad-offset = <0x258>;
> + mode-gpio;
> + output-value = <1>;
> + direction = ;
> + };
> + };
> +
> gpioa {
> compatible = "intel,ich6-gpio";
> u-boot,dm-pre-reloc;
> diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h
> b/arch/x86/include/asm/arch-baytrail/gpio.h
> index 4e8987c..85a65a8 100644
> --- a/arch/x86/include/asm/arch-baytrail/gpio.h
> +++ b/arch/x86/include/asm/arch-baytrail/gpio.h
> @@ -9,5 +9,6 @@
>
> /* Where in config space is the register that points to the GPIO registers?
> */
> #define PCI_CFG_GPIOBASE 0x48
> +#define PCI_CFG_IOBASE 0x4c
>
> #endif /* _X86_ARCH_GPIO_H_ */
> diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
> index 1099427..ed85b08 100644
> --- a/arch/x86/include/asm/gpio.h
> +++ b/arch/x86/include/asm/gpio.h
> @@ -147,6 +147,7 @@ struct pch_gpio_map {
> } set3;
> };
>
> +int gpio_ich6_pinctrl_init(void);
> void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
> void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
>
> diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
> index 7e679a0..a110d5b 100644
> --- a/drivers/gpio/intel_ich6_gpio.c
> +++ b/drivers/gpio/intel_ich6_gpio.c
> @@ -44,21 +44,32 @@ struct ich6_bank_priv {
> uint16_t lvl;
> };
>
> +#define GPIO_USESEL_OFFSET(x) (x)
> +#define GPIO_IOSEL_OFFSET(x) (x + 4)
> +#define GPIO_LVL_OFFSET(x) (x + 8)
Comments on the above
> +
> +#define IOPAD_MODE_MASK0x7
> +#define IOPAD_PULL_ASSIGN_MASK 0x3
> +#define IOPAD_PULL_ASSIGN_SHIFT7
Can you make the mask value an actual valid mask, like:
+#define IOPAD_PULL_ASSIGN_MASK (0x3 << IOPAD_PULL_ASSIGN_SHIFT)
> +#define IOPAD_PULL_STRENGTH_MASK 0x3
> +#define IOPAD_PULL_STRENGTH_SHIFT 9
> +
> +static int __ich6_gpio_set_value(uint16_t base, unsigned offset, int value);
Can you reorder the functions to avoid the need for these forward
declarations? Also only one underscore prefix please.
> +static int __ich6_gpio_set_direction(uint16_t base, unsigned offset, int
> dir);
> +static int __ich6_gpio_set_function(uint16_t base, unsigned offset, int
> func);
> +
> /* TODO: Move this to device tree, or platform data */
> void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
> {
> gd->arch.gpio_map = map;
> }
>
> -static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
> +static int gpio_ich6_get_base(unsigned long base)
> {
> - struct ich6_bank_platdata *p
[U-Boot] unassigned-patches/145: Re: [PATCH 4/4] x86: minnowmax: initialize the pin-muxing from device tree
Hi Grabriel,
On 23 April 2015 at 10:16, Gabriel Huau wrote:
> Signed-off-by: Gabriel Huau
> ---
> board/intel/minnowmax/minnowmax.c | 9 +
> include/configs/minnowmax.h | 1 +
> 2 files changed, 10 insertions(+)
>
> diff --git a/board/intel/minnowmax/minnowmax.c
> b/board/intel/minnowmax/minnowmax.c
> index 6e82b16..60dd2bb 100644
> --- a/board/intel/minnowmax/minnowmax.c
> +++ b/board/intel/minnowmax/minnowmax.c
> @@ -7,6 +7,7 @@
> #include
> #include
> #include
> +#include
This should go up one line I think, for ordering.
> #include
> #include
>
> @@ -14,6 +15,14 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +int arch_early_init_r(void)
> +{
> + /* do the pin-muxing */
> + gpio_ich6_pinctrl_init();
> +
> + return 0;
> +}
> +
> int board_early_init_f(void)
> {
> lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
> diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
> index 823e051..3c7b266 100644
> --- a/include/configs/minnowmax.h
> +++ b/include/configs/minnowmax.h
> @@ -15,6 +15,7 @@
>
> #define CONFIG_SYS_MONITOR_LEN (1 << 20)
> #define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_ARCH_EARLY_INIT_R
>
> #define CONFIG_NR_DRAM_BANKS 1
>
> --
> 2.1.4
>
Regards,
Simon
---
Added to GNATS database as unassigned-patches/145
>Responsible:patch-coord
>Message-Id:
>
>In-Reply-To:<1429805775-1809-5-git-send-email-cont...@huau-gabriel.fr>
>References: <1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr>
><1429805775-1809-5-git-send-email-cont...@huau-gabriel.fr>
>Patch-Date: Fri Apr 24 05:37:28 +0200 2015
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[U-Boot] unassigned-patches/146: Re: [PATCH 2/4] x86: minnowmax: add GPIO banks in the device tree
Hi Gabriel,
On Fri, Apr 24, 2015 at 12:16 AM, Gabriel Huau wrote:
> There is 6 banks:
There are
> 4 banks for CORE: available in S0 mode
> 2 banks for SUS (Suspend): available in S0-S5 mode
>
> Signed-off-by: Gabriel Huau
> ---
> arch/x86/dts/minnowmax.dts | 42 ++
> 1 file changed, 42 insertions(+)
>
> diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
> index 8f34369..c73e421 100644
> --- a/arch/x86/dts/minnowmax.dts
> +++ b/arch/x86/dts/minnowmax.dts
> @@ -21,6 +21,48 @@
> silent_console = <0>;
> };
>
> + gpioa {
> + compatible = "intel,ich6-gpio";
> + u-boot,dm-pre-reloc;
> + reg = <0 0x20>;
> + bank-name = "A";
> + };
> +
> + gpiob {
> + compatible = "intel,ich6-gpio";
> + u-boot,dm-pre-reloc;
> + reg = <0x20 0x20>;
> + bank-name = "B";
> + };
> +
> + gpioc {
> + compatible = "intel,ich6-gpio";
> + u-boot,dm-pre-reloc;
> + reg = <0x40 0x20>;
> + bank-name = "C";
> + };
> +
> + gpiod {
> + compatible = "intel,ich6-gpio";
> + u-boot,dm-pre-reloc;
> + reg = <0x60 0x20>;
> + bank-name = "D";
> + };
> +
> + gpioe {
> + compatible = "intel,ich6-gpio";
> + u-boot,dm-pre-reloc;
> + reg = <0x80 0x20>;
> + bank-name = "E";
> + };
> +
> + gpiof {
> + compatible = "intel,ich6-gpio";
> + u-boot,dm-pre-reloc;
> + reg = <0xA0 0x20>;
> + bank-name = "F";
> + };
> +
> chosen {
> stdout-path = "/serial";
> };
> --
Reviewed-by: Bin Meng
---
Added to GNATS database as unassigned-patches/146
>Responsible:patch-coord
>Message-Id:
>
>In-Reply-To:<1429805775-1809-3-git-send-email-cont...@huau-gabriel.fr>
>References: <1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr>
><1429805775-1809-3-git-send-email-cont...@huau-gabriel.fr>
>Patch-Date: Fri Apr 24 04:03:19 +0200 2015
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[U-Boot] unassigned-patches/147: Re: [PATCH 2/4] x86: minnowmax: add GPIO banks in the device tree
On 23 April 2015 at 10:16, Gabriel Huau wrote: > There is 6 banks: > 4 banks for CORE: available in S0 mode > 2 banks for SUS (Suspend): available in S0-S5 mode > > Signed-off-by: Gabriel Huau > --- > arch/x86/dts/minnowmax.dts | 42 ++ > 1 file changed, 42 insertions(+) Acked-by: Simon Glass --- Added to GNATS database as unassigned-patches/147 >Responsible:patch-coord >Message-Id: > >In-Reply-To:<1429805775-1809-3-git-send-email-cont...@huau-gabriel.fr> >References: <1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr> ><1429805775-1809-3-git-send-email-cont...@huau-gabriel.fr> >Patch-Date: Fri Apr 24 05:26:17 +0200 2015 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/148: Re: [PATCH 0/4] x86: support of pin-muxing from device tree
Hi Gabriel, On Fri, Apr 24, 2015 at 12:16 AM, Gabriel Huau wrote: > This serie of patches adds the support of pin-muxing from the device tree > through > different properties. I have put two example to enable the USB Host on the > minnowboard max. > > The support of the call to 'setup_pch_gpios' is still supported and > only the minnowboard has been tested with the device tree implementation. > > Because the GPIO and IO base register ares different, I have also defined > some proxy function to set the function/value and direction of the GPIO as > the GPIO register can override some registers in the IO. > > Gabriel Huau (4): > x86: baytrail: fix the GPIOBASE address > x86: minnowmax: add GPIO banks in the device tree > x86: gpio: add pinctrl support from the device tree > x86: minnowmax: initialize the pin-muxing from device tree > > arch/x86/dts/minnowmax.dts| 63 + > arch/x86/include/asm/arch-baytrail/gpio.h | 3 +- > arch/x86/include/asm/gpio.h | 1 + > board/intel/minnowmax/minnowmax.c | 9 ++ > drivers/gpio/intel_ich6_gpio.c| 222 > ++ > include/configs/minnowmax.h | 1 + > include/dt-bindings/gpio/gpio.h | 20 +++ > 7 files changed, 292 insertions(+), 27 deletions(-) > > -- Thanks for these patches! Just a general comment, you don't need send emails to u-boot-patc...@bugs.denx.de, and always include a simple sentence in the commit message :) Regards, Bin --- Added to GNATS database as unassigned-patches/148 >Responsible:patch-coord >Message-Id: > >In-Reply-To:<1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr> >References: <1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr> >Patch-Date: Fri Apr 24 05:23:35 +0200 2015 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/149: [PATCH] stm32f4: fix serial output bug
Signed-off-by: kunhuahuang
---
Added to GNATS database as unassigned-patches/149
>Responsible:patch-coord
>Message-Id: <1429868904-4779-1-git-send-email-huangkun...@gmail.com>
>In-Reply-To:
>References:
>Patch-Date: Fri Apr 24 11:48:24 +0200 2015
---
drivers/serial/serial_stm32.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index 3c80096..693a7fa 100644
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -81,6 +81,10 @@ static int stm32_serial_getc(void)
static void stm32_serial_putc(const char c)
{
struct stm32_serial *usart = (struct stm32_serial *)USART_BASE;
+
+ if(c == '\n')
+ stm32_serial_putc('\r');
+
while ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)
;
writel(c, &usart->dr);
--
1.9.1
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[U-Boot] unassigned-patches/151: Re: [PATCH 0/4] x86: support of pin-muxing from device tree
Hi Bin, On 04/23/2015 08:23 PM, Bin Meng wrote: > Hi Gabriel, > > On Fri, Apr 24, 2015 at 12:16 AM, Gabriel Huau > wrote: >> This serie of patches adds the support of pin-muxing from the device tree >> through >> different properties. I have put two example to enable the USB Host on the >> minnowboard max. >> >> The support of the call to 'setup_pch_gpios' is still supported and >> only the minnowboard has been tested with the device tree implementation. >> >> Because the GPIO and IO base register ares different, I have also defined >> some proxy function to set the function/value and direction of the GPIO as >> the GPIO register can override some registers in the IO. >> >> Gabriel Huau (4): >>x86: baytrail: fix the GPIOBASE address >>x86: minnowmax: add GPIO banks in the device tree >>x86: gpio: add pinctrl support from the device tree >>x86: minnowmax: initialize the pin-muxing from device tree >> >> arch/x86/dts/minnowmax.dts| 63 + >> arch/x86/include/asm/arch-baytrail/gpio.h | 3 +- >> arch/x86/include/asm/gpio.h | 1 + >> board/intel/minnowmax/minnowmax.c | 9 ++ >> drivers/gpio/intel_ich6_gpio.c| 222 >> ++ >> include/configs/minnowmax.h | 1 + >> include/dt-bindings/gpio/gpio.h | 20 +++ >> 7 files changed, 292 insertions(+), 27 deletions(-) >> >> -- > Thanks for these patches! Just a general comment, you don't need send > emails to u-boot-patc...@bugs.denx.de, and always include a simple > sentence in the commit message :) > > Regards, > Bin That's why I received plenty of emails to tell me that my patches were not assigned :). I'll do the modification for the next version, thank you for the feedback, I appreciate this. Regards, Gabriel --- Added to GNATS database as unassigned-patches/151 >Responsible:patch-coord >Message-Id: <553a55c4.9080...@huau-gabriel.fr> >In-Reply-To: > >References: <1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr> > >Patch-Date: Fri Apr 24 16:40:04 +0200 2015 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/150: Re: [PATCH 3/4] x86: gpio: add pinctrl support from the device tree
Hi Simon,
On 04/23/2015 08:35 PM, Simon Glass wrote:
> Hi,
>
> On 23 April 2015 at 10:16, Gabriel Huau wrote:
>> A set of properties has been defined for the device tree to select for
>> each pin the pull/func/default output configuration.
>>
>> The offset for the PAD needs to be provided and if a GPIO needs to be
>> configured, his offset needs to be provided as well.
>>
>> Here is an example:
>> pin_usb_host_en0@0 {
>> gpio-offset = <0x80 8>;
>> pad-offset = <0x260>;
>> mode-gpio;
>> output-value = <1>;
>> direction = ;
>> };
>>
>> Signed-off-by: Gabriel Huau
>> ---
>> arch/x86/dts/minnowmax.dts| 21 +++
>> arch/x86/include/asm/arch-baytrail/gpio.h | 1 +
>> arch/x86/include/asm/gpio.h | 1 +
>> drivers/gpio/intel_ich6_gpio.c| 222
>> ++
>> include/dt-bindings/gpio/gpio.h | 20 +++
>> 5 files changed, 239 insertions(+), 26 deletions(-)
>>
>> diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
>> index c73e421..3936e21 100644
>> --- a/arch/x86/dts/minnowmax.dts
>> +++ b/arch/x86/dts/minnowmax.dts
>> @@ -6,6 +6,8 @@
>>
>> /dts-v1/;
>>
>> +#include
>> +
>> /include/ "skeleton.dtsi"
>> /include/ "serial.dtsi"
>>
>> @@ -21,6 +23,25 @@
>> silent_console = <0>;
>> };
>>
>> + pch_pinctrl {
>> + compatible = "intel,ich6-pinctrl";
> Make sure you use tabs for indenting here.
>
> You should create a binding file to describe your binding - in
> doc/device-tree-bindings.
>
>> + pin_usb_host_en0@0 {
>> + gpio-offset = <0x80 8>;
>> + pad-offset = <0x260>;
>> + mode-gpio;
>> + output-value = <1>;
>> + direction = ;
>> + };
>> +
>> + pin_usb_host_en1@0 {
>> + gpio-offset = <0x80 9>;
>> + pad-offset = <0x258>;
>> + mode-gpio;
>> + output-value = <1>;
>> + direction = ;
>> + };
>> + };
>> +
>> gpioa {
>> compatible = "intel,ich6-gpio";
>> u-boot,dm-pre-reloc;
>> diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h
>> b/arch/x86/include/asm/arch-baytrail/gpio.h
>> index 4e8987c..85a65a8 100644
>> --- a/arch/x86/include/asm/arch-baytrail/gpio.h
>> +++ b/arch/x86/include/asm/arch-baytrail/gpio.h
>> @@ -9,5 +9,6 @@
>>
>> /* Where in config space is the register that points to the GPIO
>> registers? */
>> #define PCI_CFG_GPIOBASE 0x48
>> +#define PCI_CFG_IOBASE 0x4c
>>
>> #endif /* _X86_ARCH_GPIO_H_ */
>> diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
>> index 1099427..ed85b08 100644
>> --- a/arch/x86/include/asm/gpio.h
>> +++ b/arch/x86/include/asm/gpio.h
>> @@ -147,6 +147,7 @@ struct pch_gpio_map {
>> } set3;
>> };
>>
>> +int gpio_ich6_pinctrl_init(void);
>> void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
>> void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
>>
>> diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
>> index 7e679a0..a110d5b 100644
>> --- a/drivers/gpio/intel_ich6_gpio.c
>> +++ b/drivers/gpio/intel_ich6_gpio.c
>> @@ -44,21 +44,32 @@ struct ich6_bank_priv {
>> uint16_t lvl;
>> };
>>
>> +#define GPIO_USESEL_OFFSET(x) (x)
>> +#define GPIO_IOSEL_OFFSET(x) (x + 4)
>> +#define GPIO_LVL_OFFSET(x) (x + 8)
> Comments on the above
>
>> +
>> +#define IOPAD_MODE_MASK0x7
>> +#define IOPAD_PULL_ASSIGN_MASK 0x3
>> +#define IOPAD_PULL_ASSIGN_SHIFT7
> Can you make the mask value an actual valid mask, like:
>
> +#define IOPAD_PULL_ASSIGN_MASK (0x3 << IOPAD_PULL_ASSIGN_SHIFT)
>
>> +#define IOPAD_PULL_STRENGTH_MASK 0x3
>> +#define IOPAD_PULL_STRENGTH_SHIFT 9
>> +
>> +static int __ich6_gpio_set_value(uint16_t base, unsigned offset, int value);
> Can you reorder the functions to avoid the need for these forward
> declarations? Also only one under
[U-Boot] [PATCH v6] dreamplug: initial board support.
From: Jason Cooper Copied wholeheartedly from board/Marvell/guruplug and modified to add support for SPI NOR flash. CONFIG_MACH_DREAMPLUG defined in include/configs/dreamplug.h until Linus's kernel.org tree adds it to mach-types.h. Once it trickles down, the definition can be removed from dreamplug.h. Signed-off-by: Jason Cooper --- Changes from v1 to v2: - resorted series to move 'make all' support last. Changes from v2 to v3: - Use MACH_TYPE_GURUPLUG for now until dreamplug support is in Linux. - Update MAINTAINERS. - Collapse into one patch. Changes from v3 to v4: - update copyright info as recommended by Prafulla Wadaskar. - maintain proper order in boards.cfg, MAINTAINERS, etc. - label MPP's - change back to MACH_TYPE_DREAMPLUG. This patch is just RFC until the Dreamplug is supported in Linux (and MACH_TYPE_ added). Changes from v4 to v5: - Complete rewrite due to receiving u-boot source indirectly from Global Scale Tech. - Added driver for integrated RTC. (thx GST!) - Added support for displaying CPU frequencies at boot. (thx GST!) - Adjust USB timeout to handle dreamplug EHCI chipset. - Cleaned up MPP registers based on Global Scale code. (thx GST!) - broke out MACH_TYPE_DREAMPLUG changes since it's going to be a while until the Linux arm tree gets sorted and accepts new boards again. Since all Dreamplugs currently on the market set r1 to MACH_TYPE_GURUPLUG, this allows the board to be added to u-boot while waiting for Linux mainline. Once it's in Linux mainline, then the last patch can be integrated to use MACH_TYPE_DREAMPLUG. Changes from v5 to v6: - Define MACH_TYPE_DREAMPLUG in includes/configs/dreamplug.h until Linus's kernel.org tree includes assigned machine id. This is on Wolfgang's recommendation [1]. - Removed dcache disabling as it is no longer enabled by default. - USB timeout fix was merged. - Marvell Integrated RTC was merged. - Dropped CPU frequency printout as I'm not familiar enough with all flavors of kirkwood SoCs to do it correctly. - Labelled MPP*_GPIO pins that are broken out as gpio pins for the user. - Fixed function name mv_phy_88e1121_init() -> mv_phy_88e1116_init(). [1] http://www.mail-archive.com/u-boot@lists.denx.de/msg60921.html MAINTAINERS |4 + board/Marvell/dreamplug/Makefile | 54 +++ board/Marvell/dreamplug/dreamplug.c | 154 board/Marvell/dreamplug/dreamplug.h | 42 + board/Marvell/dreamplug/kwbimage.cfg | 163 ++ boards.cfg |1 + include/configs/dreamplug.h | 158 7 files changed, 576 insertions(+), 0 deletions(-) create mode 100644 board/Marvell/dreamplug/Makefile create mode 100644 board/Marvell/dreamplug/dreamplug.c create mode 100644 board/Marvell/dreamplug/dreamplug.h create mode 100644 board/Marvell/dreamplug/kwbimage.cfg create mode 100644 include/configs/dreamplug.h diff --git a/MAINTAINERS b/MAINTAINERS index 2f60a60..88d5637 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -70,6 +70,10 @@ Conn Clark ESTEEM192E MPC8xx +Jason Cooper + + dreamplug ARM926EJS (Kirkwood SoC) + Joe D'Abbraccio MPC837xERDB MPC837x diff --git a/board/Marvell/dreamplug/Makefile b/board/Marvell/dreamplug/Makefile new file mode 100644 index 000..9ee5406 --- /dev/null +++ b/board/Marvell/dreamplug/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2011 +# Jason Cooper +# +# Based on work by: +# Marvell Semiconductor +# Written-by: Siddarth Gore +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS := dreamplug.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SO
Re: [U-Boot] [GIT PULL] [Update] Pull request: u-boot-imx
Hi Stefano,
On Fri, 10 Aug 2012 08:54:06 +0200, Stefano Babic
wrote:
> Hi Albert,
>
> an update pull request, please pull from u-boot-imx, thanks.
>
> The following changes since commit
> 8abcd8ab962cd5fb2a4c025e7c7b62a9faf4aa08:
>
> DaVinci DA8xx: fix set_cpu_clk_info() (2012-08-05 22:02:40 +0200)
>
> are available in the git repository at:
>
> git://www.denx.de/git/u-boot-imx.git master
>
> for you to fetch changes up to
> 42abce776222a5d5cb2b355e77539cabb705b04a:
>
> sc_sps_1: Adjust board config to use 'mxs' SoC code (2012-08-10
> 08:48:24 +0200)
>
>
> Benoît Thébaudeau (1):
> rtc: imxdi: Initial support
>
> Fabio Estevam (3):
> mx28evk: Turn on caches
> mx51evk: do not overwrite the console
> vision2: do not overwrite the console
>
> Marek Vasut (9):
> MX28: SPI: Refactor spi_xfer a bit
> MX28: SPI: Pull out the PIO transfer function
> MX28: SPI: Add DMA transfer support
> MX28: Fix up the MMC driver DMA mode
> MX28: Split out the PIO and DMA transfer functions
> MX28: Transfer small blocks via PIO in MXS MMC
> MX28: Fix MXS MMC DMA issues
> MX28: Move the u-boot.bd info CPUDIR/SOCDIR
> MX28: Add SchulerControl SC_SPS_1 platform
>
> Otavio Salvador (10):
> imx: Use a clear identification of an unidentified CPU type
> MX28: extend print_cpuinfo() to use chip information
> MX28: use a clear name for DDR2 initialization
> mxs: reorganize source directory for easy sharing of code in
> i.MXS SoCs
> mxs: prefix register acessor macros with 'mxs' prefix
> mxs: prefix register structs with 'mxs' prefix
> mxs: Reowork SPL to use 'mxs' prefix for methods
> mxs: Clarify why we poweroff in case of brownout in 5v conflict
> mxs: rename mx28.c to mxs.c as it is common to i.MX233 and
> i.MX28 SoCs sc_sps_1: Adjust board config to use 'mxs' SoC code
>
> Stathis Voukelatos (1):
> i.MX28: bug fixes in PMU configuration code
>
> Stefano Babic (1):
> MX5: mx53loco: do not overwrite the console
>
> Veli-Pekka Peltola (1):
> Add support for Bluegiga APX4 Development Kit
>
> MAINTAINERS|5 +
> Makefile |2 +-
> arch/arm/cpu/arm926ejs/{mx28 => mxs}/Makefile |2 +-
> arch/arm/cpu/arm926ejs/{mx28 => mxs}/clock.c | 40 +--
> arch/arm/cpu/arm926ejs/{mx28 => mxs}/iomux.c |6 +-
> arch/arm/cpu/arm926ejs/{mx28/mx28.c => mxs/mxs.c} | 72 +++--
> .../arm926ejs/{mx28/mx28_init.h => mxs/mxs_init.h} | 14 +-
> arch/arm/cpu/arm926ejs/{mx28 => mxs}/spl_boot.c| 20 +-
> .../cpu/arm926ejs/{mx28 => mxs}/spl_lradc_init.c | 10 +-
> .../arm/cpu/arm926ejs/{mx28 => mxs}/spl_mem_init.c | 64 ++---
> .../cpu/arm926ejs/{mx28 => mxs}/spl_power_init.c | 274
> ++--
> arch/arm/cpu/arm926ejs/{mx28 => mxs}/start.S |0
> arch/arm/cpu/arm926ejs/{mx28 => mxs}/timer.c |8 +-
> .../arm/cpu/arm926ejs/{mx28 => mxs}/u-boot-spl.lds |2 +-
> .../arm/cpu/arm926ejs/mxs}/u-boot.bd |0
> arch/arm/cpu/armv7/imx-common/cpu.c|4 +-
> .../include/asm/{arch-mx28 => arch-mxs}/clock.h|0
> arch/arm/include/asm/{arch-mx28 => arch-mxs}/dma.h |0
> .../arm/include/asm/{arch-mx28 => arch-mxs}/gpio.h |0
> .../include/asm/{arch-mx28 => arch-mxs}/imx-regs.h |0
> .../asm/{arch-mx28 => arch-mxs}/iomux-mx28.h |0
> .../include/asm/{arch-mx28 => arch-mxs}/iomux.h|0
> .../asm/{arch-mx28 => arch-mxs}/regs-apbh.h| 256
> +-
> .../asm/{arch-mx28 => arch-mxs}/regs-base.h|0
> .../include/asm/{arch-mx28 => arch-mxs}/regs-bch.h | 44 ++--
> .../asm/{arch-mx28 => arch-mxs}/regs-clkctrl.h | 60 ++---
> .../asm/{arch-mx28 => arch-mxs}/regs-common.h | 34 +--
> .../asm/{arch-mx28 => arch-mxs}/regs-digctl.h | 56 ++--
> .../asm/{arch-mx28 => arch-mxs}/regs-gpmi.h| 28 +-
> .../include/asm/{arch-mx28 => arch-mxs}/regs-i2c.h | 30 +--
> .../asm/{arch-mx28 => arch-mxs}/regs-lcdif.h | 66 ++---
> .../asm/{arch-mx28 => arch-mxs}/regs-lradc.h | 50 ++--
> .../asm/{arch-mx28 => arch-mxs}/regs-ocotp.h | 88 +++
> .../asm/{arch-mx28 => arch-mxs}/regs-pinctrl.h | 170
> ++-- .../asm/{arch-mx28 => arch-mxs}/regs-power.h |
> 30 +-- .../include/asm/{arch-mx28 => arch-
Re: [U-Boot] Please pull u-boot-atmel/master
Hi Andreas, On Wed, 8 Aug 2012 00:29:12 +0200, Andreas Bießmann wrote: > The following changes since commit > 8abcd8ab962cd5fb2a4c025e7c7b62a9faf4aa08: > > DaVinci DA8xx: fix set_cpu_clk_info() (2012-08-05 22:02:40 +0200) > > are available in the git repository at: > > git://git.denx.de/u-boot-atmel.git master > > for you to fetch changes up to > 17cda15fa6fb3ab2433bed951dad5c4ab30d8cbc: > > at91: Add support for taskit AT91SAM9G20 boards. (2012-08-07 > 23:47:29 +0200) > > > Andreas Bießmann (3): > doc/git-mailrc: update at91 and avr32 > MAINTAINERS: fix entry of Ilko Iliev > MAINTAINERS: fix Andreas Bießmann AVR32 entry > > Bo Shen (1): > arm : Atmel : add at91sam9x5ek board support > > Markus Hubig (2): > Enable the EMAC clock in at91_macb_hw_init(). > at91: Add support for taskit AT91SAM9G20 boards. > > MAINTAINERS| 23 +- > arch/arm/cpu/arm926ejs/at91/Makefile |1 + > arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c |4 + > arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c | 232 > arch/arm/cpu/arm926ejs/at91/clock.c > | 12 +- arch/arm/include/asm/arch-at91/at91sam9_matrix.h |2 + > arch/arm/include/asm/arch-at91/at91sam9x5.h| 170 > arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h | > 91 ++ arch/arm/include/asm/arch-at91/hardware.h |2 + > board/atmel/at91sam9x5ek/Makefile | 52 > board/atmel/at91sam9x5ek/at91sam9x5ek.c| 293 > > board/atmel/at91sam9x5ek/config.mk |1 + > board/taskit/stamp9g20/Makefile| 53 > board/taskit/stamp9g20/led.c | 138 + > board/taskit/stamp9g20/stamp9g20.c | 191 > + boards.cfg | > 3 + doc/git-mailrc |5 +- > drivers/net/macb.c |4 +- > include/configs/at91sam9x5ek.h | 183 > include/configs/stamp9g20.h| > 266 ++ 20 files changed, 1713 insertions(+), 13 > deletions(-) create mode 100644 > arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c create mode 100644 > arch/arm/include/asm/arch-at91/at91sam9x5.h create mode 100644 > arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h create mode 100644 > board/atmel/at91sam9x5ek/Makefile create mode 100644 > board/atmel/at91sam9x5ek/at91sam9x5ek.c create mode 100644 > board/atmel/at91sam9x5ek/config.mk create mode 100644 > board/taskit/stamp9g20/Makefile create mode 100644 > board/taskit/stamp9g20/led.c create mode 100644 > board/taskit/stamp9g20/stamp9g20.c create mode 100644 > include/configs/at91sam9x5ek.h create mode 100644 > include/configs/stamp9g20.h > Applied to u-boot-arm/master, thanks! Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-atmel/master
Hi Andreas, On Wed, 8 Aug 2012 00:29:12 +0200, Andreas Bießmann wrote: > The following changes since commit > 8abcd8ab962cd5fb2a4c025e7c7b62a9faf4aa08: > > DaVinci DA8xx: fix set_cpu_clk_info() (2012-08-05 22:02:40 +0200) > > are available in the git repository at: > > git://git.denx.de/u-boot-atmel.git master > > for you to fetch changes up to > 17cda15fa6fb3ab2433bed951dad5c4ab30d8cbc: > > at91: Add support for taskit AT91SAM9G20 boards. (2012-08-07 > 23:47:29 +0200) > > > Andreas Bießmann (3): > doc/git-mailrc: update at91 and avr32 > MAINTAINERS: fix entry of Ilko Iliev > MAINTAINERS: fix Andreas Bießmann AVR32 entry > > Bo Shen (1): > arm : Atmel : add at91sam9x5ek board support > > Markus Hubig (2): > Enable the EMAC clock in at91_macb_hw_init(). > at91: Add support for taskit AT91SAM9G20 boards. > > MAINTAINERS| 23 +- > arch/arm/cpu/arm926ejs/at91/Makefile |1 + > arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c |4 + > arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c | 232 > arch/arm/cpu/arm926ejs/at91/clock.c > | 12 +- arch/arm/include/asm/arch-at91/at91sam9_matrix.h |2 + > arch/arm/include/asm/arch-at91/at91sam9x5.h| 170 > arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h | > 91 ++ arch/arm/include/asm/arch-at91/hardware.h |2 + > board/atmel/at91sam9x5ek/Makefile | 52 > board/atmel/at91sam9x5ek/at91sam9x5ek.c| 293 > > board/atmel/at91sam9x5ek/config.mk |1 + > board/taskit/stamp9g20/Makefile| 53 > board/taskit/stamp9g20/led.c | 138 + > board/taskit/stamp9g20/stamp9g20.c | 191 > + boards.cfg | > 3 + doc/git-mailrc |5 +- > drivers/net/macb.c |4 +- > include/configs/at91sam9x5ek.h | 183 > include/configs/stamp9g20.h| > 266 ++ 20 files changed, 1713 insertions(+), 13 > deletions(-) create mode 100644 > arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c create mode 100644 > arch/arm/include/asm/arch-at91/at91sam9x5.h create mode 100644 > arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h create mode 100644 > board/atmel/at91sam9x5ek/Makefile create mode 100644 > board/atmel/at91sam9x5ek/at91sam9x5ek.c create mode 100644 > board/atmel/at91sam9x5ek/config.mk create mode 100644 > board/taskit/stamp9g20/Makefile create mode 100644 > board/taskit/stamp9g20/led.c create mode 100644 > board/taskit/stamp9g20/stamp9g20.c create mode 100644 > include/configs/at91sam9x5ek.h create mode 100644 > include/configs/stamp9g20.h > Applied to u-boot-arm/master, thanks! Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-ti/master
Hi Tom, On Tue, 7 Aug 2012 10:08:39 -0700, Tom Rini wrote: > Hello, > > The following changes since commit > 8abcd8ab962cd5fb2a4c025e7c7b62a9faf4aa08: > > DaVinci DA8xx: fix set_cpu_clk_info() (2012-08-05 22:02:40 +0200) > > are available in the git repository at: > > git://git.denx.de/u-boot-ti next > > for you to fetch changes up to > a47233a30055660ad64d865f1fde19503ed02696: > > am335x_evm: enable SMSC PHY driver (2012-08-07 10:07:22 -0700) > > > Enric Balletbò i Serra (1): > OMAP3: fix DRAM size for IGEP-based boards. > > Ilya Yanok (1): > am335x_evm: enable SMSC PHY driver > > board/isee/igep0020/igep0020.c |6 +++--- > board/isee/igep0030/igep0030.c |6 +++--- > include/configs/am335x_evm.h | 1 + > 3 files changed, 7 insertions(+), 6 deletions(-) > Applied to u-boot-arm/master, thanks! Amicalement, -- Albert. _______ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-staging/tr...@ti.com
Hi Tom, On Fri, 10 Aug 2012 22:06:59 +0200, Wolfgang Denk wrote: > Dear Tom, > > In message <20120810161021.GG3306@bill-the-cat> you wrote: > > > > To try and ease the backlog of ARM changes, I've taken the liberty > > of grabbing the Snowball and Raspberry Pi model B board support > > patches and putting them into the staging tree. Both of these > > series have been posted for some time and been reviewed. Wolfgang, > > if you would like to wait for Albert to pick up this request, > > that's fine. I just wanted to make sure the submitters weren't > > left waiting. Thanks! > > Thanks, highly appreciated. > > As this contains a lot of ARM, indeed I would like to wait for > Albert's ACK or pulling (whichever he prefers). > > Best regards, > > Wolfgang Denk > Applied to u-boot-arm/master, thanks! Amicalement, -- Albert. _______ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Commit 8b5a02640adf77301f943e8754992c50df004e8a breaks about 20 ARM builds
Hi all, I have encountered an issue when rebasing the ARM tree above u-boot/master, with this commit : 8b5a02640adf77301f943e8754992c50df004e8a It seems to break about 20 ARM builds, for instance spear600, on my stock Ubuntu 12.04 ARM gcc: uboot@lilith:~/src/u-boot-arm$ git checkout 8b5a02640adf77301f943e8754992c50df004e8a^ Previous HEAD position was 8b5a026... Makefile: cosmetic: optimize usage of LIBS-y HEAD is now at f52d7b3... Makefile: replace LIBS by LIBS-y uboot@lilith:~/src/u-boot-arm$ LANG=C ./MAKEALL spear600 Configuring for spear600 - Board: spear6xx_evb, Options: spear600 text databss dec hex filename 190670 8604 21924 221198 3600e ./u-boot - SUMMARY Boards compiled: 1 -- uboot@lilith:~/src/u-boot-arm$ git checkout 8b5a02640adf77301f943e8754992c50df004e8a Previous HEAD position was f52d7b3... Makefile: replace LIBS by LIBS-y HEAD is now at 8b5a026... Makefile: cosmetic: optimize usage of LIBS-y uboot@lilith:~/src/u-boot-arm$ LANG=C ./MAKEALL spear600 Configuring for spear600 - Board: spear6xx_evb, Options: spear600 make: *** [u-boot] Error 139 arm-linux-gnueabi-size: ./u-boot: File format not recognized arch/arm/cpu/arm926ejs/start.o: In function `flush_dcache': /home/uboot/src/u-boot-arm/arch/arm/cpu/arm926ejs/start.S:393: undefined reference to `lowlevel_init' arch/arm/lib/libarm.o: In function `board_init_r': /home/uboot/src/u-boot-arm/arch/arm/lib/board.c:585: undefined reference to `misc_init_r' arch/arm/lib/libarm.o:(.data+0x4): undefined reference to `board_early_init_f' arch/arm/lib/libarm.o:(.data+0x28): undefined reference to `dram_init' board/spear/spear600/libspear600.o: In function `board_init': /home/uboot/src/u-boot-arm/board/spear/spear600/spear600.c:38: undefined reference to `spear_board_init' arm-linux-gnueabi-ld: BFD (GNU Binutils for Ubuntu) 2.22 assertion fail ../../bfd/elf32-arm.c:13830 /bin/bash: line 1: 10706 Segmentation fault (core dumped) arm-linux-gnueabi-ld -pie -T u-boot.lds -Bstatic -Ttext 0x0070 $UNDEF_SYM arch/arm/cpu/arm926ejs/start.o --start-group api/libapi.o arch/arm/cpu/arm926ejs/libarm926ejs.o arch/arm/cpu/arm926ejs/spear/libspear.o arch/arm/lib/libarm.o common/libcommon.o disk/libdisk.o drivers/bios_emulator/libatibiosemu.o drivers/block/libblock.o drivers/dma/libdma.o drivers/fpga/libfpga.o drivers/gpio/libgpio.o drivers/hwmon/libhwmon.o drivers/i2c/libi2c.o drivers/input/libinput.o drivers/misc/libmisc.o drivers/mmc/libmmc.o drivers/mtd/libmtd.o drivers/mtd/nand/libnand.o drivers/mtd/onenand/libonenand.o drivers/mtd/spi/libspi_flash.o drivers/mtd/ubi/libubi.o drivers/net/libnet.o drivers/net/phy/libphy.o drivers/pci/libpci.o drivers/pcmcia/libpcmcia.o drivers/power/libpower.o drivers/rtc/librtc.o drivers/serial/libserial.o drivers/spi/libspi.o drivers/twserial/libtws.o drivers/usb/eth/libusb_eth.o drivers/usb/gadget/libusb_gadget.o drivers/usb/host/libusb_host.o drivers/usb/musb/libusb_musb.o drivers/usb/phy/libusb_phy.o drivers/usb/ulpi/libusb_ulpi.o drivers/video/libvideo.o drivers/watchdog/libwatchdog.o fs/cramfs/libcramfs.o fs/ext2/libext2fs.o fs/fat/libfat.o fs/fdos/libfdos.o fs/jffs2/libjffs2.o fs/reiserfs/libreiserfs.o fs/ubifs/libubifs.o fs/yaffs2/libyaffs2.o fs/zfs/libzfs.o lib/libfdt/libfdt.o lib/libgeneric.o lib/lzma/liblzma.o lib/lzo/liblzo.o lib/zlib/libz.o net/libnet.o post/libpost.o test/libtest.o board/spear/spear600/libspear600.o --end-group /home/uboot/src/u-boot-arm/arch/arm/lib/eabi_compat.o -L /usr/lib/gcc/arm-linux-gnueabi/4.6 -lgcc -Map u-boot.map -o u-boot make: *** [u-boot] Error 139 - SUMMARY Boards compiled: 1 Boards with errors: 1 ( spear600 ) -- Daniel, can you please investigate this? Amicalement, -- Albert. _______ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-staging/tr...@ti.com
Hi Albert, On Tue, 14 Aug 2012 02:04:15 +0200, Albert ARIBAUD (U-Boot) wrote: > Hi Tom, > > On Fri, 10 Aug 2012 22:06:59 +0200, Wolfgang Denk wrote: > > > Dear Tom, > > > > In message <20120810161021.GG3306@bill-the-cat> you wrote: > > > > > > To try and ease the backlog of ARM changes, I've taken the liberty > > > of grabbing the Snowball and Raspberry Pi model B board support > > > patches and putting them into the staging tree. Both of these > > > series have been posted for some time and been reviewed. > > > Wolfgang, if you would like to wait for Albert to pick up this > > > request, that's fine. I just wanted to make sure the submitters > > > weren't left waiting. Thanks! > > > > Thanks, highly appreciated. > > > > As this contains a lot of ARM, indeed I would like to wait for > > Albert's ACK or pulling (whichever he prefers). > > > > Best regards, > > > > Wolfgang Denk > > > > Applied to u-boot-arm/master, thanks! But I might hold this a little, as commit "snowball: Adding architecture dependent initialisation" 7e2b895eb5aa10890910eed8921d042d13b828c0 seems to play bad with my stock Ubuntu 12.04 GCC on u8500_href: uboot@lilith:~/src/u-boot-arm$ git checkout f917361b988f69ddc0dbe2bd2beb93b296065b70^ HEAD is now at 1b5d8d5... u8500: Moving prcmu to cpu directory uboot@lilith:~/src/u-boot-arm$ LANG=C ./MAKEALL u8500_href Configuring for u8500_href board... textdata bss dec hex filename 139584 4408 221728 36572059498 ./u-boot - SUMMARY Boards compiled: 1 -- uboot@lilith:~/src/u-boot-arm$ git checkout f917361b988f69ddc0dbe2bd2beb93b296065b70 Previous HEAD position was 1b5d8d5... u8500: Moving prcmu to cpu directory HEAD is now at f917361... snowball: Adding architecture dependent initialisation uboot@lilith:~/src/u-boot-arm$ LANG=C ./MAKEALL u8500_href Configuring for u8500_href board... text data bss dec hex filename 1397444408 221696 365848 59518 ./u-boot u8500_href.c:45:0: warning: "PRCMU_BASE" redefined [enabled by default] /home/uboot/src/u-boot-arm/include/asm/arch/prcmu.h:30:0: note: this is the location of the previous definition - SUMMARY Boards compiled: 1 Boards with warnings but no errors: 1 ( u8500_href ) ------ Granted, this is only a warning, but I'd like to see it fixed. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] please pull u-boot-avr32/master
Hi Andreas, On Thu, 16 Aug 2012 14:26:47 +0200, "Andreas Bießmann" wrote: > Dear Wolfgang Denk, > > please do not pull this. I have some more changes, but some need a > rebase on current u-boot-arm. So please first pull this one, then > trigger me to adopt my patch on top of it. > > Best regards > > Andreas Bießmann Andreas, note that u-boot-arm/master is not currently rebased on u-bmmt/master because of commit 8b5a02640adf7 which breaks some twenty ARM boards. Daniel Schwierzeck is working on a fix. Also, I am awaiting Tom Rini's branch from staging. Amicalement, -- Albert. ___________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Function prototype conflicts with standalone apps
Hi Chris,
On Wed, 16 Jan 2013 17:23:58 +1300, Chris Packham
wrote:
> Hi,
>
> I've just run into something porting an existing out of tree board to
> u-boot 2012.10 but I think it points to a generic issue for standalone
> applications.
>
> Consider the following change
>
> diff --git a/examples/standalone/hello_world.c
> b/examples/standalone/hello_world.c
> index 067c390..d2e6a77 100644
> --- a/examples/standalone/hello_world.c
> +++ b/examples/standalone/hello_world.c
> @@ -24,7 +24,7 @@
> #include
> #include
>
> -int hello_world (int argc, char * const argv[])
> +int net_init (int argc, char * const argv[])
> {
> int i;
>
> Because I'm not linking with the u-boot object file, I should be able to
> use any function name I like in my application as long as it isn't one of
> the functions in exports.h (at least in theory). Unfortunately I end up
> with the following compiler error
>
> hello_world.c:27: error: conflicting types for ‘net_init’
> uboot/include/net.h:489: error: previous declaration of ‘net_init’ was
> here
> make[1]: *** [hello_world.o] Error 1
>
> If I replace #include in my app with the first hunk of includes
> from the top of common.h then I can compile just fine.
>
> I was wondering if it made sense to people to have standalone applications
> define something like __STANDALONE__ either via CPPFLAGS or in the source
> itself and use the presence of that to exclude the majority of common.h
> when used in standalone applications. Or alternatively move the required
> bits to exports.h.
(long rant ahead. Short answer after end of rant)
[RANT]
Code writers indeed have a right to name any function or other object
any way they choose... within the constraints of the situation.
Some of these constraints stem from the tools -- you just cannot put an
ampersand in a C object name, for instance -- and some stem from the
'agreement' entered into when using a library -- precisely, the
agreement on the name and semantics of such and such object names.
Here, by including exports.h, you enter an agreement in which
the object name 'net_init' receives a specific meaning. What you want
is to benefit from the agreement without abiding by it.
Now this can be changed, technically, as most things are, and a new
kind of agreement could be devised with fine-grain control on which
object names would or would not be defined. The question is, *should*
this be done?
Would you, analogously, suggest that Linux app developers be able to
opt out of defining fopen() when they #include because they
feel they have a right to define 'char* fopen(float F)' in their code if
they so please? And that it should be done so for just about any
kernel-exported symbol? I suspect not.
So why ask this from U-Boot?
[/RANT]
I personally will NAK such a suggestion. I don't see the point in
adding complexity just to solve a naming conflict between a framework,
de facto standard, name and a freely-modifiable application name. Just
rename the application function -- that'll be all the better since that
will also remove potential misunderstanding for readers of your code.
> Thanks,
> Chris
Amicalement,
--
Albert.
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Re: [U-Boot] [PATCH v4 5/7] MAINTAINERS: Add Tetsuyuki Kobayshi for kzm9g
Hi Nohiburo, Tetsuyuki, On Fri, 20 Jul 2012 08:51:29 +0900, Nobuhiro Iwamatsu wrote: > Applied to my arm/rmobile branch. > Thank you. > > Best regards, > Nobuhiro Actually this did does not seem to have been applied to arm/rmobile, and was not in my patchwork todo either. Should I apply the patch directly in arm/master? Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/39: [PATCH] DHCP regression on 2009-06
Fixed the DHCP/BOOTP/RARP regression introduced in u-boot-2009.06 by initializing our IP addr to 0 in order to accept any IP addr assigned to us by the DHCP/BOOTP/RARP server. Ack-by: Robin Getz Signed-off-by: Michael Zaidman --- Added to GNATS database as unassigned-patches/39 >Responsible:patch-coord >Message-Id: <1247603832-10715-1-git-send-email-michael.zaid...@gmail.com> >In-Reply-To: >References: >Patch-Date: Tue Jul 14 22:37:12 +0200 2009 --- net/net.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/net/net.c b/net/net.c index 5637cf5..9bd3208 100644 --- a/net/net.c +++ b/net/net.c @@ -388,17 +388,20 @@ restart: #if defined(CONFIG_CMD_DHCP) case DHCP: BootpTry = 0; + NetOurIP = 0; DhcpRequest(); /* Basically same as BOOTP */ break; #endif case BOOTP: BootpTry = 0; + NetOurIP = 0; BootpRequest (); break; case RARP: RarpTry = 0; + NetOurIP = 0; RarpRequest (); break; #if defined(CONFIG_CMD_PING) -- 1.6.0.4 _______ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] unassigned-patches/39
Synopsis: [U-Boot][PATCH] DHCP regression on 2009-06 State-Changed-From-To: open->closed State-Changed-By: wd State-Changed-When: Thu, 23 Jul 2009 19:25:27 +0200 State-Changed-Why: Fixed by commit 09133f8580f0106429ba3600f1855bd3577ae58b ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/51: [PATCH] S5PC100: Moved the #defines for PLLs to common header file
The get_pll_clk(int) API returns the PLL frequency based on the (int) argument which is defined locally in clock.c Moving that #define to common header file (clk.h) would be helpful when using the API from other files. Signed-off-by: Naveen Krishna Ch --- Added to GNATS database as unassigned-patches/51 >Responsible:patch-coord >Message-Id: <1265200544-26547-1-git-send-email-ch.nav...@samsung.com> >In-Reply-To: >References: >Patch-Date: Wed Feb 03 13:35:44 +0100 2010 --- cpu/arm_cortexa8/s5pc1xx/clock.c |7 +-- include/asm-arm/arch-s5pc1xx/clk.h |6 ++ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/cpu/arm_cortexa8/s5pc1xx/clock.c b/cpu/arm_cortexa8/s5pc1xx/clock.c index a9e78dd..19619f9 100644 --- a/cpu/arm_cortexa8/s5pc1xx/clock.c +++ b/cpu/arm_cortexa8/s5pc1xx/clock.c @@ -25,12 +25,7 @@ #include #include #include - -#define APLL 0 -#define MPLL 1 -#define EPLL 2 -#define HPLL 3 -#define VPLL 4 +#include #define CLK_M 0 #define CLK_D 1 diff --git a/include/asm-arm/arch-s5pc1xx/clk.h b/include/asm-arm/arch-s5pc1xx/clk.h index f1aa44f..3e59abe 100644 --- a/include/asm-arm/arch-s5pc1xx/clk.h +++ b/include/asm-arm/arch-s5pc1xx/clk.h @@ -23,6 +23,12 @@ #ifndef __ASM_ARM_ARCH_CLK_H_ #define __ASM_ARM_ARCH_CLK_H_ +#define APLL 0 +#define MPLL 1 +#define EPLL 2 +#define HPLL 3 +#define VPLL 4 + void s5pc1xx_clock_init(void); extern unsigned long (*get_pll_clk)(int pllreg); -- 1.6.6 _______ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/3] RFC: Dreamplug support
From: Jason Cooper This is my first attempt at adding the Marvell Dreamplug to U-Boot. It compiles clean, and I've loaded it via JTAG and used it to dump the existing bootloader out of the SPI flash. I have _not_ used it to burn itself to the flash yet. I'm looking for comments before I try that. ;-) Some concerns: 1.) does the 'make all' support need to be last? I've used rebase to edit patches and commits, but I've never reshuffled. Each patch compiles clean. 2.) The SPI flash chip is a Macronix MX25L1606, however it has the identical chip idcode to the MX25L1605. How is that properly handled? The 06 does have some new features [1]. 3.) I added the board number [2], etc to asm/mach-types.h even though it says to not to. ;-) Is there a proper way to do it? If it's copied from the Linux kernel, it hasn't been updated in a while... [1] http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/5F41CDDCB837422C48257639003E5EC3/$File/AN055-Migrate_to_MX25L1606E_and_MX25L8006E-1.2.pdf [2] http://www.arm.linux.org.uk/developer/machines/list.php?id=3550 Jason Cooper (3): dreamplug: Initial support. dreamplug: include in 'make all' dreamplug: switch from NAND flash to SPI flash. MAKEALL |1 + arch/arm/include/asm/mach-types.h| 13 +++ board/Marvell/dreamplug/Makefile | 51 +++ board/Marvell/dreamplug/dreamplug.c | 153 board/Marvell/dreamplug/dreamplug.h | 39 board/Marvell/dreamplug/kwbimage.cfg | 160 ++ boards.cfg |1 + include/configs/dreamplug.h | 111 +++ 8 files changed, 529 insertions(+), 0 deletions(-) create mode 100644 board/Marvell/dreamplug/Makefile create mode 100644 board/Marvell/dreamplug/dreamplug.c create mode 100644 board/Marvell/dreamplug/dreamplug.h create mode 100644 board/Marvell/dreamplug/kwbimage.cfg create mode 100644 include/configs/dreamplug.h _______ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] dreamplug: Initial support.
; "\
+ "bootm 0x640;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "x_bootcmd_ethernet=ping 192.168.2.1\0" \
+ "x_bootcmd_usb=usb start\0" \
+ "x_bootcmd_kernel=nand read.e 0x640 0x10 0x40\0" \
+ "x_bootargs=console=ttyS0,115200\0" \
+ "x_bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
+#define CONFIG_PHY_BASE_ADR0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+#endif /* _CONFIG_DREAMPLUG_H */
--
1.7.0.4
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[U-Boot] [PATCH 3/3] dreamplug: switch from NAND flash to SPI flash.
From: Jason Cooper
MPP._SPI_ configuration copied from
boards/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
Signed-off-by: Jason Cooper
---
board/Marvell/dreamplug/dreamplug.c | 18 +-
board/Marvell/dreamplug/kwbimage.cfg |4 +---
include/configs/dreamplug.h |2 +-
3 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/board/Marvell/dreamplug/dreamplug.c
b/board/Marvell/dreamplug/dreamplug.c
index 32d82ba..6442396 100644
--- a/board/Marvell/dreamplug/dreamplug.c
+++ b/board/Marvell/dreamplug/dreamplug.c
@@ -43,14 +43,14 @@ int board_early_init_f(void)
/* Multi-Purpose Pins Functionality configuration */
u32 kwmpp_config[] = {
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
+ MPP0_SPI_SCn,
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ MPP4_GPIO,
+ MPP5_GPO,
MPP6_SYSRST_OUTn,
- MPP7_GPO, /* GPIO_RST */
+ MPP7_SPI_SCn,
MPP8_TW_SDA,
MPP9_TW_SCK,
MPP10_UART0_TXD,
@@ -61,8 +61,8 @@ int board_early_init_f(void)
MPP15_SD_D1,
MPP16_SD_D2,
MPP17_SD_D3,
- MPP18_NF_IO0,
- MPP19_NF_IO1,
+ MPP18_GPO,
+ MPP19_GPO,
MPP20_GE1_0,
MPP21_GE1_1,
MPP22_GE1_2,
diff --git a/board/Marvell/dreamplug/kwbimage.cfg
b/board/Marvell/dreamplug/kwbimage.cfg
index 2afd927..ae76b32 100644
--- a/board/Marvell/dreamplug/kwbimage.cfg
+++ b/board/Marvell/dreamplug/kwbimage.cfg
@@ -26,9 +26,7 @@
#
# Boot Media configurations
-BOOT_FROM nand
-NAND_ECC_MODE default
-NAND_PAGE_SIZE 0x0800
+BOOT_FROM spi
# SOC registers configuration using bootrom header extension
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h
index 7b494cc..bf477b2 100644
--- a/include/configs/dreamplug.h
+++ b/include/configs/dreamplug.h
@@ -47,7 +47,7 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FAT
-#define CONFIG_CMD_NAND
+#define CONFIG_CMD_SF
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#define CONFIG_CMD_IDE
--
1.7.0.4
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[U-Boot] [PATCH 2/3] dreamplug: include in 'make all'
From: Jason Cooper Signed-off-by: Jason Cooper --- MAKEALL |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/MAKEALL b/MAKEALL index d592374..35fc5b7 100755 --- a/MAKEALL +++ b/MAKEALL @@ -345,6 +345,7 @@ LIST_ARM9=" \ edb9315a\ edminiv2\ guruplug\ + dreamplug \ imx27lite \ jadecpu \ lpd7a400\ -- 1.7.0.4 _______ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/3 v2] RFC: Dreamplug support
From: Jason Cooper It compiles clean, and I've loaded it via JTAG and used it to dump the existing bootloader out of the SPI flash. I have _not_ used it to burn itself to the flash yet. I'm looking for comments before I try that. ;-) Some concerns: 1.) does the 'make all' support need to be last? I've used rebase to edit patches and commits, but I've never reshuffled. Each patch compiles clean. FIXED in v2. 2.) The SPI flash chip is a Macronix MX25L1606, however it has the identical chip idcode to the MX25L1605. How is that properly handled? The 06 does have some new features [1]. 3.) I added the board number [2], etc to asm/mach-types.h even though it says to not to. ;-) Is there a proper way to do it? If it's copied from the Linux kernel, it hasn't been updated in a while... [1] http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/5F41CDDCB837422C48257639003E5EC3/$File/AN055-Migrate_to_MX25L1606E_and_MX25L8006E-1.2.pdf [2] http://www.arm.linux.org.uk/developer/machines/list.php?id=3550 Changes from v1 to v2: - resorted series to move 'make all' support last. Jason Cooper (3): dreamplug: Initial support. dreamplug: switch from NAND flash to SPI flash. dreamplug: include in 'make all' MAKEALL |1 + arch/arm/include/asm/mach-types.h| 13 +++ board/Marvell/dreamplug/Makefile | 51 +++ board/Marvell/dreamplug/dreamplug.c | 153 board/Marvell/dreamplug/dreamplug.h | 39 board/Marvell/dreamplug/kwbimage.cfg | 160 ++ boards.cfg |1 + include/configs/dreamplug.h | 111 +++ 8 files changed, 529 insertions(+), 0 deletions(-) create mode 100644 board/Marvell/dreamplug/Makefile create mode 100644 board/Marvell/dreamplug/dreamplug.c create mode 100644 board/Marvell/dreamplug/dreamplug.h create mode 100644 board/Marvell/dreamplug/kwbimage.cfg create mode 100644 include/configs/dreamplug.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3 v2] dreamplug: switch from NAND flash to SPI flash.
From: Jason Cooper
MPP._SPI_ configuration copied from
boards/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
Signed-off-by: Jason Cooper
---
board/Marvell/dreamplug/dreamplug.c | 18 +-
board/Marvell/dreamplug/kwbimage.cfg |4 +---
include/configs/dreamplug.h |2 +-
3 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/board/Marvell/dreamplug/dreamplug.c
b/board/Marvell/dreamplug/dreamplug.c
index 32d82ba..6442396 100644
--- a/board/Marvell/dreamplug/dreamplug.c
+++ b/board/Marvell/dreamplug/dreamplug.c
@@ -43,14 +43,14 @@ int board_early_init_f(void)
/* Multi-Purpose Pins Functionality configuration */
u32 kwmpp_config[] = {
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
+ MPP0_SPI_SCn,
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ MPP4_GPIO,
+ MPP5_GPO,
MPP6_SYSRST_OUTn,
- MPP7_GPO, /* GPIO_RST */
+ MPP7_SPI_SCn,
MPP8_TW_SDA,
MPP9_TW_SCK,
MPP10_UART0_TXD,
@@ -61,8 +61,8 @@ int board_early_init_f(void)
MPP15_SD_D1,
MPP16_SD_D2,
MPP17_SD_D3,
- MPP18_NF_IO0,
- MPP19_NF_IO1,
+ MPP18_GPO,
+ MPP19_GPO,
MPP20_GE1_0,
MPP21_GE1_1,
MPP22_GE1_2,
diff --git a/board/Marvell/dreamplug/kwbimage.cfg
b/board/Marvell/dreamplug/kwbimage.cfg
index 2afd927..ae76b32 100644
--- a/board/Marvell/dreamplug/kwbimage.cfg
+++ b/board/Marvell/dreamplug/kwbimage.cfg
@@ -26,9 +26,7 @@
#
# Boot Media configurations
-BOOT_FROM nand
-NAND_ECC_MODE default
-NAND_PAGE_SIZE 0x0800
+BOOT_FROM spi
# SOC registers configuration using bootrom header extension
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h
index 7b494cc..bf477b2 100644
--- a/include/configs/dreamplug.h
+++ b/include/configs/dreamplug.h
@@ -47,7 +47,7 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FAT
-#define CONFIG_CMD_NAND
+#define CONFIG_CMD_SF
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#define CONFIG_CMD_IDE
--
1.7.0.4
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[U-Boot] [PATCH 3/3 v2] dreamplug: include in 'make all'
From: Jason Cooper Signed-off-by: Jason Cooper --- MAKEALL |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/MAKEALL b/MAKEALL index d592374..35fc5b7 100755 --- a/MAKEALL +++ b/MAKEALL @@ -345,6 +345,7 @@ LIST_ARM9=" \ edb9315a\ edminiv2\ guruplug\ + dreamplug \ imx27lite \ jadecpu \ lpd7a400\ -- 1.7.0.4 _______ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3 v2] dreamplug: Initial support.
; "\
+ "bootm 0x640;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "x_bootcmd_ethernet=ping 192.168.2.1\0" \
+ "x_bootcmd_usb=usb start\0" \
+ "x_bootcmd_kernel=nand read.e 0x640 0x10 0x40\0" \
+ "x_bootargs=console=ttyS0,115200\0" \
+ "x_bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
+#define CONFIG_PHY_BASE_ADR0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+#endif /* _CONFIG_DREAMPLUG_H */
--
1.7.0.4
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[U-Boot] [PATCH 0/1 v3] Dreamplug support
From: Jason Cooper It compiles clean, and I've loaded it via JTAG and used it to dump the existing bootloader out of the SPI flash. I have _not_ used it to burn itself to the flash yet. I'm looking for comments before I try that. ;-) Some concerns: - The SPI flash chip is a Macronix MX25L1606, however it has the identical chip idcode to the MX25L1605. How is that properly handled? The 06 does have some new features [1]. [1] http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/5F41CDDCB837422C48257639003E5EC3/$File/AN055-Migrate_to_MX25L1606E_and_MX25L8006E-1.2.pdf Changes from v1 to v2: - resorted series to move 'make all' support last. Changes from v2 to v3: - Use MACH_TYPE_GURUPLUG for now until dreamplug support is in Linux. - Update MAINTAINERS. - Collapse into one patch Jason Cooper (1): dreamplug: Initial support. MAINTAINERS |1 + MAKEALL |1 + board/Marvell/dreamplug/Makefile | 51 +++ board/Marvell/dreamplug/dreamplug.c | 154 board/Marvell/dreamplug/dreamplug.h | 39 board/Marvell/dreamplug/kwbimage.cfg | 160 ++ boards.cfg |1 + include/configs/dreamplug.h | 111 +++ 8 files changed, 518 insertions(+), 0 deletions(-) create mode 100644 board/Marvell/dreamplug/Makefile create mode 100644 board/Marvell/dreamplug/dreamplug.c create mode 100644 board/Marvell/dreamplug/dreamplug.h create mode 100644 board/Marvell/dreamplug/kwbimage.cfg create mode 100644 include/configs/dreamplug.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/1] dreamplug: Initial support.
From: Jason Cooper Copied files from boards/Marvell/guruplug/ and did s/GURUPLUG/DREAMPLUG/g s/guruplug/dreamplug/g Switched from NAND flash to SPI flash. MPP._SPI_ configuration copied from boards/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c Also, MACH_TYPE_DREAMPLUG (board id 3550) has been registered at http://www.arm.linux.co.uk/developer/machines/, once support has been added to mainline Linux, we'll update the board id here. For now, we use MACH_TYPE_GURUPLUG, just as the factory U-Boot does. Signed-off-by: Jason Cooper --- MAINTAINERS |1 + MAKEALL |1 + board/Marvell/dreamplug/Makefile | 51 +++ board/Marvell/dreamplug/dreamplug.c | 154 board/Marvell/dreamplug/dreamplug.h | 39 board/Marvell/dreamplug/kwbimage.cfg | 160 ++ boards.cfg |1 + include/configs/dreamplug.h | 111 +++ 8 files changed, 518 insertions(+), 0 deletions(-) create mode 100644 board/Marvell/dreamplug/Makefile create mode 100644 board/Marvell/dreamplug/dreamplug.c create mode 100644 board/Marvell/dreamplug/dreamplug.h create mode 100644 board/Marvell/dreamplug/kwbimage.cfg create mode 100644 include/configs/dreamplug.h diff --git a/MAINTAINERS b/MAINTAINERS index c462ae2..c3711a8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -202,6 +202,7 @@ Niklaus Giger Siddarth Gore guruplugARM926EJS (Kirkwood SoC) + dreamplug ARM926EJS (Kirkwood SoC) Paul Gortmaker diff --git a/MAKEALL b/MAKEALL index d592374..35fc5b7 100755 --- a/MAKEALL +++ b/MAKEALL @@ -345,6 +345,7 @@ LIST_ARM9=" \ edb9315a\ edminiv2\ guruplug\ + dreamplug \ imx27lite \ jadecpu \ lpd7a400\ diff --git a/board/Marvell/dreamplug/Makefile b/board/Marvell/dreamplug/Makefile new file mode 100644 index 000..b7e5270 --- /dev/null +++ b/board/Marvell/dreamplug/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Siddarth Gore +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS := dreamplug.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c new file mode 100644 index 000..3797af1 --- /dev/null +++ b/board/Marvell/dreamplug/dreamplug.c @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Siddarth Gore + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "dreamplug.h" + +DECLARE_GLO
[U-Boot] [PATCH 0/1 v4] RFC: Dreamplug support
From: Jason Cooper It compiles clean, and I've loaded it via JTAG and used it to dump the existing bootloader out of the SPI flash. I have _not_ used it to burn itself to the flash yet. I'm looking for comments before I try that. ;-) Some concerns: - The SPI flash chip is a Macronix MX25L1606, however it has the identical chip idcode to the MX25L1605. How is that properly handled? The 06 does have some new features [1]. [1] http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/5F41CDDCB837422C48257639003E5EC3/$File/AN055-Migrate_to_MX25L1606E_and_MX25L8006E-1.2.pdf Changes from v1 to v2: - resorted series to move 'make all' support last. Changes from v2 to v3: - Use MACH_TYPE_GURUPLUG for now until dreamplug support is in Linux. - Update MAINTAINERS. - Collapse into one patch. Changes from v3 to v4: - update copyright info as recommended by Prafulla Wadaskar. - maintain proper order in boards.cfg, MAINTAINERS, etc. - label MPP's - change back to MACH_TYPE_DREAMPLUG. This patch is just RFC until the Dreamplug is supported in Linux (and MACH_TYPE_ added). Jason Cooper (1): dreamplug: Initial support. MAINTAINERS |4 + MAKEALL |1 + board/Marvell/dreamplug/Makefile | 54 +++ board/Marvell/dreamplug/dreamplug.c | 157 board/Marvell/dreamplug/dreamplug.h | 42 + board/Marvell/dreamplug/kwbimage.cfg | 163 ++ boards.cfg |1 + include/configs/dreamplug.h | 114 8 files changed, 536 insertions(+), 0 deletions(-) create mode 100644 board/Marvell/dreamplug/Makefile create mode 100644 board/Marvell/dreamplug/dreamplug.c create mode 100644 board/Marvell/dreamplug/dreamplug.h create mode 100644 board/Marvell/dreamplug/kwbimage.cfg create mode 100644 include/configs/dreamplug.h ___________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/1 v4] RFC: dreamplug: Initial support.
et}; setenv ethact egiga1; " \
+ "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
+ "setenv bootargs ${x_bootargs} ${x_bootargs_root}; "\
+ "bootm 0x640;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "x_bootcmd_ethernet=ping 192.168.2.1\0" \
+ "x_bootcmd_usb=usb start\0" \
+ "x_bootcmd_kernel=nand read.e 0x640 0x10 0x40\0" \
+ "x_bootargs=console=ttyS0,115200\0" \
+ "x_bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
+#define CONFIG_PHY_BASE_ADR0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+#endif /* _CONFIG_DREAMPLUG_H */
--
1.7.0.4
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[U-Boot] [PATCH 1/1] usb: Some EHCI chipsets are slow to respond.
From: Jason Cooper
This fixes 'EHCI timed out on TD...' on the dreamplug board.
Signed-off-by: Jason Cooper
---
include/usb.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/usb.h b/include/usb.h
index 53603a5..168e2b2 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -46,7 +46,7 @@
* This is the timeout to allow for submitting an urb in ms. We allow more
* time for a BULK device to react - some are slow.
*/
-#define USB_TIMEOUT_MS(pipe) (usb_pipebulk(pipe) ? 5000 : 100)
+#define USB_TIMEOUT_MS(pipe) (usb_pipebulk(pipe) ? 5000 : 500)
/* device request (setup) */
struct devrequest {
--
1.7.0.4
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[U-Boot] [PATCH] drivers/rtc: add Marvell Integrated RTC.
From: Jason Cooper
rewrite of the not-merged code from Globalscale Technologies. This RTC is
known to exist in the DreamPlug platform and is accessed via two registers.
Signed-off-by: Jason Cooper
---
Questions:
- I completely rewrote this, should I add mention of Commercial/GPL2+/BSD
(pick your license) source files I based it on?
http://people.debian.org/~clint/dreamplug/dreamplug-uboot-gti.tar.gz
- The link is a dirty git tree. The uncommitted stuff is how they
modified Guruplug u-boot to work on the Dreamplug.
- chmod -x the changed files to undo the windows fs stuff.
- the usb storage changes are already in.
- I'm close on the SPI flash stuff.
- This patch is the RTC driver.
- Their MPP cfg is cleaner than mine, I'll use theirs.
- I'll add the clock stuff in a future patch.
- I feel that register definitions should be somewhere else, like SoC code.
But I don't know if this is Dreamplug-specific, kirkwood-specific, or other?
- common/cmd_date.c assumes I2C interface, is that harmless?
- common/cmd_date.c checks return value. The register ops have no return
value. I assume it's safe to always return zero?
- Is there an easy way to calc the day of the year based on the info in the
date register? I don't like leaving that set ot zero.
- This is compile-tested. Once I get back to my Dreamplug, I will test.
- checkpatch has 2 warnings about volatile. My understanding is that it is
needed when reading/writing registers.
drivers/rtc/Makefile|1 +
drivers/rtc/mvinteg_rtc.c | 151 +++
drivers/rtc/mvinteg_rtc.h | 89 +
include/configs/dreamplug.h |8 ++
4 files changed, 249 insertions(+), 0 deletions(-)
create mode 100644 drivers/rtc/mvinteg_rtc.c
create mode 100644 drivers/rtc/mvinteg_rtc.h
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index e4be4a4..ed63e9c 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -55,6 +55,7 @@ COBJS-$(CONFIG_MCFRTC) += mcfrtc.o
COBJS-$(CONFIG_RTC_MK48T59) += mk48t59.o
COBJS-$(CONFIG_RTC_MPC5200) += mpc5xxx.o
COBJS-$(CONFIG_RTC_MPC8xx) += mpc8xx.o
+COBJS-$(CONFIG_RTC_MVINTEG) += mvinteg_rtc.o
COBJS-$(CONFIG_RTC_PCF8563) += pcf8563.o
COBJS-$(CONFIG_RTC_PL031) += pl031.o
COBJS-$(CONFIG_RTC_PT7C4338) += pt7c4338.o
diff --git a/drivers/rtc/mvinteg_rtc.c b/drivers/rtc/mvinteg_rtc.c
new file mode 100644
index 000..1fcfba5
--- /dev/null
+++ b/drivers/rtc/mvinteg_rtc.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2011
+ * Jason Cooper
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Date & Time support for Marvell Integrated RTC
+ */
+
+#include
+#include
+#include
+#include "mvinteg_rtc.h"
+
+/* This RTC does not support century, so we assume 20 */
+#define CENTURY 20
+
+int rtc_get(struct rtc_time *t)
+{
+ u32 time;
+ u32 date;
+ u8 tens;
+ u8 single;
+
+ /* read the time register */
+ time = MV_REG_READ(MVINTEG_RTCTIME_REG);
+
+ /* read the date register */
+ date = MV_REG_READ(MVINTEG_RTCDATE_REG);
+
+ /* seconds */
+ tens = ((time & MVINTEG_10SEC_MSK) >> MVINTEG_10SEC_SFT);
+ single = ((time & MVINTEG_SEC_MSK) >> MVINTEG_SEC_SFT);
+ t->tm_sec = 10 * tens + single;
+
+ /* minutes */
+ tens = ((time & MVINTEG_10MIN_MSK) >> MVINTEG_10MIN_SFT);
+ single = ((time & MVINTEG_MIN_MSK) >> MVINTEG_MIN_SFT);
+ t->tm_min = 10 * tens + single;
+
+ /* hours */
+ tens = ((time & MVINTEG_10HOUR_MSK) >> MVINTEG_10HOUR_SFT);
+ single = ((time & MVINTEG_HOUR_MSK) >> MVINTEG_HOUR_SFT);
+ t->tm_hour = 10 * tens + single;
+
+ /* day */
+ t->tm_wday = ((time & MVINTEG_DAY_MSK) >> MVINTEG_DAY_SFT);
+ t->tm_wday--;
+
+ /* date */
+ tens = ((date & MVINTEG_10DATE_MSK) >> MVINTEG_10DATE_SFT);
+ single = ((date & MVINTEG_DATE_MSK) >>
[U-Boot] unassigned-patches/36: [PATCH] NetLoop initialization bug
The patch fixes the bug of partial initialization of global network
parameters.
Upon u-boot's start up the first ping command causes a failure of the
consequent TFTP command. It happens in the recently added mechanism of
the NetLoop initialization where initialization of global network
parameters is separated in the NetInitLoop routine which is called per
env_id change. Thus, ping request will initialize the network parameters
necessary for ping operation only, afterwards the env_changed_id will be
set to the env_id that will prevent all following initialization requests
from other protocols.
The problem is that the initialized by ping subset of network parameters
is not sufficient for other protocols and particularly for TFTP which
requires the NetServerIp also.
Signed-off-by: Michael Zaidman
---
Added to GNATS database as unassigned-patches/36
>Responsible:patch-coord
>Message-Id: <1238789765-8024-1-git-send-email-michael.zaid...@gmail.com>
>In-Reply-To:
>References:
>Patch-Date: Fri Apr 03 22:16:05 +0200 2009
---
net/net.c | 61 +++--
1 files changed, 3 insertions(+), 58 deletions(-)
diff --git a/net/net.c b/net/net.c
index a89f6a0..97883df 100644
--- a/net/net.c
+++ b/net/net.c
@@ -285,67 +285,15 @@ NetInitLoop(proto_t protocol)
int env_id = get_env_id ();
/* update only when the environment has changed */
- if (env_changed_id == env_id)
- return 0;
-
- switch (protocol) {
-#if defined(CONFIG_CMD_NFS)
- case NFS:
-#endif
-#if defined(CONFIG_CMD_PING)
- case PING:
-#endif
-#if defined(CONFIG_CMD_SNTP)
- case SNTP:
-#endif
- case NETCONS:
- case TFTP:
+ if (env_changed_id != env_id) {
NetCopyIP(&NetOurIP, &bd->bi_ip_addr);
NetOurGatewayIP = getenv_IPaddr ("gatewayip");
NetOurSubnetMask= getenv_IPaddr ("netmask");
- NetOurVLAN = getenv_VLAN("vlan");
- NetOurNativeVLAN = getenv_VLAN("nvlan");
-
- switch (protocol) {
-#if defined(CONFIG_CMD_NFS)
- case NFS:
-#endif
- case NETCONS:
- case TFTP:
- NetServerIP = getenv_IPaddr ("serverip");
- break;
-#if defined(CONFIG_CMD_PING)
- case PING:
- /* nothing */
- break;
-#endif
-#if defined(CONFIG_CMD_SNTP)
- case SNTP:
- /* nothing */
- break;
-#endif
- default:
- break;
- }
-
- break;
- case BOOTP:
- case RARP:
- /*
-* initialize our IP addr to 0 in order to accept ANY
-* IP addr assigned to us by the BOOTP / RARP server
-*/
- NetOurIP = 0;
NetServerIP = getenv_IPaddr ("serverip");
- NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */
- NetOurNativeVLAN = getenv_VLAN("nvlan");
- case CDP:
- NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */
NetOurNativeVLAN = getenv_VLAN("nvlan");
- break;
- default:
- break;
+ NetOurVLAN = getenv_VLAN("vlan");
}
+
env_changed_id = env_id;
return 0;
}
@@ -440,10 +388,7 @@ restart:
#if defined(CONFIG_CMD_DHCP)
case DHCP:
- /* Start with a clean slate... */
BootpTry = 0;
- NetOurIP = 0;
- NetServerIP = getenv_IPaddr ("serverip");
DhcpRequest(); /* Basically same as BOOTP */
break;
#endif
--
1.5.6.3
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Re: [U-Boot] bugs/36
Synopsis: [U-Boot][PATCH] NetLoop initialization bug Responsible-Changed-From-To: patch-coord->gu-net Responsible-Changed-By: wd Responsible-Changed-When: Fri, 03 Apr 2009 22:31:14 +0200 Responsible-Changed-Why: Assigned to Ben ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/37: [PATCH] NetLoop initialization bug
The patch fixes the bug of partial initialization of global network
parameters.
Upon u-boot's start up the first ping command causes a failure of the
consequent TFTP command. It happens in the recently added mechanism of
the NetLoop initialization where initialization of global network
parameters is separated in the NetInitLoop routine which is called per
env_id change. Thus, ping request will initialize the network parameters
necessary for ping operation only, afterwards the env_changed_id will be
set to the env_id that will prevent all following initialization requests
from other protocols.
The problem is that the initialized by ping subset of network parameters
is not sufficient for other protocols and particularly for TFTP which
requires the NetServerIp also.
Signed-off-by: Michael Zaidman
---
Added to GNATS database as unassigned-patches/37
>Responsible:patch-coord
>Message-Id: <1238798580-8828-1-git-send-email-michael.zaid...@gmail.com>
>In-Reply-To:
>References:
>Patch-Date: Sat Apr 04 00:43:00 +0200 2009
---
net/net.c | 63 +++-
1 files changed, 4 insertions(+), 59 deletions(-)
diff --git a/net/net.c b/net/net.c
index a89f6a0..b8648bd 100644
--- a/net/net.c
+++ b/net/net.c
@@ -285,68 +285,16 @@ NetInitLoop(proto_t protocol)
int env_id = get_env_id ();
/* update only when the environment has changed */
- if (env_changed_id == env_id)
- return 0;
-
- switch (protocol) {
-#if defined(CONFIG_CMD_NFS)
- case NFS:
-#endif
-#if defined(CONFIG_CMD_PING)
- case PING:
-#endif
-#if defined(CONFIG_CMD_SNTP)
- case SNTP:
-#endif
- case NETCONS:
- case TFTP:
+ if (env_changed_id != env_id) {
NetCopyIP(&NetOurIP, &bd->bi_ip_addr);
NetOurGatewayIP = getenv_IPaddr ("gatewayip");
NetOurSubnetMask= getenv_IPaddr ("netmask");
- NetOurVLAN = getenv_VLAN("vlan");
- NetOurNativeVLAN = getenv_VLAN("nvlan");
-
- switch (protocol) {
-#if defined(CONFIG_CMD_NFS)
- case NFS:
-#endif
- case NETCONS:
- case TFTP:
- NetServerIP = getenv_IPaddr ("serverip");
- break;
-#if defined(CONFIG_CMD_PING)
- case PING:
- /* nothing */
- break;
-#endif
-#if defined(CONFIG_CMD_SNTP)
- case SNTP:
- /* nothing */
- break;
-#endif
- default:
- break;
- }
-
- break;
- case BOOTP:
- case RARP:
- /*
-* initialize our IP addr to 0 in order to accept ANY
-* IP addr assigned to us by the BOOTP / RARP server
-*/
- NetOurIP = 0;
NetServerIP = getenv_IPaddr ("serverip");
- NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */
- NetOurNativeVLAN = getenv_VLAN("nvlan");
- case CDP:
- NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */
NetOurNativeVLAN = getenv_VLAN("nvlan");
- break;
- default:
- break;
+ NetOurVLAN = getenv_VLAN("vlan");
+ env_changed_id = env_id;
}
- env_changed_id = env_id;
+
return 0;
}
@@ -440,10 +388,7 @@ restart:
#if defined(CONFIG_CMD_DHCP)
case DHCP:
- /* Start with a clean slate... */
BootpTry = 0;
- NetOurIP = 0;
- NetServerIP = getenv_IPaddr ("serverip");
DhcpRequest(); /* Basically same as BOOTP */
break;
#endif
--
1.5.6.3
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[U-Boot] unassigned-patches/34: [PATCH] Add support for setting environment variable from RAM.
This is useful for allowing scripts to read environment variables from
file, among other things.
This is a slightly modified version of what Alessandro submitted to the
mailing list last July:
http://www.mail-archive.com/u-boot-us...@lists.sourceforge.net/msg07932.html
I changed the name from 'setenvram' to 'ramenv' to prevent breakage of scripts
that use the abbreviation 'set' (which my handss have the habit of doing).
Signed-off-by: Eric Nelson
---
Added to GNATS database as unassigned-patches/34
>Responsible:patch-coord
>Message-Id:
><1233611420-21083-1-git-send-email-eric.nel...@boundarydevices.com>
>In-Reply-To:
>References:
>Patch-Date: Mon Feb 02 22:50:20 +0100 2009
---
common/cmd_nvedit.c | 46 ++
1 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index 1fcb4c9..bcb6d9f 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -494,6 +494,44 @@ int do_askenv ( cmd_tbl_t *cmdtp, int flag, int argc, char
*argv[])
#endif
/
+ * Set a new environment variable from RAM.
+ * Requires three arguments: the variable name, a memory address and a length.
+ *
+ * Deletes the environment variable if the length is zero.
+ */
+int do_ramenv(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned long len, i;
+ char *addr;
+
+ if (argc != 4) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+ addr = (char *)simple_strtol(argv[2], NULL, 16);
+ len = simple_strtol(argv[3], NULL, 16);
+ if (!addr || !len) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+ addr[len] = '\0';
+ for (i = 0; i < len; i++) {
+ /* turn newlines into semicolon */
+ if (addr[i] == '\n')
+ addr[i] = ';'; /* ignore dos-style newlines */
+ if (addr[i] == '\r')
+ addr[i] = ' '; /* accept sh-comments and discard them */
+ if (addr[i] == '#') {
+ while (addr[i] && addr[i] != '\n')
+ addr[i++] = ' ';
+ i--;
+ }
+ }
+ setenv(argv[1], addr);
+ return 0;
+}
+
+/
* Look up variable from environment,
* return address of storage for that variable,
* or NULL if not found
@@ -605,6 +643,14 @@ U_BOOT_CMD(
"- delete environment variable 'name'\n"
);
+U_BOOT_CMD(
+ ramenv, 4, 0, do_ramenv,
+ "ramenv - get environment variable from ram\n",
+ "name addr maxlen\n"
+ "- set environment variable 'name' from addr 'addr'\n"
+ "- delete environment variable if maxlen is 0\n"
+);
+
#if defined(CONFIG_CMD_ASKENV)
U_BOOT_CMD(
--
1.5.5.1.382.g182fb
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Re: [U-Boot] unassigned-patches/34
Synopsis: [PATCH] Add support for setting environment variable from RAM. Responsible-Changed-From-To: patch-coord->wd Responsible-Changed-By: wd Responsible-Changed-When: Thu, 05 Feb 2009 22:15:06 +0100 Responsible-Changed-Why: Rejected after discussion on ML. State-Changed-From-To: open->closed State-Changed-By: wd State-Changed-When: Thu, 05 Feb 2009 22:15:06 +0100 State-Changed-Why: Rejected after discussion on ML. _______ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/132: Re: [PATCH] x86: minnowmax: add GPIO mapping support
Hi Gabriel, On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau wrote: > Configure the pinctrl as it required to make some IO controllers > working (USB/UART/I2C/...). > The idea would be in the next version to modify the pch GPIO driver and > configure these pins through the device tree. > > These modifications are ported from the coreboot project. > > Signed-off-by: Gabriel Huau > --- > arch/x86/cpu/baytrail/Makefile| 1 + > arch/x86/cpu/baytrail/gpio.c | 206 +++ > arch/x86/include/asm/arch-baytrail/gpio.h | 364 > ++ > arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ > arch/x86/include/asm/arch-baytrail/irq.h | 119 + > arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + > arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ > arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ > board/intel/minnowmax/minnowmax.c | 212 +++ > include/configs/minnowmax.h | 11 + > 10 files changed, 1450 insertions(+) > create mode 100644 arch/x86/cpu/baytrail/gpio.c > create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h > create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h > create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h > create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h > create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h > [snip] > diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h > index 823e051..738c6fa 100644 > --- a/include/configs/minnowmax.h > +++ b/include/configs/minnowmax.h > @@ -69,4 +69,15 @@ > /* Avoid a warning in the Realtek Ethernet driver */ > #define CONFIG_SYS_CACHELINE_SIZE 16 > > +/* > + * Baytrail has 3 GPIOs bank over PCI, there is no > + * driver at the moment so let's disable the command > + * and the default x86 driver to avoid any collision > + * with the GPIO mapping code. > + * @TODO: adding a baytrail-gpio driver and configure > + * the muxing through the device tree > + */ > +#undef CONFIG_INTEL_ICH6_GPIO > +#undef CONFIG_CMD_GPIO > + Why undef these two? The BayTrail SoC does support GPIO banks in the legacy bridge. > #endif /* __CONFIG_H */ > -- Regards, Bin --- Added to GNATS database as unassigned-patches/132 >Responsible:patch-coord >Message-Id: > >In-Reply-To:<1424037328-31636-1-git-send-email-cont...@huau-gabriel.fr> >References: <1424037328-31636-1-git-send-email-cont...@huau-gabriel.fr> >Patch-Date: Wed Feb 25 08:52:14 +0100 2015 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/133: Re: [PATCH] x86: minnowmax: add GPIO mapping support
Hi Simon,
With a little bit of delay here are the responses ... :)
On 02/17/2015 08:04 PM, Simon Glass wrote:
> Hi Gabriel,
>
> On 15 February 2015 at 14:55, Gabriel Huau wrote:
>> Configure the pinctrl as it required to make some IO controllers
>> working (USB/UART/I2C/...).
>> The idea would be in the next version to modify the pch GPIO driver and
>> configure these pins through the device tree.
>>
>> These modifications are ported from the coreboot project.
>>
>> Signed-off-by: Gabriel Huau
> Thanks for the patch!
>
> I have mostly nits except for one comment about register access which
> is different in U-Boot...
I read all the comments and I agree on almost all of them but I have
some questions.
>> +
>> + /* Add correct func to GPIO pad config */
>> + pad_conf0 = config->pad_conf0;
>> + if (config->is_gpio) {
>> + if (gpio >= bank->gpio_f1_range_start &&
>> + gpio <= bank->gpio_f1_range_end)
>> + pad_conf0 |= PAD_FUNC1;
>> + else
>> + pad_conf0 |= PAD_FUNC0;
>> + }
>> +
>> + writel(reg + PAD_CONF0_REG, pad_conf0);
>> + writel(reg + PAD_CONF1_REG, config->pad_conf1);
>> + writel(reg + PAD_VAL_REG, config->pad_val);
>> + }
>> +
>> + if (bank->legacy_base != GP_LEGACY_BASE_NONE)
>> + for (set = 0; set <= (bank->gpio_count - 1) / 32; ++set) {
>> + reg = bank->legacy_base + 0x20 * set;
>> +
>> + outl(use_sel[set], reg + LEGACY_USE_SEL_REG);
>> + outl(io_sel[set], reg + LEGACY_IO_SEL_REG);
>> + outl(gp_lvl[set], reg + LEGACY_GP_LVL_REG);
>> + outl(tpe[set], reg + LEGACY_TPE_REG);
>> + outl(tne[set], reg + LEGACY_TNE_REG);
>> +
>> + /* TS registers are WOC */
> If you know what this comment means, please spell it out without
> abbreviations.
Actually, I don't know the meaning of WOC and I couldn't find a
definition in the datasheet.
>
>> + outl(0, reg + LEGACY_TS_REG);
>> +
>> + if (bank->has_wake_en)
>> + outl(wake_en[set], reg + LEGACY_WAKE_EN_REG);
>> + }
>> +}
>> +
>> +static void setup_gpio_route(const struct byt_gpio_map *sus,
>> + const struct byt_gpio_map *core)
>> +{
>> + uint32_t route_reg = 0;
>> + int i;
>> +
>> + for (i = 0; i < 8; i++) {
>> + /* SMI takes precedence and wake_en implies SCI. */
>> + if (sus[i].smi)
>> + route_reg |= ROUTE_SMI << (2 * i);
>> + else if (sus[i].sci)
>> + route_reg |= ROUTE_SCI << (2 * i);
>> +
>> + if (core[i].smi)
>> + route_reg |= ROUTE_SMI << (2 * (i + 8));
>> + else if (core[i].sci)
>> + route_reg |= ROUTE_SCI << (2 * (i + 8));
>> + }
> What happens to route_reg after this? I don't see it get returned.
>
I will remove the code, actually it was used when the SMI was enabled.
>> +
>> +#define GPIO_LEVEL_LOW 0
>> +#define GPIO_LEVEL_HIGH1
>> +
>> +#define GPIO_PEDGE_DISABLE 0
>> +#define GPIO_PEDGE_ENABLE 1
>> +
>> +#define GPIO_NEDGE_DISABLE 0
>> +#define GPIO_NEDGE_ENABLE 1
>> +
>> +/* config0[29] - Disable second mask */
>> +#define PAD_MASK2_DISABLE (1 << 29)
>> +
>> +/* config0[27] - Direct Irq En */
>> +#define PAD_IRQ_EN (1 << 27)
>> +
>> +/* config0[26] - gd_tne */
>> +#define PAD_TNE_IRQ(1 << 26)
>> +
>> +/* config0[25] - gd_tpe */
>> +#define PAD_TPE_IRQ(1 << 25)
>> +
>> +/* config0[24] - Gd Level */
>> +#define PAD_LEVEL_IRQ (1 << 24)
>> +#define PAD_EDGE_IRQ (0 << 24)
>> +
>> +/* config0[17] - Slow clkgate / glitch filter */
>> +#define PAD_SLOWGF_ENABLE (1 << 17)
>> +
>> +/* config0[16] - Fast clkgate / glitch filter */
>> +#define PAD_FASTGF_ENABLE (1 << 16)
>> +
>> +/* config0[15] - Hysteresis enable (inverted) *
[U-Boot] unassigned-patches/134: Re: [PATCH] x86: minnowmax: add GPIO mapping support
Hi Bin, On 02/24/2015 11:52 PM, Bin Meng wrote: > Hi Gabriel, > > On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau wrote: >> Configure the pinctrl as it required to make some IO controllers >> working (USB/UART/I2C/...). >> The idea would be in the next version to modify the pch GPIO driver and >> configure these pins through the device tree. >> >> These modifications are ported from the coreboot project. >> >> Signed-off-by: Gabriel Huau >> --- >> arch/x86/cpu/baytrail/Makefile| 1 + >> arch/x86/cpu/baytrail/gpio.c | 206 +++ >> arch/x86/include/asm/arch-baytrail/gpio.h | 364 >> ++ >> arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ >> arch/x86/include/asm/arch-baytrail/irq.h | 119 + >> arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + >> arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ >> arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ >> board/intel/minnowmax/minnowmax.c | 212 +++ >> include/configs/minnowmax.h | 11 + >> 10 files changed, 1450 insertions(+) >> create mode 100644 arch/x86/cpu/baytrail/gpio.c >> create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h >> create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h >> create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h >> create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h >> create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h >> > [snip] > >> diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h >> index 823e051..738c6fa 100644 >> --- a/include/configs/minnowmax.h >> +++ b/include/configs/minnowmax.h >> @@ -69,4 +69,15 @@ >> /* Avoid a warning in the Realtek Ethernet driver */ >> #define CONFIG_SYS_CACHELINE_SIZE 16 >> >> +/* >> + * Baytrail has 3 GPIOs bank over PCI, there is no >> + * driver at the moment so let's disable the command >> + * and the default x86 driver to avoid any collision >> + * with the GPIO mapping code. >> + * @TODO: adding a baytrail-gpio driver and configure >> + * the muxing through the device tree >> + */ >> +#undef CONFIG_INTEL_ICH6_GPIO >> +#undef CONFIG_CMD_GPIO >> + > Why undef these two? The BayTrail SoC does support GPIO banks in the > legacy bridge. I might misunderstood the GPIO subsystem but I thought there was 2 banks available through the PCU iLB GPIO controller which contains the SCORE and SSUS (102 / 44 pins). The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it was just a different controller from the Baytrail, but if I can use it to control all the GPIOs + doing the IO mapping, I'll be glad to do it! > >> #endif /* __CONFIG_H */ >> -- > Regards, > Bin Regards, Gabriel --- Added to GNATS database as unassigned-patches/134 >Responsible:patch-coord >Message-Id: <54edf800.8060...@huau-gabriel.fr> >In-Reply-To: > >References: <1424037328-31636-1-git-send-email-cont...@huau-gabriel.fr> > >Patch-Date: Wed Feb 25 17:27:44 +0100 2015 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/135: Re: [PATCH] x86: minnowmax: add GPIO mapping support
Hi Gabriel, On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau wrote: > Hi Bin, > > > On 02/24/2015 11:52 PM, Bin Meng wrote: >> >> Hi Gabriel, >> >> On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau >> wrote: >>> >>> Configure the pinctrl as it required to make some IO controllers >>> working (USB/UART/I2C/...). >>> The idea would be in the next version to modify the pch GPIO driver and >>> configure these pins through the device tree. >>> >>> These modifications are ported from the coreboot project. >>> >>> Signed-off-by: Gabriel Huau >>> --- >>> arch/x86/cpu/baytrail/Makefile| 1 + >>> arch/x86/cpu/baytrail/gpio.c | 206 +++ >>> arch/x86/include/asm/arch-baytrail/gpio.h | 364 >>> ++ >>> arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ >>> arch/x86/include/asm/arch-baytrail/irq.h | 119 + >>> arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + >>> arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ >>> arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ >>> board/intel/minnowmax/minnowmax.c | 212 +++ >>> include/configs/minnowmax.h | 11 + >>> 10 files changed, 1450 insertions(+) >>> create mode 100644 arch/x86/cpu/baytrail/gpio.c >>> create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h >>> create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h >>> create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h >>> create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h >>> create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h >>> >> [snip] >> >>> diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h >>> index 823e051..738c6fa 100644 >>> --- a/include/configs/minnowmax.h >>> +++ b/include/configs/minnowmax.h >>> @@ -69,4 +69,15 @@ >>> /* Avoid a warning in the Realtek Ethernet driver */ >>> #define CONFIG_SYS_CACHELINE_SIZE 16 >>> >>> +/* >>> + * Baytrail has 3 GPIOs bank over PCI, there is no >>> + * driver at the moment so let's disable the command >>> + * and the default x86 driver to avoid any collision >>> + * with the GPIO mapping code. >>> + * @TODO: adding a baytrail-gpio driver and configure >>> + * the muxing through the device tree >>> + */ >>> +#undef CONFIG_INTEL_ICH6_GPIO >>> +#undef CONFIG_CMD_GPIO >>> + >> >> Why undef these two? The BayTrail SoC does support GPIO banks in the >> legacy bridge. > > I might misunderstood the GPIO subsystem but I thought there was 2 banks > available through the PCU iLB GPIO controller which contains the SCORE and > SSUS (102 / 44 pins). > The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it > was just a different controller from the Baytrail, but if I can use it to > control all the GPIOs + doing the IO mapping, I'll be glad to do it! I checked the BayTrail datasheet. Its GPIO is in the iLB (legacy bridge), which is the same as other IA chipset (Ivybridge, TunnelCreek, Quark). It has 4 banks in core domain and 2 banks in sus domain. So 6 banks in total. You need define 6 gpio nodes in the minnowmax board dts file. You should be able to use the existing gpio driver to configure. >> >>> #endif /* __CONFIG_H */ >>> -- Regards, Bin --- Added to GNATS database as unassigned-patches/135 >Responsible:patch-coord >Message-Id: > >In-Reply-To:<54edf800.8060...@huau-gabriel.fr> >References: <1424037328-31636-1-git-send-email-cont...@huau-gabriel.fr> > ><54edf800.8060...@huau-gabriel.fr> >Patch-Date: Fri Feb 27 04:30:19 +0100 2015 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/136: Re: [PATCH] x86: minnowmax: add GPIO mapping support
Hi Bin, On 02/26/2015 07:30 PM, Bin Meng wrote: > Hi Gabriel, > > On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau > wrote: >> Hi Bin, >> >> >> On 02/24/2015 11:52 PM, Bin Meng wrote: >>> Hi Gabriel, >>> >>> On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau >>> wrote: >>>> Configure the pinctrl as it required to make some IO controllers >>>> working (USB/UART/I2C/...). >>>> The idea would be in the next version to modify the pch GPIO driver and >>>> configure these pins through the device tree. >>>> >>>> These modifications are ported from the coreboot project. >>>> >>>> Signed-off-by: Gabriel Huau >>>> --- >>>>arch/x86/cpu/baytrail/Makefile| 1 + >>>>arch/x86/cpu/baytrail/gpio.c | 206 +++ >>>>arch/x86/include/asm/arch-baytrail/gpio.h | 364 >>>> ++ >>>>arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ >>>>arch/x86/include/asm/arch-baytrail/irq.h | 119 + >>>>arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + >>>>arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ >>>>arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ >>>>board/intel/minnowmax/minnowmax.c | 212 +++ >>>>include/configs/minnowmax.h | 11 + >>>>10 files changed, 1450 insertions(+) >>>>create mode 100644 arch/x86/cpu/baytrail/gpio.c >>>>create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h >>>>create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h >>>>create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h >>>>create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h >>>>create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h >>>> >>> [snip] >>> >>>> diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h >>>> index 823e051..738c6fa 100644 >>>> --- a/include/configs/minnowmax.h >>>> +++ b/include/configs/minnowmax.h >>>> @@ -69,4 +69,15 @@ >>>>/* Avoid a warning in the Realtek Ethernet driver */ >>>>#define CONFIG_SYS_CACHELINE_SIZE 16 >>>> >>>> +/* >>>> + * Baytrail has 3 GPIOs bank over PCI, there is no >>>> + * driver at the moment so let's disable the command >>>> + * and the default x86 driver to avoid any collision >>>> + * with the GPIO mapping code. >>>> + * @TODO: adding a baytrail-gpio driver and configure >>>> + * the muxing through the device tree >>>> + */ >>>> +#undef CONFIG_INTEL_ICH6_GPIO >>>> +#undef CONFIG_CMD_GPIO >>>> + >>> Why undef these two? The BayTrail SoC does support GPIO banks in the >>> legacy bridge. >> I might misunderstood the GPIO subsystem but I thought there was 2 banks >> available through the PCU iLB GPIO controller which contains the SCORE and >> SSUS (102 / 44 pins). >> The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it >> was just a different controller from the Baytrail, but if I can use it to >> control all the GPIOs + doing the IO mapping, I'll be glad to do it! > I checked the BayTrail datasheet. Its GPIO is in the iLB (legacy > bridge), which is the same as other IA chipset (Ivybridge, > TunnelCreek, Quark). It has 4 banks in core domain and 2 banks in sus > domain. So 6 banks in total. You need define 6 gpio nodes in the > minnowmax board dts file. You should be able to use the existing gpio > driver to configure. Thanks for the clarification! Actually, I saw it today when I was doing some tests and I configured the 6 banks in the devices tree. I also fixed the GPIO base address to 0x48 but I got some issues like the fact I'm reading only 0 from all the registers. The registers are configured to be in the IO Space (0x500), I checked the PCI configuration space to make sure that everything is enabled correctly, but I'm still missing something. Once I'll be able to use these GPIOs, I will update the entire patch to remove the port from Coreboot as this is not necessary. >>>>#endif /* __CONFIG_H */ >>>> -- > Regards, > Bin Regards, Gabriel --- Added to GNATS database as unassigned-patches/136 >Responsible:patch-coord >Message-Id: <54f022b9.8060...@huau-gabriel.fr> >In-Reply-To: > >References: <1424037328-31636-1-git-send-email-cont...@huau-gabriel.fr> > ><54edf800.8060...@huau-gabriel.fr> > >Patch-Date: Fri Feb 27 08:54:33 +0100 2015 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Adding Device Tree Overlays for MIPI-CSI2 Camera and libcamera to u-boot in a buildroot or Yocto Build
Hi, Does anyone have any advice on how to add DTOs needed by libcamera to a u-boot in a buildroot or Yocto build or on whether it's more appropriate to add them as part of u-boot or as another part of the build? We'd like to add Kieran's DTOs https://git.uk.ideasonboard.com/camera/dt-overlays/src/branch/main/arch/arm64/boot/dts/freescale to the buildroot default configuration for Debix Model A SBC https://github.com/buildroot/buildroot/blob/master/configs/polyhex_debix_model_a_defconfig Ideally we'd also like to add the overlays for the Sony IMX 708 Image Sensor used in the RPi V3 camera but these aren't mainline: https://github.com/raspberrypi/linux/blob/rpi-6.12.y/arch/arm/boot/dts/overlays/imx708-overlay.dts https://github.com/raspberrypi/linux/blob/rpi-6.12.y/arch/arm/boot/dts/overlays/imx708.dtsi We're planning to use the Debix Model A SBC or Debix SoM A with SoM A I/O board to prototype a new open source wildlife camera for our work in conservation of tree dwelling endangered dormice https://new-homes-for-old-friends.cairnwater.com/ then after field studies with the prototype design a custom board for an NXP i.MX 8M Plus SoM. The analysis for the new open source wildlife camera is here: https://github.com/William-Robert-Robertson/WildCamera Will
Re: [U-Boot] md,mw commands
Hi V.Balaji, Le 2012-03-06 10:41, VISWANADHULA BALAJI a écrit : Hi, Iam using 256MB RAM on arm11 board.I just tried md,mw commands from uboot like the following mw C80 0x 0x500 here C80 is the 200MB of RAM MCS8142>> md C80 0c80: 0c800010: 0c800020: 0c800030: 0c800040: 0c800050: 0c800060: 0c800070: 0c800080: 0c800090: 0c8000a0: 0c8000b0: 0c8000c0: 0c8000d0: 0c8000e0: 0c8000f0: mw 3200 0x 0x500 here 3200 is the 800MB of RAM MCS8142>> md 3200 3200: 3210: 3220: 3230: 3240: 3250: 3260: 3270: How it is possible to see the data even after the 256MB of RAM.If i give the sizes like 256MB ,512MB mw command get hangs otherwise the data is writing to the RAM even the size exceeds the size of actual RAM. Please help me. Did you check the configuration of your board's memory controller, especially how "chip select" mechanism is mapped onto ARM11 address space? A bad configuration can mirror the actual 256 MB several times over a bigger area -- so address 0 of your RAM would be seen at ARM11 address 0, but also 0x1000, 0x2000, etc. A quick check would be to write something at 0x1000 and then read 0x2000, and see if it mirrors 0x1000. Thanks V.Balaji Amicalement, -- Albert. _______ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 5/7] armv8: layerscape: Eanble falcon boot
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Content preview: Hi, Le Sun, 17 Sep 2017 11:54:56 -0600 Simon Glass
a écrit: > +Philippe for review > > On 14 September 2017 at 13:01, York
Sun wrote: > > Add jump_to_image_linux() for arm64. Add
"noreturn" flag to > > armv8_switch_to_el2(). Add hooks to fsl-layerscape
to enable falcon > > boot. > > > > Signed-off-by: York Sun
> > > > --- > > > > Changes in v2: > > Relace getenv_f() with env_get_f()
after rebasing to latet master. > > > >
.../arm/cpu/armv8/fsl-layerscape/doc/README.falcon
| 140 > > + > > arch/arm/cpu/armv8/fsl-layerscape/spl.c
| 29 + > > arch/arm/include/asm/system.h | 2 +- > > arch/arm/lib/spl.c
| 11 ++ 4 files > > changed, 181 insertions(+), 1 deletion(-) create mode
100644 > > arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon > >
Reviewed-by:
Simon Glass [...]
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--- Begin Message ---
Hi,
Le Sun, 17 Sep 2017 11:54:56 -0600
Simon Glass a écrit:
> +Philippe for review
>
> On 14 September 2017 at 13:01, York Sun wrote:
> > Add jump_to_image_linux() for arm64. Add "noreturn" flag to
> > armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon
> > boot.
> >
> > Signed-off-by: York Sun
> >
> > ---
> >
> > Changes in v2:
> > Relace getenv_f() with env_get_f() after rebasing to latet master.
> >
> > .../arm/cpu/armv8/fsl-layerscape/doc/README.falcon | 140
> > +
> > arch/arm/cpu/armv8/fsl-layerscape/spl.c| 29 +
> > arch/arm/include/asm/system.h | 2 +-
> > arch/arm/lib/spl.c | 11 ++ 4 files
> > changed, 181 insertions(+), 1 deletion(-) create mode 100644
> > arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon
>
> Reviewed-by: Simon Glass
Nitpick: fix typo ("Eanble") in subject (can be done when applying if
no v3 is needed).
Amicalement,
--
Albert.
--- End Message ---
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