Re: [PATCH 4/7] net: dwc_eth_qos: Add glue driver for GMAC on Rockchip RK3568
Hi Jonas,
Thank you for your help.
在 2023/8/7 08:08, Jonas Karlman 写道:
Add a new glue driver for Rockchip SoCs, i.e RK3568, with a GMAC based
on Synopsys DWC Ethernet QoS IP.
rk_gmac_ops was ported from linux commit:
3bb3d6b1c195 ("net: stmmac: Add RK3566/RK3568 SoC support")
Signed-off-by: Jonas Karlman
---
Cc: David Wu
Cc: Ezequiel Garcia
---
drivers/net/Kconfig| 8 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 8 +-
drivers/net/dwc_eth_qos.h | 2 +
drivers/net/dwc_eth_qos_rockchip.c | 348 +
5 files changed, 365 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/dwc_eth_qos_rockchip.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 0ed39a61e4de..29304fd77759 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -225,6 +225,14 @@ config DWC_ETH_QOS_IMX
The Synopsys Designware Ethernet QOS IP block with the specific
configuration used in IMX soc.
+config DWC_ETH_QOS_ROCKCHIP
+ bool "Synopsys DWC Ethernet QOS device support for Rockchip SoCs"
+ depends on DWC_ETH_QOS
+ select DM_ETH_PHY
+ help
+ The Synopsys Designware Ethernet QOS IP block with specific
+ configuration used in Rockchip SoCs.
+
config DWC_ETH_QOS_STM32
bool "Synopsys DWC Ethernet QOS device support for STM32"
depends on DWC_ETH_QOS
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index d4af253b6f28..1d444f5b4a69 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
+obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o
obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
obj-$(CONFIG_E1000) += e1000.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 24fb3fac1f12..9fb98a2c3c74 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1707,7 +1707,12 @@ static const struct udevice_id eqos_ids[] = {
.data = (ulong)&eqos_imx_config
},
#endif
-
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP)
+ {
+ .compatible = "rockchip,rk3568-gmac",
+ .data = (ulong)&eqos_rockchip_config
+ },
+#endif
If this compatible could move to dwc_eth_qos_rockchip.c, it is better,
we have other SoCs that also use this driver in the feature, and it
must increase
this array all the time for new SoCs later, it will be better only change
dwc_eth_qos_rockchip.c, we don't need to change the current file.
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_QCOM)
{
.compatible = "qcom,qcs404-ethqos",
@@ -1720,7 +1725,6 @@ static const struct udevice_id eqos_ids[] = {
.data = (ulong)&eqos_jh7110_config
},
#endif
-
{ }
};
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index 06a082da72ef..e3222e1e17e5 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -82,6 +82,7 @@ struct eqos_mac_regs {
#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT21
#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT8
+#define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1
#define EQOS_MAC_MDIO_ADDRESS_CR_20_352
#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
#define EQOS_MAC_MDIO_ADDRESS_SKAPBIT(4)
@@ -287,5 +288,6 @@ void eqos_flush_buffer_generic(void *buf, size_t size);
int eqos_null_ops(struct udevice *dev);
extern struct eqos_config eqos_imx_config;
+extern struct eqos_config eqos_rockchip_config;
extern struct eqos_config eqos_qcom_config;
extern struct eqos_config eqos_jh7110_config;
diff --git a/drivers/net/dwc_eth_qos_rockchip.c
b/drivers/net/dwc_eth_qos_rockchip.c
new file mode 100644
index ..c8abe351fc3e
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_rockchip.c
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dwc_eth_qos.h"
+
+struct rk_gmac_ops {
+ const char *compatible;
+ int (*set_to_rgmii)(struct udevice *dev,
+ int tx_delay, int rx_delay);
+ int (*set_to_rmii)(struct udevice *dev);
+ int (*set_gmac_speed)(struct udevice *dev);
+ u32 regs[3];
+};
+
+struct rockchip_platform_data {
+ struct reset_ctl_bulk resets;
+ const struct rk_gmac_ops *ops;
+ int id;
+ struct regmap *grf;
+};
+
+#define HIWORD_UPDATE(va
[PATCH] net: eth-uclass: Change uclass driver name to ethernet
dev_read_alias_seq() used uc_drv->name compared to alias
stem string, Ethernet's alias stem uses "ethernet", which
does not match the eth-uclass driver name "eth", can not
get the correct index of ethernet alias namer. So it seems
change uclass driver name to match the alias stem is a more
reasonable way.
Signed-off-by: David Wu
---
net/eth-uclass.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index e14695c0f1..7dd962db64 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -594,7 +594,7 @@ static int eth_pre_remove(struct udevice *dev)
}
UCLASS_DRIVER(eth) = {
- .name = "eth",
+ .name = "ethernet",
.id = UCLASS_ETH,
.post_bind = eth_post_bind,
.pre_unbind = eth_pre_unbind,
--
2.19.1
[PATCH v1] net: eth-uclass: Change uclass driver name to ethernet
dev_read_alias_seq() used uc_drv->name compared to alias
stem string, Ethernet's alias stem uses "ethernet", which
does not match the eth-uclass driver name "eth", can not
get the correct index of ethernet alias namer. So it seems
change uclass driver name to match the alias stem is a more
reasonable way.
Signed-off-by: David Wu
---
net/eth-uclass.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index e14695c0f1..3497a17db6 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -593,8 +593,8 @@ static int eth_pre_remove(struct udevice *dev)
return 0;
}
-UCLASS_DRIVER(eth) = {
- .name = "eth",
+UCLASS_DRIVER(ethernet) = {
+ .name = "ethernet",
.id = UCLASS_ETH,
.post_bind = eth_post_bind,
.pre_unbind = eth_pre_unbind,
--
2.19.1
[PATCH 0/8] Add dwc_eth_qos support for rockchip
Rockchip Socs can support two controllers "snps, dwmac-4.20a" and "snps, dwmac-3.50". In order to support two at gmac-rockchip.c, export public interface functions and struct data, it will be more general for others. David Wu (8): net: dwc_eth_qos: Use dev_ functions calls to get FDT data net: dwc_eth_qos: Fix the software reset net: dwc_eth_qos: Add option "snps,reset-gpio" phy-rst gpio for stm32 net: dwc_eth_qos: Move interface() to eqos_ops struct net: dwc_eth_qos: Make clk_rx and clk_tx optional net: dwc_eth_qos: Split eqos_start() to get link speed net: dwc_eth_qos: Export common struct and interface at head file net: gmac_rockchip: Add dwc_eth_qos support drivers/net/Kconfig | 2 +- drivers/net/dwc_eth_qos.c | 264 +--- drivers/net/gmac_rockchip.c | 160 ++ 3 files changed, 263 insertions(+), 163 deletions(-) -- 2.19.1
[PATCH 1/8] net: dwc_eth_qos: Use dev_ functions calls to get FDT data
It seems dev_ functions are more general than fdt_ functions.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 63f2086dec..a72132cacf 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1728,8 +1728,7 @@ static phy_interface_t eqos_get_interface_stm32(struct
udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
- NULL);
+ phy_mode = dev_read_string(dev, "phy-mode");
if (phy_mode)
interface = phy_get_interface_by_name(phy_mode);
@@ -1788,9 +1787,9 @@ static int eqos_probe(struct udevice *dev)
eqos->dev = dev;
eqos->config = (void *)dev_get_driver_data(dev);
- eqos->regs = devfdt_get_addr(dev);
+ eqos->regs = dev_read_addr(dev);
if (eqos->regs == FDT_ADDR_T_NONE) {
- pr_err("devfdt_get_addr() failed");
+ pr_err("dev_read_addr() failed");
return -ENODEV;
}
eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
--
2.19.1
[PATCH 3/8] net: dwc_eth_qos: Add option "snps, reset-gpio" phy-rst gpio for stm32
It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
gpio is used, adding this option makes reset function more general.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 40 ++-
1 file changed, 35 insertions(+), 5 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 16988f6bdc..06a8d924a7 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -298,6 +298,7 @@ struct eqos_priv {
struct eqos_tegra186_regs *tegra186_regs;
struct reset_ctl reset_ctl;
struct gpio_desc phy_reset_gpio;
+ u32 reset_delays[3];
struct clk clk_master_bus;
struct clk clk_rx;
struct clk clk_ptp_ref;
@@ -701,6 +702,15 @@ static int eqos_start_resets_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
+ ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
+ if (ret < 0) {
+ pr_err("dm_gpio_set_value(phy_reset, deassert) failed:
%d",
+ ret);
+ return ret;
+ }
+
+ udelay(eqos->reset_delays[0]);
+
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
if (ret < 0) {
pr_err("dm_gpio_set_value(phy_reset, assert) failed:
%d",
@@ -708,7 +718,7 @@ static int eqos_start_resets_stm32(struct udevice *dev)
return ret;
}
- udelay(2);
+ udelay(eqos->reset_delays[1]);
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
if (ret < 0) {
@@ -716,6 +726,8 @@ static int eqos_start_resets_stm32(struct udevice *dev)
ret);
return ret;
}
+
+ udelay(eqos->reset_delays[2]);
}
debug("%s: OK\n", __func__);
@@ -1065,16 +1077,16 @@ static int eqos_start(struct udevice *dev)
val |= EQOS_DMA_MODE_SWR;
writel(val, &eqos->dma_regs->mode);
limit = eqos->config->swr_wait / 10;
- while (limit--) {
+ do {
if (!(readl(&eqos->dma_regs->mode) & EQOS_DMA_MODE_SWR))
break;
mdelay(1);
- }
+ } while (limit--);
if (limit < 0) {
pr_err("EQOS_DMA_MODE_SWR stuck");
- goto err_stop_clks;
- return -ETIMEDOUT;
+ ret = -ETIMEDOUT;
+ goto err_stop_resets;
}
ret = eqos->config->ops->eqos_calibrate_pads(dev);
@@ -1712,11 +1724,29 @@ static int eqos_probe_resources_stm32(struct udevice
*dev)
if (ret)
pr_warn("gpio_request_by_name(phy reset) not provided
%d",
ret);
+ else
+ eqos->reset_delays[1] = 2;
eqos->phyaddr = ofnode_read_u32_default(phandle_args.node,
"reg", -1);
}
+ if (!dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
+ int reset_flags = GPIOD_IS_OUT;
+
+ if (dev_read_bool(dev, "snps,reset-active-low"))
+ reset_flags |= GPIOD_ACTIVE_LOW;
+
+ ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
+ &eqos->phy_reset_gpio, reset_flags);
+ if (ret == 0)
+ ret = dev_read_u32_array(dev, "snps,reset-delays-us",
+eqos->reset_delays, 3);
+ else
+ pr_warn("gpio_request_by_name(snps,reset-gpio) failed:
%d",
+ ret);
+ }
+
debug("%s: OK\n", __func__);
return 0;
--
2.19.1
[PATCH 4/8] net: dwc_eth_qos: Move interface() to eqos_ops struct
After moving to eqos_ops, if eqos_config is defined
outside, can not export interface() definition.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 06a8d924a7..fbd6caf85b 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -267,7 +267,6 @@ struct eqos_config {
int swr_wait;
int config_mac;
int config_mac_mdio;
- phy_interface_t (*interface)(struct udevice *dev);
struct eqos_ops *ops;
};
@@ -286,6 +285,7 @@ struct eqos_ops {
int (*eqos_disable_calibration)(struct udevice *dev);
int (*eqos_set_tx_clk_speed)(struct udevice *dev);
ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
+ phy_interface_t (*eqos_get_interface)(struct udevice *dev);
};
struct eqos_priv {
@@ -1105,7 +1105,7 @@ static int eqos_start(struct udevice *dev)
*/
if (!eqos->phy) {
eqos->phy = phy_connect(eqos->mii, eqos->phyaddr, dev,
- eqos->config->interface(dev));
+ eqos->config->ops->eqos_get_interface(dev));
if (!eqos->phy) {
pr_err("phy_connect() failed");
goto err_stop_resets;
@@ -1675,7 +1675,7 @@ static int eqos_probe_resources_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- interface = eqos->config->interface(dev);
+ interface = eqos->config->ops->eqos_get_interface(dev);
if (interface == PHY_INTERFACE_MODE_NONE) {
pr_err("Invalid PHY interface\n");
@@ -1918,7 +1918,8 @@ static struct eqos_ops eqos_tegra186_ops = {
.eqos_calibrate_pads = eqos_calibrate_pads_tegra186,
.eqos_disable_calibration = eqos_disable_calibration_tegra186,
.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186,
- .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186,
+ .eqos_get_interface = eqos_get_interface_tegra186
};
static const struct eqos_config eqos_tegra186_config = {
@@ -1927,7 +1928,6 @@ static const struct eqos_config eqos_tegra186_config = {
.swr_wait = 10,
.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35,
- .interface = eqos_get_interface_tegra186,
.ops = &eqos_tegra186_ops
};
@@ -1945,7 +1945,8 @@ static struct eqos_ops eqos_stm32_ops = {
.eqos_calibrate_pads = eqos_calibrate_pads_stm32,
.eqos_disable_calibration = eqos_disable_calibration_stm32,
.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
- .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32,
+ .eqos_get_interface = eqos_get_interface_stm32
};
static const struct eqos_config eqos_stm32_config = {
@@ -1954,7 +1955,6 @@ static const struct eqos_config eqos_stm32_config = {
.swr_wait = 50,
.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
- .interface = eqos_get_interface_stm32,
.ops = &eqos_stm32_ops
};
--
2.19.1
[PATCH 2/8] net: dwc_eth_qos: Fix the software reset
When using rgmii Gigabit mode, the wait_for_bit_le32()
reset method resulting in RX can not receive data, after
this patch, works well.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index a72132cacf..16988f6bdc 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1034,7 +1034,7 @@ static int eqos_write_hwaddr(struct udevice *dev)
static int eqos_start(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
- int ret, i;
+ int ret, i, limit;
ulong rate;
u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
ulong last_rx_desc;
@@ -1060,12 +1060,21 @@ static int eqos_start(struct udevice *dev)
eqos->reg_access_ok = true;
- ret = wait_for_bit_le32(&eqos->dma_regs->mode,
- EQOS_DMA_MODE_SWR, false,
- eqos->config->swr_wait, false);
- if (ret) {
+ /* DMA SW reset */
+ val = readl(&eqos->dma_regs->mode);
+ val |= EQOS_DMA_MODE_SWR;
+ writel(val, &eqos->dma_regs->mode);
+ limit = eqos->config->swr_wait / 10;
+ while (limit--) {
+ if (!(readl(&eqos->dma_regs->mode) & EQOS_DMA_MODE_SWR))
+ break;
+ mdelay(1);
+ }
+
+ if (limit < 0) {
pr_err("EQOS_DMA_MODE_SWR stuck");
- goto err_stop_resets;
+ goto err_stop_clks;
+ return -ETIMEDOUT;
}
ret = eqos->config->ops->eqos_calibrate_pads(dev);
--
2.19.1
[PATCH 6/8] net: dwc_eth_qos: Split eqos_start() to get link speed
Before enabling mac and mac working, we need to obtain
the current link speed to configure the clock, so split
eqos_start into two functions.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 56 ++-
1 file changed, 38 insertions(+), 18 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index b5d5156292..25b3449047 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1051,19 +1051,15 @@ static int eqos_write_hwaddr(struct udevice *dev)
return 0;
}
-static int eqos_start(struct udevice *dev)
+static int eqos_init(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
- int ret, i, limit;
+ int ret, limit;
ulong rate;
- u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
- ulong last_rx_desc;
+ u32 val;
debug("%s(dev=%p):\n", __func__, dev);
- eqos->tx_desc_idx = 0;
- eqos->rx_desc_idx = 0;
-
ret = eqos->config->ops->eqos_start_clks(dev);
if (ret < 0) {
pr_err("eqos_start_clks() failed: %d", ret);
@@ -1151,6 +1147,30 @@ static int eqos_start(struct udevice *dev)
goto err_shutdown_phy;
}
+ debug("%s: OK\n", __func__);
+ return 0;
+
+err_shutdown_phy:
+ phy_shutdown(eqos->phy);
+err_stop_resets:
+ eqos->config->ops->eqos_stop_resets(dev);
+err_stop_clks:
+ eqos->config->ops->eqos_stop_clks(dev);
+err:
+ pr_err("FAILED: %d", ret);
+ return ret;
+}
+
+static void eqos_enable(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
+ ulong last_rx_desc;
+ int i;
+
+ eqos->tx_desc_idx = 0;
+ eqos->rx_desc_idx = 0;
+
/* Configure MTL */
/* Enable Store and Forward mode for TX */
@@ -1352,19 +1372,19 @@ static int eqos_start(struct udevice *dev)
writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
eqos->started = true;
+}
- debug("%s: OK\n", __func__);
- return 0;
+static int eqos_start(struct udevice *dev)
+{
+ int ret;
-err_shutdown_phy:
- phy_shutdown(eqos->phy);
-err_stop_resets:
- eqos->config->ops->eqos_stop_resets(dev);
-err_stop_clks:
- eqos->config->ops->eqos_stop_clks(dev);
-err:
- pr_err("FAILED: %d", ret);
- return ret;
+ ret = eqos_init(dev);
+ if (ret)
+ return ret;
+
+ eqos_enable(dev);
+
+ return 0;
}
static void eqos_stop(struct udevice *dev)
--
2.19.1
[PATCH 7/8] net: dwc_eth_qos: Export common struct and interface at head file
Open structure data and interface, so that Soc using dw_eth_qos
controller can reference.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 81 +--
1 file changed, 9 insertions(+), 72 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 25b3449047..7f47e5f505 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -41,6 +41,7 @@
#include
#include
#include
+#include "dwc_eth_qos.h"
/* Core registers */
@@ -94,9 +95,6 @@ struct eqos_mac_regs {
#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT0
#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
@@ -109,8 +107,6 @@ struct eqos_mac_regs {
#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT16
#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
-#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
-#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT2
#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
@@ -261,65 +257,6 @@ struct eqos_desc {
#define EQOS_DESC3_LD BIT(28)
#define EQOS_DESC3_BUF1V BIT(24)
-struct eqos_config {
- bool reg_access_always_ok;
- int mdio_wait;
- int swr_wait;
- int config_mac;
- int config_mac_mdio;
- struct eqos_ops *ops;
-};
-
-struct eqos_ops {
- void (*eqos_inval_desc)(void *desc);
- void (*eqos_flush_desc)(void *desc);
- void (*eqos_inval_buffer)(void *buf, size_t size);
- void (*eqos_flush_buffer)(void *buf, size_t size);
- int (*eqos_probe_resources)(struct udevice *dev);
- int (*eqos_remove_resources)(struct udevice *dev);
- int (*eqos_stop_resets)(struct udevice *dev);
- int (*eqos_start_resets)(struct udevice *dev);
- void (*eqos_stop_clks)(struct udevice *dev);
- int (*eqos_start_clks)(struct udevice *dev);
- int (*eqos_calibrate_pads)(struct udevice *dev);
- int (*eqos_disable_calibration)(struct udevice *dev);
- int (*eqos_set_tx_clk_speed)(struct udevice *dev);
- ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
- phy_interface_t (*eqos_get_interface)(struct udevice *dev);
-};
-
-struct eqos_priv {
- struct udevice *dev;
- const struct eqos_config *config;
- fdt_addr_t regs;
- struct eqos_mac_regs *mac_regs;
- struct eqos_mtl_regs *mtl_regs;
- struct eqos_dma_regs *dma_regs;
- struct eqos_tegra186_regs *tegra186_regs;
- struct reset_ctl reset_ctl;
- struct gpio_desc phy_reset_gpio;
- u32 reset_delays[3];
- struct clk clk_master_bus;
- struct clk clk_rx;
- struct clk clk_ptp_ref;
- struct clk clk_tx;
- struct clk clk_ck;
- struct clk clk_slave_bus;
- struct mii_dev *mii;
- struct phy_device *phy;
- int phyaddr;
- u32 max_speed;
- void *descs;
- struct eqos_desc *tx_descs;
- struct eqos_desc *rx_descs;
- int tx_desc_idx, rx_desc_idx;
- void *tx_dma_buf;
- void *rx_dma_buf;
- void *rx_pkt;
- bool started;
- bool reg_access_ok;
-};
-
/*
* TX and RX descriptors are 16 bytes. This causes problems with the cache
* maintenance on CPUs where the cache-line size exceeds the size of these
@@ -1007,7 +944,7 @@ static int eqos_adjust_link(struct udevice *dev)
return 0;
}
-static int eqos_write_hwaddr(struct udevice *dev)
+int eqos_write_hwaddr(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_platdata(dev);
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1051,7 +988,7 @@ static int eqos_write_hwaddr(struct udevice *dev)
return 0;
}
-static int eqos_init(struct udevice *dev)
+int eqos_init(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
int ret, limit;
@@ -1161,7 +1098,7 @@ err:
return ret;
}
-static void eqos_enable(struct udevice *dev)
+void eqos_enable(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
@@ -1387,7 +1324,7 @@ static int eqos_start(struct udevice *dev)
return 0;
}
-static void eqos_stop(struct udevice *dev)
+void eqos_stop(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
int i;
@@ -1441,7 +1378,7 @@ static void eqos_stop(struct udevice *dev)
debug("%s: OK\n", __func__);
}
-static int eqos_send(struct udevice *de
[PATCH 5/8] net: dwc_eth_qos: Make clk_rx and clk_tx optional
For others using, clk_rx and clk_tx may not be necessary,
and their clock names are different.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 65 +++
1 file changed, 31 insertions(+), 34 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index fbd6caf85b..b5d5156292 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -592,16 +592,20 @@ static int eqos_start_clks_stm32(struct udevice *dev)
goto err;
}
- ret = clk_enable(&eqos->clk_rx);
- if (ret < 0) {
- pr_err("clk_enable(clk_rx) failed: %d", ret);
- goto err_disable_clk_master_bus;
+ if (clk_valid(&eqos->clk_rx)) {
+ ret = clk_enable(&eqos->clk_rx);
+ if (ret < 0) {
+ pr_err("clk_enable(clk_rx) failed: %d", ret);
+ goto err_disable_clk_master_bus;
+ }
}
- ret = clk_enable(&eqos->clk_tx);
- if (ret < 0) {
- pr_err("clk_enable(clk_tx) failed: %d", ret);
- goto err_disable_clk_rx;
+ if (clk_valid(&eqos->clk_tx)) {
+ ret = clk_enable(&eqos->clk_tx);
+ if (ret < 0) {
+ pr_err("clk_enable(clk_tx) failed: %d", ret);
+ goto err_disable_clk_rx;
+ }
}
if (clk_valid(&eqos->clk_ck)) {
@@ -616,9 +620,11 @@ static int eqos_start_clks_stm32(struct udevice *dev)
return 0;
err_disable_clk_tx:
- clk_disable(&eqos->clk_tx);
+ if (clk_valid(&eqos->clk_tx))
+ clk_disable(&eqos->clk_tx);
err_disable_clk_rx:
- clk_disable(&eqos->clk_rx);
+ if (clk_valid(&eqos->clk_rx))
+ clk_disable(&eqos->clk_rx);
err_disable_clk_master_bus:
clk_disable(&eqos->clk_master_bus);
err:
@@ -647,8 +653,10 @@ static void eqos_stop_clks_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- clk_disable(&eqos->clk_tx);
- clk_disable(&eqos->clk_rx);
+ if (clk_valid(&eqos->clk_tx))
+ clk_disable(&eqos->clk_tx);
+ if (clk_valid(&eqos->clk_rx))
+ clk_disable(&eqos->clk_rx);
clk_disable(&eqos->clk_master_bus);
if (clk_valid(&eqos->clk_ck))
clk_disable(&eqos->clk_ck);
@@ -1691,20 +1699,16 @@ static int eqos_probe_resources_stm32(struct udevice
*dev)
ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
if (ret) {
pr_err("clk_get_by_name(master_bus) failed: %d", ret);
- goto err_probe;
+ return ret;
}
- ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
- if (ret) {
- pr_err("clk_get_by_name(rx) failed: %d", ret);
- goto err_free_clk_master_bus;
- }
+ ret = clk_get_by_name(dev, "mac_clk_rx", &eqos->clk_rx);
+ if (ret)
+ pr_warn("clk_get_by_name(rx) failed: %d", ret);
- ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
- if (ret) {
- pr_err("clk_get_by_name(tx) failed: %d", ret);
- goto err_free_clk_rx;
- }
+ ret = clk_get_by_name(dev, "mac_clk_tx", &eqos->clk_tx);
+ if (ret)
+ pr_warn("clk_get_by_name(tx) failed: %d", ret);
/* Get ETH_CLK clocks (optional) */
ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
@@ -1749,15 +1753,6 @@ static int eqos_probe_resources_stm32(struct udevice
*dev)
debug("%s: OK\n", __func__);
return 0;
-
-err_free_clk_rx:
- clk_free(&eqos->clk_rx);
-err_free_clk_master_bus:
- clk_free(&eqos->clk_master_bus);
-err_probe:
-
- debug("%s: returns %d\n", __func__, ret);
- return ret;
}
static phy_interface_t eqos_get_interface_stm32(struct udevice *dev)
@@ -1803,8 +1798,10 @@ static int eqos_remove_resources_stm32(struct udevice
*dev)
debug("%s(dev=%p):\n", __func__, dev);
- clk_free(&eqos->clk_tx);
- clk_free(&eqos->clk_rx);
+ if (clk_valid(&eqos->clk_tx))
+ clk_free(&eqos->clk_tx);
+ if (clk_valid(&eqos->clk_rx))
+ clk_free(&eqos->clk_rx);
clk_free(&eqos->clk_master_bus);
if (clk_valid(&eqos->clk_ck))
clk_free(&eqos->clk_ck);
--
2.19.1
[PATCH 8/8] net: gmac_rockchip: Add dwc_eth_qos support
Change the original data structure so that Rockchip's Soc
gmac controller can support the designware.c and dwc_eth_qos.c
drivers, a Soc can only support one.
Signed-off-by: David Wu
---
drivers/net/Kconfig | 2 +-
drivers/net/gmac_rockchip.c | 160 ++--
2 files changed, 135 insertions(+), 27 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4d1013c984..07d2b0787c 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -482,7 +482,7 @@ config PIC32_ETH
config GMAC_ROCKCHIP
bool "Rockchip Synopsys Designware Ethernet MAC"
- depends on DM_ETH && ETH_DESIGNWARE
+ depends on DM_ETH && (ETH_DESIGNWARE || DWC_ETH_QOS)
help
This driver provides Rockchip SoCs network support based on the
Synopsys Designware driver.
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index e152faf083..aa2bab4203 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -25,26 +25,39 @@
#include
#include
#include "designware.h"
+#include "dwc_eth_qos.h"
DECLARE_GLOBAL_DATA_PTR;
#define DELAY_ENABLE(soc, tx, rx) \
(((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE :
soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE :
soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
+struct rockchip_eth_dev {
+ union {
+ struct eqos_priv eqos;
+ struct dw_eth_dev dw;
+ };
+};
+
/*
* Platform data for the gmac
*
* dw_eth_pdata: Required platform data for designware driver (must be first)
*/
struct gmac_rockchip_platdata {
- struct dw_eth_pdata dw_eth_pdata;
+ union {
+ struct dw_eth_pdata dw_eth_pdata;
+ struct eth_pdata eth_pdata;
+ };
+ bool has_gmac4;
bool clock_input;
int tx_delay;
int rx_delay;
};
struct rk_gmac_ops {
- int (*fix_mac_speed)(struct dw_eth_dev *priv);
+ const struct eqos_config config;
+ int (*fix_mac_speed)(struct rockchip_eth_dev *dev);
void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
};
@@ -55,6 +68,9 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice
*dev)
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
const char *string;
+ if (device_is_compatible(dev, "snps,dwmac-4.20a"))
+ pdata->has_gmac4 = true;
+
string = dev_read_string(dev, "clock_in_out");
if (!strcmp(string, "input"))
pdata->clock_input = true;
@@ -71,11 +87,15 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice
*dev)
if (pdata->rx_delay == -ENOENT)
pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
- return designware_eth_ofdata_to_platdata(dev);
+ if (!pdata->has_gmac4)
+ return designware_eth_ofdata_to_platdata(dev);
+
+ return 0;
}
-static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int px30_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct px30_grf *grf;
struct clk clk_speed;
int speed, ret;
@@ -115,8 +135,9 @@ static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
}
-static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3228_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct rk322x_grf *grf;
int clk;
enum {
@@ -148,8 +169,9 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3288_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct rk3288_grf *grf;
int clk;
@@ -174,8 +196,9 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3308_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct rk3308_grf *grf;
struct clk clk_speed;
int speed, ret;
@@ -215,8 +238,9 @@ static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3328_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct rk3328_grf_regs *grf;
int clk;
enum {
@@ -248,8 +272,9 @@ static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3368_gmac_fix_mac_speed(struct dw_eth
Re: [PATCH 3/8] net: dwc_eth_qos: Add option "snps, reset-gpio" phy-rst gpio for stm32
Hi Stephen, 在 2020/5/1 上午6:36, Stephen Warren 写道: The kernel's bindings/net/snps,dwmac.yaml does not mention any reset-gpios property (which is what the existing code parses just above the portion that is quoted by this patch as context). I suspect that this patch should simply change the name of the property that this function parses to align with the binding, and fix any DTs in U-Boot that also don't match the binding? The kernel's ./Documentation/devicetree/bindings/net/stmmac.txt mentions that Required properties: - phy-mode: See ethernet.txt file in the same directory. - snps,reset-gpio gpio number for phy reset. - snps,reset-active-low boolean flag to indicate if phy reset is active low. - snps,reset-delays-us is triplet of delays The 1st cell is reset pre-delay in micro seconds. The 2nd cell is reset pulse in micro seconds. The 3rd cell is reset post-delay in micro seconds.
Re: [PATCH 3/8] net: dwc_eth_qos: Add option "snps,reset-gpio" phy-rst gpio for stm32
Hi Patrice,
在 2020/4/30 下午11:47, Patrice CHOTARD 写道:
@@ -701,6 +702,15 @@ static int eqos_start_resets_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
+ ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
+ if (ret < 0) {
+ pr_err("dm_gpio_set_value(phy_reset, deassert) failed:
%d",
+ ret);
+ return ret;
+ }
+
+ udelay(eqos->reset_delays[0]);
+
not related to this patch subject
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
if (ret < 0) {
pr_err("dm_gpio_set_value(phy_reset, assert) failed:
%d",
@@ -708,7 +718,7 @@ static int eqos_start_resets_stm32(struct udevice *dev)
return ret;
}
- udelay(2);
+ udelay(eqos->reset_delays[1]);
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
if (ret < 0) {
@@ -1712,11 +1724,29 @@ static int eqos_probe_resources_stm32(struct udevice
*dev)
if (ret)
pr_warn("gpio_request_by_name(phy reset) not provided
%d",
ret);
+ else
+ eqos->reset_delays[1] = 2;
this is not the correct place to set default value. It must be set in case we
can't get value from DT below
No, three cases below, it is second case, and we can see udelay(2) in
eqos_start_resets_stm32(), here we are to be compatible with the original.
- If there is not phy rst, reset_delays is 0;
- If "reset-gpios exists in phy node, reset_delays [1] = 2;
- "snps, reset-gpio" exists in DT, reset_delays is obtained from DT
eqos->phyaddr = ofnode_read_u32_default(phandle_args.node,
"reg", -1);
}
+ if (!dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
+ int reset_flags = GPIOD_IS_OUT;
+
+ if (dev_read_bool(dev, "snps,reset-active-low"))
+ reset_flags |= GPIOD_ACTIVE_LOW;
+
+ ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
+ &eqos->phy_reset_gpio, reset_flags);
+ if (ret == 0)
+ ret = dev_read_u32_array(dev, "snps,reset-delays-us",
+eqos->reset_delays, 3);
in case "snps,reset-delays-us" is not in present DT, all resets-delays are set
to 0, see my remark above
+ else
+ pr_warn("gpio_request_by_name(snps,reset-gpio) failed:
%d",
+ ret);
+ }
+
debug("%s: OK\n", __func__);
return 0;
Re: [PATCH 4/8] net: dwc_eth_qos: Move interface() to eqos_ops struct
Hi Stephen, 在 2020/5/1 上午6:39, Stephen Warren 写道: On 4/30/20 4:36 AM, David Wu wrote: After moving to eqos_ops, if eqos_config is defined outside, can not export interface() definition. Looking at the patch itself, I think this patch just moves a function pointer from the config to the ops structure which makes sense. However, I can't understand the patch description at all, so I worry there's intended to be some other justification/implication for this patch, and that may not be correct... In particular, defined outside of what, and what does this have to do with exporting things Yes, if define eqos_config structure in gmac_rockchip.c, need to export an eqos_get_interface function, or redefine a similar function in gmac_rockchip.c, but this function is the same implementation as eqos_get_interface_stm32(), so we can share this function. Move interface() to eqos_ops structure, no need to export interface() in the head file. I lost a patch to define eqos_ops structure at curent file, then only exprot eqos_rockchip_ops, so it would be simpler?
Re: [PATCH 3/8] net: dwc_eth_qos: Add option "snps, reset-gpio" phy-rst gpio for stm32
Hi Stephen, 在 2020/5/9 上午10:41, David Wu 写道: The kernel's ./Documentation/devicetree/bindings/net/stmmac.txt mentions that Required properties: - phy-mode: See ethernet.txt file in the same directory. - snps,reset-gpio gpio number for phy reset. - snps,reset-active-low boolean flag to indicate if phy reset is active low. - snps,reset-delays-us is triplet of delays The 1st cell is reset pre-delay in micro seconds. The 2nd cell is reset pulse in micro seconds. The 3rd cell is reset post-delay in micro seconds. Sorry, I just saw you replying again before, stmmac.txt was found, this reply email please discard.
Re: [PATCH 5/8] net: dwc_eth_qos: Make clk_rx and clk_tx optional
Hi Patrice,
在 2020/4/30 下午10:00, Patrice CHOTARD 写道:
@@ -647,8 +653,10 @@ static void eqos_stop_clks_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- clk_disable(&eqos->clk_tx);
- clk_disable(&eqos->clk_rx);
+ if (clk_valid(&eqos->clk_tx))
+ clk_disable(&eqos->clk_tx);
+ if (clk_valid(&eqos->clk_rx))
+ clk_disable(&eqos->clk_rx);
clk_disable(&eqos->clk_master_bus);
if (clk_valid(&eqos->clk_ck))
clk_disable(&eqos->clk_ck);
@@ -1691,20 +1699,16 @@ static int eqos_probe_resources_stm32(struct udevice
*dev)
ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
if (ret) {
pr_err("clk_get_by_name(master_bus) failed: %d", ret);
- goto err_probe;
+ return ret;
}
why are you changing the error path here ?
The following code has not returned, so for the sake of simpler code,
return directly.
- ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
- if (ret) {
- pr_err("clk_get_by_name(rx) failed: %d", ret);
- goto err_free_clk_master_bus;
- }
+ ret = clk_get_by_name(dev, "mac_clk_rx", &eqos->clk_rx);
+ if (ret)
+ pr_warn("clk_get_by_name(rx) failed: %d", ret);
- ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
- if (ret) {
- pr_err("clk_get_by_name(tx) failed: %d", ret);
- goto err_free_clk_rx;
- }
+ ret = clk_get_by_name(dev, "mac_clk_tx", &eqos->clk_tx);
+ if (ret)
+ pr_warn("clk_get_by_name(tx) failed: %d", ret);
Nak
Why are you changing the Rx and Tx clock names ?
for information, check with the kernel dt bindings regarding this driver:
Documentation/devicetree/bindings/net/stm32-dwmac.txt
This patch is breaking ethernet on STM32MP1 boards
I should have made a mistake here. In fact, for Rockchip, there is no
need to obtain this two clock. My intention is to make these two clocks
optional.
Re: [PATCH 5/8] net: dwc_eth_qos: Make clk_rx and clk_tx optional
Hi Stephen, 在 2020/5/1 上午6:45, Stephen Warren 写道: Oh... Judging by your email, you're trying to make this driver work on a Rockchip system. However, you're editing an STM32-specific probe function. You should introduce a new probe function for Rockchip if it needs to work differently to the existing STM32 code. Also, mac_clk_rx isn't a valid DT property name; they aren't supposed to have _ in them. I don't see mac_clk_rx or mac-clk-rx in the DT binding file in Documentation/bindings/net/rockchip-dwmac.txt the kernel. That should probably be submitted/reviewed/applied before using the binding... If necessary, I can rewrite a function to obtain resources, but I think the function of rockchip and stm should be very similar, and can be shared.
Re: [PATCH 6/8] net: dwc_eth_qos: Split eqos_start() to get link speed
Hi Patrice, 在 2020/4/30 下午11:33, Patrice CHOTARD 写道: Can you explain why you are splitting this function in 2 parts and calling these parts sequentially ? For rockchip, need to obtain the current link speed to configure the tx clocks, (for example, in rgmii mode, 1000M link: 125M, 100M link: 25M, 10M link is 2.5M rate) and then enable gmac. So after the adjust_link(), before the start gamc, this intermediate stage needs to configure the clock according to the current link speed.
Re: [PATCH 8/8] net: gmac_rockchip: Add dwc_eth_qos support
Hi Stephen, 在 2020/5/1 上午6:52, Stephen Warren 写道: I'm really confused; with a filename like gmac_rockchip.c that sounds like it's driver for a MAC device. DWC EQoS is also a MAC device. The two shouldn't be related or coupled in any way. I think what you need is to completely drop this patch (and the patch which creates dwc_eth_qos.h), and instead make the DWC EQoS driver itself directly support the Rockchip SoC by adding RK's compatible value to the list of compatible values that the EQoS driver supports, along with new probe functions etc. Maybe this requires splitting some PHY code out of gmac_rockchip into a common/separate PHY driver? I haven't looked at the code to know if that's required. I think this relationship is like the current designware.c and gmac_rockchip.c, except that the designware driver becomes DWC EQoS. In fact, most of the code is the same, because it is the same controller, and there are a few differences related to Soc implemented in gmac_rockchip.c, this is the purpose of my series of patches, and the code must be compatible with the previous Rockchip Socs.
[PATCH v2 00/11] Add dwc_eth_qos support for rockchip
Rockchip Socs can support two controllers "snps, dwmac-4.20a" and "snps, dwmac-3.50". In order to support two at gmac-rockchip.c, export public interface functions and struct data, it will be more general for others. Changes in v2: - None - Remove the code is not related (Patrice) - None - Don't change the Rx and Tx clock names. (Patrice, Stephen) - None - None - Add the lost head file. (Patrice) - None - None - None - None David Wu (11): net: dwc_eth_qos: Use dev_ functions calls to get FDT data net: dwc_eth_qos: Add option "snps,reset-gpio" phy-rst gpio for stm32 net: dwc_eth_qos: Move interface() to eqos_ops structure net: dwc_eth_qos: Make clk_rx and clk_tx optional net: dwc_eth_qos: Split eqos_start() to get link speed net: dwc_eth_qos: make eqos_start_clks and eqos_stop_clks optional net: dwc_eth_qos: Export common struct and interface at head file net: gmac_rockchip: Add dwc_eth_qos support net: dwc_eth_qos: Add eqos_rockchip_ops net: dwc_eth_qos: Add EQOS_MAC_MDIO_ADDRESS_CR_100_150 for Rockchip net: gmac_rockchip: Add RV1126 gmac support drivers/net/Kconfig | 2 +- drivers/net/dwc_eth_qos.c | 273 ++-- drivers/net/dwc_eth_qos.h | 89 drivers/net/gmac_rockchip.c | 188 + 4 files changed, 390 insertions(+), 162 deletions(-) create mode 100644 drivers/net/dwc_eth_qos.h -- 2.19.1
[PATCH v2 03/11] net: dwc_eth_qos: Move interface() to eqos_ops structure
After moving to eqos_ops, if eqos_config is defined
outside file, can not export interface() definition,
only export eqos_ops struct defined in dwc_eth_qos.c.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 54866aff6b..613cfb48ea 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -267,7 +267,6 @@ struct eqos_config {
int swr_wait;
int config_mac;
int config_mac_mdio;
- phy_interface_t (*interface)(struct udevice *dev);
struct eqos_ops *ops;
};
@@ -286,6 +285,7 @@ struct eqos_ops {
int (*eqos_disable_calibration)(struct udevice *dev);
int (*eqos_set_tx_clk_speed)(struct udevice *dev);
ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
+ phy_interface_t (*eqos_get_interface)(struct udevice *dev);
};
struct eqos_priv {
@@ -1096,7 +1096,7 @@ static int eqos_start(struct udevice *dev)
*/
if (!eqos->phy) {
eqos->phy = phy_connect(eqos->mii, eqos->phyaddr, dev,
- eqos->config->interface(dev));
+ eqos->config->ops->eqos_get_interface(dev));
if (!eqos->phy) {
pr_err("phy_connect() failed");
goto err_stop_resets;
@@ -1666,7 +1666,7 @@ static int eqos_probe_resources_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- interface = eqos->config->interface(dev);
+ interface = eqos->config->ops->eqos_get_interface(dev);
if (interface == PHY_INTERFACE_MODE_NONE) {
pr_err("Invalid PHY interface\n");
@@ -1909,7 +1909,8 @@ static struct eqos_ops eqos_tegra186_ops = {
.eqos_calibrate_pads = eqos_calibrate_pads_tegra186,
.eqos_disable_calibration = eqos_disable_calibration_tegra186,
.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186,
- .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186,
+ .eqos_get_interface = eqos_get_interface_tegra186
};
static const struct eqos_config eqos_tegra186_config = {
@@ -1918,7 +1919,6 @@ static const struct eqos_config eqos_tegra186_config = {
.swr_wait = 10,
.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35,
- .interface = eqos_get_interface_tegra186,
.ops = &eqos_tegra186_ops
};
@@ -1936,7 +1936,8 @@ static struct eqos_ops eqos_stm32_ops = {
.eqos_calibrate_pads = eqos_calibrate_pads_stm32,
.eqos_disable_calibration = eqos_disable_calibration_stm32,
.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
- .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32,
+ .eqos_get_interface = eqos_get_interface_stm32
};
static const struct eqos_config eqos_stm32_config = {
@@ -1945,7 +1946,6 @@ static const struct eqos_config eqos_stm32_config = {
.swr_wait = 50,
.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
- .interface = eqos_get_interface_stm32,
.ops = &eqos_stm32_ops
};
--
2.19.1
[PATCH v2 02/11] net: dwc_eth_qos: Add option "snps, reset-gpio" phy-rst gpio for stm32
It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
gpio is used, adding this option makes reset function more general.
Signed-off-by: David Wu
---
Changes in v2:
- Remove the code is not related (Patrice)
drivers/net/dwc_eth_qos.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index a72132cacf..54866aff6b 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -298,6 +298,7 @@ struct eqos_priv {
struct eqos_tegra186_regs *tegra186_regs;
struct reset_ctl reset_ctl;
struct gpio_desc phy_reset_gpio;
+ u32 reset_delays[3];
struct clk clk_master_bus;
struct clk clk_rx;
struct clk clk_ptp_ref;
@@ -701,6 +702,15 @@ static int eqos_start_resets_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
+ ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
+ if (ret < 0) {
+ pr_err("dm_gpio_set_value(phy_reset, deassert) failed:
%d",
+ ret);
+ return ret;
+ }
+
+ udelay(eqos->reset_delays[0]);
+
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
if (ret < 0) {
pr_err("dm_gpio_set_value(phy_reset, assert) failed:
%d",
@@ -708,7 +718,7 @@ static int eqos_start_resets_stm32(struct udevice *dev)
return ret;
}
- udelay(2);
+ udelay(eqos->reset_delays[1]);
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
if (ret < 0) {
@@ -716,6 +726,8 @@ static int eqos_start_resets_stm32(struct udevice *dev)
ret);
return ret;
}
+
+ udelay(eqos->reset_delays[2]);
}
debug("%s: OK\n", __func__);
@@ -1703,11 +1715,29 @@ static int eqos_probe_resources_stm32(struct udevice
*dev)
if (ret)
pr_warn("gpio_request_by_name(phy reset) not provided
%d",
ret);
+ else
+ eqos->reset_delays[1] = 2;
eqos->phyaddr = ofnode_read_u32_default(phandle_args.node,
"reg", -1);
}
+ if (!dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
+ int reset_flags = GPIOD_IS_OUT;
+
+ if (dev_read_bool(dev, "snps,reset-active-low"))
+ reset_flags |= GPIOD_ACTIVE_LOW;
+
+ ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
+ &eqos->phy_reset_gpio, reset_flags);
+ if (ret == 0)
+ ret = dev_read_u32_array(dev, "snps,reset-delays-us",
+eqos->reset_delays, 3);
+ else
+ pr_warn("gpio_request_by_name(snps,reset-gpio) failed:
%d",
+ ret);
+ }
+
debug("%s: OK\n", __func__);
return 0;
--
2.19.1
[PATCH v2 04/11] net: dwc_eth_qos: Make clk_rx and clk_tx optional
For others using, clk_rx and clk_tx may not be necessary,
and their clock names are different.
Signed-off-by: David Wu
---
Changes in v2:
- Don't change the Rx and Tx clock names. (Patrice, Stephen)
drivers/net/dwc_eth_qos.c | 61 +++
1 file changed, 29 insertions(+), 32 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 613cfb48ea..30e72a9d7d 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -592,16 +592,20 @@ static int eqos_start_clks_stm32(struct udevice *dev)
goto err;
}
- ret = clk_enable(&eqos->clk_rx);
- if (ret < 0) {
- pr_err("clk_enable(clk_rx) failed: %d", ret);
- goto err_disable_clk_master_bus;
+ if (clk_valid(&eqos->clk_rx)) {
+ ret = clk_enable(&eqos->clk_rx);
+ if (ret < 0) {
+ pr_err("clk_enable(clk_rx) failed: %d", ret);
+ goto err_disable_clk_master_bus;
+ }
}
- ret = clk_enable(&eqos->clk_tx);
- if (ret < 0) {
- pr_err("clk_enable(clk_tx) failed: %d", ret);
- goto err_disable_clk_rx;
+ if (clk_valid(&eqos->clk_tx)) {
+ ret = clk_enable(&eqos->clk_tx);
+ if (ret < 0) {
+ pr_err("clk_enable(clk_tx) failed: %d", ret);
+ goto err_disable_clk_rx;
+ }
}
if (clk_valid(&eqos->clk_ck)) {
@@ -616,9 +620,11 @@ static int eqos_start_clks_stm32(struct udevice *dev)
return 0;
err_disable_clk_tx:
- clk_disable(&eqos->clk_tx);
+ if (clk_valid(&eqos->clk_tx))
+ clk_disable(&eqos->clk_tx);
err_disable_clk_rx:
- clk_disable(&eqos->clk_rx);
+ if (clk_valid(&eqos->clk_rx))
+ clk_disable(&eqos->clk_rx);
err_disable_clk_master_bus:
clk_disable(&eqos->clk_master_bus);
err:
@@ -647,8 +653,10 @@ static void eqos_stop_clks_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- clk_disable(&eqos->clk_tx);
- clk_disable(&eqos->clk_rx);
+ if (clk_valid(&eqos->clk_tx))
+ clk_disable(&eqos->clk_tx);
+ if (clk_valid(&eqos->clk_rx))
+ clk_disable(&eqos->clk_rx);
clk_disable(&eqos->clk_master_bus);
if (clk_valid(&eqos->clk_ck))
clk_disable(&eqos->clk_ck);
@@ -1682,20 +1690,16 @@ static int eqos_probe_resources_stm32(struct udevice
*dev)
ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
if (ret) {
pr_err("clk_get_by_name(master_bus) failed: %d", ret);
- goto err_probe;
+ return ret;
}
ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
- if (ret) {
- pr_err("clk_get_by_name(rx) failed: %d", ret);
- goto err_free_clk_master_bus;
- }
+ if (ret)
+ pr_warn("clk_get_by_name(rx) failed: %d", ret);
ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
- if (ret) {
- pr_err("clk_get_by_name(tx) failed: %d", ret);
- goto err_free_clk_rx;
- }
+ if (ret)
+ pr_warn("clk_get_by_name(tx) failed: %d", ret);
/* Get ETH_CLK clocks (optional) */
ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
@@ -1740,15 +1744,6 @@ static int eqos_probe_resources_stm32(struct udevice
*dev)
debug("%s: OK\n", __func__);
return 0;
-
-err_free_clk_rx:
- clk_free(&eqos->clk_rx);
-err_free_clk_master_bus:
- clk_free(&eqos->clk_master_bus);
-err_probe:
-
- debug("%s: returns %d\n", __func__, ret);
- return ret;
}
static phy_interface_t eqos_get_interface_stm32(struct udevice *dev)
@@ -1794,8 +1789,10 @@ static int eqos_remove_resources_stm32(struct udevice
*dev)
debug("%s(dev=%p):\n", __func__, dev);
- clk_free(&eqos->clk_tx);
- clk_free(&eqos->clk_rx);
+ if (clk_valid(&eqos->clk_tx))
+ clk_free(&eqos->clk_tx);
+ if (clk_valid(&eqos->clk_rx))
+ clk_free(&eqos->clk_rx);
clk_free(&eqos->clk_master_bus);
if (clk_valid(&eqos->clk_ck))
clk_free(&eqos->clk_ck);
--
2.19.1
[PATCH v2 01/11] net: dwc_eth_qos: Use dev_ functions calls to get FDT data
It seems dev_ functions are more general than fdt_ functions.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 63f2086dec..a72132cacf 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1728,8 +1728,7 @@ static phy_interface_t eqos_get_interface_stm32(struct
udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
- NULL);
+ phy_mode = dev_read_string(dev, "phy-mode");
if (phy_mode)
interface = phy_get_interface_by_name(phy_mode);
@@ -1788,9 +1787,9 @@ static int eqos_probe(struct udevice *dev)
eqos->dev = dev;
eqos->config = (void *)dev_get_driver_data(dev);
- eqos->regs = devfdt_get_addr(dev);
+ eqos->regs = dev_read_addr(dev);
if (eqos->regs == FDT_ADDR_T_NONE) {
- pr_err("devfdt_get_addr() failed");
+ pr_err("dev_read_addr() failed");
return -ENODEV;
}
eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
--
2.19.1
[PATCH v2 05/11] net: dwc_eth_qos: Split eqos_start() to get link speed
For Rockchip, before enabling mac and mac working, we
need to obtain the current link speed to configure the
TX/RX clocks, so split eqos_start into two functions.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 56 ++-
1 file changed, 38 insertions(+), 18 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 30e72a9d7d..c6a1eed7de 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1051,19 +1051,15 @@ static int eqos_write_hwaddr(struct udevice *dev)
return 0;
}
-static int eqos_start(struct udevice *dev)
+static int eqos_init(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
- int ret, i;
+ int ret;
ulong rate;
- u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
- ulong last_rx_desc;
+ u32 val;
debug("%s(dev=%p):\n", __func__, dev);
- eqos->tx_desc_idx = 0;
- eqos->rx_desc_idx = 0;
-
ret = eqos->config->ops->eqos_start_clks(dev);
if (ret < 0) {
pr_err("eqos_start_clks() failed: %d", ret);
@@ -1142,6 +1138,30 @@ static int eqos_start(struct udevice *dev)
goto err_shutdown_phy;
}
+ debug("%s: OK\n", __func__);
+ return 0;
+
+err_shutdown_phy:
+ phy_shutdown(eqos->phy);
+err_stop_resets:
+ eqos->config->ops->eqos_stop_resets(dev);
+err_stop_clks:
+ eqos->config->ops->eqos_stop_clks(dev);
+err:
+ pr_err("FAILED: %d", ret);
+ return ret;
+}
+
+static void eqos_enable(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
+ ulong last_rx_desc;
+ int i;
+
+ eqos->tx_desc_idx = 0;
+ eqos->rx_desc_idx = 0;
+
/* Configure MTL */
/* Enable Store and Forward mode for TX */
@@ -1343,19 +1363,19 @@ static int eqos_start(struct udevice *dev)
writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
eqos->started = true;
+}
- debug("%s: OK\n", __func__);
- return 0;
+static int eqos_start(struct udevice *dev)
+{
+ int ret;
-err_shutdown_phy:
- phy_shutdown(eqos->phy);
-err_stop_resets:
- eqos->config->ops->eqos_stop_resets(dev);
-err_stop_clks:
- eqos->config->ops->eqos_stop_clks(dev);
-err:
- pr_err("FAILED: %d", ret);
- return ret;
+ ret = eqos_init(dev);
+ if (ret)
+ return ret;
+
+ eqos_enable(dev);
+
+ return 0;
}
static void eqos_stop(struct udevice *dev)
--
2.19.1
[PATCH v2 06/11] net: dwc_eth_qos: make eqos_start_clks and eqos_stop_clks optional
If there are definitions for eqos_start_clks and eqos_stop_clks,
then call these callback function.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index c6a1eed7de..86e5a01d44 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1060,10 +1060,12 @@ static int eqos_init(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- ret = eqos->config->ops->eqos_start_clks(dev);
- if (ret < 0) {
- pr_err("eqos_start_clks() failed: %d", ret);
- goto err;
+ if (eqos->config->ops->eqos_start_clks) {
+ ret = eqos->config->ops->eqos_start_clks(dev);
+ if (ret < 0) {
+ pr_err("eqos_start_clks() failed: %d", ret);
+ goto err;
+ }
}
ret = eqos->config->ops->eqos_start_resets(dev);
@@ -1146,7 +1148,8 @@ err_shutdown_phy:
err_stop_resets:
eqos->config->ops->eqos_stop_resets(dev);
err_stop_clks:
- eqos->config->ops->eqos_stop_clks(dev);
+ if (eqos->config->ops->eqos_stop_clks)
+ eqos->config->ops->eqos_stop_clks(dev);
err:
pr_err("FAILED: %d", ret);
return ret;
@@ -1427,7 +1430,8 @@ static void eqos_stop(struct udevice *dev)
phy_shutdown(eqos->phy);
}
eqos->config->ops->eqos_stop_resets(dev);
- eqos->config->ops->eqos_stop_clks(dev);
+ if (eqos->config->ops->eqos_stop_clks)
+ eqos->config->ops->eqos_stop_clks(dev);
debug("%s: OK\n", __func__);
}
--
2.19.1
[PATCH v2 08/11] net: gmac_rockchip: Add dwc_eth_qos support
Change the original data structure so that Rockchip's Soc
gmac controller can support the designware.c and dwc_eth_qos.c
drivers, a Soc can only support one.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/Kconfig | 2 +-
drivers/net/gmac_rockchip.c | 160 ++--
2 files changed, 135 insertions(+), 27 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4d1013c984..07d2b0787c 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -482,7 +482,7 @@ config PIC32_ETH
config GMAC_ROCKCHIP
bool "Rockchip Synopsys Designware Ethernet MAC"
- depends on DM_ETH && ETH_DESIGNWARE
+ depends on DM_ETH && (ETH_DESIGNWARE || DWC_ETH_QOS)
help
This driver provides Rockchip SoCs network support based on the
Synopsys Designware driver.
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index e152faf083..aa2bab4203 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -25,26 +25,39 @@
#include
#include
#include "designware.h"
+#include "dwc_eth_qos.h"
DECLARE_GLOBAL_DATA_PTR;
#define DELAY_ENABLE(soc, tx, rx) \
(((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE :
soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE :
soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
+struct rockchip_eth_dev {
+ union {
+ struct eqos_priv eqos;
+ struct dw_eth_dev dw;
+ };
+};
+
/*
* Platform data for the gmac
*
* dw_eth_pdata: Required platform data for designware driver (must be first)
*/
struct gmac_rockchip_platdata {
- struct dw_eth_pdata dw_eth_pdata;
+ union {
+ struct dw_eth_pdata dw_eth_pdata;
+ struct eth_pdata eth_pdata;
+ };
+ bool has_gmac4;
bool clock_input;
int tx_delay;
int rx_delay;
};
struct rk_gmac_ops {
- int (*fix_mac_speed)(struct dw_eth_dev *priv);
+ const struct eqos_config config;
+ int (*fix_mac_speed)(struct rockchip_eth_dev *dev);
void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
};
@@ -55,6 +68,9 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice
*dev)
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
const char *string;
+ if (device_is_compatible(dev, "snps,dwmac-4.20a"))
+ pdata->has_gmac4 = true;
+
string = dev_read_string(dev, "clock_in_out");
if (!strcmp(string, "input"))
pdata->clock_input = true;
@@ -71,11 +87,15 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice
*dev)
if (pdata->rx_delay == -ENOENT)
pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
- return designware_eth_ofdata_to_platdata(dev);
+ if (!pdata->has_gmac4)
+ return designware_eth_ofdata_to_platdata(dev);
+
+ return 0;
}
-static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int px30_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct px30_grf *grf;
struct clk clk_speed;
int speed, ret;
@@ -115,8 +135,9 @@ static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
}
-static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3228_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct rk322x_grf *grf;
int clk;
enum {
@@ -148,8 +169,9 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3288_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct rk3288_grf *grf;
int clk;
@@ -174,8 +196,9 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3308_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct rk3308_grf *grf;
struct clk clk_speed;
int speed, ret;
@@ -215,8 +238,9 @@ static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3328_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct rk3328_grf_regs *grf;
int clk;
enum {
@@ -248,8 +272,9 @@ static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3368_gmac_fix_mac_spe
[PATCH v2 09/11] net: dwc_eth_qos: Add eqos_rockchip_ops
The eqos_rockchip_ops is simillar to eqos_stm32_ops, and
export the eqos_rockchip_ops to use.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 16
drivers/net/dwc_eth_qos.h | 2 ++
2 files changed, 18 insertions(+)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index d6c0622de6..7453b92f40 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1907,6 +1907,22 @@ static const struct eqos_config eqos_stm32_config = {
.ops = &eqos_stm32_ops
};
+struct eqos_ops eqos_rockchip_ops = {
+ .eqos_inval_desc = eqos_inval_desc_stm32,
+ .eqos_flush_desc = eqos_flush_desc_stm32,
+ .eqos_inval_buffer = eqos_inval_buffer_stm32,
+ .eqos_flush_buffer = eqos_flush_buffer_stm32,
+ .eqos_probe_resources = eqos_probe_resources_stm32,
+ .eqos_remove_resources = eqos_remove_resources_stm32,
+ .eqos_stop_resets = eqos_stop_resets_stm32,
+ .eqos_start_resets = eqos_start_resets_stm32,
+ .eqos_calibrate_pads = eqos_calibrate_pads_stm32,
+ .eqos_disable_calibration = eqos_disable_calibration_stm32,
+ .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32,
+ .eqos_get_interface = eqos_get_interface_stm32
+};
+
static const struct udevice_id eqos_ids[] = {
{
.compatible = "nvidia,tegra186-eqos",
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index 3125a301f0..def2706271 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -84,4 +84,6 @@ int eqos_recv(struct udevice *dev, int flags, uchar
**packetp);
int eqos_free_pkt(struct udevice *dev, uchar *packet, int length);
int eqos_write_hwaddr(struct udevice *dev);
+extern struct eqos_ops eqos_rockchip_ops;
+
#endif
--
2.19.1
[PATCH v2 10/11] net: dwc_eth_qos: Add EQOS_MAC_MDIO_ADDRESS_CR_100_150 for Rockchip
The Rockchip CSR clock range is from 100M to 150M, add
EQOS_MAC_MDIO_ADDRESS_CR_100_150.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index def2706271..39f8452c17 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -12,10 +12,10 @@
#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
+#define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1
#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
-
struct eqos_config {
bool reg_access_always_ok;
int mdio_wait;
--
2.19.1
[PATCH v2 11/11] net: gmac_rockchip: Add RV1126 gmac support
This Soc is different from the previous Socs, need to
define eqos_config, and follow the dwc_eth_qos driver
process.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/gmac_rockchip.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index aa2bab4203..d48a0f516b 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -368,6 +368,13 @@ static int rv1108_set_rmii_speed(struct rockchip_eth_dev
*dev)
return 0;
}
+static int rv1126_set_rgmii_speed(struct rockchip_eth_dev *dev)
+{
+ /* TO DO... */
+
+ return 0;
+}
+
static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
{
struct px30_grf *grf;
@@ -577,6 +584,11 @@ static void rv1108_gmac_set_to_rmii(struct
gmac_rockchip_platdata *pdata)
RV1108_GMAC_PHY_INTF_SEL_RMII);
}
+static void rv1126_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ /* TO DO... */
+}
+
static int gmac_rockchip_probe(struct udevice *dev)
{
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
@@ -837,6 +849,20 @@ const struct rk_gmac_ops rv1108_gmac_ops = {
.set_to_rmii = rv1108_gmac_set_to_rmii,
};
+const struct rk_gmac_ops rv1126_gmac_ops = {
+ .config = {
+ .reg_access_always_ok = false,
+ .mdio_wait = 1,
+ .swr_wait = 200,
+ .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED,
+ .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150,
+ .ops = &eqos_rockchip_ops
+ },
+
+ .fix_mac_speed = rv1126_set_rgmii_speed,
+ .set_to_rgmii = rv1126_set_to_rgmii,
+};
+
static const struct udevice_id rockchip_gmac_ids[] = {
{ .compatible = "rockchip,px30-gmac",
.data = (ulong)&px30_gmac_ops },
@@ -854,6 +880,8 @@ static const struct udevice_id rockchip_gmac_ids[] = {
.data = (ulong)&rk3399_gmac_ops },
{ .compatible = "rockchip,rv1108-gmac",
.data = (ulong)&rv1108_gmac_ops },
+ { .compatible = "rockchip,rv1126-gmac",
+ .data = (ulong)&rv1126_gmac_ops },
{ }
};
--
2.19.1
Re: [PATCH v2 10/11] net: dwc_eth_qos: Add EQOS_MAC_MDIO_ADDRESS_CR_100_150 for Rockchip
Discard this duplicate patch.
在 2020/5/11 下午3:08, David Wu 写道:
The Rockchip CSR clock range is from 100M to 150M, add
EQOS_MAC_MDIO_ADDRESS_CR_100_150.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index def2706271..39f8452c17 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -12,10 +12,10 @@
#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
+#define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1
#define EQOS_MAC_MDIO_ADDRESS_CR_20_352
#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
-
struct eqos_config {
bool reg_access_always_ok;
int mdio_wait;
[PATCH v2 07/11] net: dwc_eth_qos: Export common struct and interface at head file
Open structure data and interface, so that Soc using dw_eth_qos
controller can reference.
Signed-off-by: David Wu
---
Changes in v2:
- Add the lost head file. (Patrice)
drivers/net/dwc_eth_qos.c | 81
drivers/net/dwc_eth_qos.h | 87 +++
2 files changed, 96 insertions(+), 72 deletions(-)
create mode 100644 drivers/net/dwc_eth_qos.h
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 86e5a01d44..d6c0622de6 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -41,6 +41,7 @@
#include
#include
#include
+#include "dwc_eth_qos.h"
/* Core registers */
@@ -94,9 +95,6 @@ struct eqos_mac_regs {
#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT0
#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
@@ -109,8 +107,6 @@ struct eqos_mac_regs {
#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT16
#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
-#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
-#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT2
#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
@@ -261,65 +257,6 @@ struct eqos_desc {
#define EQOS_DESC3_LD BIT(28)
#define EQOS_DESC3_BUF1V BIT(24)
-struct eqos_config {
- bool reg_access_always_ok;
- int mdio_wait;
- int swr_wait;
- int config_mac;
- int config_mac_mdio;
- struct eqos_ops *ops;
-};
-
-struct eqos_ops {
- void (*eqos_inval_desc)(void *desc);
- void (*eqos_flush_desc)(void *desc);
- void (*eqos_inval_buffer)(void *buf, size_t size);
- void (*eqos_flush_buffer)(void *buf, size_t size);
- int (*eqos_probe_resources)(struct udevice *dev);
- int (*eqos_remove_resources)(struct udevice *dev);
- int (*eqos_stop_resets)(struct udevice *dev);
- int (*eqos_start_resets)(struct udevice *dev);
- void (*eqos_stop_clks)(struct udevice *dev);
- int (*eqos_start_clks)(struct udevice *dev);
- int (*eqos_calibrate_pads)(struct udevice *dev);
- int (*eqos_disable_calibration)(struct udevice *dev);
- int (*eqos_set_tx_clk_speed)(struct udevice *dev);
- ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
- phy_interface_t (*eqos_get_interface)(struct udevice *dev);
-};
-
-struct eqos_priv {
- struct udevice *dev;
- const struct eqos_config *config;
- fdt_addr_t regs;
- struct eqos_mac_regs *mac_regs;
- struct eqos_mtl_regs *mtl_regs;
- struct eqos_dma_regs *dma_regs;
- struct eqos_tegra186_regs *tegra186_regs;
- struct reset_ctl reset_ctl;
- struct gpio_desc phy_reset_gpio;
- u32 reset_delays[3];
- struct clk clk_master_bus;
- struct clk clk_rx;
- struct clk clk_ptp_ref;
- struct clk clk_tx;
- struct clk clk_ck;
- struct clk clk_slave_bus;
- struct mii_dev *mii;
- struct phy_device *phy;
- int phyaddr;
- u32 max_speed;
- void *descs;
- struct eqos_desc *tx_descs;
- struct eqos_desc *rx_descs;
- int tx_desc_idx, rx_desc_idx;
- void *tx_dma_buf;
- void *rx_dma_buf;
- void *rx_pkt;
- bool started;
- bool reg_access_ok;
-};
-
/*
* TX and RX descriptors are 16 bytes. This causes problems with the cache
* maintenance on CPUs where the cache-line size exceeds the size of these
@@ -1007,7 +944,7 @@ static int eqos_adjust_link(struct udevice *dev)
return 0;
}
-static int eqos_write_hwaddr(struct udevice *dev)
+int eqos_write_hwaddr(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_platdata(dev);
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1051,7 +988,7 @@ static int eqos_write_hwaddr(struct udevice *dev)
return 0;
}
-static int eqos_init(struct udevice *dev)
+int eqos_init(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
int ret;
@@ -1155,7 +1092,7 @@ err:
return ret;
}
-static void eqos_enable(struct udevice *dev)
+void eqos_enable(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
@@ -1381,7 +1318,7 @@ static int eqos_start(struct udevice *dev)
return 0;
}
-static void eqos_stop(struct udevice *dev)
+void eqos_stop(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
int i;
[PATCH v2 10/11] net: dwc_eth_qos: Add EQOS_MAC_MDIO_ADDRESS_CR_100_150 for Rockchip
The Rockchip CSR clock range is from 100M to 150M, add
EQOS_MAC_MDIO_ADDRESS_CR_100_150.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index def2706271..39f8452c17 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -12,10 +12,10 @@
#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
+#define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1
#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
-
struct eqos_config {
bool reg_access_always_ok;
int mdio_wait;
--
2.19.1
Re: [PATCH 6/8] net: dwc_eth_qos: Split eqos_start() to get link speed
Hi Patrice, 在 2020/5/11 下午8:48, Patrice CHOTARD 写道: Hi David On 5/9/20 8:42 AM, David Wu wrote: Hi Patrice, 在 2020/4/30 下午11:33, Patrice CHOTARD 写道: Can you explain why you are splitting this function in 2 parts and calling these parts sequentially ? For rockchip, need to obtain the current link speed to configure the tx clocks, (for example, in rgmii mode, 1000M link: 125M, 100M link: 25M, 10M link is 2.5M rate) and then enable gmac. So after the adjust_link(), before the start gamc, this intermediate stage needs to configure the clock according to the current link speed. Please, add these informations in the commit message I will add it at the next version, Thanks. Thanks Patrice
[RESEND PATCH v2 00/11] Add dwc_eth_qos support for rockchip
Rockchip Socs can support two controllers "snps, dwmac-4.20a" and "snps, dwmac-3.50". In order to support two at gmac-rockchip.c, export public interface functions and struct data, it will be more general for others. Changes in v2: - None - Remove the code is not related (Patrice) - None - Don't change the Rx and Tx clock names. (Patrice, Stephen) - None - None - Add the lost head file. (Patrice) - None - None - None - None David Wu (11): net: dwc_eth_qos: Use dev_ functions calls to get FDT data net: dwc_eth_qos: Add option "snps,reset-gpio" phy-rst gpio for stm32 net: dwc_eth_qos: Move interface() to eqos_ops structure net: dwc_eth_qos: Make clk_rx and clk_tx optional net: dwc_eth_qos: Split eqos_start() to get link speed net: dwc_eth_qos: make eqos_start_clks and eqos_stop_clks optional net: dwc_eth_qos: Export common struct and interface at head file net: gmac_rockchip: Add dwc_eth_qos support net: dwc_eth_qos: Add eqos_rockchip_ops net: dwc_eth_qos: Add EQOS_MAC_MDIO_ADDRESS_CR_100_150 for Rockchip net: gmac_rockchip: Add RV1126 gmac support drivers/net/Kconfig | 2 +- drivers/net/dwc_eth_qos.c | 279 ++-- drivers/net/dwc_eth_qos.h | 89 drivers/net/gmac_rockchip.c | 188 4 files changed, 393 insertions(+), 165 deletions(-) create mode 100644 drivers/net/dwc_eth_qos.h -- 2.19.1
[RESEND PATCH v2 01/11] net: dwc_eth_qos: Use dev_ functions calls to get FDT data
It seems dev_ functions are more general than fdt_ functions.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index f67c5f4570..66a02aa80b 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1889,8 +1889,7 @@ static phy_interface_t eqos_get_interface_stm32(struct
udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
- NULL);
+ phy_mode = dev_read_string(dev, "phy-mode");
if (phy_mode)
interface = phy_get_interface_by_name(phy_mode);
@@ -1991,9 +1990,9 @@ static int eqos_probe(struct udevice *dev)
eqos->dev = dev;
eqos->config = (void *)dev_get_driver_data(dev);
- eqos->regs = devfdt_get_addr(dev);
+ eqos->regs = dev_read_addr(dev);
if (eqos->regs == FDT_ADDR_T_NONE) {
- pr_err("devfdt_get_addr() failed");
+ pr_err("dev_read_addr() failed");
return -ENODEV;
}
eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
--
2.19.1
[RESEND PATCH v2 02/11] net: dwc_eth_qos: Add option "snps, reset-gpio" phy-rst gpio for stm32
It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
gpio is used, adding this option makes reset function more general.
Signed-off-by: David Wu
---
Changes in v2:
- Remove the code is not related (Patrice)
drivers/net/dwc_eth_qos.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 66a02aa80b..92dab678c7 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -314,6 +314,7 @@ struct eqos_priv {
struct eqos_tegra186_regs *tegra186_regs;
struct reset_ctl reset_ctl;
struct gpio_desc phy_reset_gpio;
+ u32 reset_delays[3];
struct clk clk_master_bus;
struct clk clk_rx;
struct clk clk_ptp_ref;
@@ -739,6 +740,15 @@ static int eqos_start_resets_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
+ ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
+ if (ret < 0) {
+ pr_err("dm_gpio_set_value(phy_reset, deassert) failed:
%d",
+ ret);
+ return ret;
+ }
+
+ udelay(eqos->reset_delays[0]);
+
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
if (ret < 0) {
pr_err("dm_gpio_set_value(phy_reset, assert) failed:
%d",
@@ -746,7 +756,7 @@ static int eqos_start_resets_stm32(struct udevice *dev)
return ret;
}
- udelay(2);
+ udelay(eqos->reset_delays[1]);
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
if (ret < 0) {
@@ -754,6 +764,8 @@ static int eqos_start_resets_stm32(struct udevice *dev)
ret);
return ret;
}
+
+ udelay(eqos->reset_delays[2]);
}
debug("%s: OK\n", __func__);
@@ -1864,11 +1876,29 @@ static int eqos_probe_resources_stm32(struct udevice
*dev)
if (ret)
pr_warn("gpio_request_by_name(phy reset) not provided
%d",
ret);
+ else
+ eqos->reset_delays[1] = 2;
eqos->phyaddr = ofnode_read_u32_default(phandle_args.node,
"reg", -1);
}
+ if (!dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
+ int reset_flags = GPIOD_IS_OUT;
+
+ if (dev_read_bool(dev, "snps,reset-active-low"))
+ reset_flags |= GPIOD_ACTIVE_LOW;
+
+ ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
+ &eqos->phy_reset_gpio, reset_flags);
+ if (ret == 0)
+ ret = dev_read_u32_array(dev, "snps,reset-delays-us",
+eqos->reset_delays, 3);
+ else
+ pr_warn("gpio_request_by_name(snps,reset-gpio) failed:
%d",
+ ret);
+ }
+
debug("%s: OK\n", __func__);
return 0;
--
2.19.1
[RESEND PATCH v2 04/11] net: dwc_eth_qos: Make clk_rx and clk_tx optional
For others using, clk_rx and clk_tx may not be necessary,
and their clock names are different.
Signed-off-by: David Wu
---
Changes in v2:
- Don't change the Rx and Tx clock names. (Patrice, Stephen)
drivers/net/dwc_eth_qos.c | 61 +++
1 file changed, 29 insertions(+), 32 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index ae2167637f..bec9bf556b 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -613,16 +613,20 @@ static int eqos_start_clks_stm32(struct udevice *dev)
goto err;
}
- ret = clk_enable(&eqos->clk_rx);
- if (ret < 0) {
- pr_err("clk_enable(clk_rx) failed: %d", ret);
- goto err_disable_clk_master_bus;
+ if (clk_valid(&eqos->clk_rx)) {
+ ret = clk_enable(&eqos->clk_rx);
+ if (ret < 0) {
+ pr_err("clk_enable(clk_rx) failed: %d", ret);
+ goto err_disable_clk_master_bus;
+ }
}
- ret = clk_enable(&eqos->clk_tx);
- if (ret < 0) {
- pr_err("clk_enable(clk_tx) failed: %d", ret);
- goto err_disable_clk_rx;
+ if (clk_valid(&eqos->clk_tx)) {
+ ret = clk_enable(&eqos->clk_tx);
+ if (ret < 0) {
+ pr_err("clk_enable(clk_tx) failed: %d", ret);
+ goto err_disable_clk_rx;
+ }
}
if (clk_valid(&eqos->clk_ck)) {
@@ -639,9 +643,11 @@ static int eqos_start_clks_stm32(struct udevice *dev)
#ifdef CONFIG_CLK
err_disable_clk_tx:
- clk_disable(&eqos->clk_tx);
+ if (clk_valid(&eqos->clk_tx))
+ clk_disable(&eqos->clk_tx);
err_disable_clk_rx:
- clk_disable(&eqos->clk_rx);
+ if (clk_valid(&eqos->clk_rx))
+ clk_disable(&eqos->clk_rx);
err_disable_clk_master_bus:
clk_disable(&eqos->clk_master_bus);
err:
@@ -679,8 +685,10 @@ static void eqos_stop_clks_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- clk_disable(&eqos->clk_tx);
- clk_disable(&eqos->clk_rx);
+ if (clk_valid(&eqos->clk_tx))
+ clk_disable(&eqos->clk_tx);
+ if (clk_valid(&eqos->clk_rx))
+ clk_disable(&eqos->clk_rx);
clk_disable(&eqos->clk_master_bus);
if (clk_valid(&eqos->clk_ck))
clk_disable(&eqos->clk_ck);
@@ -1843,20 +1851,16 @@ static int eqos_probe_resources_stm32(struct udevice
*dev)
ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
if (ret) {
pr_err("clk_get_by_name(master_bus) failed: %d", ret);
- goto err_probe;
+ return ret;
}
ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
- if (ret) {
- pr_err("clk_get_by_name(rx) failed: %d", ret);
- goto err_free_clk_master_bus;
- }
+ if (ret)
+ pr_warn("clk_get_by_name(rx) failed: %d", ret);
ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
- if (ret) {
- pr_err("clk_get_by_name(tx) failed: %d", ret);
- goto err_free_clk_rx;
- }
+ if (ret)
+ pr_warn("clk_get_by_name(tx) failed: %d", ret);
/* Get ETH_CLK clocks (optional) */
ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
@@ -1901,15 +1905,6 @@ static int eqos_probe_resources_stm32(struct udevice
*dev)
debug("%s: OK\n", __func__);
return 0;
-
-err_free_clk_rx:
- clk_free(&eqos->clk_rx);
-err_free_clk_master_bus:
- clk_free(&eqos->clk_master_bus);
-err_probe:
-
- debug("%s: returns %d\n", __func__, ret);
- return ret;
}
static phy_interface_t eqos_get_interface_stm32(struct udevice *dev)
@@ -1991,8 +1986,10 @@ static int eqos_remove_resources_stm32(struct udevice
*dev)
debug("%s(dev=%p):\n", __func__, dev);
- clk_free(&eqos->clk_tx);
- clk_free(&eqos->clk_rx);
+ if (clk_valid(&eqos->clk_tx))
+ clk_free(&eqos->clk_tx);
+ if (clk_valid(&eqos->clk_rx))
+ clk_free(&eqos->clk_rx);
clk_free(&eqos->clk_master_bus);
if (clk_valid(&eqos->clk_ck))
clk_free(&eqos->clk_ck);
--
2.19.1
[RESEND PATCH v2 05/11] net: dwc_eth_qos: Split eqos_start() to get link speed
For Rockchip, need to obtain the current link speed to
configure the tx clocks, (for example, in rgmii mode,
1000M link: 125M, 100M link: 25M, 10M link is 2.5M rate)
and then enable gmac. So after the adjust_link(), before
the start gamc, this intermediate stage needs to configure
the clock according to the current link speed.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 56 ++-
1 file changed, 38 insertions(+), 18 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index bec9bf556b..e503be5b4b 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1175,19 +1175,15 @@ static int eqos_read_rom_hwaddr(struct udevice *dev)
return !is_valid_ethaddr(pdata->enetaddr);
}
-static int eqos_start(struct udevice *dev)
+static int eqos_init(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
- int ret, i;
+ int ret;
ulong rate;
- u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
- ulong last_rx_desc;
+ u32 val;
debug("%s(dev=%p):\n", __func__, dev);
- eqos->tx_desc_idx = 0;
- eqos->rx_desc_idx = 0;
-
ret = eqos->config->ops->eqos_start_clks(dev);
if (ret < 0) {
pr_err("eqos_start_clks() failed: %d", ret);
@@ -1273,6 +1269,30 @@ static int eqos_start(struct udevice *dev)
goto err_shutdown_phy;
}
+ debug("%s: OK\n", __func__);
+ return 0;
+
+err_shutdown_phy:
+ phy_shutdown(eqos->phy);
+err_stop_resets:
+ eqos->config->ops->eqos_stop_resets(dev);
+err_stop_clks:
+ eqos->config->ops->eqos_stop_clks(dev);
+err:
+ pr_err("FAILED: %d", ret);
+ return ret;
+}
+
+static void eqos_enable(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
+ ulong last_rx_desc;
+ int i;
+
+ eqos->tx_desc_idx = 0;
+ eqos->rx_desc_idx = 0;
+
/* Configure MTL */
writel(0x60, &eqos->mtl_regs->txq0_quantum_weight - 0x100);
@@ -1492,19 +1512,19 @@ static int eqos_start(struct udevice *dev)
writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
eqos->started = true;
+}
- debug("%s: OK\n", __func__);
- return 0;
+static int eqos_start(struct udevice *dev)
+{
+ int ret;
-err_shutdown_phy:
- phy_shutdown(eqos->phy);
-err_stop_resets:
- eqos->config->ops->eqos_stop_resets(dev);
-err_stop_clks:
- eqos->config->ops->eqos_stop_clks(dev);
-err:
- pr_err("FAILED: %d", ret);
- return ret;
+ ret = eqos_init(dev);
+ if (ret)
+ return ret;
+
+ eqos_enable(dev);
+
+ return 0;
}
static void eqos_stop(struct udevice *dev)
--
2.19.1
[RESEND PATCH v2 06/11] net: dwc_eth_qos: make eqos_start_clks and eqos_stop_clks optional
If there are definitions for eqos_start_clks and eqos_stop_clks,
then call these callback function.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index e503be5b4b..295707cbb0 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1184,10 +1184,12 @@ static int eqos_init(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- ret = eqos->config->ops->eqos_start_clks(dev);
- if (ret < 0) {
- pr_err("eqos_start_clks() failed: %d", ret);
- goto err;
+ if (eqos->config->ops->eqos_start_clks) {
+ ret = eqos->config->ops->eqos_start_clks(dev);
+ if (ret < 0) {
+ pr_err("eqos_start_clks() failed: %d", ret);
+ goto err;
+ }
}
ret = eqos->config->ops->eqos_start_resets(dev);
@@ -1277,7 +1279,8 @@ err_shutdown_phy:
err_stop_resets:
eqos->config->ops->eqos_stop_resets(dev);
err_stop_clks:
- eqos->config->ops->eqos_stop_clks(dev);
+ if (eqos->config->ops->eqos_stop_clks)
+ eqos->config->ops->eqos_stop_clks(dev);
err:
pr_err("FAILED: %d", ret);
return ret;
@@ -1576,7 +1579,8 @@ static void eqos_stop(struct udevice *dev)
phy_shutdown(eqos->phy);
}
eqos->config->ops->eqos_stop_resets(dev);
- eqos->config->ops->eqos_stop_clks(dev);
+ if (eqos->config->ops->eqos_stop_clks)
+ eqos->config->ops->eqos_stop_clks(dev);
debug("%s: OK\n", __func__);
}
--
2.19.1
[RESEND PATCH v2 03/11] net: dwc_eth_qos: Move interface() to eqos_ops structure
After moving to eqos_ops, if eqos_config is defined
outside file, can not export interface() definition,
only export eqos_ops struct defined in dwc_eth_qos.c.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 92dab678c7..ae2167637f 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -283,7 +283,6 @@ struct eqos_config {
int swr_wait;
int config_mac;
int config_mac_mdio;
- phy_interface_t (*interface)(struct udevice *dev);
struct eqos_ops *ops;
};
@@ -302,6 +301,7 @@ struct eqos_ops {
int (*eqos_disable_calibration)(struct udevice *dev);
int (*eqos_set_tx_clk_speed)(struct udevice *dev);
ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
+ phy_interface_t (*eqos_get_interface)(struct udevice *dev);
};
struct eqos_priv {
@@ -1227,7 +1227,7 @@ static int eqos_start(struct udevice *dev)
addr = DWC_NET_PHYADDR;
#endif
eqos->phy = phy_connect(eqos->mii, addr, dev,
- eqos->config->interface(dev));
+eqos->config->ops->eqos_get_interface(dev));
if (!eqos->phy) {
pr_err("phy_connect() failed");
goto err_stop_resets;
@@ -1827,7 +1827,7 @@ static int eqos_probe_resources_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- interface = eqos->config->interface(dev);
+ interface = eqos->config->ops->eqos_get_interface(dev);
if (interface == PHY_INTERFACE_MODE_NONE) {
pr_err("Invalid PHY interface\n");
@@ -1938,7 +1938,7 @@ static int eqos_probe_resources_imx(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- interface = eqos->config->interface(dev);
+ interface = eqos->config->ops->eqos_get_interface(dev);
if (interface == PHY_INTERFACE_MODE_NONE) {
pr_err("Invalid PHY interface\n");
@@ -2122,7 +2122,8 @@ static struct eqos_ops eqos_tegra186_ops = {
.eqos_calibrate_pads = eqos_calibrate_pads_tegra186,
.eqos_disable_calibration = eqos_disable_calibration_tegra186,
.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186,
- .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186,
+ .eqos_get_interface = eqos_get_interface_tegra186
};
static const struct eqos_config eqos_tegra186_config = {
@@ -2131,7 +2132,6 @@ static const struct eqos_config eqos_tegra186_config = {
.swr_wait = 10,
.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35,
- .interface = eqos_get_interface_tegra186,
.ops = &eqos_tegra186_ops
};
@@ -2149,7 +2149,8 @@ static struct eqos_ops eqos_stm32_ops = {
.eqos_calibrate_pads = eqos_calibrate_pads_stm32,
.eqos_disable_calibration = eqos_disable_calibration_stm32,
.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
- .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32,
+ .eqos_get_interface = eqos_get_interface_stm32
};
static const struct eqos_config eqos_stm32_config = {
@@ -2158,7 +2159,6 @@ static const struct eqos_config eqos_stm32_config = {
.swr_wait = 50,
.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
- .interface = eqos_get_interface_stm32,
.ops = &eqos_stm32_ops
};
@@ -2176,7 +2176,8 @@ static struct eqos_ops eqos_imx_ops = {
.eqos_calibrate_pads = eqos_calibrate_pads_imx,
.eqos_disable_calibration = eqos_disable_calibration_imx,
.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
- .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx,
+ .eqos_get_interface = eqos_get_interface_imx
};
struct eqos_config eqos_imx_config = {
@@ -2185,7 +2186,6 @@ struct eqos_config eqos_imx_config = {
.swr_wait = 50,
.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
- .interface = eqos_get_interface_imx,
.ops = &eqos_imx_ops
};
--
2.19.1
[RESEND PATCH v2 07/11] net: dwc_eth_qos: Export common struct and interface at head file
Open structure data and interface, so that Soc using dw_eth_qos
controller can reference.
Signed-off-by: David Wu
---
Changes in v2:
- Add the lost head file. (Patrice)
drivers/net/dwc_eth_qos.c | 81
drivers/net/dwc_eth_qos.h | 87 +++
2 files changed, 96 insertions(+), 72 deletions(-)
create mode 100644 drivers/net/dwc_eth_qos.h
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 295707cbb0..b3195d484e 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -46,6 +46,7 @@
#include
#include
#endif
+#include "dwc_eth_qos.h"
/* Core registers */
@@ -100,9 +101,6 @@ struct eqos_mac_regs {
#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT0
#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
@@ -123,8 +121,6 @@ struct eqos_mac_regs {
#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT16
#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
-#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
-#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT2
#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
@@ -277,65 +273,6 @@ struct eqos_desc {
#define EQOS_DESC3_LD BIT(28)
#define EQOS_DESC3_BUF1V BIT(24)
-struct eqos_config {
- bool reg_access_always_ok;
- int mdio_wait;
- int swr_wait;
- int config_mac;
- int config_mac_mdio;
- struct eqos_ops *ops;
-};
-
-struct eqos_ops {
- void (*eqos_inval_desc)(void *desc);
- void (*eqos_flush_desc)(void *desc);
- void (*eqos_inval_buffer)(void *buf, size_t size);
- void (*eqos_flush_buffer)(void *buf, size_t size);
- int (*eqos_probe_resources)(struct udevice *dev);
- int (*eqos_remove_resources)(struct udevice *dev);
- int (*eqos_stop_resets)(struct udevice *dev);
- int (*eqos_start_resets)(struct udevice *dev);
- void (*eqos_stop_clks)(struct udevice *dev);
- int (*eqos_start_clks)(struct udevice *dev);
- int (*eqos_calibrate_pads)(struct udevice *dev);
- int (*eqos_disable_calibration)(struct udevice *dev);
- int (*eqos_set_tx_clk_speed)(struct udevice *dev);
- ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
- phy_interface_t (*eqos_get_interface)(struct udevice *dev);
-};
-
-struct eqos_priv {
- struct udevice *dev;
- const struct eqos_config *config;
- fdt_addr_t regs;
- struct eqos_mac_regs *mac_regs;
- struct eqos_mtl_regs *mtl_regs;
- struct eqos_dma_regs *dma_regs;
- struct eqos_tegra186_regs *tegra186_regs;
- struct reset_ctl reset_ctl;
- struct gpio_desc phy_reset_gpio;
- u32 reset_delays[3];
- struct clk clk_master_bus;
- struct clk clk_rx;
- struct clk clk_ptp_ref;
- struct clk clk_tx;
- struct clk clk_ck;
- struct clk clk_slave_bus;
- struct mii_dev *mii;
- struct phy_device *phy;
- int phyaddr;
- u32 max_speed;
- void *descs;
- struct eqos_desc *tx_descs;
- struct eqos_desc *rx_descs;
- int tx_desc_idx, rx_desc_idx;
- void *tx_dma_buf;
- void *rx_dma_buf;
- void *rx_pkt;
- bool started;
- bool reg_access_ok;
-};
-
/*
* TX and RX descriptors are 16 bytes. This causes problems with the cache
* maintenance on CPUs where the cache-line size exceeds the size of these
@@ -1121,7 +1058,7 @@ static int eqos_adjust_link(struct udevice *dev)
return 0;
}
-static int eqos_write_hwaddr(struct udevice *dev)
+int eqos_write_hwaddr(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_platdata(dev);
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1175,7 +1112,7 @@ static int eqos_read_rom_hwaddr(struct udevice *dev)
return !is_valid_ethaddr(pdata->enetaddr);
}
-static int eqos_init(struct udevice *dev)
+int eqos_init(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
int ret;
@@ -1286,7 +1223,7 @@ err:
return ret;
}
-static void eqos_enable(struct udevice *dev)
+void eqos_enable(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
@@ -1530,7 +1467,7 @@ static int eqos_start(struct udevice *dev)
return 0;
}
-static void eqos_stop(struct udevice *dev)
+void eqos_stop(struct udevice *dev)
{
struct eq
[RESEND PATCH v2 08/11] net: gmac_rockchip: Add dwc_eth_qos support
Change the original data structure so that Rockchip's Soc
gmac controller can support the designware.c and dwc_eth_qos.c
drivers, a Soc can only support one.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/Kconfig | 2 +-
drivers/net/gmac_rockchip.c | 160 ++--
2 files changed, 135 insertions(+), 27 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 38f2bd6637..d29adebee0 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -490,7 +490,7 @@ config PIC32_ETH
config GMAC_ROCKCHIP
bool "Rockchip Synopsys Designware Ethernet MAC"
- depends on DM_ETH && ETH_DESIGNWARE
+ depends on DM_ETH && (ETH_DESIGNWARE || DWC_ETH_QOS)
help
This driver provides Rockchip SoCs network support based on the
Synopsys Designware driver.
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index e152faf083..aa2bab4203 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -25,26 +25,39 @@
#include
#include
#include "designware.h"
+#include "dwc_eth_qos.h"
DECLARE_GLOBAL_DATA_PTR;
#define DELAY_ENABLE(soc, tx, rx) \
(((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE :
soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE :
soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
+struct rockchip_eth_dev {
+ union {
+ struct eqos_priv eqos;
+ struct dw_eth_dev dw;
+ };
+};
+
/*
* Platform data for the gmac
*
* dw_eth_pdata: Required platform data for designware driver (must be first)
*/
struct gmac_rockchip_platdata {
- struct dw_eth_pdata dw_eth_pdata;
+ union {
+ struct dw_eth_pdata dw_eth_pdata;
+ struct eth_pdata eth_pdata;
+ };
+ bool has_gmac4;
bool clock_input;
int tx_delay;
int rx_delay;
};
struct rk_gmac_ops {
- int (*fix_mac_speed)(struct dw_eth_dev *priv);
+ const struct eqos_config config;
+ int (*fix_mac_speed)(struct rockchip_eth_dev *dev);
void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
};
@@ -55,6 +68,9 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice
*dev)
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
const char *string;
+ if (device_is_compatible(dev, "snps,dwmac-4.20a"))
+ pdata->has_gmac4 = true;
+
string = dev_read_string(dev, "clock_in_out");
if (!strcmp(string, "input"))
pdata->clock_input = true;
@@ -71,11 +87,15 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice
*dev)
if (pdata->rx_delay == -ENOENT)
pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
- return designware_eth_ofdata_to_platdata(dev);
+ if (!pdata->has_gmac4)
+ return designware_eth_ofdata_to_platdata(dev);
+
+ return 0;
}
-static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int px30_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct px30_grf *grf;
struct clk clk_speed;
int speed, ret;
@@ -115,8 +135,9 @@ static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
}
-static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3228_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct rk322x_grf *grf;
int clk;
enum {
@@ -148,8 +169,9 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3288_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct rk3288_grf *grf;
int clk;
@@ -174,8 +196,9 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3308_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct rk3308_grf *grf;
struct clk clk_speed;
int speed, ret;
@@ -215,8 +238,9 @@ static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3328_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
{
+ struct dw_eth_dev *priv = &dev->dw;
struct rk3328_grf_regs *grf;
int clk;
enum {
@@ -248,8 +272,9 @@ static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
-static int rk3368_gmac_fix_mac_spe
[RESEND PATCH v2 10/11] net: dwc_eth_qos: Add EQOS_MAC_MDIO_ADDRESS_CR_100_150 for Rockchip
The Rockchip CSR clock range is from 100M to 150M, add
EQOS_MAC_MDIO_ADDRESS_CR_100_150.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index def2706271..39f8452c17 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -12,10 +12,10 @@
#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
+#define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1
#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
-
struct eqos_config {
bool reg_access_always_ok;
int mdio_wait;
--
2.19.1
[RESEND PATCH v2 09/11] net: dwc_eth_qos: Add eqos_rockchip_ops
The eqos_rockchip_ops is simillar to eqos_stm32_ops, and
export the eqos_rockchip_ops to use.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 16
drivers/net/dwc_eth_qos.h | 2 ++
2 files changed, 18 insertions(+)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index b3195d484e..f4f6f73849 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -2147,6 +2147,22 @@ struct eqos_config eqos_imx_config = {
.ops = &eqos_imx_ops
};
+struct eqos_ops eqos_rockchip_ops = {
+ .eqos_inval_desc = eqos_inval_desc_generic,
+ .eqos_flush_desc = eqos_flush_desc_generic,
+ .eqos_inval_buffer = eqos_inval_buffer_generic,
+ .eqos_flush_buffer = eqos_flush_buffer_generic,
+ .eqos_probe_resources = eqos_probe_resources_stm32,
+ .eqos_remove_resources = eqos_remove_resources_stm32,
+ .eqos_stop_resets = eqos_stop_resets_stm32,
+ .eqos_start_resets = eqos_start_resets_stm32,
+ .eqos_calibrate_pads = eqos_calibrate_pads_stm32,
+ .eqos_disable_calibration = eqos_disable_calibration_stm32,
+ .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32,
+ .eqos_get_interface = eqos_get_interface_stm32
+};
+
static const struct udevice_id eqos_ids[] = {
{
.compatible = "nvidia,tegra186-eqos",
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index 3125a301f0..def2706271 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -84,4 +84,6 @@ int eqos_recv(struct udevice *dev, int flags, uchar
**packetp);
int eqos_free_pkt(struct udevice *dev, uchar *packet, int length);
int eqos_write_hwaddr(struct udevice *dev);
+extern struct eqos_ops eqos_rockchip_ops;
+
#endif
--
2.19.1
[RESEND PATCH v2 11/11] net: gmac_rockchip: Add RV1126 gmac support
This Soc is different from the previous Socs, need to
define eqos_config, and follow the dwc_eth_qos driver
process.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/gmac_rockchip.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index aa2bab4203..d48a0f516b 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -368,6 +368,13 @@ static int rv1108_set_rmii_speed(struct rockchip_eth_dev
*dev)
return 0;
}
+static int rv1126_set_rgmii_speed(struct rockchip_eth_dev *dev)
+{
+ /* TO DO... */
+
+ return 0;
+}
+
static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
{
struct px30_grf *grf;
@@ -577,6 +584,11 @@ static void rv1108_gmac_set_to_rmii(struct
gmac_rockchip_platdata *pdata)
RV1108_GMAC_PHY_INTF_SEL_RMII);
}
+static void rv1126_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ /* TO DO... */
+}
+
static int gmac_rockchip_probe(struct udevice *dev)
{
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
@@ -837,6 +849,20 @@ const struct rk_gmac_ops rv1108_gmac_ops = {
.set_to_rmii = rv1108_gmac_set_to_rmii,
};
+const struct rk_gmac_ops rv1126_gmac_ops = {
+ .config = {
+ .reg_access_always_ok = false,
+ .mdio_wait = 1,
+ .swr_wait = 200,
+ .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED,
+ .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150,
+ .ops = &eqos_rockchip_ops
+ },
+
+ .fix_mac_speed = rv1126_set_rgmii_speed,
+ .set_to_rgmii = rv1126_set_to_rgmii,
+};
+
static const struct udevice_id rockchip_gmac_ids[] = {
{ .compatible = "rockchip,px30-gmac",
.data = (ulong)&px30_gmac_ops },
@@ -854,6 +880,8 @@ static const struct udevice_id rockchip_gmac_ids[] = {
.data = (ulong)&rk3399_gmac_ops },
{ .compatible = "rockchip,rv1108-gmac",
.data = (ulong)&rv1108_gmac_ops },
+ { .compatible = "rockchip,rv1126-gmac",
+ .data = (ulong)&rv1126_gmac_ops },
{ }
};
--
2.19.1
Re: [PATCH v2 00/11] Add dwc_eth_qos support for rockchip
Hi Patrice, Thanks for your remind, i resend this series base on last v2020.07-rc2. 在 2020/5/12 下午4:17, Patrice CHOTARD 写道: Hi David IN order to test it on STM32, can you rebase this series on last master branch, there was some update already merged that avoid to apply smoothly this series. Thanks Patrice On 5/11/20 9:00 AM, David Wu wrote: Rockchip Socs can support two controllers "snps, dwmac-4.20a" and "snps, dwmac-3.50". In order to support two at gmac-rockchip.c, export public interface functions and struct data, it will be more general for others. Changes in v2: - None - Remove the code is not related (Patrice) - None - Don't change the Rx and Tx clock names. (Patrice, Stephen) - None - None - Add the lost head file. (Patrice) - None - None - None - None David Wu (11): net: dwc_eth_qos: Use dev_ functions calls to get FDT data net: dwc_eth_qos: Add option "snps,reset-gpio" phy-rst gpio for stm32 net: dwc_eth_qos: Move interface() to eqos_ops structure net: dwc_eth_qos: Make clk_rx and clk_tx optional net: dwc_eth_qos: Split eqos_start() to get link speed net: dwc_eth_qos: make eqos_start_clks and eqos_stop_clks optional net: dwc_eth_qos: Export common struct and interface at head file net: gmac_rockchip: Add dwc_eth_qos support net: dwc_eth_qos: Add eqos_rockchip_ops net: dwc_eth_qos: Add EQOS_MAC_MDIO_ADDRESS_CR_100_150 for Rockchip net: gmac_rockchip: Add RV1126 gmac support drivers/net/Kconfig | 2 +- drivers/net/dwc_eth_qos.c | 273 ++-- drivers/net/dwc_eth_qos.h | 89 drivers/net/gmac_rockchip.c | 188 + 4 files changed, 390 insertions(+), 162 deletions(-) create mode 100644 drivers/net/dwc_eth_qos.h
Re: [PATCH] net: use the same alias stem for ethernet as linux
Hi Michael,
Thank you for your patch, good complement.
在 2021/2/25 下午11:51, Michael Walle 写道:
Linux uses the prefix "ethernet" whereas u-boot uses "eth". This is from
the linux tree:
$ grep "eth[0-9].*=.*&" arch/**/*dts{,i}|wc -l
0
$ grep "ethernet[0-9].*=.*&" arch/**/*dts{,i}|wc -l
633
In u-boot device trees both prefixes are used. Until recently the only
user of the ethernet alias was the sandbox test device tree. This
changed with commit fc054d563bfb ("net: Introduce DSA class for Ethernet
switches"). There, the MAC addresses are inherited based on the devices
sequence IDs which is in turn given by the device tree.
Before there are more users in u-boot and both worlds will differ even
more, rename the alias prefix to "ethernet" to match the linux ones.
Also adapt the test cases and rename any old aliases in the u-boot
device trees.
Cc: David Wu
Signed-off-by: Michael Walle
---
Vladimir, I didn't do another patch to rename any ethernet aliases to
"eth". Though kontron boards contain "ethernetN" aliases, all in tree
variants don't make use of it. So there is nothing to be fixed.
arch/arm/dts/fsl-ls1028a-rdb.dts | 12 ++--
arch/sandbox/dts/test.dts| 10 +-
net/eth-uclass.c | 4 ++--
test/dm/ofnode.c | 2 +-
test/dm/test-fdt.c | 2 +-
5 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts
index 3432fca352..82a8c0a0cd 100644
--- a/arch/arm/dts/fsl-ls1028a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1028a-rdb.dts
@@ -15,12 +15,12 @@
compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
aliases {
spi0 = &fspi;
- eth0 = &enetc0;
- eth1 = &enetc2;
- eth2 = &mscc_felix_port0;
- eth3 = &mscc_felix_port1;
- eth4 = &mscc_felix_port2;
- eth5 = &mscc_felix_port3;
+ ethernet0 = &enetc0;
+ ethernet1 = &enetc2;
+ ethernet2 = &mscc_felix_port0;
+ ethernet3 = &mscc_felix_port1;
+ ethernet4 = &mscc_felix_port2;
+ ethernet5 = &mscc_felix_port3;
};
};
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 3ef3ba0b17..7a5d4aa71d 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -14,11 +14,11 @@
aliases {
console = &uart0;
- eth0 = "/eth@10002000";
- eth2 = &swp_0;
- eth3 = ð_3;
- eth4 = &dsa_eth0;
- eth5 = ð_5;
+ ethernet0 = "/eth@10002000";
+ ethernet2 = &swp_0;
+ ethernet3 = ð_3;
+ ethernet4 = &dsa_eth0;
+ ethernet5 = ð_5;
gpio1 = &gpio_a;
gpio2 = &gpio_b;
gpio3 = &gpio_c;
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 0b4260dc5b..5146bd 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -605,8 +605,8 @@ static int eth_pre_remove(struct udevice *dev)
return 0;
}
-UCLASS_DRIVER(eth) = {
- .name = "eth",
+UCLASS_DRIVER(ethernet) = {
+ .name = "ethernet",
.id = UCLASS_ETH,
.post_bind = eth_post_bind,
.pre_unbind = eth_pre_unbind,
diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c
index c539134296..3b708b63eb 100644
--- a/test/dm/ofnode.c
+++ b/test/dm/ofnode.c
@@ -213,7 +213,7 @@ static int dm_test_ofnode_read_aliases(struct
unit_test_state *uts)
ofnode node;
int size;
- node = ofnode_get_aliases_node("eth3");
+ node = ofnode_get_aliases_node("ethernet3");
ut_assert(ofnode_valid(node));
ut_asserteq_str("sbe5", ofnode_get_name(node));
diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index 6e83aeecd9..98972665f2 100644
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c
@@ -183,7 +183,7 @@ static int dm_test_alias_highest_id(struct unit_test_state
*uts)
{
int ret;
- ret = dev_read_alias_highest_id("eth");
+ ret = dev_read_alias_highest_id("ethernet");
ut_asserteq(5, ret);
ret = dev_read_alias_highest_id("gpio");
Re: [RESEND PATCH v2 02/11] net: dwc_eth_qos: Add option "snps,reset-gpio" phy-rst gpio for stm32
Hi Patrick,
Yes, this is the case, it should be add at PHY node, and I also used the
original writing "snps,reset*" at MAC node. Anyway, I will try to put
the reset gpio in the PHY node.
在 2020/5/13 下午8:55, Patrick DELAUNAY 写道:
Hi David
From: David Wu
Sent: mardi 12 mai 2020 11:56
It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
gpio is used, adding this option makes reset function more general.
Signed-off-by: David Wu
---
Changes in v2:
- Remove the code is not related (Patrice)
drivers/net/dwc_eth_qos.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index
66a02aa80b..92dab678c7 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -314,6 +314,7 @@ struct eqos_priv {
struct eqos_tegra186_regs *tegra186_regs;
struct reset_ctl reset_ctl;
struct gpio_desc phy_reset_gpio;
+ u32 reset_delays[3];
struct clk clk_master_bus;
struct clk clk_rx;
struct clk clk_ptp_ref;
@@ -739,6 +740,15 @@ static int eqos_start_resets_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
+ ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
+ if (ret < 0) {
+ pr_err("dm_gpio_set_value(phy_reset, deassert) failed:
%d",
+ ret);
+ return ret;
+ }
+
+ udelay(eqos->reset_delays[0]);
+
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
if (ret < 0) {
pr_err("dm_gpio_set_value(phy_reset, assert) failed:
%d",
@@ -746,7 +756,7 @@ static int eqos_start_resets_stm32(struct udevice *dev)
return ret;
}
- udelay(2);
+ udelay(eqos->reset_delays[1]);
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
if (ret < 0) {
@@ -754,6 +764,8 @@ static int eqos_start_resets_stm32(struct udevice *dev)
ret);
return ret;
}
+
+ udelay(eqos->reset_delays[2]);
}
debug("%s: OK\n", __func__);
@@ -1864,11 +1876,29 @@ static int eqos_probe_resources_stm32(struct
udevice *dev)
if (ret)
pr_warn("gpio_request_by_name(phy reset) not provided
%d",
ret);
+ else
+ eqos->reset_delays[1] = 2;
eqos->phyaddr = ofnode_read_u32_default(phandle_args.node,
"reg", -1);
}
+ if (!dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
+ int reset_flags = GPIOD_IS_OUT;
+
+ if (dev_read_bool(dev, "snps,reset-active-low"))
+ reset_flags |= GPIOD_ACTIVE_LOW;
+
+ ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
+ &eqos->phy_reset_gpio, reset_flags);
+ if (ret == 0)
+ ret = dev_read_u32_array(dev, "snps,reset-delays-us",
+eqos->reset_delays, 3);
+ else
+ pr_warn("gpio_request_by_name(snps,reset-gpio) failed:
%d",
+ ret);
+ }
+
debug("%s: OK\n", __func__);
return 0;
--
2.19.1
This obsolete binding isn't expected to be supported in stm32 glue for dwmac
(and it tis the purpose of eqos_stm32_config)
Reference in linux binding
./Documentation/devicetree/bindings/net/stm32-dwmac.txt (the glue)
./Documentation/devicetree/bindings/net/snps,dwmac.yaml
snps,reset-gpio:
deprecated: true
snps,reset-active-low:
deprecated: true
snps,reset-delays-us:
deprecated: true
I expected that gpio reset in future device tree should be managed by only by
PHY generic binding
(upstream in progress on Linux side for STM32MP15x), as described in:
Documentation/devicetree/bindings/net/ethernet-phy.yaml
reset-gpios:
maxItems: 1
description:
The GPIO phandle and specifier for the PHY reset signal.
reset-assert-us:
description:
Delay after the reset was asserted in microseconds. If this
property is missing the delay will be skipped.
reset-deassert-us:
description:
Delay after the reset was deasserted in microseconds. If
this property is missing the delay will be skipped.
See alsoU-Boot: doc/device-tree-bindings/net/phy.txt
Something as
&mac {
status = "okay";
Re: [RESEND PATCH v2 02/11] net: dwc_eth_qos: Add option "snps, reset-gpio" phy-rst gpio for stm32
Hi Tom, 在 2020/6/12 下午10:48, Tom Rini 写道: On Tue, May 12, 2020 at 05:56:01PM +0800, David Wu wrote: It can be seen that most of the Socs using STM mac, "snps,reset-gpio" gpio is used, adding this option makes reset function more general. Signed-off-by: David Wu Reviewed-by: Patrice Chotard --- Changes in v2: - Remove the code is not related (Patrice) Please note that based on Patrick's feedback I am expecting a v3 of this patch or further answers about the obsolete binding being used. Thanks! I think I will submit v3 after the following two patches, it looks like I need to add a rockchip config. [1] net: dwc_eth_qos: update the compatible supported for STM32 http://patchwork.ozlabs.org/project/uboot/patch/20200514130023.15030-1-patrick.delau...@st.com/ [2] net: dwc_eth_qos: add Kconfig option to select supported configuration http://patchwork.ozlabs.org/project/uboot/list/?series=181931
Re: [PATCH] rockchip: i2c: fix switch to new implementation for rk3188
Hi Alexander,
Thank you for your patch, the grf header file is missing for rk3066, the
GRF_SOC_CON1 offset of 3066 is 0x154, the corresponding bit of i2c0~i2c4
is also bit11 ~ bit15.
There is currently no support for rk3066 at mainline, rk3066 is not
handled here, I think it’s okay, so,
Reviewed-by: David Wu
在 2020/6/27 下午11:03, Alexander Kochetkov 写道:
To make clear, there is kernel driver i2c-rk3x.c.
For rk3066 it write bits in the GRF word at offset 0x154. See [1] and [2].
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/i2c/busses/i2c-rk3x.c#n1236
[2]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/i2c/busses/i2c-rk3x.c#n1137
In u-boot there is include file cru_rk3036.h [3]. If this include file valid
for rk3066, than offset 0x154 correspond
to soc_con3 register. But all documentation I found for 30xx SoC clarify that
I2C switch bits located in the
soc_con1 registers.
So I don’t know correct location for I2C switch bits.
[3]
https://github.com/u-boot/u-boot/blob/master/arch/arm/include/asm/arch-rockchip/cru_rk3036.h
27 июня 2020 г., в 17:17, Kever Yang написал(а):
+David,
Hi David,
Could you help to commend on this?
Hi Alex,
Thanks for your patch.
On 2020/6/22 下午9:06, Alexander Kochetkov wrote:
The commit e7ae4cf27a6d 'pinctrl: rockchip: Add common rockchip
pinctrl driver' dropped rk3188_pinctrl_request operation, that
did switching to new implementation.
This commit implement switching to new implementation using
writing bits to GRF.
I don't have rk3060
rk3066
board to test, so switching implemented
as a stub returning -ENOSYS.
Signed-off-by: Alexander Kochetkov
---
drivers/i2c/rk_i2c.c | 42 +++---
1 file changed, 31 insertions(+), 11 deletions(-)
diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c
index 32b2ee8578..ad3c66843b 100644
--- a/drivers/i2c/rk_i2c.c
+++ b/drivers/i2c/rk_i2c.c
@@ -15,6 +15,8 @@
#include
#include
#include
+#include
+#include
#include
#include
@@ -41,6 +43,7 @@ enum {
*/
struct rk_i2c_soc_data {
int controller_type;
+ int (*switch_to_new_type)(int bus_nr);
};
static inline void rk_i2c_get_div(int div, int *divh, int *divl)
@@ -388,11 +391,33 @@ static int rockchip_i2c_ofdata_to_platdata(struct udevice
*bus)
return 0;
}
+static int rockchip_i2c_switch_to_new_type_rk3066(int bus_nr)
+{
+ return -ENOSYS;
+}
+
+static int rockchip_i2c_switch_to_new_type_rk3188(int bus_nr)
+{
+ struct rk3188_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ if (grf == NULL)
+ return -ENOSYS;
+
+ if (bus_nr < 0 || bus_nr > (RKI2C4_SEL_SHIFT - RKI2C0_SEL_SHIFT))
+ return -EINVAL;
+
+ /* enable new i2c controller */
+ rk_clrsetreg(&grf->soc_con1,
+1 << (RKI2C0_SEL_SHIFT + bus_nr),
+1 << (RKI2C0_SEL_SHIFT + bus_nr));
+
+ return 0;
+}
+
static int rockchip_i2c_probe(struct udevice *bus)
{
struct rk_i2c *priv = dev_get_priv(bus);
struct rk_i2c_soc_data *soc_data;
- struct udevice *pinctrl;
int bus_nr;
int ret;
@@ -408,17 +433,10 @@ static int rockchip_i2c_probe(struct udevice *bus)
return ret;
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- debug("%s: Cannot find pinctrl device\n", __func__);
- return ret;
- }
-
- /* pinctrl will switch I2C to new type */
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_I2C0 + bus_nr);
- if (ret) {
+ ret = soc_data->switch_to_new_type(bus_nr);
+ if (ret < 0) {
debug("%s: Failed to switch I2C to new type %s: %d\n",
- __func__, bus->name, ret);
+__func__, bus->name, ret);
return ret;
}
}
@@ -433,10 +451,12 @@ static const struct dm_i2c_ops rockchip_i2c_ops = {
static const struct rk_i2c_soc_data rk3066_soc_data = {
.controller_type = RK_I2C_LEGACY,
+ .switch_to_new_type = rockchip_i2c_switch_to_new_type_rk3066,
};
static const struct rk_i2c_soc_data rk3188_soc_data = {
.controller_type = RK_I2C_LEGACY,
+ .switch_to_new_type = rockchip_i2c_switch_to_new_type_rk3188,
};
static const struct rk_i2c_soc_data rk3228_soc_data = {
Re: [PATCH 1/9] net: gmac_rockchip: Fix misuse of GENMASK macro
Hi Pierre-Clément,
Thanks for your correction, there was wrong mask here.
Reviewed-by: David Wu
在 2022/4/6 23:08, Kever Yang 写道:
Add David,
Hi David,
Could you help to check this patch?
Thanks,
- Kever
On 2022/3/16 23:39, Pierre-Clément Tosi wrote:
Swap the arguments as that seems to have been the author's intention.
Note: This fix wasn't tested on hardware and will result in more bits
being set by the underlying writel() in rk_clrsetreg(), which
might bring unexpected behavioural changes.
Fixes: b07911840025 ("net: gmac_rockchip: add support for px30")
Signed-off-by: Pierre-Clément Tosi
Cc: Joe Hershberger
Cc: Heiko Stuebner
Cc: Kever Yang
Cc: Tom Rini
---
drivers/net/gmac_rockchip.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 04008d2b19..0ecbcdf641 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -350,7 +350,7 @@ static void px30_gmac_set_to_rmii(struct
gmac_rockchip_plat *pdata)
struct px30_grf *grf;
enum {
PX30_GMAC_PHY_INTF_SEL_SHIFT = 4,
- PX30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6),
+ PX30_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
PX30_GMAC_PHY_INTF_SEL_RMII = BIT(6),
};
[U-Boot] [PATCH 0/7] Add uCdimm and Mercury's EP2500 support
Hi list, This is my first time to submit a patch to this list. I hope it is in the correct format. All these patches are based on the Mar. 15's git tree plus 16 patches from TsiChung. David Wu (7): Colfdfire MCF5282: enable icache if CONFIG_SYS_ENABLE_ICACHE is defined AT49BV322A Flash: the erase regions are in the wrong order. added Mercury EP2500 board support It uses the mcf5282 processor with real time clock and EEPROM. Adding uC5272 dimm module support adding uC5274/5275 dimm module support adding uC5282 dimm module support adding credit for uC5272, uC5274/5275 and uC5282 CREDITS |2 +- Makefile | 114 ++ board/Arcturus/uC5272/Makefile| 44 + board/Arcturus/uC5272/config.mk |1 + board/Arcturus/uC5272/u-boot.lds | 142 +++ board/Arcturus/uC5272/uC5272.c| 57 + board/Arcturus/uC5275/Makefile| 44 + board/Arcturus/uC5275/config.mk | 23 + board/Arcturus/uC5275/u-boot.lds | 139 +++ board/Arcturus/uC5275/uC5275.c| 118 +++ board/Arcturus/uC5282/Makefile| 44 + board/Arcturus/uC5282/cfm_flash.c | 201 board/Arcturus/uC5282/cfm_flash.h | 42 + board/Arcturus/uC5282/config.mk | 23 + board/Arcturus/uC5282/flash.c | 2087 + board/Arcturus/uC5282/u-boot.lds | 140 +++ board/Arcturus/uC5282/uC5282.c| 98 ++ board/Mercury/ep2500/Makefile | 44 + board/Mercury/ep2500/config.mk| 23 + board/Mercury/ep2500/ep2500.c | 191 board/Mercury/ep2500/u-boot.lds | 140 +++ cpu/mcf52x2/cpu_init.c|6 +- drivers/mtd/cfi_flash.c |4 +- include/configs/EP2500.h | 297 ++ include/configs/uC5272.h | 354 +++ include/configs/uC5275.h | 263 + include/configs/uC5282.h | 299 ++ 27 files changed, 4936 insertions(+), 4 deletions(-) create mode 100644 board/Arcturus/uC5272/Makefile create mode 100644 board/Arcturus/uC5272/config.mk create mode 100644 board/Arcturus/uC5272/u-boot.lds create mode 100644 board/Arcturus/uC5272/uC5272.c create mode 100644 board/Arcturus/uC5275/Makefile create mode 100644 board/Arcturus/uC5275/config.mk create mode 100644 board/Arcturus/uC5275/u-boot.lds create mode 100644 board/Arcturus/uC5275/uC5275.c create mode 100644 board/Arcturus/uC5282/Makefile create mode 100644 board/Arcturus/uC5282/cfm_flash.c create mode 100644 board/Arcturus/uC5282/cfm_flash.h create mode 100644 board/Arcturus/uC5282/config.mk create mode 100644 board/Arcturus/uC5282/flash.c create mode 100644 board/Arcturus/uC5282/u-boot.lds create mode 100644 board/Arcturus/uC5282/uC5282.c create mode 100644 board/Mercury/ep2500/Makefile create mode 100644 board/Mercury/ep2500/config.mk create mode 100644 board/Mercury/ep2500/ep2500.c create mode 100644 board/Mercury/ep2500/u-boot.lds create mode 100644 include/configs/EP2500.h create mode 100644 include/configs/uC5272.h create mode 100644 include/configs/uC5275.h create mode 100644 include/configs/uC5282.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 7/7] adding credit for uC5272, uC5274/5275 and uC5282
Signed-off-by: David Wu --- CREDITS |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/CREDITS b/CREDITS index 043ba6e..144fc27 100644 --- a/CREDITS +++ b/CREDITS @@ -513,7 +513,7 @@ D: Port to MPC555/556 microcontrollers and support for cmi board N: David Wu E: supp...@arcturusnetworks.com -D: Mercury Security EP2500 +D: Mercury Security EP2500; Arcturus Networks Inc. uC5272, uC5274/5275 and uC5282 W: http://www.arcturusnetworks.com N: Ming-Len Wu -- 1.5.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/7] Colfdfire MCF5282: enable icache if CONFIG_SYS_ENABLE_ICACHE is defined
Signed-off-by: David Wu --- cpu/mcf52x2/cpu_init.c |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 170bbfc..36f62cc 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -621,8 +621,10 @@ void cpu_init_f(void) #endif/* CONFIG_MONITOR_IS_IN_RAM */ - /* defer enabling cache until boot (see do_go) */ - /* icache_enable(); */ +#if defined(CONFIG_SYS_ENABLE_ICACHE) + /* enable instruction cache */ + icache_enable(); +#endif } /* -- 1.5.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/7] AT49BV322A Flash: the erase regions are in the wrong order.
The device id for this Flash is 0xc8. Signed-off-by: David Wu --- drivers/mtd/cfi_flash.c |4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index fdba297..af86f99 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1690,8 +1690,10 @@ static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry) /* AT49BV6416(T) list the erase regions in the wrong order. * However, the device ID is identical with the non-broken * AT49BV642D they differ in the high byte. +* AT49BV322A is also in the wrong order. */ - if (info->device_id == 0xd6 || info->device_id == 0xd2) + if (info->device_id == 0xd6 || info->device_id == 0xd2 || + info->device_id == 0xc8) reverse_geometry = !reverse_geometry; if (reverse_geometry) -- 1.5.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/7] Adding uC5272 dimm module support
Signed-off-by: David Wu --- Makefile | 46 + board/Arcturus/uC5272/Makefile | 44 + board/Arcturus/uC5272/config.mk |1 + board/Arcturus/uC5272/u-boot.lds | 142 +++ board/Arcturus/uC5272/uC5272.c | 57 ++ include/configs/uC5272.h | 354 ++ 6 files changed, 644 insertions(+), 0 deletions(-) create mode 100644 board/Arcturus/uC5272/Makefile create mode 100644 board/Arcturus/uC5272/config.mk create mode 100644 board/Arcturus/uC5272/u-boot.lds create mode 100644 board/Arcturus/uC5272/uC5272.c create mode 100644 include/configs/uC5272.h diff --git a/Makefile b/Makefile index 1b61049..c9215d0 100644 --- a/Makefile +++ b/Makefile @@ -,6 +,52 @@ M5485HFE_config :unconfig TASREG_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 tasreg esd +uC5272-4E16U48_config \ +uC5272-8EE16U66_config \ +uC5272-8E32U66_config \ +uC5272-4EE16U48_config \ +uC5272-4E8U48_config \ +uC5272-4EE8U48_config \ +uC5272-4E8U66_config \ +uC5272-4EE8U66_config \ +uC5272-4E16U66_config \ +uC5272-4EE16U66_config \ +uC5272-4EE32U66_config \ +uC5272-8EE32U66_config:unconfig + @mkdir -p $(obj)include + @if [ "$(findstring U48,$@)" ] ; then \ + echo "#define SYSCLK_48MHZ " >>$(obj)include/config.h ;\ + fi ; + @if [ "$(findstring U66,$@)" ] ; then \ + echo "#define SYSCLK_66MHZ " >>$(obj)include/config.h ;\ + fi ; + @if [ "$(findstring EE,$@)" ] ; then \ + echo "#define HAS_ETH1 " >>$(obj)include/config.h ;\ + fi ; + @if [ "$(findstring 4E,$@)" ] ; then \ + echo "#define __4MFlash__ " >>$(obj)include/config.h ;\ + echo "#define CONFIG_SYS_FLASH_SIZE 0x0040" >>$(obj)include/config.h ;\ + echo "TEXT_BASE = 0x10c0" > board/Arcturus/uC5272/config.mk ;\ + fi ; + @if [ "$(findstring 8E,$@)" ] ; then \ + echo "#define __8MFlash__ " >>$(obj)include/config.h ;\ + echo "#define CONFIG_SYS_FLASH_SIZE 0x0080" >>$(obj)include/config.h ;\ + echo "TEXT_BASE = 0x4000" > board/Arcturus/uC5272/config.mk ;\ + fi ; + @if [ "$(findstring E8,$@)" ] ; then \ + echo "#define __8MRam__ " >>$(obj)include/config.h ;\ + echo "#define CONFIG_SYS_SDRAM_SIZE 8" >>$(obj)include/config.h ;\ + fi ; + @if [ "$(findstring E16,$@)" ] ; then \ + echo "#define __16MRam__ " >>$(obj)include/config.h ;\ + echo "#define CONFIG_SYS_SDRAM_SIZE 16" >>$(obj)include/config.h ;\ + fi ; + @if [ "$(findstring E32,$@)" ] ; then \ + echo "#define __32MRam__ " >>$(obj)include/config.h ;\ + echo "#define CONFIG_SYS_SDRAM_SIZE 32" >>$(obj)include/config.h ;\ + fi ; + @$(MKCONFIG) -a uC5272 m68k mcf52x2 uC5272 Arcturus + # ## MPC83xx Systems # diff --git a/board/Arcturus/uC5272/Makefile b/board/Arcturus/uC5272/Makefile new file mode 100644 index 000..424ab1c --- /dev/null +++ b/board/Arcturus/uC5272/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +# + +# defines $(obj).depend target +include $(SRCTREE)
[U-Boot] [PATCH 5/7] adding uC5274/5275 dimm module support
Signed-off-by: David Wu --- Makefile | 21 +++ board/Arcturus/uC5275/Makefile | 44 +++ board/Arcturus/uC5275/config.mk | 23 board/Arcturus/uC5275/u-boot.lds | 139 board/Arcturus/uC5275/uC5275.c | 118 + include/configs/uC5275.h | 263 ++ 6 files changed, 608 insertions(+), 0 deletions(-) create mode 100644 board/Arcturus/uC5275/Makefile create mode 100644 board/Arcturus/uC5275/config.mk create mode 100644 board/Arcturus/uC5275/u-boot.lds create mode 100644 board/Arcturus/uC5275/uC5275.c create mode 100644 include/configs/uC5275.h diff --git a/Makefile b/Makefile index c9215d0..6dad806 100644 --- a/Makefile +++ b/Makefile @@ -2268,6 +2268,27 @@ uC5272-8EE32U66_config: unconfig fi ; @$(MKCONFIG) -a uC5272 m68k mcf52x2 uC5272 Arcturus +uC5274-16E322T150_config \ +uC5275-16EE32U150_config \ +uC5275-16EE32M150_config: unconfig + @mkdir -p $(obj)include + @echo "#define PRODUCTION_STRING " \"$(@:_config=)\" >>$(obj)include/config.h + @if [ "$(findstring 5274,$@)" ] ; then \ + echo "#define CONFIG_M5274 " >>$(obj)include/config.h ;\ + fi ; + @if [ "$(findstring EE,$@)" ] ; then \ + echo "#define CONFIG_HAS_ETH1 " >>$(obj)include/config.h ;\ + fi ; + @if [ "$(findstring 16E,$@)" ] ; then \ + echo "#define __16MFlash__ " >>$(obj)include/config.h ;\ + echo "#define CONFIG_SYS_FLASH_SIZE 0x0100" >>$(obj)include/config.h ;\ + fi ; + @if [ "$(findstring E32,$@)" ] ; then \ + echo "#define __32MRam__ " >>$(obj)include/config.h ;\ + echo "#define CONFIG_SYS_SDRAM_SIZE 32" >>$(obj)include/config.h ;\ + fi ; + @$(MKCONFIG) -a uC5275 m68k mcf52x2 uC5275 Arcturus + # ## MPC83xx Systems # diff --git a/board/Arcturus/uC5275/Makefile b/board/Arcturus/uC5275/Makefile new file mode 100644 index 000..981763d --- /dev/null +++ b/board/Arcturus/uC5275/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/Arcturus/uC5275/config.mk b/board/Arcturus/uC5275/config.mk new file mode 100644 index 000..4605e0e --- /dev/null +++ b/board/Arcturus/uC5275/config.mk @@ -0,0 +1,23 @@ +# +# (c) Copyright 2010 Arcturus Networks Inc. +# by David Wu +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +TEXT_BASE = 0xf000 diff --git a/board/Arcturus/uC5275/u-boot.lds b/board/A
[U-Boot] [PATCH 3/7] added Mercury EP2500 board support It uses the mcf5282 processor with real time clock and EEPROM.
Signed-off-by: David Wu
---
board/Mercury/ep2500/Makefile | 44 ++
board/Mercury/ep2500/config.mk | 23 +++
board/Mercury/ep2500/ep2500.c | 191 +
board/Mercury/ep2500/u-boot.lds | 140 ++
include/configs/EP2500.h| 297
+++
5 files changed, 695 insertions(+), 0 deletions(-)
create mode 100644 board/Mercury/ep2500/Makefile
create mode 100644 board/Mercury/ep2500/config.mk
create mode 100644 board/Mercury/ep2500/ep2500.c
create mode 100644 board/Mercury/ep2500/u-boot.lds
create mode 100644 include/configs/EP2500.h
diff --git a/board/Mercury/ep2500/Makefile b/board/Mercury/ep2500/Makefile
new file mode 100644
index 000..424ab1c
--- /dev/null
+++ b/board/Mercury/ep2500/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/Mercury/ep2500/config.mk
b/board/Mercury/ep2500/config.mk
new file mode 100644
index 000..5639dbb
--- /dev/null
+++ b/board/Mercury/ep2500/config.mk
@@ -0,0 +1,23 @@
+#
+# (c) Copyright 2009 Arcturus Networks Inc.
+# by David Wu
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+TEXT_BASE = 0xFF00
diff --git a/board/Mercury/ep2500/ep2500.c b/board/Mercury/ep2500/ep2500.c
new file mode 100644
index 000..03be4cf
--- /dev/null
+++ b/board/Mercury/ep2500/ep2500.c
@@ -0,0 +1,191 @@
+/*
+ * (c) Copyright 2009 Arcturus Networks Inc.
+ * by David Wu
+ *
+ * Based in part on: board/freescale/m5282evb/m5282evb.c
+ * (c) Copyright 2000-2003 Wolfgang Denk,
+ * DENX Software Engineering, w...@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: Mercury EP2500 Board\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ u32 dramsize, i, j, dramclk;
+
+ dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
+
+ if (!(MCFSDRAMC_DACR0 &
Re: [U-Boot] [PATCH 2/7] AT49BV322A Flash: the erase regions are in the wrong order.
Hi Stefan, I am new here and I am not quite clear about how to split this patch. Any suggestion? Regards, David On Thu, 08 Apr 2010 05:35:35 -0400, Stefan Roese wrote: > On Thursday 08 April 2010 02:00:23 David Wu wrote: >> The device id for this Flash is 0xc8. >> >> Signed-off-by: David Wu >> --- >> drivers/mtd/cfi_flash.c |4 +++- >> 1 files changed, 3 insertions(+), 1 deletions(-) >> >> diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c >> index fdba297..af86f99 100644 >> --- a/drivers/mtd/cfi_flash.c >> +++ b/drivers/mtd/cfi_flash.c >> @@ -1690,8 +1690,10 @@ static void flash_fixup_atmel(flash_info_t *info, >> struct cfi_qry *qry) >> /* AT49BV6416(T) list the erase regions in the wrong order. >> * However, the device ID is identical with the non-broken >> * AT49BV642D they differ in the high byte. >> + * AT49BV322A is also in the wrong order. >> */ >> -if (info->device_id == 0xd6 || info->device_id == 0xd2) >> +if (info->device_id == 0xd6 || info->device_id == 0xd2 || >> +info->device_id == 0xc8) >> reverse_geometry = !reverse_geometry; >> >> if (reverse_geometry) > > Could you please split this patch from the patch series. I'll push it > via the > CFI git repository then. Thanks. > > Cheers, > Stefan > > -- > DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de > > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/7] AT49BV322A Flash: the erase regions are in the wrong order.
Hi Stefan, On Thu, 08 Apr 2010 11:21:45 -0400, Stefan Roese wrote: > Hi David, > > On Thursday 08 April 2010 17:16:26 David Wu wrote: >> I am new here and I am not quite clear about how to split this patch. >> Any suggestion? > > I didn't mean that you should split this patch, but that you should > split it > from your *patchset* of 7 parts. Resulting in a patchset with 6 parts > ([PATCH > 1/6] ...) and one single patch. This way it's easier for me to pick up > such a > CFI related patch. OK. Will do it. A question: Do I have to do this way or just for convenience ? My concerns are 1 more traffic to the list 2 git will complain if applying the patch in the wrong order. Regards, David > > Thanks. > > Cheers, > Stefan > > -- > DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de > > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/7] AT49BV322A Flash: the erase regions are in the wrong order.
Hi Stefan, I think those patches if I resubmit are same as before except the subjects differ. Anyway If no one complains then I will send. Regards, David On Fri, 09 Apr 2010 02:46:17 -0400, Stefan Roese wrote: > Hi David, > > On Thursday 08 April 2010 17:47:46 David Wu wrote: >> > I didn't mean that you should split this patch, but that you should >> > split it >> > from your *patchset* of 7 parts. Resulting in a patchset with 6 parts >> > ([PATCH >> > 1/6] ...) and one single patch. This way it's easier for me to pick up >> > such a >> > CFI related patch. >> >> OK. Will do it. >> A question: Do I have to do this way or just for convenience ? >> My concerns are >> 1 more traffic to the list > > Why would there be more traffic? Previously you did send 7 patches, > numbered > 1/7 ... 7/7. Now you would send 7 patches 1/6 ... 6/6 plus the CFI patch. >> 2 git will complain if applying the patch in the wrong order. > > The CFI patch is unrelated to the other patches. At least it wont > generate any > compilation breakages/problems, if this patch is applied before or after > your > other Coldfire patches. > Cheers, > Stefan > > -- > DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de > > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/6] Colfdfire MCF5282: enable icache if CONFIG_SYS_ENABLE_ICACHE is defined
Signed-off-by: David Wu --- cpu/mcf52x2/cpu_init.c |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 170bbfc..36f62cc 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -621,8 +621,10 @@ void cpu_init_f(void) #endif /* CONFIG_MONITOR_IS_IN_RAM */ - /* defer enabling cache until boot (see do_go) */ - /* icache_enable(); */ +#if defined(CONFIG_SYS_ENABLE_ICACHE) + /* enable instruction cache */ + icache_enable(); +#endif } /* -- 1.5.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/6] added Mercury EP2500 board support It uses the mcf5282 processor with real time clock and EEPROM.
Signed-off-by: David Wu
---
board/Mercury/ep2500/Makefile | 44 ++
board/Mercury/ep2500/config.mk | 23 +++
board/Mercury/ep2500/ep2500.c | 191 +
board/Mercury/ep2500/u-boot.lds | 140 ++
include/configs/EP2500.h| 297
+++
5 files changed, 695 insertions(+), 0 deletions(-)
create mode 100644 board/Mercury/ep2500/Makefile
create mode 100644 board/Mercury/ep2500/config.mk
create mode 100644 board/Mercury/ep2500/ep2500.c
create mode 100644 board/Mercury/ep2500/u-boot.lds
create mode 100644 include/configs/EP2500.h
diff --git a/board/Mercury/ep2500/Makefile b/board/Mercury/ep2500/Makefile
new file mode 100644
index 000..424ab1c
--- /dev/null
+++ b/board/Mercury/ep2500/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/Mercury/ep2500/config.mk
b/board/Mercury/ep2500/config.mk
new file mode 100644
index 000..5639dbb
--- /dev/null
+++ b/board/Mercury/ep2500/config.mk
@@ -0,0 +1,23 @@
+#
+# (c) Copyright 2009 Arcturus Networks Inc.
+# by David Wu
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+TEXT_BASE = 0xFF00
diff --git a/board/Mercury/ep2500/ep2500.c b/board/Mercury/ep2500/ep2500.c
new file mode 100644
index 000..03be4cf
--- /dev/null
+++ b/board/Mercury/ep2500/ep2500.c
@@ -0,0 +1,191 @@
+/*
+ * (c) Copyright 2009 Arcturus Networks Inc.
+ * by David Wu
+ *
+ * Based in part on: board/freescale/m5282evb/m5282evb.c
+ * (c) Copyright 2000-2003 Wolfgang Denk,
+ * DENX Software Engineering, w...@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: Mercury EP2500 Board\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ u32 dramsize, i, j, dramclk;
+
+ dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
+
+ if (!(MCFSDRAMC_DACR0 &
[U-Boot] [PATCH] AT49BV322A Flash: the erase regions are in the wrong order.
The device id for this Flash is 0xc8. Signed-off-by: David Wu --- drivers/mtd/cfi_flash.c |4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index fdba297..af86f99 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1690,8 +1690,10 @@ static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry) /* AT49BV6416(T) list the erase regions in the wrong order. * However, the device ID is identical with the non-broken * AT49BV642D they differ in the high byte. +* AT49BV322A is also in the wrong order. */ - if (info->device_id == 0xd6 || info->device_id == 0xd2) + if (info->device_id == 0xd6 || info->device_id == 0xd2 || + info->device_id == 0xc8) reverse_geometry = !reverse_geometry; if (reverse_geometry) -- 1.5.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/6] Adding uC5272 dimm module support
Signed-off-by: David Wu --- Makefile | 46 + board/Arcturus/uC5272/Makefile | 44 + board/Arcturus/uC5272/config.mk |1 + board/Arcturus/uC5272/u-boot.lds | 142 +++ board/Arcturus/uC5272/uC5272.c | 57 ++ include/configs/uC5272.h | 354 ++ 6 files changed, 644 insertions(+), 0 deletions(-) create mode 100644 board/Arcturus/uC5272/Makefile create mode 100644 board/Arcturus/uC5272/config.mk create mode 100644 board/Arcturus/uC5272/u-boot.lds create mode 100644 board/Arcturus/uC5272/uC5272.c create mode 100644 include/configs/uC5272.h diff --git a/Makefile b/Makefile index 1b61049..c9215d0 100644 --- a/Makefile +++ b/Makefile @@ -,6 +,52 @@ M5485HFE_config :unconfig TASREG_config : unconfig @$(MKCONFIG) $(@:_config=) m68k mcf52x2 tasreg esd +uC5272-4E16U48_config \ +uC5272-8EE16U66_config \ +uC5272-8E32U66_config \ +uC5272-4EE16U48_config \ +uC5272-4E8U48_config \ +uC5272-4EE8U48_config \ +uC5272-4E8U66_config \ +uC5272-4EE8U66_config \ +uC5272-4E16U66_config \ +uC5272-4EE16U66_config \ +uC5272-4EE32U66_config \ +uC5272-8EE32U66_config:unconfig + @mkdir -p $(obj)include + @if [ "$(findstring U48,$@)" ] ; then \ + echo "#define SYSCLK_48MHZ " >>$(obj)include/config.h ;\ + fi ; + @if [ "$(findstring U66,$@)" ] ; then \ + echo "#define SYSCLK_66MHZ " >>$(obj)include/config.h ;\ + fi ; + @if [ "$(findstring EE,$@)" ] ; then \ + echo "#define HAS_ETH1 " >>$(obj)include/config.h ;\ + fi ; + @if [ "$(findstring 4E,$@)" ] ; then \ + echo "#define __4MFlash__ " >>$(obj)include/config.h ;\ + echo "#define CONFIG_SYS_FLASH_SIZE 0x0040" >> $(obj)include/config.h ;\ + echo "TEXT_BASE = 0x10c0" > board/Arcturus/uC5272/config.mk ;\ + fi ; + @if [ "$(findstring 8E,$@)" ] ; then \ + echo "#define __8MFlash__ " >>$(obj)include/config.h ;\ + echo "#define CONFIG_SYS_FLASH_SIZE 0x0080" >> $(obj)include/config.h ;\ + echo "TEXT_BASE = 0x4000" > board/Arcturus/uC5272/config.mk ;\ + fi ; + @if [ "$(findstring E8,$@)" ] ; then \ + echo "#define __8MRam__ " >>$(obj)include/config.h ;\ + echo "#define CONFIG_SYS_SDRAM_SIZE 8" >>$(obj)include/config.h ;\ + fi ; + @if [ "$(findstring E16,$@)" ] ; then \ + echo "#define __16MRam__ " >>$(obj)include/config.h ;\ + echo "#define CONFIG_SYS_SDRAM_SIZE 16" >>$(obj)include/config.h ;\ + fi ; + @if [ "$(findstring E32,$@)" ] ; then \ + echo "#define __32MRam__ " >>$(obj)include/config.h ;\ + echo "#define CONFIG_SYS_SDRAM_SIZE 32" >>$(obj)include/config.h ;\ + fi ; + @$(MKCONFIG) -a uC5272 m68k mcf52x2 uC5272 Arcturus + # ## MPC83xx Systems # diff --git a/board/Arcturus/uC5272/Makefile b/board/Arcturus/uC5272/Makefile new file mode 100644 index 000..424ab1c --- /dev/null +++ b/board/Arcturus/uC5272/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +# + +# defines $(obj).depend target +in
[U-Boot] [PATCH 4/6] adding uC5274/5275 dimm module support
Signed-off-by: David Wu --- Makefile | 21 +++ board/Arcturus/uC5275/Makefile | 44 +++ board/Arcturus/uC5275/config.mk | 23 board/Arcturus/uC5275/u-boot.lds | 139 board/Arcturus/uC5275/uC5275.c | 118 + include/configs/uC5275.h | 263 ++ 6 files changed, 608 insertions(+), 0 deletions(-) create mode 100644 board/Arcturus/uC5275/Makefile create mode 100644 board/Arcturus/uC5275/config.mk create mode 100644 board/Arcturus/uC5275/u-boot.lds create mode 100644 board/Arcturus/uC5275/uC5275.c create mode 100644 include/configs/uC5275.h diff --git a/Makefile b/Makefile index c9215d0..6dad806 100644 --- a/Makefile +++ b/Makefile @@ -2268,6 +2268,27 @@ uC5272-8EE32U66_config: unconfig fi ; @$(MKCONFIG) -a uC5272 m68k mcf52x2 uC5272 Arcturus +uC5274-16E322T150_config \ +uC5275-16EE32U150_config \ +uC5275-16EE32M150_config: unconfig + @mkdir -p $(obj)include + @echo "#define PRODUCTION_STRING " \"$(@:_config=)\" >> $(obj)include/config.h + @if [ "$(findstring 5274,$@)" ] ; then \ + echo "#define CONFIG_M5274 " >>$(obj)include/config.h ;\ + fi ; + @if [ "$(findstring EE,$@)" ] ; then \ + echo "#define CONFIG_HAS_ETH1 " >>$(obj)include/config.h ;\ + fi ; + @if [ "$(findstring 16E,$@)" ] ; then \ + echo "#define __16MFlash__ " >>$(obj)include/config.h ;\ + echo "#define CONFIG_SYS_FLASH_SIZE 0x0100" >> $(obj)include/config.h ;\ + fi ; + @if [ "$(findstring E32,$@)" ] ; then \ + echo "#define __32MRam__ " >>$(obj)include/config.h ;\ + echo "#define CONFIG_SYS_SDRAM_SIZE 32" >>$(obj)include/config.h ;\ + fi ; + @$(MKCONFIG) -a uC5275 m68k mcf52x2 uC5275 Arcturus + # ## MPC83xx Systems # diff --git a/board/Arcturus/uC5275/Makefile b/board/Arcturus/uC5275/Makefile new file mode 100644 index 000..981763d --- /dev/null +++ b/board/Arcturus/uC5275/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/Arcturus/uC5275/config.mk b/board/Arcturus/uC5275/config.mk new file mode 100644 index 000..4605e0e --- /dev/null +++ b/board/Arcturus/uC5275/config.mk @@ -0,0 +1,23 @@ +# +# (c) Copyright 2010 Arcturus Networks Inc. +# by David Wu +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +TEXT_BASE = 0xf000 diff --git a/board/Arcturus/uC
[U-Boot] [PATCH 6/6] adding credit for uC5272, uC5274/5275 and uC5282
Signed-off-by: David Wu --- CREDITS |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/CREDITS b/CREDITS index 043ba6e..144fc27 100644 --- a/CREDITS +++ b/CREDITS @@ -513,7 +513,7 @@ D: Port to MPC555/556 microcontrollers and support for cmi board N: David Wu E: supp...@arcturusnetworks.com -D: Mercury Security EP2500 +D: Mercury Security EP2500; Arcturus Networks Inc. uC5272, uC5274/5275 and uC5282 W: http://www.arcturusnetworks.com N: Ming-Len Wu -- 1.5.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2] AT49BV322A Flash: the erase regions are in the wrong order.
The device id for this Flash is 0xc8. Signed-off-by: David Wu --- drivers/mtd/cfi_flash.c |4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index fdba297..af86f99 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1690,8 +1690,10 @@ static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry) /* AT49BV6416(T) list the erase regions in the wrong order. * However, the device ID is identical with the non-broken * AT49BV642D they differ in the high byte. +* AT49BV322A is also in the wrong order. */ - if (info->device_id == 0xd6 || info->device_id == 0xd2) + if (info->device_id == 0xd6 || info->device_id == 0xd2 || + info->device_id == 0xc8) reverse_geometry = !reverse_geometry; if (reverse_geometry) -- 1.5.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/7] added Mercury EP2500 board support It uses the mcf5282 processor with real time clock and EEPROM.
Hi Wolfgang,
Thanks for checking the patch, Please see inline.
On Fri, 09 Apr 2010 18:51:06 -0400, Wolfgang Denk wrote:
> Dear "David Wu",
>
> In message you wrote:
>> Signed-off-by: David Wu
>> ---
>> board/Mercury/ep2500/Makefile | 44 ++
>> board/Mercury/ep2500/config.mk | 23 +++
>> board/Mercury/ep2500/ep2500.c | 191 +
>> board/Mercury/ep2500/u-boot.lds | 140 ++
>> include/configs/EP2500.h| 297
>> +++
>> 5 files changed, 695 insertions(+), 0 deletions(-)
>> create mode 100644 board/Mercury/ep2500/Makefile
>> create mode 100644 board/Mercury/ep2500/config.mk
>> create mode 100644 board/Mercury/ep2500/ep2500.c
>> create mode 100644 board/Mercury/ep2500/u-boot.lds
>> create mode 100644 include/configs/EP2500.h
>
> Your Subject (= commit message tile) is WAY too long.
Let me know the size of subject line.
> Don't try to press everything in a single line.
>
> Entries to MAINTAINERS and MAKEALL are missing.
Will add them in. My patch is actually applied on top of another set of
patches from TsiChung.
>> +void board_get_enetaddr(uchar *enet)
>> +{
>> +int i;
>> +unsigned char buff[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
>> +
>> +/* Read MAC address (6 bytes) in EEPROM */
>> +if (i2c_read
>> +(CONFIG_SYS_I2C_EEPROM_ADDR, MAC_ADDRESS_OFFSET_IN_EEPROM,
>> + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buff, 6) != 0) {
>> +puts("Error reading the EEPROM.\n");
>> +}
>> +
>> +/*
>> + * When buff returns all 0xFF the EEPROM has not
>> + * been programed with a valid MAC. In this case
>> + * we set enet to all 0x00 as 0xFF is not valid
>> + * for this usage model.
>> + */
>> +if (buff[0] == 0xff && buff[1] == 0xff && buff[2] == 0xff &&
>> +buff[3] == 0xff && buff[4] == 0xff && buff[5] == 0xff) {
>
> We have standard functions for such checks. Please use them.
It would be nice if you can let me know the function. I am grep'ing in
u-boot and it's so hard to find it.
>> +for (i = 0; i < 6; i++)
>> +enet[i] = 0;
>> +} else {
>> +for (i = 0; i < 6; i++)
>> +enet[i] = buff[i];
>> +}
>
> Hm... the whole code makes no sense to me, as neiter all-ones nor
> all-zeros are legal MAC addresses.
All ones are valid broadcast MAC address. It is just not valid for source
MAC address.
I want to set to all zeros instead in case of all FFs. Is this against any
rules?
>
>
>> +int misc_init_r(void)
>> +{
>> +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
>> +uchar enetaddr[6];
>> +
>> +if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
>> +board_get_enetaddr(enetaddr);
>> +eth_setenv_enetaddr("ethaddr", enetaddr);
>
> Please see recent discussion about this topic.
Could you let me know the thread -- I am new here.
>
>> +void i2c_init_board(void)
>> +{
>> +struct fsl_i2c *dev;
>> +
>> +dev = (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
>> +
>> +if (readb(&dev->sr) & I2C_SR_MBB) {
>> +writeb(0, &dev->cr);
>> +writeb(0xa0, &dev->cr);
>> +readb(&dev->dr);
>> +writeb(0x0, &dev->sr);
>> +writeb(0, &dev->cr);
>> +writeb(I2C_CR_MEN, &dev->cr);
>
> Please add comments what you are doing. Replace 0x0A by a symbolic
You mean comments for "writeb(0xa0, &dev->cr)" -- OK.
> name. Use a consistent style (i. e. wither use "0x0" or "0", but
> don't mix both styles.
>> +#ifdef CONFIG_MCFFEC
>> +# define CONFIG_ETHADDR 00:00:00:00:00:00
>> +# define CONFIG_IPADDR192.168.1.2
>> +# define CONFIG_NETMASK 255.255.255.0
>> +# define CONFIG_SERVERIP 192.168.1.1
>> +# define CONFIG_GATEWAYIP 192.168.1.1
>> +# define CONFIG_OVERWRITE_ETHADDR_ONCE
>> +/*#define CONFIG_ENV_OVERWRITE */
>
> Please remove this, it will not be accepted.
Are you talking about the last line. Sure I can remove it.
Otherwise would you mind tell me the reason? format is wrong, some defines
are wrong or ifdef (or use if defined instead)?
Kind regards,
David
>
> Best regards,
>
> Wolfgang Denk
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Re: [U-Boot] [PATCH 4/7] Adding uC5272 dimm module support
Hi Wolfgang, On Fri, 09 Apr 2010 18:54:33 -0400, Wolfgang Denk wrote: > Dear "David Wu", > > In message you wrote: >> Signed-off-by: David Wu >> --- >> Makefile | 46 + >> board/Arcturus/uC5272/Makefile | 44 + >> board/Arcturus/uC5272/config.mk |1 + >> board/Arcturus/uC5272/u-boot.lds | 142 +++ >> board/Arcturus/uC5272/uC5272.c | 57 ++ >> include/configs/uC5272.h | 354 >> ++ >> 6 files changed, 644 insertions(+), 0 deletions(-) >> create mode 100644 board/Arcturus/uC5272/Makefile >> create mode 100644 board/Arcturus/uC5272/config.mk >> create mode 100644 board/Arcturus/uC5272/u-boot.lds >> create mode 100644 board/Arcturus/uC5272/uC5272.c >> create mode 100644 include/configs/uC5272.h >> >> diff --git a/Makefile b/Makefile >> index 1b61049..c9215d0 100644 >> --- a/Makefile >> +++ b/Makefile >> @@ -,6 +,52 @@ M5485HFE_config : unconfig >> TASREG_config :unconfig >> @$(MKCONFIG) $(@:_config=) m68k mcf52x2 tasreg esd >> >> +uC5272-4E16U48_config \ >> +uC5272-8EE16U66_config \ >> +uC5272-8E32U66_config \ >> +uC5272-4EE16U48_config \ >> +uC5272-4E8U48_config \ >> +uC5272-4EE8U48_config \ >> +uC5272-4E8U66_config \ >> +uC5272-4EE8U66_config \ >> +uC5272-4E16U66_config \ >> +uC5272-4EE16U66_config \ >> +uC5272-4EE32U66_config \ >> +uC5272-8EE32U66_config: unconfig >> +@mkdir -p $(obj)include >> +@if [ "$(findstring U48,$@)" ] ; then \ >> +echo "#define SYSCLK_48MHZ " >>$(obj)include/config.h ;\ >> +fi ; >> +@if [ "$(findstring U66,$@)" ] ; then \ >> +echo "#define SYSCLK_66MHZ " >>$(obj)include/config.h ;\ >> +fi ; >> +@if [ "$(findstring EE,$@)" ] ; then \ >> +echo "#define HAS_ETH1 " >>$(obj)include/config.h ;\ >> +fi ; >> +@if [ "$(findstring 4E,$@)" ] ; then \ >> +echo "#define __4MFlash__ " >>$(obj)include/config.h ;\ >> +echo "#define CONFIG_SYS_FLASH_SIZE 0x0040" >> >>$(obj)include/config.h ;\ >> +echo "TEXT_BASE = 0x10c0" > board/Arcturus/uC5272/config.mk >> ;\ >> +fi ; >> +@if [ "$(findstring 8E,$@)" ] ; then \ >> +echo "#define __8MFlash__ " >>$(obj)include/config.h ;\ >> +echo "#define CONFIG_SYS_FLASH_SIZE 0x0080" >> >>$(obj)include/config.h ;\ >> +echo "TEXT_BASE = 0x4000" > board/Arcturus/uC5272/config.mk >> ;\ >> +fi ; >> +@if [ "$(findstring E8,$@)" ] ; then \ >> +echo "#define __8MRam__ " >>$(obj)include/config.h ;\ >> +echo "#define CONFIG_SYS_SDRAM_SIZE 8" >>$(obj)include/config.h >> ;\ >> +fi ; >> +@if [ "$(findstring E16,$@)" ] ; then \ >> +echo "#define __16MRam__ " >>$(obj)include/config.h ;\ >> +echo "#define CONFIG_SYS_SDRAM_SIZE 16" >> >>$(obj)include/config.h ;\ >> +fi ; >> +@if [ "$(findstring E32,$@)" ] ; then \ >> +echo "#define __32MRam__ " >>$(obj)include/config.h ;\ >> +echo "#define CONFIG_SYS_SDRAM_SIZE 32" >> >>$(obj)include/config.h ;\ >> +fi ; >> +@$(MKCONFIG) -a uC5272 m68k mcf52x2 uC5272 Arcturus >> + > > NAK! > > > You must be joking. > > We will not accept such a mess of scriting in the top level Makefile. It was/is a mess already. I just followed the exact top level Makefile. If it is not acceptable then I'd like to know if it is OK to -- make one separate header file in include/configs for each board -- and one config.mk per board -- or other methods -- advise please > > Also, I don't understand why adding DIMM module support would result > in a new config.mk file and a new linker script being added? TEXT_BASE is changed due to changes in the memory map for different DIMM modules with different size of SDRAM and FLASH. TEXT_BASE is defined in config.mk - I thought this is the only location that really matters. Other boards may using another temporary file and included in config.mk. For me why bother to modify config.mk file directly. If there is a better choice I would like to use. One way to do is each board has a unique config.mk. > The additions to the board config file are an unacceptable mess, too. You mean you cannot understand the ifdefs so you think it is a mess? But I feel it is so neat and it supports many different configurations for uCdimm 5272 modules. I also can create many of these files with a few lines differences by each. How about this? > This needs a complete rework. Sure. I need more feed back. then I will. thanks, David > Best regards, > > Wolfgang Denk > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
Hi Lukasz,
在 2019/1/19 上午7:34, Lukasz Majewski 写道:
Hi David,
Hi Heiko,
在 2019/1/6 上午1:17, Heiko Stuebner 写道:
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c
b/arch/arm/mach-rockchip/rk3188-board-spl.c index
3c6c3d3c09..a5e4d39cb7 100644 ---
a/arch/arm/mach-rockchip/rk3188-board-spl.c +++
b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -120,7 +120,7 @@
void board_debug_uart_init(void)
void board_init_f(ulong dummy)
{
- struct udevice *pinctrl, *dev;
+ struct udevice *dev;
int ret;
#define EARLY_UART
@@ -134,10 +134,7 @@ void board_init_f(ulong dummy)
* printascii("string");
*/
debug_uart_init();
- printch('s');
- printch('p');
- printch('l');
- printch('\n');
+ printascii("U-Boot SPL board init");
Did you test this change?
I remember rk3188 having issues (aka hanging) when trying to print
strings through the debug uart and only printch working at all.
(Timer issue or so?) ... Not sure if this got fixed in the meantime?
But you are using the debug uart for "production". Please use the
proper driver.
You may either properly setup normal uart or buffer the console output
until the uart is configured by device model (DM).
Here, we just use it for debug print, and the sram size is limited to
use more complex driver at spl stage.
I don't know there was a issue, but i test it on the Radxa board
today, it looks okay.
U-Boot SPL board init
U-Boot SPL 2019.01-rc1-9-gdd7b9156fe (Jan 14 2019 - 19:53:50
+0800) Returning to boot ROM...
U-Boot 2019.01-rc1-9-gdd7b9156fe (Jan 14 2019 - 19:53:50 +0800)
Model: Radxa Rock
DRAM: 2 GiB
MMC: dwmmc@10214000: 0
Loading Environment from MMC... Card did not respond to voltage
select! *** Warning - No block device, using default environment
In:serial@20064000
Out: serial@20064000
Err: serial@20064000
Model: Radxa Rock
rockchip_dnl_key_pressed: adc_channel_single_shot fail!
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0
=>
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Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
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Re: [U-Boot] [PATCH v2 0/9] Add common pinctrl driver support for rockchip
Ping Philipp... 在 2019/1/22 上午2:50, Simon Glass 写道: Hi, On Thu, 3 Jan 2019 at 01:51, David Wu wrote: The common pinctrl driver for rockchip Socs, it depends the PINCTRL_FULL config. If use it, the default pinctrl setup from DTS could be configured at device probe. Changes in v2: - Remove px30, rk2928, rk3066*. - Split it to multiple files for the relevant per-SoC data structures. David Wu (9): rockchip: rk3399-evb: defconfig: Enable FDT for new pinctrl driver ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188 ARM: rockchip: Remove the pinctrl request at rk3288-board-spl rk3288: chrome: defconfig: Enable FDT for new pinctrl driver pinctrl: rockchip: Add common rockchip pinctrl driver rockchip: defconfig: Clean the unused pinctrl config pinctrl: rockchip: Clean the unused rockchip pinctrl drivers ARM: dts: rk322x: Correct the uart2 default pin configuration arch/arm/dts/rk322x.dtsi | 11 +- arch/arm/mach-rockchip/Kconfig| 1 - arch/arm/mach-rockchip/rk3188-board-spl.c | 41 +- arch/arm/mach-rockchip/rk3288-board-spl.c | 79 -- configs/chromebit_mickey_defconfig| 4 - configs/chromebook_jerry_defconfig| 4 - configs/chromebook_minnie_defconfig | 4 - configs/evb-px5_defconfig | 1 - configs/evb-rk3128_defconfig | 1 - configs/evb-rk3229_defconfig | 1 - configs/evb-rk3288_defconfig | 2 - configs/evb-rk3399_defconfig | 2 - configs/evb-rv1108_defconfig | 1 - configs/fennec-rk3288_defconfig | 2 - configs/firefly-rk3288_defconfig | 2 - configs/firefly-rk3399_defconfig | 1 - configs/geekbox_defconfig | 1 - configs/kylin-rk3036_defconfig| 1 - configs/lion-rk3368_defconfig | 1 - configs/miqi-rk3288_defconfig | 2 - configs/phycore-rk3288_defconfig | 2 - configs/popmetal-rk3288_defconfig | 2 - configs/puma-rk3399_defconfig | 1 - configs/rock2_defconfig | 2 - configs/rock_defconfig| 1 - configs/sandbox_defconfig | 2 - configs/sandbox_flattree_defconfig| 2 - configs/sandbox_noblk_defconfig | 2 - configs/sheep-rk3368_defconfig| 1 - configs/tinker-rk3288_defconfig | 2 - configs/vyasa-rk3288_defconfig| 2 - drivers/pinctrl/Kconfig | 91 +- drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/rockchip/Kconfig | 17 + drivers/pinctrl/rockchip/Makefile | 19 +- drivers/pinctrl/rockchip/pinctrl-rk3036.c | 65 ++ drivers/pinctrl/rockchip/pinctrl-rk3128.c | 155 +++ drivers/pinctrl/rockchip/pinctrl-rk3188.c | 82 ++ drivers/pinctrl/rockchip/pinctrl-rk322x.c | 215 drivers/pinctrl/rockchip/pinctrl-rk3288.c | 157 +++ drivers/pinctrl/rockchip/pinctrl-rk3328.c | 227 drivers/pinctrl/rockchip/pinctrl-rk3368.c | 116 ++ drivers/pinctrl/rockchip/pinctrl-rk3399.c | 193 .../pinctrl/rockchip/pinctrl-rockchip-core.c | 788 ++ drivers/pinctrl/rockchip/pinctrl-rockchip.h | 302 ++ drivers/pinctrl/rockchip/pinctrl-rv1108.c | 203 drivers/pinctrl/rockchip/pinctrl_rk3036.c | 671 drivers/pinctrl/rockchip/pinctrl_rk3128.c | 186 drivers/pinctrl/rockchip/pinctrl_rk3188.c | 989 -- drivers/pinctrl/rockchip/pinctrl_rk322x.c | 894 drivers/pinctrl/rockchip/pinctrl_rk3288.c | 869 --- drivers/pinctrl/rockchip/pinctrl_rk3328.c | 705 - drivers/pinctrl/rockchip/pinctrl_rk3368.c | 739 - drivers/pinctrl/rockchip/pinctrl_rk3399.c | 503 - drivers/pinctrl/rockchip/pinctrl_rv1108.c | 580 -- 55 files changed, 2543 insertions(+), 6406 deletions(-) create mode 100644 drivers/pinctrl/rockchip/Kconfig create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3036.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3128.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3188.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk322x.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3288.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3328.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3368.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3399.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rockchip-core.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rockchip.h create mode 100644 drivers/pinctrl
Re: [U-Boot] [PATCH v3 5/8] rockchip: rk3399: Add improved pinctrl driver.
Hi Christoph,
I once submitted a series of patches that they can support all Socs'
Pinctrl and how do you feel about using them.
http://patchwork.ozlabs.org/patch/868849/
在 2018/12/27 上午9:11, Kever Yang 写道:
Add David to review the pinctrl driver.
Thanks,
- Kever
On 12/17/2018 09:30 PM, Christoph Muellner wrote:
The current pinctrl driver for the RK3399 has a range of qulity issues.
E.g. it only implements the .set_state_simple() callback, it
does not parse the available pinctrl information from the DTS
(instead uses hardcoded values), is not flexible enough to cover
devices without 'interrupt' field in the DTS (e.g. PWM),
is not written generic enough to make code reusable among other
rockchip SoCs...
This patch addresses these issues by reimplementing the whole driver
from scratch using the .set_state() callback.
The new implementation covers all featurese of the old code
(i.e. it supports pinmuxing and pullup/pulldown configuration).
This patch has been tested on a RK3399-Q7 SoM (Puma).
Signed-off-by: Christoph Muellner
---
Changes in v3: None
Changes in v2: None
drivers/pinctrl/rockchip/pinctrl_rk3399.c | 226 ++
1 file changed, 226 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
index bc92dd7c06..ed9828989f 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) 2018 Theobroma Systems Design und Consulting GmbH
*/
#include
@@ -14,11 +15,234 @@
#include
#include
+static const u32 RK_GRF_P_PULLUP = 1;
+static const u32 RK_GRF_P_PULLDOWN = 2;
+
struct rk3399_pinctrl_priv {
struct rk3399_grf_regs *grf;
struct rk3399_pmugrf_regs *pmugrf;
+ struct rockchip_pin_bank *banks;
+};
+
+/**
+ * Location of pinctrl/pinconf registers.
+ */
+enum rk_grf_location {
+ RK_GRF,
+ RK_PMUGRF,
+};
+
+/**
+ * @nr_pins: number of pins in this bank
+ * @bank_num: number of the bank, to account for holes
+ * @iomux: array describing the 4 iomux sources of the bank
+ */
+struct rockchip_pin_bank {
+ u8 nr_pins;
+ enum rk_grf_location grf_location;
+ size_t iomux_offset;
+ size_t pupd_offset;
};
+#define PIN_BANK(pins, grf, iomux, pupd) \
+ { \
+ .nr_pins = pins,\
+ .grf_location = grf,\
+ .iomux_offset = iomux, \
+ .pupd_offset = pupd,\
+ }
+
+static struct rockchip_pin_bank rk3399_pin_banks[] = {
+ PIN_BANK(16, RK_PMUGRF,
+offsetof(struct rk3399_pmugrf_regs, gpio0a_iomux),
+offsetof(struct rk3399_pmugrf_regs, gpio0_p)),
+ PIN_BANK(32, RK_PMUGRF,
+offsetof(struct rk3399_pmugrf_regs, gpio1a_iomux),
+offsetof(struct rk3399_pmugrf_regs, gpio1_p)),
+ PIN_BANK(32, RK_GRF,
+offsetof(struct rk3399_grf_regs, gpio2a_iomux),
+offsetof(struct rk3399_grf_regs, gpio2_p)),
+ PIN_BANK(32, RK_GRF,
+offsetof(struct rk3399_grf_regs, gpio3a_iomux),
+offsetof(struct rk3399_grf_regs, gpio3_p)),
+ PIN_BANK(32, RK_GRF,
+offsetof(struct rk3399_grf_regs, gpio4a_iomux),
+offsetof(struct rk3399_grf_regs, gpio4_p)),
+};
+
+static void rk_pinctrl_get_info(uintptr_t base, u32 index, uintptr_t *addr,
+ u32 *shift, u32 *mask)
+{
+ /*
+* In general we four subsequent 32-bit configuration registers
+* per bank (e.g. GPIO2A_P, GPIO2B_P, GPIO2C_P, GPIO2D_P).
+* The configuration for each pin has two bits.
+*
+* @base...contains the address to the first register.
+* @index...defines the pin within the bank (0..31).
+* @addr...will be the address of the actual register to use
+*/
+
+ const u32 pins_per_register = 8;
+ const u32 config_bits_per_pin = 2;
+
+ /* Get the address of the configuration register. */
+ *addr = base + (index / pins_per_register) * sizeof(u32);
+
+ /* Get the bit offset within the configruation register. */
+ *shift = (index & (pins_per_register - 1)) * config_bits_per_pin;
+
+ /* Get the (unshifted) mask for the configuration pins. */
+ *mask = ((1 << config_bits_per_pin) - 1);
+
+ pr_debug("%s: addr=0x%lx, mask=0x%x, shift=0x%x\n",
+__func__, *addr, *mask, *shift);
+}
+
+static void rk3399_pinctrl_set_pin_iomux(uintptr_t grf_addr,
+struct rockchip_pin_bank *bank,
+u32 index, u32 muxval)
+{
+ uintptr_t iomux_base, addr;
+ u32 shift, mask;
+
+
Re: [U-Boot] [PATCH v3 5/8] rockchip: rk3399: Add improved pinctrl driver.
Hi Christoph,
This patch seems is less of code about drive strength, for some modules,
like LCD, Ethernet is still needed.
在 2018/12/27 下午9:13, Christoph Müllner 写道:
Hi David,
On 12/27/18 1:49 PM, David Wu wrote:
Hi Christoph,
I once submitted a series of patches that they can support all Socs'
Pinctrl and how do you feel about using them.
Thank's for pointing to that.
Your driver looks good, but I don't like the huge amount
of duplication in it (you have a function rk_calc_pull_reg_and_bit()
for each SoC variant, which more or less do all the same).
Also I prefer to have a generic core driver and SoC specific parts
in their own C files (to have a slim driver for each SoC, but a maximum
of code reuse). Also Kconfig entries like PINCTRL_ROCKCHIP_RK3188 don't
seem to do anything in your driver.
Since this is from Feb 2018:
May I ask, why you did not continue to bring that mainline?
It seems i have lost them in my mailbox. I'm going to update a new
version in the near future.
My plan is to get the driver in for RK3399 asap and enable it only for
the RK3399-Q7 board for now (to not mess with other boards).
During the next merge window I want to move the generic parts into their
own C files. Other SoC-specific drivers can follow then with their own
mini-drivers (no code just configuration).
Thanks,
Christoph
http://patchwork.ozlabs.org/patch/868849/
在 2018/12/27 上午9:11, Kever Yang 写道:
Add David to review the pinctrl driver.
Thanks,
- Kever
On 12/17/2018 09:30 PM, Christoph Muellner wrote:
The current pinctrl driver for the RK3399 has a range of qulity issues.
E.g. it only implements the .set_state_simple() callback, it
does not parse the available pinctrl information from the DTS
(instead uses hardcoded values), is not flexible enough to cover
devices without 'interrupt' field in the DTS (e.g. PWM),
is not written generic enough to make code reusable among other
rockchip SoCs...
This patch addresses these issues by reimplementing the whole driver
from scratch using the .set_state() callback.
The new implementation covers all featurese of the old code
(i.e. it supports pinmuxing and pullup/pulldown configuration).
This patch has been tested on a RK3399-Q7 SoM (Puma).
Signed-off-by: Christoph Muellner
---
Changes in v3: None
Changes in v2: None
drivers/pinctrl/rockchip/pinctrl_rk3399.c | 226
++
1 file changed, 226 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
index bc92dd7c06..ed9828989f 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) 2018 Theobroma Systems Design und Consulting GmbH
*/
#include
@@ -14,11 +15,234 @@
#include
#include
+static const u32 RK_GRF_P_PULLUP = 1;
+static const u32 RK_GRF_P_PULLDOWN = 2;
+
struct rk3399_pinctrl_priv {
struct rk3399_grf_regs *grf;
struct rk3399_pmugrf_regs *pmugrf;
+ struct rockchip_pin_bank *banks;
+};
+
+/**
+ * Location of pinctrl/pinconf registers.
+ */
+enum rk_grf_location {
+ RK_GRF,
+ RK_PMUGRF,
+};
+
+/**
+ * @nr_pins: number of pins in this bank
+ * @bank_num: number of the bank, to account for holes
+ * @iomux: array describing the 4 iomux sources of the bank
+ */
+struct rockchip_pin_bank {
+ u8 nr_pins;
+ enum rk_grf_location grf_location;
+ size_t iomux_offset;
+ size_t pupd_offset;
};
+#define PIN_BANK(pins, grf, iomux, pupd) \
+ { \
+ .nr_pins = pins, \
+ .grf_location = grf, \
+ .iomux_offset = iomux, \
+ .pupd_offset = pupd, \
+ }
+
+static struct rockchip_pin_bank rk3399_pin_banks[] = {
+ PIN_BANK(16, RK_PMUGRF,
+ offsetof(struct rk3399_pmugrf_regs, gpio0a_iomux),
+ offsetof(struct rk3399_pmugrf_regs, gpio0_p)),
+ PIN_BANK(32, RK_PMUGRF,
+ offsetof(struct rk3399_pmugrf_regs, gpio1a_iomux),
+ offsetof(struct rk3399_pmugrf_regs, gpio1_p)),
+ PIN_BANK(32, RK_GRF,
+ offsetof(struct rk3399_grf_regs, gpio2a_iomux),
+ offsetof(struct rk3399_grf_regs, gpio2_p)),
+ PIN_BANK(32, RK_GRF,
+ offsetof(struct rk3399_grf_regs, gpio3a_iomux),
+ offsetof(struct rk3399_grf_regs, gpio3_p)),
+ PIN_BANK(32, RK_GRF,
+ offsetof(struct rk3399_grf_regs, gpio4a_iomux),
+ offsetof(struct rk3399_grf_regs, gpio4_p)),
+};
+
+static void rk_pinctrl_get_info(uintptr_t base, u32 index, uintptr_t
*addr,
+ u32 *shift, u32 *mask)
+{
+ /*
+ * In general we four subsequent 32-bit configuration registers
+ * per bank (e.g. GPIO2A_P, GPIO2B_P, GPIO2C_P, GPIO2D_P).
+ * The configuration for each pin has two bits.
+ *
+ * @base...contain
Re: [U-Boot] [PATCH v3 5/8] rockchip: rk3399: Add improved pinctrl driver.
Hi Philipp, 在 2018/12/27 下午10:31, Philipp Tomsich 写道: David, On 27.12.2018, at 13:49, David Wu wrote: Hi Christoph, I once submitted a series of patches that they can support all Socs' Pinctrl and how do you feel about using them. http://patchwork.ozlabs.org/patch/868849/ Which reminds me that I am still waiting for a newer revision that addresses the various comments (e.g. breaking up into a driver and mini-drivers/driver-data, not including support for yet-unsupported SoCs, etc.)... Are you planning to do an updatted and rebased version in the near future? Yes, i will pick them up, and update. Thanks, Philipp. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 0/9] Add common pinctrl driver support for rockchip
The common pinctrl driver for rockchip Socs, it depends the PINCTRL_FULL config. If use it, the default pinctrl setup from DTS could be configured at device probe. Changes in v2: - Remove px30, rk2928, rk3066*. - Split it to multiple files for the relevant per-SoC data structures. David Wu (9): rockchip: rk3399-evb: defconfig: Enable FDT for new pinctrl driver ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188 ARM: rockchip: Remove the pinctrl request at rk3288-board-spl rk3288: chrome: defconfig: Enable FDT for new pinctrl driver pinctrl: rockchip: Add common rockchip pinctrl driver rockchip: defconfig: Clean the unused pinctrl config pinctrl: rockchip: Clean the unused rockchip pinctrl drivers ARM: dts: rk322x: Correct the uart2 default pin configuration arch/arm/dts/rk322x.dtsi | 11 +- arch/arm/mach-rockchip/Kconfig| 1 - arch/arm/mach-rockchip/rk3188-board-spl.c | 41 +- arch/arm/mach-rockchip/rk3288-board-spl.c | 79 -- configs/chromebit_mickey_defconfig| 4 - configs/chromebook_jerry_defconfig| 4 - configs/chromebook_minnie_defconfig | 4 - configs/evb-px5_defconfig | 1 - configs/evb-rk3128_defconfig | 1 - configs/evb-rk3229_defconfig | 1 - configs/evb-rk3288_defconfig | 2 - configs/evb-rk3399_defconfig | 2 - configs/evb-rv1108_defconfig | 1 - configs/fennec-rk3288_defconfig | 2 - configs/firefly-rk3288_defconfig | 2 - configs/firefly-rk3399_defconfig | 1 - configs/geekbox_defconfig | 1 - configs/kylin-rk3036_defconfig| 1 - configs/lion-rk3368_defconfig | 1 - configs/miqi-rk3288_defconfig | 2 - configs/phycore-rk3288_defconfig | 2 - configs/popmetal-rk3288_defconfig | 2 - configs/puma-rk3399_defconfig | 1 - configs/rock2_defconfig | 2 - configs/rock_defconfig| 1 - configs/sandbox_defconfig | 2 - configs/sandbox_flattree_defconfig| 2 - configs/sandbox_noblk_defconfig | 2 - configs/sheep-rk3368_defconfig| 1 - configs/tinker-rk3288_defconfig | 2 - configs/vyasa-rk3288_defconfig| 2 - drivers/pinctrl/Kconfig | 91 +- drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/rockchip/Kconfig | 17 + drivers/pinctrl/rockchip/Makefile | 19 +- drivers/pinctrl/rockchip/pinctrl-rk3036.c | 65 ++ drivers/pinctrl/rockchip/pinctrl-rk3128.c | 155 +++ drivers/pinctrl/rockchip/pinctrl-rk3188.c | 82 ++ drivers/pinctrl/rockchip/pinctrl-rk322x.c | 215 drivers/pinctrl/rockchip/pinctrl-rk3288.c | 157 +++ drivers/pinctrl/rockchip/pinctrl-rk3328.c | 227 drivers/pinctrl/rockchip/pinctrl-rk3368.c | 116 ++ drivers/pinctrl/rockchip/pinctrl-rk3399.c | 193 .../pinctrl/rockchip/pinctrl-rockchip-core.c | 788 ++ drivers/pinctrl/rockchip/pinctrl-rockchip.h | 302 ++ drivers/pinctrl/rockchip/pinctrl-rv1108.c | 203 drivers/pinctrl/rockchip/pinctrl_rk3036.c | 671 drivers/pinctrl/rockchip/pinctrl_rk3128.c | 186 drivers/pinctrl/rockchip/pinctrl_rk3188.c | 989 -- drivers/pinctrl/rockchip/pinctrl_rk322x.c | 894 drivers/pinctrl/rockchip/pinctrl_rk3288.c | 869 --- drivers/pinctrl/rockchip/pinctrl_rk3328.c | 705 - drivers/pinctrl/rockchip/pinctrl_rk3368.c | 739 - drivers/pinctrl/rockchip/pinctrl_rk3399.c | 503 - drivers/pinctrl/rockchip/pinctrl_rv1108.c | 580 -- 55 files changed, 2543 insertions(+), 6406 deletions(-) create mode 100644 drivers/pinctrl/rockchip/Kconfig create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3036.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3128.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3188.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk322x.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3288.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3328.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3368.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3399.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rockchip-core.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rockchip.h create mode 100644 drivers/pinctrl/rockchip/pinctrl-rv1108.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3128.c delete mode 100644 drivers/pinctrl
[U-Boot] [PATCH v2 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
When the boot ROM sets up MMC we don't need to do it again. Remove the
MMC setup code entirely, but we also need to enable uart for debug message.
Signed-off-by: David Wu
---
Changes in v2: None
arch/arm/mach-rockchip/rk3188-board-spl.c | 41 ++-
1 file changed, 2 insertions(+), 39 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c
b/arch/arm/mach-rockchip/rk3188-board-spl.c
index 3c6c3d3c09..a5e4d39cb7 100644
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -120,7 +120,7 @@ void board_debug_uart_init(void)
void board_init_f(ulong dummy)
{
- struct udevice *pinctrl, *dev;
+ struct udevice *dev;
int ret;
#define EARLY_UART
@@ -134,10 +134,7 @@ void board_init_f(ulong dummy)
* printascii("string");
*/
debug_uart_init();
- printch('s');
- printch('p');
- printch('l');
- printch('\n');
+ printascii("U-Boot SPL board init");
#endif
#ifdef CONFIG_ROCKCHIP_USB_UART
@@ -171,12 +168,6 @@ void board_init_f(ulong dummy)
return;
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- debug("Pinctrl init failed: %d\n", ret);
- return;
- }
-
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
debug("DRAM init failed: %d\n", ret);
@@ -214,7 +205,6 @@ static int setup_led(void)
void spl_board_init(void)
{
- struct udevice *pinctrl;
int ret;
ret = setup_led();
@@ -223,36 +213,9 @@ void spl_board_init(void)
hang();
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- debug("%s: Cannot find pinctrl device\n", __func__);
- goto err;
- }
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
- if (ret) {
- debug("%s: Failed to set up SD card\n", __func__);
- goto err;
- }
-#endif
-
- /* Enable debug UART */
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
- if (ret) {
- debug("%s: Failed to set up console UART\n", __func__);
- goto err;
- }
-
preloader_console_init();
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
return;
-
-err:
- printf("spl_board_init: Error %d\n", ret);
-
- /* No way to report error here */
- hang();
}
--
2.19.1
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[U-Boot] [PATCH v2 1/9] rockchip: rk3399-evb: defconfig: Enable FDT for new pinctrl driver
The FDT is requested for new pinctrl driver, disable SPL_OF_PLATDATA to make FDT be built in. Signed-off-by: David Wu --- Changes in v2: None configs/evb-rk3399_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index f173c10a6b..27cf8304be 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -31,7 +31,6 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y -- 2.19.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 3/9] ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188
It seems that pinctrl is not requested for rk3188 SPL, remove it so that can save more space for SPL image size. Signed-off-by: David Wu Reviewed-by: Philipp Tomsich --- Changes in v2: None arch/arm/mach-rockchip/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6dc8e3a017..15c6ed2340 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -29,7 +29,6 @@ config ROCKCHIP_RK3188 select SUPPORT_SPL select SPL select SPL_CLK - select SPL_PINCTRL select SPL_REGMAP select SPL_SYSCON select SPL_RAM -- 2.19.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 4/9] ARM: rockchip: Remove the pinctrl request at rk3288-board-spl
If we use the new pinctrl driver, the pinctrl setup will be done
by device probe. Remove the pinctrl setup at rk3288-board-spl.
Signed-off-by: David Wu
Reviewed-by: Philipp Tomsich
---
Changes in v2: None
arch/arm/mach-rockchip/rk3288-board-spl.c | 79 ---
1 file changed, 79 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index abd62e520f..9463b255e1 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -77,45 +77,6 @@ fallback:
return BOOT_DEVICE_MMC1;
}
-#ifdef CONFIG_SPL_MMC_SUPPORT
-static int configure_emmc(struct udevice *pinctrl)
-{
-#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
-
- struct gpio_desc desc;
- int ret;
-
- pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
-
- /*
-* TODO(s...@chromium.org): Pick this up from device tree or perhaps
-* use the EMMC_PWREN setting.
-*/
- ret = dm_gpio_lookup_name("D9", &desc);
- if (ret) {
- debug("gpio ret=%d\n", ret);
- return ret;
- }
- ret = dm_gpio_request(&desc, "emmc_pwren");
- if (ret) {
- debug("gpio_request ret=%d\n", ret);
- return ret;
- }
- ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
- if (ret) {
- debug("gpio dir ret=%d\n", ret);
- return ret;
- }
- ret = dm_gpio_set_value(&desc, 1);
- if (ret) {
- debug("gpio value ret=%d\n", ret);
- return ret;
- }
-#endif
- return 0;
-}
-#endif
-
#if !defined(CONFIG_SPL_OF_PLATDATA)
static int phycore_init(void)
{
@@ -144,7 +105,6 @@ static int phycore_init(void)
void board_init_f(ulong dummy)
{
- struct udevice *pinctrl;
struct udevice *dev;
int ret;
@@ -183,12 +143,6 @@ void board_init_f(ulong dummy)
return;
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- debug("Pinctrl init failed: %d\n", ret);
- return;
- }
-
#if !defined(CONFIG_SPL_OF_PLATDATA)
if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
ret = phycore_init();
@@ -239,52 +193,19 @@ static int setup_led(void)
void spl_board_init(void)
{
- struct udevice *pinctrl;
int ret;
ret = setup_led();
-
if (ret) {
debug("LED ret=%d\n", ret);
hang();
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- debug("%s: Cannot find pinctrl device\n", __func__);
- goto err;
- }
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
- if (ret) {
- debug("%s: Failed to set up SD card\n", __func__);
- goto err;
- }
- ret = configure_emmc(pinctrl);
- if (ret) {
- debug("%s: Failed to set up eMMC\n", __func__);
- goto err;
- }
-#endif
-
- /* Enable debug UART */
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
- if (ret) {
- debug("%s: Failed to set up console UART\n", __func__);
- goto err;
- }
-
preloader_console_init();
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
return;
-err:
- printf("spl_board_init: Error %d\n", ret);
-
- /* No way to report error here */
- hang();
}
#ifdef CONFIG_SPL_OS_BOOT
--
2.19.1
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[U-Boot] [PATCH v2 5/9] rk3288: chrome: defconfig: Enable FDT for new pinctrl driver
The FDT is requested for new pinctrl driver, disable SPL_OF_PLATDATA and enable SPL_OF_LIBFDT to make FDT be built in. Signed-off-by: David Wu --- Changes in v2: None configs/chromebit_mickey_defconfig | 2 -- configs/chromebook_jerry_defconfig | 2 -- configs/chromebook_minnie_defconfig | 2 -- 3 files changed, 6 deletions(-) diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 79ab6acaec..5fbb5a4ebc 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -38,7 +38,6 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -93,4 +92,3 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y -# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index d892d65bf0..f6f0697050 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -40,7 +40,6 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -95,4 +94,3 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y -# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index b042874073..705a3cd0e5 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -39,7 +39,6 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -95,4 +94,3 @@ CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y -# CONFIG_SPL_OF_LIBFDT is not set -- 2.19.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 6/9] pinctrl: rockchip: Add common rockchip pinctrl driver
Use this driver to fit all Rockchip SOCs and to support the desired pinctrl configuration via DTS. Signed-off-by: David Wu --- Changes in v2: - Remove px30, rk2928, rk3066*. - Split it to multiple files for the relevant per-SoC data structures. drivers/pinctrl/Kconfig | 91 +- drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/rockchip/Kconfig | 17 + drivers/pinctrl/rockchip/Makefile | 19 +- drivers/pinctrl/rockchip/pinctrl-rk3036.c | 65 ++ drivers/pinctrl/rockchip/pinctrl-rk3128.c | 155 drivers/pinctrl/rockchip/pinctrl-rk3188.c | 82 ++ drivers/pinctrl/rockchip/pinctrl-rk322x.c | 215 + drivers/pinctrl/rockchip/pinctrl-rk3288.c | 157 drivers/pinctrl/rockchip/pinctrl-rk3328.c | 227 + drivers/pinctrl/rockchip/pinctrl-rk3368.c | 116 +++ drivers/pinctrl/rockchip/pinctrl-rk3399.c | 193 + .../pinctrl/rockchip/pinctrl-rockchip-core.c | 788 ++ drivers/pinctrl/rockchip/pinctrl-rockchip.h | 302 +++ drivers/pinctrl/rockchip/pinctrl-rv1108.c | 203 + 15 files changed, 2532 insertions(+), 100 deletions(-) create mode 100644 drivers/pinctrl/rockchip/Kconfig create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3036.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3128.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3188.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk322x.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3288.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3328.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3368.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3399.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rockchip-core.c create mode 100644 drivers/pinctrl/rockchip/pinctrl-rockchip.h create mode 100644 drivers/pinctrl/rockchip/pinctrl-rv1108.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 7e6fad305a..d2168f7b72 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -158,96 +158,6 @@ config PINCTRL_QCA953X the GPIO definitions and pin control functions for each available multiplex function. -config PINCTRL_ROCKCHIP_RK3036 - bool "Rockchip rk3036 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3036 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3128 - bool "Rockchip rk3128 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3128 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3188 - bool "Rockchip rk3188 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3188 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK322X - bool "Rockchip rk322x pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk322x SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3288 - bool "Rockchip rk3288 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3288 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3328 - bool "Rockchip rk3328 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3328 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3368 - bool "Rockchip RK3368 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3368 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3399 - bool "Rockchip rk3399 pin control dr
[U-Boot] [PATCH v2 7/9] rockchip: defconfig: Clean the unused pinctrl config
If we used the pinctrl-rockchip driver, these config is not needed, so remove them. Signed-off-by: David Wu --- Changes in v2: None configs/chromebit_mickey_defconfig | 2 -- configs/chromebook_jerry_defconfig | 2 -- configs/chromebook_minnie_defconfig | 2 -- configs/evb-px5_defconfig | 1 - configs/evb-rk3128_defconfig| 1 - configs/evb-rk3229_defconfig| 1 - configs/evb-rk3288_defconfig| 2 -- configs/evb-rk3399_defconfig| 1 - configs/evb-rv1108_defconfig| 1 - configs/fennec-rk3288_defconfig | 2 -- configs/firefly-rk3288_defconfig| 2 -- configs/firefly-rk3399_defconfig| 1 - configs/geekbox_defconfig | 1 - configs/kylin-rk3036_defconfig | 1 - configs/lion-rk3368_defconfig | 1 - configs/miqi-rk3288_defconfig | 2 -- configs/phycore-rk3288_defconfig| 2 -- configs/popmetal-rk3288_defconfig | 2 -- configs/puma-rk3399_defconfig | 1 - configs/rock2_defconfig | 2 -- configs/rock_defconfig | 1 - configs/sandbox_defconfig | 2 -- configs/sandbox_flattree_defconfig | 2 -- configs/sandbox_noblk_defconfig | 2 -- configs/sheep-rk3368_defconfig | 1 - configs/tinker-rk3288_defconfig | 2 -- configs/vyasa-rk3288_defconfig | 2 -- 27 files changed, 42 deletions(-) diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 5fbb5a4ebc..2b3e7b409a 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -61,8 +61,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index f6f0697050..d8db223e90 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -63,8 +63,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 705a3cd0e5..ee92a22e18 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -62,8 +62,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index c3bda3bf3b..1d428e7ac8 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -22,7 +22,6 @@ CONFIG_CLK=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3368=y CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig index 044e60735a..17ad6ae58d 100644 --- a/configs/evb-rk3128_defconfig +++ b/configs/evb-rk3128_defconfig @@ -31,7 +31,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3128=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 0cc92a3314..14ff54af20 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -44,7 +44,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK322X=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=150 diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 1485844aa6..4bf548790c 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -57,8 +57,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_FULL is not set -CONFIG_PINCTRL_ROCKCHIP_RK3288=y CONFIG_DM_PMIC=y CONFIG_PMIC_ACT8846=y CONFIG_REGULATOR_ACT8846=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 27cf8304be..9746755f1e 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -49,7 +49,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RK3399=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index 2ef041f2c5..7836a772e2 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -37,7 +37,6 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y -CONFIG_PINCTRL_ROCKCHIP_RV1108=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_BAUDRATE=150
[U-Boot] [PATCH v2 9/9] ARM: dts: rk322x: Correct the uart2 default pin configuration
To match the iomux setting of uart2 at SPL, correct the uart2
default pin configuration, if not changed, the evb-rk3229 can't
output the log message.
Signed-off-by: David Wu
---
Changes in v2: None
arch/arm/dts/rk322x.dtsi | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
index be026b0e07..4a8be5dabb 100644
--- a/arch/arm/dts/rk322x.dtsi
+++ b/arch/arm/dts/rk322x.dtsi
@@ -206,7 +206,7 @@
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
- pinctrl-0 = <&uart2_xfer>;
+ pinctrl-0 = <&uart21_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -748,7 +748,7 @@
uart2 {
uart2_xfer: uart2-xfer {
- rockchip,pins = <1 RK_PC2 RK_FUNC_2
&pcfg_pull_none>,
+ rockchip,pins = <1 RK_PC2 RK_FUNC_2
&pcfg_pull_up>,
<1 RK_PC3 RK_FUNC_2
&pcfg_pull_none>;
};
@@ -760,6 +760,13 @@
rockchip,pins = <0 RK_PD0 RK_FUNC_1
&pcfg_pull_none>;
};
};
+
+ uart2-1 {
+ uart21_xfer: uart21-xfer {
+ rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
+ <1 9 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
};
dmc: dmc@1120 {
--
2.19.1
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Re: [U-Boot] [PATCH v2 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
Hi Heiko,
在 2019/1/6 上午1:17, Heiko Stuebner 写道:
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c
b/arch/arm/mach-rockchip/rk3188-board-spl.c
index 3c6c3d3c09..a5e4d39cb7 100644
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -120,7 +120,7 @@ void board_debug_uart_init(void)
void board_init_f(ulong dummy)
{
- struct udevice *pinctrl, *dev;
+ struct udevice *dev;
int ret;
#define EARLY_UART
@@ -134,10 +134,7 @@ void board_init_f(ulong dummy)
* printascii("string");
*/
debug_uart_init();
- printch('s');
- printch('p');
- printch('l');
- printch('\n');
+ printascii("U-Boot SPL board init");
Did you test this change?
I remember rk3188 having issues (aka hanging) when trying to print
strings through the debug uart and only printch working at all.
(Timer issue or so?) ... Not sure if this got fixed in the meantime?
I don't know there was a issue, but i test it on the Radxa board today,
it looks okay.
U-Boot SPL board init
U-Boot SPL 2019.01-rc1-9-gdd7b9156fe (Jan 14 2019 - 19:53:50 +0800)
Returning to boot ROM...
U-Boot 2019.01-rc1-9-gdd7b9156fe (Jan 14 2019 - 19:53:50 +0800)
Model: Radxa Rock
DRAM: 2 GiB
MMC: dwmmc@10214000: 0
Loading Environment from MMC... Card did not respond to voltage select!
*** Warning - No block device, using default environment
In:serial@20064000
Out: serial@20064000
Err: serial@20064000
Model: Radxa Rock
rockchip_dnl_key_pressed: adc_channel_single_shot fail!
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0
=>
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[U-Boot] rockchip: rk3288: grf: FIX the correct gmac tx_delay shift
If the tx_delay is not enabled, the RGMII/1000M can't work.
Signed-off-by: David Wu
---
arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
index 1a7c819..6e5a947 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -813,7 +813,7 @@ enum {
(1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
RK3288_TXCLK_DLY_ENA_GMAC_ENABLE =
- (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
+ (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
RK3288_CLK_RX_DL_CFG_GMAC_MASK =
--
1.9.1
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Re: [U-Boot] [U-Boot, 01/14] net: rockchip: Separate rmii and rgmii speed setup
Hi Philipp,
在 2018年02月19日 03:36, Philipp Tomsich 写道:
On Sat, 3 Feb 2018, David Wu wrote:
Some Socs both have rgmii and rmii interface, so we need to
separate their speed setting.
Signed-off-by: David Wu
Acked-by: Philipp Tomsich
---
drivers/net/gmac_rockchip.c | 62
+++--
1 file changed, 43 insertions(+), 19 deletions(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 683e820..4396ca1 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -40,7 +40,10 @@ struct gmac_rockchip_platdata {
};
struct rk_gmac_ops {
- int (*fix_mac_speed)(struct dw_eth_dev *priv);
+ int (*fix_rmii_speed)(struct gmac_rockchip_platdata *pdata,
+ struct dw_eth_dev *priv);
+ int (*fix_rgmii_speed)(struct gmac_rockchip_platdata *pdata,
+ struct dw_eth_dev *priv);
Why can't this be a single fix_mac_speed function that does the right
thing both for RMII and RGMII depending on the platdata?
I think this part is similar to the kernel code, and it's better to
maintain.
void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
};
@@ -70,7 +73,8 @@ static int gmac_rockchip_ofdata_to_platdata(struct
udevice *dev)
return designware_eth_ofdata_to_platdata(dev);
}
-static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata
*pdata,
+ struct dw_eth_dev *priv)
{
struct rk322x_grf *grf;
int clk;
@@ -103,7 +107,8 @@ static int rk3228_gmac_fix_mac_speed(struct
dw_eth_dev *priv)
return 0;
}
-static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3288_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata
*pdata,
+ struct dw_eth_dev *priv)
{
struct rk3288_grf *grf;
int clk;
@@ -129,7 +134,8 @@ static int rk3288_gmac_fix_mac_speed(struct
dw_eth_dev *priv)
return 0;
}
-static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata
*pdata,
+ struct dw_eth_dev *priv)
{
struct rk3328_grf_regs *grf;
int clk;
@@ -162,7 +168,8 @@ static int rk3328_gmac_fix_mac_speed(struct
dw_eth_dev *priv)
return 0;
}
-static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3368_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata
*pdata,
+ struct dw_eth_dev *priv)
{
struct rk3368_grf *grf;
int clk;
@@ -194,7 +201,8 @@ static int rk3368_gmac_fix_mac_speed(struct
dw_eth_dev *priv)
return 0;
}
-static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3399_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata
*pdata,
+ struct dw_eth_dev *priv)
{
struct rk3399_grf_regs *grf;
int clk;
@@ -220,7 +228,8 @@ static int rk3399_gmac_fix_mac_speed(struct
dw_eth_dev *priv)
return 0;
}
-static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
+static int rv1108_gmac_fix_rmii_speed(struct gmac_rockchip_platdata
*pdata,
+ struct dw_eth_dev *priv)
{
struct rv1108_grf *grf;
int clk, speed;
@@ -489,7 +498,7 @@ static int gmac_rockchip_probe(struct udevice *dev)
break;
default:
- debug("NO interface defined!\n");
+ debug("%s: NO interface defined!\n", __func__);
return -ENXIO;
}
@@ -498,18 +507,33 @@ static int gmac_rockchip_probe(struct udevice *dev)
static int gmac_rockchip_eth_start(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct eth_pdata *eth_pdata = dev_get_platdata(dev);
struct dw_eth_dev *priv = dev_get_priv(dev);
struct rk_gmac_ops *ops =
(struct rk_gmac_ops *)dev_get_driver_data(dev);
+ struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
int ret;
- ret = designware_eth_init(priv, pdata->enetaddr);
- if (ret)
- return ret;
- ret = ops->fix_mac_speed(priv);
+ ret = designware_eth_init(priv, eth_pdata->enetaddr);
if (ret)
return ret;
+
+ switch (eth_pdata->phy_interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ ret = ops->fix_rgmii_speed(pdata, priv);
+ if (ret)
+ return ret;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ ret = ops->fix_rmii_speed(pdata, priv);
+ if (ret)
+ return ret;
+ break;
Looking at this, the fix_mac_speed()-function could look into pdata to
determine what needs to be done... no need to complicate the common code
path with this.
+ default:
+ debug("%s: NO interface defined!\n", __func__);
+ return -ENXIO;
+ }
+
ret = designware_eth_enable(priv);
if (ret)
return ret;
@@ -527,32 +551,32 @@ const struct eth_
Re: [U-Boot] [U-Boot, 10/14] ARM: dts: rockchip: Enable integrated phy support for rk3229-evb
Hi Philipp,
在 2018年02月19日 03:38, Philipp Tomsich 写道:
On Sat, 3 Feb 2018, David Wu wrote:
In fact, the evb-rk3229 is default supported the integrated phy,
not need to change any hardware. So it is better to enbale it and
disable external 1000M phy.
Signed-off-by: David Wu
Acked-by: Philipp Tomsich
---
arch/arm/dts/rk3229-evb.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts
index ae0b0a4..547c7a2 100644
--- a/arch/arm/dts/rk3229-evb.dts
+++ b/arch/arm/dts/rk3229-evb.dts
@@ -63,7 +63,29 @@
snps,reset-delays-us = <0 1 100>;
tx_delay = <0x30>;
rx_delay = <0x10>;
+ status = "disabled";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_MAC_SRC>;
+ assigned-clock-rates = <5000>;
+ clock_in_out = "output";
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rmii";
+ phy-handle = <&phy>;
status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: phy@0 {
+ compatible = "ethernet-phy-id1234.d400",
"ethernet-phy-ieee802.3-c22";
Where is "ethernet-phy-id1234.d400" defined/used? I don't see anything
in Linux or U-Boot.
Yes, The "ethernet-phy-id1234.d400" is not defined at linux/U-Boot.
It does use the "ethernet-phy-ieee802.3-c22". The
"ethernet-phy-id1234.d400" is a decorated aliases, the 0x1234d0 is the
phy-id.
+ reg = <0>;
+ phy-is-integrated;
Documentation in the documentation for DTS bindings?
Shouldn't this be rockchip,phy-is-integrated?
What is the status of this on the Linux side?
I think it's consistent with kernel, especially if we might use kernel
DTB file.
+ };
+ };
};
&emmc {
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Re: [U-Boot] [U-Boot, 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
Hi Philipp,
在 2018年02月19日 03:00, Philipp Tomsich 写道:
On Sat, 3 Feb 2018, David Wu wrote:
When the boot ROM sets up MMC we don't need to do it again. Remove the
MMC setup code entirely, but we also need to enable uart for debug
message.
If the MMC always set up correctly for all configurations (e.g. bus-width)
or should some of the setup be duplicated there to ensure that we catch
all corner cases?
For this, I will do a check if we need to setup duplicated.
Signed-off-by: David Wu
Acked-by: Philipp Tomsich
---
arch/arm/mach-rockchip/rk3188-board-spl.c | 42
+++
1 file changed, 3 insertions(+), 39 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c
b/arch/arm/mach-rockchip/rk3188-board-spl.c
index 8e3b8ae..8371a31 100644
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -100,10 +100,11 @@ static int setup_arm_clock(void)
void board_init_f(ulong dummy)
{
- struct udevice *pinctrl, *dev;
+ struct udevice *dev;
int ret;
/* Example code showing how to enable the debug UART on RK3188 */
+#define EARLY_UART
#ifdef EARLY_UART
#include
/* Enable early UART on the RK3188 */
@@ -124,10 +125,7 @@ void board_init_f(ulong dummy)
* printascii("string");
*/
debug_uart_init();
- printch('s');
- printch('p');
- printch('l');
- printch('\n');
+ printascii("U-Boot SPL board init");
#endif
ret = spl_early_init();
@@ -144,12 +142,6 @@ void board_init_f(ulong dummy)
return;
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- debug("Pinctrl init failed: %d\n", ret);
- return;
- }
-
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
debug("DRAM init failed: %d\n", ret);
@@ -187,7 +179,6 @@ static int setup_led(void)
void spl_board_init(void)
{
- struct udevice *pinctrl;
int ret;
ret = setup_led();
@@ -196,36 +187,9 @@ void spl_board_init(void)
hang();
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- debug("%s: Cannot find pinctrl device\n", __func__);
- goto err;
- }
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
- if (ret) {
- debug("%s: Failed to set up SD card\n", __func__);
- goto err;
- }
-#endif
-
- /* Enable debug UART */
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
- if (ret) {
- debug("%s: Failed to set up console UART\n", __func__);
- goto err;
- }
-
preloader_console_init();
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
return;
-
-err:
- printf("spl_board_init: Error %d\n", ret);
-
- /* No way to report error here */
- hang();
}
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Re: [U-Boot] [U-Boot, 6/9] pinctrl: rockchip: Add common rockchip pinctrl driver
Hi Philipp, Okay, each SOC should have its own file, which include private data structure, and probe(). Can reduce driver size. 在 2018年02月19日 03:20, Philipp Tomsich 写道: On Sat, 3 Feb 2018, David Wu wrote: Use this driver to fit all Rockchip SOCs and to support the desired pinctrl configuration via DTS. Please split this into multiple comments (and possibly multiple files) for the relevant per-SoC data structures. I'd like this to be multiple commits to add the individual data structures for each of the SOCs. We had the fundamental discussion of how to deal with drivers that require additional config-structures and code for some SOCs in the HDMI/VOP context and we should follow the same here. Signed-off-by: David Wu Reviewed-by: Kever Yang Tested-by: Kever Yang Acked-by: Philipp Tomsich --- drivers/pinctrl/Kconfig | 98 +- drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/pinctrl-rockchip.c | 2440 3 files changed, 2454 insertions(+), 86 deletions(-) create mode 100644 drivers/pinctrl/pinctrl-rockchip.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 7e8e4b0..6177e7c 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -158,95 +158,23 @@ config PINCTRL_QCA953X the GPIO definitions and pin control functions for each available multiplex function. -config PINCTRL_ROCKCHIP_RK3036 - bool "Rockchip rk3036 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3036 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3128 - bool "Rockchip rk3128 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3128 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3188 - bool "Rockchip rk3188 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3188 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK322X - bool "Rockchip rk322x pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk322x SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3288 - bool "Rockchip rk3288 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3288 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3328 - bool "Rockchip rk3328 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3328 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3368 - bool "Rockchip RK3368 pin control driver" - depends on DM - help - Support pin multiplexing control on Rockchip rk3368 SoCs. - - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. - -config PINCTRL_ROCKCHIP_RK3399 - bool "Rockchip rk3399 pin control driver" - depends on DM +config PINCTRL_ROCKCHIP + bool "Rockchip pin control driver" + depends on PINCTRL_FULL + default y help - Support pin multiplexing control on Rockchip rk3399 SoCs. + Support pin multiplexing control on Rockchip SoCs. - The driver is controlled by a device tree node which contains both - the GPIO definitions and pin control functions for each available - multiplex function. + The driver is controlled by a device tree node which contains pin + control functions for each available multiplex function. -config PINCTRL_ROCKCHIP_RV1108 - bool "Rockchip rv1108 pin control driver" - depends on DM +config SPL_PINCTRL_ROCKCHIP + bool "Support Rockchip pin controllers in SPL" + depends on SPL_PINCTRL_FULL + default y help - Support pin multiplexing control on Rockchip rv1108 SoC. - - The driver is controlled by a device tree node whi
[U-Boot] rockchip: rk322x: Disable integrated macphy for saving power consuming
Unfortunately, the integrated macphy default is enabled, which will
increase power consuming, if we do not use this PHY. So let's disable
it at first, which will save power consuming. If we really use it, then
enable it in driver level.
Signed-off-by: David Wu
---
arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 32 +
arch/arm/mach-rockchip/rk322x-board.c | 8 +++
2 files changed, 40 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
index 26071c8..c0c0d84 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
@@ -54,6 +54,32 @@ struct rk322x_grf {
unsigned int os_reg[8];
unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1];
unsigned int ddrc_stat;
+ unsigned int reserved10[(0x680 - 0x604) / 4 - 1];
+ unsigned int sig_detect_con[2];
+ unsigned int reserved11[(0x690 - 0x684) / 4 - 1];
+ unsigned int sig_detect_status[2];
+ unsigned int reserved12[(0x6a0 - 0x694) / 4 - 1];
+ unsigned int sig_detect_clr[2];
+ unsigned int reserved13[(0x6b0 - 0x6a4) / 4 - 1];
+ unsigned int emmc_det;
+ unsigned int reserved14[(0x700 - 0x6b0) / 4 - 1];
+ unsigned int host0_con[3];
+ unsigned int reserved15;
+ unsigned int host1_con[3];
+ unsigned int reserved16;
+ unsigned int host2_con[3];
+ unsigned int reserved17[(0x760 - 0x728) / 4 - 1];
+ unsigned int usbphy0_con[27];
+ unsigned int reserved18[(0x800 - 0x7c8) / 4 - 1];
+ unsigned int usbphy1_con[27];
+ unsigned int reserved19[(0x880 - 0x868) / 4 - 1];
+ unsigned int otg_con0;
+ unsigned int uoc_status0;
+ unsigned int reserved20[(0x900 - 0x884) / 4 - 1];
+ unsigned int mac_con[2];
+ unsigned int reserved21[(0xb00 - 0x904) / 4 - 1];
+ unsigned int macphy_con[4];
+ unsigned int macphy_status;
};
check_member(rk322x_grf, ddrc_stat, 0x604);
@@ -516,4 +542,10 @@ enum {
CON_IOMUX_PWM0SEL_SHIFT = 0,
CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
};
+
+/* GRF_MACPHY_CON0 */
+enum {
+ MACPHY_CFG_ENABLE_SHIFT = 0,
+ MACPHY_CFG_ENABLE_MASK = 1 << MACPHY_CFG_ENABLE_SHIFT,
+};
#endif
diff --git a/arch/arm/mach-rockchip/rk322x-board.c
b/arch/arm/mach-rockchip/rk322x-board.c
index b6543a5..c8e6c6c 100644
--- a/arch/arm/mach-rockchip/rk322x-board.c
+++ b/arch/arm/mach-rockchip/rk322x-board.c
@@ -67,6 +67,14 @@ int board_init(void)
CON_IOMUX_UART2SEL_MASK,
CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
+ /*
+ * The integrated macphy is enabled by default, disable it
+ * for saving power consuming.
+ */
+ rk_clrsetreg(&grf->macphy_con[0],
+MACPHY_CFG_ENABLE_MASK,
+0 << MACPHY_CFG_ENABLE_SHIFT);
+
return 0;
}
--
1.9.1
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[U-Boot] [PATCH v2 00/18] Add gmac support for rk3399-evb rv1108-evb rk3328-evb and rk3229-evb
This serie of patches add rmii interface support, and support more socs's gmac function, such as rv1108, rk3328 and rk3229. Changes in v2: - New patch - New patch - Add check whether the set rgmii/rmii function is a valid function pointer - Use current phy interface to set mac clock rate - Clean the grf offset at gmac_rockchip.c - New patch - New patch - New patch - New patch - New patch - New patch - New patch - New patch - New patch - New patch - New patch - New patch David Wu (18): rockchip: clk: Add mac clock set for rk3399 rockchip: dts: rk3399-evb: Change the tx/rx delay value for transmission quality rockchip: configs: Enable CONFIG_NET_RANDOM_ETHADDR for rk3288-evb rockchip: grf_rv1108.h: Fix the grf offsets rockchip: pinctrl: rv1108: Move the iomux definitions into pinctrl-driver net: gmac_rockchip: Add support for the RV1108 GMAC rockchip: pinctrl: rk3328: Move the iomux definitions into pinctrl-driver rockchip: pinctrl: Add rk3328 gmac pinctrl support clk: rockchip: Add rk3328 gamc clock support net: gmac_rockchip: Add rk3328 gmac support rockchip: configs: Enable GMAC configs for evb-rk3328 rockchip: dts: rk3328: Add gmac2io support rockchip: dts: rk3328-evb: Enable gmac2io for rk3328-evb rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driver rockchip: pinctrl: Add rk322x gmac pinctrl support clk: rockchip: Add rk322x gamc clock support net: gmac_rockchip: Add support for the RK3228 GMAC config: evb-rk3229: Enable rk gmac configs arch/arm/dts/rk3328-evb.dts | 30 ++ arch/arm/dts/rk3328.dtsi| 19 + arch/arm/dts/rk3399-evb.dts | 4 +- arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 455 -- arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 113 - arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 405 +--- arch/arm/mach-rockchip/rk322x-board-spl.c | 20 +- arch/arm/mach-rockchip/rk322x-board.c | 16 + board/rockchip/evb_rv1108/evb_rv1108.c | 15 + configs/evb-rk3229_defconfig| 5 + configs/evb-rk3288_defconfig| 1 + configs/evb-rk3328_defconfig| 5 + drivers/clk/rockchip/clk_rk322x.c | 13 + drivers/clk/rockchip/clk_rk3328.c | 20 + drivers/clk/rockchip/clk_rk3399.c | 21 +- drivers/net/gmac_rockchip.c | 259 ++- drivers/pinctrl/rockchip/pinctrl_rk322x.c | 591 drivers/pinctrl/rockchip/pinctrl_rk3328.c | 380 +++ drivers/pinctrl/rockchip/pinctrl_rv1108.c | 399 include/dt-bindings/clock/rk3328-cru.h | 6 +- 20 files changed, 1794 insertions(+), 983 deletions(-) -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 01/18] rockchip: clk: Add mac clock set for rk3399
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Content preview: Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface. Signed-off-by:
David Wu Acked-by: Philipp Tomsich
Reviewed-by: Philipp Tomsich ---
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--- Begin Message ---
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.
Signed-off-by: David Wu
Acked-by: Philipp Tomsich
Reviewed-by: Philipp Tomsich
---
Changes in v2: None
drivers/clk/rockchip/clk_rk3399.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/clk/rockchip/clk_rk3399.c
index 6f85a38..93aa4ff 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -143,6 +143,14 @@ enum {
ACLK_PERIHP_DIV_CON_SHIFT = 0,
ACLK_PERIHP_DIV_CON_MASK= 0x1f,
+ /* CLKSEL_CON19 */
+ MAC_DIV_CON_SHIFT = 8,
+ MAC_DIV_CON_MASK= GENMASK(10, 8),
+ RMII_EXTCLK_SHIFT = 4,
+ RMII_EXTCLK_MASK= BIT(4),
+ RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
+ RMII_EXTCLK_SELECT_EXT_CLK = BIT(4),
+
/* CLKSEL_CON21 */
ACLK_EMMC_PLL_SEL_SHIFT = 7,
ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
@@ -785,6 +793,16 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
return set_rate;
}
+static int rockchip_mac_set_clk(struct rk3399_cru *cru,
+ int periph, uint freq)
+{
+ /* Assuming mac_clk is fed by an external clock */
+ rk_clrsetreg(&cru->clksel_con[19], RMII_EXTCLK_MASK,
+RMII_EXTCLK_SELECT_EXT_CLK);
+
+ return 0;
+}
+
static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
{
u32 div, val;
@@ -869,8 +887,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong
rate)
ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
break;
case SCLK_MAC:
- /* nothing to do, as this is an external clock */
- ret = rate;
+ ret = rockchip_mac_set_clk(priv->cru, clk->id, rate);
break;
case SCLK_I2C1:
case SCLK_I2C2:
--
2.7.4
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[U-Boot] [PATCH v2 02/18] rockchip: dts: rk3399-evb: Change the tx/rx delay value for transmission quality
Spam detection software, running on the system "lists.denx.de", has identified this incoming email as possible spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see @@CONTACT_ADDRESS@@ for details. Content preview: Give the mac controller the correct tx-delay and rx-delay value for the rgmii mode transmission. If they are not matched, there would be Ethernet packets lost, the net feature may not work. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- [...] Content analysis details: (5.7 points, 5.0 required) pts rule name description -- -- 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL [211.157.147.130 listed in psbl.surriel.com] 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5) [211.157.147.130 listed in bl.mailspike.net] 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted --- Begin Message --- Give the mac controller the correct tx-delay and rx-delay value for the rgmii mode transmission. If they are not matched, there would be Ethernet packets lost, the net feature may not work. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: None arch/arm/dts/rk3399-evb.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index 0e5d8d7..ed5ef88 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -276,7 +276,7 @@ assigned-clock-parents = <&clkin_gmac>; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x10>; - rx_delay = <0x10>; + tx_delay = <0x28>; + rx_delay = <0x11>; status = "okay"; }; -- 2.7.4 --- End Message --- ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 03/18] rockchip: configs: Enable CONFIG_NET_RANDOM_ETHADDR for rk3288-evb
If the Ethernet address is not set, the network can't work, enable the random address config for default use. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: None configs/evb-rk3288_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index e944f97..6c67509 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 04/18] rockchip: grf_rv1108.h: Fix the grf offsets
The last 4 grf registers offset of rv1108 are wrong, fix them
for correct usage.
Signed-off-by: David Wu
---
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
index c816a5b..428cf6a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
@@ -100,13 +100,17 @@ struct rv1108_grf {
u32 reserved14[2];
u32 dma_con0;
u32 dma_con1;
- u32 reserved15[539];
+ u32 reserved15[59];
u32 uoc_status;
+ u32 reserved16[2];
u32 host_status;
+ u32 reserved17[59];
u32 gmac_con0;
+ u32 reserved18[191];
u32 chip_id;
};
-check_member(rv1108_grf, chip_id, 0xf90);
+
+check_member(rv1108_grf, chip_id, 0x0c00);
/* GRF_GPIO1B_IOMUX */
enum {
--
2.7.4
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[U-Boot] [PATCH v2 05/18] rockchip: pinctrl: rv1108: Move the iomux definitions into pinctrl-driver
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Content preview: If we include both the rk3288_grf.h and rv1108_grf.h, it will
cause the conflicts of redefinition. Clean the iomux definitions at
grf_rv1108.h,
and move them into pinctrl-driver. Signed-off-by: David Wu
--- [...]
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--- Begin Message ---
If we include both the rk3288_grf.h and rv1108_grf.h, it will cause the
conflicts of redefinition. Clean the iomux definitions at grf_rv1108.h,
and move them into pinctrl-driver.
Signed-off-by: David Wu
---
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 399
board/rockchip/evb_rv1108/evb_rv1108.c | 15 +
drivers/pinctrl/rockchip/pinctrl_rv1108.c | 399
3 files changed, 414 insertions(+), 399 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
index 428cf6a..76e742b 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
@@ -111,403 +111,4 @@ struct rv1108_grf {
};
check_member(rv1108_grf, chip_id, 0x0c00);
-
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK= 3 << GPIO1B7_SHIFT,
- GPIO1B7_GPIO= 0,
- GPIO1B7_LCDC_D12,
- GPIO1B7_I2S_SDIO2_M0,
- GPIO1B7_GMAC_RXDV,
-
- GPIO1B6_SHIFT = 12,
- GPIO1B6_MASK= 3 << GPIO1B6_SHIFT,
- GPIO1B6_GPIO= 0,
- GPIO1B6_LCDC_D13,
- GPIO1B6_I2S_LRCLKTX_M0,
- GPIO1B6_GMAC_RXD1,
-
- GPIO1B5_SHIFT = 10,
- GPIO1B5_MASK= 3 << GPIO1B5_SHIFT,
- GPIO1B5_GPIO= 0,
- GPIO1B5_LCDC_D14,
- GPIO1B5_I2S_SDIO1_M0,
- GPIO1B5_GMAC_RXD0,
-
- GPIO1B4_SHIFT = 8,
- GPIO1B4_MASK= 3 << GPIO1B4_SHIFT,
- GPIO1B4_GPIO= 0,
- GPIO1B4_LCDC_D15,
- GPIO1B4_I2S_MCLK_M0,
- GPIO1B4_GMAC_TXEN,
-
- GPIO1B3_SHIFT = 6,
- GPIO1B3_MASK= 3 << GPIO1B3_SHIFT,
- GPIO1B3_GPIO= 0,
- GPIO1B3_LCDC_D16,
- GPIO1B3_I2S_SCLK_M0,
- GPIO1B3_GMAC_TXD1,
-
- GPIO1B2_SHIFT = 4,
- GPIO1B2_MASK= 3 << GPIO1B2_SHIFT,
- GPIO1B2_GPIO= 0,
- GPIO1B2_LCDC_D17,
- GPIO1B2_I2S_SDIO_M0,
- GPIO1B2_GMAC_TXD0,
-
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK= 3 << GPIO1B1_SHIFT,
- GPIO1B1_GPIO= 0,
- GPIO1B1_LCDC_D9,
- GPIO1B1_PWM7,
-
- GPIO1B0_SHIFT = 0,
- GPIO1B0_MASK= 3,
- GPIO1B0_GPIO= 0,
- GPIO1B0_LCDC_D8,
- GPIO1B0_PWM6,
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
- GPIO1C7_SHIFT = 14,
- GPIO1C7_MASK= 3 << GPIO1C7_SHIFT,
- GPIO1C7_GPIO= 0,
- GPIO1C7_CIF_D5,
- GPIO1C7_I2S_SDIO2_M1,
-
- GPIO1C6_SHIFT = 12,
- GPIO1C6_MASK= 3 << GPIO1C6_SHIFT,
- GPIO1C6_GPIO= 0,
- GPIO1C6_CIF_D4,
- GPIO1C6_I2S_LRCLKTX_M1,
-
- GPIO1C5_SHIFT = 10,
- GPIO1C5_MASK= 3 << GPIO1C5_SHIFT,
- GPIO1C5_GPIO= 0,
- GPIO1C5_LCDC_CLK,
- GPIO1C5_GMAC_CLK,
-
- GPIO1C4_SHIFT = 8,
- GPIO1C4_MASK= 3 << GPIO1C4_SHIFT,
- GPIO1C4_GPIO= 0,
- GPIO1C4_LCDC_HSYNC,
- GPIO1C4_GMAC_MDC,
-
- GPIO1C3_SHIFT = 6,
- GPIO1C3_MASK= 3 << GPIO1C3_SHIFT,
- GPIO1C3_GPIO= 0,
- GPIO1C3_LCDC_VSYNC,
- GPIO1C3_GMAC_MDIO,
-
- GPIO1C2_SHIFT = 4,
- GPIO1C2_MASK= 3 << GPIO1C2_SHIFT,
- GPIO1C2_GPIO= 0,
- GPIO1C2_LCDC_EN,
- GPIO1C2_I2S_SDIO3_M0,
- GPIO1
[U-Boot] [PATCH v2 06/18] net: gmac_rockchip: Add support for the RV1108 GMAC
The rv1108 GMAC only support rmii interface, so need to add the
set_rmii() ops. Use the phy current interface to set rmii or
rgmii ops. At the same time, need to set the mac clock rate of
rmii with 50M, the clock rate of rgmii with 125M.
Signed-off-by: David Wu
---
Changes in v2:
- Add check whether the set rgmii/rmii function is a valid function pointer
- Use current phy interface to set mac clock rate
- Clean the grf offset at gmac_rockchip.c
drivers/net/gmac_rockchip.c | 89 +
1 file changed, 82 insertions(+), 7 deletions(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 586ccbf..22e3941 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include "designware.h"
@@ -37,6 +38,7 @@ struct gmac_rockchip_platdata {
struct rk_gmac_ops {
int (*fix_mac_speed)(struct dw_eth_dev *priv);
+ void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
};
@@ -142,6 +144,41 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev
*priv)
return 0;
}
+static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
+{
+ struct rv1108_grf *grf;
+ int clk, speed;
+ enum {
+ RV1108_GMAC_SPEED_MASK = BIT(2),
+ RV1108_GMAC_SPEED_10M = 0 << 2,
+ RV1108_GMAC_SPEED_100M = 1 << 2,
+ RV1108_GMAC_CLK_SEL_MASK= BIT(7),
+ RV1108_GMAC_CLK_SEL_2_5M= 0 << 7,
+ RV1108_GMAC_CLK_SEL_25M = 1 << 7,
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RV1108_GMAC_CLK_SEL_2_5M;
+ speed = RV1108_GMAC_SPEED_10M;
+ break;
+ case 100:
+ clk = RV1108_GMAC_CLK_SEL_25M;
+ speed = RV1108_GMAC_SPEED_100M;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->gmac_con0,
+RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
+clk | speed);
+
+ return 0;
+}
+
static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3288_grf *grf;
@@ -221,11 +258,28 @@ static void rk3399_gmac_set_to_rgmii(struct
gmac_rockchip_platdata *pdata)
pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
}
+static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rv1108_grf *grf;
+
+ enum {
+ RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4,
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->gmac_con0,
+RV1108_GMAC_PHY_INTF_SEL_MASK,
+RV1108_GMAC_PHY_INTF_SEL_RMII);
+}
+
static int gmac_rockchip_probe(struct udevice *dev)
{
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
struct rk_gmac_ops *ops =
(struct rk_gmac_ops *)dev_get_driver_data(dev);
+ struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
+ struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata;
struct clk clk;
int ret;
@@ -233,13 +287,27 @@ static int gmac_rockchip_probe(struct udevice *dev)
if (ret)
return ret;
- /* Since mac_clk is fed by an external clock we can use 0 here */
- ret = clk_set_rate(&clk, 0);
- if (ret)
- return ret;
-
- /* Set to RGMII mode */
- ops->set_to_rgmii(pdata);
+ switch (eth_pdata->phy_interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ ret = clk_set_rate(&clk, 12500);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+ /* Set to RGMII mode */
+ if (ops->set_to_rgmii)
+ ops->set_to_rgmii(pdata);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ ret = clk_set_rate(&clk, 5000);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+ /* Set to RMII mode */
+ if (ops->set_to_rmii)
+ ops->set_to_rmii(pdata);
+ break;
+ default:
+ debug("NO interface defined!\n");
+ return -ENXIO;
+ }
return designware_eth_probe(dev);
}
@@ -289,6 +357,11 @@ const struct rk_gmac_ops rk3399_gmac_ops = {
.set_to_rgmii = rk3399_gmac_set_to_rgmii,
};
+const s
