[PATCH v2] rockchip: rk3568: Add support for Lubancat2 board from EmbedFire

[Andy Yan]

LubanCat2 is a rk3568 based SBC from EmbedFire.

Specification:
- Rockchip rk3568
- LPDDR4/4X 1/2/4/8 GB
- TF scard slot
- eMMC 8/32/64/128 GB
- Gigabit ethernet x 2
- HDMI out
- USB 2.0 Host x 1
- USB 2.0 Type-C OTG x 1
- USB 3.0 Host x 1
- Mini PCIE interface for WIFI/BT module
- M.2 key for 2280 NVME
- 40 pin header

The dts file is sync from linux mainline.

Signed-off-by: Andy Yan 

---

Changes in v2:
- enable SPL_FIT_SIGNATURE

 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi |  87 +++
 arch/arm/dts/rk3568-lubancat-2.dts | 734 +
 configs/lubancat-2-rk3568_defconfig|  94 +++
 4 files changed, 917 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3568-lubancat-2.dts
 create mode 100644 configs/lubancat-2-rk3568_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 480269fa60..b177c0c4f9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -169,7 +169,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-anbernic-rgxx3.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb \
-   rk3568-rock-3a.dtb
+   rk3568-rock-3a.dtb \
+   rk3568-lubancat-2.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-edgeble-neu6a-io.dtb \
diff --git a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi 
b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
new file mode 100644
index 00..42072dd0bd
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2023 Andy Yan 
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+   chosen {
+   stdout-path = &uart2;
+   };
+};
+
+&emmc_bus8 {
+   bootph-all;
+};
+
+&emmc_clk {
+   bootph-all;
+};
+
+&emmc_cmd {
+   bootph-all;
+};
+
+&emmc_datastrobe {
+   bootph-all;
+};
+
+&pinctrl {
+   bootph-all;
+};
+
+&pcfg_pull_none {
+   bootph-all;
+};
+
+&pcfg_pull_up_drv_level_2 {
+   bootph-all;
+};
+
+&pcfg_pull_up {
+   bootph-all;
+};
+
+&sdmmc0_bus4 {
+   bootph-all;
+};
+
+&sdmmc0_clk {
+   bootph-all;
+};
+
+&sdmmc0_cmd {
+   bootph-all;
+};
+
+&sdmmc0_det {
+   bootph-all;
+};
+
+&sdhci {
+   cap-mmc-highspeed;
+   mmc-ddr-1_8v;
+   mmc-hs200-1_8v;
+   mmc-hs400-1_8v;
+   mmc-hs400-enhanced-strobe;
+};
+
+&sdmmc2 {
+   status = "disabled";
+};
+
+&uart1 {
+   status = "disabled";
+};
+
+&uart2m0_xfer {
+   bootph-all;
+};
+
+&uart2 {
+   clock-frequency = <2400>;
+   bootph-all;
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-lubancat-2.dts 
b/arch/arm/dts/rk3568-lubancat-2.dts
new file mode 100644
index 00..da257b0591
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2.dts
@@ -0,0 +1,734 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2023 EmbedFire 
+ * Copyright (c) 2023 Andy Yan 
+ */
+
+/dts-v1/;
+#include 
+#include 
+#include 
+#include 
+#include "rk3568.dtsi"
+
+/ {
+   model = "EmbedFire LubanCat 2";
+   compatible = "embedfire,lubancat-2", "rockchip,rk3568";
+
+   aliases {
+   ethernet0 = &gmac0;
+   ethernet1 = &gmac1;
+   mmc0 = &sdmmc0;
+   mmc1 = &sdhci;
+   };
+
+   chosen: chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   user_led: user-led {
+   label = "user_led";
+   linux,default-trigger = "heartbeat";
+   default-state = "on";
+   gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&user_led_pin>;
+   };
+   };
+
+   hdmi-con {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con_in: endpoint {
+   remote-endpoint = <&hdmi_out_con>;
+   };
+   };
+   };
+
+   dc_5v: dc-5v-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "dc_5v";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   };
+
+   vcc3v3_sys: vcc3v3-sys-regulator 

[PATCH v3] rockchip: rk3568: Add EmbedFire Lubancat 2 support

[Andy Yan]

LubanCat2 is a rk3568 based SBC from EmbedFire.

Specification:
- Rockchip rk3568
- LPDDR4/4X 1/2/4/8 GB
- TF scard slot
- eMMC 8/32/64/128 GB
- Gigabit ethernet x 2
- HDMI out
- USB 2.0 Host x 1
- USB 2.0 Type-C OTG x 1
- USB 3.0 Host x 1
- Mini PCIE interface for WIFI/BT module
- M.2 key for 2280 NVME
- 40 pin header

The dts file is sync from linux mainline.

There are some dts bootph-all and USB3 update according to Jonas suggestion[0],
so this patch based on Jonas patch [1] [2].

Signed-off-by: Andy Yan 
[0]:http://patchwork.ozlabs.org/project/uboot/patch/20230708102556.25472-1-andys...@163.com/
[1]:http://patchwork.ozlabs.org/project/uboot/cover/20230728115302.1735429-1-jo...@kwiboo.se/
[2]:http://patchwork.ozlabs.org/project/uboot/cover/20230728124011.1747408-1-jo...@kwiboo.se/

---

Changes in v3:
- some alphabetical order update
- disable all SPI flash related options.
- remove bootph-all for pinctrl
- add emmc_datastrobe pinconfig for hs200/hs400 in u-boot.dtsi
- use USB_DWC3_GENERIC driver as Jonas suggested.
- add CONFIG_SPL_DM_SEQ_ALIAS

Changes in v2:
- enable SPL_FIT_SIGNATURE

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi |  28 +
 arch/arm/dts/rk3568-lubancat-2.dts | 734 +
 configs/lubancat-2-rk3568_defconfig|  87 +++
 4 files changed, 850 insertions(+)
 create mode 100644 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3568-lubancat-2.dts
 create mode 100644 configs/lubancat-2-rk3568_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bd5887bf75..fb139a14fe 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -172,6 +172,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-anbernic-rgxx3.dtb \
rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb \
+   rk3568-lubancat-2.dtb \
rk3568-nanopi-r5c.dtb \
rk3568-nanopi-r5s.dtb \
rk3568-odroid-m1.dtb \
diff --git a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi 
b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
new file mode 100644
index 00..52bd757bd0
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2023 Andy Yan 
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+   chosen {
+   stdout-path = &uart2;
+   };
+};
+
+&sdhci {
+   cap-mmc-highspeed;
+   mmc-ddr-1_8v;
+   mmc-hs200-1_8v;
+   mmc-hs400-1_8v;
+   mmc-hs400-enhanced-strobe;
+   pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+};
+
+&uart2 {
+   bootph-all;
+   clock-frequency = <2400>;
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-lubancat-2.dts 
b/arch/arm/dts/rk3568-lubancat-2.dts
new file mode 100644
index 00..da257b0591
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2.dts
@@ -0,0 +1,734 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2023 EmbedFire 
+ * Copyright (c) 2023 Andy Yan 
+ */
+
+/dts-v1/;
+#include 
+#include 
+#include 
+#include 
+#include "rk3568.dtsi"
+
+/ {
+   model = "EmbedFire LubanCat 2";
+   compatible = "embedfire,lubancat-2", "rockchip,rk3568";
+
+   aliases {
+   ethernet0 = &gmac0;
+   ethernet1 = &gmac1;
+   mmc0 = &sdmmc0;
+   mmc1 = &sdhci;
+   };
+
+   chosen: chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   user_led: user-led {
+   label = "user_led";
+   linux,default-trigger = "heartbeat";
+   default-state = "on";
+   gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&user_led_pin>;
+   };
+   };
+
+   hdmi-con {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con_in: endpoint {
+   remote-endpoint = <&hdmi_out_con>;
+   };
+   };
+   };
+
+   dc_5v: dc-5v-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "dc_5v";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   };
+
+   vcc3v3_sys: vcc3v3-sys-regulator {
+   

Re:Re: [PATCH v3] rockchip: rk3568: Add EmbedFire Lubancat 2 support

[Andy Yan]

Hi Jonas：
  Thanks for you kindly review。












At 2023-07-30 21:22:36, "Jonas Karlman"  wrote:
>Hi Andy,
>
>On 2023-07-29 13:58, Andy Yan wrote:
>> LubanCat2 is a rk3568 based SBC from EmbedFire.
>> 
>> Specification:
>> - Rockchip rk3568
>> - LPDDR4/4X 1/2/4/8 GB
>> - TF scard slot
>> - eMMC 8/32/64/128 GB
>> - Gigabit ethernet x 2
>> - HDMI out
>> - USB 2.0 Host x 1
>> - USB 2.0 Type-C OTG x 1
>> - USB 3.0 Host x 1
>> - Mini PCIE interface for WIFI/BT module
>> - M.2 key for 2280 NVME
>> - 40 pin header
>> 
>> The dts file is sync from linux mainline.
>> 
>> There are some dts bootph-all and USB3 update according to Jonas 
>> suggestion[0],
>> so this patch based on Jonas patch [1] [2].
>> 
>> Signed-off-by: Andy Yan 
>> [0]:http://patchwork.ozlabs.org/project/uboot/patch/20230708102556.25472-1-andys...@163.com/
>> [1]:http://patchwork.ozlabs.org/project/uboot/cover/20230728115302.1735429-1-jo...@kwiboo.se/
>> [2]:http://patchwork.ozlabs.org/project/uboot/cover/20230728124011.1747408-1-jo...@kwiboo.se/
>> 
>> ---
>> 
>> Changes in v3:
>> - some alphabetical order update
>> - disable all SPI flash related options.
>> - remove bootph-all for pinctrl
>> - add emmc_datastrobe pinconfig for hs200/hs400 in u-boot.dtsi
>> - use USB_DWC3_GENERIC driver as Jonas suggested.
>> - add CONFIG_SPL_DM_SEQ_ALIAS
>> 
>> Changes in v2:
>> - enable SPL_FIT_SIGNATURE
>> 
>>  arch/arm/dts/Makefile  |   1 +
>>  arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi |  28 +
>>  arch/arm/dts/rk3568-lubancat-2.dts | 734 +
>>  configs/lubancat-2-rk3568_defconfig|  87 +++
>>  4 files changed, 850 insertions(+)
>>  create mode 100644 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
>>  create mode 100644 arch/arm/dts/rk3568-lubancat-2.dts
>>  create mode 100644 configs/lubancat-2-rk3568_defconfig
>
>You should add an entry for this board to evb_rk3568/MAINTAINERS and
>also to the documentation at doc/board/rockchip/rockchip.rst
>
>[...]
>
>> diff --git a/arch/arm/dts/rk3568-lubancat-2.dts 
>> b/arch/arm/dts/rk3568-lubancat-2.dts
>> new file mode 100644
>> index 00..da257b0591
>> --- /dev/null
>> +++ b/arch/arm/dts/rk3568-lubancat-2.dts
>> @@ -0,0 +1,734 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +
>> +/*
>> + * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
>> + * Copyright (c) 2023 EmbedFire 
>> + * Copyright (c) 2023 Andy Yan 
>
>You are changing copyright header on a file otherwise copied 1:1 from
>the linux kernel.
>
>> + */
>> +
>
>[...]
>
>> diff --git a/configs/lubancat-2-rk3568_defconfig 
>> b/configs/lubancat-2-rk3568_defconfig
>> new file mode 100644
>> index 00..278ee8dc70
>> --- /dev/null
>> +++ b/configs/lubancat-2-rk3568_defconfig
>> @@ -0,0 +1,87 @@
>> +CONFIG_ARM=y
>> +CONFIG_SKIP_LOWLEVEL_INIT=y
>> +CONFIG_COUNTER_FREQUENCY=2400
>> +CONFIG_ARCH_ROCKCHIP=y
>> +CONFIG_TEXT_BASE=0x00a0
>> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
>> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
>> +CONFIG_NR_DRAM_BANKS=2
>> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
>> +CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2"
>> +CONFIG_ROCKCHIP_RK3568=y
>> +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
>> +CONFIG_SPL_SERIAL=y
>> +CONFIG_SPL_STACK_R_ADDR=0x60
>> +CONFIG_SPL_STACK=0x40
>> +CONFIG_DEBUG_UART_BASE=0xFE66
>> +CONFIG_DEBUG_UART_CLOCK=2400
>> +CONFIG_SYS_LOAD_ADDR=0xc00800
>> +CONFIG_DEBUG_UART=y
>> +CONFIG_FIT=y
>> +CONFIG_FIT_VERBOSE=y
>> +CONFIG_SPL_FIT_SIGNATURE=y
>> +CONFIG_SPL_LOAD_FIT=y
>> +CONFIG_LEGACY_IMAGE_FORMAT=y
>> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lubancat-2.dtb"
>> +# CONFIG_DISPLAY_CPUINFO is not set
>> +CONFIG_DISPLAY_BOARDINFO_LATE=y
>> +CONFIG_SPL_MAX_SIZE=0x4
>> +CONFIG_SPL_PAD_TO=0x7f8000
>> +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
>> +CONFIG_SPL_BSS_START_ADDR=0x400
>> +CONFIG_SPL_BSS_MAX_SIZE=0x4000
>> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
>> +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
>> +CONFIG_SPL_STACK_R=y
>> +CONFIG_SPL_ATF=y
>> +CONFIG_CMD_GPIO=y
>> +CONFIG_CMD_GPT=y
>> +CONFIG_CMD_I2C=y
>> +CONFIG_CMD_MMC=y
>> +CONFIG_CMD_USB=y
>> +# CONFIG_CMD_SETEXPR is not set
>> +CONFIG_CMD_PMIC=y
>> +CONFIG_CMD_REGULATOR=y
&g

[PATCH v4] rockchip: rk3568: Add EmbedFire Lubancat 2 support

[Andy Yan]

LubanCat2 is a rk3568 based SBC from EmbedFire.

Specification:
- Rockchip rk3568
- LPDDR4/4X 1/2/4/8 GB
- TF scard slot
- eMMC 8/32/64/128 GB
- Gigabit ethernet x 2
- HDMI out
- USB 2.0 Host x 1
- USB 2.0 Type-C OTG x 1
- USB 3.0 Host x 1
- Mini PCIE interface for WIFI/BT module
- M.2 key for 2280 NVME
- 40 pin header

The dts file is sync from linux mainline.

Signed-off-by: Andy Yan 

---

Changes in v4:
- Add entry for this board to evb_rk3568/MAINTAINERS
- document this board at doc/board/rockchip/rockchip.rst
- restore the  copyright header of dts from linux kernel
- remove ETH_DESIGNWARE from defconfig
- remove mmc-hs200-1_8v from u-boot.dsti

Changes in v3:
- some alphabetical order update
- disable all SPI flash related options.
- remove bootph-all for pinctrl
- add emmc_datastrobe pinconfig for hs200/hs400 in u-boot.dtsi
- use USB_DWC3_GENERIC driver as Jonas suggested.
- add CONFIG_SPL_DM_SEQ_ALIAS

Changes in v2:
- enable SPL_FIT_SIGNATURE

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi |  27 +
 arch/arm/dts/rk3568-lubancat-2.dts | 733 +
 board/rockchip/evb_rk3568/MAINTAINERS  |   7 +
 configs/lubancat-2-rk3568_defconfig|  85 +++
 doc/board/rockchip/rockchip.rst|   1 +
 6 files changed, 854 insertions(+)
 create mode 100644 arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3568-lubancat-2.dts
 create mode 100644 configs/lubancat-2-rk3568_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bd518064f3..64c885dcf9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -178,6 +178,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-soquartz-cm4.dtb \
rk3566-soquartz-model-a.dtb \
rk3568-evb.dtb \
+   rk3568-lubancat-2.dtb \
rk3568-nanopi-r5c.dtb \
rk3568-nanopi-r5s.dtb \
rk3568-odroid-m1.dtb \
diff --git a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi 
b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
new file mode 100644
index 00..27c6277523
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2023 Andy Yan 
+ */
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+   chosen {
+   stdout-path = &uart2;
+   };
+};
+
+&sdhci {
+   cap-mmc-highspeed;
+   mmc-ddr-1_8v;
+   mmc-hs400-1_8v;
+   mmc-hs400-enhanced-strobe;
+   pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+};
+
+&uart2 {
+   bootph-all;
+   clock-frequency = <2400>;
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-lubancat-2.dts 
b/arch/arm/dts/rk3568-lubancat-2.dts
new file mode 100644
index 00..e653b067aa
--- /dev/null
+++ b/arch/arm/dts/rk3568-lubancat-2.dts
@@ -0,0 +1,733 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 EmbedFire 
+ */
+
+/dts-v1/;
+#include 
+#include 
+#include 
+#include 
+#include "rk3568.dtsi"
+
+/ {
+   model = "EmbedFire LubanCat 2";
+   compatible = "embedfire,lubancat-2", "rockchip,rk3568";
+
+   aliases {
+   ethernet0 = &gmac0;
+   ethernet1 = &gmac1;
+   mmc0 = &sdmmc0;
+   mmc1 = &sdhci;
+   };
+
+   chosen: chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+
+   user_led: user-led {
+   label = "user_led";
+   linux,default-trigger = "heartbeat";
+   default-state = "on";
+   gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&user_led_pin>;
+   };
+   };
+
+   hdmi-con {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con_in: endpoint {
+   remote-endpoint = <&hdmi_out_con>;
+   };
+   };
+   };
+
+   dc_5v: dc-5v-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "dc_5v";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   };
+
+   vcc3v3_sys: vcc3v3-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_sys"

Re:[PATCH v2 13/17] video: rockchip: Add rk3328 vop support

[Andy Yan]

Hi Jaqan：

At 2023-12-19 03:11:10, "Jagan Teki"  wrote:
>From: Jagan Teki 
>
>Add support for Rockchip RK3328 VOP.
>
>Require VOP cleanup before handoff to Linux by writing reset values to
>WIN registers. Without this Linux VOP trigger page fault as below
>[0.752016] Loading compiled-in X.509 certificates
>[0.787796] inno_hdmi_phy_rk3328_clk_recalc_rate: parent 2400
>[0.788391] inno-hdmi-phy ff43.phy: 
>inno_hdmi_phy_rk3328_clk_recalc_rate rate 14850 vco 14850
>[0.798353] rockchip-drm display-subsystem: bound ff37.vop (ops 
>vop_component_ops)
>[0.799403] dwhdmi-rockchip ff3c.hdmi: supply avdd-0v9 not found, using 
>dummy regulator
>[0.800288] rk_iommu ff373f00.iommu: Enable stall request timed out, 
>status: 0x4b
>[0.801131] dwhdmi-rockchip ff3c.hdmi: supply avdd-1v8 not found, using 
>dummy regulator
>[0.802056] rk_iommu ff373f00.iommu: Disable paging request timed out, 
>status: 0x4b
>[0.803233] dwhdmi-rockchip ff3c.hdmi: Detected HDMI TX controller 
>v2.11a with HDCP (inno_dw_hdmi_phy2)
>[0.805355] dwhdmi-rockchip ff3c.hdmi: registered DesignWare HDMI I2C 
>bus driver
>[0.808769] rockchip-drm display-subsystem: bound ff3c.hdmi (ops 
>dw_hdmi_rockchip_ops)
>[0.810869] [drm] Initialized rockchip 1.0.0 20140818 for display-subsystem 
>on minor 0
>
>Signed-off-by: Jagan Teki 
>---
>Changes for v2:
>- Add VOP cleanup
>- Update commit
>
> drivers/video/rockchip/Makefile |  1 +
> drivers/video/rockchip/rk3328_vop.c | 83 +
> 2 files changed, 84 insertions(+)
> create mode 100644 drivers/video/rockchip/rk3328_vop.c
>
>diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile
>index 4991303c73..f55beceebf 100644
>--- a/drivers/video/rockchip/Makefile
>+++ b/drivers/video/rockchip/Makefile
>@@ -6,6 +6,7 @@
> ifdef CONFIG_VIDEO_ROCKCHIP
> obj-y += rk_vop.o
> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288_vop.o
>+obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328_vop.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o
> obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o
> obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
>diff --git a/drivers/video/rockchip/rk3328_vop.c 
>b/drivers/video/rockchip/rk3328_vop.c
>new file mode 100644
>index 00..a4da3a91e8
>--- /dev/null
>+++ b/drivers/video/rockchip/rk3328_vop.c
>@@ -0,0 +1,83 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+/*
>+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
>+ */
>+
>+#include 
>+#include 
>+#include 
>+#include "rk_vop.h"
>+
>+DECLARE_GLOBAL_DATA_PTR;
>+
>+static void rk3328_set_pin_polarity(struct udevice *dev,
>+  enum vop_modes mode, u32 polarity)
>+{
>+  struct rk_vop_priv *priv = dev_get_priv(dev);
>+  struct rk3288_vop *regs = priv->regs;
>+
>+  switch (mode) {
>+  case VOP_MODE_HDMI:
>+  clrsetbits_le32(®s->dsp_ctrl1,
>+  M_RK3399_DSP_HDMI_POL,
>+  V_RK3399_DSP_HDMI_POL(polarity));
>+  break;
>+  default:
>+  debug("%s: unsupported output mode %x\n", __func__, mode);
>+  }
>+}
>+
>+static int rk3328_vop_probe(struct udevice *dev)
>+{
>+  /* Before relocation we don't need to do anything */
>+  if (!(gd->flags & GD_FLG_RELOC))
>+  return 0;
>+
>+  return rk_vop_probe(dev);
>+}
>+
>+static int rk3328_vop_remove(struct udevice *dev)
>+{
>+  struct rk_vop_priv *priv = dev_get_priv(dev);
>+  struct rk3288_vop *regs = priv->regs;
>+  struct rk3288_vop *win_regs = priv->regs + priv->win_offset;
>+
>+  /* write reset values */
>+  writel(0xef013f, &win_regs->win0_act_info);
>+  writel(0xef013f, &win_regs->win0_dsp_info);
>+  writel(0xa000a, &win_regs->win0_dsp_st);
>+  writel(0x0, &win_regs->win0_yrgb_mst);
>+  writel(0x01, ®s->reg_cfg_done);
>+
>+  return 0;
>+}

I think this just workaround Linux iommu page fault by luck。
The reset value（what you called it is）your write just let win0 read a
320x240 rectangular from address 0 and display it at next frame（maybe 16ms 
later if your
current display is run at 60HZ）。

1. we don't know what content is at address 0, so you will see something 
strange on your monitor.
2. there is no guarantee that address 0 is really readable（maybe a security 
memory space， or maybe
it is not a valid address）， this may cause another issue that not easy to 
detect。

>+
>+struct rkvop_driverdata rk3328_driverdata = {
>+  .dsp_offset = 0x490,
>+  .win_offset = 0xd0,
>+  .features = VOP_FEATURE_OUTPUT_10BIT,
>+  .set_pin_polarity = rk3328_set_pin_polarity,
>+};
>+
>+static const struct udevice_id rk3328_vop_ids[] = {
>+  {
>+  .compatible = "rockchip,rk3328-vop",
>+  .data = (ulong)&rk3328_driverdata
>+  },
>+  { /* sentile */ }
>+};
>+
>+static const struct video_ops rk3328_vop_ops = {
>+};
>+
>+U_BOOT_DRIVER(rk3328_vop) = {
>+ 

Re:Re: [PATCH v2 13/17] video: rockchip: Add rk3328 vop support

[Andy Yan]

Hi Jaqan，
在 2023-12-19 15:42:26，"Jagan Teki"  写道：
>Hi Andy,
>
>On Tue, Dec 19, 2023 at 6:50 AM Andy Yan  wrote:
>>
>>
>> Hi Jaqan：
>>
>> At 2023-12-19 03:11:10, "Jagan Teki"  wrote:
>> >From: Jagan Teki 
>> >
>> >Add support for Rockchip RK3328 VOP.
>> >
>> >Require VOP cleanup before handoff to Linux by writing reset values to
>> >WIN registers. Without this Linux VOP trigger page fault as below
>> >[0.752016] Loading compiled-in X.509 certificates
>> >[0.787796] inno_hdmi_phy_rk3328_clk_recalc_rate: parent 2400
>> >[0.788391] inno-hdmi-phy ff43.phy: 
>> >inno_hdmi_phy_rk3328_clk_recalc_rate rate 14850 vco 14850
>> >[0.798353] rockchip-drm display-subsystem: bound ff37.vop (ops 
>> >vop_component_ops)
>> >[0.799403] dwhdmi-rockchip ff3c.hdmi: supply avdd-0v9 not found, 
>> >using dummy regulator
>> >[0.800288] rk_iommu ff373f00.iommu: Enable stall request timed out, 
>> >status: 0x4b
>> >[0.801131] dwhdmi-rockchip ff3c.hdmi: supply avdd-1v8 not found, 
>> >using dummy regulator
>> >[0.802056] rk_iommu ff373f00.iommu: Disable paging request timed out, 
>> >status: 0x4b
>> >[0.803233] dwhdmi-rockchip ff3c.hdmi: Detected HDMI TX controller 
>> >v2.11a with HDCP (inno_dw_hdmi_phy2)
>> >[0.805355] dwhdmi-rockchip ff3c.hdmi: registered DesignWare HDMI 
>> >I2C bus driver
>> >[0.808769] rockchip-drm display-subsystem: bound ff3c.hdmi (ops 
>> >dw_hdmi_rockchip_ops)
>> >[0.810869] [drm] Initialized rockchip 1.0.0 20140818 for 
>> >display-subsystem on minor 0
>> >
>> >Signed-off-by: Jagan Teki 
>> >---
>> >Changes for v2:
>> >- Add VOP cleanup
>> >- Update commit
>> >
>> > drivers/video/rockchip/Makefile |  1 +
>> > drivers/video/rockchip/rk3328_vop.c | 83 +
>> > 2 files changed, 84 insertions(+)
>> > create mode 100644 drivers/video/rockchip/rk3328_vop.c
>> >
>> >diff --git a/drivers/video/rockchip/Makefile 
>> >b/drivers/video/rockchip/Makefile
>> >index 4991303c73..f55beceebf 100644
>> >--- a/drivers/video/rockchip/Makefile
>> >+++ b/drivers/video/rockchip/Makefile
>> >@@ -6,6 +6,7 @@
>> > ifdef CONFIG_VIDEO_ROCKCHIP
>> > obj-y += rk_vop.o
>> > obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288_vop.o
>> >+obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328_vop.o
>> > obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o
>> > obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o
>> > obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
>> >diff --git a/drivers/video/rockchip/rk3328_vop.c 
>> >b/drivers/video/rockchip/rk3328_vop.c
>> >new file mode 100644
>> >index 00..a4da3a91e8
>> >--- /dev/null
>> >+++ b/drivers/video/rockchip/rk3328_vop.c
>> >@@ -0,0 +1,83 @@
>> >+// SPDX-License-Identifier: GPL-2.0+
>> >+/*
>> >+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
>> >+ */
>> >+
>> >+#include 
>> >+#include 
>> >+#include 
>> >+#include "rk_vop.h"
>> >+
>> >+DECLARE_GLOBAL_DATA_PTR;
>> >+
>> >+static void rk3328_set_pin_polarity(struct udevice *dev,
>> >+  enum vop_modes mode, u32 polarity)
>> >+{
>> >+  struct rk_vop_priv *priv = dev_get_priv(dev);
>> >+  struct rk3288_vop *regs = priv->regs;
>> >+
>> >+  switch (mode) {
>> >+  case VOP_MODE_HDMI:
>> >+  clrsetbits_le32(®s->dsp_ctrl1,
>> >+  M_RK3399_DSP_HDMI_POL,
>> >+  V_RK3399_DSP_HDMI_POL(polarity));
>> >+  break;
>> >+  default:
>> >+  debug("%s: unsupported output mode %x\n", __func__, mode);
>> >+  }
>> >+}
>> >+
>> >+static int rk3328_vop_probe(struct udevice *dev)
>> >+{
>> >+  /* Before relocation we don't need to do anything */
>> >+  if (!(gd->flags & GD_FLG_RELOC))
>> >+  return 0;
>> >+
>> >+  return rk_vop_probe(dev);
>> >+}
>> >+
>> >+static int rk3328_vop_remove(struct udevice *dev)
>> >+{
>> >+  struct rk_vop_priv *priv = dev_get_priv(dev);
>> >+  struct rk3288_vop *re

[PATCH 2/2] board: rockchip: Add support for rk3588 based Cool Pi CM5 EVB

[Andy Yan]

Cool Pi CM5 EVB works as a mother board connect with CM5.

CM5 Specification:
- Rockchip RK3588
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet x 1 with PHY YT8531
- Gigabit ethernet x 1 drived by PCIE with YT6801S

CM5 EVB Specification:
- HDMI Type A out x 2
- HDMI Type D in x 1
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- PCIE M.2 E Key for Wireless connection
- PCIE M.2 M Key for NVME connection
- 40 pin header

The dts is from linux-6.8 rc1.

Signed-off-by: Andy Yan 
---

 .../arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi |  30 +
 arch/arm/dts/rk3588-coolpi-cm5-evb.dts| 214 ++
 arch/arm/dts/rk3588-coolpi-cm5.dtsi   | 650 ++
 board/rockchip/evb_rk3588/MAINTAINERS |   8 +
 configs/coolpi-cm5-evb-rk3588_defconfig   | 105 +++
 5 files changed, 1007 insertions(+)
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-evb.dts
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5.dtsi
 create mode 100644 configs/coolpi-cm5-evb-rk3588_defconfig

diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi 
b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
new file mode 100644
index 000..6b69ff424fa
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+   };
+};
+
+&fspim2_pins {
+   bootph-all;
+};
+
+&sfc {
+   bootph-pre-ram;
+   u-boot,spl-sfc-no-dma;
+   pinctrl-names = "default";
+   pinctrl-0 = <&fspim2_pins>;
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb.dts 
b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts
new file mode 100644
index 000..d4c70835e0f
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include 
+#include "rk3588-coolpi-cm5.dtsi"
+
+/ {
+   model = "RK3588 CoolPi CM5 EVB";
+   compatible = "coolpi,pi-cm5-evb", "coolpi,pi-cm5", "rockchip,rk3588";
+
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&bl_en>;
+   power-supply = <&vcc12v_dcin>;
+   pwms = <&pwm2 0 25000 0>;
+   };
+
+   leds: leds {
+   compatible = "gpio-leds";
+
+   green_led: led-0 {
+   color = ;
+   function = LED_FUNCTION_STATUS;
+   gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+   };
+
+   vcc12v_dcin: vcc12v-dcin-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc12v_dcin";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <1200>;
+   regulator-max-microvolt = <1200>;
+   };
+
+   vcc5v0_sys: vcc5v0-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   vin-supply = <&vcc12v_dcin>;
+   };
+
+   vcc3v3_sys: vcc3v3-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   vin-supply = <&vcc12v_dcin>;
+   };
+
+   vcc3v3_lcd: vcc3v3-lcd-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_lcd";
+   enable-active-high;
+   gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+  

[PATCH 1/2] board: rockchip: Add support for rk3588s based Cool Pi 4B

[Andy Yan]

CoolPi 4B is a rk3588s based SBC.

Specification:
- Rockchip RK3588S
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet drived by PCIE with RTL8111HS
- HDMI Type D out
- Mini DP out
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- WIFI/BT module AIC8800
- 40 pin header

The dts is from linux-6.8 rc1.

Signed-off-by: Andy Yan 
---

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi |  30 +
 arch/arm/dts/rk3588s-coolpi-4b.dts | 813 +
 board/rockchip/evb_rk3588/MAINTAINERS  |   7 +
 configs/coolpi-4b-rk3588s_defconfig| 105 +++
 5 files changed, 956 insertions(+)
 create mode 100644 arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3588s-coolpi-4b.dts
 create mode 100644 configs/coolpi-4b-rk3588s_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b5c588c3363..a3d0cad3471 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -189,6 +189,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-rock-3a.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3588) += \
+   rk3588s-coolpi-4b.dts \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
diff --git a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi 
b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
new file mode 100644
index 000..6b69ff424fa
--- /dev/null
+++ b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+   };
+};
+
+&fspim2_pins {
+   bootph-all;
+};
+
+&sfc {
+   bootph-pre-ram;
+   u-boot,spl-sfc-no-dma;
+   pinctrl-names = "default";
+   pinctrl-0 = <&fspim2_pins>;
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
diff --git a/arch/arm/dts/rk3588s-coolpi-4b.dts 
b/arch/arm/dts/rk3588s-coolpi-4b.dts
new file mode 100644
index 000..a15c8e8fa6d
--- /dev/null
+++ b/arch/arm/dts/rk3588s-coolpi-4b.dts
@@ -0,0 +1,813 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction
+ *
+ */
+
+/dts-v1/;
+
+#include 
+#include 
+#include 
+#include "rk3588s.dtsi"
+
+/ {
+   model = "RK3588S CoolPi 4 Model B";
+   compatible = "coolpi,pi-4b", "rockchip,rk3588s";
+
+   aliases {
+   mmc0 = &sdhci;
+   mmc1 = &sdio;
+   mmc2 = &sdmmc;
+   serial2 = &uart2;
+   };
+
+   analog-sound {
+   compatible = "audio-graph-card";
+   dais = <&i2s0_8ch_p0>;
+   label = "rk3588-es8316";
+   routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+   widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+   };
+
+   chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   leds: leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <&gpio_leds>;
+
+   led0: led-green {
+   color = ;
+   function = LED_FUNCTION_STATUS;
+   gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+
+   led1: led-red {
+   color = ;
+   default-state = "off";
+   function = LED_FUNCTION_WLAN;
+   gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "phy0tx";
+   };
+   };
+
+   sdio_pwrseq: sdio-pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   clocks = <&hym8563>;
+   clock-names = "ext_clock";
+   pinctrl-names = "default";
+   pinctrl-0 = <&wifi_enable_h>;
+   /*
+* On the module itself this is one of these (depending
+* on the actual ca

[PATCH] rockchip: rk3588-evb: Enable USB support

[Andy Yan]

From: Andy Yan 

Enable USB releated config to support
boot from usb.

Signed-off-by: Andy Yan 
---
 configs/evb-rk3588_defconfig | 12 
 1 file changed, 12 insertions(+)

diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index 0b7b4f2f627..8a6aa91cb29 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -40,6 +40,7 @@ CONFIG_SPL_ATF=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_REGULATOR=y
 # CONFIG_SPL_DOS_PARTITION is not set
@@ -61,6 +62,9 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_PHY_REALTEK=y
 CONFIG_DWC_ETH_QOS=y
 CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_SPL_RAM=y
@@ -68,4 +72,12 @@ CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_ERRNO_STR=y
-- 
2.34.1

[PATCH v2 2/2] board: rockchip: Add support for rk3588 based Cool Pi CM5 EVB

[Andy Yan]

Cool Pi CM5 EVB works as a mother board connect with CM5.

CM5 Specification:
- Rockchip RK3588
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet x 1 with PHY YT8531
- Gigabit ethernet x 1 drived by PCIE with YT6801S

CM5 EVB Specification:
- HDMI Type A out x 2
- HDMI Type D in x 1
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- PCIE M.2 E Key for Wireless connection
- PCIE M.2 M Key for NVME connection
- 40 pin header

The dts is from linux-6.8 rc1.

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang 


---

Changes in v2:
- sync dts from linux-rockchip which will be in linux-6.8 rc6[0]

[0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/

 .../arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi |  30 +
 arch/arm/dts/rk3588-coolpi-cm5-evb.dts| 216 ++
 arch/arm/dts/rk3588-coolpi-cm5.dtsi   | 649 ++
 board/rockchip/evb_rk3588/MAINTAINERS |   8 +
 configs/coolpi-cm5-evb-rk3588_defconfig   | 105 +++
 5 files changed, 1008 insertions(+)
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-evb.dts
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5.dtsi
 create mode 100644 configs/coolpi-cm5-evb-rk3588_defconfig

diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi 
b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
new file mode 100644
index 00..6b69ff424f
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+   };
+};
+
+&fspim2_pins {
+   bootph-all;
+};
+
+&sfc {
+   bootph-pre-ram;
+   u-boot,spl-sfc-no-dma;
+   pinctrl-names = "default";
+   pinctrl-0 = <&fspim2_pins>;
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb.dts 
b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts
new file mode 100644
index 00..a4946cdc3b
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include 
+#include "rk3588-coolpi-cm5.dtsi"
+
+/ {
+   model = "RK3588 CoolPi CM5 EVB";
+   compatible = "coolpi,pi-cm5-evb", "coolpi,pi-cm5", "rockchip,rk3588";
+
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&bl_en>;
+   power-supply = <&vcc12v_dcin>;
+   pwms = <&pwm2 0 25000 0>;
+   };
+
+   leds: leds {
+   compatible = "gpio-leds";
+
+   green_led: led-0 {
+   color = ;
+   function = LED_FUNCTION_STATUS;
+   gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+   };
+
+   vcc12v_dcin: vcc12v-dcin-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc12v_dcin";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <1200>;
+   regulator-max-microvolt = <1200>;
+   };
+
+   vcc5v0_sys: vcc5v0-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   vin-supply = <&vcc12v_dcin>;
+   };
+
+   vcc3v3_sys: vcc3v3-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   vin-supply = <&vcc12v_dcin>;
+   };
+
+   vcc3v3_lcd: vcc3v3-lcd-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = 

[PATCH v2 1/2] board: rockchip: Add support for rk3588s based Cool Pi 4B

[Andy Yan]

CoolPi 4B is a rk3588s based SBC.

Specification:
- Rockchip RK3588S
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet drived by PCIE with RTL8111HS
- HDMI Type D out
- Mini DP out
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- WIFI/BT module AIC8800
- 40 pin header

The dts is from linux-6.8 rc1.

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang 

---

Changes in v2:
- sync dts from linux-rockchip which will be in linux-6.8 rc6[0]

[0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi |  30 +
 arch/arm/dts/rk3588s-coolpi-4b.dts | 812 +
 board/rockchip/evb_rk3588/MAINTAINERS  |   7 +
 configs/coolpi-4b-rk3588s_defconfig| 105 +++
 5 files changed, 955 insertions(+)
 create mode 100644 arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3588s-coolpi-4b.dts
 create mode 100644 configs/coolpi-4b-rk3588s_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ce10d3dbb0..ae7c088ceb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -190,6 +190,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-rock-3a.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3588) += \
+   rk3588s-coolpi-4b.dts \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
diff --git a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi 
b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
new file mode 100644
index 00..6b69ff424f
--- /dev/null
+++ b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+   };
+};
+
+&fspim2_pins {
+   bootph-all;
+};
+
+&sfc {
+   bootph-pre-ram;
+   u-boot,spl-sfc-no-dma;
+   pinctrl-names = "default";
+   pinctrl-0 = <&fspim2_pins>;
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
diff --git a/arch/arm/dts/rk3588s-coolpi-4b.dts 
b/arch/arm/dts/rk3588s-coolpi-4b.dts
new file mode 100644
index 00..e037bf9db7
--- /dev/null
+++ b/arch/arm/dts/rk3588s-coolpi-4b.dts
@@ -0,0 +1,812 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction
+ *
+ */
+
+/dts-v1/;
+
+#include 
+#include 
+#include 
+#include "rk3588s.dtsi"
+
+/ {
+   model = "RK3588S CoolPi 4 Model B";
+   compatible = "coolpi,pi-4b", "rockchip,rk3588s";
+
+   aliases {
+   mmc0 = &sdhci;
+   mmc1 = &sdmmc;
+   mmc2 = &sdio;
+   };
+
+   analog-sound {
+   compatible = "audio-graph-card";
+   dais = <&i2s0_8ch_p0>;
+   label = "rk3588-es8316";
+   routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+   widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+   };
+
+   chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   leds: leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <&gpio_leds>;
+
+   led0: led-green {
+   color = ;
+   function = LED_FUNCTION_STATUS;
+   gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+
+   led1: led-red {
+   color = ;
+   default-state = "off";
+   function = LED_FUNCTION_WLAN;
+   gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "phy0tx";
+   };
+   };
+
+   sdio_pwrseq: sdio-pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   clocks = <&hym8563>;
+   clock-names = "ext_clock";
+   pinctrl-names = "default";
+   pinctrl-0 = <&wifi_enable_h&g

Re:Re: [PATCH v2 1/2] board: rockchip: Add support for rk3588s based Cool Pi 4B

[Andy Yan]

At 2024-02-14 22:13:08, "Quentin Schulz"  
wrote:
>Hi Andy,
>
>On 2/14/24 10:31, Andy Yan wrote:
>> [You don't often get email from andys...@163.com. Learn why this is 
>> important at https://aka.ms/LearnAboutSenderIdentification ]
>> 
>> CoolPi 4B is a rk3588s based SBC.
>> 
>> Specification:
>> - Rockchip RK3588S
>> - LPDDR4 2/4/8/16 GB
>> - TF scard slot
>> - eMMC 8/32/64/128 GB module
>> - SPI Nor 8MB
>> - Gigabit ethernet drived by PCIE with RTL8111HS
>> - HDMI Type D out
>> - Mini DP out
>> - USB 2.0 Host x 2
>> - USB 3.0 OTG x 1
>> - USB 3.0 Host x 1
>> - WIFI/BT module AIC8800
>> - 40 pin header
>> 
>> The dts is from linux-6.8 rc1.
>> 
>> Signed-off-by: Andy Yan 
>> Reviewed-by: Kever Yang 
>> 
>> ---
>> 
>> Changes in v2:
>> - sync dts from linux-rockchip which will be in linux-6.8 rc6[0]
>> 
>> [0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/
>>   arch/arm/dts/Makefile  |   1 +
>>   arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi |  30 +
>>   arch/arm/dts/rk3588s-coolpi-4b.dts | 812 +
>>   board/rockchip/evb_rk3588/MAINTAINERS  |   7 +
>>   configs/coolpi-4b-rk3588s_defconfig| 105 +++
>>   5 files changed, 955 insertions(+)
>>   create mode 100644 arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
>>   create mode 100644 arch/arm/dts/rk3588s-coolpi-4b.dts
>>   create mode 100644 configs/coolpi-4b-rk3588s_defconfig
>> 
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index ce10d3dbb0..ae7c088ceb 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -190,6 +190,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
>>  rk3568-rock-3a.dtb
>> 
>>   dtb-$(CONFIG_ROCKCHIP_RK3588) += \
>> +   rk3588s-coolpi-4b.dts \
>>  rk3588-edgeble-neu6a-io.dtb \
>>  rk3588-edgeble-neu6b-io.dtb \
>>  rk3588-evb1-v10.dtb \
>> diff --git a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi 
>> b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
>> new file mode 100644
>> index 00..6b69ff424f
>> --- /dev/null
>> +++ b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
>> @@ -0,0 +1,30 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +
>> +#include "rk3588s-u-boot.dtsi"
>> +
>> +/ {
>> +   chosen {
>> +   u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
>> +   };
>
>This is already in rk3588s-u-boot.dtsi

Okay, will be dropped in the next version. Thanks for catching that.

>
>> +};
>> +
>> +&fspim2_pins {
>> +   bootph-all;
>> +};
>> +
>> +&sfc {
>> +   bootph-pre-ram;
>> +   u-boot,spl-sfc-no-dma;
>> +   pinctrl-names = "default";
>> +   pinctrl-0 = <&fspim2_pins>;
>> +   status = "okay";
>> +
>> +   flash@0 {
>> +   bootph-pre-ram;
>> +   compatible = "jedec,spi-nor";
>> +   reg = <0>;
>> +   spi-max-frequency = <2400>;
>> +   spi-rx-bus-width = <4>;
>> +   spi-tx-bus-width = <1>;
>> +   };
>> +};
>> diff --git a/arch/arm/dts/rk3588s-coolpi-4b.dts 
>> b/arch/arm/dts/rk3588s-coolpi-4b.dts
>> new file mode 100644
>> index 00..e037bf9db7
>> --- /dev/null
>> +++ b/arch/arm/dts/rk3588s-coolpi-4b.dts
>> @@ -0,0 +1,812 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
>> + *
>> + * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction
>> + *
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include "rk3588s.dtsi"
>> +
>> +/ {
>> +   model = "RK3588S CoolPi 4 Model B";
>> +   compatible = "coolpi,pi-4b", "rockchip,rk3588s";
>> +
>> +   aliases {
>> +   mmc0 = &sdhci;
>> +   mmc1 = &sdmmc;
>> +   mmc2 = &sdio;
>> +   };
>> +
>> +   analog-sound {
>> +   compatible = "audio-graph-card";
>> +   dais = <&i2s0_8ch_p0>;
>> +   label = "rk3588-es8316";
>> +   routing = &qu

Re:Re: [PATCH v2 1/2] board: rockchip: Add support for rk3588s based Cool Pi 4B

[Andy Yan]

Hi Quentin：
At 2024-02-15 18:40:25, "Quentin Schulz"  
wrote:
>Hi Andy,
>
>On 2/15/24 11:35, Andy Yan wrote:
>[...]
>>>> diff --git a/configs/coolpi-4b-rk3588s_defconfig 
>>>> b/configs/coolpi-4b-rk3588s_defconfig
>>>> new file mode 100644
>>>> index 00..3e3e5abc86
>>>> --- /dev/null
>>>> +++ b/configs/coolpi-4b-rk3588s_defconfig
>>>> @@ -0,0 +1,105 @@
>>>> +CONFIG_ARM=y
>>>> +CONFIG_SKIP_LOWLEVEL_INIT=y
>>>> +CONFIG_COUNTER_FREQUENCY=2400
>>>> +CONFIG_ARCH_ROCKCHIP=y
>>>> +CONFIG_TEXT_BASE=0x00a0
>>>> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
>>>> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
>>>> +CONFIG_NR_DRAM_BANKS=2
>>>> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>>>> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
>>>> +CONFIG_SF_DEFAULT_SPEED=2400
>>>> +CONFIG_SF_DEFAULT_MODE=0x2000
>>>> +CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b"
>>>> +CONFIG_ROCKCHIP_RK3588=y
>>>> +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
>>>> +CONFIG_ROCKCHIP_SPI_IMAGE=y
>>>> +CONFIG_SPL_SERIAL=y
>>>> +CONFIG_SPL_STACK_R_ADDR=0x60
>>>> +CONFIG_TARGET_EVB_RK3588=y
>>>> +CONFIG_SPL_STACK=0x40
>>>> +CONFIG_DEBUG_UART_BASE=0xFEB5
>>>> +CONFIG_DEBUG_UART_CLOCK=2400
>>>> +CONFIG_SPL_SPI_FLASH_SUPPORT=y
>>>> +CONFIG_SPL_SPI=y
>>>> +CONFIG_SYS_LOAD_ADDR=0xc00800
>>>> +CONFIG_PCI=y
>>>> +CONFIG_DEBUG_UART=y
>>>> +CONFIG_AHCI=y
>>>> +CONFIG_FIT=y
>>>> +CONFIG_FIT_VERBOSE=y
>>>> +CONFIG_SPL_FIT_SIGNATURE=y
>>>> +CONFIG_SPL_LOAD_FIT=y
>>>> +CONFIG_LEGACY_IMAGE_FORMAT=y
>>>> +CONFIG_OF_BOARD_SETUP=y
>>>> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb"
>>>> +# CONFIG_DISPLAY_CPUINFO is not set
>>>> +CONFIG_DISPLAY_BOARDINFO_LATE=y
>>>> +CONFIG_SPL_MAX_SIZE=0x4
>>>> +CONFIG_SPL_PAD_TO=0x7f8000
>>>> +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
>>>> +CONFIG_SPL_BSS_START_ADDR=0x400
>>>> +CONFIG_SPL_BSS_MAX_SIZE=0x4000
>>>> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
>>>> +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
>>>> +CONFIG_SPL_STACK_R=y
>>>> +CONFIG_SPL_SPI_LOAD=y
>>>> +CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
>>>> +CONFIG_SPL_ATF=y
>>>> +CONFIG_CMD_GPIO=y
>>>> +CONFIG_CMD_GPT=y
>>>> +CONFIG_CMD_I2C=y
>>>> +CONFIG_CMD_MMC=y
>>>> +CONFIG_CMD_PCI=y
>>>> +CONFIG_CMD_USB=y
>>>> +# CONFIG_CMD_SETEXPR is not set
>>>> +CONFIG_CMD_REGULATOR=y
>>>> +# CONFIG_SPL_DOS_PARTITION is not set
>>>> +CONFIG_SPL_OF_CONTROL=y
>>>> +CONFIG_OF_LIVE=y
>>>> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks 
>>>> assigned-clock-rates assigned-clock-parents"
>>>> +CONFIG_SPL_DM_SEQ_ALIAS=y
>>>> +CONFIG_SPL_REGMAP=y
>>>> +CONFIG_SPL_SYSCON=y
>>>> +CONFIG_AHCI_PCI=y
>>>> +CONFIG_DWC_AHCI=y
>>>> +CONFIG_SPL_CLK=y
>>>> +CONFIG_ROCKCHIP_GPIO=y
>>>> +CONFIG_SYS_I2C_ROCKCHIP=y
>>>> +CONFIG_MISC=y
>>>> +CONFIG_SUPPORT_EMMC_RPMB=y
>>>> +CONFIG_MMC_DW=y
>>>> +CONFIG_MMC_DW_ROCKCHIP=y
>>>> +CONFIG_MMC_SDHCI=y
>>>> +CONFIG_MMC_SDHCI_SDMA=y
>>>> +CONFIG_MMC_SDHCI_ROCKCHIP=y
>>>> +CONFIG_SF_DEFAULT_BUS=5
>>>> +CONFIG_SPI_FLASH_SFDP_SUPPORT=y
>>>> +CONFIG_SPI_FLASH_XMC=y
>>>> +CONFIG_SPI_FLASH_XTX=y
>>>> +CONFIG_PHY_MOTORCOMM=y
>>>> +CONFIG_DWC_ETH_QOS=y
>>>> +CONFIG_DWC_ETH_QOS_ROCKCHIP=y
>>>> +CONFIG_NVME_PCI=y
>>>> +CONFIG_PCIE_DW_ROCKCHIP=y
>>>> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
>>>> +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
>>>> +CONFIG_PHY_ROCKCHIP_USBDP=y
>>>> +CONFIG_SPL_PINCTRL=y
>>>> +CONFIG_PWM_ROCKCHIP=y
>>>> +CONFIG_SPL_RAM=y
>>>> +CONFIG_SCSI=y
>>>> +CONFIG_BAUDRATE=150
>>>> +CONFIG_DEBUG_UART_SHIFT=2
>>>> +CONFIG_SYS_NS16550_MEM32=y
>>>> +CONFIG_ROCKCHIP_SFC=y
>>>> +CONFIG_SYSRESET=y
>>>> +CONFIG_USB=y
>>>> +CONFIG_USB_XHCI_HCD=y
>>>> +CONFIG_USB_EHCI_HCD=y
>>>> +CONFIG_USB_EHCI_GENERIC=y
>>>> +CONFIG_USB_OHCI_HCD=y
>>>> +CONFIG_USB_OHCI_GENERIC=y
>>>> +CONFIG_USB_DWC3=y
>>>> +CONFIG_USB_DWC3_GENERIC=y
>>>> +CONFIG_ERRNO_STR=y
>>>
>>> Is there any reason for NOT enabling MMC_HS400_ES?
>> 
>> No, I just follow the config of other rk3588/s based boards.
>
>Fortunately enough, a patch was recently merged to have at least HS200 
>on RK3588, which is the first mode that actually works, anything below 
>that is broken right now.
>
>> It seems that there are no rk3588/s based boards enable MMC_HS400_ES in the 
>> current u-boot mainline ?
>> 
>
>Jaguar is hopefully coming soon-ish, maybe not in this release but the 
>next one (patches are sent already), and we make us of it in U-Boot 
>proper and the SPL. Up to you, can always be enabled later on.

With a quick search， I fond jonas'S patch for enabling HS200 has been merged, 
but
your patch will bring HS400_ES, does that mean all the rk3588/s based boars 
will switch to
HS400 ES if they support it?

Thanks.
>
>FWIW, both comments on this patch also apply to the second patch in this 
>series :)
>
>Cheers,
>Quentin

Re:Re: [PATCH v2 1/2] board: rockchip: Add support for rk3588s based Cool Pi 4B

[Andy Yan]

Hi Quentin：


在 2024-02-15 20:42:56，"Quentin Schulz"  
写道：
>Hi Andy,
>
>On 2/15/24 12:55, Andy Yan wrote:
>> [You don't often get email from andys...@163.com. Learn why this is 
>> important at https://aka.ms/LearnAboutSenderIdentification ]
>> 
>> Hi Quentin：
>> At 2024-02-15 18:40:25, "Quentin Schulz" 
>>  wrote:
>>> Hi Andy,
>>>
>>> On 2/15/24 11:35, Andy Yan wrote:
>>> [...]
>>>>>> diff --git a/configs/coolpi-4b-rk3588s_defconfig 
>>>>>> b/configs/coolpi-4b-rk3588s_defconfig
>>>>>> new file mode 100644
>>>>>> index 00..3e3e5abc86
>>>>>> --- /dev/null
>>>>>> +++ b/configs/coolpi-4b-rk3588s_defconfig
>>>>>> @@ -0,0 +1,105 @@
>>>>>> +CONFIG_ARM=y
>>>>>> +CONFIG_SKIP_LOWLEVEL_INIT=y
>>>>>> +CONFIG_COUNTER_FREQUENCY=2400
>>>>>> +CONFIG_ARCH_ROCKCHIP=y
>>>>>> +CONFIG_TEXT_BASE=0x00a0
>>>>>> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
>>>>>> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
>>>>>> +CONFIG_NR_DRAM_BANKS=2
>>>>>> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>>>>>> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
>>>>>> +CONFIG_SF_DEFAULT_SPEED=2400
>>>>>> +CONFIG_SF_DEFAULT_MODE=0x2000
>>>>>> +CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b"
>>>>>> +CONFIG_ROCKCHIP_RK3588=y
>>>>>> +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
>>>>>> +CONFIG_ROCKCHIP_SPI_IMAGE=y
>>>>>> +CONFIG_SPL_SERIAL=y
>>>>>> +CONFIG_SPL_STACK_R_ADDR=0x60
>>>>>> +CONFIG_TARGET_EVB_RK3588=y
>>>>>> +CONFIG_SPL_STACK=0x40
>>>>>> +CONFIG_DEBUG_UART_BASE=0xFEB5
>>>>>> +CONFIG_DEBUG_UART_CLOCK=2400
>>>>>> +CONFIG_SPL_SPI_FLASH_SUPPORT=y
>>>>>> +CONFIG_SPL_SPI=y
>>>>>> +CONFIG_SYS_LOAD_ADDR=0xc00800
>>>>>> +CONFIG_PCI=y
>>>>>> +CONFIG_DEBUG_UART=y
>>>>>> +CONFIG_AHCI=y
>>>>>> +CONFIG_FIT=y
>>>>>> +CONFIG_FIT_VERBOSE=y
>>>>>> +CONFIG_SPL_FIT_SIGNATURE=y
>>>>>> +CONFIG_SPL_LOAD_FIT=y
>>>>>> +CONFIG_LEGACY_IMAGE_FORMAT=y
>>>>>> +CONFIG_OF_BOARD_SETUP=y
>>>>>> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb"
>>>>>> +# CONFIG_DISPLAY_CPUINFO is not set
>>>>>> +CONFIG_DISPLAY_BOARDINFO_LATE=y
>>>>>> +CONFIG_SPL_MAX_SIZE=0x4
>>>>>> +CONFIG_SPL_PAD_TO=0x7f8000
>>>>>> +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
>>>>>> +CONFIG_SPL_BSS_START_ADDR=0x400
>>>>>> +CONFIG_SPL_BSS_MAX_SIZE=0x4000
>>>>>> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
>>>>>> +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
>>>>>> +CONFIG_SPL_STACK_R=y
>>>>>> +CONFIG_SPL_SPI_LOAD=y
>>>>>> +CONFIG_SYS_SPI_U_BOOT_OFFS=0x6
>>>>>> +CONFIG_SPL_ATF=y
>>>>>> +CONFIG_CMD_GPIO=y
>>>>>> +CONFIG_CMD_GPT=y
>>>>>> +CONFIG_CMD_I2C=y
>>>>>> +CONFIG_CMD_MMC=y
>>>>>> +CONFIG_CMD_PCI=y
>>>>>> +CONFIG_CMD_USB=y
>>>>>> +# CONFIG_CMD_SETEXPR is not set
>>>>>> +CONFIG_CMD_REGULATOR=y
>>>>>> +# CONFIG_SPL_DOS_PARTITION is not set
>>>>>> +CONFIG_SPL_OF_CONTROL=y
>>>>>> +CONFIG_OF_LIVE=y
>>>>>> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent 
>>>>>> assigned-clocks assigned-clock-rates assigned-clock-parents"
>>>>>> +CONFIG_SPL_DM_SEQ_ALIAS=y
>>>>>> +CONFIG_SPL_REGMAP=y
>>>>>> +CONFIG_SPL_SYSCON=y
>>>>>> +CONFIG_AHCI_PCI=y
>>>>>> +CONFIG_DWC_AHCI=y
>>>>>> +CONFIG_SPL_CLK=y
>>>>>> +CONFIG_ROCKCHIP_GPIO=y
>>>>>> +CONFIG_SYS_I2C_ROCKCHIP=y
>>>>>> +CONFIG_MISC=y
>>>>>> +CONFIG_SUPPORT_EMMC_RPMB=y
>>>>>> +CONFIG_MMC_DW=y
>>>>>> +CONFIG_MMC_DW_ROCKCHIP=y
>>>>>> +CONFIG_MMC_SDHCI=y
>>>>>> +CONFIG_MMC_SDHCI_SDMA=y
>>>>>> +CONFIG_MMC_SDHCI_ROCKCHIP=y
>>>>>> +CONFIG_SF_DEFAULT_BUS

[PATCH v3 1/2] board: rockchip: Add support for rk3588s based Cool Pi 4B

[Andy Yan]

CoolPi 4B is a rk3588s based SBC.

Specification:
- Rockchip RK3588S
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet drived by PCIE with RTL8111HS
- HDMI Type D out
- Mini DP out
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- WIFI/BT module AIC8800
- 40 pin header

The dts is from linux-6.8 rc1.

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang 
[0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/

---

Changes in v3:
- remove spl-boot-order as it is already in rk3588s-u-boot.dtsi
- Enable MMC_HS400 and MMC_HS400_ES as suggestted by Quentin

Changes in v2:
- sync dts from linux-rockchip which will be in linux-6.8 rc6[0]

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi |  29 +
 arch/arm/dts/rk3588s-coolpi-4b.dts | 812 +
 board/rockchip/evb_rk3588/MAINTAINERS  |   7 +
 configs/coolpi-4b-rk3588s_defconfig| 113 +++
 5 files changed, 962 insertions(+)
 create mode 100644 arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3588s-coolpi-4b.dts
 create mode 100644 configs/coolpi-4b-rk3588s_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ce10d3dbb0..ae7c088ceb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -190,6 +190,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-rock-3a.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3588) += \
+   rk3588s-coolpi-4b.dts \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
diff --git a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi 
b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
new file mode 100644
index 00..6e4b97028d
--- /dev/null
+++ b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
+
+&fspim2_pins {
+   bootph-all;
+};
+
+&sdhci {
+   cap-mmc-highspeed;
+   mmc-hs200-1_8v;
+};
+
+&sfc {
+   bootph-pre-ram;
+   u-boot,spl-sfc-no-dma;
+   pinctrl-names = "default";
+   pinctrl-0 = <&fspim2_pins>;
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
diff --git a/arch/arm/dts/rk3588s-coolpi-4b.dts 
b/arch/arm/dts/rk3588s-coolpi-4b.dts
new file mode 100644
index 00..e037bf9db7
--- /dev/null
+++ b/arch/arm/dts/rk3588s-coolpi-4b.dts
@@ -0,0 +1,812 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction
+ *
+ */
+
+/dts-v1/;
+
+#include 
+#include 
+#include 
+#include "rk3588s.dtsi"
+
+/ {
+   model = "RK3588S CoolPi 4 Model B";
+   compatible = "coolpi,pi-4b", "rockchip,rk3588s";
+
+   aliases {
+   mmc0 = &sdhci;
+   mmc1 = &sdmmc;
+   mmc2 = &sdio;
+   };
+
+   analog-sound {
+   compatible = "audio-graph-card";
+   dais = <&i2s0_8ch_p0>;
+   label = "rk3588-es8316";
+   routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+   widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+   };
+
+   chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   leds: leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <&gpio_leds>;
+
+   led0: led-green {
+   color = ;
+   function = LED_FUNCTION_STATUS;
+   gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+
+   led1: led-red {
+   color = ;
+   default-state = "off";
+   function = LED_FUNCTION_WLAN;
+   gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "phy0tx";
+   };
+   };
+
+   sdio_pwrseq: sdio-pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   clocks = <&hym8563>;
+   clock-names = "ext_clock";
+   pinctr

[PATCH v3 2/2] board: rockchip: Add support for rk3588 based Cool Pi CM5 EVB

[Andy Yan]

Cool Pi CM5 EVB works as a mother board connect with CM5.

CM5 Specification:
- Rockchip RK3588
- LPDDR4 2/4/8/16 GB
- TF scard slot
- eMMC 8/32/64/128 GB module
- SPI Nor 8MB
- Gigabit ethernet x 1 with PHY YT8531
- Gigabit ethernet x 1 drived by PCIE with YT6801S

CM5 EVB Specification:
- HDMI Type A out x 2
- HDMI Type D in x 1
- USB 2.0 Host x 2
- USB 3.0 OTG x 1
- USB 3.0 Host x 1
- PCIE M.2 E Key for Wireless connection
- PCIE M.2 M Key for NVME connection
- 40 pin header

The dts is from linux-6.8 rc1.

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang 

[0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/

---

Changes in v3:
- remove spl-boot-order as it is already in rk3588s-u-boot.dtsi
- Enable MMC_HS400 and MMC_HS400_ES as suggestted by Quentin

Changes in v2:
- sync dts from linux-rockchip which will be in linux-6.8 rc6[0]

 arch/arm/dts/Makefile |   1 +
 .../arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi |  29 +
 arch/arm/dts/rk3588-coolpi-cm5-evb.dts| 216 ++
 arch/arm/dts/rk3588-coolpi-cm5.dtsi   | 649 ++
 board/rockchip/evb_rk3588/MAINTAINERS |   8 +
 configs/coolpi-cm5-evb-rk3588_defconfig   | 113 +++
 6 files changed, 1016 insertions(+)
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-evb.dts
 create mode 100644 arch/arm/dts/rk3588-coolpi-cm5.dtsi
 create mode 100644 configs/coolpi-cm5-evb-rk3588_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ae7c088ceb..aafc41c466 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -191,6 +191,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
 
 dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588s-coolpi-4b.dts \
+   rk3588-coolpi-cm5-evb.dts \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi 
b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
new file mode 100644
index 00..ed15b14ea0
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-u-boot.dtsi"
+
+&fspim2_pins {
+   bootph-all;
+};
+
+&sdhci {
+   cap-mmc-highspeed;
+   mmc-hs200-1_8v;
+};
+
+&sfc {
+   bootph-pre-ram;
+   u-boot,spl-sfc-no-dma;
+   pinctrl-names = "default";
+   pinctrl-0 = <&fspim2_pins>;
+   status = "okay";
+
+   flash@0 {
+   bootph-pre-ram;
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <2400>;
+   spi-rx-bus-width = <4>;
+   spi-tx-bus-width = <1>;
+   };
+};
diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb.dts 
b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts
new file mode 100644
index 00..a4946cdc3b
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include 
+#include "rk3588-coolpi-cm5.dtsi"
+
+/ {
+   model = "RK3588 CoolPi CM5 EVB";
+   compatible = "coolpi,pi-cm5-evb", "coolpi,pi-cm5", "rockchip,rk3588";
+
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&bl_en>;
+   power-supply = <&vcc12v_dcin>;
+   pwms = <&pwm2 0 25000 0>;
+   };
+
+   leds: leds {
+   compatible = "gpio-leds";
+
+   green_led: led-0 {
+   color = ;
+   function = LED_FUNCTION_STATUS;
+   gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+   linux,default-trigger = "heartbeat";
+   };
+   };
+
+   vcc12v_dcin: vcc12v-dcin-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc12v_dcin";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <1200>;
+   regulator-max-microvolt = <1200>;
+   };
+
+   vcc5v0_sys: vcc5v0-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   vin-supply = <&vcc12v_dcin>;
+

[U-Boot] [PATCH v3 1/9] arm: rockchip: Add RK3308 SOC support

[Andy Yan]

RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang

---

Changes in v3: None

 arch/arm/include/asm/arch-rk3308/boot0.h  |  11 +
 arch/arm/include/asm/arch-rk3308/cru_rk3308.h | 290 ++
 arch/arm/include/asm/arch-rk3308/gpio.h   |  11 +
 arch/arm/include/asm/arch-rk3308/grf_rk3308.h | 197 
 arch/arm/mach-rockchip/Kconfig|  24 ++
 arch/arm/mach-rockchip/Makefile   |   1 +
 arch/arm/mach-rockchip/rk3308/Kconfig |  14 +
 arch/arm/mach-rockchip/rk3308/Makefile|   9 +
 arch/arm/mach-rockchip/rk3308/clk_rk3308.c|  31 ++
 arch/arm/mach-rockchip/rk3308/rk3308.c| 175 +++
 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c |  20 ++
 include/configs/rk3308_common.h   |  58 
 12 files changed, 841 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rk3308/boot0.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/cru_rk3308.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/gpio.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/grf_rk3308.h
 create mode 100644 arch/arm/mach-rockchip/rk3308/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rk3308/Makefile
 create mode 100644 arch/arm/mach-rockchip/rk3308/clk_rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
 create mode 100644 include/configs/rk3308_common.h

diff --git a/arch/arm/include/asm/arch-rk3308/boot0.h 
b/arch/arm/include/asm/arch-rk3308/boot0.h
new file mode 100644
index 00..2e78b074ad
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3308/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include 
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h 
b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
new file mode 100644
index 00..a14b64cdb3
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
@@ -0,0 +1,290 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
+ */
+#ifndef _ASM_ARCH_CRU_RK3308_H
+#define _ASM_ARCH_CRU_RK3308_H
+
+#include 
+
+#define MHz100
+#define OSC_HZ (24 * MHz)
+
+#define APLL_HZ(816 * MHz)
+
+#define CORE_ACLK_HZ   40800
+#define CORE_DBG_HZ20400
+
+#define BUS_ACLK_HZ2
+#define BUS_HCLK_HZ1
+#define BUS_PCLK_HZ1
+
+#define PERI_ACLK_HZ   2
+#define PERI_HCLK_HZ   1
+#define PERI_PCLK_HZ   1
+
+#define AUDIO_HCLK_HZ  1
+#define AUDIO_PCLK_HZ  1
+
+#define RK3308_PLL_CON(x)  ((x) * 0x4)
+#define RK3308_MODE_CON0xa0
+
+/* RK3308 pll id */
+enum rk3308_pll_id {
+   APLL,
+   DPLL,
+   VPLL0,
+   VPLL1,
+   PLL_COUNT,
+};
+
+struct rk3308_clk_info {
+   unsigned long id;
+   char *name;
+};
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3308_clk_priv {
+   struct rk3308_cru *cru;
+   ulong armclk_hz;
+   ulong dpll_hz;
+   ulong vpll0_hz;
+   ulong vpll1_hz;
+};
+
+struct rk3308_cru {
+   struct rk3308_pll {
+   unsigned int con0;
+   unsigned int con1;
+   unsigned int con2;
+   unsigned int con3;
+   unsigned int con4;
+   unsigned int reserved0[3];
+   } pll[4];
+   unsigned int reserved1[8];
+   unsigned int mode;
+   unsigned int misc;
+   unsigned int reserved2[2];
+   unsigned int glb_cnt_th;
+   unsigned int glb_rst_st;
+   unsigned int glb_srst_fst;
+   unsigned int glb_srst_snd;
+   unsigned int glb_rst_con;
+   unsigned int pll_lock;
+   unsigned int reserved3[6];
+   unsigned int hwffc_con0;
+   unsigned int reserved4;
+   unsigned int hwffc_th;
+   unsigned int hwffc_intst;
+   unsigned int apll_con0_s;
+   unsigned int apll_con1_s;
+   unsigned int clksel_con0_s;
+   unsigned int reserved5;
+   unsigned int clksel_con[74];
+   unsigned int reserved6[54];
+   unsigned int clkgate_con[15];
+   unsigned int reserved7[(0x380 - 0x338) / 4 - 1];
+   unsigned int ssgtbl[32];
+   unsigned int softrst_con[10];
+   unsigned int reserved8[(0x480 - 0x424) / 4 - 1];
+   unsigned int sdmmc_con[2];
+   unsigned int sdio_con[2];
+   unsigned int emmc_con[2];
+};
+
+enum {
+   /* PLLCON0*/
+   PLL_BP_SHIFT= 15,
+   PLL_POSTDIV1_SHIFT  = 12,
+   PLL_POSTDIV1_MASK   = 7 << PLL_POSTDIV1_SHIFT,
+   PLL_FBDIV_SHIFT = 0,
+   PLL_FBDIV_MASK  =

[U-Boot] [PATCH v3 0/9] Add support for RK3308 SOC

[Andy Yan]

RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.

This path set add basic support for it, test on a emmc
based evb and roc-rk3308-cc.


Changes in v3:
- Add commit message.
- rename config to roc-cc-rk3308_defconfig
- Doc update with more detail message.

Andy Yan (8):
  arm: rockchip: Add RK3308 SOC support
  arm: dts: rockchip: Add dts for rk3308 evb
  board: rockchip: Add rk3308 evb support
  rockchip: rk3308: Add sdram driver
  rockchip: mkimage: add support for RK3308
  rockchip: rk3308: Add dts for ROC-RK3308-CC
  rockchip: rk3308: Add support for ROC-RK3308-CC board
  doc: rockchip: Add documentation for rk3308 based boards

Finley Xiao (1):
  rockchip: clk: Add clk driver for rk3308

 arch/arm/dts/Makefile |4 +
 arch/arm/dts/rk3308-evb-u-boot.dtsi   |   17 +
 arch/arm/dts/rk3308-evb.dts   |  230 +++
 arch/arm/dts/rk3308-roc-cc-u-boot.dtsi|   17 +
 arch/arm/dts/rk3308-roc-cc.dts|  190 ++
 arch/arm/dts/rk3308-u-boot.dtsi   |   25 +
 arch/arm/dts/rk3308.dtsi  | 1829 +
 arch/arm/include/asm/arch-rk3308/boot0.h  |   11 +
 arch/arm/include/asm/arch-rk3308/cru_rk3308.h |  290 +++
 arch/arm/include/asm/arch-rk3308/gpio.h   |   11 +
 arch/arm/include/asm/arch-rk3308/grf_rk3308.h |  197 ++
 arch/arm/mach-rockchip/Kconfig|   24 +
 arch/arm/mach-rockchip/Makefile   |1 +
 arch/arm/mach-rockchip/rk3308/Kconfig |   27 +
 arch/arm/mach-rockchip/rk3308/Makefile|9 +
 arch/arm/mach-rockchip/rk3308/clk_rk3308.c|   31 +
 arch/arm/mach-rockchip/rk3308/rk3308.c|  175 ++
 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c |   20 +
 board/firefly/firefly-rk3308/Kconfig  |   15 +
 board/firefly/firefly-rk3308/MAINTAINERS  |5 +
 board/firefly/firefly-rk3308/Makefile |7 +
 board/firefly/firefly-rk3308/roc_cc_rk3308.c  |   82 +
 board/rockchip/evb_rk3308/Kconfig |   15 +
 board/rockchip/evb_rk3308/MAINTAINERS |6 +
 board/rockchip/evb_rk3308/Makefile|7 +
 board/rockchip/evb_rk3308/evb_rk3308.c|   44 +
 configs/evb-rk3308_defconfig  |   77 +
 configs/roc-cc-rk3308_defconfig   |   77 +
 doc/README.rockchip   |   92 +-
 drivers/clk/rockchip/Makefile |1 +
 drivers/clk/rockchip/clk_rk3308.c | 1078 ++
 drivers/ram/rockchip/Makefile |1 +
 drivers/ram/rockchip/sdram_rk3308.c   |   55 +
 include/configs/evb_rk3308.h  |   20 +
 include/configs/firefly_rk3308.h  |   20 +
 include/configs/rk3308_common.h   |   58 +
 include/dt-bindings/clock/rk3308-cru.h|  387 
 tools/rkcommon.c  |1 +
 38 files changed, 5155 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3308-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-evb.dts
 create mode 100644 arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-roc-cc.dts
 create mode 100644 arch/arm/dts/rk3308-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308.dtsi
 create mode 100644 arch/arm/include/asm/arch-rk3308/boot0.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/cru_rk3308.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/gpio.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/grf_rk3308.h
 create mode 100644 arch/arm/mach-rockchip/rk3308/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rk3308/Makefile
 create mode 100644 arch/arm/mach-rockchip/rk3308/clk_rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
 create mode 100644 board/firefly/firefly-rk3308/Kconfig
 create mode 100644 board/firefly/firefly-rk3308/MAINTAINERS
 create mode 100644 board/firefly/firefly-rk3308/Makefile
 create mode 100644 board/firefly/firefly-rk3308/roc_cc_rk3308.c
 create mode 100644 board/rockchip/evb_rk3308/Kconfig
 create mode 100644 board/rockchip/evb_rk3308/MAINTAINERS
 create mode 100644 board/rockchip/evb_rk3308/Makefile
 create mode 100644 board/rockchip/evb_rk3308/evb_rk3308.c
 create mode 100644 configs/evb-rk3308_defconfig
 create mode 100644 configs/roc-cc-rk3308_defconfig
 create mode 100644 drivers/clk/rockchip/clk_rk3308.c
 create mode 100644 drivers/ram/rockchip/sdram_rk3308.c
 create mode 100644 include/configs/evb_rk3308.h
 create mode 100644 include/configs/firefly_rk3308.h
 create mode 100644 include/configs/rk3308_common.h
 create mode 100644 include/dt-bindings/clock/rk3308-cru.h

-- 
2.17.1



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[U-Boot] [PATCH v3 4/9] board: rockchip: Add rk3308 evb support

[Andy Yan]

Add support for rk3308 evaluation board.

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang
---

Changes in v3: None

 arch/arm/mach-rockchip/rk3308/Kconfig  |  8 +++
 board/rockchip/evb_rk3308/Kconfig  | 15 +
 board/rockchip/evb_rk3308/MAINTAINERS  |  6 ++
 board/rockchip/evb_rk3308/Makefile |  7 +++
 board/rockchip/evb_rk3308/evb_rk3308.c | 44 +++
 configs/evb-rk3308_defconfig   | 77 ++
 include/configs/evb_rk3308.h   | 20 +++
 7 files changed, 177 insertions(+)
 create mode 100644 board/rockchip/evb_rk3308/Kconfig
 create mode 100644 board/rockchip/evb_rk3308/MAINTAINERS
 create mode 100644 board/rockchip/evb_rk3308/Makefile
 create mode 100644 board/rockchip/evb_rk3308/evb_rk3308.c
 create mode 100644 configs/evb-rk3308_defconfig
 create mode 100644 include/configs/evb_rk3308.h

diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig 
b/arch/arm/mach-rockchip/rk3308/Kconfig
index 9c09661595..c74d1fc7f1 100644
--- a/arch/arm/mach-rockchip/rk3308/Kconfig
+++ b/arch/arm/mach-rockchip/rk3308/Kconfig
@@ -1,5 +1,9 @@
 if ROCKCHIP_RK3308
 
+config TARGET_EVB_RK3308
+   bool "EVB_RK3308"
+   select BOARD_LATE_INIT
+
 config SYS_SOC
default "rk3308"
 
@@ -11,4 +15,8 @@ config SPL_SERIAL_SUPPORT
 
 config ROCKCHIP_BOOT_MODE_REG
default 0xff000500
+
+
+source "board/rockchip/evb_rk3308/Kconfig"
+
 endif
diff --git a/board/rockchip/evb_rk3308/Kconfig 
b/board/rockchip/evb_rk3308/Kconfig
new file mode 100644
index 00..0074429cb6
--- /dev/null
+++ b/board/rockchip/evb_rk3308/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3308
+
+config SYS_BOARD
+   default "evb_rk3308"
+
+config SYS_VENDOR
+   default "rockchip"
+
+config SYS_CONFIG_NAME
+   default "evb_rk3308"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+
+endif
diff --git a/board/rockchip/evb_rk3308/MAINTAINERS 
b/board/rockchip/evb_rk3308/MAINTAINERS
new file mode 100644
index 00..0af119ae0a
--- /dev/null
+++ b/board/rockchip/evb_rk3308/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3308
+M:  Andy Yan 
+S:  Maintained
+F:  board/rockchip/evb_rk3308
+F:  include/configs/evb_rk3308.h
+F:  configs/evb-rk3308_defconfig
diff --git a/board/rockchip/evb_rk3308/Makefile 
b/board/rockchip/evb_rk3308/Makefile
new file mode 100644
index 00..05de5560f1
--- /dev/null
+++ b/board/rockchip/evb_rk3308/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2018 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += evb_rk3308.o
diff --git a/board/rockchip/evb_rk3308/evb_rk3308.c 
b/board/rockchip/evb_rk3308/evb_rk3308.c
new file mode 100644
index 00..180f1fe4f0
--- /dev/null
+++ b/board/rockchip/evb_rk3308/evb_rk3308.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd
+ */
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define KEY_DOWN_MIN_VAL0
+#define KEY_DOWN_MAX_VAL30
+
+/*
+ * Two board variants whith adc channel 3 is for board id
+ * v10: 1024, v11: 512
+ * v10: adc channel 0 for dnl key
+ * v11: adc channel 1 for dnl key
+ */
+int rockchip_dnl_key_pressed(void)
+{
+   unsigned int key_val, id_val;
+   int key_ch;
+
+   if (adc_channel_single_shot("saradc", 3, &id_val)) {
+   printf("%s read board id failed\n", __func__);
+   return false;
+   }
+
+   if (abs(id_val - 1024) <= 30)
+   key_ch = 0;
+   else
+   key_ch = 1;
+
+   if (adc_channel_single_shot("saradc", key_ch, &key_val)) {
+   printf("%s read adc key val failed\n", __func__);
+   return false;
+   }
+
+   if (key_val >= KEY_DOWN_MIN_VAL && key_val <= KEY_DOWN_MAX_VAL)
+   return true;
+   else
+   return false;
+}
diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
new file mode 100644
index 00..36d30dfa80
--- /dev/null
+++ b/configs/evb-rk3308_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0060
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3308=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TARGET_EVB_RK3308=y
+CONFIG_SPL_STACK_R_ADDR=0xc0
+CONFIG_DEBUG_UART_BASE=0xFF0C
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_DEBUG_UART=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+# 

[U-Boot] [PATCH v3 3/9] arm: dts: rockchip: Add dts for rk3308 evb

[Andy Yan]

Add dts for rk3308 evb, sync from the linux kernel
upstream list [0].

[0]https://patchwork.kernel.org/patch/11201555/

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang
---

Changes in v3: None

 arch/arm/dts/Makefile   |3 +
 arch/arm/dts/rk3308-evb-u-boot.dtsi |   17 +
 arch/arm/dts/rk3308-evb.dts |  230 
 arch/arm/dts/rk3308-u-boot.dtsi |   25 +
 arch/arm/dts/rk3308.dtsi| 1829 +++
 5 files changed, 2104 insertions(+)
 create mode 100644 arch/arm/dts/rk3308-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-evb.dts
 create mode 100644 arch/arm/dts/rk3308-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 85ef00a2bd..f2ea546831 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -93,6 +93,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb
 
+dtb-$(CONFIG_ROCKCHIP_RK3308) += \
+   rk3308-evb.dtb
+
 dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
rk3328-rock64.dtb
diff --git a/arch/arm/dts/rk3308-evb-u-boot.dtsi 
b/arch/arm/dts/rk3308-evb-u-boot.dtsi
new file mode 100644
index 00..c6ea746de0
--- /dev/null
+++ b/arch/arm/dts/rk3308-evb-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+#include "rk3308-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", &emmc;
+   };
+};
+
+&uart4 {
+   u-boot,dm-pre-reloc;
+   clock-frequency = <2400>;
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3308-evb.dts b/arch/arm/dts/rk3308-evb.dts
new file mode 100644
index 00..124a240866
--- /dev/null
+++ b/arch/arm/dts/rk3308-evb.dts
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ */
+
+/dts-v1/;
+#include 
+#include "rk3308.dtsi"
+
+/ {
+   model = "Rockchip RK3308 EVB";
+   compatible = "rockchip,rk3308-evb", "rockchip,rk3308";
+
+   chosen {
+   stdout-path = "serial4:150n8";
+   };
+
+   adc-keys0 {
+   compatible = "adc-keys";
+   io-channels = <&saradc 0>;
+   io-channel-names = "buttons";
+   poll-interval = <100>;
+   keyup-threshold-microvolt = <180>;
+
+   func-key {
+   linux,code = ;
+   label = "function";
+   press-threshold-microvolt = <18000>;
+   };
+   };
+
+   adc-keys1 {
+   compatible = "adc-keys";
+   io-channels = <&saradc 1>;
+   io-channel-names = "buttons";
+   poll-interval = <100>;
+   keyup-threshold-microvolt = <180>;
+
+   esc-key {
+   linux,code = ;
+   label = "micmute";
+   press-threshold-microvolt = <113>;
+   };
+
+   home-key {
+   linux,code = ;
+   label = "mode";
+   press-threshold-microvolt = <901000>;
+   };
+
+   menu-key {
+   linux,code = ;
+   label = "play";
+   press-threshold-microvolt = <624000>;
+   };
+
+   vol-down-key {
+   linux,code = ;
+   label = "volume down";
+   press-threshold-microvolt = <30>;
+   };
+
+   vol-up-key {
+   linux,code = ;
+   label = "volume up";
+   press-threshold-microvolt = <18000>;
+   };
+   };
+
+   gpio-keys {
+   compatible = "gpio-keys";
+   autorepeat;
+
+   pinctrl-names = "default";
+   pinctrl-0 = <&pwr_key>;
+
+   power {
+   gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+   linux,code = ;
+   label = "GPIO Key Power";
+   wakeup-source;
+   debounce-interval = <100>;
+   };
+   };
+
+   vcc12v_dcin: vcc12v-dcin {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc12v_dcin";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <1200>;
+ 

[U-Boot] [PATCH v3 2/9] rockchip: clk: Add clk driver for rk3308

[Andy Yan]

From: Finley Xiao 

Add clk controller driver for RK3308 SOC.

This patch depends on Elaine's pll patch[0].

[0]http://patchwork.ozlabs.org/patch/1183718/

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang
---

Changes in v3: None

 drivers/clk/rockchip/Makefile  |1 +
 drivers/clk/rockchip/clk_rk3308.c  | 1078 
 include/dt-bindings/clock/rk3308-cru.h |  387 +
 3 files changed, 1466 insertions(+)
 create mode 100644 drivers/clk/rockchip/clk_rk3308.c
 create mode 100644 include/dt-bindings/clock/rk3308-cru.h

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 03a9fa77ba..f2068a8e94 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_ROCKCHIP_RK3128) += clk_rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
diff --git a/drivers/clk/rockchip/clk_rk3308.c 
b/drivers/clk/rockchip/clk_rk3308.c
new file mode 100644
index 00..e5653bbad7
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -0,0 +1,1078 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+   VCO_MAX_HZ  = 3200U * 100,
+   VCO_MIN_HZ  = 800 * 100,
+   OUTPUT_MAX_HZ   = 3200U * 100,
+   OUTPUT_MIN_HZ   = 24 * 100,
+};
+
+#define DIV_TO_RATE(input_rate, div)((input_rate) / ((div) + 1))
+
+#define RK3308_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \
+{   \
+   .rate   = _rate##U, \
+   .aclk_div = _aclk_div,  \
+   .pclk_div = _pclk_div,  \
+}
+
+static struct rockchip_pll_rate_table rk3308_pll_rates[] = {
+   /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+   RK3036_PLL_RATE(13, 6, 325, 1, 1, 1, 0),
+   RK3036_PLL_RATE(12, 1, 50, 1, 1, 1, 0),
+   RK3036_PLL_RATE(81600, 1, 68, 2, 1, 1, 0),
+   RK3036_PLL_RATE(74800, 2, 187, 3, 1, 1, 0),
+};
+
+static struct rockchip_cpu_rate_table rk3308_cpu_rates[] = {
+   RK3308_CPUCLK_RATE(12, 1, 5),
+   RK3308_CPUCLK_RATE(100800, 1, 5),
+   RK3308_CPUCLK_RATE(81600, 1, 3),
+   RK3308_CPUCLK_RATE(6, 1, 3),
+   RK3308_CPUCLK_RATE(40800, 1, 1),
+};
+
+static struct rockchip_pll_clock rk3308_pll_clks[] = {
+   [APLL] = PLL(pll_rk3328, PLL_APLL, RK3308_PLL_CON(0),
+RK3308_MODE_CON, 0, 10, 0, rk3308_pll_rates),
+   [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3308_PLL_CON(8),
+RK3308_MODE_CON, 2, 10, 0, NULL),
+   [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
+ RK3308_MODE_CON, 4, 10, 0, NULL),
+   [VPLL1] = PLL(pll_rk3328, PLL_VPLL1, RK3308_PLL_CON(24),
+ RK3308_MODE_CON, 6, 10, 0, NULL),
+};
+
+static ulong rk3308_armclk_set_clk(struct rk3308_clk_priv *priv, ulong hz)
+{
+   struct rk3308_cru *cru = priv->cru;
+   const struct rockchip_cpu_rate_table *rate;
+   ulong old_rate;
+
+   rate = rockchip_get_cpu_settings(rk3308_cpu_rates, hz);
+   if (!rate) {
+   printf("%s unsupport rate\n", __func__);
+   return -EINVAL;
+   }
+
+   /*
+* select apll as cpu/core clock pll source and
+* set up dependent divisors for PERI and ACLK clocks.
+* core hz : apll = 1:1
+*/
+   old_rate = rockchip_pll_get_rate(&rk3308_pll_clks[APLL],
+priv->cru, APLL);
+   if (old_rate > hz) {
+   if (rockchip_pll_set_rate(&rk3308_pll_clks[APLL],
+ priv->cru, APLL, hz))
+   return -EINVAL;
+   rk_clrsetreg(&cru->clksel_con[0],
+CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
+CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
+rate->aclk_div << CORE_ACLK_DIV_SHIFT |
+rate->pclk_div << CORE_DBG_DIV_SHIFT |
+CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
+0 << CORE_DIV_CON_SHIFT);
+   } else if (old_rate < hz) {
+   rk_clrsetreg(&cru->clksel_con[0],
+CORE_CLK_PLL_SEL_MASK | CORE_

[U-Boot] [PATCH v3 6/9] rockchip: mkimage: add support for RK3308

[Andy Yan]

Usage:

 (1) tools/mkimage -n rk3308 -T rksd -d tpl/u-boot-tpl.bin idbloader.img
 (2) cat spl/u-boot-spl.bin >> idbloader.img
 (3) upgrade_tool wl 0x40 idbloader.img

Note:
  When use a ddr binary from rkbin as tpl, use it replace u-boot-tpl.bin in (1)

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang
---

Changes in v3: None

 tools/rkcommon.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 831c2ad820..a16f83c1ef 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -72,6 +72,7 @@ static struct spl_info spl_infos[] = {
{ "rk3188", "RK31", 0x8000 - 0x800, true },
{ "rk322x", "RK32", 0x8000 - 0x1000, false },
{ "rk3288", "RK32", 0x8000, false },
+   { "rk3308", "RK33", 0x4 - 0x1000, false},
{ "rk3328", "RK32", 0x8000 - 0x1000, false },
{ "rk3368", "RK33", 0x8000 - 0x1000, false },
{ "rk3399", "RK33", 0x3 - 0x2000, false },
-- 
2.17.1



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[U-Boot] [PATCH v3 7/9] rockchip: rk3308: Add dts for ROC-RK3308-CC

[Andy Yan]

Add dts file for ROC-RK3308-CC from firefly.

Sync form linux rockchip for v5.5-armsoc/dts64:
"arm64: dts: rockchip: Add devicetree for board roc-rk3308-cc"
(sha1: 4403e1237be3af0977aa23ef399e3496316317a0)

Signed-off-by: Andy Yan 

---

Changes in v3:
- Add commit message.

 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/rk3308-roc-cc-u-boot.dtsi |  17 +++
 arch/arm/dts/rk3308-roc-cc.dts | 190 +
 3 files changed, 209 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-roc-cc.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f2ea546831..be5c8d0ff6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -94,7 +94,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-vyasa.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3308) += \
-   rk3308-evb.dtb
+   rk3308-evb.dtb \
+   rk3308-roc-cc.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
diff --git a/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi 
b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
new file mode 100644
index 00..ffbe742053
--- /dev/null
+++ b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+#include "rk3308-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", &emmc;
+   };
+};
+
+&uart2 {
+   u-boot,dm-pre-reloc;
+   clock-frequency = <2400>;
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3308-roc-cc.dts b/arch/arm/dts/rk3308-roc-cc.dts
new file mode 100644
index 00..e10aa638a3
--- /dev/null
+++ b/arch/arm/dts/rk3308-roc-cc.dts
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3308.dtsi"
+
+/ {
+   model = "Firefly ROC-RK3308-CC board";
+   compatible = "firefly,roc-rk3308-cc", "rockchip,rk3308";
+   chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   ir_rx {
+   compatible = "gpio-ir-receiver";
+   gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&ir_recv_pin>;
+   };
+
+   ir_tx {
+   compatible = "pwm-ir-tx";
+   pwms = <&pwm5 0 25000 0>;
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   power {
+   label = "firefly:red:power";
+   linux,default-trigger = "ir-power-click";
+   default-state = "on";
+   gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+   };
+
+   user {
+   label = "firefly:blue:user";
+   linux,default-trigger = "ir-user-click";
+   default-state = "off";
+   gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
+   };
+   };
+
+   typec_vcc5v: typec-vcc5v {
+   compatible = "regulator-fixed";
+   regulator-name = "typec_vcc5v";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   };
+
+   vcc5v0_sys: vcc5v0-sys {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_sys";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   vin-supply = <&typec_vcc5v>;
+   };
+
+   vdd_core: vdd-core {
+   compatible = "pwm-regulator";
+   pwms = <&pwm0 0 5000 1>;
+   regulator-name = "vdd_core";
+   regulator-min-microvolt = <827000>;
+   regulator-max-microvolt = <134>;
+   regulator-init-microvolt = <1015000>;
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-settling-time-up-us = <250>;
+   pwm-supply = <&vcc5v0_sys>;
+   };
+
+   vdd_log: vdd-log {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd_log";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <105>;
+   regulator-max-microvolt = <105>;
+

[U-Boot] [PATCH v3 5/9] rockchip: rk3308: Add sdram driver

[Andy Yan]

A dm based dram driver for rk3308 u-boot
to get capacity.

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang
---

Changes in v3: None

 drivers/ram/rockchip/Makefile   |  1 +
 drivers/ram/rockchip/sdram_rk3308.c | 55 +
 2 files changed, 56 insertions(+)
 create mode 100644 drivers/ram/rockchip/sdram_rk3308.c

diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index feb1f82d00..1adca32dcb 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -9,5 +9,6 @@ obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
 obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o
 obj-$(CONFIG_RAM_RK3399) += sdram_rk3399.o
diff --git a/drivers/ram/rockchip/sdram_rk3308.c 
b/drivers/ram/rockchip/sdram_rk3308.c
new file mode 100644
index 00..43d44cce62
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3308.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct dram_info {
+   struct ram_info info;
+   struct rk3308_grf *grf;
+};
+
+static int rk3308_dmc_probe(struct udevice *dev)
+{
+   struct dram_info *priv = dev_get_priv(dev);
+
+   priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+   priv->info.base = CONFIG_SYS_SDRAM_BASE;
+   priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->grf->os_reg2);
+
+   return 0;
+}
+
+static int rk3308_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+   struct dram_info *priv = dev_get_priv(dev);
+
+   *info = priv->info;
+
+   return 0;
+}
+
+static struct ram_ops rk3308_dmc_ops = {
+   .get_info = rk3308_dmc_get_info,
+};
+
+static const struct udevice_id rk3308_dmc_ids[] = {
+   { .compatible = "rockchip,rk3308-dmc" },
+   { }
+};
+
+U_BOOT_DRIVER(dmc_rk3308) = {
+   .name = "rockchip_rk3308_dmc",
+   .id = UCLASS_RAM,
+   .of_match = rk3308_dmc_ids,
+   .ops = &rk3308_dmc_ops,
+   .probe = rk3308_dmc_probe,
+   .priv_auto_alloc_size = sizeof(struct dram_info),
+};
-- 
2.17.1



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[U-Boot] [PATCH v3 8/9] rockchip: rk3308: Add support for ROC-RK3308-CC board

[Andy Yan]

ROC-RK3308-CC is a rk3308 based board designed by
Firelfy, with eMMC and 256MB DDR3 and RTL8188 Wifi
on board.

Signed-off-by: Andy Yan 

---

Changes in v3:
- rename config to roc-cc-rk3308_defconfig

 arch/arm/mach-rockchip/rk3308/Kconfig|  5 ++
 board/firefly/firefly-rk3308/Kconfig | 15 
 board/firefly/firefly-rk3308/MAINTAINERS |  5 ++
 board/firefly/firefly-rk3308/Makefile|  7 ++
 board/firefly/firefly-rk3308/roc_cc_rk3308.c | 82 
 configs/roc-cc-rk3308_defconfig  | 77 ++
 include/configs/firefly_rk3308.h | 20 +
 7 files changed, 211 insertions(+)
 create mode 100644 board/firefly/firefly-rk3308/Kconfig
 create mode 100644 board/firefly/firefly-rk3308/MAINTAINERS
 create mode 100644 board/firefly/firefly-rk3308/Makefile
 create mode 100644 board/firefly/firefly-rk3308/roc_cc_rk3308.c
 create mode 100644 configs/roc-cc-rk3308_defconfig
 create mode 100644 include/configs/firefly_rk3308.h

diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig 
b/arch/arm/mach-rockchip/rk3308/Kconfig
index c74d1fc7f1..b9fdfe2e95 100644
--- a/arch/arm/mach-rockchip/rk3308/Kconfig
+++ b/arch/arm/mach-rockchip/rk3308/Kconfig
@@ -4,6 +4,10 @@ config TARGET_EVB_RK3308
bool "EVB_RK3308"
select BOARD_LATE_INIT
 
+config TARGET_ROC_RK3308_CC
+   bool "Firefly roc-rk3308-cc"
+   select BOARD_LATE_INIT
+
 config SYS_SOC
default "rk3308"
 
@@ -18,5 +22,6 @@ config ROCKCHIP_BOOT_MODE_REG
 
 
 source "board/rockchip/evb_rk3308/Kconfig"
+source "board/firefly/firefly-rk3308/Kconfig"
 
 endif
diff --git a/board/firefly/firefly-rk3308/Kconfig 
b/board/firefly/firefly-rk3308/Kconfig
new file mode 100644
index 00..80b1ad85a2
--- /dev/null
+++ b/board/firefly/firefly-rk3308/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ROC_RK3308_CC
+
+config SYS_BOARD
+   default "firefly-rk3308"
+
+config SYS_VENDOR
+   default "firefly"
+
+config SYS_CONFIG_NAME
+   default "firefly_rk3308"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+
+endif
diff --git a/board/firefly/firefly-rk3308/MAINTAINERS 
b/board/firefly/firefly-rk3308/MAINTAINERS
new file mode 100644
index 00..8670d8c6a8
--- /dev/null
+++ b/board/firefly/firefly-rk3308/MAINTAINERS
@@ -0,0 +1,5 @@
+ROC-RK3308-CC
+M:  Andy Yan 
+S:  Maintained
+F:  board/firefly/firefly-rk3308/roc_rk3308_cc.c
+F:  configs/roc-rk3308-cc_defconfig
diff --git a/board/firefly/firefly-rk3308/Makefile 
b/board/firefly/firefly-rk3308/Makefile
new file mode 100644
index 00..4c50b26ea9
--- /dev/null
+++ b/board/firefly/firefly-rk3308/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2018 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += roc_cc_rk3308.o
diff --git a/board/firefly/firefly-rk3308/roc_cc_rk3308.c 
b/board/firefly/firefly-rk3308/roc_cc_rk3308.c
new file mode 100644
index 00..1deaa39516
--- /dev/null
+++ b/board/firefly/firefly-rk3308/roc_cc_rk3308.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#if defined(CONFIG_DEBUG_UART)
+#define GRF_BASE   0xff00
+
+enum {
+   GPIO1C7_SHIFT   = 8,
+   GPIO1C7_MASK= GENMASK(11, 8),
+   GPIO1C7_GPIO= 0,
+   GPIO1C7_UART1_RTSN,
+   GPIO1C7_UART2_TX_M0,
+   GPIO1C7_SPI2_MOSI,
+   GPIO1C7_JTAG_TMS,
+
+   GPIO1C6_SHIFT   = 4,
+   GPIO1C6_MASK= GENMASK(7, 4),
+   GPIO1C6_GPIO= 0,
+   GPIO1C6_UART1_CTSN,
+   GPIO1C6_UART2_RX_M0,
+   GPIO1C6_SPI2_MISO,
+   GPIO1C6_JTAG_TCLK,
+
+   GPIO4D3_SHIFT   = 6,
+   GPIO4D3_MASK= GENMASK(7, 6),
+   GPIO4D3_GPIO= 0,
+   GPIO4D3_SDMMC_D3,
+   GPIO4D3_UART2_TX_M1,
+
+   GPIO4D2_SHIFT   = 4,
+   GPIO4D2_MASK= GENMASK(5, 4),
+   GPIO4D2_GPIO= 0,
+   GPIO4D2_SDMMC_D2,
+   GPIO4D2_UART2_RX_M1,
+
+   UART2_IO_SEL_SHIFT  = 2,
+   UART2_IO_SEL_MASK   = GENMASK(3, 2),
+   UART2_IO_SEL_M0 = 0,
+   UART2_IO_SEL_M1,
+   UART2_IO_SEL_USB,
+};
+
+void board_debug_uart_init(void)
+{
+   static struct rk3308_grf * const grf = (void *)GRF_BASE;
+
+   /* Enable early UART2 channel m0 on the rk3308 */
+   rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
+UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
+   rk_clrsetreg(&grf->gpio1ch_iomux,
+GPIO1C6_MASK | GPIO1C7_MASK,
+GPIO1C6_UART2_RX_M0 << GPIO1C6_SHIFT |
+GPIO1C7_UART2_TX_M0 << GPIO1C7_SHIFT);
+}
+#endif
+
+#define KEY_DOWN_MIN_VAL0
+#define KEY_DOWN_MAX_VAL30
+
+int rockc

[U-Boot] [PATCH v3 9/9] doc: rockchip: Add documentation for rk3308 based boards

[Andy Yan]

Add build documentation for rk3308 based boards.

Signed-off-by: Andy Yan 

---

Changes in v3:
- Doc update with more detail message.

 doc/README.rockchip | 92 -
 1 file changed, 91 insertions(+), 1 deletion(-)

diff --git a/doc/README.rockchip b/doc/README.rockchip
index d17afeabdd..67c14006a3 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -47,6 +47,11 @@ Two RK3036 boards are supported:
- EVB RK3036 - use evb-rk3036 configuration
- Kylin - use kylin_rk3036 configuration
 
+Two RK3308 boards are supported:
+
+   - EVB RK3308 - use evb-rk3308 configuration
+   - ROC-CC-RK3308 - use roc-rk3308-cc configuration
+
 Two RK3328 board are supported:
 
- EVB RK3328 - use evb-rk3328_defconfig
@@ -94,7 +99,20 @@ For example:
 
 (or you can use another cross compiler if you prefer)
 
-2. To build RK3399 board:
+2. To build RK3308 board:
+   - Get the rkbin
+ => git clone https://github.com/rockchip-linux/rkbin.git
+
+   - Compile U-Boot
+ => cd /path/to/u-boot
+ => export BL31=/path/to/rkbin/bin/rk33/rk3308_bl31_v2.22.elf
+ => make roc-rk3308-cc_defconfig
+ => make CROSS_COMPILE=aarch64-linux-gnu- all
+ => make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb
+ => ./tools/mkimage -n rk3308 -T rksd -d 
/path/to/rkbin/bin/rk33/rk3308_ddr_589MHz_uart2_m0_v1.26.bin idbloader.img
+ => cat spl/u-boot-spl.bin  >> idbloader.img
+
+3. To build RK3399 board:
 
Option 1: Package the image with Rockchip miniloader:
 
@@ -203,6 +221,78 @@ as several other platforms do. However it does not seem to 
be possible to
 use the existing boot ROM code from SPL.
 
 
+Writing to the eMMC with USB on ROC-RK3308-CC
+=
+For USB to work you must get your board into Bootrom mode,
+either by erasing the eMMC or short circuit the GND and D0
+on core board.
+
+Connect the board to your computer via tyepc.
+=> rkdeveloptool db rk3308_loader_v1.26.117.bin
+=> rkdeveloptool wl 0x40 idbloader.img
+=> rkdeveloptool wl 0x4000 u-boot.itb
+=> rkdeveloptool rd
+
+Then you will see the boot log from Debug UART at baud rate 150:
+DDR Version V1.26
+REGFB: 0x0032, 0x0032
+In
+589MHz
+DDR3
+ Col=10 Bank=8 Row=14 Size=256MB
+msch:1
+Returning to boot ROM...
+
+U-Boot SPL 2020.01-rc1-00225-g34b681327f (Nov 14 2019 - 10:58:04 +0800)
+Trying to boot from MMC1
+INFO:Preloader serial: 2
+NOTICE:  BL31: v1.3(release):30f1405
+NOTICE:  BL31: Built : 17:08:28, Sep 23 2019
+INFO:Lastlog: last=0x10, realtime=0x102000, size=0x2000
+INFO:ARM GICv2 driver initialized
+INFO:Using opteed sec cpu_context!
+INFO:boot cpu mask: 1
+INFO:plat_rockchip_pmu_init: pd status 0xe b
+INFO:BL31: Initializing runtime services
+WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE 
initialization. SMC`s destined for OPTEE will rK
+ERROR:   Error initializing runtime service opteed_fast
+INFO:BL31: Preparing for EL3 exit to normal world
+INFO:Entry point address = 0x60
+INFO:SPSR = 0x3c9
+
+
+U-Boot 2020.01-rc1-00225-g34b681327f (Nov 14 2019 - 10:58:47 +0800)
+
+Model: Firefly ROC-RK3308-CC board
+DRAM:  254 MiB
+MMC:   dwmmc@ff48: 0, dwmmc@ff49: 1
+rockchip_dnl_key_pressed read adc key val failed
+Net:   No ethernet found.
+Hit any key to stop autoboot:  0
+Card did not respond to voltage select!
+switch to partitions #0, OK
+mmc1(part 0) is current device
+Scanning mmc 1:4...
+Found /extlinux/extlinux.conf
+Retrieving file: /extlinux/extlinux.conf
+151 bytes read in 3 ms (48.8 KiB/s)
+1:  kernel-mainline
+Retrieving file: /Image
+14737920 bytes read in 377 ms (37.3 MiB/s)
+append: earlycon=uart8250,mmio32,0xff0c console=ttyS2,150n8
+Retrieving file: /rk3308-roc-cc.dtb
+28954 bytes read in 4 ms (6.9 MiB/s)
+Flattened Device Tree blob at 01f0
+Booting using the fdt blob at 0x1f0
+## Loading Device Tree to 0df3a000, end 0df44119 ... OK
+
+Starting kernel ...
+[0.00] Booting Linux on physical CPU 0x00 [0x410fd042]
+[0.00] Linux version 5.4.0-rc1-00040-g4dc2d508fa47-dirty (andy@B150) 
(gcc version 6.3.1 20170404 (Linaro GCC 6.3-209
+[0.00] Machine model: Firefly ROC-RK3308-CC board
+[0.00] earlycon: uart8250 at MMIO32 0xff0c (options '')
+[0.00] printk: bootconsole [uart8250] enabled
+
 Booting from an SD card
 ===
 
-- 
2.17.1



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[U-Boot] [PATCH 1/6] arm: rockchip: Add RK3308 SOC support

[Andy Yan]

RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.

Signed-off-by: Andy Yan 

---

 arch/arm/include/asm/arch-rk3308/boot0.h  |  11 +
 arch/arm/include/asm/arch-rk3308/cru_rk3308.h | 290 ++
 arch/arm/include/asm/arch-rk3308/gpio.h   |  11 +
 arch/arm/include/asm/arch-rk3308/grf_rk3308.h | 197 
 arch/arm/mach-rockchip/Kconfig|  24 ++
 arch/arm/mach-rockchip/Makefile   |   1 +
 arch/arm/mach-rockchip/rk3308/Kconfig |  14 +
 arch/arm/mach-rockchip/rk3308/Makefile|   9 +
 arch/arm/mach-rockchip/rk3308/clk_rk3308.c|  31 ++
 arch/arm/mach-rockchip/rk3308/rk3308.c| 175 +++
 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c |  20 ++
 include/configs/rk3308_common.h   |  58 
 12 files changed, 841 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rk3308/boot0.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/cru_rk3308.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/gpio.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/grf_rk3308.h
 create mode 100644 arch/arm/mach-rockchip/rk3308/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rk3308/Makefile
 create mode 100644 arch/arm/mach-rockchip/rk3308/clk_rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
 create mode 100644 include/configs/rk3308_common.h

diff --git a/arch/arm/include/asm/arch-rk3308/boot0.h 
b/arch/arm/include/asm/arch-rk3308/boot0.h
new file mode 100644
index 00..2e78b074ad
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3308/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include 
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h 
b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
new file mode 100644
index 00..a14b64cdb3
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
@@ -0,0 +1,290 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
+ */
+#ifndef _ASM_ARCH_CRU_RK3308_H
+#define _ASM_ARCH_CRU_RK3308_H
+
+#include 
+
+#define MHz100
+#define OSC_HZ (24 * MHz)
+
+#define APLL_HZ(816 * MHz)
+
+#define CORE_ACLK_HZ   40800
+#define CORE_DBG_HZ20400
+
+#define BUS_ACLK_HZ2
+#define BUS_HCLK_HZ1
+#define BUS_PCLK_HZ1
+
+#define PERI_ACLK_HZ   2
+#define PERI_HCLK_HZ   1
+#define PERI_PCLK_HZ   1
+
+#define AUDIO_HCLK_HZ  1
+#define AUDIO_PCLK_HZ  1
+
+#define RK3308_PLL_CON(x)  ((x) * 0x4)
+#define RK3308_MODE_CON0xa0
+
+/* RK3308 pll id */
+enum rk3308_pll_id {
+   APLL,
+   DPLL,
+   VPLL0,
+   VPLL1,
+   PLL_COUNT,
+};
+
+struct rk3308_clk_info {
+   unsigned long id;
+   char *name;
+};
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3308_clk_priv {
+   struct rk3308_cru *cru;
+   ulong armclk_hz;
+   ulong dpll_hz;
+   ulong vpll0_hz;
+   ulong vpll1_hz;
+};
+
+struct rk3308_cru {
+   struct rk3308_pll {
+   unsigned int con0;
+   unsigned int con1;
+   unsigned int con2;
+   unsigned int con3;
+   unsigned int con4;
+   unsigned int reserved0[3];
+   } pll[4];
+   unsigned int reserved1[8];
+   unsigned int mode;
+   unsigned int misc;
+   unsigned int reserved2[2];
+   unsigned int glb_cnt_th;
+   unsigned int glb_rst_st;
+   unsigned int glb_srst_fst;
+   unsigned int glb_srst_snd;
+   unsigned int glb_rst_con;
+   unsigned int pll_lock;
+   unsigned int reserved3[6];
+   unsigned int hwffc_con0;
+   unsigned int reserved4;
+   unsigned int hwffc_th;
+   unsigned int hwffc_intst;
+   unsigned int apll_con0_s;
+   unsigned int apll_con1_s;
+   unsigned int clksel_con0_s;
+   unsigned int reserved5;
+   unsigned int clksel_con[74];
+   unsigned int reserved6[54];
+   unsigned int clkgate_con[15];
+   unsigned int reserved7[(0x380 - 0x338) / 4 - 1];
+   unsigned int ssgtbl[32];
+   unsigned int softrst_con[10];
+   unsigned int reserved8[(0x480 - 0x424) / 4 - 1];
+   unsigned int sdmmc_con[2];
+   unsigned int sdio_con[2];
+   unsigned int emmc_con[2];
+};
+
+enum {
+   /* PLLCON0*/
+   PLL_BP_SHIFT= 15,
+   PLL_POSTDIV1_SHIFT  = 12,
+   PLL_POSTDIV1_MASK   = 7 << PLL_POSTDIV1_SHIFT,
+   PLL_FBDIV_SHIFT = 0,
+   PLL_FBDIV_MASK  = 0xfff,
+
+   /* P

[U-Boot] [PATCH 3/6] arm: dts: rockchip: Add dts for rk3308 evb

[Andy Yan]

Add dts for rk3308 evb, sync from the linux kernel
upstream list [0].

[0]https://patchwork.kernel.org/patch/11201555/

Signed-off-by: Andy Yan 
---

 arch/arm/dts/Makefile   |3 +
 arch/arm/dts/rk3308-evb-u-boot.dtsi |   17 +
 arch/arm/dts/rk3308-evb.dts |  230 
 arch/arm/dts/rk3308-u-boot.dtsi |   25 +
 arch/arm/dts/rk3308.dtsi| 1832 +++
 5 files changed, 2107 insertions(+)
 create mode 100644 arch/arm/dts/rk3308-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-evb.dts
 create mode 100644 arch/arm/dts/rk3308-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 11feb0c533..95538b117e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -93,6 +93,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb
 
+dtb-$(CONFIG_ROCKCHIP_RK3308) += \
+   rk3308-evb.dtb
+
 dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
rk3328-rock64.dtb
diff --git a/arch/arm/dts/rk3308-evb-u-boot.dtsi 
b/arch/arm/dts/rk3308-evb-u-boot.dtsi
new file mode 100644
index 00..c6ea746de0
--- /dev/null
+++ b/arch/arm/dts/rk3308-evb-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+#include "rk3308-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", &emmc;
+   };
+};
+
+&uart4 {
+   u-boot,dm-pre-reloc;
+   clock-frequency = <2400>;
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3308-evb.dts b/arch/arm/dts/rk3308-evb.dts
new file mode 100644
index 00..124a240866
--- /dev/null
+++ b/arch/arm/dts/rk3308-evb.dts
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ */
+
+/dts-v1/;
+#include 
+#include "rk3308.dtsi"
+
+/ {
+   model = "Rockchip RK3308 EVB";
+   compatible = "rockchip,rk3308-evb", "rockchip,rk3308";
+
+   chosen {
+   stdout-path = "serial4:150n8";
+   };
+
+   adc-keys0 {
+   compatible = "adc-keys";
+   io-channels = <&saradc 0>;
+   io-channel-names = "buttons";
+   poll-interval = <100>;
+   keyup-threshold-microvolt = <180>;
+
+   func-key {
+   linux,code = ;
+   label = "function";
+   press-threshold-microvolt = <18000>;
+   };
+   };
+
+   adc-keys1 {
+   compatible = "adc-keys";
+   io-channels = <&saradc 1>;
+   io-channel-names = "buttons";
+   poll-interval = <100>;
+   keyup-threshold-microvolt = <180>;
+
+   esc-key {
+   linux,code = ;
+   label = "micmute";
+   press-threshold-microvolt = <113>;
+   };
+
+   home-key {
+   linux,code = ;
+   label = "mode";
+   press-threshold-microvolt = <901000>;
+   };
+
+   menu-key {
+   linux,code = ;
+   label = "play";
+   press-threshold-microvolt = <624000>;
+   };
+
+   vol-down-key {
+   linux,code = ;
+   label = "volume down";
+   press-threshold-microvolt = <30>;
+   };
+
+   vol-up-key {
+   linux,code = ;
+   label = "volume up";
+   press-threshold-microvolt = <18000>;
+   };
+   };
+
+   gpio-keys {
+   compatible = "gpio-keys";
+   autorepeat;
+
+   pinctrl-names = "default";
+   pinctrl-0 = <&pwr_key>;
+
+   power {
+   gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+   linux,code = ;
+   label = "GPIO Key Power";
+   wakeup-source;
+   debounce-interval = <100>;
+   };
+   };
+
+   vcc12v_dcin: vcc12v-dcin {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc12v_dcin";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <1200>;
+   regulator-max-microvolt = <1200>;

[U-Boot] [PATCH 0/6] Add support for RK3308 SOC

[Andy Yan]

RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.

This path set add basic support for it, test with a
emmc board.

More boards support such as Firefly ROC-RK3308-CC will coming soon.


Andy Yan (5):
  arm: rockchip: Add RK3308 SOC support
  arm: dts: rockchip: Add dts for rk3308 evb
  board: rockchip: Add rk3308 evb support
  rockchip: rk3308: Add sdram driver
  rockchip: mkimage: add support for RK3308

Finley Xiao (1):
  rockchip: clk: Add clk driver for rk3308

 arch/arm/dts/Makefile |3 +
 arch/arm/dts/rk3308-evb-u-boot.dtsi   |   17 +
 arch/arm/dts/rk3308-evb.dts   |  230 +++
 arch/arm/dts/rk3308-u-boot.dtsi   |   25 +
 arch/arm/dts/rk3308.dtsi  | 1832 +
 arch/arm/include/asm/arch-rk3308/boot0.h  |   11 +
 arch/arm/include/asm/arch-rk3308/cru_rk3308.h |  290 +++
 arch/arm/include/asm/arch-rk3308/gpio.h   |   11 +
 arch/arm/include/asm/arch-rk3308/grf_rk3308.h |  197 ++
 arch/arm/mach-rockchip/Kconfig|   24 +
 arch/arm/mach-rockchip/Makefile   |1 +
 arch/arm/mach-rockchip/rk3308/Kconfig |   22 +
 arch/arm/mach-rockchip/rk3308/Makefile|9 +
 arch/arm/mach-rockchip/rk3308/clk_rk3308.c|   31 +
 arch/arm/mach-rockchip/rk3308/rk3308.c|  175 ++
 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c |   20 +
 board/rockchip/evb_rk3308/Kconfig |   15 +
 board/rockchip/evb_rk3308/MAINTAINERS |6 +
 board/rockchip/evb_rk3308/Makefile|7 +
 board/rockchip/evb_rk3308/evb_rk3308.c|   44 +
 configs/evb-rk3308_defconfig  |   77 +
 drivers/clk/rockchip/Makefile |1 +
 drivers/clk/rockchip/clk_rk3308.c | 1078 ++
 drivers/ram/rockchip/Makefile |1 +
 drivers/ram/rockchip/sdram_rk3308.c   |   55 +
 include/configs/evb_rk3308.h  |   20 +
 include/configs/rk3308_common.h   |   58 +
 include/dt-bindings/clock/rk3308-cru.h|  387 
 tools/rkcommon.c  |1 +
 29 files changed, 4648 insertions(+)
 create mode 100644 arch/arm/dts/rk3308-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-evb.dts
 create mode 100644 arch/arm/dts/rk3308-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308.dtsi
 create mode 100644 arch/arm/include/asm/arch-rk3308/boot0.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/cru_rk3308.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/gpio.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/grf_rk3308.h
 create mode 100644 arch/arm/mach-rockchip/rk3308/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rk3308/Makefile
 create mode 100644 arch/arm/mach-rockchip/rk3308/clk_rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
 create mode 100644 board/rockchip/evb_rk3308/Kconfig
 create mode 100644 board/rockchip/evb_rk3308/MAINTAINERS
 create mode 100644 board/rockchip/evb_rk3308/Makefile
 create mode 100644 board/rockchip/evb_rk3308/evb_rk3308.c
 create mode 100644 configs/evb-rk3308_defconfig
 create mode 100644 drivers/clk/rockchip/clk_rk3308.c
 create mode 100644 drivers/ram/rockchip/sdram_rk3308.c
 create mode 100644 include/configs/evb_rk3308.h
 create mode 100644 include/configs/rk3308_common.h
 create mode 100644 include/dt-bindings/clock/rk3308-cru.h

-- 
2.17.1



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[U-Boot] [PATCH 2/6] rockchip: clk: Add clk driver for rk3308

[Andy Yan]

From: Finley Xiao 

Add clk controller driver for RK3308 SOC.

Signed-off-by: Andy Yan 
---

 drivers/clk/rockchip/Makefile  |1 +
 drivers/clk/rockchip/clk_rk3308.c  | 1078 
 include/dt-bindings/clock/rk3308-cru.h |  387 +
 3 files changed, 1466 insertions(+)
 create mode 100644 drivers/clk/rockchip/clk_rk3308.c
 create mode 100644 include/dt-bindings/clock/rk3308-cru.h

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 03a9fa77ba..f2068a8e94 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_ROCKCHIP_RK3128) += clk_rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
diff --git a/drivers/clk/rockchip/clk_rk3308.c 
b/drivers/clk/rockchip/clk_rk3308.c
new file mode 100644
index 00..e4e213d463
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -0,0 +1,1078 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+   VCO_MAX_HZ  = 3200U * 100,
+   VCO_MIN_HZ  = 800 * 100,
+   OUTPUT_MAX_HZ   = 3200U * 100,
+   OUTPUT_MIN_HZ   = 24 * 100,
+};
+
+#define DIV_TO_RATE(input_rate, div)((input_rate) / ((div) + 1))
+
+#define RK3308_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \
+{   \
+   .rate   = _rate##U, \
+   .aclk_div = _aclk_div,  \
+   .pclk_div = _pclk_div,  \
+}
+
+static struct rockchip_pll_rate_table rk3308_pll_rates[] = {
+   /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+   RK3036_PLL_RATE(13, 6, 325, 1, 1, 1, 0),
+   RK3036_PLL_RATE(12, 1, 50, 1, 1, 1, 0),
+   RK3036_PLL_RATE(81600, 1, 68, 2, 1, 1, 0),
+   RK3036_PLL_RATE(74800, 2, 187, 3, 1, 1, 0),
+};
+
+static struct rockchip_cpu_rate_table rk3308_cpu_rates[] = {
+   RK3308_CPUCLK_RATE(12, 1, 5),
+   RK3308_CPUCLK_RATE(100800, 1, 5),
+   RK3308_CPUCLK_RATE(81600, 1, 3),
+   RK3308_CPUCLK_RATE(6, 1, 3),
+   RK3308_CPUCLK_RATE(40800, 1, 1),
+};
+
+static struct rockchip_pll_clock rk3308_pll_clks[] = {
+   [APLL] = PLL(pll_rk3328, PLL_APLL, RK3308_PLL_CON(0),
+RK3308_MODE_CON, 0, 10, 0, rk3308_pll_rates),
+   [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3308_PLL_CON(8),
+RK3308_MODE_CON, 2, 10, 0, NULL),
+   [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
+ RK3308_MODE_CON, 4, 10, 0, NULL),
+   [VPLL1] = PLL(pll_rk3328, PLL_VPLL1, RK3308_PLL_CON(24),
+ RK3308_MODE_CON, 6, 10, 0, NULL),
+};
+
+static ulong rk3308_armclk_set_clk(struct rk3308_clk_priv *priv, ulong hz)
+{
+   struct rk3308_cru *cru = priv->cru;
+   const struct rockchip_cpu_rate_table *rate;
+   ulong old_rate;
+
+   rate = rockchip_get_cpu_settings(rk3308_cpu_rates, hz);
+   if (!rate) {
+   printf("%s unsupport rate\n", __func__);
+   return -EINVAL;
+   }
+
+   /*
+* select apll as cpu/core clock pll source and
+* set up dependent divisors for PERI and ACLK clocks.
+* core hz : apll = 1:1
+*/
+   old_rate = rockchip_pll_get_rate(&rk3308_pll_clks[APLL],
+priv->cru, APLL);
+   if (old_rate > hz) {
+   if (rockchip_pll_set_rate(&rk3308_pll_clks[APLL],
+ priv->cru, APLL, hz))
+   return -EINVAL;
+   rk_clrsetreg(&cru->clksel_con[0],
+CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
+CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
+rate->aclk_div << CORE_ACLK_DIV_SHIFT |
+rate->pclk_div << CORE_DBG_DIV_SHIFT |
+CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
+0 << CORE_DIV_CON_SHIFT);
+   } else if (old_rate < hz) {
+   rk_clrsetreg(&cru->clksel_con[0],
+CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
+CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
+rate->aclk_div << C

[U-Boot] [PATCH 4/6] board: rockchip: Add rk3308 evb support

[Andy Yan]

Add support for rk3308 evaluation board.

Signed-off-by: Andy Yan 
---

 arch/arm/mach-rockchip/rk3308/Kconfig  |  8 +++
 board/rockchip/evb_rk3308/Kconfig  | 15 +
 board/rockchip/evb_rk3308/MAINTAINERS  |  6 ++
 board/rockchip/evb_rk3308/Makefile |  7 +++
 board/rockchip/evb_rk3308/evb_rk3308.c | 44 +++
 configs/evb-rk3308_defconfig   | 77 ++
 include/configs/evb_rk3308.h   | 20 +++
 7 files changed, 177 insertions(+)
 create mode 100644 board/rockchip/evb_rk3308/Kconfig
 create mode 100644 board/rockchip/evb_rk3308/MAINTAINERS
 create mode 100644 board/rockchip/evb_rk3308/Makefile
 create mode 100644 board/rockchip/evb_rk3308/evb_rk3308.c
 create mode 100644 configs/evb-rk3308_defconfig
 create mode 100644 include/configs/evb_rk3308.h

diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig 
b/arch/arm/mach-rockchip/rk3308/Kconfig
index 9c09661595..c74d1fc7f1 100644
--- a/arch/arm/mach-rockchip/rk3308/Kconfig
+++ b/arch/arm/mach-rockchip/rk3308/Kconfig
@@ -1,5 +1,9 @@
 if ROCKCHIP_RK3308
 
+config TARGET_EVB_RK3308
+   bool "EVB_RK3308"
+   select BOARD_LATE_INIT
+
 config SYS_SOC
default "rk3308"
 
@@ -11,4 +15,8 @@ config SPL_SERIAL_SUPPORT
 
 config ROCKCHIP_BOOT_MODE_REG
default 0xff000500
+
+
+source "board/rockchip/evb_rk3308/Kconfig"
+
 endif
diff --git a/board/rockchip/evb_rk3308/Kconfig 
b/board/rockchip/evb_rk3308/Kconfig
new file mode 100644
index 00..0074429cb6
--- /dev/null
+++ b/board/rockchip/evb_rk3308/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3308
+
+config SYS_BOARD
+   default "evb_rk3308"
+
+config SYS_VENDOR
+   default "rockchip"
+
+config SYS_CONFIG_NAME
+   default "evb_rk3308"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+
+endif
diff --git a/board/rockchip/evb_rk3308/MAINTAINERS 
b/board/rockchip/evb_rk3308/MAINTAINERS
new file mode 100644
index 00..0af119ae0a
--- /dev/null
+++ b/board/rockchip/evb_rk3308/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3308
+M:  Andy Yan 
+S:  Maintained
+F:  board/rockchip/evb_rk3308
+F:  include/configs/evb_rk3308.h
+F:  configs/evb-rk3308_defconfig
diff --git a/board/rockchip/evb_rk3308/Makefile 
b/board/rockchip/evb_rk3308/Makefile
new file mode 100644
index 00..05de5560f1
--- /dev/null
+++ b/board/rockchip/evb_rk3308/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2018 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += evb_rk3308.o
diff --git a/board/rockchip/evb_rk3308/evb_rk3308.c 
b/board/rockchip/evb_rk3308/evb_rk3308.c
new file mode 100644
index 00..180f1fe4f0
--- /dev/null
+++ b/board/rockchip/evb_rk3308/evb_rk3308.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd
+ */
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define KEY_DOWN_MIN_VAL0
+#define KEY_DOWN_MAX_VAL30
+
+/*
+ * Two board variants whith adc channel 3 is for board id
+ * v10: 1024, v11: 512
+ * v10: adc channel 0 for dnl key
+ * v11: adc channel 1 for dnl key
+ */
+int rockchip_dnl_key_pressed(void)
+{
+   unsigned int key_val, id_val;
+   int key_ch;
+
+   if (adc_channel_single_shot("saradc", 3, &id_val)) {
+   printf("%s read board id failed\n", __func__);
+   return false;
+   }
+
+   if (abs(id_val - 1024) <= 30)
+   key_ch = 0;
+   else
+   key_ch = 1;
+
+   if (adc_channel_single_shot("saradc", key_ch, &key_val)) {
+   printf("%s read adc key val failed\n", __func__);
+   return false;
+   }
+
+   if (key_val >= KEY_DOWN_MIN_VAL && key_val <= KEY_DOWN_MAX_VAL)
+   return true;
+   else
+   return false;
+}
diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
new file mode 100644
index 00..36d30dfa80
--- /dev/null
+++ b/configs/evb-rk3308_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0060
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3308=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TARGET_EVB_RK3308=y
+CONFIG_SPL_STACK_R_ADDR=0xc0
+CONFIG_DEBUG_UART_BASE=0xFF0C
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_DEBUG_UART=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+

[U-Boot] [PATCH 5/6] rockchip: rk3308: Add sdram driver

[Andy Yan]

A dm based dram driver for rk3308 u-boot
to get capacity.

Signed-off-by: Andy Yan 
---

 drivers/ram/rockchip/Makefile   |  1 +
 drivers/ram/rockchip/sdram_rk3308.c | 55 +
 2 files changed, 56 insertions(+)
 create mode 100644 drivers/ram/rockchip/sdram_rk3308.c

diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index feb1f82d00..1adca32dcb 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -9,5 +9,6 @@ obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
 obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o
 obj-$(CONFIG_RAM_RK3399) += sdram_rk3399.o
diff --git a/drivers/ram/rockchip/sdram_rk3308.c 
b/drivers/ram/rockchip/sdram_rk3308.c
new file mode 100644
index 00..43d44cce62
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3308.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct dram_info {
+   struct ram_info info;
+   struct rk3308_grf *grf;
+};
+
+static int rk3308_dmc_probe(struct udevice *dev)
+{
+   struct dram_info *priv = dev_get_priv(dev);
+
+   priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+   priv->info.base = CONFIG_SYS_SDRAM_BASE;
+   priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->grf->os_reg2);
+
+   return 0;
+}
+
+static int rk3308_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+   struct dram_info *priv = dev_get_priv(dev);
+
+   *info = priv->info;
+
+   return 0;
+}
+
+static struct ram_ops rk3308_dmc_ops = {
+   .get_info = rk3308_dmc_get_info,
+};
+
+static const struct udevice_id rk3308_dmc_ids[] = {
+   { .compatible = "rockchip,rk3308-dmc" },
+   { }
+};
+
+U_BOOT_DRIVER(dmc_rk3308) = {
+   .name = "rockchip_rk3308_dmc",
+   .id = UCLASS_RAM,
+   .of_match = rk3308_dmc_ids,
+   .ops = &rk3308_dmc_ops,
+   .probe = rk3308_dmc_probe,
+   .priv_auto_alloc_size = sizeof(struct dram_info),
+};
-- 
2.17.1



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[U-Boot] [PATCH 6/6] rockchip: mkimage: add support for RK3308

[Andy Yan]

Usage:

 (1) tools/mkimage -n rk3308 -T rksd -d tpl/u-boot-tpl.bin idbloader.img
 (2) cat spl/u-boot-spl.bin >> idbloader.img
 (3) upgrade_tool wl 0x40 idbloader.img

Note:
  When use a ddr binary from rkbin as tpl, use it replace u-boot-tpl.bin in (1)

Signed-off-by: Andy Yan 
---

 tools/rkcommon.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 831c2ad820..a16f83c1ef 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -72,6 +72,7 @@ static struct spl_info spl_infos[] = {
{ "rk3188", "RK31", 0x8000 - 0x800, true },
{ "rk322x", "RK32", 0x8000 - 0x1000, false },
{ "rk3288", "RK32", 0x8000, false },
+   { "rk3308", "RK33", 0x4 - 0x1000, false},
{ "rk3328", "RK32", 0x8000 - 0x1000, false },
{ "rk3368", "RK33", 0x8000 - 0x1000, false },
{ "rk3399", "RK33", 0x3 - 0x2000, false },
-- 
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[U-Boot] [PATCH v2 0/9] Add support for RK3308 SOC

[Andy Yan]

RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.

This path set add basic support for it, test with a
emmc board.

More boards support such as Firefly ROC-RK3308-CC will coming soon.

Changes in v2:
- Add board ROC-rk3308-CC
- Update doc/README.rockchip

Andy Yan (8):
  arm: rockchip: Add RK3308 SOC support
  arm: dts: rockchip: Add dts for rk3308 evb
  board: rockchip: Add rk3308 evb support
  rockchip: rk3308: Add sdram driver
  rockchip: mkimage: add support for RK3308
  rockchip: rk3308: Add dts for ROC-RK3308-CC
  rockchip: rk3308: Add support for ROC-RK3308-CC board
  doc: rockchip: Add documentation for rk3308 based boards

Finley Xiao (1):
  rockchip: clk: Add clk driver for rk3308

 arch/arm/dts/Makefile |4 +
 arch/arm/dts/rk3308-evb-u-boot.dtsi   |   17 +
 arch/arm/dts/rk3308-evb.dts   |  230 +++
 arch/arm/dts/rk3308-roc-cc-u-boot.dtsi|   17 +
 arch/arm/dts/rk3308-roc-cc.dts|  190 ++
 arch/arm/dts/rk3308-u-boot.dtsi   |   25 +
 arch/arm/dts/rk3308.dtsi  | 1829 +
 arch/arm/include/asm/arch-rk3308/boot0.h  |   11 +
 arch/arm/include/asm/arch-rk3308/cru_rk3308.h |  290 +++
 arch/arm/include/asm/arch-rk3308/gpio.h   |   11 +
 arch/arm/include/asm/arch-rk3308/grf_rk3308.h |  197 ++
 arch/arm/mach-rockchip/Kconfig|   24 +
 arch/arm/mach-rockchip/Makefile   |1 +
 arch/arm/mach-rockchip/rk3308/Kconfig |   27 +
 arch/arm/mach-rockchip/rk3308/Makefile|9 +
 arch/arm/mach-rockchip/rk3308/clk_rk3308.c|   31 +
 arch/arm/mach-rockchip/rk3308/rk3308.c|  175 ++
 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c |   20 +
 board/firefly/firefly-rk3308/Kconfig  |   15 +
 board/firefly/firefly-rk3308/MAINTAINERS  |5 +
 board/firefly/firefly-rk3308/Makefile |7 +
 board/firefly/firefly-rk3308/roc_rk3308_cc.c  |   82 +
 board/rockchip/evb_rk3308/Kconfig |   15 +
 board/rockchip/evb_rk3308/MAINTAINERS |6 +
 board/rockchip/evb_rk3308/Makefile|7 +
 board/rockchip/evb_rk3308/evb_rk3308.c|   44 +
 configs/evb-rk3308_defconfig  |   77 +
 configs/roc-rk3308-cc_defconfig   |   77 +
 doc/README.rockchip   |   20 +-
 drivers/clk/rockchip/Makefile |1 +
 drivers/clk/rockchip/clk_rk3308.c | 1078 ++
 drivers/ram/rockchip/Makefile |1 +
 drivers/ram/rockchip/sdram_rk3308.c   |   55 +
 include/configs/evb_rk3308.h  |   20 +
 include/configs/rk3308_common.h   |   58 +
 include/dt-bindings/clock/rk3308-cru.h|  387 
 tools/rkcommon.c  |1 +
 37 files changed, 5063 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3308-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-evb.dts
 create mode 100644 arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-roc-cc.dts
 create mode 100644 arch/arm/dts/rk3308-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308.dtsi
 create mode 100644 arch/arm/include/asm/arch-rk3308/boot0.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/cru_rk3308.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/gpio.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/grf_rk3308.h
 create mode 100644 arch/arm/mach-rockchip/rk3308/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rk3308/Makefile
 create mode 100644 arch/arm/mach-rockchip/rk3308/clk_rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
 create mode 100644 board/firefly/firefly-rk3308/Kconfig
 create mode 100644 board/firefly/firefly-rk3308/MAINTAINERS
 create mode 100644 board/firefly/firefly-rk3308/Makefile
 create mode 100644 board/firefly/firefly-rk3308/roc_rk3308_cc.c
 create mode 100644 board/rockchip/evb_rk3308/Kconfig
 create mode 100644 board/rockchip/evb_rk3308/MAINTAINERS
 create mode 100644 board/rockchip/evb_rk3308/Makefile
 create mode 100644 board/rockchip/evb_rk3308/evb_rk3308.c
 create mode 100644 configs/evb-rk3308_defconfig
 create mode 100644 configs/roc-rk3308-cc_defconfig
 create mode 100644 drivers/clk/rockchip/clk_rk3308.c
 create mode 100644 drivers/ram/rockchip/sdram_rk3308.c
 create mode 100644 include/configs/evb_rk3308.h
 create mode 100644 include/configs/rk3308_common.h
 create mode 100644 include/dt-bindings/clock/rk3308-cru.h

-- 
2.17.1



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[U-Boot] [PATCH v2 4/9] board: rockchip: Add rk3308 evb support

[Andy Yan]

Add support for rk3308 evaluation board.

Signed-off-by: Andy Yan 
---

Changes in v2: None

 arch/arm/mach-rockchip/rk3308/Kconfig  |  8 +++
 board/rockchip/evb_rk3308/Kconfig  | 15 +
 board/rockchip/evb_rk3308/MAINTAINERS  |  6 ++
 board/rockchip/evb_rk3308/Makefile |  7 +++
 board/rockchip/evb_rk3308/evb_rk3308.c | 44 +++
 configs/evb-rk3308_defconfig   | 77 ++
 include/configs/evb_rk3308.h   | 20 +++
 7 files changed, 177 insertions(+)
 create mode 100644 board/rockchip/evb_rk3308/Kconfig
 create mode 100644 board/rockchip/evb_rk3308/MAINTAINERS
 create mode 100644 board/rockchip/evb_rk3308/Makefile
 create mode 100644 board/rockchip/evb_rk3308/evb_rk3308.c
 create mode 100644 configs/evb-rk3308_defconfig
 create mode 100644 include/configs/evb_rk3308.h

diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig 
b/arch/arm/mach-rockchip/rk3308/Kconfig
index 9c09661595..c74d1fc7f1 100644
--- a/arch/arm/mach-rockchip/rk3308/Kconfig
+++ b/arch/arm/mach-rockchip/rk3308/Kconfig
@@ -1,5 +1,9 @@
 if ROCKCHIP_RK3308
 
+config TARGET_EVB_RK3308
+   bool "EVB_RK3308"
+   select BOARD_LATE_INIT
+
 config SYS_SOC
default "rk3308"
 
@@ -11,4 +15,8 @@ config SPL_SERIAL_SUPPORT
 
 config ROCKCHIP_BOOT_MODE_REG
default 0xff000500
+
+
+source "board/rockchip/evb_rk3308/Kconfig"
+
 endif
diff --git a/board/rockchip/evb_rk3308/Kconfig 
b/board/rockchip/evb_rk3308/Kconfig
new file mode 100644
index 00..0074429cb6
--- /dev/null
+++ b/board/rockchip/evb_rk3308/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3308
+
+config SYS_BOARD
+   default "evb_rk3308"
+
+config SYS_VENDOR
+   default "rockchip"
+
+config SYS_CONFIG_NAME
+   default "evb_rk3308"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+
+endif
diff --git a/board/rockchip/evb_rk3308/MAINTAINERS 
b/board/rockchip/evb_rk3308/MAINTAINERS
new file mode 100644
index 00..0af119ae0a
--- /dev/null
+++ b/board/rockchip/evb_rk3308/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3308
+M:  Andy Yan 
+S:  Maintained
+F:  board/rockchip/evb_rk3308
+F:  include/configs/evb_rk3308.h
+F:  configs/evb-rk3308_defconfig
diff --git a/board/rockchip/evb_rk3308/Makefile 
b/board/rockchip/evb_rk3308/Makefile
new file mode 100644
index 00..05de5560f1
--- /dev/null
+++ b/board/rockchip/evb_rk3308/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2018 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += evb_rk3308.o
diff --git a/board/rockchip/evb_rk3308/evb_rk3308.c 
b/board/rockchip/evb_rk3308/evb_rk3308.c
new file mode 100644
index 00..180f1fe4f0
--- /dev/null
+++ b/board/rockchip/evb_rk3308/evb_rk3308.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd
+ */
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define KEY_DOWN_MIN_VAL0
+#define KEY_DOWN_MAX_VAL30
+
+/*
+ * Two board variants whith adc channel 3 is for board id
+ * v10: 1024, v11: 512
+ * v10: adc channel 0 for dnl key
+ * v11: adc channel 1 for dnl key
+ */
+int rockchip_dnl_key_pressed(void)
+{
+   unsigned int key_val, id_val;
+   int key_ch;
+
+   if (adc_channel_single_shot("saradc", 3, &id_val)) {
+   printf("%s read board id failed\n", __func__);
+   return false;
+   }
+
+   if (abs(id_val - 1024) <= 30)
+   key_ch = 0;
+   else
+   key_ch = 1;
+
+   if (adc_channel_single_shot("saradc", key_ch, &key_val)) {
+   printf("%s read adc key val failed\n", __func__);
+   return false;
+   }
+
+   if (key_val >= KEY_DOWN_MIN_VAL && key_val <= KEY_DOWN_MAX_VAL)
+   return true;
+   else
+   return false;
+}
diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
new file mode 100644
index 00..36d30dfa80
--- /dev/null
+++ b/configs/evb-rk3308_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0060
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3308=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TARGET_EVB_RK3308=y
+CONFIG_SPL_STACK_R_ADDR=0xc0
+CONFIG_DEBUG_UART_BASE=0xFF0C
+CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_DEBUG_UART=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# 

[U-Boot] [PATCH v2 3/9] arm: dts: rockchip: Add dts for rk3308 evb

[Andy Yan]

Add dts for rk3308 evb, sync from the linux kernel
upstream list [0].

[0]https://patchwork.kernel.org/patch/11201555/

Signed-off-by: Andy Yan 
---

Changes in v2: None

 arch/arm/dts/Makefile   |3 +
 arch/arm/dts/rk3308-evb-u-boot.dtsi |   17 +
 arch/arm/dts/rk3308-evb.dts |  230 
 arch/arm/dts/rk3308-u-boot.dtsi |   25 +
 arch/arm/dts/rk3308.dtsi| 1829 +++
 5 files changed, 2104 insertions(+)
 create mode 100644 arch/arm/dts/rk3308-evb-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-evb.dts
 create mode 100644 arch/arm/dts/rk3308-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 11feb0c533..95538b117e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -93,6 +93,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb
 
+dtb-$(CONFIG_ROCKCHIP_RK3308) += \
+   rk3308-evb.dtb
+
 dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
rk3328-rock64.dtb
diff --git a/arch/arm/dts/rk3308-evb-u-boot.dtsi 
b/arch/arm/dts/rk3308-evb-u-boot.dtsi
new file mode 100644
index 00..c6ea746de0
--- /dev/null
+++ b/arch/arm/dts/rk3308-evb-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+#include "rk3308-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", &emmc;
+   };
+};
+
+&uart4 {
+   u-boot,dm-pre-reloc;
+   clock-frequency = <2400>;
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3308-evb.dts b/arch/arm/dts/rk3308-evb.dts
new file mode 100644
index 00..124a240866
--- /dev/null
+++ b/arch/arm/dts/rk3308-evb.dts
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ */
+
+/dts-v1/;
+#include 
+#include "rk3308.dtsi"
+
+/ {
+   model = "Rockchip RK3308 EVB";
+   compatible = "rockchip,rk3308-evb", "rockchip,rk3308";
+
+   chosen {
+   stdout-path = "serial4:150n8";
+   };
+
+   adc-keys0 {
+   compatible = "adc-keys";
+   io-channels = <&saradc 0>;
+   io-channel-names = "buttons";
+   poll-interval = <100>;
+   keyup-threshold-microvolt = <180>;
+
+   func-key {
+   linux,code = ;
+   label = "function";
+   press-threshold-microvolt = <18000>;
+   };
+   };
+
+   adc-keys1 {
+   compatible = "adc-keys";
+   io-channels = <&saradc 1>;
+   io-channel-names = "buttons";
+   poll-interval = <100>;
+   keyup-threshold-microvolt = <180>;
+
+   esc-key {
+   linux,code = ;
+   label = "micmute";
+   press-threshold-microvolt = <113>;
+   };
+
+   home-key {
+   linux,code = ;
+   label = "mode";
+   press-threshold-microvolt = <901000>;
+   };
+
+   menu-key {
+   linux,code = ;
+   label = "play";
+   press-threshold-microvolt = <624000>;
+   };
+
+   vol-down-key {
+   linux,code = ;
+   label = "volume down";
+   press-threshold-microvolt = <30>;
+   };
+
+   vol-up-key {
+   linux,code = ;
+   label = "volume up";
+   press-threshold-microvolt = <18000>;
+   };
+   };
+
+   gpio-keys {
+   compatible = "gpio-keys";
+   autorepeat;
+
+   pinctrl-names = "default";
+   pinctrl-0 = <&pwr_key>;
+
+   power {
+   gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+   linux,code = ;
+   label = "GPIO Key Power";
+   wakeup-source;
+   debounce-interval = <100>;
+   };
+   };
+
+   vcc12v_dcin: vcc12v-dcin {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc12v_dcin";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <1200>;
+   regulator-max-microvolt = &

[U-Boot] [PATCH v2 2/9] rockchip: clk: Add clk driver for rk3308

[Andy Yan]

From: Finley Xiao 

Add clk controller driver for RK3308 SOC.

Signed-off-by: Andy Yan 
---

Changes in v2: None

 drivers/clk/rockchip/Makefile  |1 +
 drivers/clk/rockchip/clk_rk3308.c  | 1078 
 include/dt-bindings/clock/rk3308-cru.h |  387 +
 3 files changed, 1466 insertions(+)
 create mode 100644 drivers/clk/rockchip/clk_rk3308.c
 create mode 100644 include/dt-bindings/clock/rk3308-cru.h

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 03a9fa77ba..f2068a8e94 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_ROCKCHIP_RK3128) += clk_rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
diff --git a/drivers/clk/rockchip/clk_rk3308.c 
b/drivers/clk/rockchip/clk_rk3308.c
new file mode 100644
index 00..e4e213d463
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -0,0 +1,1078 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+   VCO_MAX_HZ  = 3200U * 100,
+   VCO_MIN_HZ  = 800 * 100,
+   OUTPUT_MAX_HZ   = 3200U * 100,
+   OUTPUT_MIN_HZ   = 24 * 100,
+};
+
+#define DIV_TO_RATE(input_rate, div)((input_rate) / ((div) + 1))
+
+#define RK3308_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \
+{   \
+   .rate   = _rate##U, \
+   .aclk_div = _aclk_div,  \
+   .pclk_div = _pclk_div,  \
+}
+
+static struct rockchip_pll_rate_table rk3308_pll_rates[] = {
+   /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+   RK3036_PLL_RATE(13, 6, 325, 1, 1, 1, 0),
+   RK3036_PLL_RATE(12, 1, 50, 1, 1, 1, 0),
+   RK3036_PLL_RATE(81600, 1, 68, 2, 1, 1, 0),
+   RK3036_PLL_RATE(74800, 2, 187, 3, 1, 1, 0),
+};
+
+static struct rockchip_cpu_rate_table rk3308_cpu_rates[] = {
+   RK3308_CPUCLK_RATE(12, 1, 5),
+   RK3308_CPUCLK_RATE(100800, 1, 5),
+   RK3308_CPUCLK_RATE(81600, 1, 3),
+   RK3308_CPUCLK_RATE(6, 1, 3),
+   RK3308_CPUCLK_RATE(40800, 1, 1),
+};
+
+static struct rockchip_pll_clock rk3308_pll_clks[] = {
+   [APLL] = PLL(pll_rk3328, PLL_APLL, RK3308_PLL_CON(0),
+RK3308_MODE_CON, 0, 10, 0, rk3308_pll_rates),
+   [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3308_PLL_CON(8),
+RK3308_MODE_CON, 2, 10, 0, NULL),
+   [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
+ RK3308_MODE_CON, 4, 10, 0, NULL),
+   [VPLL1] = PLL(pll_rk3328, PLL_VPLL1, RK3308_PLL_CON(24),
+ RK3308_MODE_CON, 6, 10, 0, NULL),
+};
+
+static ulong rk3308_armclk_set_clk(struct rk3308_clk_priv *priv, ulong hz)
+{
+   struct rk3308_cru *cru = priv->cru;
+   const struct rockchip_cpu_rate_table *rate;
+   ulong old_rate;
+
+   rate = rockchip_get_cpu_settings(rk3308_cpu_rates, hz);
+   if (!rate) {
+   printf("%s unsupport rate\n", __func__);
+   return -EINVAL;
+   }
+
+   /*
+* select apll as cpu/core clock pll source and
+* set up dependent divisors for PERI and ACLK clocks.
+* core hz : apll = 1:1
+*/
+   old_rate = rockchip_pll_get_rate(&rk3308_pll_clks[APLL],
+priv->cru, APLL);
+   if (old_rate > hz) {
+   if (rockchip_pll_set_rate(&rk3308_pll_clks[APLL],
+ priv->cru, APLL, hz))
+   return -EINVAL;
+   rk_clrsetreg(&cru->clksel_con[0],
+CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
+CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
+rate->aclk_div << CORE_ACLK_DIV_SHIFT |
+rate->pclk_div << CORE_DBG_DIV_SHIFT |
+CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
+0 << CORE_DIV_CON_SHIFT);
+   } else if (old_rate < hz) {
+   rk_clrsetreg(&cru->clksel_con[0],
+CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
+CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
+rate-&

[U-Boot] [PATCH v2 1/9] arm: rockchip: Add RK3308 SOC support

[Andy Yan]

RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.

Signed-off-by: Andy Yan 

---

Changes in v2: None

 arch/arm/include/asm/arch-rk3308/boot0.h  |  11 +
 arch/arm/include/asm/arch-rk3308/cru_rk3308.h | 290 ++
 arch/arm/include/asm/arch-rk3308/gpio.h   |  11 +
 arch/arm/include/asm/arch-rk3308/grf_rk3308.h | 197 
 arch/arm/mach-rockchip/Kconfig|  24 ++
 arch/arm/mach-rockchip/Makefile   |   1 +
 arch/arm/mach-rockchip/rk3308/Kconfig |  14 +
 arch/arm/mach-rockchip/rk3308/Makefile|   9 +
 arch/arm/mach-rockchip/rk3308/clk_rk3308.c|  31 ++
 arch/arm/mach-rockchip/rk3308/rk3308.c| 175 +++
 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c |  20 ++
 include/configs/rk3308_common.h   |  58 
 12 files changed, 841 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rk3308/boot0.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/cru_rk3308.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/gpio.h
 create mode 100644 arch/arm/include/asm/arch-rk3308/grf_rk3308.h
 create mode 100644 arch/arm/mach-rockchip/rk3308/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rk3308/Makefile
 create mode 100644 arch/arm/mach-rockchip/rk3308/clk_rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/rk3308.c
 create mode 100644 arch/arm/mach-rockchip/rk3308/syscon_rk3308.c
 create mode 100644 include/configs/rk3308_common.h

diff --git a/arch/arm/include/asm/arch-rk3308/boot0.h 
b/arch/arm/include/asm/arch-rk3308/boot0.h
new file mode 100644
index 00..2e78b074ad
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3308/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include 
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h 
b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
new file mode 100644
index 00..a14b64cdb3
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
@@ -0,0 +1,290 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
+ */
+#ifndef _ASM_ARCH_CRU_RK3308_H
+#define _ASM_ARCH_CRU_RK3308_H
+
+#include 
+
+#define MHz100
+#define OSC_HZ (24 * MHz)
+
+#define APLL_HZ(816 * MHz)
+
+#define CORE_ACLK_HZ   40800
+#define CORE_DBG_HZ20400
+
+#define BUS_ACLK_HZ2
+#define BUS_HCLK_HZ1
+#define BUS_PCLK_HZ1
+
+#define PERI_ACLK_HZ   2
+#define PERI_HCLK_HZ   1
+#define PERI_PCLK_HZ   1
+
+#define AUDIO_HCLK_HZ  1
+#define AUDIO_PCLK_HZ  1
+
+#define RK3308_PLL_CON(x)  ((x) * 0x4)
+#define RK3308_MODE_CON0xa0
+
+/* RK3308 pll id */
+enum rk3308_pll_id {
+   APLL,
+   DPLL,
+   VPLL0,
+   VPLL1,
+   PLL_COUNT,
+};
+
+struct rk3308_clk_info {
+   unsigned long id;
+   char *name;
+};
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3308_clk_priv {
+   struct rk3308_cru *cru;
+   ulong armclk_hz;
+   ulong dpll_hz;
+   ulong vpll0_hz;
+   ulong vpll1_hz;
+};
+
+struct rk3308_cru {
+   struct rk3308_pll {
+   unsigned int con0;
+   unsigned int con1;
+   unsigned int con2;
+   unsigned int con3;
+   unsigned int con4;
+   unsigned int reserved0[3];
+   } pll[4];
+   unsigned int reserved1[8];
+   unsigned int mode;
+   unsigned int misc;
+   unsigned int reserved2[2];
+   unsigned int glb_cnt_th;
+   unsigned int glb_rst_st;
+   unsigned int glb_srst_fst;
+   unsigned int glb_srst_snd;
+   unsigned int glb_rst_con;
+   unsigned int pll_lock;
+   unsigned int reserved3[6];
+   unsigned int hwffc_con0;
+   unsigned int reserved4;
+   unsigned int hwffc_th;
+   unsigned int hwffc_intst;
+   unsigned int apll_con0_s;
+   unsigned int apll_con1_s;
+   unsigned int clksel_con0_s;
+   unsigned int reserved5;
+   unsigned int clksel_con[74];
+   unsigned int reserved6[54];
+   unsigned int clkgate_con[15];
+   unsigned int reserved7[(0x380 - 0x338) / 4 - 1];
+   unsigned int ssgtbl[32];
+   unsigned int softrst_con[10];
+   unsigned int reserved8[(0x480 - 0x424) / 4 - 1];
+   unsigned int sdmmc_con[2];
+   unsigned int sdio_con[2];
+   unsigned int emmc_con[2];
+};
+
+enum {
+   /* PLLCON0*/
+   PLL_BP_SHIFT= 15,
+   PLL_POSTDIV1_SHIFT  = 12,
+   PLL_POSTDIV1_MASK   = 7 << PLL_POSTDIV1_SHIFT,
+   PLL_FBDIV_SHIFT = 0,
+   PLL_FBDIV_MASK  = 0xfff,
+
+   /* P

[U-Boot] [PATCH v2 8/9] rockchip: rk3308: Add support for ROC-RK3308-CC board

[Andy Yan]

Signed-off-by: Andy Yan 

---

Changes in v2:
- Add board ROC-rk3308-CC

 arch/arm/mach-rockchip/rk3308/Kconfig|  5 ++
 board/firefly/firefly-rk3308/Kconfig | 15 
 board/firefly/firefly-rk3308/MAINTAINERS |  5 ++
 board/firefly/firefly-rk3308/Makefile|  7 ++
 board/firefly/firefly-rk3308/roc_rk3308_cc.c | 82 
 configs/roc-rk3308-cc_defconfig  | 77 ++
 6 files changed, 191 insertions(+)
 create mode 100644 board/firefly/firefly-rk3308/Kconfig
 create mode 100644 board/firefly/firefly-rk3308/MAINTAINERS
 create mode 100644 board/firefly/firefly-rk3308/Makefile
 create mode 100644 board/firefly/firefly-rk3308/roc_rk3308_cc.c
 create mode 100644 configs/roc-rk3308-cc_defconfig

diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig 
b/arch/arm/mach-rockchip/rk3308/Kconfig
index c74d1fc7f1..b9fdfe2e95 100644
--- a/arch/arm/mach-rockchip/rk3308/Kconfig
+++ b/arch/arm/mach-rockchip/rk3308/Kconfig
@@ -4,6 +4,10 @@ config TARGET_EVB_RK3308
bool "EVB_RK3308"
select BOARD_LATE_INIT
 
+config TARGET_ROC_RK3308_CC
+   bool "Firefly roc-rk3308-cc"
+   select BOARD_LATE_INIT
+
 config SYS_SOC
default "rk3308"
 
@@ -18,5 +22,6 @@ config ROCKCHIP_BOOT_MODE_REG
 
 
 source "board/rockchip/evb_rk3308/Kconfig"
+source "board/firefly/firefly-rk3308/Kconfig"
 
 endif
diff --git a/board/firefly/firefly-rk3308/Kconfig 
b/board/firefly/firefly-rk3308/Kconfig
new file mode 100644
index 00..7d4d189e54
--- /dev/null
+++ b/board/firefly/firefly-rk3308/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ROC_RK3308_CC
+
+config SYS_BOARD
+   default "firefly-rk3308"
+
+config SYS_VENDOR
+   default "firefly"
+
+config SYS_CONFIG_NAME
+   default "evb_rk3308"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+
+endif
diff --git a/board/firefly/firefly-rk3308/MAINTAINERS 
b/board/firefly/firefly-rk3308/MAINTAINERS
new file mode 100644
index 00..8670d8c6a8
--- /dev/null
+++ b/board/firefly/firefly-rk3308/MAINTAINERS
@@ -0,0 +1,5 @@
+ROC-RK3308-CC
+M:  Andy Yan 
+S:  Maintained
+F:  board/firefly/firefly-rk3308/roc_rk3308_cc.c
+F:  configs/roc-rk3308-cc_defconfig
diff --git a/board/firefly/firefly-rk3308/Makefile 
b/board/firefly/firefly-rk3308/Makefile
new file mode 100644
index 00..587d2e6f44
--- /dev/null
+++ b/board/firefly/firefly-rk3308/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2018 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += roc_rk3308_cc.o
diff --git a/board/firefly/firefly-rk3308/roc_rk3308_cc.c 
b/board/firefly/firefly-rk3308/roc_rk3308_cc.c
new file mode 100644
index 00..1deaa39516
--- /dev/null
+++ b/board/firefly/firefly-rk3308/roc_rk3308_cc.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#if defined(CONFIG_DEBUG_UART)
+#define GRF_BASE   0xff00
+
+enum {
+   GPIO1C7_SHIFT   = 8,
+   GPIO1C7_MASK= GENMASK(11, 8),
+   GPIO1C7_GPIO= 0,
+   GPIO1C7_UART1_RTSN,
+   GPIO1C7_UART2_TX_M0,
+   GPIO1C7_SPI2_MOSI,
+   GPIO1C7_JTAG_TMS,
+
+   GPIO1C6_SHIFT   = 4,
+   GPIO1C6_MASK= GENMASK(7, 4),
+   GPIO1C6_GPIO= 0,
+   GPIO1C6_UART1_CTSN,
+   GPIO1C6_UART2_RX_M0,
+   GPIO1C6_SPI2_MISO,
+   GPIO1C6_JTAG_TCLK,
+
+   GPIO4D3_SHIFT   = 6,
+   GPIO4D3_MASK= GENMASK(7, 6),
+   GPIO4D3_GPIO= 0,
+   GPIO4D3_SDMMC_D3,
+   GPIO4D3_UART2_TX_M1,
+
+   GPIO4D2_SHIFT   = 4,
+   GPIO4D2_MASK= GENMASK(5, 4),
+   GPIO4D2_GPIO= 0,
+   GPIO4D2_SDMMC_D2,
+   GPIO4D2_UART2_RX_M1,
+
+   UART2_IO_SEL_SHIFT  = 2,
+   UART2_IO_SEL_MASK   = GENMASK(3, 2),
+   UART2_IO_SEL_M0 = 0,
+   UART2_IO_SEL_M1,
+   UART2_IO_SEL_USB,
+};
+
+void board_debug_uart_init(void)
+{
+   static struct rk3308_grf * const grf = (void *)GRF_BASE;
+
+   /* Enable early UART2 channel m0 on the rk3308 */
+   rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
+UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
+   rk_clrsetreg(&grf->gpio1ch_iomux,
+GPIO1C6_MASK | GPIO1C7_MASK,
+GPIO1C6_UART2_RX_M0 << GPIO1C6_SHIFT |
+GPIO1C7_UART2_TX_M0 << GPIO1C7_SHIFT);
+}
+#endif
+
+#define KEY_DOWN_MIN_VAL0
+#define KEY_DOWN_MAX_VAL30
+
+int rockchip_dnl_key_pressed(void)
+{
+   unsigned int val;
+
+
+   if (adc_channel_single_shot("saradc", 1, &val)) {
+   printf("%s read adc key val failed\n", __func__);
+   return false;
+   }

[U-Boot] [PATCH v2 5/9] rockchip: rk3308: Add sdram driver

[Andy Yan]

A dm based dram driver for rk3308 u-boot
to get capacity.

Signed-off-by: Andy Yan 
---

Changes in v2: None

 drivers/ram/rockchip/Makefile   |  1 +
 drivers/ram/rockchip/sdram_rk3308.c | 55 +
 2 files changed, 56 insertions(+)
 create mode 100644 drivers/ram/rockchip/sdram_rk3308.c

diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index feb1f82d00..1adca32dcb 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -9,5 +9,6 @@ obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
 obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
 obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
 obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
+obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o
 obj-$(CONFIG_RAM_RK3399) += sdram_rk3399.o
diff --git a/drivers/ram/rockchip/sdram_rk3308.c 
b/drivers/ram/rockchip/sdram_rk3308.c
new file mode 100644
index 00..43d44cce62
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3308.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct dram_info {
+   struct ram_info info;
+   struct rk3308_grf *grf;
+};
+
+static int rk3308_dmc_probe(struct udevice *dev)
+{
+   struct dram_info *priv = dev_get_priv(dev);
+
+   priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+   priv->info.base = CONFIG_SYS_SDRAM_BASE;
+   priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->grf->os_reg2);
+
+   return 0;
+}
+
+static int rk3308_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+   struct dram_info *priv = dev_get_priv(dev);
+
+   *info = priv->info;
+
+   return 0;
+}
+
+static struct ram_ops rk3308_dmc_ops = {
+   .get_info = rk3308_dmc_get_info,
+};
+
+static const struct udevice_id rk3308_dmc_ids[] = {
+   { .compatible = "rockchip,rk3308-dmc" },
+   { }
+};
+
+U_BOOT_DRIVER(dmc_rk3308) = {
+   .name = "rockchip_rk3308_dmc",
+   .id = UCLASS_RAM,
+   .of_match = rk3308_dmc_ids,
+   .ops = &rk3308_dmc_ops,
+   .probe = rk3308_dmc_probe,
+   .priv_auto_alloc_size = sizeof(struct dram_info),
+};
-- 
2.17.1



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[U-Boot] [PATCH v2 9/9] doc: rockchip: Add documentation for rk3308 based boards

[Andy Yan]

Add build documentation for rk3308 based boards.

Signed-off-by: Andy Yan 

---

Changes in v2:
- Update doc/README.rockchip

 doc/README.rockchip | 20 +++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/doc/README.rockchip b/doc/README.rockchip
index d17afeabdd..f9f5ca8ac8 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -47,6 +47,11 @@ Two RK3036 boards are supported:
- EVB RK3036 - use evb-rk3036 configuration
- Kylin - use kylin_rk3036 configuration
 
+Two RK3308 boards are supported:
+
+   - EVB RK3308 - use evb-rk3308 configuration
+   - roc-RK3308-CC - use roc-rk3308-cc configuration
+
 Two RK3328 board are supported:
 
- EVB RK3328 - use evb-rk3328_defconfig
@@ -94,7 +99,20 @@ For example:
 
 (or you can use another cross compiler if you prefer)
 
-2. To build RK3399 board:
+2. To build RK3308 board:
+   - Get the rkbin
+ => git clone https://github.com/rockchip-linux/rkbin.git
+
+   - Compile U-Boot
+ => cd /path/to/u-boot
+ => export BL31=/path/to/rkbin/bin/rk33/rk3308_bl31_v2.22.elf
+ => make roc-rk3308-cc_defconfig
+ => make CROSS_COMPILE=aarch64-linux-gnu- all
+ => make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb
+ => ./tools/mkimage -n rk3308 -T rksd -d 
/path/to/rkbin/bin/rk33/rk3308_ddr_589MHz_uart2_m0_v1.26.bin idbloader.img
+ => cat spl/u-boot-spl.bin  >> idbloader.img
+
+3. To build RK3399 board:
 
Option 1: Package the image with Rockchip miniloader:
 
-- 
2.17.1



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[U-Boot] [PATCH v2 6/9] rockchip: mkimage: add support for RK3308

[Andy Yan]

Usage:

 (1) tools/mkimage -n rk3308 -T rksd -d tpl/u-boot-tpl.bin idbloader.img
 (2) cat spl/u-boot-spl.bin >> idbloader.img
 (3) upgrade_tool wl 0x40 idbloader.img

Note:
  When use a ddr binary from rkbin as tpl, use it replace u-boot-tpl.bin in (1)

Signed-off-by: Andy Yan 
---

Changes in v2: None

 tools/rkcommon.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 831c2ad820..a16f83c1ef 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -72,6 +72,7 @@ static struct spl_info spl_infos[] = {
{ "rk3188", "RK31", 0x8000 - 0x800, true },
{ "rk322x", "RK32", 0x8000 - 0x1000, false },
{ "rk3288", "RK32", 0x8000, false },
+   { "rk3308", "RK33", 0x4 - 0x1000, false},
{ "rk3328", "RK32", 0x8000 - 0x1000, false },
{ "rk3368", "RK33", 0x8000 - 0x1000, false },
{ "rk3399", "RK33", 0x3 - 0x2000, false },
-- 
2.17.1



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[U-Boot] [PATCH v2 7/9] rockchip: rk3308: Add dts for ROC-RK3308-CC

[Andy Yan]

Signed-off-by: Andy Yan 
---

Changes in v2: None

 arch/arm/dts/Makefile  |   3 +-
 arch/arm/dts/rk3308-roc-cc-u-boot.dtsi |  17 +++
 arch/arm/dts/rk3308-roc-cc.dts | 190 +
 3 files changed, 209 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3308-roc-cc.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 95538b117e..1cb10b5613 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -94,7 +94,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-vyasa.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3308) += \
-   rk3308-evb.dtb
+   rk3308-evb.dtb \
+   rk3308-roc-cc.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
diff --git a/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi 
b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
new file mode 100644
index 00..ffbe742053
--- /dev/null
+++ b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
+ */
+#include "rk3308-u-boot.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", &emmc;
+   };
+};
+
+&uart2 {
+   u-boot,dm-pre-reloc;
+   clock-frequency = <2400>;
+   status = "okay";
+};
diff --git a/arch/arm/dts/rk3308-roc-cc.dts b/arch/arm/dts/rk3308-roc-cc.dts
new file mode 100644
index 00..e10aa638a3
--- /dev/null
+++ b/arch/arm/dts/rk3308-roc-cc.dts
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3308.dtsi"
+
+/ {
+   model = "Firefly ROC-RK3308-CC board";
+   compatible = "firefly,roc-rk3308-cc", "rockchip,rk3308";
+   chosen {
+   stdout-path = "serial2:150n8";
+   };
+
+   ir_rx {
+   compatible = "gpio-ir-receiver";
+   gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&ir_recv_pin>;
+   };
+
+   ir_tx {
+   compatible = "pwm-ir-tx";
+   pwms = <&pwm5 0 25000 0>;
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   power {
+   label = "firefly:red:power";
+   linux,default-trigger = "ir-power-click";
+   default-state = "on";
+   gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+   };
+
+   user {
+   label = "firefly:blue:user";
+   linux,default-trigger = "ir-user-click";
+   default-state = "off";
+   gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
+   };
+   };
+
+   typec_vcc5v: typec-vcc5v {
+   compatible = "regulator-fixed";
+   regulator-name = "typec_vcc5v";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   };
+
+   vcc5v0_sys: vcc5v0-sys {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc5v0_sys";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   regulator-boot-on;
+   vin-supply = <&typec_vcc5v>;
+   };
+
+   vdd_core: vdd-core {
+   compatible = "pwm-regulator";
+   pwms = <&pwm0 0 5000 1>;
+   regulator-name = "vdd_core";
+   regulator-min-microvolt = <827000>;
+   regulator-max-microvolt = <134>;
+   regulator-init-microvolt = <1015000>;
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-settling-time-up-us = <250>;
+   pwm-supply = <&vcc5v0_sys>;
+   };
+
+   vdd_log: vdd-log {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd_log";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <105>;
+   regulator-max-microvolt = <105>;
+   vin-supply = <&vcc5v0_sys>;
+   };
+
+   vcc_io: vcc-io {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc_io";
+   re

Re: rockchip: correctly set vop0 or vop1

[Andy Yan]

Hi :

On 6/27/20 8:56 PM, Kever Yang wrote:

+Andy Yan for this topic,

Hi Patrick and Arnaud,

    I would like to leave this patch until the code fits for all the 
socs,


Thanks,

- Kever

On 2020/6/8 下午8:39, Patrick Wildt wrote:

On Mon, Jun 08, 2020 at 02:24:32PM +0200, Arnaud Patard wrote:

Patrick Wildt  writes:


On Mon, Jun 08, 2020 at 10:18:19AM +0200, Arnaud Patard wrote:

Patrick Wildt  writes:

Hi,


The EDP_LCDC_SEL bit has to be set correctly to select vop0 or
vop1, but so far we have set it in both conditions, which is not
correct.

Can someone verify this is the correct way round?  vop1 -> set,
vop0 -> clear?

Signed-off-by: Patrick Wildt 

diff --git a/drivers/video/rockchip/rk_edp.c 
b/drivers/video/rockchip/rk_edp.c

index 92188be9275..000bd481408 100644
--- a/drivers/video/rockchip/rk_edp.c
+++ b/drivers/video/rockchip/rk_edp.c
@@ -1062,7 +1062,8 @@ static int rk_edp_probe(struct udevice *dev)
  rk_setreg(&priv->grf->soc_con12, 1 << 4);
    /* select epd signal from vop0 or vop1 */
-    rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 5) : 
(1 << 5));

+    rk_clrsetreg(&priv->grf->soc_con6, (1 << 5),
+    (vop_id == 1) ? (1 << 5) : (0 << 5));
While working on PBP EDP support, found this too but I'm not sure 
it's

fine or not. For rk3399, my (not yet published) patch is doing:

+   if (vop_id == 0)
+   rk_clrreg(&priv->grf->soc_con20, (1 << 5));
+   else
+   rk_setreg(&priv->grf->soc_con20, (1 << 5));

I believe that the rk3288 may need similar treatment but I've yet to
look at the rk3288 manual.

Arnaud

Yes, it does.  If you look at the linux code, they have:

static const struct rockchip_dp_chip_data rk3399_edp = {
 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
 .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
 .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, 
RK3399_EDP_LCDC_SEL),

 .chip_type = RK3399_EDP,
};

static const struct rockchip_dp_chip_data rk3288_dp = {
 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
 .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
 .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, 
RK3288_EDP_LCDC_SEL),

 .chip_type = RK3288_DP,
};



It's true that different soc have different grf register for selecting 
lcdc/vop, and so it is for other modules such as rockchip_gmac/pinctrl. 
The above code in linux kernel is a example for how  we handle this case.




which indicates that for rk3399 *and* rk3288 the bit has to be set to
select "lit".  Now your diff looks equivalent to mine, apart from 
using

a different operation to achieve the same goal.

The linux code does

 ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, 
encoder);

 if (ret < 0)
 return;

 if (ret)
 val = dp->data->lcdsel_lit;
 else
 val = dp->data->lcdsel_big;

Assuming that endpoint_id essentiall returns vop id 0 or vop id 1, 
this

would mean that vop1 -> lit -> set bit and vop0 -> big -> clr bit.

That said, my diff seems to be fine, and your RK3399 code as well.  Do
you agree?
According to the code you've shown, it should be fine for rk3288 I 
guess
but not for rk3399. Please note that it's grf soc_con6 register for 
rk3288

but grf soc_con20 for rk3399.

Arnaud

Exactly, which is why you had that if defined() in your diff, to compile
one part of the code for RK3288, and the other for RK3399. :) The bit
though happens to be the same.

[PATCH 1/2] rockchip: rk3308: allow loading larger kernel Image

[Andy Yan]

When compile the curren mainline linux kernel(Linux 5.5-rc3)
with defconfig, the final Image is 29M, it's much
larger than Linux 5.4.

On the current u-boot side on rk3308, the gap between
kernel and fdt is 25M, the fdt will overwrite kernel
Image, so move ftd to a higher memory to give 34M
gab for them.

Signed-off-by: Andy Yan 
---

 include/configs/rk3308_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index a67d3d7d1b..bd9ac826f3 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -42,7 +42,7 @@
 #define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x0050\0" \
"pxefile_addr_r=0x0060\0" \
-   "fdt_addr_r=0x01f0\0" \
+   "fdt_addr_r=0x0280\0" \
"kernel_addr_r=0x0068\0" \
"ramdisk_addr_r=0x0400\0"
 
-- 
2.17.1

[PATCH 2/2] doc: rockchip: Fix reference the wrong defconfig name of ROC-CC-RK3308

[Andy Yan]

The defconfig file for ROC-CC-RK3308 is roc-cc-rk3308_defconfig.

Fixes: 7f08bfb74f04 ("doc: rockchip: Add documentation for rk3308 based
boards")

Signed-off-by: Andy Yan 
---

 doc/README.rockchip | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/doc/README.rockchip b/doc/README.rockchip
index dae4ebc8e4..ffab8ff417 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -50,7 +50,7 @@ Two RK3036 boards are supported:
 Two RK3308 boards are supported:
 
- EVB RK3308 - use evb-rk3308 configuration
-   - ROC-CC-RK3308 - use roc-rk3308-cc configuration
+   - ROC-CC-RK3308 - use roc-cc-rk3308 configuration
 
 Two RK3328 board are supported:
 
@@ -106,7 +106,7 @@ For example:
- Compile U-Boot
  => cd /path/to/u-boot
  => export BL31=/path/to/rkbin/bin/rk33/rk3308_bl31_v2.22.elf
- => make roc-rk3308-cc_defconfig
+ => make roc-cc-rk3308_defconfig
  => make CROSS_COMPILE=aarch64-linux-gnu- all
  => ./tools/mkimage -n rk3308 -T rksd -d 
/path/to/rkbin/bin/rk33/rk3308_ddr_589MHz_uart2_m0_v1.26.bin idbloader.img
  => cat spl/u-boot-spl.bin  >> idbloader.img
-- 
2.17.1

Re: [U-Boot] [PATCH v2 1/5] clk_rv1108: Sync with vendor tree

[Andy Yan]

Hi

On 2018/11/21 上午2:55, Otavio Salvador wrote:

Make adjustments to the rv1108 clock driver in order to align it
with the internal Rockchip version.

Signed-off-by: Otavio Salvador 
---

Changes in v2: None

  .../include/asm/arch-rockchip/cru_rv1108.h| 143 +-
  drivers/clk/rockchip/clk_rv1108.c | 457 +-
  include/dt-bindings/clock/rv1108-cru.h| 154 --
  3 files changed, 706 insertions(+), 48 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h 
b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h
index 3cc2ed0187..4ce8caa40f 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h
@@ -11,7 +11,11 @@
  #define OSC_HZ(24 * 1000 * 1000)
  
  #define APLL_HZ		(600 * 100)

-#define GPLL_HZ(594 * 100)
+#define GPLL_HZ(1188 * 100)
+#define ACLK_PERI_HZ   (14850)
+#define HCLK_PERI_HZ   (14850)
+#define PCLK_PERI_HZ   (7425)
+#define ACLK_BUS_HZ(14850)
  
  struct rv1108_clk_priv {

struct rv1108_cru *cru;
@@ -80,6 +84,11 @@ enum {
WORK_MODE_NORMAL= 1,
DSMPD_SHIFT = 3,
DSMPD_MASK  = 1 << DSMPD_SHIFT,
+   INTEGER_MODE= 1,
+   GLOBAL_POWER_DOWN_SHIFT = 0,
+   GLOBAL_POWER_DOWN_MASK  = 1 << GLOBAL_POWER_DOWN_SHIFT,
+   GLOBAL_POWER_DOWN   = 1,
+   GLOBAL_POWER_UP = 0,
  
  	/* CLKSEL0_CON */

CORE_PLL_SEL_SHIFT  = 8,
@@ -90,11 +99,77 @@ enum {
CORE_CLK_DIV_SHIFT  = 0,
CORE_CLK_DIV_MASK   = 0x1f << CORE_CLK_DIV_SHIFT,
  
+	/* CLKSEL_CON1 */

+   PCLK_DBG_DIV_CON_SHIFT  = 4,
+   PCLK_DBG_DIV_CON_MASK   = 0xf << PCLK_DBG_DIV_CON_SHIFT,
+   ACLK_CORE_DIV_CON_SHIFT = 0,
+   ACLK_CORE_DIV_CON_MASK  = 7 << ACLK_CORE_DIV_CON_SHIFT,
+
+   /* CLKSEL_CON2 */
+   ACLK_BUS_PLL_SEL_SHIFT  = 8,
+   ACLK_BUS_PLL_SEL_MASK   = 3 << ACLK_BUS_PLL_SEL_SHIFT,
+   ACLK_BUS_PLL_SEL_GPLL   = 0,
+   ACLK_BUS_PLL_SEL_APLL   = 1,
+   ACLK_BUS_PLL_SEL_DPLL   = 2,
+   ACLK_BUS_DIV_CON_SHIFT  = 0,
+   ACLK_BUS_DIV_CON_MASK   = 0x1f << ACLK_BUS_DIV_CON_SHIFT,
+   ACLK_BUS_DIV_CON_WIDTH  = 5,
+
+   /* CLKSEL_CON3 */
+   PCLK_BUS_DIV_CON_SHIFT  = 8,
+   PCLK_BUS_DIV_CON_MASK   = 0x1f << PCLK_BUS_DIV_CON_SHIFT,
+   HCLK_BUS_DIV_CON_SHIFT  = 0,
+   HCLK_BUS_DIV_CON_MASK   = 0x1f,
+
+   /* CLKSEL_CON4 */
+   CLK_DDR_PLL_SEL_SHIFT   = 8,
+   CLK_DDR_PLL_SEL_MASK= 0x3 << CLK_DDR_PLL_SEL_SHIFT,
+   CLK_DDR_DIV_CON_SHIFT   = 0,
+   CLK_DDR_DIV_CON_MASK= 0x3 << CLK_DDR_DIV_CON_SHIFT,
+
+   /* CLKSEL_CON19 */
+   CLK_I2C1_PLL_SEL_SHIFT  = 15,
+   CLK_I2C1_PLL_SEL_MASK   = 1 << CLK_I2C1_PLL_SEL_SHIFT,
+   CLK_I2C1_PLL_SEL_DPLL   = 0,
+   CLK_I2C1_PLL_SEL_GPLL   = 1,
+   CLK_I2C1_DIV_CON_SHIFT  = 8,
+   CLK_I2C1_DIV_CON_MASK   = 0x7f << CLK_I2C1_DIV_CON_SHIFT,
+   CLK_I2C0_PLL_SEL_SHIFT  = 7,
+   CLK_I2C0_PLL_SEL_MASK   = 1 << CLK_I2C0_PLL_SEL_SHIFT,
+   CLK_I2C0_DIV_CON_SHIFT  = 0,
+   CLK_I2C0_DIV_CON_MASK   = 0x7f,
+   I2C_DIV_CON_WIDTH   = 7,
+
+   /* CLKSEL_CON20 */
+   CLK_I2C3_PLL_SEL_SHIFT  = 15,
+   CLK_I2C3_PLL_SEL_MASK   = 1 << CLK_I2C3_PLL_SEL_SHIFT,
+   CLK_I2C3_PLL_SEL_DPLL   = 0,
+   CLK_I2C3_PLL_SEL_GPLL   = 1,
+   CLK_I2C3_DIV_CON_SHIFT  = 8,
+   CLK_I2C3_DIV_CON_MASK   = 0x7f << CLK_I2C3_DIV_CON_SHIFT,
+   CLK_I2C2_PLL_SEL_SHIFT  = 7,
+   CLK_I2C2_PLL_SEL_MASK   = 1 << CLK_I2C2_PLL_SEL_SHIFT,
+   CLK_I2C2_DIV_CON_SHIFT  = 0,
+   CLK_I2C2_DIV_CON_MASK   = 0x7f,
+
/* CLKSEL_CON22 */
CLK_SARADC_DIV_CON_SHIFT= 0,
CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
CLK_SARADC_DIV_CON_WIDTH= 10,
  
+	/* CLKSEL_CON23 */

+   ACLK_PERI_PLL_SEL_SHIFT = 15,
+   ACLK_PERI_PLL_SEL_MASK  = 1 << ACLK_PERI_PLL_SEL_SHIFT,
+   ACLK_PERI_PLL_SEL_GPLL  = 0,
+   ACLK_PERI_PLL_SEL_DPLL  = 1,
+   PCLK_PERI_DIV_CON_SHIFT = 10,
+   PCLK_PERI_DIV_CON_MASK  = 0x1f << PCLK_PERI_DIV_CON_SHIFT,
+   HCLK_PERI_DIV_CON_SHIFT = 5,
+   HCLK_PERI_DIV_CON_MASK  = 0x1f << HCLK_PERI_DIV_CON_SHIFT,
+   ACLK_PERI_DIV_CON_SHIFT = 0,
+   ACLK_PERI_DIV_CON_MASK  = 0x1f,
+   PERI_DIV_CON_WIDTH  = 5,
+
/* CLKSEL24_CON */
MAC_PLL_SEL_SHIFT   = 12,
MAC_PLL_SEL_MASK= 1 << MAC_PLL_SEL_SHIFT,
@@ -105,6 +

Re: [U-Boot] [PATCH v2 2/5] rv1108: Enable BOUNCE_BUFFER

[Andy Yan]

Hi

On 2018/11/21 上午2:55, Otavio Salvador wrote:

In order to be able to build the Rockchip eMMC driver on rv1108, the
BOUNCE_BUFFER option needs to be selected. Select it like it is done
on the other Rockchip SoC common files.

Signed-off-by: Otavio Salvador 
---

Changes in v2:
- new patch

  include/configs/rv1108_common.h | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index 2ab3b85e0c..cc0384e2f4 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -17,6 +17,9 @@
  #define CONFIG_SYS_TIMER_BASE 0x10350020
  #define CONFIG_SYS_TIMER_COUNTER  (CONFIG_SYS_TIMER_BASE + 8)
  
+/* MMC/SD IP block */

+#define CONFIG_BOUNCE_BUFFER
+
  #define CONFIG_SYS_SDRAM_BASE 0x6000
  #define CONFIG_SYS_INIT_SP_ADDR   (CONFIG_SYS_TEXT_BASE + 
0x10)
  #define CONFIG_SYS_LOAD_ADDR  (CONFIG_SYS_SDRAM_BASE + 0x200)



Reviewed-by: Andy Yan 


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Re: [U-Boot] [PATCH v2 3/5] rv1108: Enable eMMC support

[Andy Yan]

Hi:

 The subject should be something like: "Arm: dts: rockchip: add emmc 
pinctrl for rv1108"


On 2018/11/21 上午2:55, Otavio Salvador wrote:

This adds the pinctrl handles to enable the use of eMMC on custom
boards (as minievk) and makes it easier for later addition.

Signed-off-by: Otavio Salvador 
---

Changes in v2:
- split bounce buffer change on a new patch

  arch/arm/dts/rv1108.dtsi | 29 +
  1 file changed, 29 insertions(+)

diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi
index acfd97e18d..23a44bfaca 100644
--- a/arch/arm/dts/rv1108.dtsi
+++ b/arch/arm/dts/rv1108.dtsi
@@ -427,6 +427,35 @@
};
};
  
+		emmc {

+   emmc_clk: emmc-clk {
+   rockchip,pins = <2 RK_PB6 RK_FUNC_1 
&pcfg_pull_none_drv_8ma>;
+   };
+
+   emmc_cmd: emmc-cmd {
+   rockchip,pins = <2 RK_PB4 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>;
+   };
+
+   emmc_pwren: emmc-pwren {
+   rockchip,pins = <2 RK_PC2 RK_FUNC_2 
&pcfg_pull_none>;
+   };
+
+   emmc_bus1: emmc-bus1 {
+   rockchip,pins = <2 RK_PA0 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>;
+   };
+
+   emmc_bus8: emmc-bus8 {
+   rockchip,pins = <2 RK_PA0 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>,
+   <2 RK_PA1 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>,
+   <2 RK_PA2 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>,
+   <2 RK_PA3 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>,
+   <2 RK_PA4 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>,
+   <2 RK_PA5 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>,
+   <2 RK_PA6 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>,
+   <2 RK_PA7 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>;
+   };
+   };
+
sdmmc {
sdmmc_clk: sdmmc-clk {
rockchip,pins = <3 RK_PC4 RK_FUNC_1 
&pcfg_pull_none_drv_4ma>;


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Re: [U-Boot] [PATCH v2 4/5] rv1108: Make USB OTG functional

[Andy Yan]

Hi:

On 2018/11/21 上午2:55, Otavio Salvador wrote:

Like it is done for other Rockchip SoCs, introduce a board_usb_init()
function so that USB OTG can be functional on rv1108 too.

Signed-off-by: Otavio Salvador 
---

Changes in v2: None

  arch/arm/dts/rv1108.dtsi  | 45 ++-
  arch/arm/mach-rockchip/Makefile   |  1 +
  arch/arm/mach-rockchip/rv1108-board.c | 81 +++
  3 files changed, 124 insertions(+), 3 deletions(-)
  create mode 100644 arch/arm/mach-rockchip/rv1108-board.c



It's better to split dtsi and .c file



diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi
index 23a44bfaca..215d885225 100644
--- a/arch/arm/dts/rv1108.dtsi
+++ b/arch/arm/dts/rv1108.dtsi
@@ -121,8 +121,35 @@
};
  
  	grf: syscon@1030 {

-   compatible = "rockchip,rv1108-grf", "syscon";
+   compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
reg = <0x1030 0x1000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   u2phy: usb2-phy@100 {
+   compatible = "rockchip,rv1108-usb2phy";
+   reg = <0x100 0x0c>;
+   clocks = <&cru SCLK_USBPHY>;
+   clock-names = "phyclk";
+   #clock-cells = <0>;
+   clock-output-names = "usbphy";
+   rockchip,usbgrf = <&usbgrf>;
+   status = "disabled";
+
+   u2phy_otg: otg-port {
+   interrupts = ;
+   interrupt-names = "otg-mux";
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+
+   u2phy_host: host-port {
+   interrupts = ;
+   interrupt-names = "linestate";
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+   };
};
  
  	saradc: saradc@1038c000 {

@@ -141,6 +168,11 @@
reg = <0x2006 0x1000>;
};
  
+	usbgrf: syscon@202a {

+   compatible = "rockchip,rv1108-usbgrf", "syscon";
+   reg = <0x202a 0x1000>;
+   };
+
cru: clock-controller@2020 {
compatible = "rockchip,rv1108-cru";
reg = <0x2020 0x1000>;
@@ -200,12 +232,19 @@
};
  
  	usb20_otg: usb@3018 {

-   compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb",
+   compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
 "snps,dwc2";
reg = <0x3018 0x4>;
interrupts = ;
-   hnp-srp-disable;
+   clocks = <&cru HCLK_OTG>;
+   clock-names = "otg";
dr_mode = "otg";
+   g-np-tx-fifo-size = <16>;
+   g-rx-fifo-size = <280>;
+   g-tx-fifo-size = <256 128 128 64 32 16>;
+   g-use-dma;
+   phys = <&u2phy_otg>;
+   phy-names = "usb2-phy";
status = "disabled";
};
  
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile

index 05706c472a..368302e1da 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
  obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
  obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
  obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o
+obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108-board.o
  endif
  
  obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o

diff --git a/arch/arm/mach-rockchip/rv1108-board.c 
b/arch/arm/mach-rockchip/rv1108-board.c
new file mode 100644
index 00..3412f2c063
--- /dev/null
+++ b/arch/arm/mach-rockchip/rv1108-board.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include 
+#include 
+
+static struct dwc2_plat_otg_data rv1108_otg_data = {
+   .rx_fifo_sz = 512,
+   .np_tx_fifo_sz  = 16,
+   .tx_fifo_sz = 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+   const void *blob = gd->fdt_blob;
+   bool matched = false;
+   int node, phy_node;
+   u32 grf_phy_offset;
+   const char *mode;
+
+   /* find the usb_otg node */
+   node = fdt_node_offset_by_compatible(blob, -1, "rockchip,rk3066-usb");
+   while (node > 0) {
+   mode = fdt_getprop(blob, node, "dr_mode", NULL);
+   if (mode && strcmp(mode, "otg") == 0) {
+   matched = true;
+   break;
+   }
+
+   node = fdt_node_offset_by_compat

Re: [U-Boot] [PATCH v2 5/5] rv1108: Add support for default distro_bootcmd

[Andy Yan]

Hi:

On 2018/11/21 上午2:55, Otavio Salvador wrote:

This allow easier integration of RV1108 based boards on generic
distributions and build systems.

Signed-off-by: Otavio Salvador 
---

Changes in v2: None

  include/configs/rv1108_common.h | 15 +++
  1 file changed, 15 insertions(+)

diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index cc0384e2f4..16d4e2e355 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -28,3 +28,18 @@
  #define CONFIG_USB_OHCI_NEW
  #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS1
  #endif
+
+#ifndef CONFIG_SPL_BUILD
+#define ENV_MEM_LAYOUT_SETTINGS \
+   "scriptaddr=0x6000\0" \
+   "fdt_addr_r=0x61f0\0" \
+   "kernel_addr_r=0x6200\0" \
+   "ramdisk_addr_r=0x6400\0"
+
+#include 
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   ENV_MEM_LAYOUT_SETTINGS \
+   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+   "partitions=" PARTS_DEFAULT \
+   BOOTENV
+#endif



Reviewed-by: Andy Yan 


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Re: [U-Boot] [PATCH v2 3/5] rv1108: Enable eMMC support

[Andy Yan]

Hi:

On 2018/11/27 上午12:18, Otavio Salvador wrote:

On Tue, Nov 20, 2018 at 4:56 PM Otavio Salvador  wrote:

This adds the pinctrl handles to enable the use of eMMC on custom
boards (as minievk) and makes it easier for later addition.

Signed-off-by: Otavio Salvador 

Andy, did you review it? Is there someone which would be more
appropriate for me to send the patches?



Thte whole series will to through Dr. Philipp Tomsich





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Re: [U-Boot] [PATCH v3 0/9] Stop AXP from crashing when enabling LDO3

[Andy Yan]

Hi:
Priit Laes  于2018年11月22日周四 上午2:06写道：

> This is a resend/v2 of a "Stop AXP from crashing when enabling LDO3"
> series,
> posted by Olliver Schinagl in March 2017. Unfortunately it never got past
> initial discussion [1], but most Olimex Lime2 boards are still running
> into this bug.
>
> When powering up an AXP209, the default value for LDO3 output is enabled.
> This
> works fine. However if for whatever reason, LDO3 is disabled, for example
> by OS
> during reboot and u-boot enables LDO3 again, the PMIC shuts down (without
> setting an interrupt) causing the board to hang. This behavior has been
> seen
> from Linux as well, u-boot disables LDO3 as a default value, the kernel
> enables
> it per its DTS, the kernel hangs as the PMIC gets shut down.
>
> The root cause is that some boards have too high capacitance on the LDO3
> output
> port causing inrush currents exceeding the maximum of the AXP209.
>
> The fix is to turn on the LDO3 at the lowest possible voltage and then set
> the
> final voltage.
>
> If the capacitance is really big (due to a connected device for example)
> the
> AXP209 also features VRC, or Voltage Rate Control, allowing voltage to
> ramp up
> even slower.
>
> Similar changes need to be also implemented in the operating system driver
> side when driver needs to toggle power for the ALDO3 regulator.
>
> This patch series implements the above with a few tiny cleanups.
>
> The initial discussion with some scope screenshots can be found in the
> linux-sunxi mailing list [0].
>
> And the initial series were posted to u-boot mailing list [1].
>
> Signed-off-by: Olliver Schinagl 
> Signed-off-by: Priit Laes 
>
> [0] https://groups.google.com/forum/m/#!topic/linux-sunxi/EDvEsbHHqQI
> [1] https://lists.denx.de/pipermail/u-boot/2017-March/282789.html
>
> --
> Changes since v2:
> - Collected Acked-by tags, patches 1,3-5 are now ripe for picking.
> - Olliver fixed wrong code in patch 2, thanks for Maxime for spotting
> - Fixed checkpatch error in patch 5
> - Expanded commit message for patch 6
>
> Changes from initial submission:
> - Rebased on top of latest master and fixed conflicts
> - Added comments about datasheet errors for patch 6
> - Fixed some typos and checkpatch errors
> - Added patch to Olimex Lime2 eMMC board
>
> Olliver Schinagl (8):
>   sunxi: board: Print error after power initialization fails
>   sunxi: pmic_bus: Decrease boot time by not writing duplicate data
>   power: axp209: Use BIT() macro
>   power: axp209: Define the chip version mask
>   power: axp209: Reduce magic values by adding defines for LDO[234]
>   power: axp209: Add support for voltage rate control on LDO3
>   power: axp209: Limit inrush current for broken boards
>   arm: sunxi: Reduce inrush current on Olimex OLinuXino-A20-Lime2
>
> Priit Laes (1):
>   arm: sunxi: Reduce inrush current on Olimex OLinuXino-A20-Lime2-eMMC
>
>  arch/arm/mach-sunxi/pmic_bus.c |  6 ++-
>  board/sunxi/board.c| 18 +++---
>  configs/A20-OLinuXino-Lime2-eMMC_defconfig |  2 +-
>  configs/A20-OLinuXino-Lime2_defconfig  |  2 +-
>  drivers/power/Kconfig  | 43 ++-
>  drivers/power/axp209.c | 66 ++
>  include/axp209.h   | 70 +--
>  7 files changed, 172 insertions(+), 35 deletions(-)
>
> base-commit: a3e1653ddeb02f39481eba572275016171e9670c
>


I also play with a Lime2-eMMC board(rev K) these days,  but I found this
board could do reboot whatevery in u-boot or kernel when it boot from
emmc.  But it reboot well when it boot from sdcard.

 root@lime2:~#
root@lime2:~#
root@lime2:~#
root@lime2:~# reboot
[ 2089.632091] reboot: Restarting system

Can't see any further reboot log. unless i replug the power jack.





When I do reset from u-boot , it failed too:

Boot SPL 2018.05-armbian (Nov 28 2018 - 14:39:04 +0800)
DRAM: 3/2/2
Trying to boot from MMC2


U-ready
DRAM:  1 GiB
MMC:   SUNXI MMC: 1
Loading Environment from EXT4... MMC: no card present
** Bad device mmc 0 **
In:serial
Out:   serial
Err:   serial
Allwinner mUSB OTG (Peripheral)
SCSI:  SATA link 0 timeout.
A: ethernet@01c5
Warning: usb_ether using MAC address from ROM
, eth1: usb_ether
MMC: no card present
** Bad device mmc 0 **
us 0 for devices... 1 USB Device(s) found
scan1 USB Device(s) found
   scaswitch to partitions #0, OK
mmc1(part MMC: no card present
=> 
=>
=> reset
resetting ...

I post these here hope to know if anyone meet the same situtation.


-- 
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Re: [U-Boot] [PATCH v3 0/9] Stop AXP from crashing when enabling LDO3

[Andy Yan]

Hi :
Andy Yan  于2018年11月28日周三 下午7:10写道：

> Hi:
> Priit Laes  于2018年11月22日周四 上午2:06写道：
>
>> This is a resend/v2 of a "Stop AXP from crashing when enabling LDO3"
>> series,
>> posted by Olliver Schinagl in March 2017. Unfortunately it never got past
>> initial discussion [1], but most Olimex Lime2 boards are still running
>> into this bug.
>>
>> When powering up an AXP209, the default value for LDO3 output is enabled.
>> This
>> works fine. However if for whatever reason, LDO3 is disabled, for example
>> by OS
>> during reboot and u-boot enables LDO3 again, the PMIC shuts down (without
>> setting an interrupt) causing the board to hang. This behavior has been
>> seen
>> from Linux as well, u-boot disables LDO3 as a default value, the kernel
>> enables
>> it per its DTS, the kernel hangs as the PMIC gets shut down.
>>
>> The root cause is that some boards have too high capacitance on the LDO3
>> output
>> port causing inrush currents exceeding the maximum of the AXP209.
>>
>> The fix is to turn on the LDO3 at the lowest possible voltage and then
>> set the
>> final voltage.
>>
>> If the capacitance is really big (due to a connected device for example)
>> the
>> AXP209 also features VRC, or Voltage Rate Control, allowing voltage to
>> ramp up
>> even slower.
>>
>> Similar changes need to be also implemented in the operating system driver
>> side when driver needs to toggle power for the ALDO3 regulator.
>>
>> This patch series implements the above with a few tiny cleanups.
>>
>> The initial discussion with some scope screenshots can be found in the
>> linux-sunxi mailing list [0].
>>
>> And the initial series were posted to u-boot mailing list [1].
>>
>> Signed-off-by: Olliver Schinagl 
>> Signed-off-by: Priit Laes 
>>
>> [0] https://groups.google.com/forum/m/#!topic/linux-sunxi/EDvEsbHHqQI
>> [1] https://lists.denx.de/pipermail/u-boot/2017-March/282789.html
>>
>> --
>> Changes since v2:
>> - Collected Acked-by tags, patches 1,3-5 are now ripe for picking.
>> - Olliver fixed wrong code in patch 2, thanks for Maxime for spotting
>> - Fixed checkpatch error in patch 5
>> - Expanded commit message for patch 6
>>
>> Changes from initial submission:
>> - Rebased on top of latest master and fixed conflicts
>> - Added comments about datasheet errors for patch 6
>> - Fixed some typos and checkpatch errors
>> - Added patch to Olimex Lime2 eMMC board
>>
>> Olliver Schinagl (8):
>>   sunxi: board: Print error after power initialization fails
>>   sunxi: pmic_bus: Decrease boot time by not writing duplicate data
>>   power: axp209: Use BIT() macro
>>   power: axp209: Define the chip version mask
>>   power: axp209: Reduce magic values by adding defines for LDO[234]
>>   power: axp209: Add support for voltage rate control on LDO3
>>   power: axp209: Limit inrush current for broken boards
>>   arm: sunxi: Reduce inrush current on Olimex OLinuXino-A20-Lime2
>>
>> Priit Laes (1):
>>   arm: sunxi: Reduce inrush current on Olimex OLinuXino-A20-Lime2-eMMC
>>
>>  arch/arm/mach-sunxi/pmic_bus.c |  6 ++-
>>  board/sunxi/board.c| 18 +++---
>>  configs/A20-OLinuXino-Lime2-eMMC_defconfig |  2 +-
>>  configs/A20-OLinuXino-Lime2_defconfig  |  2 +-
>>  drivers/power/Kconfig  | 43 ++-
>>  drivers/power/axp209.c | 66 ++
>>  include/axp209.h   | 70 +--
>>  7 files changed, 172 insertions(+), 35 deletions(-)
>>
>> base-commit: a3e1653ddeb02f39481eba572275016171e9670c
>>
>
>
> I also play with a Lime2-eMMC board(rev K) these days,  but I found this
> board could do reboot whatevery in u-boot or kernel when it boot from
> emmc.  But it reboot well when it boot from sdcard.
>
>
Sorry I mean this board couldn't do reboot from kernel or u-boot here .


>  root@lime2:~#
> root@lime2:~#
> root@lime2:~#
> root@lime2:~# reboot
> [ 2089.632091] reboot: Restarting system
>
> Can't see any further reboot log. unless i replug the power jack.
>
>
>
>
>
> When I do reset from u-boot , it failed too:
>
> Boot SPL 2018.05-armbian (Nov 28 2018 - 14:39:04 +0800)
> DRAM: 3/2/2
> Trying to boot from MMC2
>
>
> U-ready
> DRAM:  1 GiB
> MMC:   SUNXI MMC: 1
> Loading Environment from EXT4... MMC: no card present
> ** Bad device mmc 0 **
> In:serial
> Out:   serial
> Err

Re: [U-Boot] [PATCH v3 0/9] Stop AXP from crashing when enabling LDO3

[Andy Yan]

Hi :
Priit Laes  于2018年11月28日周三 下午10:23写道：

> On Wed, Nov 28, 2018 at 08:23:37PM +0800, Andy Yan wrote:
> > Hi :
> > Andy Yan  于2018年11月28日周三 下午7:10写道：
> >
> > > Hi:
> > > Priit Laes  于2018年11月22日周四 上午2:06写道：
> > >
> > >> This is a resend/v2 of a "Stop AXP from crashing when enabling LDO3"
> > >> series,
> > >> posted by Olliver Schinagl in March 2017. Unfortunately it never got
> past
> > >> initial discussion [1], but most Olimex Lime2 boards are still running
> > >> into this bug.
> > >>
> > >> When powering up an AXP209, the default value for LDO3 output is
> enabled.
> > >> This
> > >> works fine. However if for whatever reason, LDO3 is disabled, for
> example
> > >> by OS
> > >> during reboot and u-boot enables LDO3 again, the PMIC shuts down
> (without
> > >> setting an interrupt) causing the board to hang. This behavior has
> been
> > >> seen
> > >> from Linux as well, u-boot disables LDO3 as a default value, the
> kernel
> > >> enables
> > >> it per its DTS, the kernel hangs as the PMIC gets shut down.
> > >>
> > >> The root cause is that some boards have too high capacitance on the
> LDO3
> > >> output
> > >> port causing inrush currents exceeding the maximum of the AXP209.
> > >>
> > >> The fix is to turn on the LDO3 at the lowest possible voltage and then
> > >> set the
> > >> final voltage.
> > >>
> > >> If the capacitance is really big (due to a connected device for
> example)
> > >> the
> > >> AXP209 also features VRC, or Voltage Rate Control, allowing voltage to
> > >> ramp up
> > >> even slower.
> > >>
> > >> Similar changes need to be also implemented in the operating system
> driver
> > >> side when driver needs to toggle power for the ALDO3 regulator.
> > >>
> > >> This patch series implements the above with a few tiny cleanups.
> > >>
> > >> The initial discussion with some scope screenshots can be found in the
> > >> linux-sunxi mailing list [0].
> > >>
> > >> And the initial series were posted to u-boot mailing list [1].
> > >>
> > >> Signed-off-by: Olliver Schinagl 
> > >> Signed-off-by: Priit Laes 
> > >>
> > >> [0] https://groups.google.com/forum/m/#!topic/linux-sunxi/EDvEsbHHqQI
> > >> [1] https://lists.denx.de/pipermail/u-boot/2017-March/282789.html
> > >>
> > >> --
> > >> Changes since v2:
> > >> - Collected Acked-by tags, patches 1,3-5 are now ripe for picking.
> > >> - Olliver fixed wrong code in patch 2, thanks for Maxime for spotting
> > >> - Fixed checkpatch error in patch 5
> > >> - Expanded commit message for patch 6
> > >>
> > >> Changes from initial submission:
> > >> - Rebased on top of latest master and fixed conflicts
> > >> - Added comments about datasheet errors for patch 6
> > >> - Fixed some typos and checkpatch errors
> > >> - Added patch to Olimex Lime2 eMMC board
> > >>
> > >> Olliver Schinagl (8):
> > >>   sunxi: board: Print error after power initialization fails
> > >>   sunxi: pmic_bus: Decrease boot time by not writing duplicate data
> > >>   power: axp209: Use BIT() macro
> > >>   power: axp209: Define the chip version mask
> > >>   power: axp209: Reduce magic values by adding defines for LDO[234]
> > >>   power: axp209: Add support for voltage rate control on LDO3
> > >>   power: axp209: Limit inrush current for broken boards
> > >>   arm: sunxi: Reduce inrush current on Olimex OLinuXino-A20-Lime2
> > >>
> > >> Priit Laes (1):
> > >>   arm: sunxi: Reduce inrush current on Olimex OLinuXino-A20-Lime2-eMMC
> > >>
> > >>  arch/arm/mach-sunxi/pmic_bus.c |  6 ++-
> > >>  board/sunxi/board.c| 18 +++---
> > >>  configs/A20-OLinuXino-Lime2-eMMC_defconfig |  2 +-
> > >>  configs/A20-OLinuXino-Lime2_defconfig  |  2 +-
> > >>  drivers/power/Kconfig  | 43 ++-
> > >>  drivers/power/axp209.c | 66
> ++
> > >>  include/axp209.h   | 70
> +--
> > >>  7 files changed, 172 ins

[U-Boot] [PATCH] image-fdt: reserve lmb for fdt

[Andy Yan]

Memory region for fdt should be reserved, or they
may be allocated by other module via lmb_alloc.
Then the fdt data will be destroy.

We found a case on a board with 64MB DRAM like bellow:

No ethernet found.
Hit any key to stop autoboot:  0
ANDROID: reboot reason: "recovery"
FDT load addr 0x10f0 size 41 KiB
Booting kernel at 0x2008000 with fdt at 2c8ac00...

lmb_add base:0x58000 size:0x3fa8000
lmb_add base:0x0 size:0x0
lmb_reserve base:0x34ca2a0 size:0xb35d60
  Booting Android Image at 0x02008000 ...
Kernel load addr 0x02008800 size 3808 KiB
RAM disk load addr 0x1100 size 9000 KiB
*  fdt: cmdline image address = 0x02c8ac00
  Checking for 'FDT'/'FDT Image' at 02c8ac00
*  fdt: raw FDT blob
   Flattened Device Tree blob at 02c8ac00
   Booting using the fdt blob at 0x2c8ac00
   of_flat_tree at 0x02c8ac00 size 0x9d6d
   XIP Kernel Image ... OK
do_bootm_states reserve: 0x2008800 -- 0x3b7c30
lmb_reserve base:0x2008800 size:0x3b7c30
no initrd_high
env_get_bootm_size size:66748416(0x3fa8000) tmp:360448(0x58000)
start:360448(0x58000)
   initrd_high = 0x03fa8000, copy_to_ram = 1
   Loading Ramdisk to 02c0, end 034c9d09 ... OK
ERROR: image is not a fdt - must RESET the board to recover.
FDT creation failed! hanging...### ERROR ### Please RESET the board ###

Signed-off-by: Andy Yan 
---

 common/image-fdt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/common/image-fdt.c b/common/image-fdt.c
index 9b41f16248..56f6d7e26b 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -422,6 +422,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], 
uint8_t arch,
 
*of_flat_tree = fdt_blob;
*of_size = fdt_totalsize(fdt_blob);
+   lmb_reserve(&images->lmb, (ulong)*of_flat_tree, *of_size);
debug("   of_flat_tree at 0x%08lx size 0x%08lx\n",
  (ulong)*of_flat_tree, *of_size);
 
-- 
2.17.1


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Re: [U-Boot] [PATCH] image-fdt: reserve lmb for fdt

[Andy Yan]

ping

Andy Yan  于2018年8月7日周二 下午7:43写道：

> Memory region for fdt should be reserved, or they
> may be allocated by other module via lmb_alloc.
> Then the fdt data will be destroy.
>
> We found a case on a board with 64MB DRAM like bellow:
>
> No ethernet found.
> Hit any key to stop autoboot:  0
> ANDROID: reboot reason: "recovery"
> FDT load addr 0x10f0 size 41 KiB
> Booting kernel at 0x2008000 with fdt at 2c8ac00...
>
> lmb_add base:0x58000 size:0x3fa8000
> lmb_add base:0x0 size:0x0
> lmb_reserve base:0x34ca2a0 size:0xb35d60
>   Booting Android Image at 0x02008000 ...
> Kernel load addr 0x02008800 size 3808 KiB
> RAM disk load addr 0x1100 size 9000 KiB
> *  fdt: cmdline image address = 0x02c8ac00
>   Checking for 'FDT'/'FDT Image' at 02c8ac00
> *  fdt: raw FDT blob
>Flattened Device Tree blob at 02c8ac00
>Booting using the fdt blob at 0x2c8ac00
>of_flat_tree at 0x02c8ac00 size 0x9d6d
>XIP Kernel Image ... OK
> do_bootm_states reserve: 0x2008800 -- 0x3b7c30
> lmb_reserve base:0x2008800 size:0x3b7c30
> no initrd_high
> env_get_bootm_size size:66748416(0x3fa8000) tmp:360448(0x58000)
> start:360448(0x58000)
>initrd_high = 0x03fa8000, copy_to_ram = 1
>Loading Ramdisk to 02c0, end 034c9d09 ... OK
> ERROR: image is not a fdt - must RESET the board to recover.
> FDT creation failed! hanging...### ERROR ### Please RESET the board ###
>
> Signed-off-by: Andy Yan 
> ---
>
>  common/image-fdt.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/common/image-fdt.c b/common/image-fdt.c
> index 9b41f16248..56f6d7e26b 100644
> --- a/common/image-fdt.c
> +++ b/common/image-fdt.c
> @@ -422,6 +422,7 @@ int boot_get_fdt(int flag, int argc, char * const
> argv[], uint8_t arch,
>
> *of_flat_tree = fdt_blob;
> *of_size = fdt_totalsize(fdt_blob);
> +   lmb_reserve(&images->lmb, (ulong)*of_flat_tree, *of_size);
> debug("   of_flat_tree at 0x%08lx size 0x%08lx\n",
>   (ulong)*of_flat_tree, *of_size);
>
> --
> 2.17.1
>
>
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Re: [U-Boot] [U-Boot, 2/2] rockchip: Drop call to rockchip_dnl_mode_check() for now【请注意，邮件由u-boot-boun...@lists.denx.de代发】

[Andy Yan]

Hi Philipp:

    Sorry for the late reply, we just come back from the Chinese Spring 
Festival.


On 2019/2/1 下午6:26, Philipp Tomsich wrote:

Kever,

Independent of whether we revert this for the current cycle (and also 
independent of
if I ever find the other patch you had been referring to — I couldn’t 
find it in my local
mailing list archive) and then deprecate it for the next release 
(unless converted to
DM), we still have a number of architectural issues that need to be 
addressed:


I still doubt  is this a right  work-flow for patch apply. Before we  
apply  a patch  which will break many other boards , should we  make 
sure there is a solution patch applied for these boars first?




1.This really should be a driver under DTS control.
2.We need to not get away from configuring SOM-specific addresses via 
Kconfig


Both these issues are technical debt that we’ve accumulated over the 
last 18 months

and need to address for the sake of future maintainability.
E.g. ‘setting an address to 0x0 via Kconfig to disable a 
driver/feature’ really isn’t in line

with the architectural direction of U-Boot.

For technical side, I think CONFIG_ROCKCHIP_BOOT_MODE_REG is necessary 
here, we will read this register from save_boot_params when we get out 
from bootrom,  the dtb is not available at this point.


On the other hand, almost rockchip based products use a recovery key to 
enter download(upgrade)mode, this is a muti-funtion key, most of them 
reuse with vol+- key,  we would like the u-boot share


dtb with linux kernel. To keep the linux kernel dts as clean as possible 
,we don't want to add another dts property to describe this key either. 
This is why I implement function rockchip_dnl_key_pressed as __weak.



I don’t have my own house completely in order (I’ve been talking for a 
year now about
finally wrapping the RGMII/GMII selection into an ioctl-call to a 
driver) yet, but that doesn’t

mean that we we should delay this clean-up more than absolutely necessary.

Thanks,
Philipp.

On 01.02.2019, at 10:34, Philipp Tomsich 
> wrote:




On 01.02.2019, at 10:32, Kever Yang > wrote:


Hi Philipp,

   This is not right,  this patch should not merged like this!!!

   I have give my review comment in previous mail, and this will break
many boards.

   My another patch do not break anything, but you insist NAK it
without acceptable reason;


What other patch?
I don’t remember seeing that one...


   This patch definitely break other board and I have comment it, but
you just ignore other people's review and merge it, good job!

Thanks,
- Kever
On 02/01/2019 05:12 AM, Philipp Tomsich wrote:

This function causes a 5-second delay and stops the display working on
minnie. This code should be in a driver and should only be enabled by
a device-tree property, so that it does not affect devices which 
do not

have this feature.

Signed-off-by: Simon Glass >
Reviewed-by: Philipp Tomsich 
>

---

arch/arm/mach-rockchip/boot_mode.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)


Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH 05/18] rockchip: Add mention of other boards

[Andy Yan]

Hi Simon:

Simon Glass  于2019年1月10日周四 下午12:30写道：

> At present some Rockchip SoCs and boards are not mentioned in the README.
> So that people can see which SoCs are supported, expand the list to
> include everything.
>
> Signed-off-by: Simon Glass 
> ---
>
>  doc/README.rockchip | 43 +--
>  1 file changed, 41 insertions(+), 2 deletions(-)
>
> diff --git a/doc/README.rockchip b/doc/README.rockchip
> index 51b00a9d85..2b24ce8c06 100644
> --- a/doc/README.rockchip
> +++ b/doc/README.rockchip
> @@ -34,23 +34,62 @@ You will need:
>  Building
>  
>
> -At present nine RK3288 boards are supported:
> +At present 12 RK3288 boards are supported:
>
> - EVB RK3288 - use evb-rk3288 configuration
> - Fennec RK3288 - use fennec-rk3288 configuration
> - Firefly RK3288 - use firefly-rk3288 configuration
> - Hisense Chromebook - use chromebook_jerry configuration
> +   - Asus C100P Chromebook - use chromebook_minnie configuration
> +   - Asus Chromebit - use chromebook_mickey configuration
> - MiQi RK3288 - use miqi-rk3288 configuration
> - phyCORE-RK3288 RDK - use phycore-rk3288 configuration
> - PopMetal RK3288 - use popmetal-rk3288 configuration
> - Radxa Rock 2 - use rock2 configuration
> - Tinker RK3288 - use tinker-rk3288 configuration
> +   - Vyasa RK3288 - use vyasa-rk3288 configuration
>
> -Two RK3036 board are supported:
> +Two RK3036 boards are supported:
>
> - EVB RK3036 - use evb-rk3036 configuration
> - Kylin - use kylin_rk3036 configuration
>
> +One RK3328 board is supported:
> +
> +   - EVB RK3328
> +
> +Five RK3399 boards are supported (aarch64):
> +
> +   - EBV RK3399 - use evb_rk3399 configuration
> +   - Firefly RK3399 - use the same evb_rk3399 configuration
> +   - Puma - use puma_rk3399 configuration
> +   - Ficus - use ficus-rk3399 configuration
> +   - Rock960 (Vamrs) - use rock960-rk3399 configuration
> +
> +Four RK3368 boards are supported:
> +
> +   - Sheep - use sheep-rk3368 configuration
> +   - Lion - use lion-rk3368 configuration
> +   - Geekbox - use geekbox configuration
> +   - EVB PX5 - use evb-px5  configuration
> +
> +One RK3128 board is supported:
> +
> +   - EVB RK3128 - use evb-rk3128 configuration
> +
> +One RK3229 board is supported:
> +
> +   - EVB RK3229 - use evb-rk3229 configuration
> +
> +One RV1108 board is supported:
> +
> +   - Elgin R1 - use elgin-rv1108 configuration
>

We also  have an EVB for RV1108, see  board/rockchip/evb_rv1108/README

> +
> +One RV3188 baord is supported:
> +
> +   - Raxda Rock - use rock configuration
> +
> +
>  For example:
>
> CROSS_COMPILE=arm-linux-gnueabi- make O=firefly
> firefly-rk3288_defconfig all
> --
> 2.20.1.97.g81188d93c3-goog
>
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Re: [U-Boot] Rockchip RV1108 eMMC support not working

[Andy Yan]

Hi Otavio:
Otavio Salvador  于2018年10月9日周二 上午3:29写道：

> Hi,
>
> We have a custom board based on rv1108 evb where we are trying to add
> eMMC support.
>
> Here are the changes we made so far:
>
>  arch/arm/dts/rv1108-evb.dts | 45
> +
>  configs/evb-rv1108_defconfig|  4 
>  include/configs/evb_rv1108.h| 14 +
>  include/configs/rv1108_common.h |  3 +++
>  4 files changed, 53 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/dts/rv1108-evb.dts b/arch/arm/dts/rv1108-evb.dts
> index ccb9969..f07f402 100644
> --- a/arch/arm/dts/rv1108-evb.dts
> +++ b/arch/arm/dts/rv1108-evb.dts
> @@ -77,3 +77,48 @@
>  &usb_host_ohci {
>  status = "okay";
>  };
> +
> +&emmc {
> +pinctrl-names = "default";
> +pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
> +bus-width = <8>;
> +cap-mmc-highspeed;
> +supports-emmc;
> +disable-wp;
> +non-removable;
> +num-slots = <1>;
> +status = "okay";
> +};
> +
> +&pinctrl {
> +pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
> +bias-disable;
> +drive-strength = <8>;
> +};
> +
> +pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
> +bias-pull-up;
> +drive-strength = <8>;
> +};
> +
> +emmc {
> +emmc_clk: emmc-clk {
> +rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
> +};
> +
> +emmc_cmd: emmc-cmd {
> +rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
> +};
> +
> +emmc_bus8: emmc-bus8 {
> +rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
> +<2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
> +<2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
> +<2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
> +<2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
> +<2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
> +<2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
> +<2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
> +};
> +};
> +};
> diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig
> index 2ef041f..6c992c6 100644
> --- a/configs/evb-rv1108_defconfig
> +++ b/configs/evb-rv1108_defconfig
> @@ -14,10 +14,12 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
>  CONFIG_RANDOM_UUID=y
>  CONFIG_CMD_SF=y
>  CONFIG_CMD_USB=y
> +CONFIG_CMD_MMC=y
>  # CONFIG_CMD_SETEXPR is not set
>  CONFIG_CMD_CACHE=y
>  CONFIG_CMD_TIME=y
>  CONFIG_DEFAULT_DEVICE_TREE="rv1108-evb"
> +CONFIG_ENV_IS_IN_MMC=y
>  CONFIG_NET_RANDOM_ETHADDR=y
>  CONFIG_REGMAP=y
>  CONFIG_SYSCON=y
> @@ -27,6 +29,8 @@ CONFIG_FASTBOOT_BUF_SIZE=0x0800
>  CONFIG_FASTBOOT_FLASH=y
>  CONFIG_FASTBOOT_FLASH_MMC_DEV=1
>  CONFIG_ROCKCHIP_GPIO=y
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_ROCKCHIP=y
>  CONFIG_SYS_I2C_ROCKCHIP=y
>  CONFIG_SPI_FLASH=y
>  CONFIG_SPI_FLASH_BAR=y
> diff --git a/include/configs/evb_rv1108.h b/include/configs/evb_rv1108.h
> index 34739c7..aa6c4b0 100644
> --- a/include/configs/evb_rv1108.h
> +++ b/include/configs/evb_rv1108.h
> @@ -8,18 +8,6 @@
>
>  #include 
>
> -/*
> - * Default environment settings
> - */
> -#define CONFIG_EXTRA_ENV_SETTINGS   \
> -"netdev=eth0\0" \
> -"ipaddr=172.16.12.50\0" \
> -"serverip=172.16.12.69\0"\
> -""
> -#define CONFIG_BOOTCOMMAND\
> -"sf probe;"\
> -"sf read 0x6200 0x140800 0x50;"\
> -"dcache off;"\
> -"go 0x6200"
> +#define CONFIG_SYS_MMC_ENV_DEV0
>
>  #endif
> diff --git a/include/configs/rv1108_common.h
> b/include/configs/rv1108_common.h
> index 2ab3b85..cc0384e 100644
> --- a/include/configs/rv1108_common.h
> +++ b/include/configs/rv1108_common.h
> @@ -17,6 +17,9 @@
>  #define CONFIG_SYS_TIMER_BASE0x10350020
>  #define CONFIG_SYS_TIMER_COUNTER(CONFIG_SYS_TIMER_BASE + 8)
>
> +/* MMC/SD IP block */
> +#define CONFIG_BOUNCE_BUFFER
> +
>  #define CONFIG_SYS_SDRAM_BASE0x6000
>  #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_TEXT_BASE + 0x10)
>  #define CONFIG_SYS_LOAD_ADDR(CONFIG_SYS_SDRAM_BASE + 0x200)
> --
> 2.7.4
>
> With this change the eMMC driver is loaded:
>
> U-Boot 2018.11-rc1-00097-ge89d583-dirty (Oct 08 2018 - 16:11:40 -0300)
>
> Model: Rockchip RV1108 Evaluation board
> DRAM:  128 MiB
> APLL: 6 DPLL:12 GPLL:38400
> MMC:   dwmmc@3011: 0
> Loading Environment from MMC... *** Warning - bad CRC, using default
> environment
>
> In:serial@1021
> Out:   serial@1021
> Err:   serial@1021
> Model: Rockchip RV1108 Evaluation board
> Net:
> Warning: ethernet@3020 (eth0) using random MAC address -
> 5a:d2:06:ad:9e:ee
> eth0: ethernet@3020
> =>
>
> and we can also ch

Re: [U-Boot] Rockchip RV1108 eMMC support not working

[Andy Yan]

Hi Otavio:
I sent a mmc patch to you which I got from vincent, please have a
try.

Otavio Salvador  于2018年10月9日周二 上午10:21写道：

> Hello Andy,
>
> On Mon, Oct 8, 2018 at 11:03 PM Andy Yan  wrote:
> > Otavio Salvador  于2018年10月9日周二
> 上午3:29写道：
> > I don't have a 1108 board with emmc on my hand.
> >
> > the mmc info show that the eMMC has been detected. So would try other mmc
> > commands such as: mmc read/write ?
>
> => mmc read 0x6200 0 0x10
> MMC read: dev # 0, block # 0, count 16 ... 0 blocks read: ERROR
>
> > > => saveenv
> > > Saving Environment to MMC... Writing to MMC(0)... failed
> > > Failed (1)
> >
> >  Maybe you need a deeper dig to find the point where the error happen
>
> Any suggestion about what I might try to debug?
>
> --
> Otavio Salvador O.S. Systems
> http://www.ossystems.com.brhttp://code.ossystems.com.br
> Mobile: +55 (53) 9 9981-7854  Mobile: +1 (347) 903-9750
>
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Re: [U-Boot] [PATCH] image-fdt: reserve lmb for fdt

[Andy Yan]

Hi Simon:

Simon Glass  于2018年8月30日周四 上午8:42写道：

> On 7 August 2018 at 05:44, Andy Yan  wrote:
> > Memory region for fdt should be reserved, or they
> > may be allocated by other module via lmb_alloc.
> > Then the fdt data will be destroy.
> >
> > We found a case on a board with 64MB DRAM like bellow:
> >
> > No ethernet found.
> > Hit any key to stop autoboot:  0
> > ANDROID: reboot reason: "recovery"
> > FDT load addr 0x10f0 size 41 KiB
> > Booting kernel at 0x2008000 with fdt at 2c8ac00...
> >
> > lmb_add base:0x58000 size:0x3fa8000
> > lmb_add base:0x0 size:0x0
> > lmb_reserve base:0x34ca2a0 size:0xb35d60
> >   Booting Android Image at 0x02008000 ...
> > Kernel load addr 0x02008800 size 3808 KiB
> > RAM disk load addr 0x1100 size 9000 KiB
> > *  fdt: cmdline image address = 0x02c8ac00
> >   Checking for 'FDT'/'FDT Image' at 02c8ac00
> > *  fdt: raw FDT blob
> >Flattened Device Tree blob at 02c8ac00
> >Booting using the fdt blob at 0x2c8ac00
> >of_flat_tree at 0x02c8ac00 size 0x9d6d
> >XIP Kernel Image ... OK
> > do_bootm_states reserve: 0x2008800 -- 0x3b7c30
> > lmb_reserve base:0x2008800 size:0x3b7c30
> > no initrd_high
> > env_get_bootm_size size:66748416(0x3fa8000) tmp:360448(0x58000)
> > start:360448(0x58000)
> >initrd_high = 0x03fa8000, copy_to_ram = 1
> >Loading Ramdisk to 02c0, end 034c9d09 ... OK
> > ERROR: image is not a fdt - must RESET the board to recover.
> > FDT creation failed! hanging...### ERROR ### Please RESET the board ###
> >
> > Signed-off-by: Andy Yan 
> > ---
> >
> >  common/image-fdt.c | 1 +
> >  1 file changed, 1 insertion(+)
>
> Reviewed-by: Simon Glass 
>

Please don't forget to take it, if it okay.

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Re: [U-Boot] [PATCH 2/4] rv1108: Enable eMMC support

[Andy Yan]

Hi Otavio:


It's better to spilt the dtsi and config header file as two patches. And 
when you send different versions , you should mark your series with v1, 
v2...


On 2018/11/19 上午4:56, Otavio Salvador wrote:

In order to be able to build the Rockchip eMMC driver
on rv1108, the CONFIG_BOUNCE_BUFFER option needs to be
selected.

Select it like it is done on the other Rockchip SoC common files.

This also adds the pinctrl handles to enable the use of eMMC on custom
boards (as minievk) and makes it easier for later addition.

Signed-off-by: Otavio Salvador 
---

  arch/arm/dts/rv1108.dtsi| 29 +
  include/configs/rv1108_common.h |  3 +++
  2 files changed, 32 insertions(+)

diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi
index acfd97e18d..23a44bfaca 100644
--- a/arch/arm/dts/rv1108.dtsi
+++ b/arch/arm/dts/rv1108.dtsi
@@ -427,6 +427,35 @@
};
};
  
+		emmc {

+   emmc_clk: emmc-clk {
+   rockchip,pins = <2 RK_PB6 RK_FUNC_1 
&pcfg_pull_none_drv_8ma>;
+   };
+
+   emmc_cmd: emmc-cmd {
+   rockchip,pins = <2 RK_PB4 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>;
+   };
+
+   emmc_pwren: emmc-pwren {
+   rockchip,pins = <2 RK_PC2 RK_FUNC_2 
&pcfg_pull_none>;
+   };
+
+   emmc_bus1: emmc-bus1 {
+   rockchip,pins = <2 RK_PA0 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>;
+   };
+
+   emmc_bus8: emmc-bus8 {
+   rockchip,pins = <2 RK_PA0 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>,
+   <2 RK_PA1 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>,
+   <2 RK_PA2 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>,
+   <2 RK_PA3 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>,
+   <2 RK_PA4 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>,
+   <2 RK_PA5 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>,
+   <2 RK_PA6 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>,
+   <2 RK_PA7 RK_FUNC_2 
&pcfg_pull_up_drv_8ma>;
+   };
+   };
+
sdmmc {
sdmmc_clk: sdmmc-clk {
rockchip,pins = <3 RK_PC4 RK_FUNC_1 
&pcfg_pull_none_drv_4ma>;
diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index 2ab3b85e0c..cc0384e2f4 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -17,6 +17,9 @@
  #define CONFIG_SYS_TIMER_BASE 0x10350020
  #define CONFIG_SYS_TIMER_COUNTER  (CONFIG_SYS_TIMER_BASE + 8)
  
+/* MMC/SD IP block */

+#define CONFIG_BOUNCE_BUFFER
+
  #define CONFIG_SYS_SDRAM_BASE 0x6000
  #define CONFIG_SYS_INIT_SP_ADDR   (CONFIG_SYS_TEXT_BASE + 
0x10)
  #define CONFIG_SYS_LOAD_ADDR  (CONFIG_SYS_SDRAM_BASE + 0x200)


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[U-Boot] [PATCH] ARM: make memset and memcpy prompt message more clearly

[Andy Yan]

The origin SPL_USE_ARCH_MEMSET/MEMCPY use same prompt message
as USE_ARCH_MEMSET/MEMCPY, which makes it's hard to distinguish
them in menuconfig interface. This patch gives them different
prompt messages for spl and none-spl config.

Signed-off-by: Andy Yan 
---

 arch/arm/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 46183ae..59206b8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -253,7 +253,7 @@ config USE_ARCH_MEMCPY
  but may increase the binary size.
 
 config SPL_USE_ARCH_MEMCPY
-   bool "Use an assembly optimized implementation of memcpy"
+   bool "Use an assembly optimized implementation of memcpy for spl"
default y if USE_ARCH_MEMCPY
depends on !ARM64
help
@@ -271,7 +271,7 @@ config USE_ARCH_MEMSET
  but may increase the binary size.
 
 config SPL_USE_ARCH_MEMSET
-   bool "Use an assembly optimized implementation of memset"
+   bool "Use an assembly optimized implementation of memset for spl"
default y if USE_ARCH_MEMSET
depends on !ARM64
help
-- 
2.7.4


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Re: [U-Boot] [PATCH 0/5] fix the boot issue of Rockchip RK3036

[Andy Yan]

Hi Philipp:


On 2017年06月30日 16:14, Dr. Philipp Tomsich wrote:

Andy,


On 30 Jun 2017, at 09:47, Andy Yan  wrote:


As Kever mentioned in [0], the RK3036 based boards could't
bootup for a long time.
After a git bisect, I found the RK3036 SPL code size has
increased from patch [1] [2]. Before Tom's patch [1], the
SPL size is 3160 bytes, but it becomes 4080 bytes after [1]
applied. After a look at this patch, I realised I should
disable SPL_USE_ARCH_MEMCPY/MEMSET, and the code size indeed
come down after I disabled them. But I got a LD error after
apply patch[2]: "undefined reference to memset", RK3036 SPL
didn't use lib/string because of the sram space imitation.
The compile succeed after CONFIG_SPL_LIBGENERIC_SUPPORT enabled,
but the spl code size become 3248 bytes.

Additionally, Simon post patch [3] call printf to print a
message before back to bootrom from spl, which make the spl
code size increased to nearly 3.7 kb.

RK3036 SPL only has 4kb sram to use, the spl code will use
3.4 ~ 3.5 kb, the last 0.5kb are used for SP and GD, so there
is no space for malloc.

gcc-6-arm-linux-gnueabi
What version of GCC are you using?
If your problem can also be solved by moving to GCC 6.3 (or newer) and
the code-size improvements there, I’d rather just require a more recent
GCC version.


I default use arm-linux-gnueabe-gcc v5.4.
The current upstream kylin-rk3036_defconfig compiled by gcc-5.4 is 
4384 bytes, the size comes down to 3936 bytes if I use 
arm-linux-gnueabihf-gcc v6.3 from linaro. But this is still too large 
for rk3036.
Disable SPL_USE_ARCH_MEMCPY/MEMSET will make the spl size comes 
down to 3042 bytes by gcc v6.3. But I still need some hack: enable 
CONFIG_SPL_LIBGENERIC to get support for memset, masks Simon's print in 
bootrom.c, or the code size will become very large. Event though this 
hack make things work, we still lost a few hundreds bytes by function 
board_init_f_alloc_reserve, because platforms with very limit sram like 
rk3036 will return to bootrom after the dram initialized, they never use 
the malloc space. This few hundreds bytes is a large space for 4kb 
sarm,  it's better to letf them for code or SP.

Another thing to check would be whether you are building SPL as a
THUMB2 binary, as this can also help with the SPL size.

Yes, THUMB2 is default enabled.



To fix this issue on RK3036, I disabled CONFIG_SPL_LIBGENERIC_SUPPORT,
also make board_init_f_alloc_reserve and  board_init_f_init_reserve
as weak function, then override them in rk3036-board-spl.c with a
no malloc resered function.

[0] https://lists.denx.de/pipermail/u-boot/2017-May/292744.html
[1] http://patchwork.ozlabs.org/patch/714593/
[2] http://patchwork.ozlabs.org/patch/714592/
[3] http://patchwork.ozlabs.org/patch/751080/


Andy Yan (5):
  board_init.c: make the reserve functions as weak
  rockchip: rk3036: only reserve space for GD and SP in SPL stage
  rockchip: configs: disable SPL_ARCH_MEMCPY/MEMSET for rk3036
  rockchip: configs: add DEBUG UART for kylin board
  rockchip: add u-boot specific dts for rk3036 sdk

arch/arm/dts/rk3036-sdk-u-boot.dtsi   | 11 +
arch/arm/mach-rockchip/rk3036-board-spl.c | 37 +++
common/init/board_init.c  |  4 ++--
configs/evb-rk3036_defconfig  |  2 ++
configs/kylin-rk3036_defconfig|  6 +
5 files changed, 58 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/rk3036-sdk-u-boot.dtsi

--
2.7.4









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Re: [U-Boot] [PATCH 0/5] fix the boot issue of Rockchip RK3036

[Andy Yan]

Hi Heiko:


On 2017年07月05日 03:54, Heiko Stübner wrote:

Hi Andy,

Am Montag, 3. Juli 2017, 16:02:59 CEST schrieb Andy Yan:

On 2017年06月30日 16:14, Dr. Philipp Tomsich wrote:

On 30 Jun 2017, at 09:47, Andy Yan  wrote:
As Kever mentioned in [0], the RK3036 based boards could't
bootup for a long time.
After a git bisect, I found the RK3036 SPL code size has
increased from patch [1] [2]. Before Tom's patch [1], the
SPL size is 3160 bytes, but it becomes 4080 bytes after [1]
applied. After a look at this patch, I realised I should
disable SPL_USE_ARCH_MEMCPY/MEMSET, and the code size indeed
come down after I disabled them. But I got a LD error after
apply patch[2]: "undefined reference to memset", RK3036 SPL
didn't use lib/string because of the sram space imitation.
The compile succeed after CONFIG_SPL_LIBGENERIC_SUPPORT enabled,
but the spl code size become 3248 bytes.

Additionally, Simon post patch [3] call printf to print a
message before back to bootrom from spl, which make the spl
code size increased to nearly 3.7 kb.

RK3036 SPL only has 4kb sram to use, the spl code will use
3.4 ~ 3.5 kb, the last 0.5kb are used for SP and GD, so there
is no space for malloc.

gcc-6-arm-linux-gnueabi
What version of GCC are you using?
If your problem can also be solved by moving to GCC 6.3 (or newer) and
the code-size improvements there, I’d rather just require a more recent
GCC version.

  I default use arm-linux-gnueabe-gcc v5.4.
  The current upstream kylin-rk3036_defconfig compiled by gcc-5.4 is
4384 bytes, the size comes down to 3936 bytes if I use
arm-linux-gnueabihf-gcc v6.3 from linaro. But this is still too large
for rk3036.
  Disable SPL_USE_ARCH_MEMCPY/MEMSET will make the spl size comes
down to 3042 bytes by gcc v6.3. But I still need some hack: enable
CONFIG_SPL_LIBGENERIC to get support for memset, masks Simon's print in
bootrom.c, or the code size will become very large. Event though this
hack make things work, we still lost a few hundreds bytes by function
board_init_f_alloc_reserve, because platforms with very limit sram like
rk3036 will return to bootrom after the dram initialized, they never use
the malloc space. This few hundreds bytes is a large space for 4kb
sarm,  it's better to letf them for code or SP.Heiko

For a start, maybe you could take a look at Simon's size reduction
series from april. The TPL-specific stuff may not be that interesting,
but the first patch adds a totally slimmed down memset, which
may be better for real hard size constraints

[PATCH v2 0/5] Patches to reduce TPL code size:
https://www.mail-archive.com/u-boot@lists.denx.de/msg243443.html


The SPL_TINY_MEMSET was included in my hack.



Heiko







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Re: [U-Boot] [PATCH 0/5] fix the boot issue of Rockchip RK3036

[Andy Yan]

Hi Tom:


On 2017年07月04日 21:32, Tom Rini wrote:

On Mon, Jul 03, 2017 at 04:02:59PM +0800, Andy Yan wrote:

Hi Philipp:


On 2017年06月30日 16:14, Dr. Philipp Tomsich wrote:

Andy,


On 30 Jun 2017, at 09:47, Andy Yan  wrote:


As Kever mentioned in [0], the RK3036 based boards could't
bootup for a long time.
After a git bisect, I found the RK3036 SPL code size has
increased from patch [1] [2]. Before Tom's patch [1], the
SPL size is 3160 bytes, but it becomes 4080 bytes after [1]
applied. After a look at this patch, I realised I should
disable SPL_USE_ARCH_MEMCPY/MEMSET, and the code size indeed
come down after I disabled them. But I got a LD error after
apply patch[2]: "undefined reference to memset", RK3036 SPL
didn't use lib/string because of the sram space imitation.
The compile succeed after CONFIG_SPL_LIBGENERIC_SUPPORT enabled,
but the spl code size become 3248 bytes.

Additionally, Simon post patch [3] call printf to print a
message before back to bootrom from spl, which make the spl
code size increased to nearly 3.7 kb.

RK3036 SPL only has 4kb sram to use, the spl code will use
3.4 ~ 3.5 kb, the last 0.5kb are used for SP and GD, so there
is no space for malloc.

gcc-6-arm-linux-gnueabi
What version of GCC are you using?
If your problem can also be solved by moving to GCC 6.3 (or newer) and
the code-size improvements there, I’d rather just require a more recent
GCC version.

 I default use arm-linux-gnueabe-gcc v5.4.
 The current upstream kylin-rk3036_defconfig compiled by gcc-5.4
is 4384 bytes, the size comes down to 3936 bytes if I use
arm-linux-gnueabihf-gcc v6.3 from linaro. But this is still too
large for rk3036.

Please note that (and U-Boot should be complaining at you) that with
v2018.01 we'll be moving to gcc-6.x or later for ARM.


 Disable SPL_USE_ARCH_MEMCPY/MEMSET will make the spl size comes
down to 3042 bytes by gcc v6.3. But I still need some hack: enable
CONFIG_SPL_LIBGENERIC to get support for memset, masks Simon's print
in bootrom.c, or the code size will become very large. Event though
this hack make things work, we still lost a few hundreds bytes by
function board_init_f_alloc_reserve, because platforms with very
limit sram like rk3036 will return to bootrom after the dram
initialized, they never use the malloc space. This few hundreds
bytes is a large space for 4kb sarm,  it's better to letf them for
code or SP.

Since we're really size constrained here maybe it makes sense to move
that print to a debug() ?

  Yes, move it to debug() will mask the printf in normal. But even so, 
we still lost a few hundreds bytes in function


board_init_f_alloc_reserve for malloc. RK3036 will returned to bootrom 
immediately after the sdram initialization, the few hundreds space for 
malloc pool is never used in SPL stage.


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Re: [U-Boot] [PATCH 0/5] fix the boot issue of Rockchip RK3036

[Andy Yan]

Hi Tom:


On 2017年07月05日 09:56, Tom Rini wrote:

On Wed, Jul 05, 2017 at 09:08:47AM +0800, Andy Yan wrote:

Hi Tom:


On 2017年07月04日 21:32, Tom Rini wrote:

On Mon, Jul 03, 2017 at 04:02:59PM +0800, Andy Yan wrote:

Hi Philipp:


On 2017年06月30日 16:14, Dr. Philipp Tomsich wrote:

Andy,


On 30 Jun 2017, at 09:47, Andy Yan  wrote:


As Kever mentioned in [0], the RK3036 based boards could't
bootup for a long time.
After a git bisect, I found the RK3036 SPL code size has
increased from patch [1] [2]. Before Tom's patch [1], the
SPL size is 3160 bytes, but it becomes 4080 bytes after [1]
applied. After a look at this patch, I realised I should
disable SPL_USE_ARCH_MEMCPY/MEMSET, and the code size indeed
come down after I disabled them. But I got a LD error after
apply patch[2]: "undefined reference to memset", RK3036 SPL
didn't use lib/string because of the sram space imitation.
The compile succeed after CONFIG_SPL_LIBGENERIC_SUPPORT enabled,
but the spl code size become 3248 bytes.

Additionally, Simon post patch [3] call printf to print a
message before back to bootrom from spl, which make the spl
code size increased to nearly 3.7 kb.

RK3036 SPL only has 4kb sram to use, the spl code will use
3.4 ~ 3.5 kb, the last 0.5kb are used for SP and GD, so there
is no space for malloc.

gcc-6-arm-linux-gnueabi
What version of GCC are you using?
If your problem can also be solved by moving to GCC 6.3 (or newer) and
the code-size improvements there, I’d rather just require a more recent
GCC version.

 I default use arm-linux-gnueabe-gcc v5.4.
 The current upstream kylin-rk3036_defconfig compiled by gcc-5.4
is 4384 bytes, the size comes down to 3936 bytes if I use
arm-linux-gnueabihf-gcc v6.3 from linaro. But this is still too
large for rk3036.

Please note that (and U-Boot should be complaining at you) that with
v2018.01 we'll be moving to gcc-6.x or later for ARM.


 Disable SPL_USE_ARCH_MEMCPY/MEMSET will make the spl size comes
down to 3042 bytes by gcc v6.3. But I still need some hack: enable
CONFIG_SPL_LIBGENERIC to get support for memset, masks Simon's print
in bootrom.c, or the code size will become very large. Event though
this hack make things work, we still lost a few hundreds bytes by
function board_init_f_alloc_reserve, because platforms with very
limit sram like rk3036 will return to bootrom after the dram
initialized, they never use the malloc space. This few hundreds
bytes is a large space for 4kb sarm,  it's better to letf them for
code or SP.

Since we're really size constrained here maybe it makes sense to move
that print to a debug() ?


   Yes, move it to debug() will mask the printf in normal. But even
so, we still lost a few hundreds bytes in function

board_init_f_alloc_reserve for malloc. RK3036 will returned to
bootrom immediately after the sdram initialization, the few hundreds
space for malloc pool is never used in SPL stage.

Can you work the code paths out such that board_init_f_alloc_reserve
would not be called then?


 board_init_f_alloc_reserve is called from crt0.S, in not so easy to work the 
code path out. And  board_init_f_alloc_reserve
 also reserve space for GD, this is we needed. So I want make this function as 
weak, then I can override it in my board spl state.




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Re: [U-Boot] [PATCH 1/5] board_init.c: make the reserve functions as weak

[Andy Yan]

Hi Simon:


On 2017年07月07日 11:58, Simon Glass wrote:

Hi Andy,

On 30 June 2017 at 01:47, Andy Yan  wrote:

Some platform like rk3036 has no enough sapce for
malloc and also has no necessary to use malloc function
in spl stage. But the malloc pool is need in u-boot stage
before relocation.Make the reserve functions as weak, so
we can override it with a no malloc reserve in spl stage
and use the weak function to reserve malloc pool in u-boot
stage.

Signed-off-by: Andy Yan 

---

  common/init/board_init.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

I am not keen on weak functions for this sort of thing.

Can we instead be explicit and introduce a new control CONFIG_SPL_SYS_MALLOC_F?


I also have this ideas, but with a grep I found the 
CONFIG_SYS_MALLOC_F_LEN is spread all over the project. So maybe it's a 
little hard to seperate it. Anyway, I will have a try.


Regards,
Simon






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[U-Boot] [PATCH v2 2/9] mips: spl and normal u-boot stage set SYS_MALLOC_F indepently

[Andy Yan]

Some platforms has very small sram to run spl code, so
it may have no enough sapce for so much malloc pool before
relocation in spl stage as the normal u-boot stage.

Signed-off-by: Andy Yan 
---

Changes in v2: None

 arch/mips/cpu/start.S | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index d01ee9f..0cc140b 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -60,8 +60,12 @@
sp, sp, GD_SIZE # reserve space for gd
and sp, sp, t0  # force 16 byte alignment
movek0, sp  # save gd pointer
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#ifdef CONFIG_SYS_MALLOC_F
+# ifdef CONFIG_SPL_BUILD
+   li  t2, CONFIG_SPL_SYS_MALLOC_F_LEN
+# else
li  t2, CONFIG_SYS_MALLOC_F_LEN
+# endif
PTR_SUBU \
sp, sp, t2  # reserve space for early malloc
and sp, sp, t0  # force 16 byte alignment
@@ -75,7 +79,7 @@
blt t0, t1, 1b
 PTR_ADDIU t0, PTRSIZE
 
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#ifdef CONFIG_SYS_MALLOC_F
PTR_S   sp, GD_MALLOC_BASE(k0)  # gd->malloc_base offset
 #endif
.endm
-- 
2.7.4


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[U-Boot] [PATCH v2 3/9] powerpc: spl and normal u-boot stage set SYS_MALLOC_F indepently

[Andy Yan]

Some platforms has very small sram to run spl code, so
it may have no enough sapce for so much malloc pool before
relocation in spl stage as the normal u-boot stage.

Signed-off-by: Andy Yan 
---

Changes in v2: None

 arch/powerpc/cpu/mpc83xx/start.S | 13 +
 arch/powerpc/cpu/mpc85xx/start.S | 16 ++--
 2 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index 2fed4a1..f067b9e 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -48,6 +48,11 @@
 #define CONFIG_SYS_FLASHBOOT
 #endif
 
+#if defined(CONFIG_SPL_BUILD)
+#define MALLOC_F_LEN   CONFIG_SPL_SYS_MALLOC_F_LEN
+#else
+#define MALLOC_F_LEN   CONFIG_SYS_MALLOC_F_LEN
+#endif
 /*
  * Set up GOT: Global Offset Table
  *
@@ -274,14 +279,14 @@ in_flash:
cmplw   r3, r4
bne 1b
 
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#ifdef CONFIG_SYS_MALLOC_F
 
-#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > 
CONFIG_SYS_INIT_RAM_SIZE
-#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#if MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#error "MALLOC_F_LEN too large to fit into initial RAM."
 #endif
 
/* r3 = new stack pointer / pre-reloc malloc area */
-   subir3, r3, CONFIG_SYS_MALLOC_F_LEN
+   subir3, r3, MALLOC_F_LEN
 
/* Set pointer to pre-reloc malloc area in GD */
stw r3, GD_MALLOC_BASE(r4)
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 63fdffd..6fa7592 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -38,6 +38,11 @@
 #define NOR_BOOT
 #endif
 
+#if defined(CONFIG_SPL_BUILD)
+#define MALLOC_F_LEN   CONFIG_SPL_SYS_MALLOC_F_LEN
+#else
+#define MALLOC_F_LEN   CONFIG_SYS_MALLOC_F_LEN
+#endif
 /*
  * Set up GOT: Global Offset Table
  *
@@ -1183,14 +1188,13 @@ _start_cont:
lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
 
-#ifdef CONFIG_SYS_MALLOC_F_LEN
-
-#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > 
CONFIG_SYS_INIT_RAM_SIZE
-#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#ifdef CONFIG_SYS_MALLOC_F
+#if MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#error "MALLOC_F_LEN too large to fit into initial RAM."
 #endif
 
/* Leave 16+ byte for back chain termination and NULL return address */
-   subir3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+   subir3,r3,((MALLOC_F_LEN+16+15)&~0xf)
 #endif
 
/* End of RAM */
@@ -1204,7 +1208,7 @@ _start_cont:
cmplw   r4,r3
bne 1b
 
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#ifdef CONFIG_SYS_MALLOC_F
lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
 
-- 
2.7.4


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[U-Boot] [PATCH v2 4/9] microblaze: spl and normal u-boot stage set SYS_MALLOC_F indepently

[Andy Yan]

Some platforms has very small sram to run spl code, so
it may have no enough sapce for so much malloc pool before
relocation in spl stage as the normal u-boot stage.

Signed-off-by: Andy Yan 
---

Changes in v2: None

 arch/microblaze/cpu/start.S | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 79dc0cf..bfc0f54 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -11,6 +11,11 @@
 #include 
 #include 
 
+#if defined(CONFIG_SPL_BUILD)
+#define MALLOC_F_LEN   CONFIG_SPL_SYS_MALLOC_F_LEN
+#else
+#define MALLOC_F_LEN   CONFIG_SYS_MALLOC_F_LEN
+#endif
.text
.global _start
 _start:
@@ -32,7 +37,7 @@ _start:
addir1, r1, -4  /* Decrement SP to top of memory */
 #else
 #if defined(CONFIG_SYS_MALLOC_F_LEN)
-   addir1, r0, CONFIG_SYS_INIT_SP_OFFSET - CONFIG_SYS_MALLOC_F_LEN
+   addir1, r0, CONFIG_SYS_INIT_SP_OFFSET - MALLOC_F_LEN
 #else
addir1, r0, CONFIG_SYS_INIT_SP_OFFSET
 #endif
@@ -162,14 +167,14 @@ clear_bss:
 #ifndef CONFIG_SPL_BUILD
or  r5, r0, r0  /* flags - empty */
addir31, r0, _gd
-#if defined(CONFIG_SYS_MALLOC_F_LEN)
+#if defined(CONFIG_SYS_MALLOC_F)
addir6, r0, CONFIG_SYS_INIT_SP_OFFSET
swi r6, r31, GD_MALLOC_BASE
 #endif
braiboard_init_f
 #else
addir31, r0, _gd
-#if defined(CONFIG_SYS_MALLOC_F_LEN)
+#if defined(CONFIG_SYS_MALLOC_F)
addir6, r0, CONFIG_SPL_STACK_ADDR
swi r6, r31, GD_MALLOC_BASE
 #endif
-- 
2.7.4


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[U-Boot] [PATCH v2 5/9] rockchip: set malloc pool size to 0 before relocation in spl state on rk3036 based board

[Andy Yan]

RK3036 only has 4kb sram, the spl code will use
3.4 ~ 3.5 kb, the last 0.5kb are used for SP and
GD, so there is no space for malloc. Also, the spl
will directly return to bootrom after dram initialized,
they never need the space for malloc.

Signed-off-by: Andy Yan 

---

Changes in v2:
- set spl pre relocation malloc pool by CONFIG_SPL_SYS_MALLOC_F_LEN

 configs/evb-rk3036_defconfig   | 1 +
 configs/kylin-rk3036_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 321ef71..78e2095 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -4,6 +4,7 @@ CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_EVB_RK3036=y
 CONFIG_SPL_STACK_R_ADDR=0x8
 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
 CONFIG_DEBUG_UART=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_STACK_R=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 715e4b2..fd20eff 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -4,6 +4,7 @@ CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_KYLIN_RK3036=y
 CONFIG_SPL_STACK_R_ADDR=0x8
 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_STACK_R=y
 # CONFIG_CMD_IMLS is not set
-- 
2.7.4


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[U-Boot] [PATCH v2 6/9] rockchip: disable SPL_ARCH_MEMCPY/MEMSET for rk3036

[Andy Yan]

RK3036 has no enough sapce use ARCH_MEMCPY/MEMSET in spl stage

Signed-off-by: Andy Yan 
Reviewed-by: Simon Glass 
---

Changes in v2: None

 configs/evb-rk3036_defconfig   | 2 ++
 configs/kylin-rk3036_defconfig | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 78e2095..8e7a65b 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -1,4 +1,6 @@
 CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_EVB_RK3036=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index fd20eff..266ac94 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -1,4 +1,6 @@
 CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_KYLIN_RK3036=y
-- 
2.7.4


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[U-Boot] [PATCH v2 7/9] rockchip: enable SPL_LIBGENERIC for rk3036 based boards

[Andy Yan]

function board_init_f_init_reserve will call memset, which
is implemented in lib, and enabled by CONFIG_SPL_LIBGENERIC_SUPPORT
in spl stage.
To reduce the code size, also enable SPL_TINY_MEMSET.

Signed-off-by: Andy Yan 
---

Changes in v2: None

 arch/arm/mach-rockchip/rk3036-board-spl.c | 6 --
 configs/evb-rk3036_defconfig  | 2 ++
 configs/kylin-rk3036_defconfig| 3 ++-
 3 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c 
b/arch/arm/mach-rockchip/rk3036-board-spl.c
index 7b8d0ee..9458201 100644
--- a/arch/arm/mach-rockchip/rk3036-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3036-board-spl.c
@@ -53,9 +53,3 @@ void board_init_r(gd_t *id, ulong dest_addr)
while (1)
;
 }
-
-void hang(void)
-{
-   while (1)
-   ;
-}
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 8e7a65b..c0eef27 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 # CONFIG_SPL_USE_ARCH_MEMSET is not set
 CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_EVB_RK3036=y
 CONFIG_SPL_STACK_R_ADDR=0x8
@@ -38,5 +39,6 @@ CONFIG_DEBUG_UART_BASE=0x20068000
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
+CONFIG_SPL_TINY_MEMSET=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 266ac94..bba01fd 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 # CONFIG_SPL_USE_ARCH_MEMSET is not set
 CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_KYLIN_RK3036=y
 CONFIG_SPL_STACK_R_ADDR=0x8
@@ -22,7 +23,6 @@ CONFIG_CMD_TIME=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_SPL_PARTITION_UUIDS=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CLK=y
@@ -38,5 +38,6 @@ CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_STORAGE=y
+CONFIG_SPL_TINY_MEMSET=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
-- 
2.7.4


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[U-Boot] [PATCH v2 8/9] rockchip: use debug() instead of printf when back to bootrom

[Andy Yan]

printf will increase the code size more than 1kb, but platform
like rk3036 has no enough space for it.

Signed-off-by: Andy Yan 
---

Changes in v2: None

 arch/arm/mach-rockchip/bootrom.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c
index da36f92..ba34c35 100644
--- a/arch/arm/mach-rockchip/bootrom.c
+++ b/arch/arm/mach-rockchip/bootrom.c
@@ -10,7 +10,7 @@
 void back_to_bootrom(void)
 {
 #if defined(CONFIG_SPL_LIBGENERIC_SUPPORT) && !defined(CONFIG_TPL_BUILD)
-   printf("Returning to boot ROM...");
+   debug("Returning to boot ROM...");
 #endif
_back_to_bootrom_s();
 }
-- 
2.7.4


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[U-Boot] [PATCH v2 9/9] rockchip: add u-boot specific dts for rk3036 sdk

[Andy Yan]

Add this dts to enable debug uart releated devices
before relocation.

Signed-off-by: Andy Yan 
Reviewed-by: Simon Glass 
---

Changes in v2: None

 arch/arm/dts/rk3036-sdk-u-boot.dtsi | 11 +++
 1 file changed, 11 insertions(+)
 create mode 100644 arch/arm/dts/rk3036-sdk-u-boot.dtsi

diff --git a/arch/arm/dts/rk3036-sdk-u-boot.dtsi 
b/arch/arm/dts/rk3036-sdk-u-boot.dtsi
new file mode 100644
index 000..6f15f4a
--- /dev/null
+++ b/arch/arm/dts/rk3036-sdk-u-boot.dtsi
@@ -0,0 +1,11 @@
+&uart2 {
+   u-boot,dm-pre-reloc;
+};
+
+&grf {
+   u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+   u-boot,dm-pre-reloc;
+};
-- 
2.7.4


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[U-Boot] [PATCH v2 0/9] make SPL and normal u-boot stage use independent SYS_MALLOC_F_LEN

[Andy Yan]

Some platforms like RK3036 has very small sram to run spl code, so
it has no enough sapce for so much malloc pool before relocation in
spl stage as the normal u-boot stake.
As the long discussion in [1] [2], I make this series out, try to
make spl and normal u-boot stage use independent SYS_MALLOC_F_LEN.

[1]https://lists.denx.de/pipermail/u-boot/2017-July/297370.html
[2]https://lists.denx.de/pipermail/u-boot/2017-July/297504.html


Changes in v2:
- introduce a new control CONFIG_SPL_SYS_MALLOC_F_LEN, adviced by Simon
- set spl pre relocation malloc pool by CONFIG_SPL_SYS_MALLOC_F_LEN

Andy Yan (9):
  make SPL and normal u-boot stage use independent SYS_MALLOC_F_LEN
  mips: spl and normal u-boot stage set SYS_MALLOC_F indepently
  powerpc: spl and normal u-boot stage set SYS_MALLOC_F indepently
  microblaze: spl and normal u-boot stage set SYS_MALLOC_F indepently
  rockchip: set malloc pool size to 0 before relocation in spl state on
rk3036 based board
  rockchip: disable SPL_ARCH_MEMCPY/MEMSET for rk3036
  rockchip: enable SPL_LIBGENERIC for rk3036 based boards
  rockchip: use debug() instead of printf when back to bootrom
  rockchip: add u-boot specific dts for rk3036 sdk

 Kconfig   | 10 ++
 arch/arm/dts/rk3036-sdk-u-boot.dtsi   | 11 +++
 arch/arm/mach-rockchip/bootrom.c  |  2 +-
 arch/arm/mach-rockchip/rk3036-board-spl.c |  6 --
 arch/microblaze/cpu/start.S   | 11 ---
 arch/mips/cpu/start.S |  8 ++--
 arch/powerpc/cpu/mpc83xx/start.S  | 13 +
 arch/powerpc/cpu/mpc85xx/start.S  | 16 ++--
 arch/sandbox/cpu/start.c  |  2 +-
 cmd/bdinfo.c  |  2 +-
 common/Makefile   |  2 +-
 common/board_f.c  |  4 ++--
 common/board_r.c  |  2 +-
 common/dlmalloc.c | 12 ++--
 common/init/board_init.c  |  4 ++--
 common/spl/spl.c  |  6 +++---
 configs/evb-rk3036_defconfig  |  5 +
 configs/kylin-rk3036_defconfig|  6 +-
 drivers/core/Kconfig  |  8 
 drivers/serial/serial-uclass.c|  4 ++--
 include/asm-generic/global_data.h |  2 +-
 include/common.h  | 11 +++
 lib/asm-offsets.c |  2 +-
 lib/efi/efi_app.c |  2 +-
 24 files changed, 102 insertions(+), 49 deletions(-)
 create mode 100644 arch/arm/dts/rk3036-sdk-u-boot.dtsi

-- 
2.7.4


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[U-Boot] [PATCH v2 1/9] make SPL and normal u-boot stage use independent SYS_MALLOC_F_LEN

[Andy Yan]

Some platforms has very small sram to run spl code, so it has no
enough sapce for so much malloc pool before relocation in
spl stage as the normal u-boot stake.
Make spl and normal u-boot stage use independent SYS_MALLOC_F_LEN,
Then people can sets the pre-relocation malloc pool according to
the memory space indepently.

Signed-off-by: Andy Yan 

---

Changes in v2:
- introduce a new control CONFIG_SPL_SYS_MALLOC_F_LEN, adviced by Simon

 Kconfig   | 10 ++
 arch/sandbox/cpu/start.c  |  2 +-
 cmd/bdinfo.c  |  2 +-
 common/Makefile   |  2 +-
 common/board_f.c  |  4 ++--
 common/board_r.c  |  2 +-
 common/dlmalloc.c | 12 ++--
 common/init/board_init.c  |  4 ++--
 common/spl/spl.c  |  6 +++---
 drivers/core/Kconfig  |  8 
 drivers/serial/serial-uclass.c|  4 ++--
 include/asm-generic/global_data.h |  2 +-
 include/common.h  | 11 +++
 lib/asm-offsets.c |  2 +-
 lib/efi/efi_app.c |  2 +-
 15 files changed, 47 insertions(+), 26 deletions(-)

diff --git a/Kconfig b/Kconfig
index bb80ada..c1451bc 100644
--- a/Kconfig
+++ b/Kconfig
@@ -95,6 +95,16 @@ config SYS_MALLOC_F_LEN
  particular needs this to operate, so that it can allocate the
  initial serial device and any others that are needed.
 
+config SPL_SYS_MALLOC_F_LEN
+hex "Size of malloc() pool in spl before relocation"
+depends on SYS_MALLOC_F
+default SYS_MALLOC_F_LEN
+help
+  Before relocation, memory is very limited on many platforms. Still,
+  we can provide a small malloc() pool if needed. Driver model in
+  particular needs this to operate, so that it can allocate the
+  initial serial device and any others that are needed.
+
 menuconfig EXPERT
bool "Configure standard U-Boot features (expert users)"
default y
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index f605d4d..17e531a 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -310,7 +310,7 @@ int main(int argc, char *argv[])
 
memset(&data, '\0', sizeof(data));
gd = &data;
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#ifdef CONFIG_SYS_MALLOC_F
gd->malloc_base = CONFIG_MALLOC_F_ADDR;
 #endif
setup_ram_buf(state);
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 8971697..64836e9 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -346,7 +346,7 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
 #endif
 #ifdef CONFIG_SYS_MALLOC_F
printf("Early malloc usage: %lx / %x\n", gd->malloc_ptr,
-  CONFIG_SYS_MALLOC_F_LEN);
+  get_sys_malloc_f_len());
 #endif
if (gd->fdt_blob)
printf("fdt_blob = %p\n", gd->fdt_blob);
diff --git a/common/Makefile b/common/Makefile
index 17a92ea..29c880d 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -139,7 +139,7 @@ obj-y += console.o
 endif
 obj-$(CONFIG_CROS_EC) += cros_ec.o
 obj-y += dlmalloc.o
-ifdef CONFIG_SYS_MALLOC_F_LEN
+ifdef CONFIG_SYS_MALLOC_F
 obj-y += malloc_simple.o
 endif
 obj-y += image.o
diff --git a/common/board_f.c b/common/board_f.c
index ffa84e3..82dae70 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -727,7 +727,7 @@ static int initf_bootstage(void)
 
 static int initf_console_record(void)
 {
-#if defined(CONFIG_CONSOLE_RECORD) && defined(CONFIG_SYS_MALLOC_F_LEN)
+#if defined(CONFIG_CONSOLE_RECORD) && defined(CONFIG_SYS_MALLOC_F)
return console_record_init();
 #else
return 0;
@@ -736,7 +736,7 @@ static int initf_console_record(void)
 
 static int initf_dm(void)
 {
-#if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN)
+#if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F)
int ret;
 
bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
diff --git a/common/board_r.c b/common/board_r.c
index ecca1ed..e7d4010 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -256,7 +256,7 @@ static int initr_malloc(void)
 {
ulong malloc_start;
 
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#ifdef CONFIG_SYS_MALLOC_F
debug("Pre-reloc malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
  gd->malloc_ptr / 1024);
 #endif
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index fc1e8b3..d19c3e1 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -1254,7 +1254,7 @@ Void_t* mALLOc(bytes) size_t bytes;
 
   INTERNAL_SIZE_T nb;
 
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#ifdef CONFIG_SYS_MALLOC_F
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT))
return malloc_simple(bytes);
 #endif
@@ -1522,7 +1522,7 @@ void fREe(mem) Void_t* mem;
   mchunkptr fwd;   /* misc temp for linking */
   int   islr;  /* track whether mer

Re: [U-Boot] [PATCH 2/2] [rfc] support booting arm64 android image

[Andy Yan]

Hi:

2017-07-13 15:33 GMT+08:00 Bin Chen :

> Hi Tom,
>
> Thanks for the review.
>
> On 13 July 2017 at 04:25, Tom Rini  wrote:
>
> > On Tue, Jul 11, 2017 at 03:56:04PM +1000, Bin Chen wrote:
> >
> > > It's my understanding that we are supposed to use booti, instead of
> > bootm,
> > > for arm64 image. But booti lacks of android image support. Bootm has
> > > the andriod image support but lack of the arm64 image handling.
> > >
> > > So, what is suppose the right way of booting an android arm64 image?
> > > or, should we create a separate command?
> > >
> > > This patch is an invitation for that discussion.
> > >
> > > It *hacked* the booti command and it aslo assume the dtb is in the
> > second area
> > > of android boot image. It also has other belives like u-boot should be
> > > in control of where to put the kernnel/ramdisk/dtb images so it ignores
> > > the value specified in the android images.
> > >
> > > Signed-off-by: Bin Chen 
> >
> > So, booti is very much for the "Image" format described in the Linux
> > kernel in Documentation/arm64/booting.txt.  One can (and people have)
> > used bootm on aarch64 for "uImage" style kernels and FIT kernels, and I
> > would see being able to boot an aarch64 Android image with bootm as the
> > way to go forward.
>
>
> Are you suggesting that we should use bootm path, instead of booti?
>
> I have two questions regarding this:
>
> 1. currently arm64 kernel don't have a uImage kernel target. And I'm not
> sure
>  if adding that will be something that is wanted and/or sensible.
>
>


> 2. bootm path doesn't have the logic that is currently in the booti, such
> as the
> kernel relocation.
>
> Also, one other question raised during internal discussion was why the
> booti
> was created in the first place, if we could have had that implemented in
> the
> bootm path.
>
>
>
> > The analogy would be that we use bootm for Android
> > on arm not bootz.  Thanks!
> >
> > --
> > Tom
> >
>
>
>
> --
> Regards,
> Bin
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Re: [U-Boot] [PATCH 2/2] [rfc] support booting arm64 android image

[Andy Yan]

Hi:

2017-07-13 15:33 GMT+08:00 Bin Chen :

> Hi Tom,
>
> Thanks for the review.
>
> On 13 July 2017 at 04:25, Tom Rini  wrote:
>
> > On Tue, Jul 11, 2017 at 03:56:04PM +1000, Bin Chen wrote:
> >
> > > It's my understanding that we are supposed to use booti, instead of
> > bootm,
> > > for arm64 image. But booti lacks of android image support. Bootm has
> > > the andriod image support but lack of the arm64 image handling.
> > >
> > > So, what is suppose the right way of booting an android arm64 image?
> > > or, should we create a separate command?
> > >
> > > This patch is an invitation for that discussion.
> > >
> > > It *hacked* the booti command and it aslo assume the dtb is in the
> > second area
> > > of android boot image. It also has other belives like u-boot should be
> > > in control of where to put the kernnel/ramdisk/dtb images so it ignores
> > > the value specified in the android images.
> > >
> > > Signed-off-by: Bin Chen 
> >
> > So, booti is very much for the "Image" format described in the Linux
> > kernel in Documentation/arm64/booting.txt.  One can (and people have)
> > used bootm on aarch64 for "uImage" style kernels and FIT kernels, and I
> > would see being able to boot an aarch64 Android image with bootm as the
> > way to go forward.
>
>
> Are you suggesting that we should use bootm path, instead of booti?
>
> I have two questions regarding this:
>
> 1. currently arm64 kernel don't have a uImage kernel target. And I'm not
> sure
>  if adding that will be something that is wanted and/or sensible.
>
>
  It seems that bootm doesn't always require a uImage kernel. Consider we
use bootm to boot a ARM32 based android boot.img.
we pack the zImage in boot.img directly, without make it to uImage .

> 2. bootm path doesn't have the logic that is currently in the booti, such
> as the
> kernel relocation.
>
> Also, one other question raised during internal discussion was why the
> booti
> was created in the first place, if we could have had that implemented in
> the
> bootm path.
>
>
>
> > The analogy would be that we use bootm for Android
> > on arm not bootz.  Thanks!
> >
> > --
> > Tom
> >
>
>
>
> --
> Regards,
> Bin
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Re: [U-Boot] [PATCH 00/52] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7

[Andy Yan]

Hi:


On 2017年07月19日 04:35, Philipp Tomsich wrote:

Here's a series that has a lot going on, but I didn't want to split it
to allow everyone to understand the motivation between some of the
changes to the SPL/TPL framework.  The short summary of this is
"enablement for DRAM init on the RK3368 with everything else that's
necessary to do it using OF_PLATDATA in TPL".

Enabling the RK3368 created a few more challenges that I'd expected:
  - I needed different stack locations, text addresses and sizes for
TPL and SPL
  - the TPL stage was to use OF_PLATDATA and SPL was to use full OF_CONTROL
  - with the RK3368 TPL stage, there was a need to extend the back-to-bootrom
support for Rockchip to AArch64
  - I wanted to start folding some of the Rockchip specific SPL support
(i.e. back-to-bootrom) back into the general SPL framework to allow
using it as a general boot method


I have a confusion here: according to the README.TPL,  TPL is Third 
Program Loader, which loaded by the SPL. So I think it should run after 
the SPL. But from RK3188 and RK3368 TPL implementation , they all run 
before SPL.Maybe it is my misunderstanding, hope to get some guidance.:-)

So I ended up separating quite a bit of features between SPL and TPL
while keeping things transparent to the few other boards using TPL (at
least I hope that things are transparent, as we didn't have any of
those in our lab to test on)...

Tested with: RK3368-uQ7, Debian 9, Linux 4.13-rc1.

Just one final remark: the DMC driver for the RK3368 currently covers
the configuration we use on the RK3368-uQ7 (i.e. 32bit wide, 2 ranks)
and is stress-tested (including 8-way SPEC runs) at all 3 supported
speeds.  I've built a bit of infrastructure (e.g. the way the
memory-schedule is determined) that I hope will be a useful
starting-point in unifying the drivers for the various closely related
DRAM controllers (e.g. for the RK3288) for Rockchip devices in the
future.



Klaus Goger (1):
   rockchip: board: puma_rk3399: rename ATF firmware

Philipp Tomsich (51):
   spl: add a 'return to bootrom' boot method
   spl: configure 'return to bootrom' separately for SPL and TPL
   rockchip: back-to-bootrom: add 'back-to-bootrom' support for AArch64
   rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL
   rockchip: back-to-bootrom: simplify the #ifdef-check for LIBGENERIC in
 TPL/SPL
   spl: dm: Kconfig: use more specific prereqs for SPL_REGMAP and
 SPL_SYSCON
   spl: dm: Kconfig: split REGMAP/SYSCON support for TPL from SPL
   spl: dm: Kconfig: SPL_RAM depends on SPL_DM
   spl: dm: Kconfig: introduce TPL_RAM (in analogy to SPL_RAM)
   spl: dm: Kconfig: SPL_CLK depens on SPL_DM
   spl: dm: Kconfig: split CLK support for SPL and TPL
   spl: dm: Kconfig: split OF_CONTROL and OF_PLATDATA between SPL and TPL
   spl: dm: use CONFIG_IS_ENABLED to test for the DM option
   armv8: remove unused low-level modules from TPL
   armv8: spl: Support separate stack for TPL
   spl: allow a separate TEXT_BASE, LDSCRIPT and MAX_SIZE for TPL
   spl: Kconfig: split SYS_MALLOC_SIMPLE for TPL and SPL
   lib: spl: differentiate between TPL and SPL for
 libfdt/of_control/of_platdata
   spl: consistently use $(SPL_TPL_) to select features for SPL and TPL
 builds
   spl: add TPL_DRIVER_MISC_SUPPORT option
   drivers: spl: consistently use the $(SPL_TPL_) macro
   rockchip: Makefile: allow selective inclusion of sdram_common.o from
 TPL/SPL/U-Boot
   rockchip: rk3368: improve Kconfig text for the RK3368
   rockchip: rk3368: mkimage: add support for the RK3368
   rockchip: rk3368: pmugrf: add definitions for os_reg[0..3]
   rockchip: rk3368: define CONFIG_SYS_SDRAM_BASE
   rockchip: rk3368: spl: define COUNTER_FREQUENCY to 24MHz
   rockchip: rk3368: spl: add memory layout for TPL and SPL
   rockchip: rk3368: syscon: MSCH/PMUGRF/GRF support for OF_PLATDATA
   rockchip: rk3368: grf: use shifted-constants and prefix with RK3368_
   rockchip: pinctrl: rk3368: add GMAC (RGMII only) support
   rockchip: pinctrl: rk3368: add support for configuring the MMC pins
   rockchip: clk: rk3368: implement bandwidth adjust for PLLs
   rockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driver
   rockchip: clk: rk3368: do not change CPLL/GPLL before returning to
 BROM
   rockchip: clk: rk3368: implement DPLL (DRAM PLL) support
   rockchip: clk: rk3368: define DMA1_SRST_REQ and DMA2_SRST_REQ
   rockchip: clk: rk3368: implement MMC/SD clock reparenting
   rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL)
   rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock
   rockchip: clk: rk3368: mark 'priv' __maybe_unused in
 rk3368_clk_set_rate()
   net: gmac_rockchip: Add support for the RK3368 GMAC
   rockchip: Makefile: streamline SPL/TPL configuration
   rockchip: rk3368: add DRAM controller driver with DRAM initialisation
   rockchip: dts: rk3368: add DMC node in rk3368.dtsi
   rockchip: rk3368: spl: enable SPL_FRAMEWORK in rk3368_common.h
  

Re: [U-Boot] [PATCH 29/52] rockchip: rk3368: syscon: MSCH/PMUGRF/GRF support for OF_PLATDATA

[Andy Yan]

Hi Philipp:


On 2017年07月19日 04:36, Philipp Tomsich wrote:

The RK3368 has both a limited SPL size (just 0x7000 bytes) and the
added challenge of booting in AArch64, which increases the code size
for SPL (particularily when using the LP64 programming model).  For
this reason we expect the RK3368 to always use OF_PLATDATA for its
SPL stage.


According to your previous patch, maybe you mean TPL here?

This change adds support for the MSCH, PMUGRF and GRF register regions
in syscon, which are necessary for initialising the RK3368's DRAM
controller.

Signed-off-by: Philipp Tomsich 
---

  arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 35 +++
  1 file changed, 35 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c 
b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
index 03e97eb..90a993e 100644
--- a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
+++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
@@ -1,6 +1,8 @@
  /*
   * (C) Copyright 2017 Rockchip Electronics Co., Ltd
   * Author: Andy Yan 
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
   * SPDX-License-Identifier:   GPL-2.0+
   */
  
@@ -14,6 +16,8 @@ static const struct udevice_id rk3368_syscon_ids[] = {

  .data = ROCKCHIP_SYSCON_GRF },
{ .compatible = "rockchip,rk3368-pmugrf",
  .data = ROCKCHIP_SYSCON_PMUGRF },
+   { .compatible = "rockchip,rk3368-msch",
+ .data = ROCKCHIP_SYSCON_MSCH },
{ }
  };
  
@@ -22,3 +26,34 @@ U_BOOT_DRIVER(syscon_rk3368) = {

.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids,
  };
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int rk3368_syscon_bind_of_platdata(struct udevice *dev)
+{
+   dev->driver_data = dev->driver->of_match->data;
+   debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+   return 0;
+}
+
+U_BOOT_DRIVER(rockchip_rk3368_grf) = {
+   .name = "rockchip_rk3368_grf",
+   .id = UCLASS_SYSCON,
+   .of_match = rk3368_syscon_ids,
+   .bind = rk3368_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = {
+   .name = "rockchip_rk3368_pmugrf",
+   .id = UCLASS_SYSCON,
+   .of_match = rk3368_syscon_ids + 1,
+   .bind = rk3368_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3368_msch) = {
+   .name = "rockchip_rk3368_msch",
+   .id = UCLASS_SYSCON,
+   .of_match = rk3368_syscon_ids + 2,
+   .bind = rk3368_syscon_bind_of_platdata,
+};
+#endif



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Re: [U-Boot] [PATCH 30/52] rockchip: rk3368: grf: use shifted-constants and prefix with RK3368_

[Andy Yan]

Hi Philipp:


On 2017年07月19日 04:36, Philipp Tomsich wrote:

The RK3368 GRF header was still defines with a shifted-mask but with
non-shifted function selectors for the IOMUX defines.  As the RK3368
support is still fresh enough to allow a quick rename, we do this now
before having more code use this.

As some of the downstream drivers (e.g. the Designware GMAC wrapper)
may need to include the grf-header of multiple devices, we rename the
various defines for the RK3368 by prefixing them with the device name.
This avoids future trouble during driver integration.


Is that really necessary to add such a prefix for all the register 
definition, just to fit  the GMAC dirver?
Maybe the gmac driver can define the platform specific macro in its own 
code like dwmac-rk in the kernel. Then we can keep the register header 
file a little tidy.



Signed-off-by: Philipp Tomsich 
---

  arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 617 +---
  drivers/pinctrl/rockchip/pinctrl_rk3368.c   |  17 +-
  2 files changed, 334 insertions(+), 300 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h 
b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
index a438f5d..a97dc1e 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -1,4 +1,6 @@
-/* (C) Copyright 2016 Rockchip Electronics Co., Ltd
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
   *
   * SPDX-License-Identifier: GPL-2.0+
   */
@@ -100,315 +102,318 @@ check_member(rk3368_pmu_grf, os_reg[0], 0x200);
  
  /*GRF_GPIO0C_IOMUX*/

  enum {
-   GPIO0C7_SHIFT   = 14,
-   GPIO0C7_MASK= 3 << GPIO0C7_SHIFT,
-   GPIO0C7_GPIO= 0,
-   GPIO0C7_LCDC_D19,
-   GPIO0C7_TRACE_D9,
-   GPIO0C7_UART1_RTSN,
-
-   GPIO0C6_SHIFT   = 12,
-   GPIO0C6_MASK= 3 << GPIO0C6_SHIFT,
-   GPIO0C6_GPIO= 0,
-   GPIO0C6_LCDC_D18,
-   GPIO0C6_TRACE_D8,
-   GPIO0C6_UART1_CTSN,
-
-   GPIO0C5_SHIFT   = 10,
-   GPIO0C5_MASK= 3 << GPIO0C5_SHIFT,
-   GPIO0C5_GPIO= 0,
-   GPIO0C5_LCDC_D17,
-   GPIO0C5_TRACE_D7,
-   GPIO0C5_UART1_SOUT,
-
-   GPIO0C4_SHIFT   = 8,
-   GPIO0C4_MASK= 3 << GPIO0C4_SHIFT,
-   GPIO0C4_GPIO= 0,
-   GPIO0C4_LCDC_D16,
-   GPIO0C4_TRACE_D6,
-   GPIO0C4_UART1_SIN,
-
-   GPIO0C3_SHIFT   = 6,
-   GPIO0C3_MASK= 3 << GPIO0C3_SHIFT,
-   GPIO0C3_GPIO= 0,
-   GPIO0C3_LCDC_D15,
-   GPIO0C3_TRACE_D5,
-   GPIO0C3_MCU_JTAG_TDO,
-
-   GPIO0C2_SHIFT   = 4,
-   GPIO0C2_MASK= 3 << GPIO0C2_SHIFT,
-   GPIO0C2_GPIO= 0,
-   GPIO0C2_LCDC_D14,
-   GPIO0C2_TRACE_D4,
-   GPIO0C2_MCU_JTAG_TDI,
-
-   GPIO0C1_SHIFT   = 2,
-   GPIO0C1_MASK= 3 << GPIO0C1_SHIFT,
-   GPIO0C1_GPIO= 0,
-   GPIO0C1_LCDC_D13,
-   GPIO0C1_TRACE_D3,
-   GPIO0C1_MCU_JTAG_TRTSN,
-
-   GPIO0C0_SHIFT   = 0,
-   GPIO0C0_MASK= 3 << GPIO0C0_SHIFT,
-   GPIO0C0_GPIO= 0,
-   GPIO0C0_LCDC_D12,
-   GPIO0C0_TRACE_D2,
-   GPIO0C0_MCU_JTAG_TDO,
+   RK3368_GPIO0C7_MASK= GENMASK(15, 14),
+   RK3368_GPIO0C7_GPIO= 0,
+   RK3368_GPIO0C7_LCDC_D19= (1 << 14),
+   RK3368_GPIO0C7_TRACE_D9= (2 << 14),
+   RK3368_GPIO0C7_UART1_RTSN  = (3 << 14),
+
+   RK3368_GPIO0C6_MASK= GENMASK(13, 12),
+   RK3368_GPIO0C6_GPIO= 0,
+   RK3368_GPIO0C6_LCDC_D18= (1 << 12),
+   RK3368_GPIO0C6_TRACE_D8= (2 << 12),
+   RK3368_GPIO0C6_UART1_CTSN  = (3 << 12),
+
+   RK3368_GPIO0C5_MASK= GENMASK(11, 10),
+   RK3368_GPIO0C5_GPIO= 0,
+   RK3368_GPIO0C5_LCDC_D17= (1 << 10),
+   RK3368_GPIO0C5_TRACE_D7= (2 << 10),
+   RK3368_GPIO0C5_UART1_SOUT  = (3 << 10),
+
+   RK3368_GPIO0C4_MASK= GENMASK(9, 8),
+   RK3368_GPIO0C4_GPIO= 0,
+   RK3368_GPIO0C4_LCDC_D16= (1 << 8),
+   RK3368_GPIO0C4_TRACE_D6= (2 << 8),
+   RK3368_GPIO0C4_UART1_SIN   = (3 << 8),
+
+   RK3368_GPIO0C3_MASK= GENMASK(7, 6),
+   RK3368_GPIO0C3_GPIO= 0,
+   RK3368_GPIO0C3_LCDC_D15= (1 << 6),
+   RK3368_GPIO0C3_TRACE_D5= (2 << 6),
+   RK3368_GPIO0C3_MCU_JTAG_TDO= (3 << 6),
+
+   RK3368_GPIO0C2_MASK= GENMASK(5, 4),
+   RK3368_GPIO0C2_GPIO= 0,
+   RK3368_GPIO0C2_LCDC_D14= (1 << 4),
+   RK3368_GPIO0C2_TRACE_D4= (2 << 4),
+   RK3368_GPIO0C2_MCU_JTAG_TDI= (3 << 4),
+
+   RK3368_GPIO0C1_MASK= GENMASK(3, 2),
+   RK3368_GP

Re: [U-Boot] [PATCH 34/52] rockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driver

[Andy Yan]

Hi Philipp:


On 2017年07月19日 04:36, Philipp Tomsich wrote:

With the RK3368's limited TPL size, we'll want to use OF_PLATFDATA for
the SPL stage.  This implements support for OF_PLATDATA in the clock


TPL or SPL?

driver for the RK3368.




Signed-off-by: Philipp Tomsich 
---

  drivers/clk/rockchip/clk_rk3368.c | 17 +
  1 file changed, 17 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3368.c 
b/drivers/clk/rockchip/clk_rk3368.c
index d8f06d5..809ad19 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -8,7 +8,9 @@
  #include 
  #include 
  #include 
+#include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -19,6 +21,12 @@
  
  DECLARE_GLOBAL_DATA_PTR;
  
+#if CONFIG_IS_ENABLED(OF_PLATDATA)

+struct rk3368_clk_plat {
+   struct dtd_rockchip_rk3368_cru dtd;
+};
+#endif
+
  struct pll_div {
u32 nr;
u32 nf;
@@ -254,7 +262,11 @@ static struct clk_ops rk3368_clk_ops = {
  static int rk3368_clk_probe(struct udevice *dev)
  {
struct rk3368_clk_priv *priv = dev_get_priv(dev);
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+   struct rk3368_clk_plat *plat = dev_get_platdata(dev);
  
+	priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);

+#endif
rkclk_init(priv->cru);
  
  	return 0;

@@ -262,9 +274,11 @@ static int rk3368_clk_probe(struct udevice *dev)
  
  static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)

  {
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3368_clk_priv *priv = dev_get_priv(dev);
  
  	priv->cru = (struct rk3368_cru *)devfdt_get_addr(dev);

+#endif
  
  	return 0;

  }
@@ -291,6 +305,9 @@ U_BOOT_DRIVER(rockchip_rk3368_cru) = {
.id = UCLASS_CLK,
.of_match   = rk3368_clk_ids,
.priv_auto_alloc_size = sizeof(struct rk3368_clk_priv),
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+   .platdata_auto_alloc_size = sizeof(struct rk3368_clk_plat),
+#endif
.ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
.ops= &rk3368_clk_ops,
.bind   = rk3368_clk_bind,



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Re: [U-Boot] [PATCH 45/52] rockchip: dts: rk3368: add DMC node in rk3368.dtsi

[Andy Yan]

Hi Philipp:


On 2017年07月19日 04:36, Philipp Tomsich wrote:

For full SPL support, including DRAM initialisation, we need a few
nodes from the DTS: this commit adds the DMC (DRAM controller) node,
the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU
as 'u-boot,dm-pre-reloc'.  In addition to this, we also include the
dt-binding for the DMC to allow DTS files including this DTSI to refer
to the symbolic constants for the DDR3 bin and for the
memory-schedule.

Note that the DMC contains both the memory regions for the
(Designware) protocol controller as well as the DDR PHY.

Signed-off-by: Philipp Tomsich 
---

  arch/arm/dts/rk3368.dtsi | 26 --
  1 file changed, 20 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
index 9daf765..8dd6549 100644
--- a/arch/arm/dts/rk3368.dtsi
+++ b/arch/arm/dts/rk3368.dtsi
@@ -46,6 +46,7 @@
  #include 
  #include 
  #include 
+#include 
  
  / {

compatible = "rockchip,rk3368";
@@ -227,6 +228,23 @@
#clock-cells = <0>;
};
  
+	dmc: dmc@ff61 {

+   u-boot,dm-pre-reloc;
+   compatible = "rockchip,rk3368-dmc", "syscon";
+   rockchip,cru = <&cru>;
+   rockchip,grf = <&grf>;
+   rockchip,msch = <&service_msch>;
+   reg = <0 0xff61 0 0x400
+  0 0xff62 0 0x400>;
+   };
+
+   service_msch: syscon@ffac {
+   u-boot,dm-pre-reloc;
+   compatible = "rockchip,rk3368-msch", "syscon";
+   reg = <0x0 0xffac 0x0 0x2000>;
+   status = "okay";
+   };
+
sdmmc: dwmmc@ff0c {
compatible = "rockchip,rk3368-dw-mshc", 
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0c 0x0 0x4000>;
@@ -546,12 +564,6 @@
status = "disabled";
};
  
-	dmc: dmc@ff61 {

-   u-boot,dm-pre-reloc;
-   compatible = "rockchip,rk3368-dmc", "syscon";
-   reg = <0x0 0xff61 0x0 0x1000>;
-   };
-
i2c0: i2c@ff65 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff65 0x0 0x1000>;
@@ -653,6 +665,7 @@
};
  
  	cru: clock-controller@ff76 {

+   u-boot,dm-pre-reloc;


As U-BOOT has introduced xxx-u-boot.dtsi for the U-BOOT-spceific  
dt information. I think it's better to put this u-boot needed things in 
rk3368-u-boot.dtsi. It will make things easier when we need to sync the 
dts with upstream kernel.

compatible = "rockchip,rk3368-cru";
reg = <0x0 0xff76 0x0 0x1000>;
rockchip,grf = <&grf>;
@@ -661,6 +674,7 @@
};
  
  	grf: syscon@ff77 {

+   u-boot,dm-pre-reloc;
compatible = "rockchip,rk3368-grf", "syscon";
reg = <0x0 0xff77 0x0 0x1000>;
};



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Re: [U-Boot] [PATCH 30/52] rockchip: rk3368: grf: use shifted-constants and prefix with RK3368_

[Andy Yan]

Hi Philipp:


On 2017年07月21日 16:34, Dr. Philipp Tomsich wrote:

On 21 Jul 2017, at 05:50, Andy Yan  wrote:

Hi Philipp:


On 2017年07月19日 04:36, Philipp Tomsich wrote:

The RK3368 GRF header was still defines with a shifted-mask but with
non-shifted function selectors for the IOMUX defines.  As the RK3368
support is still fresh enough to allow a quick rename, we do this now
before having more code use this.

As some of the downstream drivers (e.g. the Designware GMAC wrapper)
may need to include the grf-header of multiple devices, we rename the
various defines for the RK3368 by prefixing them with the device name.
This avoids future trouble during driver integration.

Is that really necessary to add such a prefix for all the register 
definition, just to fit  the GMAC dirver?
Maybe the gmac driver can define the platform specific macro in its own code 
like dwmac-rk in the kernel. Then we can keep the register header file a little 
tidy.

The problem is not the GMAC driver (although it was the motivation for doing
this change), but rather how easy it is to pick up the wrong grf-file and refer
to the wrong definitions/values… the conflicts are not through the GMAC-specifc
defines but rather through things like the IOMUX masks or (before I moved
this to the DDR-driver) things like the defines to enable DRAM in GRF.

Until we find a way to consistently structure things in such a way that
(a) common constructs can be shared (e.g. the masks in the IOMUX)
(b) specific definitions (e.g. the pin-out for a specific device) is 
not visible outside of its driver
I prefer the names to explicitly refer to each device.
   
That said, the longer-term plan (especially with a larger number of devices

being supported) needs to include a consistent rework of how (and where)
we manage all these definitions from the grf-header files.
It's true that many devices use GRF, we also face this condition in the 
kernel land.And all the drivers in kernel handle this device specific 
definition in the driver itself(by of_device_id->data or MACRO). And 
there is also no need to use the grf constructs, the common syscon api 
will provide  you the grf base address. I think this keeps things 
simple, we don't need to rely on too much of the grf or cru header, 
maybe some day we can remove the header file, just as clean as the kernel.
On the other hand, add such a prefix of rk3368 breaks the consistency 
with other rockchip devices.





Signed-off-by: Philipp Tomsich 
---

  arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 617 +---
  drivers/pinctrl/rockchip/pinctrl_rk3368.c   |  17 +-
  2 files changed, 334 insertions(+), 300 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h 
b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
index a438f5d..a97dc1e 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -1,4 +1,6 @@
-/* (C) Copyright 2016 Rockchip Electronics Co., Ltd
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
   *
   * SPDX-License-Identifier: GPL-2.0+
   */
@@ -100,315 +102,318 @@ check_member(rk3368_pmu_grf, os_reg[0], 0x200);
/*GRF_GPIO0C_IOMUX*/
  enum {
-   GPIO0C7_SHIFT   = 14,
-   GPIO0C7_MASK= 3 << GPIO0C7_SHIFT,
-   GPIO0C7_GPIO= 0,
-   GPIO0C7_LCDC_D19,
-   GPIO0C7_TRACE_D9,
-   GPIO0C7_UART1_RTSN,
-
-   GPIO0C6_SHIFT   = 12,
-   GPIO0C6_MASK= 3 << GPIO0C6_SHIFT,
-   GPIO0C6_GPIO= 0,
-   GPIO0C6_LCDC_D18,
-   GPIO0C6_TRACE_D8,
-   GPIO0C6_UART1_CTSN,
-
-   GPIO0C5_SHIFT   = 10,
-   GPIO0C5_MASK= 3 << GPIO0C5_SHIFT,
-   GPIO0C5_GPIO= 0,
-   GPIO0C5_LCDC_D17,
-   GPIO0C5_TRACE_D7,
-   GPIO0C5_UART1_SOUT,
-
-   GPIO0C4_SHIFT   = 8,
-   GPIO0C4_MASK= 3 << GPIO0C4_SHIFT,
-   GPIO0C4_GPIO= 0,
-   GPIO0C4_LCDC_D16,
-   GPIO0C4_TRACE_D6,
-   GPIO0C4_UART1_SIN,
-
-   GPIO0C3_SHIFT   = 6,
-   GPIO0C3_MASK= 3 << GPIO0C3_SHIFT,
-   GPIO0C3_GPIO= 0,
-   GPIO0C3_LCDC_D15,
-   GPIO0C3_TRACE_D5,
-   GPIO0C3_MCU_JTAG_TDO,
-
-   GPIO0C2_SHIFT   = 4,
-   GPIO0C2_MASK= 3 << GPIO0C2_SHIFT,
-   GPIO0C2_GPIO= 0,
-   GPIO0C2_LCDC_D14,
-   GPIO0C2_TRACE_D4,
-   GPIO0C2_MCU_JTAG_TDI,
-
-   GPIO0C1_SHIFT   = 2,
-   GPIO0C1_MASK= 3 << GPIO0C1_SHIFT,
-   GPIO0C1_GPIO= 0,
-   GPIO0C1_LCDC_D13,
-   GPIO0C1_TRACE_D3,
-   GPIO0C1_MCU_JTAG_TRTSN,
-
-   GPIO0C0_SHIFT   = 0,
-   GPIO0C0_MASK= 3 << GPIO0C0_SHIFT,
-   GPIO0C0_GPIO= 0,
-   GPIO0C0_LCD

[U-Boot] [PATCH v3 00/10] make SPL and normal u-boot stage use independent SYS_MALLOC_F_LEN

[Andy Yan]

Some platforms like RK3036 has very small sram to run spl code, so
it has no enough sapce for so much malloc pool before relocation in
spl stage as the normal u-boot stage.
As the long discussion in [1] [2], I make this series out, try to
make spl and normal u-boot stage use independent SYS_MALLOC_F_LEN.

[1]https://lists.denx.de/pipermail/u-boot/2017-July/297370.html
[2]https://lists.denx.de/pipermail/u-boot/2017-July/297504.html


Changes in v3:
- use CONFIG_VAL(), which suggested by Simon
- disable SPL_DM_SERIAL
- use puts instead of printf, which suggested by Simon

Changes in v2:
- introduce a new control CONFIG_SPL_SYS_MALLOC_F_LEN, adviced by Simon

Andy Yan (10):
  make SPL and normal u-boot stage use independent SYS_MALLOC_F_LEN
  mips: spl and normal u-boot stage set SYS_MALLOC_F_LEN indepently
  powerpc: spl and normal u-boot stage set SYS_MALLOC_F_LEN indepently
  microblaze: spl and normal u-boot stage set SYS_MALLOC_F_LEN
indepently
  sandbox: use CONFIG_VAL(SYS_MALLOC_F_LEN) to distinguish malloc pool
size before relocation
  rockchip: set malloc pool size to 0 before relocation in spl state on
rk3036 based board
  rockchip: disable SPL_ARCH_MEMCPY/MEMSET for rk3036
  rockchip: enable SPL_LIBGENERIC for rk3036 based boards
  rockchip: use puts instead of printf when back to bootrom
  rockchip: add u-boot specific dts for rk3036 sdk

 Kconfig   | 10 ++
 arch/arm/dts/rk3036-sdk-u-boot.dtsi   | 11 +++
 arch/arm/mach-rockchip/bootrom.c  |  4 ++--
 arch/arm/mach-rockchip/rk3036-board-spl.c |  6 --
 arch/microblaze/cpu/start.S   |  8 
 arch/mips/cpu/start.S |  6 +++---
 arch/powerpc/cpu/mpc83xx/start.S  |  8 
 arch/powerpc/cpu/mpc85xx/start.S  | 11 +--
 arch/sandbox/cpu/start.c  |  2 +-
 cmd/bdinfo.c  |  4 ++--
 common/Makefile   |  4 +++-
 common/board_f.c  |  4 ++--
 common/board_r.c  |  2 +-
 common/dlmalloc.c | 12 ++--
 common/init/board_init.c  |  8 
 common/spl/spl.c  |  8 
 configs/evb-rk3036_defconfig  |  7 ++-
 configs/kylin-rk3036_defconfig|  7 ++-
 drivers/core/Kconfig  |  8 
 drivers/serial/serial-uclass.c|  4 ++--
 include/asm-generic/global_data.h |  2 +-
 lib/asm-offsets.c |  2 +-
 lib/efi/efi_app.c |  2 +-
 23 files changed, 83 insertions(+), 57 deletions(-)
 create mode 100644 arch/arm/dts/rk3036-sdk-u-boot.dtsi

-- 
2.7.4


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[U-Boot] [PATCH v3 01/10] make SPL and normal u-boot stage use independent SYS_MALLOC_F_LEN

[Andy Yan]

Some platforms has very small sram to run spl code, so it has no
enough sapce for so much malloc pool before relocation in
spl stage as the normal u-boot stage.
Make spl and normal u-boot stage use independent SYS_MALLOC_F_LEN,
Then people can sets the pre-relocation malloc pool according to
the memory space indepently.

Signed-off-by: Andy Yan 
Reviewed-by: Tom Rini 

---

Changes in v3:
- use CONFIG_VAL(), which suggested by Simon

Changes in v2:
- introduce a new control CONFIG_SPL_SYS_MALLOC_F_LEN, adviced by Simon

 Kconfig   | 10 ++
 cmd/bdinfo.c  |  4 ++--
 common/Makefile   |  4 +++-
 common/board_f.c  |  4 ++--
 common/board_r.c  |  2 +-
 common/dlmalloc.c | 12 ++--
 common/init/board_init.c  |  8 
 common/spl/spl.c  |  8 
 drivers/core/Kconfig  |  8 
 drivers/serial/serial-uclass.c|  4 ++--
 include/asm-generic/global_data.h |  2 +-
 lib/asm-offsets.c |  2 +-
 lib/efi/efi_app.c |  2 +-
 13 files changed, 41 insertions(+), 29 deletions(-)

diff --git a/Kconfig b/Kconfig
index bb80ada..c1451bc 100644
--- a/Kconfig
+++ b/Kconfig
@@ -95,6 +95,16 @@ config SYS_MALLOC_F_LEN
  particular needs this to operate, so that it can allocate the
  initial serial device and any others that are needed.
 
+config SPL_SYS_MALLOC_F_LEN
+hex "Size of malloc() pool in spl before relocation"
+depends on SYS_MALLOC_F
+default SYS_MALLOC_F_LEN
+help
+  Before relocation, memory is very limited on many platforms. Still,
+  we can provide a small malloc() pool if needed. Driver model in
+  particular needs this to operate, so that it can allocate the
+  initial serial device and any others that are needed.
+
 menuconfig EXPERT
bool "Configure standard U-Boot features (expert users)"
default y
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 8971697..81ac78d 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -344,9 +344,9 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
 #ifdef CONFIG_BOARD_TYPES
printf("Board Type  = %ld\n", gd->board_type);
 #endif
-#ifdef CONFIG_SYS_MALLOC_F
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
printf("Early malloc usage: %lx / %x\n", gd->malloc_ptr,
-  CONFIG_SYS_MALLOC_F_LEN);
+  CONFIG_VAL(SYS_MALLOC_F_LEN));
 #endif
if (gd->fdt_blob)
printf("fdt_blob = %p\n", gd->fdt_blob);
diff --git a/common/Makefile b/common/Makefile
index 17a92ea..60681c8 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -139,9 +139,11 @@ obj-y += console.o
 endif
 obj-$(CONFIG_CROS_EC) += cros_ec.o
 obj-y += dlmalloc.o
-ifdef CONFIG_SYS_MALLOC_F_LEN
+ifdef CONFIG_SYS_MALLOC_F
+ifneq ($(CONFIG_$(SPL_)SYS_MALLOC_F_LEN),0)
 obj-y += malloc_simple.o
 endif
+endif
 obj-y += image.o
 obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
 obj-$(CONFIG_$(SPL_)OF_LIBFDT) += image-fdt.o
diff --git a/common/board_f.c b/common/board_f.c
index ffa84e3..a2af660 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -727,7 +727,7 @@ static int initf_bootstage(void)
 
 static int initf_console_record(void)
 {
-#if defined(CONFIG_CONSOLE_RECORD) && defined(CONFIG_SYS_MALLOC_F_LEN)
+#if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
return console_record_init();
 #else
return 0;
@@ -736,7 +736,7 @@ static int initf_console_record(void)
 
 static int initf_dm(void)
 {
-#if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN)
+#if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
int ret;
 
bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
diff --git a/common/board_r.c b/common/board_r.c
index ecca1ed..985aa95 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -256,7 +256,7 @@ static int initr_malloc(void)
 {
ulong malloc_start;
 
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
debug("Pre-reloc malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
  gd->malloc_ptr / 1024);
 #endif
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index fc1e8b3..c37979b 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -1254,7 +1254,7 @@ Void_t* mALLOc(bytes) size_t bytes;
 
   INTERNAL_SIZE_T nb;
 
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT))
return malloc_simple(bytes);
 #endif
@@ -1522,7 +1522,7 @@ void fREe(mem) Void_t* mem;
   mchunkptr fwd;   /* misc temp for linking */
   int   islr;  /* track whether merging with last_remainder */
 
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
/* free() is a no-op - all the memor

[U-Boot] [PATCH v3 02/10] mips: spl and normal u-boot stage set SYS_MALLOC_F_LEN indepently

[Andy Yan]

Some platforms has very small sram to run spl code, so
it may have no enough sapce for so much malloc pool before
relocation in spl stage as the normal u-boot stage.
Use CONFIG_VAL(SYS_MALLOC_F_LEN) to fit this condition.

Signed-off-by: Andy Yan 
Acked-by: Daniel Schwierzeck 

---

Changes in v3:
- use CONFIG_VAL(), which suggested by Simon

Changes in v2: None

 arch/mips/cpu/start.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index d01ee9f..aa07654 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -60,8 +60,8 @@
sp, sp, GD_SIZE # reserve space for gd
and sp, sp, t0  # force 16 byte alignment
movek0, sp  # save gd pointer
-#ifdef CONFIG_SYS_MALLOC_F_LEN
-   li  t2, CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+   li  t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
PTR_SUBU \
sp, sp, t2  # reserve space for early malloc
and sp, sp, t0  # force 16 byte alignment
@@ -75,7 +75,7 @@
blt t0, t1, 1b
 PTR_ADDIU t0, PTRSIZE
 
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
PTR_S   sp, GD_MALLOC_BASE(k0)  # gd->malloc_base offset
 #endif
.endm
-- 
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[U-Boot] [PATCH v3 03/10] powerpc: spl and normal u-boot stage set SYS_MALLOC_F_LEN indepently

[Andy Yan]

Some platforms has very small sram to run spl code, so
it may have no enough sapce for so much malloc pool before
relocation in spl stage as the normal u-boot stage.
Use CONFIG_VAL(SYS_MALLOC_F_LEN) to fit this condition.

Signed-off-by: Andy Yan 

---

Changes in v3:
- use CONFIG_VAL(), which suggested by Simon

Changes in v2: None

 arch/powerpc/cpu/mpc83xx/start.S |  8 
 arch/powerpc/cpu/mpc85xx/start.S | 11 +--
 2 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index 2fed4a1..1c3c737 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -274,14 +274,14 @@ in_flash:
cmplw   r3, r4
bne 1b
 
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
 
-#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > 
CONFIG_SYS_INIT_RAM_SIZE
-#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > 
CONFIG_SYS_INIT_RAM_SIZE
+#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
 #endif
 
/* r3 = new stack pointer / pre-reloc malloc area */
-   subir3, r3, CONFIG_SYS_MALLOC_F_LEN
+   subir3, r3, CONFIG_VAL(SYS_MALLOC_F_LEN)
 
/* Set pointer to pre-reloc malloc area in GD */
stw r3, GD_MALLOC_BASE(r4)
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 63fdffd..58cb9fc 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1183,14 +1183,13 @@ _start_cont:
lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
 
-#ifdef CONFIG_SYS_MALLOC_F_LEN
-
-#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > 
CONFIG_SYS_INIT_RAM_SIZE
-#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > 
CONFIG_SYS_INIT_RAM_SIZE
+#error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
 #endif
 
/* Leave 16+ byte for back chain termination and NULL return address */
-   subir3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+   subir3,r3,((CONFIG_VAL(SYS_MALLOC_F_LEN)+16+15)&~0xf)
 #endif
 
/* End of RAM */
@@ -1204,7 +1203,7 @@ _start_cont:
cmplw   r4,r3
bne 1b
 
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
 
-- 
2.7.4


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[U-Boot] [PATCH v3 05/10] sandbox: use CONFIG_VAL(SYS_MALLOC_F_LEN) to distinguish malloc pool size before relocation

[Andy Yan]

From: Andy Yan 

SPL and normal u-boot stage use different malloc pool size
configuration before relocation, so use CONFIG_VAL(SYS_MALLOC_F_LEN)
to fit different boot stage.

Signed-off-by: Andy Yan 

Changes in v3:
- use CONFIG_VAL(), which suggested by Simon

Changes in v2: None

 arch/sandbox/cpu/start.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index f605d4d..00742fd 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -310,7 +310,7 @@ int main(int argc, char *argv[])
 
memset(&data, '\0', sizeof(data));
gd = &data;
-#ifdef CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
gd->malloc_base = CONFIG_MALLOC_F_ADDR;
 #endif
setup_ram_buf(state);
-- 
2.7.4


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[U-Boot] [PATCH v3 04/10] microblaze: spl and normal u-boot stage set SYS_MALLOC_F_LEN indepently

[Andy Yan]

Some platforms has very small sram to run spl code, so
it may have no enough sapce for so much malloc pool before
relocation in spl stage as the normal u-boot stage.
Use CONFIG_VAL(SYS_MALLOC_F_LEN) to fit this condition.

Signed-off-by: Andy Yan 

---

Changes in v3:
- use CONFIG_VAL(), which suggested by Simon

Changes in v2: None

 arch/microblaze/cpu/start.S | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 79dc0cf..baf4f51 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -31,8 +31,8 @@ _start:
mts rshr, r1
addir1, r1, -4  /* Decrement SP to top of memory */
 #else
-#if defined(CONFIG_SYS_MALLOC_F_LEN)
-   addir1, r0, CONFIG_SYS_INIT_SP_OFFSET - CONFIG_SYS_MALLOC_F_LEN
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+   addir1, r0, CONFIG_SYS_INIT_SP_OFFSET - CONFIG_VAL(SYS_MALLOC_F_LEN)
 #else
addir1, r0, CONFIG_SYS_INIT_SP_OFFSET
 #endif
@@ -162,14 +162,14 @@ clear_bss:
 #ifndef CONFIG_SPL_BUILD
or  r5, r0, r0  /* flags - empty */
addir31, r0, _gd
-#if defined(CONFIG_SYS_MALLOC_F_LEN)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
addir6, r0, CONFIG_SYS_INIT_SP_OFFSET
swi r6, r31, GD_MALLOC_BASE
 #endif
braiboard_init_f
 #else
addir31, r0, _gd
-#if defined(CONFIG_SYS_MALLOC_F_LEN)
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
addir6, r0, CONFIG_SPL_STACK_ADDR
swi r6, r31, GD_MALLOC_BASE
 #endif
-- 
2.7.4


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[U-Boot] [PATCH v3 06/10] rockchip: set malloc pool size to 0 before relocation in spl state on rk3036 based board

[Andy Yan]

RK3036 only has 4kb sram, the spl code will use
3.4 ~ 3.5 kb, the last 0.5kb are used for SP and
GD, so there is no space for malloc. Also, the spl
will directly return to bootrom after dram initialized,
they never need the space for malloc.

Signed-off-by: Andy Yan 
Reviewed-by: Simon Glass 
---

Changes in v3: None
Changes in v2: None

 configs/evb-rk3036_defconfig   | 1 +
 configs/kylin-rk3036_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 321ef71..78e2095 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -4,6 +4,7 @@ CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_EVB_RK3036=y
 CONFIG_SPL_STACK_R_ADDR=0x8
 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
 CONFIG_DEBUG_UART=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_STACK_R=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 715e4b2..fd20eff 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -4,6 +4,7 @@ CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_KYLIN_RK3036=y
 CONFIG_SPL_STACK_R_ADDR=0x8
 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_STACK_R=y
 # CONFIG_CMD_IMLS is not set
-- 
2.7.4


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[U-Boot] [PATCH v3 07/10] rockchip: disable SPL_ARCH_MEMCPY/MEMSET for rk3036

[Andy Yan]

RK3036 has no enough sapce use ARCH_MEMCPY/MEMSET in spl stage

Signed-off-by: Andy Yan 
Reviewed-by: Simon Glass 
---

Changes in v3: None
Changes in v2: None

 configs/evb-rk3036_defconfig   | 2 ++
 configs/kylin-rk3036_defconfig | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 78e2095..8e7a65b 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -1,4 +1,6 @@
 CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_EVB_RK3036=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index fd20eff..266ac94 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -1,4 +1,6 @@
 CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_KYLIN_RK3036=y
-- 
2.7.4


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[U-Boot] [PATCH v3 10/10] rockchip: add u-boot specific dts for rk3036 sdk

[Andy Yan]

Add this dts to enable debug uart releated devices
before relocation.

Signed-off-by: Andy Yan 
Reviewed-by: Simon Glass 
---

Changes in v3: None
Changes in v2: None

 arch/arm/dts/rk3036-sdk-u-boot.dtsi | 11 +++
 1 file changed, 11 insertions(+)
 create mode 100644 arch/arm/dts/rk3036-sdk-u-boot.dtsi

diff --git a/arch/arm/dts/rk3036-sdk-u-boot.dtsi 
b/arch/arm/dts/rk3036-sdk-u-boot.dtsi
new file mode 100644
index 000..6f15f4a
--- /dev/null
+++ b/arch/arm/dts/rk3036-sdk-u-boot.dtsi
@@ -0,0 +1,11 @@
+&uart2 {
+   u-boot,dm-pre-reloc;
+};
+
+&grf {
+   u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+   u-boot,dm-pre-reloc;
+};
-- 
2.7.4


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[U-Boot] [PATCH v3 09/10] rockchip: use puts instead of printf when back to bootrom

[Andy Yan]

printf will increase the code size more than 1kb, but platform
like rk3036 has no enough space for it.

Signed-off-by: Andy Yan 

---

Changes in v3:
- use puts instead of printf, which suggested by Simon

Changes in v2: None

 arch/arm/mach-rockchip/bootrom.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c
index da36f92..4ca9962 100644
--- a/arch/arm/mach-rockchip/bootrom.c
+++ b/arch/arm/mach-rockchip/bootrom.c
@@ -9,8 +9,8 @@
 
 void back_to_bootrom(void)
 {
-#if defined(CONFIG_SPL_LIBGENERIC_SUPPORT) && !defined(CONFIG_TPL_BUILD)
-   printf("Returning to boot ROM...");
+#if defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && !defined(CONFIG_TPL_BUILD)
+   puts("Returning to boot ROM...");
 #endif
_back_to_bootrom_s();
 }
-- 
2.7.4


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[U-Boot] [PATCH v3 08/10] rockchip: enable SPL_LIBGENERIC for rk3036 based boards

[Andy Yan]

function board_init_f_init_reserve will call memset, which
is implemented in lib, and enabled by CONFIG_SPL_LIBGENERIC_SUPPORT
in spl stage.
To reduce the code size, also enable SPL_TINY_MEMSET.
As rk3036 will return to bootrom immediately after dram
initialization, there is no need to run DM, so disable
SPL_DM_SERIAL.

Signed-off-by: Andy Yan 
Reviewed-by: Simon Glass 

---

Changes in v3:
- disable SPL_DM_SERIAL

Changes in v2: None

 arch/arm/mach-rockchip/rk3036-board-spl.c | 6 --
 configs/evb-rk3036_defconfig  | 4 +++-
 configs/kylin-rk3036_defconfig| 4 +++-
 3 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c 
b/arch/arm/mach-rockchip/rk3036-board-spl.c
index 7b8d0ee..9458201 100644
--- a/arch/arm/mach-rockchip/rk3036-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3036-board-spl.c
@@ -53,9 +53,3 @@ void board_init_r(gd_t *id, ulong dest_addr)
while (1)
;
 }
-
-void hang(void)
-{
-   while (1)
-   ;
-}
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 8e7a65b..dd03816 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 # CONFIG_SPL_USE_ARCH_MEMSET is not set
 CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_EVB_RK3036=y
 CONFIG_SPL_STACK_R_ADDR=0x8
@@ -33,10 +34,11 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_ROCKCHIP_RK3036=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
+# CONFIG_SPL_DM_SERIAL is not set
 CONFIG_DEBUG_UART_BASE=0x20068000
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
+CONFIG_SPL_TINY_MEMSET=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 266ac94..cd3074a 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 # CONFIG_SPL_USE_ARCH_MEMSET is not set
 CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ROCKCHIP_RK3036=y
 CONFIG_TARGET_KYLIN_RK3036=y
 CONFIG_SPL_STACK_R_ADDR=0x8
@@ -22,7 +23,6 @@ CONFIG_CMD_TIME=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_SPL_PARTITION_UUIDS=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CLK=y
@@ -34,9 +34,11 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_ROCKCHIP_RK3036=y
 CONFIG_DM_REGULATOR_FIXED=y
+# CONFIG_SPL_DM_SERIAL is not set
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_STORAGE=y
+CONFIG_SPL_TINY_MEMSET=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
-- 
2.7.4


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Re: [U-Boot] [PATCH 00/52] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7

[Andy Yan]

Hi Philipp:


On 2017年07月21日 18:55, Dr. Philipp Tomsich wrote:

On 21 Jul 2017, at 04:33, Andy Yan  wrote:

Hi:


On 2017年07月19日 04:35, Philipp Tomsich wrote:

Here's a series that has a lot going on, but I didn't want to split it
to allow everyone to understand the motivation between some of the
changes to the SPL/TPL framework.  The short summary of this is
"enablement for DRAM init on the RK3368 with everything else that's
necessary to do it using OF_PLATDATA in TPL".

Enabling the RK3368 created a few more challenges that I'd expected:
  - I needed different stack locations, text addresses and sizes for
TPL and SPL
  - the TPL stage was to use OF_PLATDATA and SPL was to use full OF_CONTROL
  - with the RK3368 TPL stage, there was a need to extend the back-to-bootrom
support for Rockchip to AArch64
  - I wanted to start folding some of the Rockchip specific SPL support
(i.e. back-to-bootrom) back into the general SPL framework to allow
using it as a general boot method

I have a confusion here: according to the README.TPL,  TPL is Third Program 
Loader, which loaded by the SPL. So I think it should run after the SPL. But 
from RK3188 and RK3368 TPL implementation , they all run before SPL.Maybe it is 
my misunderstanding, hope to get some guidance.:-)

I think you are right and most Rockchip boards have been using this the wrong 
way around.


Only RK3188 uses TPL now.


With the fine-grained configurability that I created for the RK3368, it will be 
easy enough to switch this around on the RK3368.
However, this will then also be done for the other RK3xxx devices to restore 
consistency.

I would prefer to first add the RK3368 support with the “backwards TPL/SPL” 
(i.e. TPL before SPL) to remain consistent with current mach-rockchip usage of 
the TPL/SPL terminology.
Once this is merged, we can then switch this around for each board individually.


So I ended up separating quite a bit of features between SPL and TPL
while keeping things transparent to the few other boards using TPL (at
least I hope that things are transparent, as we didn't have any of
those in our lab to test on)...

Tested with: RK3368-uQ7, Debian 9, Linux 4.13-rc1.

Just one final remark: the DMC driver for the RK3368 currently covers
the configuration we use on the RK3368-uQ7 (i.e. 32bit wide, 2 ranks)
and is stress-tested (including 8-way SPEC runs) at all 3 supported
speeds.  I've built a bit of infrastructure (e.g. the way the
memory-schedule is determined) that I hope will be a useful
starting-point in unifying the drivers for the various closely related
DRAM controllers (e.g. for the RK3288) for Rockchip devices in the
future.



Klaus Goger (1):
   rockchip: board: puma_rk3399: rename ATF firmware

Philipp Tomsich (51):
   spl: add a 'return to bootrom' boot method
   spl: configure 'return to bootrom' separately for SPL and TPL
   rockchip: back-to-bootrom: add 'back-to-bootrom' support for AArch64
   rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL
   rockchip: back-to-bootrom: simplify the #ifdef-check for LIBGENERIC in
 TPL/SPL
   spl: dm: Kconfig: use more specific prereqs for SPL_REGMAP and
 SPL_SYSCON
   spl: dm: Kconfig: split REGMAP/SYSCON support for TPL from SPL
   spl: dm: Kconfig: SPL_RAM depends on SPL_DM
   spl: dm: Kconfig: introduce TPL_RAM (in analogy to SPL_RAM)
   spl: dm: Kconfig: SPL_CLK depens on SPL_DM
   spl: dm: Kconfig: split CLK support for SPL and TPL
   spl: dm: Kconfig: split OF_CONTROL and OF_PLATDATA between SPL and TPL
   spl: dm: use CONFIG_IS_ENABLED to test for the DM option
   armv8: remove unused low-level modules from TPL
   armv8: spl: Support separate stack for TPL
   spl: allow a separate TEXT_BASE, LDSCRIPT and MAX_SIZE for TPL
   spl: Kconfig: split SYS_MALLOC_SIMPLE for TPL and SPL
   lib: spl: differentiate between TPL and SPL for
 libfdt/of_control/of_platdata
   spl: consistently use $(SPL_TPL_) to select features for SPL and TPL
 builds
   spl: add TPL_DRIVER_MISC_SUPPORT option
   drivers: spl: consistently use the $(SPL_TPL_) macro
   rockchip: Makefile: allow selective inclusion of sdram_common.o from
 TPL/SPL/U-Boot
   rockchip: rk3368: improve Kconfig text for the RK3368
   rockchip: rk3368: mkimage: add support for the RK3368
   rockchip: rk3368: pmugrf: add definitions for os_reg[0..3]
   rockchip: rk3368: define CONFIG_SYS_SDRAM_BASE
   rockchip: rk3368: spl: define COUNTER_FREQUENCY to 24MHz
   rockchip: rk3368: spl: add memory layout for TPL and SPL
   rockchip: rk3368: syscon: MSCH/PMUGRF/GRF support for OF_PLATDATA
   rockchip: rk3368: grf: use shifted-constants and prefix with RK3368_
   rockchip: pinctrl: rk3368: add GMAC (RGMII only) support
   rockchip: pinctrl: rk3368: add support for configuring the MMC pins
   rockchip: clk: rk3368: implement bandwidth adjust for PLLs
   rockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driver

[U-Boot] [PATCH 0/7] Add basic support for Rockchip RK3368 SOC

[Andy Yan]

The RK3368 is an octa-core Cortex-A53 SoC from Rockchip.
This adds basic support to chain-load U-Boot from Rockchip's
miniloader.


Andreas Färber (2):
  rockchip: rk3368: Add core start-up code for RK3368
  rockchip: rk3368: Add initial support for RK3368 based GeekBox

Andy Yan (5):
  rockchip: rk3368: Add clok drvier
  rockchip: rk3368: Add pinctrl driver
  rockchip: rk3368: Add sysreset driver
  rockchip: rk3368: Add PX5 Evaluation board
  rockchip: rk3368: add Sheep board

 arch/arm/dts/Makefile   |6 +-
 arch/arm/dts/rk3368-geekbox.dts |  319 +++
 arch/arm/dts/rk3368-px5-evb.dts |  319 +++
 arch/arm/dts/rk3368-sheep.dts   |  283 ++
 arch/arm/dts/rk3368.dtsi| 1090 +++
 arch/arm/include/asm/arch-rockchip/cru_rk3368.h |  110 +++
 arch/arm/include/asm/arch-rockchip/grf_rk3368.h |  443 +
 arch/arm/mach-rockchip/Kconfig  |   13 +
 arch/arm/mach-rockchip/Makefile |1 +
 arch/arm/mach-rockchip/rk3368/Kconfig   |   34 +
 arch/arm/mach-rockchip/rk3368/Makefile  |8 +
 arch/arm/mach-rockchip/rk3368/clk_rk3368.c  |   32 +
 arch/arm/mach-rockchip/rk3368/rk3368.c  |   84 ++
 arch/arm/mach-rockchip/rk3368/syscon_rk3368.c   |   25 +
 board/geekbuying/geekbox/Kconfig|   15 +
 board/geekbuying/geekbox/MAINTAINERS|6 +
 board/geekbuying/geekbox/Makefile   |7 +
 board/geekbuying/geekbox/geekbox.c  |   28 +
 board/rockchip/evb_px5/Kconfig  |   15 +
 board/rockchip/evb_px5/MAINTAINERS  |6 +
 board/rockchip/evb_px5/Makefile |7 +
 board/rockchip/evb_px5/evb-px5.c|   47 +
 board/rockchip/sheep_rk3368/Kconfig |   15 +
 board/rockchip/sheep_rk3368/MAINTAINERS |6 +
 board/rockchip/sheep_rk3368/Makefile|7 +
 board/rockchip/sheep_rk3368/sheep_rk3368.c  |   37 +
 configs/evb-px5_defconfig   |   30 +
 configs/geekbox_defconfig   |   21 +
 configs/sheep-rk3368_defconfig  |   28 +
 drivers/clk/rockchip/Makefile   |1 +
 drivers/clk/rockchip/clk_rk3368.c   |  296 ++
 drivers/pinctrl/Kconfig |9 +
 drivers/pinctrl/rockchip/Makefile   |1 +
 drivers/pinctrl/rockchip/pinctrl_rk3368.c   |  243 +
 drivers/sysreset/Makefile   |1 +
 drivers/sysreset/sysreset_rk3368.c  |   58 ++
 include/configs/evb_px5.h   |   18 +
 include/configs/geekbox.h   |   18 +
 include/configs/rk3368_common.h |   43 +
 include/configs/sheep_rk3368.h  |   22 +
 include/dt-bindings/clock/rk3368-cru.h  |  384 
 41 files changed, 4135 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/rk3368-geekbox.dts
 create mode 100644 arch/arm/dts/rk3368-px5-evb.dts
 create mode 100644 arch/arm/dts/rk3368-sheep.dts
 create mode 100644 arch/arm/dts/rk3368.dtsi
 create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3368.h
 create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3368.h
 create mode 100644 arch/arm/mach-rockchip/rk3368/Kconfig
 create mode 100644 arch/arm/mach-rockchip/rk3368/Makefile
 create mode 100644 arch/arm/mach-rockchip/rk3368/clk_rk3368.c
 create mode 100644 arch/arm/mach-rockchip/rk3368/rk3368.c
 create mode 100644 arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
 create mode 100644 board/geekbuying/geekbox/Kconfig
 create mode 100644 board/geekbuying/geekbox/MAINTAINERS
 create mode 100644 board/geekbuying/geekbox/Makefile
 create mode 100644 board/geekbuying/geekbox/geekbox.c
 create mode 100644 board/rockchip/evb_px5/Kconfig
 create mode 100644 board/rockchip/evb_px5/MAINTAINERS
 create mode 100644 board/rockchip/evb_px5/Makefile
 create mode 100644 board/rockchip/evb_px5/evb-px5.c
 create mode 100644 board/rockchip/sheep_rk3368/Kconfig
 create mode 100644 board/rockchip/sheep_rk3368/MAINTAINERS
 create mode 100644 board/rockchip/sheep_rk3368/Makefile
 create mode 100644 board/rockchip/sheep_rk3368/sheep_rk3368.c
 create mode 100644 configs/evb-px5_defconfig
 create mode 100644 configs/geekbox_defconfig
 create mode 100644 configs/sheep-rk3368_defconfig
 create mode 100644 drivers/clk/rockchip/clk_rk3368.c
 create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3368.c
 create mode 100644 drivers/sysreset/sysreset_rk3368.c
 create mode 100644 include/configs/evb_px5.h
 create mode 100644 include/configs/geekbox.h
 create mode 100644 include/configs/rk3368_common.h
 create mode 100644 include/configs/sheep_rk3368.h
 create mode 100644 include/dt-bindings/clock/rk3368-cru.h

-- 
2.7.4


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