Hi Quentin：
在 2024-02-15 20:42:56，"Quentin Schulz" <quentin.sch...@theobroma-systems.com> 写道： >Hi Andy, > >On 2/15/24 12:55, Andy Yan wrote: >> [You don't often get email from andys...@163.com. Learn why this is >> important at https://aka.ms/LearnAboutSenderIdentification ] >> >> Hi Quentin： >> At 2024-02-15 18:40:25, "Quentin Schulz" >> <quentin.sch...@theobroma-systems.com> wrote: >>> Hi Andy, >>> >>> On 2/15/24 11:35, Andy Yan wrote: >>> [...] >>>>>> diff --git a/configs/coolpi-4b-rk3588s_defconfig >>>>>> b/configs/coolpi-4b-rk3588s_defconfig >>>>>> new file mode 100644 >>>>>> index 0000000000..3e3e5abc86 >>>>>> --- /dev/null >>>>>> +++ b/configs/coolpi-4b-rk3588s_defconfig >>>>>> @@ -0,0 +1,105 @@ >>>>>> +CONFIG_ARM=y >>>>>> +CONFIG_SKIP_LOWLEVEL_INIT=y >>>>>> +CONFIG_COUNTER_FREQUENCY=24000000 >>>>>> +CONFIG_ARCH_ROCKCHIP=y >>>>>> +CONFIG_TEXT_BASE=0x00a00000 >>>>>> +CONFIG_SPL_LIBCOMMON_SUPPORT=y >>>>>> +CONFIG_SPL_LIBGENERIC_SUPPORT=y >>>>>> +CONFIG_NR_DRAM_BANKS=2 >>>>>> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y >>>>>> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 >>>>>> +CONFIG_SF_DEFAULT_SPEED=24000000 >>>>>> +CONFIG_SF_DEFAULT_MODE=0x2000 >>>>>> +CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b" >>>>>> +CONFIG_ROCKCHIP_RK3588=y >>>>>> +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y >>>>>> +CONFIG_ROCKCHIP_SPI_IMAGE=y >>>>>> +CONFIG_SPL_SERIAL=y >>>>>> +CONFIG_SPL_STACK_R_ADDR=0x600000 >>>>>> +CONFIG_TARGET_EVB_RK3588=y >>>>>> +CONFIG_SPL_STACK=0x400000 >>>>>> +CONFIG_DEBUG_UART_BASE=0xFEB50000 >>>>>> +CONFIG_DEBUG_UART_CLOCK=24000000 >>>>>> +CONFIG_SPL_SPI_FLASH_SUPPORT=y >>>>>> +CONFIG_SPL_SPI=y >>>>>> +CONFIG_SYS_LOAD_ADDR=0xc00800 >>>>>> +CONFIG_PCI=y >>>>>> +CONFIG_DEBUG_UART=y >>>>>> +CONFIG_AHCI=y >>>>>> +CONFIG_FIT=y >>>>>> +CONFIG_FIT_VERBOSE=y >>>>>> +CONFIG_SPL_FIT_SIGNATURE=y >>>>>> +CONFIG_SPL_LOAD_FIT=y >>>>>> +CONFIG_LEGACY_IMAGE_FORMAT=y >>>>>> +CONFIG_OF_BOARD_SETUP=y >>>>>> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb" >>>>>> +# CONFIG_DISPLAY_CPUINFO is not set >>>>>> +CONFIG_DISPLAY_BOARDINFO_LATE=y >>>>>> +CONFIG_SPL_MAX_SIZE=0x40000 >>>>>> +CONFIG_SPL_PAD_TO=0x7f8000 >>>>>> +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y >>>>>> +CONFIG_SPL_BSS_START_ADDR=0x4000000 >>>>>> +CONFIG_SPL_BSS_MAX_SIZE=0x4000 >>>>>> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set >>>>>> +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set >>>>>> +CONFIG_SPL_STACK_R=y >>>>>> +CONFIG_SPL_SPI_LOAD=y >>>>>> +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 >>>>>> +CONFIG_SPL_ATF=y >>>>>> +CONFIG_CMD_GPIO=y >>>>>> +CONFIG_CMD_GPT=y >>>>>> +CONFIG_CMD_I2C=y >>>>>> +CONFIG_CMD_MMC=y >>>>>> +CONFIG_CMD_PCI=y >>>>>> +CONFIG_CMD_USB=y >>>>>> +# CONFIG_CMD_SETEXPR is not set >>>>>> +CONFIG_CMD_REGULATOR=y >>>>>> +# CONFIG_SPL_DOS_PARTITION is not set >>>>>> +CONFIG_SPL_OF_CONTROL=y >>>>>> +CONFIG_OF_LIVE=y >>>>>> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent >>>>>> assigned-clocks assigned-clock-rates assigned-clock-parents" >>>>>> +CONFIG_SPL_DM_SEQ_ALIAS=y >>>>>> +CONFIG_SPL_REGMAP=y >>>>>> +CONFIG_SPL_SYSCON=y >>>>>> +CONFIG_AHCI_PCI=y >>>>>> +CONFIG_DWC_AHCI=y >>>>>> +CONFIG_SPL_CLK=y >>>>>> +CONFIG_ROCKCHIP_GPIO=y >>>>>> +CONFIG_SYS_I2C_ROCKCHIP=y >>>>>> +CONFIG_MISC=y >>>>>> +CONFIG_SUPPORT_EMMC_RPMB=y >>>>>> +CONFIG_MMC_DW=y >>>>>> +CONFIG_MMC_DW_ROCKCHIP=y >>>>>> +CONFIG_MMC_SDHCI=y >>>>>> +CONFIG_MMC_SDHCI_SDMA=y >>>>>> +CONFIG_MMC_SDHCI_ROCKCHIP=y >>>>>> +CONFIG_SF_DEFAULT_BUS=5 >>>>>> +CONFIG_SPI_FLASH_SFDP_SUPPORT=y >>>>>> +CONFIG_SPI_FLASH_XMC=y >>>>>> +CONFIG_SPI_FLASH_XTX=y >>>>>> +CONFIG_PHY_MOTORCOMM=y >>>>>> +CONFIG_DWC_ETH_QOS=y >>>>>> +CONFIG_DWC_ETH_QOS_ROCKCHIP=y >>>>>> +CONFIG_NVME_PCI=y >>>>>> +CONFIG_PCIE_DW_ROCKCHIP=y >>>>>> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y >>>>>> +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y >>>>>> +CONFIG_PHY_ROCKCHIP_USBDP=y >>>>>> +CONFIG_SPL_PINCTRL=y >>>>>> +CONFIG_PWM_ROCKCHIP=y >>>>>> +CONFIG_SPL_RAM=y >>>>>> +CONFIG_SCSI=y >>>>>> +CONFIG_BAUDRATE=1500000 >>>>>> +CONFIG_DEBUG_UART_SHIFT=2 >>>>>> +CONFIG_SYS_NS16550_MEM32=y >>>>>> +CONFIG_ROCKCHIP_SFC=y >>>>>> +CONFIG_SYSRESET=y >>>>>> +CONFIG_USB=y >>>>>> +CONFIG_USB_XHCI_HCD=y >>>>>> +CONFIG_USB_EHCI_HCD=y >>>>>> +CONFIG_USB_EHCI_GENERIC=y >>>>>> +CONFIG_USB_OHCI_HCD=y >>>>>> +CONFIG_USB_OHCI_GENERIC=y >>>>>> +CONFIG_USB_DWC3=y >>>>>> +CONFIG_USB_DWC3_GENERIC=y >>>>>> +CONFIG_ERRNO_STR=y >>>>> >>>>> Is there any reason for NOT enabling MMC_HS400_ES? >>>> >>>> No, I just follow the config of other rk3588/s based boards. >>> >>> Fortunately enough, a patch was recently merged to have at least HS200 >>> on RK3588, which is the first mode that actually works, anything below >>> that is broken right now. >>> >>>> It seems that there are no rk3588/s based boards enable MMC_HS400_ES in >>>> the current u-boot mainline ? >>>> >>> >>> Jaguar is hopefully coming soon-ish, maybe not in this release but the >>> next one (patches are sent already), and we make us of it in U-Boot >>> proper and the SPL. Up to you, can always be enabled later on. >> >> With a quick search， I fond jonas'S patch for enabling HS200 has been >> merged, but >> your patch will bring HS400_ES, does that mean all the rk3588/s based boars >> will switch to >> HS400 ES if they support it? >> > >No, it's on a per-board basis. Not all eMMC or boards support >HS400/HS400_ES, it depends on the signal quality/integrity and the eMMC >chip itself if I'm not mistaken. If I remember correctly, Jonas had some >RK3588 boards which didn't work with HS400/HS400_ES (probably one of >those boards with the eMMC that is plugged in?). With the following add to my defconfig： +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_SPL_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y I can see HS400 with mmc ifnfo， but no HS400ES？Maybe the emmc on the board does not support HS400ES，but I don't have datasheet about the emmc to check it. With some test , HS400 seems work fine on these two boards, I think I can enable it in the next version. => mmc info Device: mmc@fe2e0000 Manufacturer ID: ec OEM: 0 Name: AT2S9C Bus Speed: 200000000 Mode: HS400 (200MHz) Rd Block Len: 512 MMC version 5.1 High Capacity: Yes Capacity: 58.2 GiB Bus Width: 8-bit DDR Erase Group Size: 512 KiB HC WP Group Size: 8 MiB User Capacity: 58.2 GiB WRREL Boot Capacity: 4 MiB ENH RPMB Capacity: 4 MiB ENH Boot area 0 is not write protected Boot area 1 is not write protected > >Now to come to think of it... I don't know how/why HS400 isn't enabled >only when it's present in the DTB? > >Cheers, >Quentin
