Re: [PATCH 6/6] arm: mach-k3: Move DRAM address of ATF for AM62/AM62a
Hello Andrew, thanks for this series. On Wed, Feb 14, 2024 at 10:30:09AM -0600, Andrew Davis wrote: > The current address of TF-A in DRAM is just below the 512MB address line. > This means if the DRAM in a system is 512MB then TF-A is right at the > end of memory which is often reused, for instance U-Boot relocates itself > here. If a system has less than 512MB then that system wouldn't work at > all as TF-A would fail to load. Do you expect issue with system with exactly 512MB of RAM? We have such a board available and this is something that was not on our radar. The way we handle this is with `verdin-am62.c:board_get_usable_ram_top()` There is also some other reserved memory just before the 512MB limit, not just the TF-A. Francesco
Re: [PATCH v8 12/16] arm: dts: Introduce j784s4 u-boot dts files
Hi Nishanth
On 24-Jan-24 2:22 AM, Nishanth Menon wrote:
On 20:28-20240123, Apurva Nandan wrote:
[...]
in j784s4-binman.dtsi:
&binman {
j784s4_tiboot3_hs_fs_template: template-9 {
and then in sk.dtsi:
sk.dtsi means sk-uboot.dtsi or sk-binman.dtsi?
you wont need an sk-binman.dtsi with template. sk-u-boot.dtsi and
r5-sk.dts ofcourse will instantiate the required templates!
&binman {
ti-j784s4-hs-evm.bin {
insert-template =<&j784s4_tiboot3_hs_fs_template>;
};
};
This allows boards to readily include the template for the binaries of
choice and generate just relevant output. Wont it save much confusion?
[...]
It is still little unclear what is the full thing that you are recommending
to implement here.
From what I understood, is it as follows?
- Three binman files will be there: j784s4-binman.dtsi (soc binman),
j784s4-evm-binman.dtsi and am69-sk-binman.dtsi (board binman)
Nope. just j784s4-binman.dtsi with bin file templates for different kinds
of devices.
- j784s4-binman.dtsi will be a SoC binman, and will have only templates for
all tiboot3 gp, hs, hsfs, and tispl/uboot
tiboot3.bin is a an example, but you should do templates for other files
(tispl, u-boot.img... )as well on similar lines. So all a board file
ideally should instantiate is device types it wants and overrides of
dtbs it needs.
- The board binman files will include these templates and update the dtb
files in them.
Correct.
- Final board.dts will use the correct board-binman.dtsi files
if the templates are abstract enough, the additional code will be so
minimal that we wont need a board-binman.dtsi - just u-boot.dtsi and
r5.dtsi can include the relevant templates.
Hope this helps.
So I took a stab at working on this for couple of days, a fix was needed
within the tool to allow binman to handle multiple consecutive templates
which is needed here etc. which is why it did not work as is; but the
built binaries are still not stable for boot. I think this will need
some additional work and debugging. As of now, templating is not widely
used, so I'm guessing some more minor fixes would be needed to get it
building as we intend.
If you are okay, I think we can take this series as is for now, I will
take action to start off a series cleaning up and using templating for
all the devices.
--
Thanking You
Neha Malcom Francis
Re: [RFC PATCH v2 1/2] fastboot: introduce 'oem board' subcommand
Hi Alexey,
Thank you for the patch.
On jeu., févr. 01, 2024 at 12:20, Alexey Romanov
wrote:
> Currently, fastboot protocol in U-Boot has no opportunity
> to execute vendor custom code with verifed boot. This patch
> introduce new fastboot subcommand fastboot oem board:,
> which allow to run custom oem_board function.
>
> Default implementation is __weak. Vendor must redefine it in
> board/ folder with his own logic.
>
> For example, some vendors have their custom nand/emmc partition
> flashing or erasing. Here some typical command for such use cases:
>
> - flashing:
>
> $ fastboot stage bootloader.img
> $ fastboot oem board:write_bootloader
>
> - erasing:
>
> $ fastboot oem board:erase_env
>
> Signed-off-by: Alexey Romanov
Sorry for the delay. I needed time to give this some thoughts and I
waited for Sean to chime as well on this.
I've heard from Neil that this might be related to:
https://github.com/superna/pyamlboot/pull/20
I think this can be useful. Not necessarily for writing custom
partitions, but I see this could be used for other things:
1. Provision SoC-specific fuses (serialno/mac addr) at the factory line
(for production devices)
Examples:
$ fastboot oem board:write_serialno ABCDEF
$ fastboot oem board:write_macaddr AA:BB:CC:DD:EE
2. Access secure storage (via an Trusted Application)
But both examples could also be in a fastboot flash format:
$ fastboot flash serialno ABCDEF
One concern I have is that U-Boot forks might use this command as
an excuse to not makes things generic.
I hope that others will chime in on this as well.
I'd like to discuss this more because once this command is in we cannot
remove it later.
> ---
> drivers/fastboot/Kconfig | 7 +++
> drivers/fastboot/fb_command.c | 15 +++
> include/fastboot.h| 1 +
> 3 files changed, 23 insertions(+)
>
> diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
> index a4313d60a9..4d94391a76 100644
> --- a/drivers/fastboot/Kconfig
> +++ b/drivers/fastboot/Kconfig
> @@ -241,6 +241,13 @@ config FASTBOOT_OEM_RUN
> this feature if you are using verified boot, as it will allow an
> attacker to bypass any restrictions you have in place.
>
> +config FASTBOOT_OEM_BOARD
> + bool "Enable the 'oem board' command"
> + help
> + This extends the fastboot protocol with an "oem board" command. This
> + command allows running vendor custom code defined in board/ files.
> + Otherwise, it will do nothing and send fastboot fail.
If we move forward with this, please also document the new command in:
doc/android/fastboot.rst
> +
> endif # FASTBOOT
>
> endmenu
> diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c
> index 5fcadcdf50..2298815770 100644
> --- a/drivers/fastboot/fb_command.c
> +++ b/drivers/fastboot/fb_command.c
> @@ -40,6 +40,7 @@ static void reboot_recovery(char *, char *);
> static void oem_format(char *, char *);
> static void oem_partconf(char *, char *);
> static void oem_bootbus(char *, char *);
> +static void oem_board(char *, char *);
> static void run_ucmd(char *, char *);
> static void run_acmd(char *, char *);
>
> @@ -107,6 +108,10 @@ static const struct {
> .command = "oem run",
> .dispatch = CONFIG_IS_ENABLED(FASTBOOT_OEM_RUN, (run_ucmd),
> (NULL))
> },
> + [FASTBOOT_COMMAND_OEM_BOARD] = {
> + .command = "oem board",
> + .dispatch = CONFIG_IS_ENABLED(FASTBOOT_OEM_BOARD, (oem_board),
> (NULL))
> + },
> [FASTBOOT_COMMAND_UCMD] = {
> .command = "UCmd",
> .dispatch = CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT, (run_ucmd),
> (NULL))
> @@ -490,3 +495,13 @@ static void __maybe_unused oem_bootbus(char
> *cmd_parameter, char *response)
> else
> fastboot_okay(NULL, response);
> }
> +
> +void __weak fastboot_oem_board(char *cmd_parameter, void *data, u32 size,
> char *response)
> +{
> + fastboot_fail("oem board function not defined", response);
> +}
> +
> +static void __maybe_unused oem_board(char *cmd_parameter, char *response)
> +{
> + fastboot_oem_board(cmd_parameter, fastboot_buf_addr, image_size,
> response);
> +}
> diff --git a/include/fastboot.h b/include/fastboot.h
> index 296451f89d..06c1f26b6c 100644
> --- a/include/fastboot.h
> +++ b/include/fastboot.h
> @@ -37,6 +37,7 @@ enum {
> FASTBOOT_COMMAND_OEM_PARTCONF,
> FASTBOOT_COMMAND_OEM_BOOTBUS,
> FASTBOOT_COMMAND_OEM_RUN,
> + FASTBOOT_COMMAND_OEM_BOARD,
> FASTBOOT_COMMAND_ACMD,
> FASTBOOT_COMMAND_UCMD,
> FASTBOOT_COMMAND_COUNT
> --
> 2.30.1
Re: [RFC PATCH v2 2/2] board: ad401: example of fastboot oem board realization
On jeu., févr. 01, 2024 at 12:20, Alexey Romanov
wrote:
> An example of how we use fastboot oeam board subcommand
> for Sean Anderson.
>
> 1 - OEM_BOARD_WRITE_BOOTLOADER_CMD:
>
> We use it for custom Amlogic bootloader + tpl
> flashing protocol.
>
> 2 - OEM_BOARD_ERASE_CMD:
>
> Custom logic for erasing the env-emulated partition,
> which isn't in the mtd markup map.
>
> Example of the script which completely flashes the device:
>
> $ fastboot erase bootloader
> $ fastboot stage u-boot.bin
> $ fastboot oem board:write_bootloader
> $ fastboot reboot-bootloader
> $ fastboot oem board:erase_env
> $ fastboot erase misc
> $ fastboot erase super
> $ fastboot flash super rootfs
> $ fastboot reboot
>
> Signed-off-by: Alexey Romanov
> ---
> board/amlogic/ad401/fastboot.c | 222 +
> 1 file changed, 222 insertions(+)
> create mode 100644 board/amlogic/ad401/fastboot.c
>
> diff --git a/board/amlogic/ad401/fastboot.c b/board/amlogic/ad401/fastboot.c
> new file mode 100644
> index 00..01da8efa5b
> --- /dev/null
> +++ b/board/amlogic/ad401/fastboot.c
> @@ -0,0 +1,222 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2023 SaluteDevices, Inc.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +enum {
> + OEM_BOARD_ERASE_CMD,
> + OEM_BOARD_WRITE_BOOTLOADER_CMD,
> +};
> +
> +struct defenv {
> + char *name;
> + char value[256];
> +};
> +
> +static void save_defenv(struct defenv *e, size_t cnt)
> +{
> + int i;
> +
> + for (i = 0; i < cnt; i++) {
> + const char *env_val = env_get(e[i].name);
> +
> + if (env_val)
> + strlcpy(e[i].value, env_val, sizeof(e[i].value));
> + else
> + e[i].value[0] = '\0';
> + }
> +}
> +
> +static void set_defenv(struct defenv *e, size_t cnt)
> +{
> + int i;
> +
> + for (i = 0; i < cnt; i++)
> + env_set(e[i].name, e[i].value);
> +}
> +
> +static int fastboot_erase_env(void)
> +{
> + char *const defenv_names[] = { "lock", "mtdparts", "mtdids" };
> + struct defenv env[ARRAY_SIZE(defenv_names)];
> + int err, i;
> +
> + for (i = 0; i < ARRAY_SIZE(env); i++)
> + env[i].name = defenv_names[i];
> +
> + printf("ENV is being erased...\n");
> +
> + /*
> + * Reset environment to the default, excluding 'lock' variable,
> + * because it reflects the fastboot's state after execution of
> + * 'flashing unlock' command, hence it must survive the env-erasing.
> + * Otherwise, further erase commands will fail on check_lock().
> + *
> + * Also, we have to save 'mtdparts' and 'mtdids' variables
> + * because they are necessary to obtain partition map.
> + */
> +
> + save_defenv(env, ARRAY_SIZE(env));
> + env_set_default(NULL, 0);
> + set_defenv(env, ARRAY_SIZE(env));
> +
> + err = env_save();
> + if (err) {
> + pr_err("Can't overwrite ENV-partition\n");
> + return err;
> + }
Hmm so the fastboot locked state is saved in the U-Boot environment.
There is probably a good reason for this (no secure storage for
example). But this does not feel board specific.
Wouldn't it be better if we could just run "fastboot erase bootenv" and
that the generic fastboot code does the right thing?
(which is env default, and ignoring some magic/specific variables)
> +
> + return 0;
> +}
> +
> +static int fastboot_nand_write_tpl(struct mtd_info *mtd, void *buffer,
> +u32 offset, size_t size, int flags)
> +{
> + int boot_cpy_num = meson_bootloader_copy_num(BOOT_TPL);
> + u64 size_per_copy = meson_bootloader_copy_size(mtd, BOOT_TPL);
> + int i;
> +
> + for (i = 0; i < boot_cpy_num; i++) {
> + size_t retlen, len = size;
> + int ret;
> +
> + ret = nand_write_skip_bad(mtd, offset + (i * size_per_copy),
> + &len, &retlen, offset + size_per_copy,
> + buffer, flags);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int fastboot_nand_write_bl2(struct mtd_info *mtd, void *buffer,
> +u32 offset, size_t size, int flags)
> +{
> + int boot_cpy_num = meson_bootloader_copy_num(BOOT_BL2);
> + u64 size_per_copy = meson_bootloader_copy_size(mtd, BOOT_BL2);
> + int i;
> +
> + for (i = 0; i < boot_cpy_num; i++) {
> + int ret;
> +
> + ret = meson_bootloader_write_bl2(mtd, buffer,
> + offset + (i * size_per_copy),
> + size, flags);
> + if (ret)
> + return ret;
> + }
> +
> + return meson_bootloader_write_info_pages();
> +}
> +
> +static in
Re: [PATCH v1 3/5] cmd: optee_rpmb: build cmd for sandbox
Hi Igor, Thank you for the patch. On mer., févr. 14, 2024 at 19:34, Igor Opaniuk wrote: > Support CMD_OPTEE_RPMB for SANDBOX configurations. > Test: > > $ ./u-boot -d arch/sandbox/dts/test.dtb > ... > => optee_rpmb write_pvalue test_variable test_value > Wrote 11 bytes > => optee_rpmb read_pvalue test_variable 11 > Read 11 bytes, value = test_value > > Signed-off-by: Igor Opaniuk Reviewed-by: Mattijs Korpershoek Tested-by: Mattijs Korpershoek # on sandbox > --- > > cmd/Kconfig | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/cmd/Kconfig b/cmd/Kconfig > index a86b5705174..8ad8c0c542c 100644 > --- a/cmd/Kconfig > +++ b/cmd/Kconfig > @@ -1370,7 +1370,9 @@ config CMD_CLONE > > config CMD_OPTEE_RPMB > bool "Enable read/write support on RPMB via OPTEE" > - depends on SUPPORT_EMMC_RPMB && OPTEE > + depends on (SUPPORT_EMMC_RPMB && OPTEE) || SANDBOX_TEE > + default y if SANDBOX_TEE > + select OPTEE_TA_AVB if SANDBOX_TEE > help > Enable the commands for reading, writing persistent named values > in the Replay Protection Memory Block partition in eMMC by > -- > 2.34.1
Re:Re: [PATCH v2 1/2] board: rockchip: Add support for rk3588s based Cool Pi 4B
At 2024-02-14 22:13:08, "Quentin Schulz"
wrote:
>Hi Andy,
>
>On 2/14/24 10:31, Andy Yan wrote:
>> [You don't often get email from andys...@163.com. Learn why this is
>> important at https://aka.ms/LearnAboutSenderIdentification ]
>>
>> CoolPi 4B is a rk3588s based SBC.
>>
>> Specification:
>> - Rockchip RK3588S
>> - LPDDR4 2/4/8/16 GB
>> - TF scard slot
>> - eMMC 8/32/64/128 GB module
>> - SPI Nor 8MB
>> - Gigabit ethernet drived by PCIE with RTL8111HS
>> - HDMI Type D out
>> - Mini DP out
>> - USB 2.0 Host x 2
>> - USB 3.0 OTG x 1
>> - USB 3.0 Host x 1
>> - WIFI/BT module AIC8800
>> - 40 pin header
>>
>> The dts is from linux-6.8 rc1.
>>
>> Signed-off-by: Andy Yan
>> Reviewed-by: Kever Yang
>>
>> ---
>>
>> Changes in v2:
>> - sync dts from linux-rockchip which will be in linux-6.8 rc6[0]
>>
>> [0]https://patchwork.kernel.org/project/linux-rockchip/patch/2450634.jE0xQCEvom@phil/
>> arch/arm/dts/Makefile | 1 +
>> arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi | 30 +
>> arch/arm/dts/rk3588s-coolpi-4b.dts | 812 +
>> board/rockchip/evb_rk3588/MAINTAINERS | 7 +
>> configs/coolpi-4b-rk3588s_defconfig| 105 +++
>> 5 files changed, 955 insertions(+)
>> create mode 100644 arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
>> create mode 100644 arch/arm/dts/rk3588s-coolpi-4b.dts
>> create mode 100644 configs/coolpi-4b-rk3588s_defconfig
>>
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index ce10d3dbb0..ae7c088ceb 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -190,6 +190,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
>> rk3568-rock-3a.dtb
>>
>> dtb-$(CONFIG_ROCKCHIP_RK3588) += \
>> + rk3588s-coolpi-4b.dts \
>> rk3588-edgeble-neu6a-io.dtb \
>> rk3588-edgeble-neu6b-io.dtb \
>> rk3588-evb1-v10.dtb \
>> diff --git a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
>> b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
>> new file mode 100644
>> index 00..6b69ff424f
>> --- /dev/null
>> +++ b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
>> @@ -0,0 +1,30 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +
>> +#include "rk3588s-u-boot.dtsi"
>> +
>> +/ {
>> + chosen {
>> + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
>> + };
>
>This is already in rk3588s-u-boot.dtsi
Okay, will be dropped in the next version. Thanks for catching that.
>
>> +};
>> +
>> +&fspim2_pins {
>> + bootph-all;
>> +};
>> +
>> +&sfc {
>> + bootph-pre-ram;
>> + u-boot,spl-sfc-no-dma;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&fspim2_pins>;
>> + status = "okay";
>> +
>> + flash@0 {
>> + bootph-pre-ram;
>> + compatible = "jedec,spi-nor";
>> + reg = <0>;
>> + spi-max-frequency = <2400>;
>> + spi-rx-bus-width = <4>;
>> + spi-tx-bus-width = <1>;
>> + };
>> +};
>> diff --git a/arch/arm/dts/rk3588s-coolpi-4b.dts
>> b/arch/arm/dts/rk3588s-coolpi-4b.dts
>> new file mode 100644
>> index 00..e037bf9db7
>> --- /dev/null
>> +++ b/arch/arm/dts/rk3588s-coolpi-4b.dts
>> @@ -0,0 +1,812 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
>> + *
>> + * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction
>> + *
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include
>> +#include
>> +#include
>> +#include "rk3588s.dtsi"
>> +
>> +/ {
>> + model = "RK3588S CoolPi 4 Model B";
>> + compatible = "coolpi,pi-4b", "rockchip,rk3588s";
>> +
>> + aliases {
>> + mmc0 = &sdhci;
>> + mmc1 = &sdmmc;
>> + mmc2 = &sdio;
>> + };
>> +
>> + analog-sound {
>> + compatible = "audio-graph-card";
>> + dais = <&i2s0_8ch_p0>;
>> + label = "rk3588-es8316";
>> + routing = "MIC2", "Mic Jack",
>> + "Headphones", "HPOL",
>> + "Headphones", "HPOR";
>> + widgets = "Microphone", "Mic Jack",
>> + "Headphone", "Headphones";
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial2:150n8";
>> + };
>> +
>> + leds: leds {
>> + compatible = "gpio-leds";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&gpio_leds>;
>> +
>> + led0: led-green {
>> + color = ;
>> + function = LED_FUNCTION_STATUS;
>> + gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "heartbeat";
>> + };
>> +
>> + led1: led-red {
>> + color = ;
>> + default-state = "off";
>> + function = LED_FUNCTION_WLAN;
>> +
Re: [PATCH v2 1/2] board: rockchip: Add support for rk3588s based Cool Pi 4B
Hi Andy, On 2/15/24 11:35, Andy Yan wrote: [...] diff --git a/configs/coolpi-4b-rk3588s_defconfig b/configs/coolpi-4b-rk3588s_defconfig new file mode 100644 index 00..3e3e5abc86 --- /dev/null +++ b/configs/coolpi-4b-rk3588s_defconfig @@ -0,0 +1,105 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=2400 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a0 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0 +CONFIG_SF_DEFAULT_SPEED=2400 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x60 +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SPL_STACK=0x40 +CONFIG_DEBUG_UART_BASE=0xFEB5 +CONFIG_DEBUG_UART_CLOCK=2400 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x4 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x6 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=150 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y Is there any reason for NOT enabling MMC_HS400_ES? No, I just follow the config of other rk3588/s based boards. Fortunately enough, a patch was recently merged to have at least HS200 on RK3588, which is the first mode that actually works, anything below that is broken right now. It seems that there are no rk3588/s based boards enable MMC_HS400_ES in the current u-boot mainline ? Jaguar is hopefully coming soon-ish, maybe not in this release but the next one (patches are sent already), and we make us of it in U-Boot proper and the SPL. Up to you, can always be enabled later on. FWIW, both comments on this patch also apply to the second patch in this series :) Cheers, Quentin
TI LCD Driver and splash screen.
Hello. I am bringing up a new am335x platform and need splash screen support. I already wrote new backlight and LCD panel Linux drivers for the platform. The kernel side is solid. I brought the device tree and backlight driver from the kernel and put it into v2023.04 U-Boot. Currently getting a "cannot allocate frame buffer memory error" and have tried a bunch of different things. I have attached my current defconfig. The panel/graphics portion in the device tree I copied from arch/arm/dts/am335x-brxre1.dts to start. Was hoping people had some pointers or ideas. Cheers, Steve am335x_metrohm_dsplus_defconfig Description: Binary data
Double free error with ubi_volume_desc/ubi_close_volume
Hi all, I seem to be running into a double free error with ubi_volume_desc/ubi_close_volume during a ubifsmount/ubifsload/ubifsumount sequence. This is the sequence that I'm seeing: ubifsmount - do_ubifs_mount - cmd_ubifs_mount - uboot_ubifs_mount - ubifs_mount - open_ubi - ubi_open_volume -> returns ubi_volume_desc #1 - open_ubi returns ubi_volume_desc #1 - ubi_volume_desc #1 stored in local ubi variable - ubifs_fill_super - ubi_open_volume returns ubi_volume_desc #2 - ubi_volume_desc #2 stored in sb->s_fs_info->ubi - ubi_close_volume(ubi) i.e. ubi_close_volume(ubi_volume_desc #1) - kfree(ubi_volume_desc #1) - sb stored in global ubifs_sb (including ubi_volume_desc #2) ubifsload - do_ubifs_load - ubifs_load - ubifs_read - ubi_open_volume -> returns ubi_volume_desc #3 - ubi_volume_desc #3 stored in ubifs_sb->s_fs_info->ubi (this overwrites ubi_volume_desc #2!) - ubi_close_volume(ubifs_sb->s_fs_info->ubi) i.e. ubi_close_volume(ubi_volume_desc #3) - kfree(ubi_volume_desc #3) ubifsumount - do_ubifs_umount - cmd_ubifs_umount - uboot_ubifs_umount - ubifs_umount(ubifs_sb->s_fs_info) - ubi_close_volume(ubifs_sb->s_fs_info->ubi) i.e. ubi_close_volume(ubi_volume_desc #3) - kfree(ubi_volume_desc #3) - this is a double free error, ubi_volume_desc #2 should be closed instead (but the reference has been lost)! The issue seems to be that ubifs_read overwrites the ubi_volume_desc that's stored in the superblock, and thus ubi_volume_desc #2 is never freed, while ubi_volume_desc #3 is freed twice. I'm not sure what the correct behaviour should be: - should the volume be closed at the end of ubifs_mount, or stay open until ubifs_umount? - should ubifs_read not open the volume if it is already open? Thanks in advance! Regards, Felix
Double free error with ubi_volume_desc/ubi_close_volume
Hi all, I seem to be running into a double free error with ubi_volume_desc/ubi_close_volume during a ubifsmount/ubifsload/ubifsumount sequence. This is the sequence that I'm seeing: ubifsmount - do_ubifs_mount - cmd_ubifs_mount - uboot_ubifs_mount - ubifs_mount - open_ubi - ubi_open_volume -> returns ubi_volume_desc #1 - open_ubi returns ubi_volume_desc #1 - ubi_volume_desc #1 stored in local ubi variable - ubifs_fill_super - ubi_open_volume returns ubi_volume_desc #2 - ubi_volume_desc #2 stored in sb->s_fs_info->ubi - ubi_close_volume(ubi) i.e. ubi_close_volume(ubi_volume_desc #1) - kfree(ubi_volume_desc #1) - sb stored in global ubifs_sb (including ubi_volume_desc #2) ubifsload - do_ubifs_load - ubifs_load - ubifs_read - ubi_open_volume -> returns ubi_volume_desc #3 - ubi_volume_desc #3 stored in ubifs_sb->s_fs_info->ubi (this overwrites ubi_volume_desc #2!) - ubi_close_volume(ubifs_sb->s_fs_info->ubi) i.e. ubi_close_volume(ubi_volume_desc #3) - kfree(ubi_volume_desc #3) ubifsumount - do_ubifs_umount - cmd_ubifs_umount - uboot_ubifs_umount - ubifs_umount(ubifs_sb->s_fs_info) - ubi_close_volume(ubifs_sb->s_fs_info->ubi) i.e. ubi_close_volume(ubi_volume_desc #3) - kfree(ubi_volume_desc #3) - this is a double free error, ubi_volume_desc #2 should be closed instead (but the reference has been lost)! The issue seems to be that ubifs_read overwrites the ubi_volume_desc that's stored in the superblock, and thus ubi_volume_desc #2 is never freed, while ubi_volume_desc #3 is freed twice. I'm not sure what the correct behaviour should be: - should the volume be closed at the end of ubifs_mount, or stay open until ubifs_umount? - should ubifs_read not open the volume if it is already open? Thanks in advance! Regards, Felix
How to load raw disk image in u-boot?
Hello,
I am working on the secure boot for raspberry pi topic as described here
https://github.com/raspberrypi/usbboot/tree/master?tab=readme-ov-file#secure-boot---image-creation
The
boot.img file contains u-boot.bin, config.txt, boot.scr, Image, DTB and
other raspberry pi necessary files.
But when I try to integrate this with u-boot, the boot.img is not being
parsed and I see below errors
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
No EFI system partition
BootOrder not defined
EFI boot manager: Cannot load any image
I tried to manually load it using:
fatload mmc 0:1 ${kernel_addr_r} boot.img
this works but, booty is not able to run it
booti ${kernel_addr_r} - ${fdt_addr}
Bad Linux ARM64 Image magic!
I believe first we need to uncompress the raw disk image and then load it.
However with unzip it is not possible to do it.
unzip ${kernel_addr_r} 0x8300
Error: Bad gzipped data
So, how can we load the raw disk image in U-boot?
Re:Re: [PATCH v2 1/2] board: rockchip: Add support for rk3588s based Cool Pi 4B
Hi Quentin： At 2024-02-15 18:40:25, "Quentin Schulz" wrote: >Hi Andy, > >On 2/15/24 11:35, Andy Yan wrote: >[...] diff --git a/configs/coolpi-4b-rk3588s_defconfig b/configs/coolpi-4b-rk3588s_defconfig new file mode 100644 index 00..3e3e5abc86 --- /dev/null +++ b/configs/coolpi-4b-rk3588s_defconfig @@ -0,0 +1,105 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=2400 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a0 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0 +CONFIG_SF_DEFAULT_SPEED=2400 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x60 +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SPL_STACK=0x40 +CONFIG_DEBUG_UART_BASE=0xFEB5 +CONFIG_DEBUG_UART_CLOCK=2400 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x4 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x6 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=150 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y >>> >>> Is there any reason for NOT enabling MMC_HS400_ES? >> >> No, I just follow the config of other rk3588/s based boards. > >Fortunately enough, a patch was recently merged to have at least HS200 >on RK3588, which is the first mode that actually works, anything below >that is broken right now. > >> It seems that there are no rk3588/s based boards enable MMC_HS400_ES in the >> current u-boot mainline ? >> > >Jaguar is hopefully coming soon-ish, maybe not in this release but the >next one (patches are sent already), and we make us of it in U-Boot >proper and the SPL. Up to you, can always be enabled later on. With a quick search， I fond jonas'S patch for enabling HS200 has been merged, but your patch will bring HS400_ES, does that mean all the rk3588/s based boars will switch to HS400 ES if they support it? Thanks. > >FWIW, both comments on this patch also apply to the second patch in this >series :) > >Cheers, >Quentin
Re: [PATCH v2 2/3] board: Add support for Sielaff i.MX6 Solo board
Hi Frieder, On Tue, Feb 13, 2024 at 2:22 PM Frieder Schrempf wrote: > > From: Frieder Schrempf > > The Sielaff i.MX6 Solo board is a control and HMI board for vending > machines. Add support for this board. > > The devicetree files are taken from pending changes in the Linux > kernel that are available from linux-next and will likely be > part of Linux v6.9. > > Signed-off-by: Frieder Schrempf > --- > Changes in v2: > * Implement changes suggested by Fabio (Thanks!) > * Fix system reset and remove unneeded cpu_reset() > * Add 'static const' to nfc_pads[] > * Remove hostname from env > * Remove options to disable caches > * Enable watchdog and wdt command > * Enable LTO I put this series in CI and it complained that there is no MAINTAINERS entry for this board: https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/784464 and there was also an issue with the documentation: https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/784463 Please fix these two issues and submit v3.
Re: [PATCH v2 1/2] board: rockchip: Add support for rk3588s based Cool Pi 4B
Hi Andy, On 2/15/24 12:55, Andy Yan wrote: [You don't often get email from andys...@163.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] Hi Quentin： At 2024-02-15 18:40:25, "Quentin Schulz" wrote: Hi Andy, On 2/15/24 11:35, Andy Yan wrote: [...] diff --git a/configs/coolpi-4b-rk3588s_defconfig b/configs/coolpi-4b-rk3588s_defconfig new file mode 100644 index 00..3e3e5abc86 --- /dev/null +++ b/configs/coolpi-4b-rk3588s_defconfig @@ -0,0 +1,105 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=2400 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a0 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0 +CONFIG_SF_DEFAULT_SPEED=2400 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x60 +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SPL_STACK=0x40 +CONFIG_DEBUG_UART_BASE=0xFEB5 +CONFIG_DEBUG_UART_CLOCK=2400 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x4 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x6 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=150 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y Is there any reason for NOT enabling MMC_HS400_ES? No, I just follow the config of other rk3588/s based boards. Fortunately enough, a patch was recently merged to have at least HS200 on RK3588, which is the first mode that actually works, anything below that is broken right now. It seems that there are no rk3588/s based boards enable MMC_HS400_ES in the current u-boot mainline ? Jaguar is hopefully coming soon-ish, maybe not in this release but the next one (patches are sent already), and we make us of it in U-Boot proper and the SPL. Up to you, can always be enabled later on. With a quick search， I fond jonas'S patch for enabling HS200 has been merged, but your patch will bring HS400_ES, does that mean all the rk3588/s based boars will switch to HS400 ES if they support it? No, it's on a per-board basis. Not all eMMC or boards support HS400/HS400_ES, it depends on the signal quality/integrity and the eMMC chip itself if I'm not mistaken. If I remember correctly, Jonas had some RK3588 boards which didn't work with HS400/HS400_ES (probably one of those boards with the eMMC that is plugged in?). Now to come to think of it... I don't know how/why HS400 isn't enabled only when it's present in the DTB? Cheers, Quentin
Re: [PATCH v2] scripts: dtc-version: Don't show error messages
On Wed, Feb 14, 2024 at 04:48:52AM +0100, Dragan Simic wrote: > On 2024-02-06 12:00, Dragan Simic wrote: > > Prevent the error messages produced by which(1), such as the one quoted > > below, from being visible in the build outputs. > > > > which: no dtc in (./scripts/dtc) > > > > This makes the build outputs look a tiny bit cleaner. > > Just checking, is there something that prevents this patch from > becoming merged? I'll probably take this once the merge window opens, thanks. -- Tom signature.asc Description: PGP signature
Re: [GIT PULL] xilinx patches for v2024.04-rc3
On Wed, Feb 14, 2024 at 04:59:52PM +0100, Michal Simek wrote: > Hi Tom, > > please pull these patches to your branch. Most of them are related to device > tree and aligning with the latest dt schema for SR certification. > CI is not reporting any issue too. > > Thanks, > Michal > > > The following changes since commit e8f2404e093daf6cc3ac2b3233e3c6770d13e371: > > Merge branch 'master-779h0-r2' of > https://source.denx.de/u-boot/custodians/u-boot-sh (2024-02-11 12:42:25 > -0500) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-microblaze.git > tags/xilinx-for-v2024.04-rc3 > > for you to fetch changes up to c2ad5fb616d4e8aa2ac00e224030589847731fbe: > > arm64: versal-net: Setup correct addresses of GICR/GICD (2024-02-14 > 11:23:43 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: EXT: [PATCH 2/5] msc_sm2s_imx8mp: Make Ethernet functional
On Tue, Feb 13, 2024 at 08:43:39AM -0300, Fabio Estevam wrote: > > From: Fabio Estevam > > Currently, the Ethernet ports are not working. > > The Ethernet PHY reset lines are controlled by the TCA6424 I2C GPIO > expander. > > The TCA6424 I2C GPIO expander is supported by the CONFIG_DM_PCA953X > driver. > > Select the CONFIG_DM_PCA953X option so that the Ethernet PHYs can > go through a proper reset making Ethernet to be functional. > > Signed-off-by: Fabio Estevam Reviewed-by: Ian Ray > --- > configs/msc_sm2s_imx8mp_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/configs/msc_sm2s_imx8mp_defconfig > b/configs/msc_sm2s_imx8mp_defconfig > index 9c27a72f8a..a190c1ea22 100644 > --- a/configs/msc_sm2s_imx8mp_defconfig > +++ b/configs/msc_sm2s_imx8mp_defconfig > @@ -72,6 +72,7 @@ CONFIG_CLK_COMPOSITE_CCF=y > CONFIG_SPL_CLK_IMX8MP=y > CONFIG_CLK_IMX8MP=y > CONFIG_MXC_GPIO=y > +CONFIG_DM_PCA953X=y > CONFIG_DM_I2C=y > CONFIG_LED=y > CONFIG_LED_GPIO=y > -- > 2.34.1 > >
Re: EXT: [PATCH 1/5] msc_sm2s_imx8mp: Convert to DM_SERIAL
On Tue, Feb 13, 2024 at 08:43:38AM -0300, Fabio Estevam wrote:
>
> From: Fabio Estevam
>
> The conversion to DM_SERIAL is mandatory, so do the conversion.
>
> Signed-off-by: Fabio Estevam
Reviewed-by: Ian Ray
> ---
> arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi | 8
> board/msc/sm2s_imx8mp/spl.c | 9 -
> configs/msc_sm2s_imx8mp_defconfig| 1 +
> include/configs/msc_sm2s_imx8mp.h| 2 --
> 4 files changed, 9 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi
> b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi
> index c398a743f7..1a7b530d9f 100644
> --- a/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi
> @@ -63,3 +63,11 @@
> &pmic {
> bootph-pre-ram;
> };
> +
> +&uart2 {
> + bootph-pre-ram;
> +};
> +
> +&pinctrl_uart2 {
> + bootph-pre-ram;
> +};
> diff --git a/board/msc/sm2s_imx8mp/spl.c b/board/msc/sm2s_imx8mp/spl.c
> index fed0fbcba1..ed7a1b7d3d 100644
> --- a/board/msc/sm2s_imx8mp/spl.c
> +++ b/board/msc/sm2s_imx8mp/spl.c
> @@ -168,13 +168,6 @@ static const iomux_v3_cfg_t wdog_pads[] = {
> MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> };
>
> -#define UART_PAD_CTRL(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> -
> -static const iomux_v3_cfg_t ser0_pads[] = {
> - MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> - MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> -};
> -
> int board_early_init_f(void)
> {
> struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> @@ -182,8 +175,6 @@ int board_early_init_f(void)
> imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
> set_wdog_reset(wdog);
>
> - imx_iomux_v3_setup_multiple_pads(ser0_pads, ARRAY_SIZE(ser0_pads));
> -
> return 0;
> }
>
> diff --git a/configs/msc_sm2s_imx8mp_defconfig
> b/configs/msc_sm2s_imx8mp_defconfig
> index bf1052db6f..9c27a72f8a 100644
> --- a/configs/msc_sm2s_imx8mp_defconfig
> +++ b/configs/msc_sm2s_imx8mp_defconfig
> @@ -97,6 +97,7 @@ CONFIG_SPL_PMIC_RN5T567=y
> CONFIG_DM_REGULATOR=y
> CONFIG_DM_REGULATOR_FIXED=y
> CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_DM_SERIAL=y
> CONFIG_MXC_UART=y
> CONFIG_SYSRESET=y
> CONFIG_SPL_SYSRESET=y
> diff --git a/include/configs/msc_sm2s_imx8mp.h
> b/include/configs/msc_sm2s_imx8mp.h
> index c1c1fd5a78..3c7d96cb3c 100644
> --- a/include/configs/msc_sm2s_imx8mp.h
> +++ b/include/configs/msc_sm2s_imx8mp.h
> @@ -55,8 +55,6 @@
> #define PHYS_SDRAM_2 0xc000
> #define PHYS_SDRAM_2_SIZE0x0
>
> -#define CFG_MXC_UART_BASEUART2_BASE_ADDR
> -
> #define CFG_SYS_FSL_USDHC_NUM2
> #define CFG_SYS_FSL_ESDHC_ADDR 0
>
> --
> 2.34.1
>
>
Re: EXT: [PATCH 4/5] msc_sm2s_imx8mp: Add redundant environment support
On Tue, Feb 13, 2024 at 08:43:41AM -0300, Fabio Estevam wrote: > > From: Fabio Estevam > > Redundant environment support is required for software updates. > > Add support for it. > > Signed-off-by: Fabio Estevam Reviewed-by: Ian Ray > --- > configs/msc_sm2s_imx8mp_defconfig | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/configs/msc_sm2s_imx8mp_defconfig > b/configs/msc_sm2s_imx8mp_defconfig > index a190c1ea22..3a49b7d55c 100644 > --- a/configs/msc_sm2s_imx8mp_defconfig > +++ b/configs/msc_sm2s_imx8mp_defconfig > @@ -5,7 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x200 > CONFIG_SPL_GPIO=y > CONFIG_SPL_LIBCOMMON_SUPPORT=y > CONFIG_SPL_LIBGENERIC_SUPPORT=y > -CONFIG_ENV_SIZE=0x1000 > +CONFIG_ENV_SIZE=0x4000 > +CONFIG_ENV_OFFSET=0x20 > CONFIG_DM_GPIO=y > CONFIG_DEFAULT_DEVICE_TREE="imx8mp-msc-sm2s" > CONFIG_SPL_TEXT_BASE=0x92 > @@ -16,6 +17,7 @@ CONFIG_SPL_SERIAL=y > CONFIG_SPL_DRIVERS_MISC=y > CONFIG_SPL_STACK=0x96 > CONFIG_SPL=y > +CONFIG_ENV_OFFSET_REDUND=0x204000 > CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800 > CONFIG_SYS_LOAD_ADDR=0x4048 > CONFIG_SYS_BOOT_GET_CMDLINE=y > @@ -62,6 +64,8 @@ CONFIG_CMD_EXT4_WRITE=y > CONFIG_OF_CONTROL=y > CONFIG_SPL_OF_CONTROL=y > CONFIG_ENV_OVERWRITE=y > +CONFIG_ENV_IS_IN_MMC=y > +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y > CONFIG_SYS_RELOC_GD_ENV_ADDR=y > CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y > CONFIG_USE_ETHPRIME=y > -- > 2.34.1 > >
Re: EXT: [PATCH 3/5] imx8mp-msc-sm2s: Add mmc aliases
On Tue, Feb 13, 2024 at 08:43:40AM -0300, Fabio Estevam wrote:
>
> From: Fabio Estevam
>
> Add mmc alias so that the eMMC is mmc0 and the SD card
> is mmc1 to have a well defined device numbering scheme.
>
> Signed-off-by: Fabio Estevam
Reviewed-by: Ian Ray
> ---
> arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi
> b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi
> index 1a7b530d9f..ce61ca6671 100644
> --- a/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi
> @@ -9,6 +9,11 @@
> model = "MSC SM2S-IMX8MPLUS";
> compatible = "avnet,sm2s-imx8mp", "fsl,imx8mp";
>
> + aliases {
> + mmc0 = &usdhc3;
> + mmc1 = &usdhc2;
> + };
> +
> wdt-reboot {
> compatible = "wdt-reboot";
> wdt = <&wdog1>;
> --
> 2.34.1
>
>
Re: EXT: [PATCH 5/5] msc_sm2s_imx8mp: Fix CONFIG_DEFAULT_FDT_FILE
On Tue, Feb 13, 2024 at 08:43:42AM -0300, Fabio Estevam wrote: > > From: Fabio Estevam > > There is no imx8mp-msc-sm2s.dtb file in upstream Linux. > > Change it to imx8mp-msc-sm2s-ep1.dtb. > > Signed-off-by: Fabio Estevam Reviewed-by: Ian Ray > --- > configs/msc_sm2s_imx8mp_defconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/configs/msc_sm2s_imx8mp_defconfig > b/configs/msc_sm2s_imx8mp_defconfig > index 3a49b7d55c..5688c7a64d 100644 > --- a/configs/msc_sm2s_imx8mp_defconfig > +++ b/configs/msc_sm2s_imx8mp_defconfig > @@ -28,7 +28,7 @@ CONFIG_SPL_LOAD_FIT=y > CONFIG_SYS_BOOTM_LEN=0x200 > CONFIG_DISTRO_DEFAULTS=y > CONFIG_OF_SYSTEM_SETUP=y > -CONFIG_DEFAULT_FDT_FILE="imx8mp-msc-sm2s.dtb" > +CONFIG_DEFAULT_FDT_FILE="imx8mp-msc-sm2s-ep1.dtb" > CONFIG_SYS_CBSIZE=2048 > CONFIG_SYS_PBSIZE=2074 > CONFIG_SPL_MAX_SIZE=0x26000 > -- > 2.34.1 > >
Re: ACPI Vendor ID Request
On Sun, Jan 21, 2024 at 10:17:22AM -0500, Tom Rini wrote: > On Sun, Jan 21, 2024 at 03:42:16PM +0100, Heinrich Schuchardt wrote: > > Hello Tom, > > > > as we have started to generate ACPI tables in U-Boot we should request an > > ACPI vendor ID for the U-Boot project. > > > > As described in https://uefi.org/PNP_ACPI_Registry this is done by sending a > > mail to vid-requ...@uefi.org. > > > > As the ID is meant to have 4 letters I suggest to use 'UBOO'. > > > > https://uefi.org/ACPI_ID_List shows existing IDs. I don't know if the owner > > must be a legal company (which probably needs to be member of the UEFI > > forum) or we simply can have "Das U-Boot project" as owner. > > I see from the list that Coreboot has "BOOT" so presumably we can > request UBOO for the project, and I've done so now. For the record, we've been granted the ID 'UBOO' now, officially. -- Tom signature.asc Description: PGP signature
[PATCH v3 1/3] mtd: spi-nor-ids: Add support for ESMT/EON EN25Q80B
From: Frieder Schrempf
The datasheet can be found here:
https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25Q80B_Ver.E.pdf
Signed-off-by: Frieder Schrempf
Reviewed-by: Fabio Estevam
---
Changes in v3:
* none
Changes in v2:
* Add R-b tag from Fabio (Thanks!)
---
drivers/mtd/spi/spi-nor-ids.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 38a287487ed..4e83b8c94c9 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -80,6 +80,7 @@ const struct flash_info spi_nor_ids[] = {
#endif
#ifdef CONFIG_SPI_FLASH_EON/* EON */
/* EON -- en25xxx */
+ { INFO("en25q80b", 0x1c3014, 0, 64 * 1024, 16, SECT_4K) },
{ INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
{ INFO("en25q64",0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) },
--
2.43.0
[PATCH v3 2/3] board: Add support for Sielaff i.MX6 Solo board
From: Frieder Schrempf
The Sielaff i.MX6 Solo board is a control and HMI board for vending
machines. Add support for this board.
The devicetree files are taken from pending changes in the Linux
kernel that are available from linux-next and will likely be
part of Linux v6.9.
Signed-off-by: Frieder Schrempf
---
Changes in v3:
* Add missing MAINTAINERS file
Changes in v2:
* Implement changes suggested by Fabio (Thanks!)
* Fix system reset and remove unneeded cpu_reset()
* Add 'static const' to nfc_pads[]
* Remove hostname from env
* Remove options to disable caches
* Enable watchdog and wdt command
* Enable LTO
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx6dl-sielaff-u-boot.dtsi | 38 ++
arch/arm/dts/imx6dl-sielaff.dts | 533 ++
arch/arm/mach-imx/mx6/Kconfig | 10 +
board/sielaff/imx6dl-sielaff/Kconfig | 15 +
board/sielaff/imx6dl-sielaff/MAINTAINERS | 9 +
board/sielaff/imx6dl-sielaff/Makefile | 8 +
board/sielaff/imx6dl-sielaff/imx6dl-sielaff.c | 111
.../sielaff/imx6dl-sielaff/imx6dl-sielaff.env | 114
board/sielaff/imx6dl-sielaff/spl.c| 273 +
configs/imx6dl_sielaff_defconfig | 120
include/configs/imx6dl-sielaff.h | 25 +
12 files changed, 1257 insertions(+)
create mode 100644 arch/arm/dts/imx6dl-sielaff-u-boot.dtsi
create mode 100644 arch/arm/dts/imx6dl-sielaff.dts
create mode 100644 board/sielaff/imx6dl-sielaff/Kconfig
create mode 100644 board/sielaff/imx6dl-sielaff/MAINTAINERS
create mode 100644 board/sielaff/imx6dl-sielaff/Makefile
create mode 100644 board/sielaff/imx6dl-sielaff/imx6dl-sielaff.c
create mode 100644 board/sielaff/imx6dl-sielaff/imx6dl-sielaff.env
create mode 100644 board/sielaff/imx6dl-sielaff/spl.c
create mode 100644 configs/imx6dl_sielaff_defconfig
create mode 100644 include/configs/imx6dl-sielaff.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0fcae77cefe..d60fa1179af 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -930,6 +930,7 @@ dtb-y += \
imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
+ imx6dl-sielaff.dtb \
imx6dl-wandboard-revd1.dtb \
imx6s-dhcom-drc02.dtb
diff --git a/arch/arm/dts/imx6dl-sielaff-u-boot.dtsi
b/arch/arm/dts/imx6dl-sielaff-u-boot.dtsi
new file mode 100644
index 000..8f5a70ccb85
--- /dev/null
+++ b/arch/arm/dts/imx6dl-sielaff-u-boot.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+/ {
+ binman: binman {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ offset = <0x0>;
+ filename = "SPL";
+ };
+
+ uboot: blob-ext@2 {
+ offset = <0x11000>;
+ filename = "u-boot.img";
+ };
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ };
+};
+
+&fec {
+ phy-mode = "rmii";
+ phy-reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <100>;
+};
+
+&gpmi {
+ fsl,legacy-bch-geometry;
+};
diff --git a/arch/arm/dts/imx6dl-sielaff.dts b/arch/arm/dts/imx6dl-sielaff.dts
new file mode 100644
index 000..7de8d5f2651
--- /dev/null
+++ b/arch/arm/dts/imx6dl-sielaff.dts
@@ -0,0 +1,533 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include
+#include
+#include
+
+/ {
+ model = "Sielaff i.MX6 Solo";
+ compatible = "sielaff,imx6dl-board", "fsl,imx6dl";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ backlight: pwm-backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight>;
+ pwms = <&pwm3 0 5 0>;
+ brightness-levels = <0 0 64 88 112 136 184 232 255>;
+ default-brightness-level = <4>;
+ enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+ power-supply = <®_backlight>;
+ };
+
+ cec {
+ compatible = "cec-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi_cec>;
+ cec-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+ hdmi-phandle = <&hdmi>;
+ };
+
+ enet_ref: clock-enet-ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <5000>;
+ clock-output-names = "enet-ref";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&
[PATCH v3 3/3] doc: board: Add minimal documentation for Sielaff i.MX6 Solo board
From: Frieder Schrempf Describe how to build and boot for the Sielaff i.MX6 Solo board. Signed-off-by: Frieder Schrempf --- Changes in v3: * include docs in upper-level index Changes in v2: * none --- doc/board/index.rst | 1 + doc/board/sielaff/imx6dl-sielaff.rst | 32 doc/board/sielaff/index.rst | 9 3 files changed, 42 insertions(+) create mode 100644 doc/board/sielaff/imx6dl-sielaff.rst create mode 100644 doc/board/sielaff/index.rst diff --git a/doc/board/index.rst b/doc/board/index.rst index d0f9f355d2e..62357c99388 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -42,6 +42,7 @@ Board-specific doc renesas/index rockchip/index samsung/index + sielaff/index siemens/index sifive/index sipeed/index diff --git a/doc/board/sielaff/imx6dl-sielaff.rst b/doc/board/sielaff/imx6dl-sielaff.rst new file mode 100644 index 000..24dd67ccaef --- /dev/null +++ b/doc/board/sielaff/imx6dl-sielaff.rst @@ -0,0 +1,32 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Sielaff i.MX6 Solo Board + + +The Sielaff i.MX6 Solo board is a control and HMI board for vending +machines. + +Quick Start +--- + +- Build U-Boot +- Boot + +Build U-Boot + + +.. code-block:: bash + + $ make imx6dl_sielaff_defconfig + $ make CROSS_COMPILE=arm-none-linux-gnueabihf- + +Burn the flash.bin to SD card at an offset of 1 KiB: + +.. code-block:: bash + + $ dd if=flash.bin of=/dev/sd[x] bs=1K seek=1 conv=notrunc + +Boot + + +Put the SD card in the slot on the board and apply power. diff --git a/doc/board/sielaff/index.rst b/doc/board/sielaff/index.rst new file mode 100644 index 000..a8376484d88 --- /dev/null +++ b/doc/board/sielaff/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Sielaff +=== + +.. toctree:: + :maxdepth: 2 + + imx6dl-sielaff -- 2.43.0
Re: [PATCH v2 2/3] board: Add support for Sielaff i.MX6 Solo board
On 15.02.24 13:27, Fabio Estevam wrote: > Hi Frieder, > > On Tue, Feb 13, 2024 at 2:22 PM Frieder Schrempf wrote: >> >> From: Frieder Schrempf >> >> The Sielaff i.MX6 Solo board is a control and HMI board for vending >> machines. Add support for this board. >> >> The devicetree files are taken from pending changes in the Linux >> kernel that are available from linux-next and will likely be >> part of Linux v6.9. >> >> Signed-off-by: Frieder Schrempf >> --- >> Changes in v2: >> * Implement changes suggested by Fabio (Thanks!) >> * Fix system reset and remove unneeded cpu_reset() >> * Add 'static const' to nfc_pads[] >> * Remove hostname from env >> * Remove options to disable caches >> * Enable watchdog and wdt command >> * Enable LTO > > I put this series in CI and it complained that there is no MAINTAINERS > entry for this board: > > https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/784464 > > and there was also an issue with the documentation: > > https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/784463 > > Please fix these two issues and submit v3. Oops, right. Totally forgot about these two things. I just sent out a v3. Thanks!
Re: [PATCH v3 3/3] doc: board: Add minimal documentation for Sielaff i.MX6 Solo board
On 15.02.24 2:35 PM, Frieder Schrempf wrote: From: Frieder Schrempf Describe how to build and boot for the Sielaff i.MX6 Solo board. Signed-off-by: Frieder Schrempf --- Changes in v3: * include docs in upper-level index Changes in v2: * none --- doc/board/index.rst | 1 + doc/board/sielaff/imx6dl-sielaff.rst | 32 doc/board/sielaff/index.rst | 9 3 files changed, 42 insertions(+) create mode 100644 doc/board/sielaff/imx6dl-sielaff.rst create mode 100644 doc/board/sielaff/index.rst diff --git a/doc/board/index.rst b/doc/board/index.rst index d0f9f355d2e..62357c99388 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -42,6 +42,7 @@ Board-specific doc renesas/index rockchip/index samsung/index + sielaff/index siemens/index sifive/index sipeed/index diff --git a/doc/board/sielaff/imx6dl-sielaff.rst b/doc/board/sielaff/imx6dl-sielaff.rst new file mode 100644 index 000..24dd67ccaef --- /dev/null +++ b/doc/board/sielaff/imx6dl-sielaff.rst @@ -0,0 +1,32 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Sielaff i.MX6 Solo Board + + +The Sielaff i.MX6 Solo board is a control and HMI board for vending +machines. Thank you for providing the build instruction. I had to look up the abbreviation: %s/HMI/Human Machine Interface (HMI)/ + +Quick Start +--- + +- Build U-Boot +- Boot These lines are not needed. We have a navigation tree on the left side of the generated HTML page. + +Build U-Boot + + +.. code-block:: bash + + $ make imx6dl_sielaff_defconfig + $ make CROSS_COMPILE=arm-none-linux-gnueabihf- U-Boot does not use floats. make CROSS_COMPILE=arm-linux-gnueabi- + +Burn the flash.bin to SD card at an offset of 1 KiB: Copy the flash.bin file to an SD card at an offset of 1 KiB: + +.. code-block:: bash + + $ dd if=flash.bin of=/dev/sd[x] bs=1K seek=1 conv=notrunc Please, remove '$ '. It makes copy and paste more difficult. Anyway $ is the wrong prompt. Only root can use dd. If you really want a prompt, use: .. prompt:: bash # conv=notrunc has no effect on SD-cards but is needed when copying to an image file. Best regards Heinrich + +Boot + + +Put the SD card in the slot on the board and apply power. diff --git a/doc/board/sielaff/index.rst b/doc/board/sielaff/index.rst new file mode 100644 index 000..a8376484d88 --- /dev/null +++ b/doc/board/sielaff/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Sielaff +=== + +.. toctree:: + :maxdepth: 2 + + imx6dl-sielaff
[PATCH v4 1/3] mtd: spi-nor-ids: Add support for ESMT/EON EN25Q80B
From: Frieder Schrempf
The datasheet can be found here:
https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25Q80B_Ver.E.pdf
Signed-off-by: Frieder Schrempf
Reviewed-by: Fabio Estevam
---
Changes in v4:
* none
Changes in v3:
* none
Changes in v2:
* Add R-b tag from Fabio (Thanks!)
---
drivers/mtd/spi/spi-nor-ids.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 38a287487ed..4e83b8c94c9 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -80,6 +80,7 @@ const struct flash_info spi_nor_ids[] = {
#endif
#ifdef CONFIG_SPI_FLASH_EON/* EON */
/* EON -- en25xxx */
+ { INFO("en25q80b", 0x1c3014, 0, 64 * 1024, 16, SECT_4K) },
{ INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
{ INFO("en25q64",0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) },
--
2.43.0
[PATCH v4 2/3] board: Add support for Sielaff i.MX6 Solo board
From: Frieder Schrempf
The Sielaff i.MX6 Solo board is a control and HMI board for vending
machines. Add support for this board.
The devicetree files are taken from pending changes in the Linux
kernel that are available from linux-next and will likely be
part of Linux v6.9.
Signed-off-by: Frieder Schrempf
---
Changes in v4:
* none
Changes in v3:
* Add missing MAINTAINERS file
Changes in v2:
* Implement changes suggested by Fabio (Thanks!)
* Fix system reset and remove unneeded cpu_reset()
* Add 'static const' to nfc_pads[]
* Remove hostname from env
* Remove options to disable caches
* Enable watchdog and wdt command
* Enable LTO
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx6dl-sielaff-u-boot.dtsi | 38 ++
arch/arm/dts/imx6dl-sielaff.dts | 533 ++
arch/arm/mach-imx/mx6/Kconfig | 10 +
board/sielaff/imx6dl-sielaff/Kconfig | 15 +
board/sielaff/imx6dl-sielaff/MAINTAINERS | 9 +
board/sielaff/imx6dl-sielaff/Makefile | 8 +
board/sielaff/imx6dl-sielaff/imx6dl-sielaff.c | 111
.../sielaff/imx6dl-sielaff/imx6dl-sielaff.env | 114
board/sielaff/imx6dl-sielaff/spl.c| 273 +
configs/imx6dl_sielaff_defconfig | 120
include/configs/imx6dl-sielaff.h | 25 +
12 files changed, 1257 insertions(+)
create mode 100644 arch/arm/dts/imx6dl-sielaff-u-boot.dtsi
create mode 100644 arch/arm/dts/imx6dl-sielaff.dts
create mode 100644 board/sielaff/imx6dl-sielaff/Kconfig
create mode 100644 board/sielaff/imx6dl-sielaff/MAINTAINERS
create mode 100644 board/sielaff/imx6dl-sielaff/Makefile
create mode 100644 board/sielaff/imx6dl-sielaff/imx6dl-sielaff.c
create mode 100644 board/sielaff/imx6dl-sielaff/imx6dl-sielaff.env
create mode 100644 board/sielaff/imx6dl-sielaff/spl.c
create mode 100644 configs/imx6dl_sielaff_defconfig
create mode 100644 include/configs/imx6dl-sielaff.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0fcae77cefe..d60fa1179af 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -930,6 +930,7 @@ dtb-y += \
imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
+ imx6dl-sielaff.dtb \
imx6dl-wandboard-revd1.dtb \
imx6s-dhcom-drc02.dtb
diff --git a/arch/arm/dts/imx6dl-sielaff-u-boot.dtsi
b/arch/arm/dts/imx6dl-sielaff-u-boot.dtsi
new file mode 100644
index 000..8f5a70ccb85
--- /dev/null
+++ b/arch/arm/dts/imx6dl-sielaff-u-boot.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+/ {
+ binman: binman {
+ filename = "flash.bin";
+ pad-byte = <0x00>;
+
+ spl: blob-ext@1 {
+ offset = <0x0>;
+ filename = "SPL";
+ };
+
+ uboot: blob-ext@2 {
+ offset = <0x11000>;
+ filename = "u-boot.img";
+ };
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ };
+};
+
+&fec {
+ phy-mode = "rmii";
+ phy-reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <100>;
+};
+
+&gpmi {
+ fsl,legacy-bch-geometry;
+};
diff --git a/arch/arm/dts/imx6dl-sielaff.dts b/arch/arm/dts/imx6dl-sielaff.dts
new file mode 100644
index 000..7de8d5f2651
--- /dev/null
+++ b/arch/arm/dts/imx6dl-sielaff.dts
@@ -0,0 +1,533 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2022 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include
+#include
+#include
+
+/ {
+ model = "Sielaff i.MX6 Solo";
+ compatible = "sielaff,imx6dl-board", "fsl,imx6dl";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ backlight: pwm-backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight>;
+ pwms = <&pwm3 0 5 0>;
+ brightness-levels = <0 0 64 88 112 136 184 232 255>;
+ default-brightness-level = <4>;
+ enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+ power-supply = <®_backlight>;
+ };
+
+ cec {
+ compatible = "cec-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi_cec>;
+ cec-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+ hdmi-phandle = <&hdmi>;
+ };
+
+ enet_ref: clock-enet-ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <5000>;
+ clock-output-names = "enet-ref";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+
[PATCH v4 3/3] doc: board: Add minimal documentation for Sielaff i.MX6 Solo board
From: Frieder Schrempf Describe how to build and boot for the Sielaff i.MX6 Solo board. Signed-off-by: Frieder Schrempf --- Changes in v4: * changes requested by Heinrich (thanks!) Changes in v3: * include docs in upper-level index Changes in v2: * none --- doc/board/index.rst | 1 + doc/board/sielaff/imx6dl-sielaff.rst | 29 doc/board/sielaff/index.rst | 9 + 3 files changed, 39 insertions(+) create mode 100644 doc/board/sielaff/imx6dl-sielaff.rst create mode 100644 doc/board/sielaff/index.rst diff --git a/doc/board/index.rst b/doc/board/index.rst index d0f9f355d2e..62357c99388 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -42,6 +42,7 @@ Board-specific doc renesas/index rockchip/index samsung/index + sielaff/index siemens/index sifive/index sipeed/index diff --git a/doc/board/sielaff/imx6dl-sielaff.rst b/doc/board/sielaff/imx6dl-sielaff.rst new file mode 100644 index 000..699079b3271 --- /dev/null +++ b/doc/board/sielaff/imx6dl-sielaff.rst @@ -0,0 +1,29 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Sielaff i.MX6 Solo Board + + +The Sielaff i.MX6 Solo board is a control and Human Machine Interface (HMI) +board for vending machines. + +Quick Start +--- + +Build U-Boot + + +.. code-block:: bash + + make imx6dl_sielaff_defconfig + make CROSS_COMPILE=arm-linux-gnueabi- + +Copy the flash.bin file to an SD card at an offset of 1 KiB: + +.. code-block:: bash + + dd if=flash.bin of=/dev/sd[x] bs=1K seek=1 + +Boot + + +Put the SD card in the slot on the board and apply power. diff --git a/doc/board/sielaff/index.rst b/doc/board/sielaff/index.rst new file mode 100644 index 000..a8376484d88 --- /dev/null +++ b/doc/board/sielaff/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Sielaff +=== + +.. toctree:: + :maxdepth: 2 + + imx6dl-sielaff -- 2.43.0
Re: [PATCH v3 3/3] doc: board: Add minimal documentation for Sielaff i.MX6 Solo board
On Thu, Feb 15, 2024 at 02:53:12PM +0100, Heinrich Schuchardt wrote:
> On 15.02.24 2:35 PM, Frieder Schrempf wrote:
> > From: Frieder Schrempf
> >
> > Describe how to build and boot for the Sielaff i.MX6 Solo board.
> >
> > Signed-off-by: Frieder Schrempf
[snip]
> > +Build U-Boot
> > +
> > +
> > +.. code-block:: bash
> > +
> > + $ make imx6dl_sielaff_defconfig
> > + $ make CROSS_COMPILE=arm-none-linux-gnueabihf-
>
> U-Boot does not use floats.
>
> make CROSS_COMPILE=arm-linux-gnueabi-
It's not about floats or not (we pass the right flags) but consistency.
And in that case, yes, we should say arm-linux-gnueabi- but also we
really need to expand doc/build/{gcc,clang}.rst to be generic enough for
platforms to refer back to rather than repeating in slightly different
ways what's in those files.
--
Tom
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Description: PGP signature
Re: [PATCH v3 3/3] doc: board: Add minimal documentation for Sielaff i.MX6 Solo board
Hi Heinrich, thanks for your comments. I fixed all these issues in v4. On 15.02.24 14:53, Heinrich Schuchardt wrote: > On 15.02.24 2:35 PM, Frieder Schrempf wrote: >> From: Frieder Schrempf >> >> Describe how to build and boot for the Sielaff i.MX6 Solo board. >> >> Signed-off-by: Frieder Schrempf >> --- >> Changes in v3: >> * include docs in upper-level index >> >> Changes in v2: >> * none >> --- >> doc/board/index.rst | 1 + >> doc/board/sielaff/imx6dl-sielaff.rst | 32 >> doc/board/sielaff/index.rst | 9 >> 3 files changed, 42 insertions(+) >> create mode 100644 doc/board/sielaff/imx6dl-sielaff.rst >> create mode 100644 doc/board/sielaff/index.rst >> >> diff --git a/doc/board/index.rst b/doc/board/index.rst >> index d0f9f355d2e..62357c99388 100644 >> --- a/doc/board/index.rst >> +++ b/doc/board/index.rst >> @@ -42,6 +42,7 @@ Board-specific doc >> renesas/index >> rockchip/index >> samsung/index >> + sielaff/index >> siemens/index >> sifive/index >> sipeed/index >> diff --git a/doc/board/sielaff/imx6dl-sielaff.rst >> b/doc/board/sielaff/imx6dl-sielaff.rst >> new file mode 100644 >> index 000..24dd67ccaef >> --- /dev/null >> +++ b/doc/board/sielaff/imx6dl-sielaff.rst >> @@ -0,0 +1,32 @@ >> +.. SPDX-License-Identifier: GPL-2.0+ >> + >> +Sielaff i.MX6 Solo Board >> + >> + >> +The Sielaff i.MX6 Solo board is a control and HMI board for vending >> +machines. > > Thank you for providing the build instruction. > > I had to look up the abbreviation: > > %s/HMI/Human Machine Interface (HMI)/ > >> + >> +Quick Start >> +--- >> + >> +- Build U-Boot >> +- Boot > > These lines are not needed. We have a navigation tree on the left side > of the generated HTML page. > >> + >> +Build U-Boot >> + >> + >> +.. code-block:: bash >> + >> + $ make imx6dl_sielaff_defconfig >> + $ make CROSS_COMPILE=arm-none-linux-gnueabihf- > > U-Boot does not use floats. > > make CROSS_COMPILE=arm-linux-gnueabi- > >> + >> +Burn the flash.bin to SD card at an offset of 1 KiB: > > Copy the flash.bin file to an SD card at an offset of 1 KiB: > >> + >> +.. code-block:: bash >> + >> + $ dd if=flash.bin of=/dev/sd[x] bs=1K seek=1 conv=notrunc > > Please, remove '$ '. It makes copy and paste more difficult. > Anyway $ is the wrong prompt. Only root can use dd. > If you really want a prompt, use: > > .. prompt:: bash # > > conv=notrunc has no effect on SD-cards but is needed when copying to an > image file. Thanks Frieder
Re: [PATCH v2] scripts: dtc-version: Don't show error messages
On 2024-02-15 14:13, Tom Rini wrote: On Wed, Feb 14, 2024 at 04:48:52AM +0100, Dragan Simic wrote: On 2024-02-06 12:00, Dragan Simic wrote: > Prevent the error messages produced by which(1), such as the one quoted > below, from being visible in the build outputs. > > which: no dtc in (./scripts/dtc) > > This makes the build outputs look a tiny bit cleaner. Just checking, is there something that prevents this patch from becoming merged? I'll probably take this once the merge window opens, thanks. Great, thanks!
Re: [PATCH v2 17/21] tools: mkfwumdata: migrate to metadata version 2
Hi, On 2/12/24 08:47, Sughosh Ganu wrote: Migrate the metadata generation tool to generate the version 2 metadata. Signed-off-by: Sughosh Ganu --- Changes since V1: * Compute location of struct fwu_fw_store_desc using pointer arithmetic. tools/mkfwumdata.c | 45 ++--- 1 file changed, 34 insertions(+), 11 deletions(-) diff --git a/tools/mkfwumdata.c b/tools/mkfwumdata.c index 9732a8ddc5..fb847e3a78 100644 --- a/tools/mkfwumdata.c +++ b/tools/mkfwumdata.c @@ -14,12 +14,13 @@ #include #include -/* This will dynamically allocate the fwu_mdata */ -#define CONFIG_FWU_NUM_BANKS 0 -#define CONFIG_FWU_NUM_IMAGES_PER_BANK 0 - /* Since we can not include fwu.h, redefine version here. */ -#define FWU_MDATA_VERSION 1 +#define FWU_MDATA_VERSION 2 + +#define MAX_BANKS 4 + +#define BANK_INVALID 0xFF +#define BANK_ACCEPTED 0xFC I think in previous version only active bank was accepted not others. I don't think it is wrong behavior but please consider to select it too. I was just surprised to see both banks in that state. Thanks, Michal
Re: [PATCH v2 18/21] tools: mkfwumdata: add logic to append vendor data to the FWU metadata
On 2/12/24 08:47, Sughosh Ganu wrote:
The version 2 of the FWU metadata allows for appending opaque vendor
specific data to the metadata structure. Add support for appending
this data to the metadata. The vendor specific data needs to be
provided through a file, passed through a command-line parameter.
Signed-off-by: Sughosh Ganu
---
Changes since V1: New patch
tools/mkfwumdata.c | 85 +-
1 file changed, 77 insertions(+), 8 deletions(-)
diff --git a/tools/mkfwumdata.c b/tools/mkfwumdata.c
index fb847e3a78..ab07623e25 100644
--- a/tools/mkfwumdata.c
+++ b/tools/mkfwumdata.c
@@ -12,6 +12,8 @@
#include
#include
#include
+#include
+#include
#include
/* Since we can not include fwu.h, redefine version here. */
@@ -30,7 +32,7 @@ typedef uint64_t u64;
#include
-static const char *opts_short = "b:i:a:p:gh";
+static const char *opts_short = "b:i:a:p:v:gh";
static struct option options[] = {
{"banks", required_argument, NULL, 'b'},
@@ -38,6 +40,7 @@ static struct option options[] = {
{"guid", required_argument, NULL, 'g'},
{"active-bank", required_argument, NULL, 'a'},
{"previous-bank", required_argument, NULL, 'p'},
+ {"vendor-file", required_argument, NULL, 'v'},
{"help", no_argument, NULL, 'h'},
{NULL, 0, NULL, 0},
};
@@ -51,6 +54,7 @@ static void print_usage(void)
"\t-a, --active-bank Active bank (default=0)\n"
"\t-p, --previous-bankPrevious active bank
(default=active_bank - 1)\n"
"\t-g, --guid Use GUID instead of UUID\n"
+ "\t-v, --vendor-file Vendor data file to append to the
metadata\n"
"\t-h, --help print a help message\n"
);
fprintf(stderr, " UUIDs list syntax:\n"
@@ -69,13 +73,16 @@ struct fwu_mdata_object {
size_t images;
size_t banks;
size_t size;
+ size_t vsize;
+ void *vbuf;
struct fwu_mdata *mdata;
};
static int previous_bank, active_bank;
static bool __use_guid;
-static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks)
+static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks,
+ size_t vendor_size)
{
struct fwu_mdata_object *mobj;
@@ -87,16 +94,28 @@ static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks)
sizeof(struct fwu_fw_store_desc) +
(sizeof(struct fwu_image_entry) +
sizeof(struct fwu_image_bank_info) * banks) * images;
+
+ mobj->size += vendor_size;
+ mobj->vsize = vendor_size;
mobj->images = images;
mobj->banks = banks;
mobj->mdata = calloc(1, mobj->size);
- if (!mobj->mdata) {
- free(mobj);
- return NULL;
+ if (!mobj->mdata)
+ goto alloc_err;
+
+ if (vendor_size) {
+ mobj->vbuf = calloc(1, mobj->vsize);
+ if (!mobj->vbuf)
+ goto alloc_err;
}
return mobj;
+
+alloc_err:
+ free(mobj->mdata);
+ free(mobj);
+ return NULL;
}
static struct fwu_image_entry *
@@ -223,6 +242,7 @@ static int fwu_parse_fill_uuids(struct fwu_mdata_object
*mobj, char *uuids[])
{
struct fwu_mdata *mdata = mobj->mdata;
struct fwu_fw_store_desc *fw_desc;
+ char *vdata;
int i, ret;
mdata->version = FWU_MDATA_VERSION;
@@ -249,23 +269,65 @@ static int fwu_parse_fill_uuids(struct fwu_mdata_object
*mobj, char *uuids[])
return ret;
}
+ if (mobj->vsize) {
+ vdata = (char *)mobj->mdata + (mobj->size - mobj->vsize);
+ memcpy(vdata, mobj->vbuf, mobj->vsize);
+ }
+
mdata->crc32 = crc32(0, (const unsigned char *)&mdata->version,
mobj->size - sizeof(uint32_t));
return 0;
}
+static int fwu_read_vendor_data(struct fwu_mdata_object *mobj,
+ const char *vendor_file)
+{
+ int ret = 0;
+ FILE *vfile = NULL;
+
+ vfile = fopen(vendor_file, "r");
+ if (!vfile) {
+ ret = -1;
+ goto out;
+ }
+
+ if (fread(mobj->vbuf, 1, mobj->vsize, vfile) != mobj->vsize)
+ ret = -1;
+
+out:
+ fclose(vfile);
+ return ret;
+}
+
static int
-fwu_make_mdata(size_t images, size_t banks, char *uuids[], char *output)
+fwu_make_mdata(size_t images, size_t banks, const char *vendor_file,
+ char *uuids[], char *output)
{
struct fwu_mdata_object *mobj;
FILE *file;
+ struct stat sbuf;
+ size_t vendor_size = 0;
int ret;
- mobj = fwu_alloc_mdata(images, banks);
+ if (vendor_file) {
+ ret = stat(vendor_file, &sbuf);
+
[GIT PULL] Please pull u-boot-dfu-20240215
Hi Tom, Here are some developments for master including: - Fix avb_verify command with SD cards - Add u-boot-dfu maintainer tree for AB/AVB - Avb: report verified boot state based on lock state - Misc avb refactors improve code quality The CI job is at https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/19653 Thanks, Mattijs The following changes since commit 37345abb97ef0dd9c50a03b2a72617612dcae585: Prepare v2024.04-rc2 (2024-02-13 18:16:57 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-dfu.git tags/u-boot-dfu-20240215 for you to fetch changes up to e2f6270f2da844d598555702d3af4f2e3fae3f9f: doc: android: avb: sync usage details (2024-02-15 10:38:34 +0100) u-boot-dfu-20240215 - Fix avb_verify command with SD cards - Add u-boot-dfu maintainer tree for AB/AVB - Avb: report verified boot state based on lock state - Misc avb refactors improve code quality Igor Opaniuk (8): MAINTAINERS: add custodian tree info for AVB/AB common: avb_verify: don't call mmc_switch_part for SD avb: move SPDX license identifiers to the first line common: avb_verify: rework error/debug prints cmd: avb: rework prints common: avb_verify: add str_avb_io_error/str_avb_slot_error cmd: avb: rework do_avb_verify_part doc: android: avb: sync usage details MAINTAINERS| 2 + cmd/avb.c | 173 + common/avb_verify.c| 89 + doc/android/avb2.rst | 16 ++- include/avb_verify.h | 7 +- test/py/tests/test_android/test_avb.py | 3 +- 6 files changed, 180 insertions(+), 110 deletions(-)
Re: [PATCH v3 1/3] mtd: spi-nor-ids: Add support for ESMT/EON EN25Q80B
On Thu, 15 Feb 2024 14:35:19 +0100
Frieder Schrempf wrote:
> From: Frieder Schrempf
>
> The datasheet can be found here:
> https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25Q80B_Ver.E.pdf
>
> Signed-off-by: Frieder Schrempf
> Reviewed-by: Fabio Estevam
> ---
> Changes in v3:
> * none
Why do you resend then? Also v4 seems unchanged? Did you adjust the people
in CC:? If you want to notify more people, please just reply to your own
patch.
Cheers,
Andre
> Changes in v2:
> * Add R-b tag from Fabio (Thanks!)
> ---
> drivers/mtd/spi/spi-nor-ids.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index 38a287487ed..4e83b8c94c9 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -80,6 +80,7 @@ const struct flash_info spi_nor_ids[] = {
> #endif
> #ifdef CONFIG_SPI_FLASH_EON /* EON */
> /* EON -- en25xxx */
> + { INFO("en25q80b", 0x1c3014, 0, 64 * 1024, 16, SECT_4K) },
> { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
> { INFO("en25q64",0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
> { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) },
Re: [PATCH v3 1/3] mtd: spi-nor-ids: Add support for ESMT/EON EN25Q80B
Hi Andre, On 15.02.24 17:50, Andre Przywara wrote: > On Thu, 15 Feb 2024 14:35:19 +0100 > Frieder Schrempf wrote: > >> From: Frieder Schrempf >> >> The datasheet can be found here: >> https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25Q80B_Ver.E.pdf >> >> Signed-off-by: Frieder Schrempf >> Reviewed-by: Fabio Estevam >> --- >> Changes in v3: >> * none > > Why do you resend then? Also v4 seems unchanged? Did you adjust the people > in CC:? If you want to notify more people, please just reply to your own > patch. This is part of a patch series and there are changes in other patches within the series. The usual workflow is to send the whole series again even if not all patches changed. At least that's what I've always been doing and so far no one complained. If there's a better way, please let me know. Thanks Frieder
Re: [PATCH v3 1/3] mtd: spi-nor-ids: Add support for ESMT/EON EN25Q80B
Hello Frieder, On 2024-02-15 17:56, Frieder Schrempf wrote: On 15.02.24 17:50, Andre Przywara wrote: On Thu, 15 Feb 2024 14:35:19 +0100 Frieder Schrempf wrote: From: Frieder Schrempf The datasheet can be found here: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25Q80B_Ver.E.pdf Signed-off-by: Frieder Schrempf Reviewed-by: Fabio Estevam --- Changes in v3: * none Why do you resend then? Also v4 seems unchanged? Did you adjust the people in CC:? If you want to notify more people, please just reply to your own patch. This is part of a patch series and there are changes in other patches within the series. The usual workflow is to send the whole series again even if not all patches changed. At least that's what I've always been doing and so far no one complained. If there's a better way, please let me know. Perhaps having a cover letter would make it easier to see what changed in each version of the series. Just my two cents.
[PATCH] boot: Only define checksum algos when the hashes are enabled
Don't define checksum algos when the underlying hashes are not enabled.
This allows disabling these hashes in SPL (or U-Boot).
Fixes: d16b38f4270 ("Add support for SHA384 and SHA512")
Fixes: 646257d1f40 ("rsa: add sha256-rsa2048 algorithm")
Signed-off-by: Sean Anderson
---
boot/image-sig.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/boot/image-sig.c b/boot/image-sig.c
index b5692d58b24..0421a61b040 100644
--- a/boot/image-sig.c
+++ b/boot/image-sig.c
@@ -17,6 +17,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define IMAGE_MAX_HASHED_NODES 100
struct checksum_algo checksum_algos[] = {
+#if CONFIG_IS_ENABLED(SHA1)
{
.name = "sha1",
.checksum_len = SHA1_SUM_LEN,
@@ -24,6 +25,8 @@ struct checksum_algo checksum_algos[] = {
.der_prefix = sha1_der_prefix,
.calculate = hash_calculate,
},
+#endif
+#if CONFIG_IS_ENABLED(SHA256)
{
.name = "sha256",
.checksum_len = SHA256_SUM_LEN,
@@ -31,7 +34,8 @@ struct checksum_algo checksum_algos[] = {
.der_prefix = sha256_der_prefix,
.calculate = hash_calculate,
},
-#ifdef CONFIG_SHA384
+#endif
+#if CONFIG_IS_ENABLED(SHA384)
{
.name = "sha384",
.checksum_len = SHA384_SUM_LEN,
@@ -40,7 +44,7 @@ struct checksum_algo checksum_algos[] = {
.calculate = hash_calculate,
},
#endif
-#ifdef CONFIG_SHA512
+#if CONFIG_IS_ENABLED(SHA512)
{
.name = "sha512",
.checksum_len = SHA512_SUM_LEN,
--
2.35.1.1320.gc452695387.dirty
[Embedded World 2024, SECO
SpA]
Re: [PATCH v3 1/3] mtd: spi-nor-ids: Add support for ESMT/EON EN25Q80B
On Thu, 15 Feb 2024 17:56:10 +0100 Frieder Schrempf wrote: Hi Frieder, > On 15.02.24 17:50, Andre Przywara wrote: > > On Thu, 15 Feb 2024 14:35:19 +0100 > > Frieder Schrempf wrote: > > > >> From: Frieder Schrempf > >> > >> The datasheet can be found here: > >> https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25Q80B_Ver.E.pdf > >> > >> Signed-off-by: Frieder Schrempf > >> Reviewed-by: Fabio Estevam > >> --- > >> Changes in v3: > >> * none > > > > Why do you resend then? Also v4 seems unchanged? Did you adjust the people > > in CC:? If you want to notify more people, please just reply to your own > > patch. > > This is part of a patch series and there are changes in other patches Ah, sorry, I missed that, because I only got 1/3. I think it's recommended to send a cover letter to the superset of all recipients, or, for such a small series, just all patches to everyone. Anyway, it's fine in this case, so just ignore me. Cheers, Andre. > within the series. The usual workflow is to send the whole series again > even if not all patches changed. At least that's what I've always been > doing and so far no one complained. If there's a better way, please let > me know. > > Thanks > Frieder
[PATCH v5] rng: Add Turris Mox rTWM RNG driver
A RNG driver for Armada 3720 boards running the Turris Mox rWTM firmware
from CZ.NIC in the secure processor.
Signed-off-by: Max Resch
---
Changes in v5:
- check return code turris_rwtm_rng_fill_entropy
- remove empty line
Changes in v4:
- wrongful/missing git rebase
Changes in v3:
- More meaningful variable names in accordance with review
Changes in v2:
- Removed ring buffer implementation
drivers/rng/Kconfig | 8 +++
drivers/rng/Makefile | 1 +
drivers/rng/turris_rwtm_rng.c | 123 ++
3 files changed, 132 insertions(+)
create mode 100644 drivers/rng/turris_rwtm_rng.c
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index a89c899568..cd72852a47 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -105,4 +105,12 @@ config RNG_JH7110
help
Enable True Random Number Generator in StarFive JH7110 SoCs.
+config RNG_TURRIS_RWTM
+ bool "Turris Mox TRNG in Secure Processor"
+ depends on DM_RNG && ARMADA_3700
+ help
+ Use TRNG in Turris Mox Secure Processor Firmware. Can be used
+ on other Armada-3700 devices (like EspressoBin) if Secure
+ Firmware from CZ.NIC is used.
+
endif
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 7e64c4cdfc..ecae1a3da3 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o
obj-$(CONFIG_RNG_ARM_RNDR) += arm_rndr.o
obj-$(CONFIG_TPM_RNG) += tpm_rng.o
obj-$(CONFIG_RNG_JH7110) += jh7110_rng.o
+obj-$(CONFIG_RNG_TURRIS_RWTM) += turris_rwtm_rng.o
diff --git a/drivers/rng/turris_rwtm_rng.c b/drivers/rng/turris_rwtm_rng.c
new file mode 100644
index 00..ca808c4579
--- /dev/null
+++ b/drivers/rng/turris_rwtm_rng.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (c) 2024, Max Resch
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* size of entropy buffer */
+#define RNG_BUFFER_SIZE128U
+
+struct turris_rwtm_rng_priv {
+ phys_addr_t buffer;
+};
+
+static int turris_rwtm_rng_fill_entropy(phys_addr_t entropy, size_t size)
+{
+ u32 args[3] = { 1, (u32)entropy, size };
+ int ret;
+
+ /* flush data cache */
+ flush_dcache_range(entropy, entropy + size);
+
+ /*
+* get entropy
+* args[0] = 1 copies BYTES array in args[1] of length args[2]
+*/
+ ret = mbox_do_cmd(MBOX_CMD_GET_RANDOM, args, 3, NULL, 0);
+ if (ret < 0)
+ return ret;
+
+ /* invalidate data cache */
+ invalidate_dcache_range(entropy, entropy + size);
+
+ return 0;
+}
+
+static int turris_rwtm_rng_random_read(struct udevice *dev, void *data, size_t
count)
+{
+ struct turris_rwtm_rng_priv *priv = dev_get_priv(dev);
+ phys_addr_t phys;
+ size_t size;
+ int ret;
+
+ phys = priv->buffer;
+
+ while (count) {
+ size = min_t(size_t, RNG_BUFFER_SIZE, count);
+
+ ret = turris_rwtm_rng_fill_entropy(phys, size);
+ if (ret < 0)
+ return ret;
+
+ memcpy(data, (void *)phys, size);
+ count -= size;
+ data = (u8 *)data + size;
+ }
+
+ return 0;
+}
+
+static int turris_rwtm_rng_probe(struct udevice *dev)
+{
+ struct turris_rwtm_rng_priv *priv = dev_get_priv(dev);
+ u32 args[] = { 0 };
+ int ret;
+
+ /*
+* check if the random command is supported
+* args[0] = 0 would copy 16 DWORDS entropy to out but we ignore them
+*/
+ ret = mbox_do_cmd(MBOX_CMD_GET_RANDOM, args, ARRAY_SIZE(args), NULL, 0);
+ if (ret < 0)
+ return ret;
+
+ /* entropy buffer */
+ priv->buffer = 0;
+
+ /* buffer address need to be aligned */
+ dma_alloc_coherent(RNG_BUFFER_SIZE, (unsigned long *)&priv->buffer);
+ if (!priv->buffer)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static int turris_rwtm_rng_remove(struct udevice *dev)
+{
+ struct turris_rwtm_rng_priv *priv = dev_get_priv(dev);
+ phys_addr_t phys = priv->buffer;
+
+ dma_free_coherent((void *)phys);
+
+ return 0;
+}
+
+static const struct dm_rng_ops turris_rwtm_rng_ops = {
+ .read = turris_rwtm_rng_random_read,
+};
+
+/*
+ * only Turris MOX firmware has the RNG but allow all probable devices to be
+ * probed the default firmware will just reject the probe
+ */
+static const struct udevice_id turris_rwtm_rng_match[] = {
+ { .compatible = "cznic,turris-mox-rwtm" },
+ { .compatible = "marvell,armada-3700-rwtm-firmware" },
+ {},
+};
+
+U_BOOT_DRIVER(turris_rwtm_rng) = {
+ .name = "turris-rwtm-rng",
+ .id = UCLASS_RNG,
+ .of_match = turris_rwtm_rng_match,
+ .ops= &turris_rwtm_rng_ops,
+ .probe = turris_rwtm_rng_probe,
+ .remove = turris_rwtm_rng_remove,
+
Re: [GIT PULL] Please pull u-boot-dfu-20240215
On Thu, Feb 15, 2024 at 03:40:33PM +0100, Mattijs Korpershoek wrote: > Hi Tom, > > Here are some developments for master including: > > - Fix avb_verify command with SD cards > - Add u-boot-dfu maintainer tree for AB/AVB > - Avb: report verified boot state based on lock state > - Misc avb refactors improve code quality > > The CI job is at > https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/19653 > > Thanks, > Mattijs > > The following changes since commit 37345abb97ef0dd9c50a03b2a72617612dcae585: > > Prepare v2024.04-rc2 (2024-02-13 18:16:57 -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-dfu.git > tags/u-boot-dfu-20240215 > > for you to fetch changes up to e2f6270f2da844d598555702d3af4f2e3fae3f9f: > > doc: android: avb: sync usage details (2024-02-15 10:38:34 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH] arm64: zynqmp: Support semhosting boot method
Currently, when we boot from JTAG we try to boot U-Boot from RAM.
However, this is a bit tricky to time, since the debugger has to wait
for SPL to initialize RAM before it can load U-Boot. This can result in
long waits, since occasionally initializing RAM (and other things in
psu_init) takes a long time to complete and the debugger must wait for
this worst case.
Support semihosting if it is enabled, as it lets U-Boot tell the
debugger when we are ready for the image. This means we don't have to
wait any more than necessary. We don't change the default config to
ensure we don't break compatibility with existing debuggers that don't
expect us to hit semihosting breakpoints.
Signed-off-by: Sean Anderson
---
arch/arm/mach-zynqmp/spl.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
index a0f35f36faa..5af735aa5ce 100644
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
@@ -66,6 +67,11 @@ void spl_board_init(void)
}
#endif
+static u32 jtag_boot_device(void)
+{
+ return semihosting_enabled() ? BOOT_DEVICE_SMH : BOOT_DEVICE_RAM;
+}
+
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = spl_boot_device();
@@ -75,7 +81,7 @@ void board_boot_order(u32 *spl_boot_list)
if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
spl_boot_list[1] = BOOT_DEVICE_MMC1;
- spl_boot_list[2] = BOOT_DEVICE_RAM;
+ spl_boot_list[2] = jtag_boot_device();
}
u32 spl_boot_device(void)
@@ -97,7 +103,7 @@ u32 spl_boot_device(void)
switch (bootmode) {
case JTAG_MODE:
- return BOOT_DEVICE_RAM;
+ return jtag_boot_device();
#ifdef CONFIG_SPL_MMC
case SD_MODE1:
case SD1_LSHFT_MODE: /* not working on silicon v1 */
--
2.35.1.1320.gc452695387.dirty
[Embedded World 2024, SECO
SpA]
Re: [PATCH] arm64: zynqmp: Support semhosting boot method
On 2/15/24 18:19, Sean Anderson wrote:
Currently, when we boot from JTAG we try to boot U-Boot from RAM.
However, this is a bit tricky to time, since the debugger has to wait
for SPL to initialize RAM before it can load U-Boot. This can result in
long waits, since occasionally initializing RAM (and other things in
psu_init) takes a long time to complete and the debugger must wait for
this worst case.
Support semihosting if it is enabled, as it lets U-Boot tell the
debugger when we are ready for the image. This means we don't have to
wait any more than necessary. We don't change the default config to
ensure we don't break compatibility with existing debuggers that don't
expect us to hit semihosting breakpoints.
Signed-off-by: Sean Anderson
---
arch/arm/mach-zynqmp/spl.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
index a0f35f36faa..5af735aa5ce 100644
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
@@ -66,6 +67,11 @@ void spl_board_init(void)
}
#endif
+static u32 jtag_boot_device(void)
+{
+ return semihosting_enabled() ? BOOT_DEVICE_SMH : BOOT_DEVICE_RAM;
+}
+
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = spl_boot_device();
@@ -75,7 +81,7 @@ void board_boot_order(u32 *spl_boot_list)
if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
spl_boot_list[1] = BOOT_DEVICE_MMC1;
- spl_boot_list[2] = BOOT_DEVICE_RAM;
+ spl_boot_list[2] = jtag_boot_device();
}
u32 spl_boot_device(void)
@@ -97,7 +103,7 @@ u32 spl_boot_device(void)
switch (bootmode) {
case JTAG_MODE:
- return BOOT_DEVICE_RAM;
+ return jtag_boot_device();
#ifdef CONFIG_SPL_MMC
case SD_MODE1:
case SD1_LSHFT_MODE: /* not working on silicon v1 */
Good timing. Can you please tell me how to test this? What's the setup?
Which debugger are you using?
Also curious if semihosting serial can be used in your setup.
Thanks,
Michal
Re: [PATCH] arm64: zynqmp: Support semhosting boot method
On 2/15/24 14:08, Michal Simek wrote:
>
>
> On 2/15/24 18:19, Sean Anderson wrote:
>> Currently, when we boot from JTAG we try to boot U-Boot from RAM.
>> However, this is a bit tricky to time, since the debugger has to wait
>> for SPL to initialize RAM before it can load U-Boot. This can result in
>> long waits, since occasionally initializing RAM (and other things in
>> psu_init) takes a long time to complete and the debugger must wait for
>> this worst case.
>>
>> Support semihosting if it is enabled, as it lets U-Boot tell the
>> debugger when we are ready for the image. This means we don't have to
>> wait any more than necessary. We don't change the default config to
>> ensure we don't break compatibility with existing debuggers that don't
>> expect us to hit semihosting breakpoints.
>>
>> Signed-off-by: Sean Anderson
>> ---
>>
>> arch/arm/mach-zynqmp/spl.c | 10 --
>> 1 file changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
>> index a0f35f36faa..5af735aa5ce 100644
>> --- a/arch/arm/mach-zynqmp/spl.c
>> +++ b/arch/arm/mach-zynqmp/spl.c
>> @@ -9,6 +9,7 @@
>> #include
>> #include
>> #include
>> +#include
>> #include
>> #include
>>
>> @@ -66,6 +67,11 @@ void spl_board_init(void)
>> }
>> #endif
>>
>> +static u32 jtag_boot_device(void)
>> +{
>> + return semihosting_enabled() ? BOOT_DEVICE_SMH : BOOT_DEVICE_RAM;
>> +}
>> +
>> void board_boot_order(u32 *spl_boot_list)
>> {
>> spl_boot_list[0] = spl_boot_device();
>> @@ -75,7 +81,7 @@ void board_boot_order(u32 *spl_boot_list)
>> if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
>> spl_boot_list[1] = BOOT_DEVICE_MMC1;
>>
>> - spl_boot_list[2] = BOOT_DEVICE_RAM;
>> + spl_boot_list[2] = jtag_boot_device();
>> }
>>
>> u32 spl_boot_device(void)
>> @@ -97,7 +103,7 @@ u32 spl_boot_device(void)
>>
>> switch (bootmode) {
>> case JTAG_MODE:
>> - return BOOT_DEVICE_RAM;
>> + return jtag_boot_device();
>> #ifdef CONFIG_SPL_MMC
>> case SD_MODE1:
>> case SD1_LSHFT_MODE: /* not working on silicon v1 */
>
> Good timing. Can you please tell me how to test this? What's the setup?
> Which debugger are you using?
I am using OpenOCD with the patches at
https://review.openocd.org/c/openocd/+/8133
My boot flow is
SPL -> ATF -> U-Boot (no FSBL)
This allows me to use a FIT which saves some time since I can
compress the bitstream. Right now I am using
xilinx_zynqmp_virt_defconfig with the following modifications:
CONFIG_SYS_LOAD_ADDR=0x3000
# CONFIG_SPL_OS_BOOT is not set
CONFIG_SPL_SEMIHOSTING=y
I also have CONFIG_XILINX_PS_INIT_FILE,
CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE, and CONFIG_PMUFW_INIT_FILE defined as
appropriate. I use the following FIT for U-Boot:
/dts-v1/;
/ {
description = "U-Boot and ATF";
#address-cells = <1>;
images {
atf {
description = "Arm Trusted Firmware";
data = /incbin/("arm-trusted-firmware.bin");
type = "firmware";
os = "arm-trusted-firmware";
arch = "arm64";
compression = "none";
load = <0xfffea000>;
entry = <0xfffea000>;
};
fpga {
description = "PL Bitstream";
data = /incbin/("system.bit.gz");
type = "fpga";
arch = "arm64";
compression = "gzip";
load = <0x7c00>;
compatible = "u-boot,fpga-legacy";
};
u-boot {
description = "U-Boot";
data = /incbin/("u-boot-nodtb.bin");
type = "firmware";
os = "u-boot";
arch = "arm64";
compression = "none";
load = <0x0008>;
entry = <0x0008>;
};
fdt {
description = "U-Boot FDT";
data = /incbin/("u-boot.dtb");
type = "flat_dt";
arch = "arm64";
compression = "none";
hash-1 {
algo = "crc32";
};
};
};
configurations {
default = "conf";
conf {
description = "Boot ATF and U-Boot";
firmware = "atf";
loadables = "u-boot", "fpga";
fdt = "fdt";
};
};
};
Boot output looks like
U-Boot SPL 2024.01 (Feb 15 2024 - 17:03:10 +)
Loading new PMUFW cfg obj (1848 bytes)
PMUFW: v1.1
Silicon version:3
EL Level: EL3
Secure Boot:not authenticated, not encrypted
Multiboot: 0
Trying to boot from MMC1
FPGA image loaded from FIT
NOTICE: BL31: v2.6(release):xlnx_rebase_v2.6_2022.2
NOTICE: BL31: Built : 03:55:03, Sep 9 2022
U-Boot 2024.01 (Feb 15 2024 - 17:03:10 +)
CPU: ZynqMP
Silicon: v3
Chip: zu4
Board: Xilinx ZynqMP
DRAM: 2 GiB (effective 4 GiB)
PMUFW: v1.1
EL Level: EL2
Secure Boot:not authenticated, not encrypted
Core: 67 devices, 29
Re: [PATCH] arm64: zynqmp: Support semhosting boot method
On 2/15/24 14:31, Sean Anderson wrote:
> On 2/15/24 14:08, Michal Simek wrote:
>>
>>
>> On 2/15/24 18:19, Sean Anderson wrote:
>>> Currently, when we boot from JTAG we try to boot U-Boot from RAM.
>>> However, this is a bit tricky to time, since the debugger has to wait
>>> for SPL to initialize RAM before it can load U-Boot. This can result in
>>> long waits, since occasionally initializing RAM (and other things in
>>> psu_init) takes a long time to complete and the debugger must wait for
>>> this worst case.
>>>
>>> Support semihosting if it is enabled, as it lets U-Boot tell the
>>> debugger when we are ready for the image. This means we don't have to
>>> wait any more than necessary. We don't change the default config to
>>> ensure we don't break compatibility with existing debuggers that don't
>>> expect us to hit semihosting breakpoints.
>>>
>>> Signed-off-by: Sean Anderson
>>> ---
>>>
>>> arch/arm/mach-zynqmp/spl.c | 10 --
>>> 1 file changed, 8 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
>>> index a0f35f36faa..5af735aa5ce 100644
>>> --- a/arch/arm/mach-zynqmp/spl.c
>>> +++ b/arch/arm/mach-zynqmp/spl.c
>>> @@ -9,6 +9,7 @@
>>> #include
>>> #include
>>> #include
>>> +#include
>>> #include
>>> #include
>>>
>>> @@ -66,6 +67,11 @@ void spl_board_init(void)
>>> }
>>> #endif
>>>
>>> +static u32 jtag_boot_device(void)
>>> +{
>>> + return semihosting_enabled() ? BOOT_DEVICE_SMH : BOOT_DEVICE_RAM;
>>> +}
>>> +
>>> void board_boot_order(u32 *spl_boot_list)
>>> {
>>> spl_boot_list[0] = spl_boot_device();
>>> @@ -75,7 +81,7 @@ void board_boot_order(u32 *spl_boot_list)
>>> if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
>>> spl_boot_list[1] = BOOT_DEVICE_MMC1;
>>>
>>> - spl_boot_list[2] = BOOT_DEVICE_RAM;
>>> + spl_boot_list[2] = jtag_boot_device();
>>> }
>>>
>>> u32 spl_boot_device(void)
>>> @@ -97,7 +103,7 @@ u32 spl_boot_device(void)
>>>
>>> switch (bootmode) {
>>> case JTAG_MODE:
>>> - return BOOT_DEVICE_RAM;
>>> + return jtag_boot_device();
>>> #ifdef CONFIG_SPL_MMC
>>> case SD_MODE1:
>>> case SD1_LSHFT_MODE: /* not working on silicon v1 */
>>
>> Good timing. Can you please tell me how to test this? What's the setup?
>> Which debugger are you using?
>
> I am using OpenOCD with the patches at
> https://cas5-0-urlprotect.trendmicro.com:443/wis/clicktime/v1/query?url=https%3a%2f%2freview.openocd.org%2fc%2fopenocd%2f%2b%2f8133&umid=819f1021-60b3-42c6-ac85-f327c489da7c&auth=d807158c60b7d2502abde8a2fc01f40662980862-7485d72bf875c6ddb963725debf981fe8dd33731
>
> My boot flow is
>
> SPL -> ATF -> U-Boot (no FSBL)
>
> This allows me to use a FIT which saves some time since I can
> compress the bitstream. Right now I am using
> xilinx_zynqmp_virt_defconfig with the following modifications:
>
> CONFIG_SYS_LOAD_ADDR=0x3000
> # CONFIG_SPL_OS_BOOT is not set
> CONFIG_SPL_SEMIHOSTING=y
>
> I also have CONFIG_XILINX_PS_INIT_FILE,
> CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE, and CONFIG_PMUFW_INIT_FILE defined as
> appropriate. I use the following FIT for U-Boot:
>
> /dts-v1/;
>
> / {
> description = "U-Boot and ATF";
> #address-cells = <1>;
>
> images {
> atf {
> description = "Arm Trusted Firmware";
> data = /incbin/("arm-trusted-firmware.bin");
> type = "firmware";
> os = "arm-trusted-firmware";
> arch = "arm64";
> compression = "none";
> load = <0xfffea000>;
> entry = <0xfffea000>;
> };
>
> fpga {
> description = "PL Bitstream";
> data = /incbin/("system.bit.gz");
> type = "fpga";
> arch = "arm64";
> compression = "gzip";
> load = <0x7c00>;
> compatible = "u-boot,fpga-legacy";
> };
>
> u-boot {
> description = "U-Boot";
> data = /incbin/("u-boot-nodtb.bin");
> type = "firmware";
> os = "u-boot";
> arch = "arm64";
> compression = "none";
> load = <0x0008>;
> entry = <0x0008>;
> };
>
> fdt {
> description = "U-Boot FDT";
> data = /incbin/("u-boot.dtb");
> type = "flat_dt";
> arch = "arm64";
> compression = "none";
> hash-1 {
> algo = "crc32";
> };
> };
> };
>
> configurations {
> default = "conf";
> conf {
> description = "Boot ATF and U-Boot";
> firmware = "atf";
> loadables = "u-boot", "fpga";
> fdt = "fdt";
> };
> };
> };
>
> Boot output looks like
>
> U-Boot SPL 2024.01 (Feb 15 2024 - 17:03:10 +)
> Loading new PMUFW cfg obj (1848 bytes)
> PMUFW: v1.1
> Sil
Re: [PATCH 6/6] arm: mach-k3: Move DRAM address of ATF for AM62/AM62a
On 2/15/24 2:06 AM, Francesco Dolcini wrote: Hello Andrew, thanks for this series. On Wed, Feb 14, 2024 at 10:30:09AM -0600, Andrew Davis wrote: The current address of TF-A in DRAM is just below the 512MB address line. This means if the DRAM in a system is 512MB then TF-A is right at the end of memory which is often reused, for instance U-Boot relocates itself here. If a system has less than 512MB then that system wouldn't work at all as TF-A would fail to load. Do you expect issue with system with exactly 512MB of RAM? We have such a board available and this is something that was not on our radar. The issues with exactly 512MB are much less than the systems with less. Mostly small software issues like the one you work around below with U-Boot relocation. The way we handle this is with `verdin-am62.c:board_get_usable_ram_top()` The point of this patch is to avoid the need for workarounds like that in the first place. There is also some other reserved memory just before the 512MB limit, not just the TF-A. This series prepares for also moving OP-TEE at some point (which will be a bit more involved as it still needs to be made position independent). The other reserved memory is mostly for remoteproc firmware which should be made dynamic instead of hard-coding memory carve-outs for their use. Andrew Francesco
Re: [PATCH v8 16/16] doc: board: ti: k3: Add J784S4 EVM and AM69 SK documentation
On Fri, Jan 19, 2024 at 11:20:43PM +0530, Apurva Nandan wrote: > TI K3 J784S4 and AM69 are new additions to the K3 SoC family. > Add documentation about the J784S4 EVM and AM69 SK. > > Signed-off-by: Dasnavis Sabiya > Signed-off-by: Apurva Nandan > --- > board/ti/j784s4/MAINTAINERS | 1 + > doc/board/ti/j784s4_evm.rst | 299 > doc/board/ti/k3.rst | 1 + > 3 files changed, 301 insertions(+) > create mode 100644 doc/board/ti/j784s4_evm.rst > > + > +Switch Setting for Boot Mode > + > + > +Boot Mode pins provide means to select the boot mode and options before the > +device is powered up. After every POR, they are the main source to populate > +the Boot Parameter Tables. > + > +Boot Mode Pins for J784S4-EVM > +^ > + > +The following tables show some common boot modes used on J784S4 EVM platform. > +More details can be found in the Technical Reference Manual: > +http://www.ti.com/lit/zip/spruj52 under the `Boot Mode Pins` section. > + > +.. list-table:: J784S4 EVM Boot Modes > + :widths: 16 16 16 > + :header-rows: 1 > + > + * - Switch Label > + - SW9: 12345678 > + - SW8: 12345678 According to spruj62 I think SW9 and SW8 are supposed to be SW7 and SW11 respectively? > + > + * - SD > + - > + - 1010 > + > + * - EMMC > + - 0100 > + - 1000 > + > + * - OSPI > + - 0100 > + - 0110 > + > + * - UART > + - 0111 > + - > + > +For SW8 and SW9, the switch state in the "ON" position = 1. Referencing more from spruj62... SW8 is a push button for a user defined interrupt for wake up (I think), and SW9 is the main domain warm reset push button. I'm not sure either of those are what you're trying to highlight here. Love the TI documentation by the way, it is very nice. Thanks, Andrew
[PATCH v4 04/39] dt-bindings: drop msm_sdhci binding
The upstream DT is supported here, so drop the U-Boot specific binding
docs.
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
doc/device-tree-bindings/mmc/msm_sdhci.txt | 25 -
1 file changed, 25 deletions(-)
diff --git a/doc/device-tree-bindings/mmc/msm_sdhci.txt
b/doc/device-tree-bindings/mmc/msm_sdhci.txt
deleted file mode 100644
index 08a290c66931..
--- a/doc/device-tree-bindings/mmc/msm_sdhci.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Qualcomm Snapdragon SDHCI controller
-
-Required properties:
-- compatible : "qcom,sdhci-msm-v4"
-- reg: Base address and length of registers:
- - Host controller registers (SDHCI)
- - SD Core registers
-- clock: interface clock (must accept SD bus clock as a frequency)
-
-Optional properties:
-- index: If there is more than one controller - controller index (required
- by generic SDHCI code).
-- bus_width: Width of SD/eMMC bus (default 4)
-- clock-frequency: Frequency of SD/eMMC bus (default 400 kHz)
-
-Example:
-
-sdhci@07864000 {
- compatible = "qcom,sdhci-msm-v4";
- reg = <0x7864900 0x11c 0x7864000 0x800>;
- index = <0x1>;
- bus-width = <0x4>;
- clock = <&clkc 1>;
- clock-frequency = <2>;
-};
--
2.43.1
[PATCH v4 05/39] clk/qcom: use upstream compatible properties
Adjust the apq8016 and apq8096 drivers to use the upstream compatible
properties, and adjust the associated dts files in U-Boot.
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
arch/arm/dts/dragonboard410c.dts | 2 +-
drivers/clk/qcom/clock-apq8016.c | 2 +-
drivers/clk/qcom/clock-apq8096.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index 6a4e3ccf17b1..02c824d0226c 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -75,7 +75,7 @@
};
};
clkc: qcom,gcc@180 {
- compatible = "qcom,gcc-apq8016";
+ compatible = "qcom,gcc-msm8916";
reg = <0x180 0x8>;
#address-cells = <0x1>;
#size-cells = <0x0>;
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index c0ce570edc79..0af7191cff52 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -145,7 +145,7 @@ static struct msm_clk_data apq8016_clk_data = {
static const struct udevice_id gcc_apq8016_of_match[] = {
{
- .compatible = "qcom,gcc-apq8016",
+ .compatible = "qcom,gcc-msm8916",
.data = (ulong)&apq8016_clk_data,
},
{ }
diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
index cf1a347309a5..1e6fdb5cd42d 100644
--- a/drivers/clk/qcom/clock-apq8096.c
+++ b/drivers/clk/qcom/clock-apq8096.c
@@ -123,7 +123,7 @@ static struct msm_clk_data apq8096_clk_data = {
static const struct udevice_id gcc_apq8096_of_match[] = {
{
- .compatible = "qcom,gcc-apq8096",
+ .compatible = "qcom,gcc-msm8996",
.data = (ulong)&apq8096_clk_data,
},
{ }
--
2.43.1
[PATCH v4 00/39] Qualcomm generic board support
Historically, Qualcomm boards in U-Boot have all had their own
board/qualcomm/xyz directory, their own CONFIG_TARGET_XYZ option, their
own hardcoded sysmap-xyz.c file, and their own U-Boot specific
devicetree with little/no compatibility with upstream DT.
This series makes a few final prepatory changes, and then replaces
almost all of the board specific code with generic alternatives. The end
result is that all Qualcomm boards both current and future (with the
exception of the db410c and db820c) can be supported by a single U-Boot
binary by just providing the correct DT. New boards can be added without
introducing any addition mach/ or board/ code or config options.
Due to the nature of this change, the patch ("mach-snapdragon:
generalise board support") has become pretty big, I tried a few
different ways to represent this in git history, but the other methods
(e.g. adding a stub "generic" target and removing it again) were more
confusing and made for much messier git history. The current patch is
mostly atomic, but requires regenerating the config.
The QCS404 EVB board had some code to enable the USB VBUS regulator,
this is dropped in favour of a adding a new vbus-supply property to the
dwc3-generic driver. This will also be used by the dragonboard845c in a
future patch. This handles the common case of a board requiring some
regulator be enabled for USB host mode.
A more detailed description of the changes is below.
== Memory map ==
The memory map was historically hardcoded into U-Boot, this meant that
U-Boot had to be built for a specific variant of a device. This is
changed to instead read the memory map from the DT /memory node.
Additionally, most boards mapped addresss 0x0 as valid, as a result if a
null pointer access happens then it will cause a bus stall (and board
hang). This is fixed so that null pointer accesses will now correctly
throw an exception.
== DT loading ==
Previously, boards used the FDT blob embedded into U-Boot (via
OF_SEPARATE). However, most Qualcomm boards run U-Boot as a secondary
bootloader, so we can instead rely on the first-stage bootloader to
populate some useful FDT properties for us (notably the /memory node and
KASLR seed) and fetch the DTB that it provides. Combined with the memory
map changes above, this let's us entirely avoid configuring the memory
map explicitly.
== defconfig ==
Most of the board defconfigs and config headers were quite similar, to
simplify maintenance going forward, all the fully generic boards (sdm845
and qcs404-evb so far) are adapted to use the new qcom_defconfig. Going
forward, all new Qualcomm boards should be supported by this defconfig.
A notable exception is for specific usecases (like U-Boot as the primary
bootloader).
== The older dragonboards ==
The db410c and db820c both have some custom board init code, as a result
they aren't yet binary compatible. mach-snapdragon is adjusted so
that all the necessary config options (e.g. CONFIG_SYS_BOARD) can be set
from their defconfigs, this makes it possible to enable support for new
boards without introducing additional config options.
The db410c can run U-Boot either chainloaded like the other boards, or
as a first-stage bootloader replacing aboot. However it was hardcoded to
only build for the latter option. This series introduces a new
"chainloaded" defconfig to enable easier testing via fastboot.
== dynamic environment variables ==
This series also introduces runtime-allocated load addresses via the lmb
allocator. This allows for booting on boards with vastly different
memory layouts without any pre-calculation or macro magic in the config
header. This feature is based on similar code in mach-apple.
The soc, board, and fdtfile environment variables are also generated
automatically. Many Qualcomm boards follow a similar scheme for DTB
naming such that the name can often be derived from the root compatible
properties. This is intended to cover the most common cases and be a
simple solution for booting generic distro images without having to
explicitly choose the right DTB. The U-Boot DTS can be tweaked if
necessary to produce the correct name, the variable can be overwritten,
or a bootloader like GRUB can load the devicetree instead.
== Upstream DT ==
All Qualcomm boards have had their devicetree files replaced with the
upstream versions. Previous patch series made the necessary driver
adjustments to fully support the upstream DT format. All future
Qualcomm boards should use upstream DTS by default.
Once Sumit's work to import dt-rebasing has been merged, we will drop
the imported DT and bindings again.
---
I have tested this series on the Dragonboard410c, Dragonboard820c, and
Dragonboard845c. I unfortunately don't have access to a QCS404 EVB board
to test.
This series is based on the qcom-next branch [1] and depends on my PMIC
fixes series [2], an integration branch for testing can be found at [3].
The non-qualcomm-specific changes (patches 1 and 2) don't have any
depende
[PATCH v4 01/39] arm: init: export prev_bl_fdt_addr
When booting U-Boot on board with a locked down first-stage bootloader,
we emulate the Linux boot header. By passing the U-Boot FDT through this
first-stage bootloader and retrieving it afterwards we can pre-populate
the memory nodes and other info like the KASLR address.
Add a function to export the FDT addr so that boards can use it over the
built-in FDT.
Don't check is_addr_accessible() here because we might not yet have a
valid mem_map if it's going to be populated from the FDT, let the board
do their own validation instead.
Reviewed-by: Tom Rini
Signed-off-by: Caleb Connolly
---
arch/arm/lib/save_prev_bl_data.c | 5 +
include/init.h | 11 +++
2 files changed, 16 insertions(+)
diff --git a/arch/arm/lib/save_prev_bl_data.c b/arch/arm/lib/save_prev_bl_data.c
index f7b23faf0d66..b286bac9bf00 100644
--- a/arch/arm/lib/save_prev_bl_data.c
+++ b/arch/arm/lib/save_prev_bl_data.c
@@ -45,6 +45,11 @@ bool is_addr_accessible(phys_addr_t addr)
return false;
}
+phys_addr_t get_prev_bl_fdt_addr(void)
+{
+ return reg0;
+}
+
int save_prev_bl_data(void)
{
struct fdt_header *fdt_blob;
diff --git a/include/init.h b/include/init.h
index 9a1951d10a01..630d86729c4e 100644
--- a/include/init.h
+++ b/include/init.h
@@ -168,6 +168,17 @@ defined(CONFIG_SAVE_PREV_BL_FDT_ADDR)
* Return: 0 if ok; -ENODATA on error
*/
int save_prev_bl_data(void);
+
+/**
+ * get_prev_bl_fdt_addr - When u-boot is chainloaded, get the address
+ * of the FDT passed by the previous bootloader.
+ *
+ * Return: the address of the FDT passed by the previous bootloader
+ * or 0 if not found.
+ */
+phys_addr_t get_prev_bl_fdt_addr(void);
+#else
+#define get_prev_bl_fdt_addr() 0LLU
#endif
/**
--
2.43.1
[PATCH v4 07/39] serial: msm: add debug UART
Introduce support for early debugging. This relies on the previous stage
bootloader to initialise the UART clocks, when running with U-Boot as
the primary bootloader this feature doesn't work. It will require a way
to configure the clocks before the driver model is available.
Signed-off-by: Caleb Connolly
---
drivers/serial/Kconfig | 8
drivers/serial/serial_msm.c | 37 +
2 files changed, 45 insertions(+)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 26460c4e0cab..fbd351a47859 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -319,6 +319,14 @@ config DEBUG_UART_S5P
will need to provide parameters to make this work. The driver will
be available until the real driver-model serial is running.
+config DEBUG_UART_MSM
+ bool "Qualcomm QUP UART debug"
+ depends on ARCH_SNAPDRAGON
+ help
+ Select this to enable a debug UART using the serial_msm driver. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver-model serial is running.
+
config DEBUG_UART_MSM_GENI
bool "Qualcomm snapdragon"
depends on ARCH_SNAPDRAGON
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index f4d96313b931..44b93bd7ff21 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -252,3 +252,40 @@ U_BOOT_DRIVER(serial_msm) = {
.probe = msm_serial_probe,
.ops= &msm_serial_ops,
};
+
+#ifdef CONFIG_DEBUG_UART_MSM
+
+static struct msm_serial_data init_serial_data = {
+ .base = CONFIG_VAL(DEBUG_UART_BASE),
+ .clk_rate = 7372800,
+};
+
+#include
+
+/* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916
*/
+//int apq8016_clk_init_uart(phys_addr_t gcc_base);
+
+static inline void _debug_uart_init(void)
+{
+ /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on
MSM8916 */
+ //apq8016_clk_init_uart(0x180);
+ uart_dm_init(&init_serial_data);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+ struct msm_serial_data *priv = &init_serial_data;
+
+ while (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
+ !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
+ ;
+
+ writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
+
+ writel(1, priv->base + UARTDM_NCF_TX);
+ writel(ch, priv->base + UARTDM_TF);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
--
2.43.1
[PATCH v4 03/39] mmc: msm_sdhci: use modern clock handling
Use the clk_* helper functions and the correct property name for clocks.
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
drivers/mmc/msm_sdhci.c | 69 +
1 file changed, 47 insertions(+), 22 deletions(-)
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index fe1e754bfde0..b63538fce20c 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -44,6 +44,7 @@ struct msm_sdhc_plat {
struct msm_sdhc {
struct sdhci_host host;
void *base;
+ struct clk_bulk clks;
};
struct msm_sdhc_variant_info {
@@ -54,35 +55,57 @@ DECLARE_GLOBAL_DATA_PTR;
static int msm_sdc_clk_init(struct udevice *dev)
{
- int node = dev_of_offset(dev);
- uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency",
- 40);
- uint clkd[2]; /* clk_id and clk_no */
- int clk_offset;
- struct udevice *clk_dev;
- struct clk clk;
- int ret;
+ struct msm_sdhc *prv = dev_get_priv(dev);
+ ofnode node = dev_ofnode(dev);
+ uint clk_rate;
+ int ret, i = 0, n_clks;
+ const char *clk_name;
- ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2);
+ ret = ofnode_read_u32(node, "clock-frequency", &clk_rate);
if (ret)
- return ret;
+ clk_rate = 40;
- clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
- if (clk_offset < 0)
- return clk_offset;
-
- ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
- if (ret)
+ ret = clk_get_bulk(dev, &prv->clks);
+ if (ret) {
+ log_warning("Couldn't get mmc clocks: %d\n", ret);
return ret;
+ }
- clk.id = clkd[1];
- ret = clk_request(clk_dev, &clk);
- if (ret < 0)
+ ret = clk_enable_bulk(&prv->clks);
+ if (ret) {
+ log_warning("Couldn't enable mmc clocks: %d\n", ret);
return ret;
+ }
- ret = clk_set_rate(&clk, clk_rate);
- if (ret < 0)
- return ret;
+ /* If clock-names is unspecified, then the first clock is the core
clock */
+ if (!ofnode_get_property(node, "clock-names", &n_clks)) {
+ if (!clk_set_rate(&prv->clks.clks[0], clk_rate)) {
+ log_warning("Couldn't set core clock rate: %d\n", ret);
+ return -EINVAL;
+ }
+ }
+
+ /* Find the index of the "core" clock */
+ while (i < n_clks) {
+ ofnode_read_string_index(node, "clock-names", i, &clk_name);
+ if (!strcmp(clk_name, "core"))
+ break;
+ i++;
+ }
+
+ if (i >= prv->clks.count) {
+ log_warning("Couldn't find core clock (index %d but only have
%d clocks)\n", i,
+ prv->clks.count);
+ return -EINVAL;
+ }
+
+ /* The clock is already enabled by the clk_bulk above */
+ ret = clk_set_rate(&prv->clks.clks[i], clk_rate);
+ /* If we get a rate of 0 then something has probably gone wrong. */
+ if (ret == 0) {
+ log_warning("Couldn't set core clock rate to %u! Driver
returned rate of 0\n", clk_rate);
+ return -EINVAL;
+ }
return 0;
}
@@ -187,6 +210,8 @@ static int msm_sdc_remove(struct udevice *dev)
if (!var_info->mci_removed)
writel(0, priv->base + SDCC_MCI_HC_MODE);
+ clk_release_bulk(&priv->clks);
+
return 0;
}
--
2.43.1
[PATCH v4 09/39] gpio: qcom_pmic: 1-based GPIOs
Qualcomm PMICs number their GPIOs starting from 1, implement a custom
.xlate method to handle this.
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
drivers/gpio/qcom_pmic_gpio.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 6167c8411678..2a4fef8d28cb 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -209,12 +209,34 @@ static int qcom_gpio_set_value(struct udevice *dev,
unsigned offset,
REG_CTL_OUTPUT_MASK, !!value);
}
+static int qcom_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+ struct ofnode_phandle_args *args)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ if (args->args_count < 1)
+ return -EINVAL;
+
+ /* GPIOs in DT are 1-based */
+ desc->offset = args->args[0] - 1;
+ if (desc->offset >= uc_priv->gpio_count)
+ return -EINVAL;
+
+ if (args->args_count < 2)
+ return 0;
+
+ desc->flags = gpio_flags_xlate(args->args[1]);
+
+ return 0;
+}
+
static const struct dm_gpio_ops qcom_gpio_ops = {
.direction_input= qcom_gpio_direction_input,
.direction_output = qcom_gpio_direction_output,
.get_value = qcom_gpio_get_value,
.set_value = qcom_gpio_set_value,
.get_function = qcom_gpio_get_function,
+ .xlate = qcom_gpio_xlate,
};
static int qcom_gpio_probe(struct udevice *dev)
--
2.43.1
[PATCH v4 12/39] sandbox: dts: fix qcom pmic gpio
Adjust the DT to match upstream bindings.
Signed-off-by: Caleb Connolly
---
arch/sandbox/dts/sandbox.dtsi | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi
index 241f397ba6e7..c93ce7128942 100644
--- a/arch/sandbox/dts/sandbox.dtsi
+++ b/arch/sandbox/dts/sandbox.dtsi
@@ -419,17 +419,16 @@
#size-cells = <0x1>;
pm8916@0 {
compatible = "qcom,spmi-pmic";
- reg = <0x0 0x1>;
+ reg = <0x0 0x0>;
#address-cells = <0x1>;
- #size-cells = <0x1>;
+ #size-cells = <0x0>;
spmi_gpios: gpios@c000 {
compatible = "qcom,pm8916-gpio";
- reg = <0xc000 0x400>;
+ reg = <0xc000>;
gpio-controller;
- gpio-count = <4>;
+ gpio-ranges = <&spmi_gpios 0 0 4>;
#gpio-cells = <2>;
- gpio-bank-name="spmi";
};
};
};
--
2.43.1
[PATCH v4 13/39] pinctrl: qcom: stub support for special GPIOs
Most platforms have a handful of "special" GPIOs, like the MMC
clock/data lanes, UFS reset, etc. These don't follow the usually naming
scheme of "gpioX" and also have unique capabilities and registers. We
can get away without supporting them all for now, but DT compatibility
is still an issue.
Add support for allowing these to be specified after the other pins, and
make all pinmux/pinconf calls for them nop.
Signed-off-by: Caleb Connolly
---
arch/arm/mach-snapdragon/include/mach/gpio.h | 2 ++
drivers/gpio/msm_gpio.c | 20
drivers/pinctrl/qcom/pinctrl-qcom.c | 12
3 files changed, 34 insertions(+)
diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h
b/arch/arm/mach-snapdragon/include/mach/gpio.h
index 8dac62f870b9..c373f5a4cf3d 100644
--- a/arch/arm/mach-snapdragon/include/mach/gpio.h
+++ b/arch/arm/mach-snapdragon/include/mach/gpio.h
@@ -13,6 +13,8 @@
struct msm_pin_data {
int pin_count;
const unsigned int *pin_offsets;
+ /* Index of first special pin, these are ignored for now */
+ unsigned int special_pins_start;
};
static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int
selector)
diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
index 80cd28bb231f..8a5e8730e911 100644
--- a/drivers/gpio/msm_gpio.c
+++ b/drivers/gpio/msm_gpio.c
@@ -39,6 +39,10 @@ static int msm_gpio_direction_input(struct udevice *dev,
unsigned int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
+ /* Always NOP for special pins, assume they're in the correct state */
+ if (gpio >= priv->pin_data->special_pins_start)
+ return 0;
+
/* Disable OE bit */
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio),
GPIO_OE_MASK, GPIO_OE_DISABLE);
@@ -50,6 +54,10 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned
int gpio, int value)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
+ /* Always NOP for special pins, assume they're in the correct state */
+ if (gpio >= priv->pin_data->special_pins_start)
+ return 0;
+
value = !!value;
/* set value */
writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
@@ -62,6 +70,10 @@ static int msm_gpio_direction_output(struct udevice *dev,
unsigned int gpio,
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
+ /* Always NOP for special pins, assume they're in the correct state */
+ if (gpio >= priv->pin_data->special_pins_start)
+ return 0;
+
value = !!value;
/* set value */
writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
@@ -76,6 +88,10 @@ static int msm_gpio_get_value(struct udevice *dev, unsigned
int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
+ /* Always NOP for special pins, assume they're in the correct state */
+ if (gpio >= priv->pin_data->special_pins_start)
+ return 0;
+
return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN);
}
@@ -83,6 +99,10 @@ static int msm_gpio_get_function(struct udevice *dev,
unsigned int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
+ /* Always NOP for special pins, assume they're in the correct state */
+ if (gpio >= priv->pin_data->special_pins_start)
+ return 0;
+
if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE)
return GPIOF_OUTPUT;
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c
b/drivers/pinctrl/qcom/pinctrl-qcom.c
index dc3d8c4d9034..1ea4d21c41fc 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
@@ -83,6 +83,10 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int
pin_selector,
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+ /* Always NOP for special pins, assume they're in the correct state */
+ if (pin_selector >= priv->data->pin_data.special_pins_start)
+ return 0;
+
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
priv->data->get_function_mux(func_selector) << 2);
@@ -94,6 +98,10 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int
pin_selector,
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+ /* Always NOP for special pins */
+ if (pin_selector >= priv->data->pin_data.special_pins_start)
+ return 0;
+
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
argument = (argument / 2) - 1;
@@ -136,6 +144,10 @@ int msm_pinctrl_bind(struct udevice *dev)
const char *name;
int ret;
+ /* Make sure we don't indadvertently treat all pins as special pins. */
+ if (!data->pin_data.special_pins_start)
+
[PATCH v4 08/39] serial: msm: fix clock handling and pinctrl
Use the modern helpers to fetch the clock and use the correct property
("clocks" instead of "clock"). Drop the call to pinctrl_select_state()
as no boards have a "uart" pinctrl state and this prints confusing
errors.
Signed-off-by: Caleb Connolly
---
arch/arm/dts/dragonboard410c.dts | 3 ++-
arch/arm/dts/dragonboard820c.dts | 3 ++-
drivers/serial/serial_msm.c | 25 +
3 files changed, 9 insertions(+), 22 deletions(-)
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index 02c824d0226c..c395e6cc0427 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -84,7 +84,8 @@
serial@78b {
compatible = "qcom,msm-uartdm-v1.4";
reg = <0x78b 0x200>;
- clock = <&clkc 4>;
+ clocks = <&clkc 4>;
+ clock-names = "core";
pinctrl-names = "uart";
pinctrl-0 = <&blsp1_uart>;
};
diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
index 146a0af8aafe..86b7f83d36d6 100644
--- a/arch/arm/dts/dragonboard820c.dts
+++ b/arch/arm/dts/dragonboard820c.dts
@@ -78,7 +78,8 @@
blsp2_uart2: serial@75b {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x75b 0x1000>;
- clock = <&gcc 4>;
+ clocks = <&gcc 4>;
+ clock-names = "core";
pinctrl-names = "uart";
pinctrl-0 = <&blsp8_uart>;
};
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index 44b93bd7ff21..ac4280c6c4c2 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -160,29 +160,14 @@ static int msm_uart_clk_init(struct udevice *dev)
{
uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 115200);
- uint clkd[2]; /* clk_id and clk_no */
- int clk_offset;
- struct udevice *clk_dev;
struct clk clk;
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "clock",
- clkd, 2);
- if (ret)
- return ret;
-
- clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
- if (clk_offset < 0)
- return clk_offset;
-
- ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
- if (ret)
- return ret;
-
- clk.id = clkd[1];
- ret = clk_request(clk_dev, &clk);
- if (ret < 0)
+ ret = clk_get_by_name(dev, "core", &clk);
+ if (ret < 0) {
+ pr_warn("%s: Failed to get clock: %d\n", __func__, ret);
return ret;
+ }
ret = clk_set_rate(&clk, clk_rate);
if (ret < 0)
@@ -218,7 +203,6 @@ static int msm_serial_probe(struct udevice *dev)
if (ret)
return ret;
- pinctrl_select_state(dev, "uart");
uart_dm_init(priv);
return 0;
@@ -251,6 +235,7 @@ U_BOOT_DRIVER(serial_msm) = {
.priv_auto = sizeof(struct msm_serial_data),
.probe = msm_serial_probe,
.ops= &msm_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
};
#ifdef CONFIG_DEBUG_UART_MSM
--
2.43.1
[PATCH v4 16/39] board: dragonboard410c: add chainloaded config fragment
Add a config fragment for building U-Boot such that it can be chainloaded by aboot/LK rather than being flashed directly to the aboot partition. Reviewed-by: Neil Armstrong Signed-off-by: Caleb Connolly --- board/qualcomm/dragonboard410c/configs/chainloaded.config | 7 +++ 1 file changed, 7 insertions(+) diff --git a/board/qualcomm/dragonboard410c/configs/chainloaded.config b/board/qualcomm/dragonboard410c/configs/chainloaded.config new file mode 100644 index ..3fd064924a1f --- /dev/null +++ b/board/qualcomm/dragonboard410c/configs/chainloaded.config @@ -0,0 +1,7 @@ +# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set +CONFIG_TEXT_BASE=0x0 +# CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR is not set +# CONFIG_REMAKE_ELF is not set +CONFIG_POSITION_INDEPENDENT=y +CONFIG_INIT_SP_RELATIVE=y +CONFIG_SYS_INIT_SP_BSS_OFFSET=524288 -- 2.43.1
[PATCH v4 02/39] usb: dwc3-generic: support external vbus regulator
Add support for a vbus-supply regulator specified in devicetree. This
provides generic support to avoid hardcoded GPIO configuration in board
init code.
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
This patch has no dependencies
Cc: Marek Vasut
---
drivers/usb/dwc3/dwc3-generic.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 6fb2de8a5ace..48da621ba966 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
#include
#include "core.h"
#include "gadget.h"
@@ -47,6 +48,7 @@ struct dwc3_generic_priv {
struct dwc3_generic_host_priv {
struct xhci_ctrl xhci_ctrl;
struct dwc3_generic_priv gen_priv;
+ struct udevice *vbus_dev;
};
static int dwc3_generic_probe(struct udevice *dev,
@@ -240,6 +242,13 @@ static int dwc3_generic_host_probe(struct udevice *dev)
if (rc)
return rc;
+ rc = device_get_supply_regulator(dev, "vbus-supply", &priv->vbus_dev);
+ if (rc)
+ debug("%s: No vbus regulator found: %d\n", dev->name, rc);
+
+ if (priv->vbus_dev)
+ regulator_set_enable(priv->vbus_dev, true);
+
hccr = (struct xhci_hccr *)priv->gen_priv.base;
hcor = (struct xhci_hcor *)(priv->gen_priv.base +
HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
@@ -256,6 +265,9 @@ static int dwc3_generic_host_remove(struct udevice *dev)
if (rc)
return rc;
+ if (priv->vbus_dev)
+ regulator_set_enable(priv->vbus_dev, false);
+
return dwc3_generic_remove(dev, &priv->gen_priv);
}
--
2.43.1
[PATCH v4 18/39] board: dragonboard410c: import board code from mach-snapdragon
Some of the db410c board support code was written to be generic and
placed in mach-snapdragon. However, as the db410c is the only board
using this, move the code out of mach-snapdragon. This makes is more
obvious what code is relevant for which targets and helps tidy things up
a little more.
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
arch/arm/mach-snapdragon/Makefile| 2 -
arch/arm/mach-snapdragon/dram.c | 99
arch/arm/mach-snapdragon/include/mach/dram.h | 12 ---
arch/arm/mach-snapdragon/include/mach/misc.h | 13
arch/arm/mach-snapdragon/misc.c | 55 -
board/qualcomm/dragonboard410c/Makefile | 2 +-
board/qualcomm/dragonboard410c/dragonboard410c.c | 48 +++-
7 files changed, 45 insertions(+), 186 deletions(-)
diff --git a/arch/arm/mach-snapdragon/Makefile
b/arch/arm/mach-snapdragon/Makefile
index 3a3a297c1768..d02432df8b04 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -6,6 +6,4 @@ obj-$(CONFIG_SDM845) += sysmap-sdm845.o
obj-$(CONFIG_SDM845) += init_sdm845.o
obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
-obj-y += misc.o
-obj-y += dram.o
obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
diff --git a/arch/arm/mach-snapdragon/dram.c b/arch/arm/mach-snapdragon/dram.c
deleted file mode 100644
index 499dfdf0da6e..
--- a/arch/arm/mach-snapdragon/dram.c
+++ /dev/null
@@ -1,99 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Onboard memory detection for Snapdragon boards
- *
- * (C) Copyright 2018 Ramon Fried
- *
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#define SMEM_USABLE_RAM_PARTITION_TABLE 402
-#define RAM_PART_NAME_LENGTH16
-#define RAM_NUM_PART_ENTRIES32
-#define CATEGORY_SDRAM 0x0E
-#define TYPE_SYSMEM 0x01
-
-struct smem_ram_ptable_hdr {
- u32 magic[2];
- u32 version;
- u32 reserved;
- u32 len;
-} __attribute__ ((__packed__));
-
-struct smem_ram_ptn {
- char name[RAM_PART_NAME_LENGTH];
- u64 start;
- u64 size;
- u32 attr;
- u32 category;
- u32 domain;
- u32 type;
- u32 num_partitions;
- u32 reserved[3];
-} __attribute__ ((__packed__));
-
-struct smem_ram_ptable {
- struct smem_ram_ptable_hdr hdr;
- u32 reserved; /* Added for 8 bytes alignment of header */
- struct smem_ram_ptn parts[RAM_NUM_PART_ENTRIES];
-} __attribute__ ((__packed__));
-
-#ifndef MEMORY_BANKS_MAX
-#define MEMORY_BANKS_MAX 4
-#endif
-
-int msm_fixup_memory(void *blob)
-{
- u64 bank_start[MEMORY_BANKS_MAX];
- u64 bank_size[MEMORY_BANKS_MAX];
- size_t size;
- int i;
- int count = 0;
- struct udevice *smem;
- int ret;
- struct smem_ram_ptable *ram_ptable;
- struct smem_ram_ptn *p;
-
- ret = uclass_get_device_by_name(UCLASS_SMEM, "smem", &smem);
- if (ret < 0) {
- printf("Failed to find SMEM node. Check device tree\n");
- return 0;
- }
-
- ram_ptable = smem_get(smem, -1, SMEM_USABLE_RAM_PARTITION_TABLE, &size);
-
- if (!ram_ptable) {
- printf("Failed to find SMEM partition.\n");
- return -ENODEV;
- }
-
- /* Check validy of RAM */
- for (i = 0; i < RAM_NUM_PART_ENTRIES; i++) {
- p = &ram_ptable->parts[i];
- if (p->category == CATEGORY_SDRAM && p->type == TYPE_SYSMEM) {
- bank_start[count] = p->start;
- bank_size[count] = p->size;
- debug("Detected memory bank %u: start: 0x%llx size:
0x%llx\n",
- count, p->start, p->size);
- count++;
- }
- }
-
- if (!count) {
- printf("Failed to detect any memory bank\n");
- return -ENODEV;
- }
-
- ret = fdt_fixup_memory_banks(blob, bank_start, bank_size, count);
- if (ret)
- return ret;
-
- return 0;
-}
diff --git a/arch/arm/mach-snapdragon/include/mach/dram.h
b/arch/arm/mach-snapdragon/include/mach/dram.h
deleted file mode 100644
index 0a9eedda414c..
--- a/arch/arm/mach-snapdragon/include/mach/dram.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Snapdragon DRAM
- * Copyright (C) 2018 Ramon Fried
- */
-
-#ifndef DRAM_H
-#define DRAM_H
-
-int msm_fixup_memory(void *blob);
-
-#endif
diff --git a/arch/arm/mach-snapdragon/include/mach/misc.h
b/arch/arm/mach-snapdragon/include/mach/misc.h
deleted file mode 100644
index c60e3e472470..
--- a/arch/arm/mach-snapdragon/include/mach/misc.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Snapdragon DRAM
- * Copyright (C) 2018 Ramon Fried
- */
-
[PATCH v4 10/39] gpio: qcom_pmic: add a quirk to skip GPIO configuration
Some platforms hard reset when attempting to configure PMIC GPIOs. Add
support for quirks specified in match data with a single quirk to skip
this configuration. We rely on the GPIO already be configured correctly,
which is always the case for volume up (the only current user of these
GPIOs).
Signed-off-by: Caleb Connolly
---
drivers/gpio/qcom_pmic_gpio.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 2a4fef8d28cb..198cd84bc31e 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -64,6 +64,15 @@
#define REG_EN_CTL 0x46
#define REG_EN_CTL_ENABLE (1 << 7)
+/**
+ * pmic_gpio_match_data - platform specific configuration
+ *
+ * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to
configure them
+ */
+enum pmic_gpio_quirks {
+ QCOM_PMIC_QUIRK_READONLY = (1 << 0),
+};
+
struct qcom_gpio_bank {
uint32_t pid; /* Peripheral ID on SPMI bus */
bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
@@ -75,7 +84,12 @@ static int qcom_gpio_set_direction(struct udevice *dev,
unsigned offset,
struct qcom_gpio_bank *priv = dev_get_priv(dev);
uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
uint32_t reg_ctl_val;
- int ret;
+ ulong quirks = dev_get_driver_data(dev);
+ int ret = 0;
+
+ /* Some PMICs don't like their GPIOs being configured */
+ if (quirks & QCOM_PMIC_QUIRK_READONLY)
+ return 0;
/* Disable the GPIO */
ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
@@ -304,7 +318,7 @@ static int qcom_gpio_of_to_plat(struct udevice *dev)
static const struct udevice_id qcom_gpio_ids[] = {
{ .compatible = "qcom,pm8916-gpio" },
{ .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
- { .compatible = "qcom,pm8998-gpio" },
+ { .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
{ .compatible = "qcom,pms405-gpio" },
{ }
};
--
2.43.1
[PATCH v4 14/39] pinctrl: qcom: fix DT compatibility
Upstream devicetrees label GPIOs with "gpioX", not "GPIO_X", fix this
for SoCs where we're now using upstream DT.
Signed-off-by: Caleb Connolly
---
drivers/pinctrl/qcom/pinctrl-apq8016.c | 26 +++
drivers/pinctrl/qcom/pinctrl-apq8096.c | 16 +-
drivers/pinctrl/qcom/pinctrl-qcs404.c | 58 --
3 files changed, 69 insertions(+), 31 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c
b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index 8149ffd83cc4..10796710ba7a 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -14,18 +14,18 @@
#define MAX_PIN_NAME_LEN 32
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
static const char * const msm_pinctrl_pins[] = {
- "SDC1_CLK",
- "SDC1_CMD",
- "SDC1_DATA",
- "SDC2_CLK",
- "SDC2_CMD",
- "SDC2_DATA",
- "QDSD_CLK",
- "QDSD_CMD",
- "QDSD_DATA0",
- "QDSD_DATA1",
- "QDSD_DATA2",
- "QDSD_DATA3",
+ "sdc1_clk",
+ "sdc1_cmd",
+ "sdc1_data",
+ "sdc2_clk",
+ "sdc2_cmd",
+ "sdc2_data",
+ "qdsd_clk",
+ "qdsd_cmd",
+ "qdsd_data0",
+ "qdsd_data1",
+ "qdsd_data2",
+ "qdsd_data3",
};
static const struct pinctrl_function msm_pinctrl_functions[] = {
@@ -42,7 +42,7 @@ static const char *apq8016_get_pin_name(struct udevice *dev,
unsigned int selector)
{
if (selector < 122) {
- snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
return pin_name;
} else {
return msm_pinctrl_pins[selector - 122];
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c
b/drivers/pinctrl/qcom/pinctrl-apq8096.c
index d64ab1ff7bee..f2eeb4cf469a 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8096.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c
@@ -14,13 +14,13 @@
#define MAX_PIN_NAME_LEN 32
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
static const char * const msm_pinctrl_pins[] = {
- "SDC1_CLK",
- "SDC1_CMD",
- "SDC1_DATA",
- "SDC2_CLK",
- "SDC2_CMD",
- "SDC2_DATA",
- "SDC1_RCLK",
+ "sdc1_clk",
+ "sdc1_cmd",
+ "sdc1_data",
+ "sdc2_clk",
+ "sdc2_cmd",
+ "sdc2_data",
+ "sdc1_rclk",
};
static const struct pinctrl_function msm_pinctrl_functions[] = {
@@ -37,7 +37,7 @@ static const char *apq8096_get_pin_name(struct udevice *dev,
unsigned int selector)
{
if (selector < 150) {
- snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
return pin_name;
} else {
return msm_pinctrl_pins[selector - 150];
diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c
b/drivers/pinctrl/qcom/pinctrl-qcs404.c
index ac00afa2a1f4..5066f2bba6b3 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcs404.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c
@@ -10,20 +10,24 @@
#include "pinctrl-qcom.h"
+#define NORTH 0x0030
+#define SOUTH 0x
+#define EAST 0x06b0
+
#define MAX_PIN_NAME_LEN 32
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
static const char * const msm_pinctrl_pins[] = {
- "SDC1_RCLK",
- "SDC1_CLK",
- "SDC1_CMD",
- "SDC1_DATA",
- "SDC2_CLK",
- "SDC2_CMD",
- "SDC2_DATA",
+ "sdc1_rclk",
+ "sdc1_clk",
+ "sdc1_cmd",
+ "sdc1_data",
+ "sdc2_clk",
+ "sdc2_cmd",
+ "sdc2_data",
};
static const struct pinctrl_function msm_pinctrl_functions[] = {
- {"blsp_uart2", 1},
+ {"gpio", 0},
{"rgmii_int", 1},
{"rgmii_ck", 1},
{"rgmii_tx", 1},
@@ -37,6 +41,40 @@ static const struct pinctrl_function msm_pinctrl_functions[]
= {
{"blsp_i2c_scl_a2", 3},
{"blsp_i2c3", 2},
{"blsp_i2c4", 1},
+ {"blsp_uart_tx_a2", 1},
+ {"blsp_uart_rx_a2", 1},
+};
+
+static const unsigned int qcs404_pin_offsets[] = {
+ [0] = SOUTH,[1] = SOUTH,[2] = SOUTH,[3] = SOUTH,[4] =
SOUTH,
+ [5] = SOUTH, [6] = SOUTH, [7] = SOUTH, [8] = SOUTH,[9] =
SOUTH,
+ [10] = SOUTH, [11] = SOUTH, [12] = SOUTH, [13] = SOUTH, [14] =
SOUTH,
+ [15] = SOUTH, [16] = SOUTH, [17] = NORTH, [18] = NORTH, [19] =
NORTH,
+ [20] = NORTH, [21] = SOUTH, [22] = NORTH, [23] = NORTH, [24] =
NORTH,
+ [25] = NORTH, [26] = EAST, [27] = EAST, [28] = EAST, [29] = EAST,
+ [30] = NORTH, [31] = NORTH, [32] = NORTH, [33] = NORTH, [34] =
SOUTH,
+ [35] = SOUTH, [36] = NORTH, [37] = NORTH, [38] = NORTH, [39] = EAST,
+ [40] = EAST, [41] = EAST, [42] = EAST, [43] = EAST, [44] = EAST,
+ [45] = EAST, [46] =
[PATCH v4 20/39] mach-snapdragon: generalise board support
Historically, Qualcomm boards have relied on heavy hardcoding in U-Boot, in many cases to the specific SoC but also to the board itself (e.g. memory map). This has been largely resolved by modernising the Qualcomm drivers in U-Boot, however the board code still largely follows this model. This patch removes the board specific memory maps and duplicated board init code, replacing it with generic init code. The memory map is now built at runtime based on data read from DT, this allows for the memory map to be provided without having to recompile U-Boot. Support is also added for booting with appended DTBs, so that the first-stage bootloader can populate the memory map for us. The sdm845 specific init code is dropped entirely, it set an environment variable depending on if a button was pressed, but this variable wasn't used in U-Boot, and could be written to use the button command instead. The KASLR detection is also dropped as with appended dtb, the kaslr seed can be read directly from the DTB passed to U-Boot. A new qcom_defconfig is added, with the aim of providing a generic U-Boot configuration that will work on as many Qualcomm boards as possible. It replaces the defconfig files for the Dragonboard 845c, Galaxy S9, and QCS404 EVB. For now the db410c and 820c are excluded as they still have some board code left. Similarly, the config headers for db845c, starqltechn, and qcs404-evb are replaced by a single qcom header. The previously db410c-specific board_usb_init() function is made to be generic and is added to mach-snapdragon. While we lack proper modelling for USB configuration, using a well-known named pinctrl state is a reasonably generic middleground, and works using upstream DT. This function will do nothing unless the USB node has a pinctrl state named "device", in which case it will be set when entering USB peripheral mode. Reviewed-by: Neil Armstrong Signed-off-by: Caleb Connolly --- arch/arm/Kconfig | 3 + arch/arm/dts/Makefile| 9 +- arch/arm/mach-snapdragon/Kconfig | 96 ++ arch/arm/mach-snapdragon/Makefile| 6 +- arch/arm/mach-snapdragon/board.c | 215 +++ arch/arm/mach-snapdragon/init_sdm845.c | 73 arch/arm/mach-snapdragon/sysmap-apq8016.c| 31 arch/arm/mach-snapdragon/sysmap-apq8096.c| 31 arch/arm/mach-snapdragon/sysmap-qcs404.c | 43 - arch/arm/mach-snapdragon/sysmap-sdm845.c | 31 board/qualcomm/dragonboard410c/Kconfig | 15 -- board/qualcomm/dragonboard410c/dragonboard410c.c | 41 - board/qualcomm/dragonboard820c/Kconfig | 15 -- board/qualcomm/dragonboard820c/dragonboard820c.c | 39 +--- board/qualcomm/dragonboard845c/Kconfig | 12 -- board/qualcomm/qcs404-evb/Kconfig| 15 -- board/qualcomm/qcs404-evb/qcs404-evb.c | 21 +-- configs/dragonboard410c_defconfig| 6 +- configs/dragonboard820c_defconfig| 6 +- configs/dragonboard845c_defconfig| 29 --- configs/qcom_defconfig | 67 +++ configs/qcs404evb_defconfig | 5 +- configs/starqltechn_defconfig| 41 - include/configs/dragonboard845c.h| 20 --- include/configs/qcom.h | 21 +++ include/configs/qcs404-evb.h | 20 --- include/configs/sdm845.h | 26 --- 27 files changed, 345 insertions(+), 592 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6b072be24634..672577d0ddcc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1095,6 +1095,9 @@ config ARCH_SNAPDRAGON select OF_SEPARATE select SMEM select SPMI + select OF_BOARD + select SAVE_PREV_BL_FDT_ADDR + select LINUX_KERNEL_IMAGE_HEADER imply CMD_DM config ARCH_SOCFPGA diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ce10d3dbb07d..751035a577f6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -631,10 +631,11 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \ dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb -dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb -dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb -dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb -dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb +dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb \ + dragonboard820c.dtb \ + dragonboard845c.dtb \ + starqltechn.dtb \ + qcs404-evb.dtb dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index f897c393464f..96e44e2c5491 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -3,6 +
[PATCH v4 15/39] pinctrl: qcom: apq8016: init pre-reloaction
On the DB410c we support running as a first stage bootloader. This
requires initialising the GPIOs which are muxed to UART before they can
be used. Add DM_FLAG_PRE_RELOC to the apq8016 pinctrl driver to ensure
that we do this early enough.
This is required to prevent the first few lines of UART log from being
dropped.
Reported-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c
b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index 10796710ba7a..df5bd1c19f6e 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -73,4 +73,5 @@ U_BOOT_DRIVER(pinctrl_apq8016) = {
.of_match = msm_pinctrl_ids,
.ops= &msm_pinctrl_ops,
.bind = msm_pinctrl_bind,
+ .flags = DM_FLAG_PRE_RELOC,
};
--
2.43.1
[PATCH v4 06/39] clock/qcom: qcs404: fix clk_set_rate
We should be returning the rate that we set the clock to, drivers like
MMC rely on this. So fix it.
Signed-off-by: Caleb Connolly
---
drivers/clk/qcom/clock-qcs404.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c
index f5b352803927..958312b88842 100644
--- a/drivers/clk/qcom/clock-qcs404.c
+++ b/drivers/clk/qcom/clock-qcs404.c
@@ -193,24 +193,18 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong
rate)
switch (clk->id) {
case GCC_BLSP1_UART2_APPS_CLK:
- /* UART: 115200 */
+ /* UART: 1843200Hz for a fixed 115200 baudrate (1920 *
(12/125)) */
clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
CFG_CLK_SRC_CXO, 16);
clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
- break;
- case GCC_BLSP1_AHB_CLK:
- clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
- break;
+ return 1843200;
case GCC_SDCC1_APPS_CLK:
/* SDCC1: 200MHz */
clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 7, 0, 0,
CFG_CLK_SRC_GPLL0, 8);
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
- break;
- case GCC_SDCC1_AHB_CLK:
- clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
- break;
+ return rate;
case GCC_ETH_RGMII_CLK:
if (rate == 25000)
clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0,
@@ -224,11 +218,15 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong
rate)
else if (rate == 500)
clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50,
CFG_CLK_SRC_GPLL1, 8);
- break;
- default:
- return 0;
+ return rate;
}
+ /* There is a bug only seeming to affect this board where the MMC
driver somehow calls
+* clk_set_rate() on a clock with id 0 which is associated with the
qcom_clk device.
+* The only clock with ID 0 is the xo_board clock which should not be
associated with
+* this device...
+*/
+ log_debug("Unknown clock id %ld\n", clk->id);
return 0;
}
@@ -305,6 +303,9 @@ static int qcs404_clk_enable(struct clk *clk)
clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0,
CFG_CLK_SRC_CXO);
break;
+ case GCC_SDCC1_AHB_CLK:
+ clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
+ break;
default:
return 0;
}
--
2.43.1
[PATCH v4 21/39] mach-snapdragon: dynamic load addresses
Heavily inspired by Apple board code. Use the LMB allocator to configure
load addresses at runtime, and implement a lookup table for selecting a
devicetree.
As some Qualcomm RBx boards have different RAM capacities and base
addresses, it isn't possible to hardcode these regions.
Signed-off-by: Caleb Connolly
---
arch/arm/Kconfig | 1 +
arch/arm/mach-snapdragon/board.c | 34
board/qualcomm/dragonboard410c/dragonboard410c.c | 2 +-
3 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 672577d0ddcc..0dba77f86b49 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1095,6 +1095,7 @@ config ARCH_SNAPDRAGON
select OF_SEPARATE
select SMEM
select SPMI
+ select BOARD_LATE_INIT
select OF_BOARD
select SAVE_PREV_BL_FDT_ADDR
select LINUX_KERNEL_IMAGE_HEADER
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index a1867852bcca..f445bed3af00 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#include
#include
@@ -159,6 +160,39 @@ int board_init(void)
return 0;
}
+void __weak qcom_late_init(void)
+{
+}
+
+#define KERNEL_COMP_SIZE SZ_64M
+
+#define addr_alloc(lmb, size) lmb_alloc(lmb, size, SZ_2M)
+
+/* Stolen from arch/arm/mach-apple/board.c */
+int board_late_init(void)
+{
+ struct lmb lmb;
+ u32 status = 0;
+
+ lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
+
+ /* We need to be fairly conservative here as we support boards with
just 1G of TOTAL RAM */
+ status |= env_set_hex("kernel_addr_r", addr_alloc(&lmb, SZ_128M));
+ status |= env_set_hex("ramdisk_addr_r", addr_alloc(&lmb, SZ_128M));
+ status |= env_set_hex("kernel_comp_addr_r", addr_alloc(&lmb,
KERNEL_COMP_SIZE));
+ status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
+ status |= env_set_hex("scriptaddr", addr_alloc(&lmb, SZ_4M));
+ status |= env_set_hex("pxefile_addr_r", addr_alloc(&lmb, SZ_4M));
+ status |= env_set_hex("fdt_addr_r", addr_alloc(&lmb, SZ_2M));
+
+ if (status)
+ log_warning("%s: Failed to set run time variables\n", __func__);
+
+ qcom_late_init();
+
+ return 0;
+}
+
static void build_mem_map(void)
{
int i;
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c
b/board/qualcomm/dragonboard410c/dragonboard410c.c
index 0136cc2237de..fbbfc0e65e24 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -88,7 +88,7 @@ int misc_init_r(void)
return 0;
}
-int board_late_init(void)
+int qcom_late_init(void)
{
char serial[16];
--
2.43.1
[PATCH v4 11/39] gpio: qcom_pmic: add pinctrl driver
Introduce a basic pinctrl driver for the SPMI PMIC GPIOs. This is
necessary to make proper use of upstream DT bindings specifically on the
dragonboard410c where they're used to switch between USB host and device
modes.
Only support for driving the pins as output low or high is enabled for
now.
To minimise duplicated code and allow for sharing common DT data, the
pinctrl driver is initialised as a child of the existing GPIO driver.
Signed-off-by: Caleb Connolly
---
drivers/gpio/qcom_pmic_gpio.c | 257 +-
1 file changed, 176 insertions(+), 81 deletions(-)
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 198cd84bc31e..9eca1556c356 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -7,10 +7,14 @@
#include
#include
+#include
+#include
+#include
#include
#include
#include
#include
+#include
#include
#include
@@ -73,17 +77,54 @@ enum pmic_gpio_quirks {
QCOM_PMIC_QUIRK_READONLY = (1 << 0),
};
-struct qcom_gpio_bank {
+struct qcom_pmic_gpio_data {
uint32_t pid; /* Peripheral ID on SPMI bus */
bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
+ u32 pin_count;
+ struct udevice *pmic; /* Reference to pmic device for read/write */
};
-static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
+/* dev can be the GPIO or pinctrl device */
+static int _qcom_gpio_set_direction(struct udevice *dev, u32 offset, bool
input, int value)
+{
+ struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
+ u32 gpio_base = plat->pid + REG_OFFSET(offset);
+ u32 reg_ctl_val;
+ int ret = 0;
+
+ /* Select the mode and output */
+ if (plat->lv_mv_type) {
+ if (input)
+ reg_ctl_val = REG_CTL_LV_MV_MODE_INPUT;
+ else
+ reg_ctl_val = REG_CTL_LV_MV_MODE_INOUT;
+ } else {
+ if (input)
+ reg_ctl_val = REG_CTL_MODE_INPUT;
+ else
+ reg_ctl_val = REG_CTL_MODE_INOUT | !!value;
+ }
+
+ ret = pmic_reg_write(plat->pmic, gpio_base + REG_CTL, reg_ctl_val);
+ if (ret < 0)
+ return ret;
+
+ if (plat->lv_mv_type && !input) {
+ ret = pmic_reg_write(plat->pmic,
+gpio_base + REG_LV_MV_OUTPUT_CTL,
+!!value << REG_LV_MV_OUTPUT_CTL_SHIFT);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int qcom_gpio_set_direction(struct udevice *dev, unsigned int offset,
bool input, int value)
{
- struct qcom_gpio_bank *priv = dev_get_priv(dev);
- uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
- uint32_t reg_ctl_val;
+ struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
+ uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
ulong quirks = dev_get_driver_data(dev);
int ret = 0;
@@ -97,33 +138,10 @@ static int qcom_gpio_set_direction(struct udevice *dev,
unsigned offset,
if (ret < 0)
return ret;
- /* Select the mode and output */
- if (priv->lv_mv_type) {
- if (input)
- reg_ctl_val = REG_CTL_LV_MV_MODE_INPUT;
- else
- reg_ctl_val = REG_CTL_LV_MV_MODE_INOUT;
- } else {
- if (input)
- reg_ctl_val = REG_CTL_MODE_INPUT;
- else
- reg_ctl_val = REG_CTL_MODE_INOUT | !!value;
- }
-
- ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL, reg_ctl_val);
- if (ret < 0)
- return ret;
-
- if (priv->lv_mv_type && !input) {
- ret = pmic_reg_write(dev->parent,
-gpio_base + REG_LV_MV_OUTPUT_CTL,
-!!value << REG_LV_MV_OUTPUT_CTL_SHIFT);
- if (ret < 0)
- return ret;
- }
+ _qcom_gpio_set_direction(dev, offset, input, value);
/* Set the right pull (no pull) */
- ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_PULL_CTL,
+ ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_PULL_CTL,
REG_DIG_PULL_NO_PU);
if (ret < 0)
return ret;
@@ -131,13 +149,13 @@ static int qcom_gpio_set_direction(struct udevice *dev,
unsigned offset,
/* Configure output pin drivers if needed */
if (!input) {
/* Select the VIN - VIN0, pin is input so it doesn't matter */
- ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_VIN_CTL,
+ ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_VIN_CTL,
REG_DIG_VIN_VIN0);
if (ret < 0)
[PATCH v4 19/39] board: dragonboard820c: use LINUX_KERNEL_IMAGE_HEADER
db820c predated support for prepending the kernel image header
automatically, drop it's custom linker script and head.S in favour of
this generic support.
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
arch/arm/mach-snapdragon/Kconfig | 1 +
board/qualcomm/dragonboard820c/Makefile | 1 -
board/qualcomm/dragonboard820c/head.S | 33 -
board/qualcomm/dragonboard820c/u-boot.lds | 111 --
4 files changed, 1 insertion(+), 145 deletions(-)
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index ad6671081910..f897c393464f 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -45,6 +45,7 @@ config TARGET_DRAGONBOARD410C
config TARGET_DRAGONBOARD820C
bool "96Boards Dragonboard 820C"
+ select LINUX_KERNEL_IMAGE_HEADER
imply CLK_QCOM_APQ8096
imply PINCTRL_QCOM_APQ8096
imply BUTTON_QCOM_PMIC
diff --git a/board/qualcomm/dragonboard820c/Makefile
b/board/qualcomm/dragonboard820c/Makefile
index 643311f5b3ba..2ae6d16364aa 100644
--- a/board/qualcomm/dragonboard820c/Makefile
+++ b/board/qualcomm/dragonboard820c/Makefile
@@ -3,4 +3,3 @@
# (C) Copyright 2017 Jorge Ramirez-Ortiz
obj-y := dragonboard820c.o
-extra-y += head.o
diff --git a/board/qualcomm/dragonboard820c/head.S
b/board/qualcomm/dragonboard820c/head.S
deleted file mode 100644
index b052a858fd32..
--- a/board/qualcomm/dragonboard820c/head.S
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * ARM64 header for proper chain-loading with Little Kernel.
- *
- * Little Kernel shipped with Dragonboard820C boots standard Linux images for
- * ARM64. This file adds header that is required to boot U-Boot properly.
- *
- * For details see:
- * https://www.kernel.org/doc/Documentation/arm64/booting.txt
- *
- * (C) Copyright 2015 Mateusz Kulikowski
- */
-
-#include
-
-/*
- * per document in linux/Doc/arm64/booting.text
- */
-.global _arm64_header
-_arm64_header:
- b _start
- .word 0
- .quad CONFIG_TEXT_BASE-PHYS_SDRAM_1 /* Image load offset, LE */
- .quad 0/* Effective size of kernel image, little-endian */
- .quad 0/* kernel flags, little-endian */
- .quad 0/* reserved */
- .quad 0/* reserved */
- .quad 0/* reserved */
- .byte 0x41 /* Magic number, "ARM\x64" */
- .byte 0x52
- .byte 0x4d
- .byte 0x64
- .word 0/* reserved (used for PE COFF offset) */
diff --git a/board/qualcomm/dragonboard820c/u-boot.lds
b/board/qualcomm/dragonboard820c/u-boot.lds
deleted file mode 100644
index 5251b59fbe76..
--- a/board/qualcomm/dragonboard820c/u-boot.lds
+++ /dev/null
@@ -1,111 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Override linker script for fastboot-readable images
- *
- * (C) Copyright 2015 Mateusz Kulikowski
- *
- * Based on arch/arm/cpu/armv8/u-boot.lds (Just add header)
- */
-
-OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64",
"elf64-littleaarch64")
-OUTPUT_ARCH(aarch64)
-ENTRY(_arm64_header)
-SECTIONS
-{
- . = 0x;
-
- . = ALIGN(8);
- .text :
- {
- *(.__image_copy_start)
- board/qualcomm/dragonboard820c/head.o (.text*)
- CPUDIR/start.o (.text*)
- }
-
- /* This needs to come before *(.text*) */
- .efi_runtime : {
-__efi_runtime_start = .;
- *(.text.efi_runtime*)
- *(.rodata.efi_runtime*)
- *(.data.efi_runtime*)
-__efi_runtime_stop = .;
- }
-
- .text_rest :
- {
- *(.text*)
- }
-
- . = ALIGN(8);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(8);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(8);
-
- . = .;
-
- . = ALIGN(8);
- __u_boot_list : {
- KEEP(*(SORT(__u_boot_list*)));
- }
-
- . = ALIGN(8);
-
- .efi_runtime_rel : {
-__efi_runtime_rel_start = .;
- *(.rel*.efi_runtime)
- *(.rel*.efi_runtime.*)
-__efi_runtime_rel_stop = .;
- }
-
- . = ALIGN(8);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- . = ALIGN(8);
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rela.dyn : {
- *(.rela*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- _end = .;
-
- . = ALIGN(8);
-
- .bss_start : {
- KEEP(*(.__bss_start));
- }
-
- .bss : {
- *(.bss*)
-. = ALIGN(8);
- }
-
- .bss_end : {
- KEEP(*(.__bss_end));
- }
-
- /DISCARD/ : { *(.dynsym) }
- /DISCARD/ : { *(.dynstr*
[PATCH v4 22/39] mach-snapdragon: generate fdtfile automatically
With just a few basic rules, we can generate the $fdtfile environment
variable to match the format used in Linux. This uses the root
compatible property inside u-boot, with specific handling for the
Dragonboard845c which is a special case, and for the qrb robotics
boards.
This is known to work on supported platforms, and lets us avoid having a
big lookup table.
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
arch/arm/mach-snapdragon/board.c | 101 +++
1 file changed, 101 insertions(+)
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index f445bed3af00..5a859aabd5c4 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -160,6 +160,106 @@ int board_init(void)
return 0;
}
+/* Sets up the "board", and "soc" environment variables as well as
constructing the devicetree
+ * path, with a few quirks to handle non-standard dtb filenames. This is not
meant to be a
+ * comprehensive solution to automatically picking the DTB, but aims to be
correct for the
+ * majority case. For most devices it should be possible to make this
algorithm work by
+ * adjusting the root compatible property in the U-Boot DTS. Handling devices
with multiple
+ * variants that are all supported by a single U-Boot image will require
implementing device-
+ * specific detection.
+ */
+static void configure_env(void)
+{
+ const char *first_compat, *last_compat;
+ char *tmp;
+ char buf[32] = { 0 };
+ /*
+* Most DTB filenames follow the scheme: qcom/-[vendor]-.dtb
+* The vendor is skipped when it's a Qualcomm reference board, or the
+* db845c.
+*/
+ char dt_path[64] = { 0 };
+ int compat_count, ret;
+ ofnode root;
+
+ root = ofnode_root();
+ /* This is almost always 2, but be explicit that we want the first and
last compatibles
+* not the first and second.
+*/
+ compat_count = ofnode_read_string_count(root, "compatible");
+ if (compat_count < 2) {
+ log_warning("%s: only one root compatible bailing!\n",
__func__);
+ return;
+ }
+
+ /* The most specific device compatible (e.g. "thundercomm,db845c") */
+ ret = ofnode_read_string_index(root, "compatible", 0, &first_compat);
+ if (ret < 0) {
+ log_warning("Can't read first compatible\n");
+ return;
+ }
+
+ /* The last compatible is always the SoC compatible */
+ ret = ofnode_read_string_index(root, "compatible", compat_count - 1,
&last_compat);
+ if (ret < 0) {
+ log_warning("Can't read second compatible\n");
+ return;
+ }
+
+ /* Copy the second compat (e.g. "qcom,sdm845") into buf */
+ strlcpy(buf, last_compat, sizeof(buf) - 1);
+ tmp = buf;
+
+ /* strsep() is destructive, it replaces the comma with a \0 */
+ if (!strsep(&tmp, ",")) {
+ log_warning("second compatible '%s' has no ','\n", buf);
+ return;
+ }
+
+ /* tmp now points to just the "sdm845" part of the string */
+ env_set("soc", tmp);
+
+ /* Now figure out the "board" part from the first compatible */
+ memset(buf, 0, sizeof(buf));
+ strlcpy(buf, first_compat, sizeof(buf) - 1);
+ tmp = buf;
+
+ /* The Qualcomm reference boards (RBx, HDK, etc) */
+ if (!strncmp("qcom", buf, strlen("qcom"))) {
+ /*
+* They all have the first compatible as "qcom,-"
+* (e.g. "qcom,qrb5165-rb5"). We extract just the part after
+* the dash.
+*/
+ if (!strsep(&tmp, "-")) {
+ log_warning("compatible '%s' has no '-'\n", buf);
+ return;
+ }
+ /* tmp is now "rb5" */
+ env_set("board", tmp);
+ } else {
+ if (!strsep(&tmp, ",")) {
+ log_warning("compatible '%s' has no ','\n", buf);
+ return;
+ }
+ /* for thundercomm we just want the bit after the comma (e.g.
"db845c"),
+* for all other boards we replace the comma with a '-' and
take both
+* (e.g. "oneplus-enchilada")
+*/
+ if (!strncmp("thundercomm", buf, strlen("thundercomm"))) {
+ env_set("board", tmp);
+ } else {
+ *(tmp - 1) = '-';
+ env_set("board", buf);
+ }
+ }
+
+ /* Now build the full path name */
+ snprintf(dt_path, sizeof(dt_path), "qcom/%s-%s.dtb",
+env_get("soc"), env_get("board"));
+ env_set("fdtfile", dt_path);
+}
+
void __weak qcom_late_init(void)
{
}
@@ -188,6 +288,7 @@ int board_late_init(void)
if (status)
log_warning("%s:
[PATCH v4 17/39] board: dragonboard410c: upstream DT compat
Use the root compatible strings from upstream Linux, add missing
'#clock-cells' property to the gcc node.
Adjust some of the msm8916/apq8016 drivers to use the correct upstream
compatible properties and DT bindings.
This prepares us to switch to upstream DT in a future patch.
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
arch/arm/dts/dragonboard410c.dts | 25 +++-
board/qualcomm/dragonboard410c/dragonboard410c.c | 93 +++-
doc/device-tree-bindings/usb/ehci-msm.txt| 10 --
drivers/clk/qcom/clock-apq8016.c | 7 +-
drivers/phy/qcom/msm8916-usbh-phy.c | 4 +-
drivers/pinctrl/qcom/pinctrl-apq8016.c | 2 +-
drivers/usb/host/ehci-msm.c | 22 ++-
include/dt-bindings/clock/qcom,gcc-msm8916.h | 179 +++
8 files changed, 246 insertions(+), 96 deletions(-)
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index c395e6cc0427..453642b25705 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -12,7 +12,7 @@
/ {
model = "Qualcomm Technologies, Inc. Dragonboard 410c";
- compatible = "qcom,dragonboard", "qcom,apq8016-sbc";
+ compatible = "qcom,apq8016-sbc", "qcom,apq8016";
qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>;
qcom,board-id = <0x10018 0x0>;
#address-cells = <0x2>;
@@ -79,6 +79,7 @@
reg = <0x180 0x8>;
#address-cells = <0x1>;
#size-cells = <0x0>;
+ #clock-cells = <0x1>;
};
serial@78b {
@@ -91,15 +92,25 @@
};
ehci@78d9000 {
- compatible = "qcom,ehci-host";
+ compatible = "qcom,ci-hdrc";
reg = <0x78d9000 0x400>;
phys = <&ehci_phy>;
- };
- ehci_phy: ehci_phy@78d9000 {
- compatible = "qcom,apq8016-usbphy";
- reg = <0x78d9000 0x400>;
- #phy-cells = <0>;
+ ulpi {
+ usb_hs_phy: phy {
+ compatible = "qcom,usb-hs-phy-msm8916",
+"qcom,usb-hs-phy";
+ #phy-cells = <0>;
+ clocks = <&xo_board>, <&gcc
GCC_USB2A_PHY_SLEEP_CLK>;
+ clock-names = "ref", "sleep";
+ resets = <&gcc GCC_USB2A_PHY_BCR>,
<&usb 0>;
+ reset-names = "phy", "por";
+ qcom,init-seq = /bits/ 8 <0x0 0x44>,
+<0x1 0x6b>,
+<0x2 0x24>,
+<0x3 0x13>;
+ };
+ };
};
sdhci@07824000 {
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c
b/board/qualcomm/dragonboard410c/dragonboard410c.c
index 350e0e9e20aa..1adac07569ae 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -23,84 +24,32 @@
DECLARE_GLOBAL_DATA_PTR;
-int dram_init(void)
-{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
+#define USB_HUB_RESET_GPIO 2
+#define USB_SW_SELECT_GPIO 3
int board_usb_init(int index, enum usb_init_type init)
{
- static struct udevice *pmic_gpio;
- static struct gpio_desc hub_reset, usb_sel;
- int ret = 0, node;
+ struct udevice *usb;
+ int ret = 0;
- if (!pmic_gpio) {
- ret = uclass_get_device_by_name(UCLASS_GPIO,
- "pm8916_gpios@c000",
- &pmic_gpio);
- if (ret < 0) {
- printf("Failed to find pm8916_gpios@c000 node.\n");
- return ret;
- }
+ /* USB device */
+ ret = device_find_global_by_ofnode(ofnode_path("/soc/usb"), &usb);
+ if (ret) {
+ printf("Cannot find USB device\n");
+ return ret;
}
- /* Try to request gpios needed to start usb host on dragonboard */
- if (!dm_gpio_is_valid(&hub_reset)) {
- node = fdt_subnode_offset(gd->fdt_blob,
- dev_o
[PATCH v4 28/39] dts: sdm845: import supporting dtsi files
Import the PM8998 and PMI8998 PMIC DTSI files from Linux as well
as the common audio codec in preperation for replacing board DTS files
with upstream.
Taken from kernel tag v6.7
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
arch/arm/dts/pm8998.dtsi | 130 +++
arch/arm/dts/pmi8998.dtsi| 98 +
arch/arm/dts/sdm845-wcd9340.dtsi | 86 ++
3 files changed, 314 insertions(+)
diff --git a/arch/arm/dts/pm8998.dtsi b/arch/arm/dts/pm8998.dtsi
new file mode 100644
index ..3f82715392c6
--- /dev/null
+++ b/arch/arm/dts/pm8998.dtsi
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/* Copyright 2018 Google LLC. */
+
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ thermal-zones {
+ pm8998-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&pm8998_temp>;
+
+ trips {
+ pm8998_alert0: pm8998-alert0 {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ pm8998_crit: pm8998-crit {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus {
+ pm8998_lsid0: pmic@0 {
+ compatible = "qcom,pm8998", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8998_pon: pon@800 {
+ compatible = "qcom,pm8998-pon";
+
+ reg = <0x800>;
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
+
+ pm8998_pwrkey: pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = ;
+ };
+
+ pm8998_resin: resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ status = "disabled";
+ };
+ };
+
+ pm8998_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pm8998_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8998_coincell: charger@2800 {
+ compatible = "qcom,pm8998-coincell",
"qcom,pm8941-coincell";
+ reg = <0x2800>;
+
+ status = "disabled";
+ };
+
+ pm8998_adc: adc@3100 {
+ compatible = "qcom,spmi-adc-rev2";
+ reg = <0x3100>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ channel@6 {
+ reg = ;
+ label = "die_temp";
+ };
+ };
+
+ pm8998_adc_tm: adc-tm@3400 {
+ compatible = "qcom,spmi-adc-tm-hc";
+ reg = <0x3400>;
+ interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
+ #thermal-sensor-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>, <0x6100>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pm8998_gpios: gpio@c000 {
+ compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
[PATCH v4 27/39] dt-bindings: import headers for SDM845
Import the DT bindings headers that are used by SDM845 from Linux. Taken from kernel tag v6.7 Reviewed-by: Neil Armstrong Signed-off-by: Caleb Connolly --- include/dt-bindings/clock/qcom,camcc-sdm845.h | 116 ++ include/dt-bindings/clock/qcom,dispcc-sdm845.h | 56 +++ include/dt-bindings/clock/qcom,gpucc-sdm845.h | 24 ++ include/dt-bindings/clock/qcom,lpass-sdm845.h | 15 + include/dt-bindings/clock/qcom,rpmh.h | 37 ++ include/dt-bindings/clock/qcom,videocc-sdm845.h| 35 ++ include/dt-bindings/dma/qcom-gpi.h | 11 + include/dt-bindings/firmware/qcom,scm.h| 39 ++ include/dt-bindings/iio/qcom,spmi-vadc.h | 300 +++ include/dt-bindings/interconnect/qcom,osm-l3.h | 15 + include/dt-bindings/interconnect/qcom,sdm845.h | 150 include/dt-bindings/phy/phy-qcom-qmp.h | 20 + include/dt-bindings/phy/phy-qcom-qusb2.h | 37 ++ include/dt-bindings/pinctrl/qcom,pmic-gpio.h | 164 include/dt-bindings/power/qcom-rpmpd.h | 412 + .../dt-bindings/regulator/qcom,rpmh-regulator.h| 36 ++ include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 + include/dt-bindings/reset/qcom,sdm845-pdc.h| 22 ++ include/dt-bindings/soc/qcom,apr.h | 28 ++ include/dt-bindings/soc/qcom,rpmh-rsc.h| 14 + include/dt-bindings/sound/qcom,q6afe.h | 9 + include/dt-bindings/sound/qcom,q6asm.h | 26 ++ include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h | 234 23 files changed, 1817 insertions(+) diff --git a/include/dt-bindings/clock/qcom,camcc-sdm845.h b/include/dt-bindings/clock/qcom,camcc-sdm845.h new file mode 100644 index ..4f7a2d2320bf --- /dev/null +++ b/include/dt-bindings/clock/qcom,camcc-sdm845.h @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H +#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H + +/* CAM_CC clock registers */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_AREG_CLK1 +#define CAM_CC_BPS_AXI_CLK 2 +#define CAM_CC_BPS_CLK 3 +#define CAM_CC_BPS_CLK_SRC 4 +#define CAM_CC_CAMNOC_ATB_CLK 5 +#define CAM_CC_CAMNOC_AXI_CLK 6 +#define CAM_CC_CCI_CLK 7 +#define CAM_CC_CCI_CLK_SRC 8 +#define CAM_CC_CPAS_AHB_CLK9 +#define CAM_CC_CPHY_RX_CLK_SRC 10 +#define CAM_CC_CSI0PHYTIMER_CLK11 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC12 +#define CAM_CC_CSI1PHYTIMER_CLK13 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC14 +#define CAM_CC_CSI2PHYTIMER_CLK15 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC16 +#define CAM_CC_CSI3PHYTIMER_CLK17 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC18 +#define CAM_CC_CSIPHY0_CLK 19 +#define CAM_CC_CSIPHY1_CLK 20 +#define CAM_CC_CSIPHY2_CLK 21 +#define CAM_CC_CSIPHY3_CLK 22 +#define CAM_CC_FAST_AHB_CLK_SRC23 +#define CAM_CC_FD_CORE_CLK 24 +#define CAM_CC_FD_CORE_CLK_SRC 25 +#define CAM_CC_FD_CORE_UAR_CLK 26 +#define CAM_CC_ICP_APB_CLK 27 +#define CAM_CC_ICP_ATB_CLK 28 +#define CAM_CC_ICP_CLK 29 +#define CAM_CC_ICP_CLK_SRC 30 +#define CAM_CC_ICP_CTI_CLK 31 +#define CAM_CC_ICP_TS_CLK 32 +#define CAM_CC_IFE_0_AXI_CLK 33 +#define CAM_CC_IFE_0_CLK 34 +#define CAM_CC_IFE_0_CLK_SRC 35 +#define CAM_CC_IFE_0_CPHY_RX_CLK 36 +#define CAM_CC_IFE_0_CSID_CLK 37 +#define CAM_CC_IFE_0_CSID_CLK_SRC 38 +#define CAM_CC_IFE_0_DSP_CLK 39 +#define CAM_CC_IFE_1_AXI_CLK 40 +#define CAM_CC_IFE_1_CLK 41 +#define CAM_CC_IFE_1_CLK_SRC 42 +#define CAM_CC_IFE_1_CPHY_RX_CLK 43 +#define CAM_CC_IFE_1_CSID_CLK 44 +#define CAM_CC_IFE_1_CSID_CLK_SRC 45 +#define CAM_CC_IFE_1_DSP_CLK 46 +#define CAM_CC_IFE_LITE_CLK4
[PATCH v4 23/39] mach-snapdragon: carve out no-map regions
On Qualcomm platforms, the TZ may already have certain memory regions
under protection by the time U-Boot starts. There is a rare case on some
platforms where the prefetcher might speculatively access one of these
regions resulting in a board crash (TZ traps and then resets the board).
We shouldn't be accessing these regions from within U-Boot anyway, so
let's mark them all with PTE_TYPE_FAULT to prevent any speculative
access and correctly trap in EL1 rather than EL3.
This is quite costly with caches off (takes ~2 seconds on SDM845 vs 35ms
with caches on). So to minimise the impact this is only enabled on
QCS404 for now (where the issue is known to occur).
In the future, we should try to find a more efficient way to handle
this, perhaps by turning on the MMU in stages.
Signed-off-by: Caleb Connolly
---
arch/arm/mach-snapdragon/board.c | 162 +--
1 file changed, 140 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index 5a859aabd5c4..f12f5791a136 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -296,7 +297,7 @@ int board_late_init(void)
static void build_mem_map(void)
{
- int i;
+ int i, j;
/*
* Ensure the peripheral block is sized to correctly cover the address
range
@@ -312,28 +313,23 @@ static void build_mem_map(void)
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN;
- debug("Configured memory map:\n");
- debug(" 0x%016llx - 0x%016llx: Peripheral block\n",
- mem_map[0].phys, mem_map[0].phys + mem_map[0].size);
-
- /*
-* Now add memory map entries for each DRAM bank, ensuring we don't
-* overwrite the list terminator
-*/
- for (i = 0; i < ARRAY_SIZE(rbx_mem_map) - 2 && gd->bd->bi_dram[i].size;
i++) {
- if (i == ARRAY_SIZE(rbx_mem_map) - 1) {
- log_warning("Too many DRAM banks!\n");
- break;
- }
- mem_map[i + 1].phys = gd->bd->bi_dram[i].start;
- mem_map[i + 1].virt = mem_map[i + 1].phys;
- mem_map[i + 1].size = gd->bd->bi_dram[i].size;
- mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-PTE_BLOCK_INNER_SHARE;
-
- debug(" 0x%016llx - 0x%016llx: DDR bank %d\n",
- mem_map[i + 1].phys, mem_map[i + 1].phys + mem_map[i +
1].size, i);
+ for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 &&
gd->bd->bi_dram[j].size; i++, j++) {
+ mem_map[i].phys = gd->bd->bi_dram[j].start;
+ mem_map[i].virt = mem_map[i].phys;
+ mem_map[i].size = gd->bd->bi_dram[j].size;
+ mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
+ PTE_BLOCK_INNER_SHARE;
}
+
+ mem_map[i].phys = UINT64_MAX;
+ mem_map[i].size = 0;
+
+#ifdef DEBUG
+ debug("Configured memory map:\n");
+ for (i = 0; mem_map[i].size; i++)
+ debug(" 0x%016llx - 0x%016llx: entry %d\n",
+ mem_map[i].phys, mem_map[i].phys + mem_map[i].size, i);
+#endif
}
u64 get_page_table_size(void)
@@ -341,10 +337,132 @@ u64 get_page_table_size(void)
return SZ_64K;
}
+static int fdt_cmp_res(const void *v1, const void *v2)
+{
+ const struct fdt_resource *res1 = v1, *res2 = v2;
+
+ return res1->start - res2->start;
+}
+
+#define N_RESERVED_REGIONS 32
+
+/* Mark all no-map regions as PTE_TYPE_FAULT to prevent speculative access.
+ * On some platforms this is enough to trigger a security violation and trap
+ * to EL3.
+ */
+static void carve_out_reserved_memory(void)
+{
+ static struct fdt_resource res[N_RESERVED_REGIONS] = { 0 };
+ int parent, rmem, count, i = 0;
+ phys_addr_t start;
+ size_t size;
+
+ /* Some reserved nodes must be carved out, as the cache-prefetcher may
otherwise
+* attempt to access them, causing a security exception.
+*/
+ parent = fdt_path_offset(gd->fdt_blob, "/reserved-memory");
+ if (parent <= 0) {
+ log_err("No reserved memory regions found\n");
+ return;
+ }
+
+ /* Collect the reserved memory regions */
+ fdt_for_each_subnode(rmem, gd->fdt_blob, parent) {
+ const fdt32_t *ptr;
+ int len;
+ if (!fdt_getprop(gd->fdt_blob, rmem, "no-map", NULL))
+ continue;
+
+ if (i == N_RESERVED_REGIONS) {
+ log_err("Too many reserved regions!\n");
+ break;
+ }
+
+ /* Read the address and size out from the reg property. Doing
this "properly" with
+* fd
[PATCH v4 25/39] doc: board/qualcomm: document generic targets
Replace the board specific docs with a generic board.rst file which documents the build/boot process for the sdm845 and qcs404 boards now that the only differences are the DTB in use. At the same time, create a debugging page to document some useful snippets and tips for working with Qualcomm platforms. Reviewed-by: Neil Armstrong Signed-off-by: Caleb Connolly --- doc/board/qualcomm/board.rst | 125 + doc/board/qualcomm/debugging.rst | 61 ++ doc/board/qualcomm/index.rst | 4 +- doc/board/qualcomm/qcs404.rst| 79 -- doc/board/qualcomm/sdm845.rst| 167 --- 5 files changed, 188 insertions(+), 248 deletions(-) diff --git a/doc/board/qualcomm/board.rst b/doc/board/qualcomm/board.rst new file mode 100644 index ..4d793209f9e3 --- /dev/null +++ b/doc/board/qualcomm/board.rst @@ -0,0 +1,125 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Dzmitry Sankouski + +Qualcomm generic boards +=== + +About this +-- +This document describes how to build and run U-Boot for Qualcomm generic +boards. Right now the generic target supports the Snapdragon 845 SoC, however +it's expected to support more SoCs going forward. + +SDM845 - high-end qualcomm chip, introduced in late 2017. +Mostly used in flagship phones and tablets of 2018. + +The current boot flow support loading u-boot as an Android boot image via +Qualcomm's UEFI-based ABL (Android) Bootloader. The DTB used by U-Boot will +be appended to the U-Boot image the same way as when booting Linux. U-Boot +will then retrieve the DTB during init. This way the memory layout and KASLR +offset will be populated by ABL. + +Installation + +Build +^ + + $ ./tools/buildman/buildman -o .output qcom + +This will build ``.output/u-boot-nodtb.bin`` using the ``qcom_defconfig``. + +Generate FIT image (optional) +^ +See doc/uImage.FIT for more details + +Pack android boot image +^^^ +We'll assemble android boot image with ``u-boot-nodtb.bin`` instead of linux kernel, +and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel +with appended dtb, so let's mimic linux to satisfy stock bootloader. + +Boards +-- + +starqlte + + +The starqltechn is a production board for Samsung S9 (SM-G9600) phone, +based on the Qualcomm SDM845 SoC. + +This device is supported by the common qcom_defconfig. + +The DTB is called "sdm845-samsung-starqltechn.dtb" + +More information can be found on the `Samsung S9 page`_. + +dragonboard845c +^^^ + +The dragonboard845c is a Qualcomm Robotics RB3 Development Platform, based on +the Qualcomm SDM845 SoC. + +This device is supported by the common qcom_defconfig + +The DTB is called "sdm845-db845c.dtb" + +More information can be found on the `DragonBoard 845c page`_. + +qcs404-evb +^^ + +The QCS404 EvB is a Qualcomm Development Platform, based on the Qualcomm QCS404 SoC. + +This device is supported by the common qcom_defconfig + +The DTB is called "qcs404-evb-4000.dtb" + +Building steps +-- + +Steps: + +- Build u-boot + +As above:: + + ./tools/buildman/buildman -o .output qcom + +Or for db410c (and other boards not supported by the generic target):: + + make CROSS_COMPILE=aarch64-linux-gnu- O=.output dragonboard410c_defconfig + make O=.output -j$(nproc) + +- gzip u-boot:: + + gzip u-boot-nodtb.bin + +- Append dtb to gzipped u-boot:: + + cat u-boot-nodtb.bin.gz arch/arm/dts/your-board.dtb > u-boot-nodtb.bin.gz-dtb + +- If you chose to build a FIT image, A ``qcom.its`` file can be found in ``board/qualcomm/generic/`` + directory. It expects a folder as ``qcom_imgs/`` in the main directory containing pre-built kernel, + dts and ramdisk images. See ``qcom.its`` for full path to images:: + + mkimage -f qcom.its qcom.itb + +- Now we've got everything to build android boot image:: + + mkbootimg --kernel u-boot-nodtb.bin.gz-dtb --ramdisk db845c.itb \ + --output boot.img --pagesize 4096 --base 0x8000 + +Or with no FIT image:: + + mkbootimg --kernel u-boot-nodtb.bin.gz-dtb \ + --output boot.img --pagesize 4096 --base 0x8000 + +- Flash boot.img using fastboot and erase dtbo to avoid conflicts with our DTB: + + .. code-block:: bash + + fastboot flash boot boot.img + fastboot erase dtbo + +.. _Samsung S9 page: https://en.wikipedia.org/wiki/Samsung_Galaxy_S9 +.. _DragonBoard 845c page: https://www.96boards.org/product/rb3-platform/ diff --git a/doc/board/qualcomm/debugging.rst b/doc/board/qualcomm/debugging.rst new file mode 100644 index ..1c35d1909d12 --- /dev/null +++ b/doc/board/qualcomm/debugging.rst @@ -0,0 +1,61 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Caleb Connolly + +Qualcomm debugging +== + +About this +-- + +This page describes
[PATCH v4 31/39] dts: msm8916: import PMIC dtsi files
Import the supporting pm8916.dtsi and msm8916-pm8916.dtsi files from
upstream in preparation for switching boards over.
Taken from kernel tag v6.7
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
arch/arm/dts/msm8916-pm8916.dtsi | 157 ++
arch/arm/dts/pm8916.dtsi | 178 +++
2 files changed, 335 insertions(+)
diff --git a/arch/arm/dts/msm8916-pm8916.dtsi b/arch/arm/dts/msm8916-pm8916.dtsi
new file mode 100644
index ..b1a7eafbee31
--- /dev/null
+++ b/arch/arm/dts/msm8916-pm8916.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * msm8916-pm8916.dtsi describes common properties (e.g. regulator connections)
+ * that apply to most devices that make use of the MSM8916 SoC and PM8916 PMIC.
+ * Many regulators have a fixed purpose in the original reference design and
+ * were rarely re-used for different purposes. Devices that deviate from the
+ * typical reference design should not make use of this include and instead add
+ * the necessary properties in the board-specific device tree.
+ */
+
+#include "msm8916.dtsi"
+#include "pm8916.dtsi"
+
+&camss {
+ vdda-supply = <&pm8916_l2>;
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&pm8916_l2>;
+ vddio-supply = <&pm8916_l6>;
+};
+
+&mdss_dsi0_phy {
+ vddio-supply = <&pm8916_l6>;
+};
+
+&mpss {
+ pll-supply = <&pm8916_l7>;
+};
+
+&pm8916_codec {
+ vdd-cdc-io-supply = <&pm8916_l5>;
+ vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>;
+ vdd-micbias-supply = <&pm8916_l13>;
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm8916_l8>;
+ vqmmc-supply = <&pm8916_l5>;
+};
+
+&sdhc_2 {
+ vmmc-supply = <&pm8916_l11>;
+ vqmmc-supply = <&pm8916_l12>;
+};
+
+&usb_hs_phy {
+ v1p8-supply = <&pm8916_l7>;
+ v3p3-supply = <&pm8916_l13>;
+};
+
+&wcnss {
+ vddpx-supply = <&pm8916_l7>;
+};
+
+&wcnss_iris {
+ vddxo-supply = <&pm8916_l7>;
+ vddrfa-supply = <&pm8916_s3>;
+ vddpa-supply = <&pm8916_l9>;
+ vdddig-supply = <&pm8916_l5>;
+};
+
+&rpm_requests {
+ pm8916_rpm_regulators: regulators {
+ compatible = "qcom,rpm-pm8916-regulators";
+ vdd_l1_l2_l3-supply = <&pm8916_s3>;
+ vdd_l4_l5_l6-supply = <&pm8916_s4>;
+ vdd_l7-supply = <&pm8916_s4>;
+
+ /* pm8916_s1 is managed by rpmpd (MSM8916_VDDCX) */
+
+ pm8916_s3: s3 {
+ regulator-min-microvolt = <125>;
+ regulator-max-microvolt = <135>;
+ regulator-always-on; /* Needed for L2 */
+ };
+
+ pm8916_s4: s4 {
+ regulator-min-microvolt = <185>;
+ regulator-max-microvolt = <215>;
+ regulator-always-on; /* Needed for L5/L7 */
+ };
+
+ /*
+* Some of the regulators are unused or managed by another
+* processor (e.g. the modem). We should still define nodes for
+* them to ensure the vote from the application processor can be
+* dropped in case the regulators are already on during boot.
+*
+* The labels for these nodes are omitted on purpose because
+* boards should configure a proper voltage before using them.
+*/
+ l1 {};
+
+ pm8916_l2: l2 {
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <120>;
+ regulator-always-on; /* Needed for LPDDR RAM */
+ };
+
+ /* pm8916_l3 is managed by rpmpd (MSM8916_VDDMX) */
+
+ l4 {};
+
+ pm8916_l5: l5 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-always-on; /* Needed for most digital I/O */
+ };
+
+ pm8916_l6: l6 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ };
+
+ pm8916_l7: l7 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-always-on; /* Needed for CPU PLL */
+ };
+
+ pm8916_l8: l8 {
+ regulator-min-microvolt = <290>;
+ regulator-max-microvolt = <290>;
+ };
+
+ pm8916_l9: l9 {
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ l10 {};
+
+ pm8916_l11: l11 {
+ regulator-min-microvolt = <295>;
+ regulator-max-micro
[PATCH v4 26/39] doc: board/qualcomm: link to APQ8016 TRM
The MSM8916/APQ8016 Technical Reference Manual is publicly available and contains a lot of useful register maps for many core parts of the SoC. Include an archive.org link to it in the dragonboard410c documentation. Signed-off-by: Caleb Connolly --- doc/board/qualcomm/dragonboard410c.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/board/qualcomm/dragonboard410c.rst b/doc/board/qualcomm/dragonboard410c.rst index d0de9dbcbc9a..34629241110c 100644 --- a/doc/board/qualcomm/dragonboard410c.rst +++ b/doc/board/qualcomm/dragonboard410c.rst @@ -14,6 +14,8 @@ through LK. This is no longer the case, now U-Boot can replace LK entirely. .. _96Boards product page: https://www.96boards.org/product/dragonboard410c/ +.. _MSM8916/SD410/APQ8016 Technical Reference Manual: https://web.archive.org/web/20210525022203/https://developer.qualcomm.com/qfile/35259/lm80-p0436-100_d_snapdragon_410e_apq8016e_tech_reference_manual_revd.pdf + Installation First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``dragonboard410c``:: -- 2.43.1
[PATCH v4 24/39] board: qcs404-evb: drop board code
This board is entirely supported by the generic arch code and DTS. The
board code used to handle turning on the vbus regulator, however this is
now handled via DT.
With this, the board specific defconfig is also no longer needed, so
drop it as well.
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
board/qualcomm/qcs404-evb/Makefile | 6
board/qualcomm/qcs404-evb/qcs404-evb.c | 49 -
configs/qcs404evb_defconfig| 56 --
3 files changed, 111 deletions(-)
diff --git a/board/qualcomm/qcs404-evb/Makefile
b/board/qualcomm/qcs404-evb/Makefile
deleted file mode 100644
index 4665827e0859..
--- a/board/qualcomm/qcs404-evb/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2022 Sumit Garg
-#
-
-obj-y += qcs404-evb.o
diff --git a/board/qualcomm/qcs404-evb/qcs404-evb.c
b/board/qualcomm/qcs404-evb/qcs404-evb.c
deleted file mode 100644
index 1a4b1f97a3ae..
--- a/board/qualcomm/qcs404-evb/qcs404-evb.c
+++ /dev/null
@@ -1,49 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Board init file for QCS404-EVB
- *
- * (C) Copyright 2022 Sumit Garg
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void qcom_board_init(void)
-{
- struct udevice *pmic_gpio;
- struct gpio_desc usb_vbus_boost_pin;
- int ret, node;
-
- ret = uclass_get_device_by_name(UCLASS_GPIO,
- "pms405_gpios@c000",
- &pmic_gpio);
- if (ret < 0) {
- printf("Failed to find pms405_gpios@c000 node.\n");
- return;
- }
-
- node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pmic_gpio),
- "usb_vbus_boost_pin");
- if (node < 0) {
- printf("Failed to find usb_hub_reset_pm dt node.\n");
- return;
- }
- ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
-&usb_vbus_boost_pin, 0);
- if (ret < 0) {
- printf("Failed to request usb_hub_reset_pm gpio.\n");
- return;
- }
-
- dm_gpio_set_dir_flags(&usb_vbus_boost_pin,
- GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
-}
diff --git a/configs/qcs404evb_defconfig b/configs/qcs404evb_defconfig
deleted file mode 100644
index d85d193895b0..
--- a/configs/qcs404evb_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_BOARD="qcs404-evb"
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_COUNTER_FREQUENCY=1900
-CONFIG_POSITION_INDEPENDENT=y
-CONFIG_ARCH_SNAPDRAGON=y
-CONFIG_DEFAULT_DEVICE_TREE="qcs404-evb"
-CONFIG_IDENT_STRING="\nQualcomm QCS404-EVB"
-CONFIG_SYS_LOAD_ADDR=0x8000
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_BOOTDELAY=5
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="earlycon ignore_loglevel root= clk_ignore_unused"
-CONFIG_SAVE_PREV_BL_FDT_ADDR=y
-CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
-CONFIG_SYS_CBSIZE=512
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-# CONFIG_NET is not set
-CONFIG_CLK=y
-CONFIG_CLK_QCOM_QCS404=y
-CONFIG_MSM_GPIO=y
-CONFIG_QCOM_PMIC_GPIO=y
-CONFIG_MISC=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ADMA=y
-CONFIG_MMC_SDHCI_MSM=y
-CONFIG_PHY=y
-CONFIG_PHY_QCOM_USB_HS_28NM=y
-CONFIG_PHY_QCOM_USB_SS=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_QCOM_QCS404=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_QCOM=y
-CONFIG_MSM_SERIAL=y
-CONFIG_SPMI_MSM=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_LMB_MAX_REGIONS=64
--
2.43.1
[PATCH v4 34/39] dts: msm8996: import PMIC dtsi files
Import PM8994 and PMI8994 DTSI files in preparation for switching
MSM8996 boards to upstream DTS.
Taken from kernel tag v6.7
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
arch/arm/dts/pm8994.dtsi | 152 ++
arch/arm/dts/pmi8994.dtsi | 65
2 files changed, 217 insertions(+)
diff --git a/arch/arm/dts/pm8994.dtsi b/arch/arm/dts/pm8994.dtsi
new file mode 100644
index ..d44a95caf04a
--- /dev/null
+++ b/arch/arm/dts/pm8994.dtsi
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0
+#include
+#include
+#include
+#include
+
+/ {
+ thermal-zones {
+ pm8994-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&pm8994_temp>;
+
+ trips {
+ pm8994_alert0: pm8994-alert0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ pm8994_crit: pm8994-crit {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus {
+
+ pmic@0 {
+ compatible = "qcom,pm8994", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>, <0x6100>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pm8994_pon: pon@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x800>;
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
+
+ pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = ;
+ };
+
+ pm8994_resin: resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ status = "disabled";
+ };
+ };
+
+ pm8994_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pm8994_vadc VADC_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8994_vadc: adc@3100 {
+ compatible = "qcom,spmi-vadc";
+ reg = <0x3100>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ channel@7 {
+ reg = ;
+ qcom,pre-scaling = <1 3>;
+ label = "vph_pwr";
+ };
+ channel@8 {
+ reg = ;
+ label = "die_temp";
+ };
+ channel@9 {
+ reg = ;
+ label = "ref_625mv";
+ };
+ channel@a {
+ reg = ;
+ label = "ref_1250mv";
+ };
+ channel@e {
+ reg = ;
+ };
+ channel@f {
+ reg = ;
+ };
+ };
+
+ pm8994_gpios: gpio@c000 {
+ compatible = "qcom,pm8994-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ gpio-ranges = <&pm8994_gpios 0 0 22>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+
[PATCH v4 30/39] dt-bindings: import headers for MSM8916
Import the dt-bindings headers in preparation for switching to upstream DTS for MSM8916. Taken from kernel tag v6.7 Reviewed-by: Neil Armstrong Signed-off-by: Caleb Connolly --- include/dt-bindings/arm/coresight-cti-dt.h | 37 + include/dt-bindings/clock/qcom,rpmcc.h | 174 include/dt-bindings/interconnect/qcom,msm8916.h | 100 ++ include/dt-bindings/pinctrl/qcom,pmic-mpp.h | 106 +++ include/dt-bindings/reset/qcom,gcc-msm8916.h| 100 ++ include/dt-bindings/sound/apq8016-lpass.h | 9 ++ include/dt-bindings/sound/qcom,lpass.h | 46 +++ 7 files changed, 572 insertions(+) diff --git a/include/dt-bindings/arm/coresight-cti-dt.h b/include/dt-bindings/arm/coresight-cti-dt.h new file mode 100644 index ..61e7bdf8ea6e --- /dev/null +++ b/include/dt-bindings/arm/coresight-cti-dt.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for the defined trigger signal + * types on CoreSight CTI. + */ + +#ifndef _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H +#define _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H + +#define GEN_IO 0 +#define GEN_INTREQ 1 +#define GEN_INTACK 2 +#define GEN_HALTREQ3 +#define GEN_RESTARTREQ 4 +#define PE_EDBGREQ 5 +#define PE_DBGRESTART 6 +#define PE_CTIIRQ 7 +#define PE_PMUIRQ 8 +#define PE_DBGTRIGGER 9 +#define ETM_EXTOUT 10 +#define ETM_EXTIN 11 +#define SNK_FULL 12 +#define SNK_ACQCOMP13 +#define SNK_FLUSHCOMP 14 +#define SNK_FLUSHIN15 +#define SNK_TRIGIN 16 +#define STM_ASYNCOUT 17 +#define STM_TOUT_SPTE 18 +#define STM_TOUT_SW19 +#define STM_TOUT_HETE 20 +#define STM_HWEVENT21 +#define ELA_TSTART 22 +#define ELA_TSTOP 23 +#define ELA_DBGREQ 24 +#define CTI_TRIG_MAX 25 + +#endif /*_DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H */ diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h new file mode 100644 index ..46309c9953b2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2015 Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H +#define _DT_BINDINGS_CLK_MSM_RPMCC_H + +/* RPM clocks */ +#define RPM_PXO_CLK0 +#define RPM_PXO_A_CLK 1 +#define RPM_CXO_CLK2 +#define RPM_CXO_A_CLK 3 +#define RPM_APPS_FABRIC_CLK4 +#define RPM_APPS_FABRIC_A_CLK 5 +#define RPM_CFPB_CLK 6 +#define RPM_CFPB_A_CLK 7 +#define RPM_QDSS_CLK 8 +#define RPM_QDSS_A_CLK 9 +#define RPM_DAYTONA_FABRIC_CLK 10 +#define RPM_DAYTONA_FABRIC_A_CLK 11 +#define RPM_EBI1_CLK 12 +#define RPM_EBI1_A_CLK 13 +#define RPM_MM_FABRIC_CLK 14 +#define RPM_MM_FABRIC_A_CLK15 +#define RPM_MMFPB_CLK 16 +#define RPM_MMFPB_A_CLK17 +#define RPM_SYS_FABRIC_CLK 18 +#define RPM_SYS_FABRIC_A_CLK 19 +#define RPM_SFPB_CLK 20 +#define RPM_SFPB_A_CLK 21 +#define RPM_SMI_CLK22 +#define RPM_SMI_A_CLK 23 +#define RPM_PLL4_CLK 24 +#define RPM_XO_D0 25 +#define RPM_XO_D1 26 +#define RPM_XO_A0 27 +#define RPM_XO_A1 28 +#define RPM_XO_A2 29 +#define RPM_NSS_FABRIC_0_CLK 30 +#define RPM_NSS_FABRIC_0_A_CLK 31 +#define RPM_NSS_FABRIC_1_CLK 32 +#define RPM_NSS_FABRIC_1_A_CLK 33 + +/* SMD RPM clocks */ +#define RPM_SMD_XO_CLK_SRC 0 +#define RPM_SMD_XO_A_CLK_SRC 1 +#define RPM_SMD_PCNOC_CLK 2 +#define RPM_SMD_PCNOC_A_CLK3 +#define RPM_SMD_SNOC_CLK 4 +#define RPM_SMD_SNOC_A_CLK 5 +#define RPM_SMD_BIMC_CLK 6 +#define RPM_SMD_BIMC_A_CLK 7 +#define RPM_SMD_QDSS_CLK 8 +#define RPM_SMD_QDSS_A_CLK 9 +#define RPM_SMD_BB_CLK110 +#define RPM_SMD_BB_CLK1_A 11 +#define RPM_SMD_BB_CLK212 +#define RPM_SMD_BB_CLK2_A 13 +#define RPM_SMD_RF_CLK114 +#define RPM_SMD_RF_CLK1_A 1
[PATCH v4 35/39] dts: dragonboard820c: use correct bindings for clocks
Don't use hardcoded clock IDs, use the IDs from the dt-bindings to be
compatible with upstream.
Taken from kernel tag v6.7
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
arch/arm/dts/dragonboard820c.dts | 5 +++--
drivers/clk/qcom/clock-apq8096.c | 5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
index 86b7f83d36d6..282c37e28f42 100644
--- a/arch/arm/dts/dragonboard820c.dts
+++ b/arch/arm/dts/dragonboard820c.dts
@@ -8,6 +8,7 @@
/dts-v1/;
#include "skeleton64.dtsi"
+#include
/ {
model = "Qualcomm Technologies, Inc. DB820c";
@@ -78,7 +79,7 @@
blsp2_uart2: serial@75b {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x75b 0x1000>;
- clocks = <&gcc 4>;
+ clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>;
clock-names = "core";
pinctrl-names = "uart";
pinctrl-0 = <&blsp8_uart>;
@@ -89,7 +90,7 @@
reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
index = <0x0>;
bus-width = <4>;
- clock = <&gcc 0>;
+ clock = <&gcc GCC_SDCC1_APPS_CLK>;
clock-frequency = <2>;
};
diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
index 1e6fdb5cd42d..a4731613c5e0 100644
--- a/drivers/clk/qcom/clock-apq8096.c
+++ b/drivers/clk/qcom/clock-apq8096.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include "clock-qcom.h"
@@ -107,10 +108,10 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong
rate)
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
- case 0: /* SDC1 */
+ case GCC_SDCC1_APPS_CLK: /* SDC1 */
return clk_init_sdc(priv, rate);
break;
- case 4: /*UART2*/
+ case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/
return clk_init_uart(priv);
default:
return 0;
--
2.43.1
[PATCH v4 37/39] dt-bindings: import headers for qcs404
Import the headers needed for QCS404-evb. Taken from kernel tag v6.7 Reviewed-by: Neil Armstrong Signed-off-by: Caleb Connolly --- include/dt-bindings/clock/qcom,turingcc-qcs404.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/include/dt-bindings/clock/qcom,turingcc-qcs404.h b/include/dt-bindings/clock/qcom,turingcc-qcs404.h new file mode 100644 index ..838faef57c67 --- /dev/null +++ b/include/dt-bindings/clock/qcom,turingcc-qcs404.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019, Linaro Ltd + */ + +#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H +#define _DT_BINDINGS_CLK_TURING_QCS404_H + +#define TURING_Q6SS_Q6_AXIM_CLK0 +#define TURING_Q6SS_AHBM_AON_CLK 1 +#define TURING_WRAPPER_AON_CLK 2 +#define TURING_Q6SS_AHBS_AON_CLK 3 +#define TURING_WRAPPER_QOS_AHBS_AON_CLK4 + +#endif -- 2.43.1
[PATCH v4 33/39] dt-bindings: import headers for MSM8996
Import dt-binding headers for MSM8996/APQ8096 from Linux. Taken from kernel tag v6.7 Reviewed-by: Neil Armstrong Signed-off-by: Caleb Connolly --- include/dt-bindings/clock/qcom,gcc-msm8996.h | 362 + include/dt-bindings/clock/qcom,mmcc-msm8996.h | 295 + .../dt-bindings/interconnect/qcom,msm8996-cbf.h| 12 + include/dt-bindings/interconnect/qcom,msm8996.h| 163 ++ include/dt-bindings/sound/qcom,wcd9335.h | 15 + 5 files changed, 847 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h new file mode 100644 index ..ddfd6fd73081 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h @@ -0,0 +1,362 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H +#define _DT_BINDINGS_CLK_MSM_GCC_8996_H + +#define GPLL0_EARLY0 +#define GPLL0 1 +#define GPLL1_EARLY2 +#define GPLL1 3 +#define GPLL2_EARLY4 +#define GPLL2 5 +#define GPLL3_EARLY6 +#define GPLL3 7 +#define GPLL4_EARLY8 +#define GPLL4 9 +#define SYSTEM_NOC_CLK_SRC 10 +/* U-Boot: KConfig check in CI erroneously picks this up, it's unused + * anyway so comment it out for now + */ +//#define CONFIG _NOC_CLK_SRC 11 +#define PERIPH_NOC_CLK_SRC 12 +#define MMSS_BIMC_GFX_CLK_SRC 13 +#define USB30_MASTER_CLK_SRC 14 +#define USB30_MOCK_UTMI_CLK_SRC15 +#define USB3_PHY_AUX_CLK_SRC 16 +#define USB20_MASTER_CLK_SRC 17 +#define USB20_MOCK_UTMI_CLK_SRC18 +#define SDCC1_APPS_CLK_SRC 19 +#define SDCC1_ICE_CORE_CLK_SRC 20 +#define SDCC2_APPS_CLK_SRC 21 +#define SDCC3_APPS_CLK_SRC 22 +#define SDCC4_APPS_CLK_SRC 23 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC24 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC25 +#define BLSP1_UART1_APPS_CLK_SRC 26 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC27 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC28 +#define BLSP1_UART2_APPS_CLK_SRC 29 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC30 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC31 +#define BLSP1_UART3_APPS_CLK_SRC 32 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC33 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC34 +#define BLSP1_UART4_APPS_CLK_SRC 35 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC36 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC37 +#define BLSP1_UART5_APPS_CLK_SRC 38 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC39 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC40 +#define BLSP1_UART6_APPS_CLK_SRC 41 +#define BLSP2_QUP1_SPI_APPS_CLK_SRC42 +#define BLSP2_QUP1_I2C_APPS_CLK_SRC43 +#define BLSP2_UART1_APPS_CLK_SRC 44 +#define BLSP2_QUP2_SPI_APPS_CLK_SRC45 +#define BLSP2_QUP2_I2C_APPS_CLK_SRC46 +#define BLSP2_UART2_APPS_CLK_SRC 47 +#define BLSP2_QUP3_SPI_APPS_CLK_SRC48 +#define BLSP2_QUP3_I2C_APPS_CLK_SRC49 +#define BLSP2_UART3_APPS_CLK_SRC 50 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC51 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC52 +#define BLSP2_UART4_APPS_CLK_SRC 53 +#define BLSP2_QUP5_SPI_APPS_CLK_SRC54 +#define BLSP2_QUP5_I2C_APPS_CLK_SRC55 +#define BLSP2_UART5_APPS_CLK_SRC 56 +#define BLSP2_QUP6_SPI_APPS_CLK_SRC57 +#define BL
[PATCH v4 32/39] dts: msm8916: replace with upstream DTS
Drop the U-Boot specific dragonboard410c.dts in favour of the upstream
msm8916-sbc.dts. No additional changes are needed to this DTS for U-Boot
support.
Taken from kernel tag v6.7
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
arch/arm/dts/Makefile |2 +-
arch/arm/dts/apq8016-sbc-u-boot.dtsi| 20 +
arch/arm/dts/apq8016-sbc.dts| 729 +
arch/arm/dts/dragonboard410c-uboot.dtsi | 44 -
arch/arm/dts/dragonboard410c.dts| 221 ---
arch/arm/dts/msm8916.dtsi | 2702 +++
configs/dragonboard410c_defconfig |2 +-
7 files changed, 3453 insertions(+), 267 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3f4e49b3e445..9ba1a94da5d0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -631,7 +631,7 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
-dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb \
+dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \
dragonboard820c.dtb \
sdm845-db845c.dtb \
sdm845-samsung-starqltechn.dtb \
diff --git a/arch/arm/dts/apq8016-sbc-u-boot.dtsi
b/arch/arm/dts/apq8016-sbc-u-boot.dtsi
new file mode 100644
index ..585d54d29623
--- /dev/null
+++ b/arch/arm/dts/apq8016-sbc-u-boot.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024, Linaro Ltd.
+ */
+
+/ {
+ /* When running as a first-stage bootloader this isn't filled in
automatically */
+ memory@8000 {
+ reg = <0 0x8000 0 0x3da0>;
+ };
+};
+
+/*
+ * When running as a first-stage bootloader, we need to re-configure the UART
pins
+ * because SBL de-initialises them. Indicate that the UART pins should be
configured
+ * during all boot stages.
+ */
+&blsp_uart2_default {
+ bootph-all;
+};
diff --git a/arch/arm/dts/apq8016-sbc.dts b/arch/arm/dts/apq8016-sbc.dts
new file mode 100644
index ..9ffad7d1f2b6
--- /dev/null
+++ b/arch/arm/dts/apq8016-sbc.dts
@@ -0,0 +1,729 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "msm8916-pm8916.dtsi"
+#include
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ model = "Qualcomm Technologies, Inc. APQ 8016 SBC";
+ compatible = "qcom,apq8016-sbc", "qcom,apq8016";
+
+ aliases {
+ mmc0 = &sdhc_1; /* eMMC */
+ mmc1 = &sdhc_2; /* SD card */
+ serial0 = &blsp_uart2;
+ serial1 = &blsp_uart1;
+ usid0 = &pm8916_0;
+ i2c0 = &blsp_i2c2;
+ i2c1 = &blsp_i2c6;
+ i2c3 = &blsp_i2c4;
+ spi0 = &blsp_spi5;
+ spi1 = &blsp_spi3;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ reserved-memory {
+ ramoops@bff0 {
+ compatible = "ramoops";
+ reg = <0x0 0xbff0 0x0 0x10>;
+
+ record-size = <0x2>;
+ console-size = <0x2>;
+ ftrace-size = <0x2>;
+ };
+ };
+
+ usb2513 {
+ compatible = "smsc,usb3503";
+ reset-gpios = <&pm8916_gpios 3 GPIO_ACTIVE_LOW>;
+ initial-mode = <1>;
+ };
+
+ usb_id: usb-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_id_default>;
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <&adv7533_out>;
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&msm_key_volp_n_default>;
+
+ button {
+ label = "Volume Up";
+ linux,code = ;
+ gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&tlmm_leds>,
+ <&pm8916_gpios_leds>,
+ <&pm8916_mpps_leds>;
+
+ compatible = "gpio-leds";
+
+ led@1 {
+ label = "apq8016-sbc:green:user1";
+ function = LED_FUNCTION_HEARTBEAT;
+ color = ;
+ gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-st
[PATCH v4 38/39] dts: qcs404-evb: replace with upstream DT
Drop the U-Boot specific DTS in favour of upstream. We'll only include
the -4000 variant as that is what U-Boot already supported.
Taken from kernel tag v6.7
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
arch/arm/dts/Makefile|2 +-
arch/arm/dts/pms405.dtsi | 149 +++
arch/arm/dts/qcs404-evb-4000-u-boot.dtsi | 48 +
arch/arm/dts/qcs404-evb-4000.dts | 96 ++
arch/arm/dts/qcs404-evb-uboot.dtsi | 30 -
arch/arm/dts/qcs404-evb.dts | 390 ---
arch/arm/dts/qcs404-evb.dtsi | 389 +++
arch/arm/dts/qcs404.dtsi | 1829 ++
8 files changed, 2512 insertions(+), 421 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 54aaf022c2eb..c4f0873dbb1f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -635,7 +635,7 @@ dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \
apq8096-db820c.dtb \
sdm845-db845c.dtb \
sdm845-samsung-starqltechn.dtb \
- qcs404-evb.dtb
+ qcs404-evb-4000.dtb
dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
diff --git a/arch/arm/dts/pms405.dtsi b/arch/arm/dts/pms405.dtsi
new file mode 100644
index ..461ad97032f7
--- /dev/null
+++ b/arch/arm/dts/pms405.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, Linaro Limited
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ thermal-zones {
+ pms405-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&pms405_temp>;
+
+ trips {
+ pms405_alert0: pms405-alert0 {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ pms405_crit: pms405-crit {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus {
+ pms405_0: pms405@0 {
+ compatible = "qcom,pms405", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pms405_gpios: gpio@c000 {
+ compatible = "qcom,pms405-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ gpio-ranges = <&pms405_gpios 0 0 12>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pon@800 {
+ compatible = "qcom,pms405-pon";
+ reg = <0x0800>;
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
+
+ pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = ;
+ };
+ };
+
+ pms405_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pms405_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pms405_adc: adc@3100 {
+ compatible = "qcom,pms405-adc", "qcom,spmi-adc-rev2";
+ reg = <0x3100>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ channel@0 {
+ reg = ;
+ qcom,pre-scaling = <1 1>;
+ label = "ref_gnd";
+ };
+
+ channel@1 {
+ reg = ;
+ qcom,pre-scaling = <1 1>;
+ label = "vref_1p25";
+ };
+
+ channel@131 {
+ reg = ;
+ qcom,pre-scaling = <1 3>;
+ label = "vph_pwr";
+
[PATCH v4 39/39] MAINTAINERS: Qualcomm: add some missing paths
Add drivers and DTS files, as well as regex matches for qcom/qualcomm/snapdragon. Reviewed-by: Neil Armstrong Signed-off-by: Caleb Connolly --- MAINTAINERS | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 46ba17647f3e..8b048b1faf7c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -576,18 +576,22 @@ M:Caleb Connolly M: Neil Armstrong R: Sumit Garg S: Maintained -F: arch/arm/mach-snapdragon/ -F: drivers/button/button-qcom-pmic.c -F: drivers/clk/qcom/ +F: arch/arm/dts/msm8*.dtsi +F: arch/arm/dts/pm8???.dtsi +F: arch/arm/dts/pms405.dtsi +F: arch/arm/dts/sdm845.dtsi +F: drivers/*/*/pm8???-* F: drivers/gpio/msm_gpio.c F: drivers/mmc/msm_sdhci.c F: drivers/phy/msm8916-usbh-phy.c -F: drivers/pinctrl/qcom/ F: drivers/serial/serial_msm.c F: drivers/serial/serial_msm_geni.c F: drivers/smem/msm_smem.c F: drivers/spmi/spmi-msm.c F: drivers/usb/host/ehci-msm.c +N: qcom +N: snapdragon +N: qualcomm ARM STI M: Patrice Chotard -- 2.43.1
[PATCH v4 36/39] dts: msm8996: replace with upstream DTS
Drop the U-Boot specific dragonboard820c.dts file in favour of the
upstream apq8096-db820c.dts and an additional -u-boot.dtsi with the
U-Boot specific additions.
Taken from kernel tag v6.7
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
arch/arm/dts/Makefile |2 +-
arch/arm/dts/apq8096-db820c-u-boot.dtsi | 14 +
arch/arm/dts/apq8096-db820c.dts | 1137 +
arch/arm/dts/dragonboard820c-uboot.dtsi | 32 -
arch/arm/dts/dragonboard820c.dts| 153 --
arch/arm/dts/msm8996.dtsi | 3884 +++
configs/dragonboard820c_defconfig |2 +-
7 files changed, 5037 insertions(+), 187 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9ba1a94da5d0..54aaf022c2eb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -632,7 +632,7 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \
- dragonboard820c.dtb \
+ apq8096-db820c.dtb \
sdm845-db845c.dtb \
sdm845-samsung-starqltechn.dtb \
qcs404-evb.dtb
diff --git a/arch/arm/dts/apq8096-db820c-u-boot.dtsi
b/arch/arm/dts/apq8096-db820c-u-boot.dtsi
new file mode 100644
index ..be61ea262b90
--- /dev/null
+++ b/arch/arm/dts/apq8096-db820c-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024, Linaro Ltd.
+ */
+
+/ {
+ /* Ensure that the fdtfile variable is generated properly */
+ compatible = "qcom,apq8096-db820c", "qcom,apq8096";
+};
+
+&sdhc2 {
+ status = "okay";
+ clock-frequency = <1>;
+};
diff --git a/arch/arm/dts/apq8096-db820c.dts b/arch/arm/dts/apq8096-db820c.dts
new file mode 100644
index ..e8148b3d6c50
--- /dev/null
+++ b/arch/arm/dts/apq8096-db820c.dts
@@ -0,0 +1,1137 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "msm8996.dtsi"
+#include "pm8994.dtsi"
+#include "pmi8994.dtsi"
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * GPIO name legend: proper name = the GPIO line is used as GPIO
+ * NC = not connected (pin out but not routed from the chip to
+ * anything the board)
+ * "[PER]" = pin is muxed for [peripheral] (not GPIO)
+ * LSEC= Low Speed External Connector
+ * P HSEC = Primary High Speed External Connector
+ * S HSEC = Secondary High Speed External Connector
+ * J14 = Camera Connector
+ * TP = Test Points
+ *
+ * Line names are taken from the schematic "DragonBoard 820c",
+ * drawing no: LM25-P2751-1
+ *
+ * For the lines routed to the external connectors the
+ * lines are named after the 96Boards CE Specification 1.0,
+ * Appendix "Expansion Connector Signal Description".
+ *
+ * When the 96Board naming of a line and the schematic name of
+ * the same line are in conflict, the 96Board specification
+ * takes precedence, which means that the external UART on the
+ * LSEC is named UART0 while the schematic and SoC names this
+ * UART3. This is only for the informational lines i.e. "[FOO]",
+ * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
+ * ones actually used for GPIO.
+ */
+
+/ {
+ model = "Qualcomm Technologies, Inc. DB820c";
+ compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
+
+ aliases {
+ serial0 = &blsp2_uart2;
+ serial1 = &blsp2_uart3;
+ serial2 = &blsp1_uart2;
+ i2c0 = &blsp1_i2c3;
+ i2c1 = &blsp2_i2c1;
+ i2c2 = &blsp2_i2c1;
+ spi0 = &blsp1_spi1;
+ spi1 = &blsp2_spi6;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ div1_mclk: divclk1 {
+ compatible = "gpio-gate-clock";
+ pinctrl-0 = <&audio_mclk>;
+ pinctrl-names = "default";
+ clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
+ #clock-cells = <0>;
+ enable-gpios = <&pm8994_gpios 15 0>;
+ };
+
+ divclk4: divclk4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "divclk4";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&divclk4_pin_a>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&volume_up_gpio>;
+
+ button {
+ label = "Volume Up";
+ linux,code = ;
+ gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ usb2_id: usb2-
[PATCH 2/2] doc: Rework the gcc section to reflect general build instructions
The first big issue is that the "gcc" file talked a lot about the
general build requirements as well, but was titled in a gcc-centric
manner. Solve this by renaming the file to compile.rst and more fully
reflecting that it is general build instructions. Next, add a section
about the prebuilt toolchains that are recommended (as they are the ones
we use in CI), and update a few places to reference these vendor-neutral
tools.
Next, we can include the reproducible builds section directly in the
compile instructions rather than as a small standalone file.
Finally, we update the sandbox document to reflect both the name change
as well as what is specifically required to build sandbox.
Signed-off-by: Tom Rini
---
Cc: Heinrich Schuchardt
---
doc/arch/sandbox/sandbox.rst | 5 ++-
doc/build/{gcc.rst => compile.rst} | 64 ++
doc/build/index.rst| 3 +-
doc/build/reproducible.rst | 27 -
4 files changed, 61 insertions(+), 38 deletions(-)
rename doc/build/{gcc.rst => compile.rst} (73%)
delete mode 100644 doc/build/reproducible.rst
diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst
index 5f8db126657f..f2ed5a25c115 100644
--- a/doc/arch/sandbox/sandbox.rst
+++ b/doc/arch/sandbox/sandbox.rst
@@ -39,11 +39,12 @@ integers can only be built on 64-bit hosts.
Note that standalone/API support is not available at present.
-
Prerequisites
-
-Install the dependencies noted in :doc:`../../build/gcc`.
+In addition to the normal dependencies shows in the :doc:`general build
+instructions <../../build/compile>` to enable display support SDL2 libraries
+need to be available.
Basic Operation
diff --git a/doc/build/gcc.rst b/doc/build/compile.rst
similarity index 73%
rename from doc/build/gcc.rst
rename to doc/build/compile.rst
index 3c6465772729..ef9c8545835a 100644
--- a/doc/build/gcc.rst
+++ b/doc/build/compile.rst
@@ -1,11 +1,19 @@
-Building with GCC
-=
+Building U-Boot
+===
Dependencies
-For building U-Boot you need a GCC compiler for your host platform. If you
-are not building on the target platform you further need a GCC cross compiler.
+For building U-Boot you need the general build tools such as `make` and a C
+compiler for your host platform. Next, if you are not building on the same
+architecture as the target platform you further need a C cross compiler.
+Furthermore, some target platforms require additional host tools to be present
+and their package names may vary slightly dependinng on the naming scheme used
+by a particular host OS.
+
+In general, GCC should be used for both the host and target C compiler. Using
+:doc:`clang ` is supported but please see the documented issues for it
as
+well.
Debian based
@@ -69,6 +77,17 @@ Depending on the build target further packages may be needed:
* riscv64 S-mode targets: opensbi
* some arm64 targets: arm-trusted-firmware
+Prebuilt
+
+
+Another option, which the project uses for CI for example, is to use a prebuilt
+toolchain. For the most part, we use the latest `kernel.org`_ prebuit binaries,
+but there are a few architectures that require their own specific toolchains
+still.
+
+In general, examples found within the documentation here refer to the tools
+found here and exceptions will be noted where relevant.
+
Prerequisites
-
@@ -112,11 +131,11 @@ command line or export it beforehand.
CROSS_COMPILE= make
-Assuming cross compiling on Debian for ARMv8 this would be
+Assuming cross compiling for ARMv8 this would be
.. code-block:: bash
-CROSS_COMPILE=aarch64-linux-gnu- make
+CROSS_COMPILE=aarch64-linux- make
Build parameters
@@ -131,13 +150,40 @@ You can speed up compilation by parallelization using the
-j parameter, e.g.
.. code-block:: bash
-CROSS_COMPILE=aarch64-linux-gnu- make -j$(nproc)
+CROSS_COMPILE=aarch64-linux- make -j$(nproc)
Further important build parameters are
* O= - generate all output files in directory , including .config
* V=1 - verbose build
+
+Reproducible builds
+~~~
+
+In order to achieve reproducible builds, timestamps used in the U-Boot build
+process have to be set to a fixed value.
+
+This is done using the SOURCE_DATE_EPOCH environment variable which specifies
+the number of seconds since 1970-01-01T00:00:00Z.
+
+
+To build the sandbox with 2023-01-01T00:00:00Z as timestamp we can use:
+
+.. code-block:: bash
+
+make sandbox_defconfig
+SOURCE_DATE_EPOCH=1672531200 make
+
+This date is shown when we launch U-Boot:
+
+.. code-block:: console
+
+./u-boot -T
+U-Boot 2023.01 (Jan 01 2023 - 00:00:00 +)
+
+The same effect can be obtained with buildman using the `-r` flag.
+
Devicetree compiler
~~~
@@ -176,6 +222,8 @@ builds during development, you can disable it by setting
`NO_LTO` to `1`.
NO_LTO=1 make
+Note that
[PATCH 1/2] doc: Update our clang documentation to reflect current status
First, since this document was written the biggest challenges at the time are simply not applicable anymore. Second, we need to list the challenges which are preventing more platforms from being able to be built with Clang today. Next, we update the general wording to be host distribution agnostic. Finally, the section about xenguest_arm64 issues is not present anymore. Signed-off-by: Tom Rini --- Cc: Mark Kettenis This does leave the FreeBSD section unchanged and should likely be looked at again by someone with a BSD build machine available. --- doc/build/clang.rst | 85 +++-- 1 file changed, 21 insertions(+), 64 deletions(-) diff --git a/doc/build/clang.rst b/doc/build/clang.rst index 09bb988e9236..d8c554982567 100644 --- a/doc/build/clang.rst +++ b/doc/build/clang.rst @@ -1,34 +1,27 @@ Building with Clang === -The biggest problem when trying to compile U-Boot with Clang is that almost all -archs rely on storing gd in a global register and the Clang 3.5 user manual -states: "Clang does not support global register variables; this is unlikely to -be implemented soon because it requires additional LLVM backend support." - -The ARM backend can be instructed not to use the r9 and x18 registers using --ffixed-r9 or -ffixed-x18 respectively. As global registers themselves are not -supported inline assembly is needed to get and set the r9 or x18 value. This -leads to larger code then strictly necessary, but at least works. - -Debian based - - -Required packages can be installed via apt, e.g. - -.. code-block:: bash - -sudo apt-get install clang - -We make use of the CROSS_COMPILE variable to derive the build target which is -passed as the --target parameter to clang. - -The CROSS_COMPILE variable further determines the paths to other build -tools. As assembler we use the binary pointed to by '$(CROSS_COMPILE)as' -instead of the LLVM integrated assembler (IAS). - -Here is an example demonstrating building U-Boot for the Raspberry Pi 2 -using clang: +In general terms, U-Boot support building with Clang as the C compiler and +building and booting our "sandbox" target is part of CI. + +There are however some specific issues that need to be addressed to fully +support building with Clang on all targets. + +* Given the issue reported in https://github.com/llvm/llvm-project/issues/78778 + currently one has to configure the build first with GCC. +* Support for passing the correct flags along to `$(CPP)` needs to be + backported from the Linux Kernel. +* Support for using Clang as the linker is required to support the LTO feature + which some platforms require in order to create an appropriately small + binary. + +In general, when building with Clang we make use of the CROSS_COMPILE variable +to derive the build target which is passed as the --target parameter to clang. +The CROSS_COMPILE variable further determines the paths to other build tools. +As assembler we use the binary pointed to by '$(CROSS_COMPILE)as' instead of +the LLVM integrated assembler (IAS). After installing clang as per the +instructions for your specific distribution, in order to build for example the +Raspberry Pi 2 using clang: .. code-block:: bash @@ -72,39 +65,3 @@ simplified with a simple wrapper script - saved as #!/bin/sh exec clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd "$@" - - -Known Issues - - -When build U-boot for `xenguest_arm64_defconfig` target, it reports linkage -error: - -.. code-block:: bash - -aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `do_hypervisor_callback': -/home/leoy/Dev2/u-boot/drivers/xen/hypervisor.c:188: undefined reference to `__aarch64_swp8_acq_rel' -aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_set_bit': -/home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:40: undefined reference to `__aarch64_ldset1_acq_rel' -aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_clear_bit': -/home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel' -aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_set_bit': -/home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:40: undefined reference to `__aarch64_ldset1_acq_rel' -aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_clear_bit': -/home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel' -aarch64-linux-gnu-ld.bfd: drivers/xen/events.o: in function `synch_test_and_clear_bit': -/home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel' -aarch64-linux-gnu-ld.bfd: drivers/xen/events.o: in function `synch_test_and_set_bit': -/home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:4
Re: [PATCH 2/2] doc: Rework the gcc section to reflect general build instructions
Am 15. Februar 2024 22:10:25 MEZ schrieb Tom Rini :
>The first big issue is that the "gcc" file talked a lot about the
>general build requirements as well, but was titled in a gcc-centric
>manner. Solve this by renaming the file to compile.rst and more fully
>reflecting that it is general build instructions. Next, add a section
>about the prebuilt toolchains that are recommended (as they are the ones
>we use in CI), and update a few places to reference these vendor-neutral
>tools.
>
>Next, we can include the reproducible builds section directly in the
>compile instructions rather than as a small standalone file.
>
>Finally, we update the sandbox document to reflect both the name change
>as well as what is specifically required to build sandbox.
>
>Signed-off-by: Tom Rini
>---
>Cc: Heinrich Schuchardt
>---
> doc/arch/sandbox/sandbox.rst | 5 ++-
> doc/build/{gcc.rst => compile.rst} | 64 ++
> doc/build/index.rst| 3 +-
> doc/build/reproducible.rst | 27 -
> 4 files changed, 61 insertions(+), 38 deletions(-)
> rename doc/build/{gcc.rst => compile.rst} (73%)
> delete mode 100644 doc/build/reproducible.rst
>
>diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst
>index 5f8db126657f..f2ed5a25c115 100644
>--- a/doc/arch/sandbox/sandbox.rst
>+++ b/doc/arch/sandbox/sandbox.rst
>@@ -39,11 +39,12 @@ integers can only be built on 64-bit hosts.
>
> Note that standalone/API support is not available at present.
>
>-
> Prerequisites
> -
>
>-Install the dependencies noted in :doc:`../../build/gcc`.
>+In addition to the normal dependencies shows in the :doc:`general build
>+instructions <../../build/compile>` to enable display support SDL2 libraries
>+need to be available.
>
>
> Basic Operation
>diff --git a/doc/build/gcc.rst b/doc/build/compile.rst
>similarity index 73%
>rename from doc/build/gcc.rst
>rename to doc/build/compile.rst
>index 3c6465772729..ef9c8545835a 100644
>--- a/doc/build/gcc.rst
>+++ b/doc/build/compile.rst
>@@ -1,11 +1,19 @@
>-Building with GCC
>-=
>+Building U-Boot
>+===
>
> Dependencies
>
>
>-For building U-Boot you need a GCC compiler for your host platform. If you
>-are not building on the target platform you further need a GCC cross
>compiler.
>+For building U-Boot you need the general build tools such as `make` and a C
>+compiler for your host platform. Next, if you are not building on the same
>+architecture as the target platform you further need a C cross compiler.
>+Furthermore, some target platforms require additional host tools to be present
>+and their package names may vary slightly dependinng on the naming scheme used
>+by a particular host OS.
>+
>+In general, GCC should be used for both the host and target C compiler. Using
>+:doc:`clang ` is supported but please see the documented issues for it
>as
>+well.
>
> Debian based
>
>@@ -69,6 +77,17 @@ Depending on the build target further packages may be
>needed:
> * riscv64 S-mode targets: opensbi
> * some arm64 targets: arm-trusted-firmware
>
>+Prebuilt
>+
>+
>+Another option, which the project uses for CI for example, is to use a
>prebuilt
>+toolchain. For the most part, we use the latest `kernel.org`_ prebuit
>binaries,
>+but there are a few architectures that require their own specific toolchains
>+still.
>+
>+In general, examples found within the documentation here refer to the tools
>+found here and exceptions will be noted where relevant.
>+
> Prerequisites
> -
>
>@@ -112,11 +131,11 @@ command line or export it beforehand.
>
> CROSS_COMPILE= make
>
>-Assuming cross compiling on Debian for ARMv8 this would be
>+Assuming cross compiling for ARMv8 this would be
>
> .. code-block:: bash
>
>-CROSS_COMPILE=aarch64-linux-gnu- make
>+CROSS_COMPILE=aarch64-linux- make
GCC uses triples to specify the architecture. With the suggested change
building will fail on many distros, e.g. in our CI image.
cf. https://gcc.gnu.org/install/specific.html#aarch64-x-x
>
> Build parameters
>
>@@ -131,13 +150,40 @@ You can speed up compilation by parallelization using
>the -j parameter, e.g.
>
> .. code-block:: bash
>
>-CROSS_COMPILE=aarch64-linux-gnu- make -j$(nproc)
>+CROSS_COMPILE=aarch64-linux- make -j$(nproc)
ditto
Best regards
Heinrich
>
> Further important build parameters are
>
> * O= - generate all output files in directory , including .config
> * V=1 - verbose build
>
>+
>+Reproducible builds
>+~~~
>+
>+In order to achieve reproducible builds, timestamps used in the U-Boot build
>+process have to be set to a fixed value.
>+
>+This is done using the SOURCE_DATE_EPOCH environment variable which specifies
>+the number of seconds since 1970-01-01T00:00:00Z.
>+
>+
>+To build the sandbox with 2023-01-01T00:00:00Z as timestamp we can use:
>+
>+.. code-block:: bash
>+
>+make sandbox_defconfig
Re: [PATCH 2/2] doc: Rework the gcc section to reflect general build instructions
On Thu, Feb 15, 2024 at 10:24:40PM +0100, Heinrich Schuchardt wrote:
>
>
> Am 15. Februar 2024 22:10:25 MEZ schrieb Tom Rini :
> >The first big issue is that the "gcc" file talked a lot about the
> >general build requirements as well, but was titled in a gcc-centric
> >manner. Solve this by renaming the file to compile.rst and more fully
> >reflecting that it is general build instructions. Next, add a section
> >about the prebuilt toolchains that are recommended (as they are the ones
> >we use in CI), and update a few places to reference these vendor-neutral
> >tools.
> >
> >Next, we can include the reproducible builds section directly in the
> >compile instructions rather than as a small standalone file.
> >
> >Finally, we update the sandbox document to reflect both the name change
> >as well as what is specifically required to build sandbox.
> >
> >Signed-off-by: Tom Rini
> >---
> >Cc: Heinrich Schuchardt
> >---
> > doc/arch/sandbox/sandbox.rst | 5 ++-
> > doc/build/{gcc.rst => compile.rst} | 64 ++
> > doc/build/index.rst| 3 +-
> > doc/build/reproducible.rst | 27 -
> > 4 files changed, 61 insertions(+), 38 deletions(-)
> > rename doc/build/{gcc.rst => compile.rst} (73%)
> > delete mode 100644 doc/build/reproducible.rst
> >
> >diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst
> >index 5f8db126657f..f2ed5a25c115 100644
> >--- a/doc/arch/sandbox/sandbox.rst
> >+++ b/doc/arch/sandbox/sandbox.rst
> >@@ -39,11 +39,12 @@ integers can only be built on 64-bit hosts.
> >
> > Note that standalone/API support is not available at present.
> >
> >-
> > Prerequisites
> > -
> >
> >-Install the dependencies noted in :doc:`../../build/gcc`.
> >+In addition to the normal dependencies shows in the :doc:`general build
> >+instructions <../../build/compile>` to enable display support SDL2 libraries
> >+need to be available.
> >
> >
> > Basic Operation
> >diff --git a/doc/build/gcc.rst b/doc/build/compile.rst
> >similarity index 73%
> >rename from doc/build/gcc.rst
> >rename to doc/build/compile.rst
> >index 3c6465772729..ef9c8545835a 100644
> >--- a/doc/build/gcc.rst
> >+++ b/doc/build/compile.rst
> >@@ -1,11 +1,19 @@
> >-Building with GCC
> >-=
> >+Building U-Boot
> >+===
> >
> > Dependencies
> >
> >
> >-For building U-Boot you need a GCC compiler for your host platform. If you
> >-are not building on the target platform you further need a GCC cross
> >compiler.
> >+For building U-Boot you need the general build tools such as `make` and a C
> >+compiler for your host platform. Next, if you are not building on the same
> >+architecture as the target platform you further need a C cross compiler.
> >+Furthermore, some target platforms require additional host tools to be
> >present
> >+and their package names may vary slightly dependinng on the naming scheme
> >used
> >+by a particular host OS.
> >+
> >+In general, GCC should be used for both the host and target C compiler.
> >Using
> >+:doc:`clang ` is supported but please see the documented issues for
> >it as
> >+well.
> >
> > Debian based
> >
> >@@ -69,6 +77,17 @@ Depending on the build target further packages may be
> >needed:
> > * riscv64 S-mode targets: opensbi
> > * some arm64 targets: arm-trusted-firmware
> >
> >+Prebuilt
> >+
> >+
> >+Another option, which the project uses for CI for example, is to use a
> >prebuilt
> >+toolchain. For the most part, we use the latest `kernel.org`_ prebuit
> >binaries,
> >+but there are a few architectures that require their own specific toolchains
> >+still.
> >+
> >+In general, examples found within the documentation here refer to the tools
> >+found here and exceptions will be noted where relevant.
> >+
> > Prerequisites
> > -
> >
> >@@ -112,11 +131,11 @@ command line or export it beforehand.
> >
> > CROSS_COMPILE= make
> >
> >-Assuming cross compiling on Debian for ARMv8 this would be
> >+Assuming cross compiling for ARMv8 this would be
> >
> > .. code-block:: bash
> >
> >-CROSS_COMPILE=aarch64-linux-gnu- make
> >+CROSS_COMPILE=aarch64-linux- make
>
> GCC uses triples to specify the architecture. With the suggested change
> building will fail on many distros, e.g. in our CI image.
>
> cf. https://gcc.gnu.org/install/specific.html#aarch64-x-x
But this is what the kernel.org compiler is called, and for consistency
we should reference the reference compiler in our docs. I'm wanting to
follow up and change everyone to use consistent names.
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH 2/2] doc: Rework the gcc section to reflect general build instructions
Am 15. Februar 2024 22:28:24 MEZ schrieb Tom Rini :
>On Thu, Feb 15, 2024 at 10:24:40PM +0100, Heinrich Schuchardt wrote:
>>
>>
>> Am 15. Februar 2024 22:10:25 MEZ schrieb Tom Rini :
>> >The first big issue is that the "gcc" file talked a lot about the
>> >general build requirements as well, but was titled in a gcc-centric
>> >manner. Solve this by renaming the file to compile.rst and more fully
>> >reflecting that it is general build instructions. Next, add a section
>> >about the prebuilt toolchains that are recommended (as they are the ones
>> >we use in CI), and update a few places to reference these vendor-neutral
>> >tools.
>> >
>> >Next, we can include the reproducible builds section directly in the
>> >compile instructions rather than as a small standalone file.
>> >
>> >Finally, we update the sandbox document to reflect both the name change
>> >as well as what is specifically required to build sandbox.
>> >
>> >Signed-off-by: Tom Rini
>> >---
>> >Cc: Heinrich Schuchardt
>> >---
>> > doc/arch/sandbox/sandbox.rst | 5 ++-
>> > doc/build/{gcc.rst => compile.rst} | 64 ++
>> > doc/build/index.rst| 3 +-
>> > doc/build/reproducible.rst | 27 -
>> > 4 files changed, 61 insertions(+), 38 deletions(-)
>> > rename doc/build/{gcc.rst => compile.rst} (73%)
>> > delete mode 100644 doc/build/reproducible.rst
>> >
>> >diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst
>> >index 5f8db126657f..f2ed5a25c115 100644
>> >--- a/doc/arch/sandbox/sandbox.rst
>> >+++ b/doc/arch/sandbox/sandbox.rst
>> >@@ -39,11 +39,12 @@ integers can only be built on 64-bit hosts.
>> >
>> > Note that standalone/API support is not available at present.
>> >
>> >-
>> > Prerequisites
>> > -
>> >
>> >-Install the dependencies noted in :doc:`../../build/gcc`.
>> >+In addition to the normal dependencies shows in the :doc:`general build
>> >+instructions <../../build/compile>` to enable display support SDL2
>> >libraries
>> >+need to be available.
>> >
>> >
>> > Basic Operation
>> >diff --git a/doc/build/gcc.rst b/doc/build/compile.rst
>> >similarity index 73%
>> >rename from doc/build/gcc.rst
>> >rename to doc/build/compile.rst
>> >index 3c6465772729..ef9c8545835a 100644
>> >--- a/doc/build/gcc.rst
>> >+++ b/doc/build/compile.rst
>> >@@ -1,11 +1,19 @@
>> >-Building with GCC
>> >-=
>> >+Building U-Boot
>> >+===
>> >
>> > Dependencies
>> >
>> >
>> >-For building U-Boot you need a GCC compiler for your host platform. If you
>> >-are not building on the target platform you further need a GCC cross
>> >compiler.
>> >+For building U-Boot you need the general build tools such as `make` and a C
>> >+compiler for your host platform. Next, if you are not building on the same
>> >+architecture as the target platform you further need a C cross compiler.
>> >+Furthermore, some target platforms require additional host tools to be
>> >present
>> >+and their package names may vary slightly dependinng on the naming scheme
>> >used
>> >+by a particular host OS.
>> >+
>> >+In general, GCC should be used for both the host and target C compiler.
>> >Using
>> >+:doc:`clang ` is supported but please see the documented issues for
>> >it as
>> >+well.
>> >
>> > Debian based
>> >
>> >@@ -69,6 +77,17 @@ Depending on the build target further packages may be
>> >needed:
>> > * riscv64 S-mode targets: opensbi
>> > * some arm64 targets: arm-trusted-firmware
>> >
>> >+Prebuilt
>> >+
>> >+
>> >+Another option, which the project uses for CI for example, is to use a
>> >prebuilt
>> >+toolchain. For the most part, we use the latest `kernel.org`_ prebuit
>> >binaries,
>> >+but there are a few architectures that require their own specific
>> >toolchains
>> >+still.
>> >+
>> >+In general, examples found within the documentation here refer to the tools
>> >+found here and exceptions will be noted where relevant.
>> >+
>> > Prerequisites
>> > -
>> >
>> >@@ -112,11 +131,11 @@ command line or export it beforehand.
>> >
>> > CROSS_COMPILE= make
>> >
>> >-Assuming cross compiling on Debian for ARMv8 this would be
>> >+Assuming cross compiling for ARMv8 this would be
>> >
>> > .. code-block:: bash
>> >
>> >-CROSS_COMPILE=aarch64-linux-gnu- make
>> >+CROSS_COMPILE=aarch64-linux- make
>>
>> GCC uses triples to specify the architecture. With the suggested change
>> building will fail on many distros, e.g. in our CI image.
>>
>> cf. https://gcc.gnu.org/install/specific.html#aarch64-x-x
>
>But this is what the kernel.org compiler is called, and for consistency
>we should reference the reference compiler in our docs. I'm wanting to
>follow up and change everyone to use consistent names.
>
Please, do not asume that Linux distros will change.
Users will and should use the tools provided by their distros. Side loading
foreign binaries is a secutity risc which should be avoid
Re: [PATCH 2/2] doc: Rework the gcc section to reflect general build instructions
On Thu, Feb 15, 2024 at 10:53:59PM +0100, Heinrich Schuchardt wrote:
>
>
> Am 15. Februar 2024 22:28:24 MEZ schrieb Tom Rini :
> >On Thu, Feb 15, 2024 at 10:24:40PM +0100, Heinrich Schuchardt wrote:
> >>
> >>
> >> Am 15. Februar 2024 22:10:25 MEZ schrieb Tom Rini :
> >> >The first big issue is that the "gcc" file talked a lot about the
> >> >general build requirements as well, but was titled in a gcc-centric
> >> >manner. Solve this by renaming the file to compile.rst and more fully
> >> >reflecting that it is general build instructions. Next, add a section
> >> >about the prebuilt toolchains that are recommended (as they are the ones
> >> >we use in CI), and update a few places to reference these vendor-neutral
> >> >tools.
> >> >
> >> >Next, we can include the reproducible builds section directly in the
> >> >compile instructions rather than as a small standalone file.
> >> >
> >> >Finally, we update the sandbox document to reflect both the name change
> >> >as well as what is specifically required to build sandbox.
> >> >
> >> >Signed-off-by: Tom Rini
> >> >---
> >> >Cc: Heinrich Schuchardt
> >> >---
> >> > doc/arch/sandbox/sandbox.rst | 5 ++-
> >> > doc/build/{gcc.rst => compile.rst} | 64 ++
> >> > doc/build/index.rst| 3 +-
> >> > doc/build/reproducible.rst | 27 -
> >> > 4 files changed, 61 insertions(+), 38 deletions(-)
> >> > rename doc/build/{gcc.rst => compile.rst} (73%)
> >> > delete mode 100644 doc/build/reproducible.rst
> >> >
> >> >diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst
> >> >index 5f8db126657f..f2ed5a25c115 100644
> >> >--- a/doc/arch/sandbox/sandbox.rst
> >> >+++ b/doc/arch/sandbox/sandbox.rst
> >> >@@ -39,11 +39,12 @@ integers can only be built on 64-bit hosts.
> >> >
> >> > Note that standalone/API support is not available at present.
> >> >
> >> >-
> >> > Prerequisites
> >> > -
> >> >
> >> >-Install the dependencies noted in :doc:`../../build/gcc`.
> >> >+In addition to the normal dependencies shows in the :doc:`general build
> >> >+instructions <../../build/compile>` to enable display support SDL2
> >> >libraries
> >> >+need to be available.
> >> >
> >> >
> >> > Basic Operation
> >> >diff --git a/doc/build/gcc.rst b/doc/build/compile.rst
> >> >similarity index 73%
> >> >rename from doc/build/gcc.rst
> >> >rename to doc/build/compile.rst
> >> >index 3c6465772729..ef9c8545835a 100644
> >> >--- a/doc/build/gcc.rst
> >> >+++ b/doc/build/compile.rst
> >> >@@ -1,11 +1,19 @@
> >> >-Building with GCC
> >> >-=
> >> >+Building U-Boot
> >> >+===
> >> >
> >> > Dependencies
> >> >
> >> >
> >> >-For building U-Boot you need a GCC compiler for your host platform. If
> >> >you
> >> >-are not building on the target platform you further need a GCC cross
> >> >compiler.
> >> >+For building U-Boot you need the general build tools such as `make` and
> >> >a C
> >> >+compiler for your host platform. Next, if you are not building on the
> >> >same
> >> >+architecture as the target platform you further need a C cross compiler.
> >> >+Furthermore, some target platforms require additional host tools to be
> >> >present
> >> >+and their package names may vary slightly dependinng on the naming
> >> >scheme used
> >> >+by a particular host OS.
> >> >+
> >> >+In general, GCC should be used for both the host and target C compiler.
> >> >Using
> >> >+:doc:`clang ` is supported but please see the documented issues
> >> >for it as
> >> >+well.
> >> >
> >> > Debian based
> >> >
> >> >@@ -69,6 +77,17 @@ Depending on the build target further packages may be
> >> >needed:
> >> > * riscv64 S-mode targets: opensbi
> >> > * some arm64 targets: arm-trusted-firmware
> >> >
> >> >+Prebuilt
> >> >+
> >> >+
> >> >+Another option, which the project uses for CI for example, is to use a
> >> >prebuilt
> >> >+toolchain. For the most part, we use the latest `kernel.org`_ prebuit
> >> >binaries,
> >> >+but there are a few architectures that require their own specific
> >> >toolchains
> >> >+still.
> >> >+
> >> >+In general, examples found within the documentation here refer to the
> >> >tools
> >> >+found here and exceptions will be noted where relevant.
> >> >+
> >> > Prerequisites
> >> > -
> >> >
> >> >@@ -112,11 +131,11 @@ command line or export it beforehand.
> >> >
> >> > CROSS_COMPILE= make
> >> >
> >> >-Assuming cross compiling on Debian for ARMv8 this would be
> >> >+Assuming cross compiling for ARMv8 this would be
> >> >
> >> > .. code-block:: bash
> >> >
> >> >-CROSS_COMPILE=aarch64-linux-gnu- make
> >> >+CROSS_COMPILE=aarch64-linux- make
> >>
> >> GCC uses triples to specify the architecture. With the suggested change
> >> building will fail on many distros, e.g. in our CI image.
> >>
> >> cf. https://gcc.gnu.org/install/specific.html#aarch64-x-x
> >
> >But this is what the kernel.org compil
Re: [PATCH 2/2] doc: Rework the gcc section to reflect general build instructions
Am 15. Februar 2024 23:00:32 MEZ schrieb Tom Rini :
>On Thu, Feb 15, 2024 at 10:53:59PM +0100, Heinrich Schuchardt wrote:
>>
>>
>> Am 15. Februar 2024 22:28:24 MEZ schrieb Tom Rini :
>> >On Thu, Feb 15, 2024 at 10:24:40PM +0100, Heinrich Schuchardt wrote:
>> >>
>> >>
>> >> Am 15. Februar 2024 22:10:25 MEZ schrieb Tom Rini :
>> >> >The first big issue is that the "gcc" file talked a lot about the
>> >> >general build requirements as well, but was titled in a gcc-centric
>> >> >manner. Solve this by renaming the file to compile.rst and more fully
>> >> >reflecting that it is general build instructions. Next, add a section
>> >> >about the prebuilt toolchains that are recommended (as they are the ones
>> >> >we use in CI), and update a few places to reference these vendor-neutral
>> >> >tools.
>> >> >
>> >> >Next, we can include the reproducible builds section directly in the
>> >> >compile instructions rather than as a small standalone file.
>> >> >
>> >> >Finally, we update the sandbox document to reflect both the name change
>> >> >as well as what is specifically required to build sandbox.
>> >> >
>> >> >Signed-off-by: Tom Rini
>> >> >---
>> >> >Cc: Heinrich Schuchardt
>> >> >---
>> >> > doc/arch/sandbox/sandbox.rst | 5 ++-
>> >> > doc/build/{gcc.rst => compile.rst} | 64 ++
>> >> > doc/build/index.rst| 3 +-
>> >> > doc/build/reproducible.rst | 27 -
>> >> > 4 files changed, 61 insertions(+), 38 deletions(-)
>> >> > rename doc/build/{gcc.rst => compile.rst} (73%)
>> >> > delete mode 100644 doc/build/reproducible.rst
>> >> >
>> >> >diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst
>> >> >index 5f8db126657f..f2ed5a25c115 100644
>> >> >--- a/doc/arch/sandbox/sandbox.rst
>> >> >+++ b/doc/arch/sandbox/sandbox.rst
>> >> >@@ -39,11 +39,12 @@ integers can only be built on 64-bit hosts.
>> >> >
>> >> > Note that standalone/API support is not available at present.
>> >> >
>> >> >-
>> >> > Prerequisites
>> >> > -
>> >> >
>> >> >-Install the dependencies noted in :doc:`../../build/gcc`.
>> >> >+In addition to the normal dependencies shows in the :doc:`general build
>> >> >+instructions <../../build/compile>` to enable display support SDL2
>> >> >libraries
>> >> >+need to be available.
>> >> >
>> >> >
>> >> > Basic Operation
>> >> >diff --git a/doc/build/gcc.rst b/doc/build/compile.rst
>> >> >similarity index 73%
>> >> >rename from doc/build/gcc.rst
>> >> >rename to doc/build/compile.rst
>> >> >index 3c6465772729..ef9c8545835a 100644
>> >> >--- a/doc/build/gcc.rst
>> >> >+++ b/doc/build/compile.rst
>> >> >@@ -1,11 +1,19 @@
>> >> >-Building with GCC
>> >> >-=
>> >> >+Building U-Boot
>> >> >+===
>> >> >
>> >> > Dependencies
>> >> >
>> >> >
>> >> >-For building U-Boot you need a GCC compiler for your host platform. If
>> >> >you
>> >> >-are not building on the target platform you further need a GCC cross
>> >> >compiler.
>> >> >+For building U-Boot you need the general build tools such as `make` and
>> >> >a C
>> >> >+compiler for your host platform. Next, if you are not building on the
>> >> >same
>> >> >+architecture as the target platform you further need a C cross compiler.
>> >> >+Furthermore, some target platforms require additional host tools to be
>> >> >present
>> >> >+and their package names may vary slightly dependinng on the naming
>> >> >scheme used
>> >> >+by a particular host OS.
>> >> >+
>> >> >+In general, GCC should be used for both the host and target C compiler.
>> >> >Using
>> >> >+:doc:`clang ` is supported but please see the documented issues
>> >> >for it as
>> >> >+well.
>> >> >
>> >> > Debian based
>> >> >
>> >> >@@ -69,6 +77,17 @@ Depending on the build target further packages may be
>> >> >needed:
>> >> > * riscv64 S-mode targets: opensbi
>> >> > * some arm64 targets: arm-trusted-firmware
>> >> >
>> >> >+Prebuilt
>> >> >+
>> >> >+
>> >> >+Another option, which the project uses for CI for example, is to use a
>> >> >prebuilt
>> >> >+toolchain. For the most part, we use the latest `kernel.org`_ prebuit
>> >> >binaries,
>> >> >+but there are a few architectures that require their own specific
>> >> >toolchains
>> >> >+still.
>> >> >+
>> >> >+In general, examples found within the documentation here refer to the
>> >> >tools
>> >> >+found here and exceptions will be noted where relevant.
>> >> >+
>> >> > Prerequisites
>> >> > -
>> >> >
>> >> >@@ -112,11 +131,11 @@ command line or export it beforehand.
>> >> >
>> >> > CROSS_COMPILE= make
>> >> >
>> >> >-Assuming cross compiling on Debian for ARMv8 this would be
>> >> >+Assuming cross compiling for ARMv8 this would be
>> >> >
>> >> > .. code-block:: bash
>> >> >
>> >> >-CROSS_COMPILE=aarch64-linux-gnu- make
>> >> >+CROSS_COMPILE=aarch64-linux- make
>> >>
>> >> GCC uses triples to specify the architecture. With the suggested c
[PATCH] efi_loader: Don't carve out memory reservations too early
Moving the efi_carve_out_dt_rsv() call in commit 1be415b21b2d
("efi_loader: create memory reservations in ACPI case")
broke boards that create additional memory reservations in
ft_board_setup() since it is now called before those additional
memory reservations are made. This is the case for the rk3588
boards and breaks booting OpenBSD on those boards.
Move the call back to its original location and add a call in
the code path used for ACPI.
Fixes: 1be415b21b2d ("efi_loader: create memory reservations in ACPI case")
Signed-off-by: Mark Kettenis
---
lib/efi_loader/efi_helper.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c
index 5dd9cc876e..58761fae78 100644
--- a/lib/efi_loader/efi_helper.c
+++ b/lib/efi_loader/efi_helper.c
@@ -456,11 +456,11 @@ efi_status_t efi_install_fdt(void *fdt)
return EFI_LOAD_ERROR;
}
- /* Create memory reservations as indicated by the device tree */
- efi_carve_out_dt_rsv(fdt);
-
- if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE))
+ if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)) {
+ /* Create memory reservations as indicated by the device tree */
+ efi_carve_out_dt_rsv(fdt);
return EFI_SUCCESS;
+ }
/* Prepare device tree for payload */
ret = copy_fdt(&fdt);
@@ -474,6 +474,9 @@ efi_status_t efi_install_fdt(void *fdt)
return EFI_LOAD_ERROR;
}
+ /* Create memory reservations as indicated by the device tree */
+ efi_carve_out_dt_rsv(fdt);
+
efi_try_purge_kaslr_seed(fdt);
if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) {
--
2.43.0
Re: [PATCH] efi_loader: Don't carve out memory reservations too early
Am 16. Februar 2024 00:25:34 MEZ schrieb Mark Kettenis :
>Moving the efi_carve_out_dt_rsv() call in commit 1be415b21b2d
>("efi_loader: create memory reservations in ACPI case")
>broke boards that create additional memory reservations in
>ft_board_setup() since it is now called before those additional
>memory reservations are made. This is the case for the rk3588
>boards and breaks booting OpenBSD on those boards.
>
>Move the call back to its original location and add a call in
>the code path used for ACPI.
>
>Fixes: 1be415b21b2d ("efi_loader: create memory reservations in ACPI case")
>Signed-off-by: Mark Kettenis
>---
> lib/efi_loader/efi_helper.c | 11 +++
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
>diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c
>index 5dd9cc876e..58761fae78 100644
>--- a/lib/efi_loader/efi_helper.c
>+++ b/lib/efi_loader/efi_helper.c
>@@ -456,11 +456,11 @@ efi_status_t efi_install_fdt(void *fdt)
> return EFI_LOAD_ERROR;
> }
>
>- /* Create memory reservations as indicated by the device tree */
>- efi_carve_out_dt_rsv(fdt);
>-
>- if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE))
>+ if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)) {
>+ /* Create memory reservations as indicated by the device tree */
Imagine booting the rk3588 board with ACPI. Wouldn't we miss creating the
ft_board_setup() reservations before efi_carve_out_dt_rsv(fdt)?
Best regards
Heinrich
>+ efi_carve_out_dt_rsv(fdt);
> return EFI_SUCCESS;
>+ }
>
> /* Prepare device tree for payload */
> ret = copy_fdt(&fdt);
>@@ -474,6 +474,9 @@ efi_status_t efi_install_fdt(void *fdt)
> return EFI_LOAD_ERROR;
> }
>
>+ /* Create memory reservations as indicated by the device tree */
>+ efi_carve_out_dt_rsv(fdt);
>+
> efi_try_purge_kaslr_seed(fdt);
>
> if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) {
LTO build failure with GCC 13.2.1
Hi all, Since commit f8cebb4f789c9950caf55a0b73e88049e7a1c3a3 enabled LTO by default for imx8m platforms, I have been having issues building u-boot. I am primarily working on imx8mp instead of imx8mm platforms so the bug resolved by that commit doesn't affect me yet. But I guess it's a generic issue with u-boot's LTO requirements and GCC 13. Build log: ``` LTO u-boot /usr/bin/aarch64-linux-gnu-ld: /usr/lib/gcc/aarch64-linux-gnu/13/libgcc.a(lse-init.o): in function `init_have_lse_atomics': /builddir/build/BUILD/gcc-13.2.1-20230728/aarch64-linux-gnu/aarch64-linux-gnu/libgcc/../../../gcc-13.2.1-20230728/libgcc/config/aarch64/lse-init.c:46: undefined reference to `__getauxval' collect2: fatal error: ld terminated with signal 11 [Segmentation fault], core dumped compilation terminated. make: *** [Makefile:1766: u-boot] Error 1 make: *** Deleting file 'u-boot' ``` GCC Version: ``` $ aarch64-linux-gnu-gcc -v Using built-in specs. COLLECT_GCC=/usr/bin/aarch64-linux-gnu-gcc COLLECT_LTO_WRAPPER=/usr/libexec/gcc/aarch64-linux-gnu/13/lto-wrapper Target: aarch64-linux-gnu Configured with: ../gcc-13.2.1-20230728/configure --bindir=/usr/bin --build=x86_64-redhat-linux-gnu --datadir=/usr/share --disable- decimal-float --disable-dependency-tracking --disable-gold --disable-libgcj --disable-libgomp --disable-libmpx --disable-libquadmat h --disable-libssp --disable-libunwind-exceptions --disable-shared --disable-silent-rules --disable-sjlj-exceptions --disable-threa ds --with-ld=/usr/bin/aarch64-linux-gnu-ld --enable-__cxa_atexit --enable-checking=release --enable-gnu-unique-object --enable-init fini-array --enable-languages=c,c++ --enable-linker-build-id --enable-lto --enable-nls --enable-obsolete --enable-plugin --enable-t argets=all --exec-prefix=/usr --host=x86_64-redhat-linux-gnu --includedir=/usr/include --infodir=/usr/share/info --libexecdir=/usr/ libexec --localstatedir=/var --mandir=/usr/share/man --prefix=/usr --program-prefix=aarch64-linux-gnu- --sbindir=/usr/sbin --shared statedir=/var/lib --sysconfdir=/etc --target=aarch64-linux-gnu --with-bugurl=http://bugzilla.redhat.com/bugzilla/ --with-gcc-major- version-only --with-isl --with-newlib --with-plugin-ld=/usr/bin/aarch64-linux-gnu-ld --with-sysroot=/usr/aarch64-linux-gnu/sys-root --with-system-libunwind --with-system-zlib --without-headers --enable-gnu-indirect-function --with-linker-hash-style=gnu Thread model: single Supported LTO compression algorithms: zlib zstd gcc version 13.2.1 20230728 (Red Hat Cross 13.2.1-1) (GCC) ``` Thanks, Sahaj Sarup
Re: [PATCH 1/6] arm: mach-k3: Add default ATF location for AM62/AM62a
Hi Andrew On 14/02/24 22:00, Andrew Davis wrote: There is a default ATF load address that is used for devices that have ATF running in SRAM. For AM62 and AM62a, ATF runs from DRAM. Instead of having to override the address in every defconfig, make add a default for these ATF in DRAM devices. Signed-off-by: Andrew Davis --- arch/arm/mach-k3/Kconfig | 5 +++-- configs/am62ax_evm_a53_defconfig | 1 - configs/am62x_beagleplay_a53_defconfig | 1 - configs/am62x_evm_a53_defconfig| 1 - configs/phycore_am62x_a53_defconfig| 1 - configs/verdin-am62_a53_defconfig | 1 - 6 files changed, 3 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 03898424c95..0bd3f9fa12d 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -123,10 +123,11 @@ config SYS_K3_SPL_ATF config K3_ATF_LOAD_ADDR hex "Load address of ATF image" + default 0x9e78 if (SOC_K3_AM625 || SOC_K3_AM62A7) default 0x7000 help - The load address for the ATF image. This value defaults to 0x7000 - if not provided in the board defconfig file. + The load address for the ATF image. This value is used to build the + FIT image header that places ATF in memory where it will run. config K3_DM_FW bool "Separate DM firmware image" diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig index 38083586a3e..03b2dea7d51 100644 --- a/configs/am62ax_evm_a53_defconfig +++ b/configs/am62ax_evm_a53_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM62A7=y -CONFIG_K3_ATF_LOAD_ADDR=0x9e78 CONFIG_TARGET_AM62A7_A53_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8048 diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig index 0be20045a97..122c1ba9299 100644 --- a/configs/am62x_beagleplay_a53_defconfig +++ b/configs/am62x_beagleplay_a53_defconfig @@ -6,7 +6,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM625=y -CONFIG_K3_ATF_LOAD_ADDR=0x9e78 CONFIG_TARGET_AM625_A53_BEAGLEPLAY=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b8 diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index 457931faf21..e29df6ec523 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM625=y -CONFIG_K3_ATF_LOAD_ADDR=0x9e78 CONFIG_TARGET_AM625_A53_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b8 diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 2d5d906a9d7..5ba08440268 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM625=y -CONFIG_K3_ATF_LOAD_ADDR=0x9e78 CONFIG_TARGET_PHYCORE_AM62X_A53=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b8 diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig index 956e3a1ad75..2003a530c7d 100644 --- a/configs/verdin-am62_a53_defconfig +++ b/configs/verdin-am62_a53_defconfig @@ -8,7 +8,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM625=y -CONFIG_K3_ATF_LOAD_ADDR=0x9e78 CONFIG_TARGET_VERDIN_AM62_A53=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b8 Reviewed-by: Neha Malcom Francis -- Thanking You Neha Malcom Francis
Re: [PATCH 2/6] arm: mach-k3: Add config option for setting OP-TEE address
On 14/02/24 22:00, Andrew Davis wrote:
Much like we have for ATF, OP-TEE has a standard address that we load
it too and run it from. Add a Kconfig item for this to remove some
hard-coding and allow this address to be more easily changed.
Signed-off-by: Andrew Davis
---
arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi | 4 ++--
arch/arm/dts/k3-am65-iot2050-boot-image.dtsi | 4 ++--
arch/arm/dts/k3-binman.dtsi | 8
arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi | 4 ++--
arch/arm/mach-k3/Kconfig | 7 +++
5 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
index a723caa5805..cca0f44b7d8 100644
--- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
@@ -105,8 +105,8 @@
arch = "arm64";
compression = "none";
os = "tee";
- load = <0x9e80>;
- entry = <0x9e80>;
+ load = ;
+ entry = ;
tee-os {
filename = "tee-raw.bin";
};
diff --git a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
index 64318d09cf0..3a6db91e132 100644
--- a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi
@@ -51,8 +51,8 @@
arch = "arm64";
compression = "none";
os = "tee";
- load = <0x9e80>;
- entry = <0x9e80>;
+ load = ;
+ entry = ;
tee-os {
};
};
diff --git a/arch/arm/dts/k3-binman.dtsi b/arch/arm/dts/k3-binman.dtsi
index 758c8bf6ea1..621653e9471 100644
--- a/arch/arm/dts/k3-binman.dtsi
+++ b/arch/arm/dts/k3-binman.dtsi
@@ -286,8 +286,8 @@
arch = "arm64";
compression = "none";
os = "tee";
- load = <0x9e80>;
- entry = <0x9e80>;
+ load = ;
+ entry = ;
ti-secure {
content = <&tee>;
keyfile = "custMpk.pem";
@@ -356,8 +356,8 @@
arch = "arm64";
compression = "none";
os = "tee";
- load = <0x9e80>;
- entry = <0x9e80>;
+ load = ;
+ entry = ;
tee-os {
filename = "tee-raw.bin";
};
diff --git a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
index 017a5a722e0..ca99fa0e690 100644
--- a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
@@ -250,8 +250,8 @@
arch = "arm64";
compression = "none";
os = "tee";
- load = <0x9e80>;
- entry = <0x9e80>;
+ load = ;
+ entry = ;
tee-os {
filename = "tee-raw.bin";
};
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 0bd3f9fa12d..55bb874d9aa 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -129,6 +129,13 @@ config K3_ATF_LOAD_ADDR
The load address for the ATF image. This value is used to build the
FIT image header that places ATF in memory where it will run.
+config K3_OPTEE_LOAD_ADDR
+ hex "Load address of OPTEE image"
+ default 0x9e80
+ help
+ The load address for the OPTEE image. This value defaults to
0x9e80
+
