[PATCH v1] arm: dts: k3-am625-verdin: fix DDRSS configuration
From: Emanuele Ghidoli
The current DDR subsystem configuration occasionally results in write failures,
impacting memory stability, on Verdin AM62 Solo 512MB WB IT 0072 SKU.
This commit addresses the issue by adjusting Drive Pull-Up/Down and
Write Latency to improve the eye diagram and ensure reliable write operations.
This configuration is shared with all Verdin AM62 SoM and
it does not introduce regressions.
Configurations changes from previous / default values:
- Drive Pull-Up/Down from 40 to 34.3 Ohm
- Write Latency from 8 to 10
- ODTLon / ODTLoff latency from 0 / 0 to 4 / 20 nCK
- VREF control range 1 at 27 %
- tFAW from 30 to 40 ns
Configuration is output from SysConfig [1] web tool, currently at version
1.18.1+3343 (DDR SubSystem v9.10).
[1] https://dev.ti.com/sysconfig
Fixes: 7d1a10659f5b ("board: toradex: add verdin am62 support")
Signed-off-by: Emanuele Ghidoli
Signed-off-by: Francesco Dolcini
---
.../dts/k3-am625-verdin-lpddr4-1600MTs.dtsi | 151 +-
1 file changed, 76 insertions(+), 75 deletions(-)
diff --git a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
index 9bad4309b491..841541bb2433 100644
--- a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
+++ b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
@@ -1,19 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
- * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.08
- * Fri Jun 09 2023 08:01:37 GMT+0200 (Central European Summer Time)
+ * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.10
+ * Mon Dec 11 2023 17:07:35 GMT+0100 (Central European Standard Time)
* DDR Type: LPDDR4
* F0 = 50MHzF1 = NA F2 = 800MHz
* Density (per channel): 16Gb
* Write DBI: Enable
* Number of Ranks: 1
- */
+*/
#define DDRSS_PLL_FHS_CNT 3
#define DDRSS_PLL_FREQUENCY_1 4
#define DDRSS_PLL_FREQUENCY_2 4
+
#define DDRSS_CTL_0_DATA 0x0B00
#define DDRSS_CTL_1_DATA 0x
#define DDRSS_CTL_2_DATA 0x
@@ -54,20 +55,20 @@
#define DDRSS_CTL_37_DATA 0x
#define DDRSS_CTL_38_DATA 0x040C
#define DDRSS_CTL_39_DATA 0x
-#define DDRSS_CTL_40_DATA 0x081C
+#define DDRSS_CTL_40_DATA 0x0A1C
#define DDRSS_CTL_41_DATA 0x
-#define DDRSS_CTL_42_DATA 0x081C
+#define DDRSS_CTL_42_DATA 0x0A1C
#define DDRSS_CTL_43_DATA 0x
#define DDRSS_CTL_44_DATA 0x05000804
#define DDRSS_CTL_45_DATA 0x0B00
#define DDRSS_CTL_46_DATA 0x09090004
-#define DDRSS_CTL_47_DATA 0x0204
+#define DDRSS_CTL_47_DATA 0x0304
#define DDRSS_CTL_48_DATA 0x00370008
#define DDRSS_CTL_49_DATA 0x09090024
-#define DDRSS_CTL_50_DATA 0x1910
+#define DDRSS_CTL_50_DATA 0x2110
#define DDRSS_CTL_51_DATA 0x00370008
#define DDRSS_CTL_52_DATA 0x09090024
-#define DDRSS_CTL_53_DATA 0x09001910
+#define DDRSS_CTL_53_DATA 0x09002110
#define DDRSS_CTL_54_DATA 0x000A0A09
#define DDRSS_CTL_55_DATA 0x0400036D
#define DDRSS_CTL_56_DATA 0x09092004
@@ -223,19 +224,19 @@
#define DDRSS_CTL_206_DATA 0x
#define DDRSS_CTL_207_DATA 0x
#define DDRSS_CTL_208_DATA 0x0024
-#define DDRSS_CTL_209_DATA 0x0012
+#define DDRSS_CTL_209_DATA 0x001A
#define DDRSS_CTL_210_DATA 0x
#define DDRSS_CTL_211_DATA 0x0024
-#define DDRSS_CTL_212_DATA 0x0012
+#define DDRSS_CTL_212_DATA 0x001A
#define DDRSS_CTL_213_DATA 0x
#define DDRSS_CTL_214_DATA 0x0004
#define DDRSS_CTL_215_DATA 0x
#define DDRSS_CTL_216_DATA 0x
#define DDRSS_CTL_217_DATA 0x0024
-#define DDRSS_CTL_218_DATA 0x0012
+#define DDRSS_CTL_218_DATA 0x001A
#define DDRSS_CTL_219_DATA 0x
#define DDRSS_CTL_220_DATA 0x0024
-#define DDRSS_CTL_221_DATA 0x0012
+#define DDRSS_CTL_221_DATA 0x001A
#define DDRSS_CTL_222_DATA 0x
#define DDRSS_CTL_223_DATA 0x
#define DDRSS_CTL_224_DATA 0x0031
@@ -268,21 +269,21 @@
#define DDRSS_CTL_251_DATA 0x
#define DDRSS_CTL_252_DATA 0x
#define DDRSS_CTL_253_DATA 0x
-#define DDRSS_CTL_254_DATA 0x46004646
-#define DDRSS_CTL_255_DATA 0x2746
-#define DDRSS_CTL_256_DATA 0x0027
-#define DDRSS_CTL_257_DATA 0x0027
-#define DDRSS_CTL_258_DATA 0x0027
-#define DDRSS_CTL_259_DATA 0x0027
-#define DDRSS_CTL_260_DATA 0x0027
+#define DDRSS_CTL_254_DATA 0x4400
+#define DDRSS_CTL_255_DATA 0x4D44
+#define DDRSS_CTL_256_DATA 0x004D
+#define DDRSS_CTL_257_DATA 0x004D
+#define DDRSS_CTL_258_DATA 0x004D
+#define DDRSS_CTL_259_DATA 0x004D
+#define DDRSS_CTL_260_DATA 0x004D
#define DDRSS_CTL_261_DATA 0x
#define DDRSS_CTL_262_DATA 0x
-#define DDRSS_CTL_263_DATA 0x000F
-#define DDRSS_CTL_264_DATA 0x000F
-#define DDRSS_CTL_265_DATA 0x000F
-#define DDRSS_CTL_266_DATA 0x000F
-#define DDRSS_CTL_267_DATA 0x000F
-#define DDRSS_CTL_268_DATA 0x000F
+#define DDRSS_CTL_263_DATA 0x004D
+#
Re: [PATCH v1] arm: dts: k3-am625-verdin: fix DDRSS configuration
On Tue, Dec 19, 2023 at 09:25:33AM +0100, Francesco Dolcini wrote:
> From: Emanuele Ghidoli
>
> The current DDR subsystem configuration occasionally results in write
> failures,
> impacting memory stability, on Verdin AM62 Solo 512MB WB IT 0072 SKU.
> This commit addresses the issue by adjusting Drive Pull-Up/Down and
> Write Latency to improve the eye diagram and ensure reliable write operations.
> This configuration is shared with all Verdin AM62 SoM and
> it does not introduce regressions.
>
> Configurations changes from previous / default values:
> - Drive Pull-Up/Down from 40 to 34.3 Ohm
> - Write Latency from 8 to 10
> - ODTLon / ODTLoff latency from 0 / 0 to 4 / 20 nCK
> - VREF control range 1 at 27 %
> - tFAW from 30 to 40 ns
>
> Configuration is output from SysConfig [1] web tool, currently at version
> 1.18.1+3343 (DDR SubSystem v9.10).
>
> [1] https://dev.ti.com/sysconfig
>
> Fixes: 7d1a10659f5b ("board: toradex: add verdin am62 support")
> Signed-off-by: Emanuele Ghidoli
> Signed-off-by: Francesco Dolcini
Hello Tom,
would be nice to have this in for v2024.01 (... I know we are pretty close
to the release with winter holidays in between ...).
Thanks,
Francesco
Re: [PATCH v1] arm: dts: k3-am625-verdin: fix DDRSS configuration
On Tue, 2023-12-19 at 09:25 +0100, Francesco Dolcini wrote:
> From: Emanuele Ghidoli
>
> The current DDR subsystem configuration occasionally results in write
> failures,
> impacting memory stability, on Verdin AM62 Solo 512MB WB IT 0072 SKU.
> This commit addresses the issue by adjusting Drive Pull-Up/Down and
> Write Latency to improve the eye diagram and ensure reliable write operations.
> This configuration is shared with all Verdin AM62 SoM and
> it does not introduce regressions.
>
> Configurations changes from previous / default values:
> - Drive Pull-Up/Down from 40 to 34.3 Ohm
> - Write Latency from 8 to 10
> - ODTLon / ODTLoff latency from 0 / 0 to 4 / 20 nCK
> - VREF control range 1 at 27 %
> - tFAW from 30 to 40 ns
>
> Configuration is output from SysConfig [1] web tool, currently at version
> 1.18.1+3343 (DDR SubSystem v9.10).
>
> [1] https://dev.ti.com/sysconfig
>
> Fixes: 7d1a10659f5b ("board: toradex: add verdin am62 support")
> Signed-off-by: Emanuele Ghidoli
> Signed-off-by: Francesco Dolcini
Acked-by: Marcel Ziswiler
> ---
> .../dts/k3-am625-verdin-lpddr4-1600MTs.dtsi | 151 +-
> 1 file changed, 76 insertions(+), 75 deletions(-)
>
> diff --git a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
> b/arch/arm/dts/k3-am625-verdin-lpddr4-
> 1600MTs.dtsi
> index 9bad4309b491..841541bb2433 100644
> --- a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
> +++ b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
> @@ -1,19 +1,20 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> * This file was generated with the
> - * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.08
> - * Fri Jun 09 2023 08:01:37 GMT+0200 (Central European Summer Time)
> + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.10
> + * Mon Dec 11 2023 17:07:35 GMT+0100 (Central European Standard Time)
> * DDR Type: LPDDR4
> * F0 = 50MHz F1 = NA F2 = 800MHz
> * Density (per channel): 16Gb
> * Write DBI: Enable
> * Number of Ranks: 1
> - */
> +*/
>
> #define DDRSS_PLL_FHS_CNT 3
> #define DDRSS_PLL_FREQUENCY_1 4
> #define DDRSS_PLL_FREQUENCY_2 4
>
> +
> #define DDRSS_CTL_0_DATA 0x0B00
> #define DDRSS_CTL_1_DATA 0x
> #define DDRSS_CTL_2_DATA 0x
> @@ -54,20 +55,20 @@
> #define DDRSS_CTL_37_DATA 0x
> #define DDRSS_CTL_38_DATA 0x040C
> #define DDRSS_CTL_39_DATA 0x
> -#define DDRSS_CTL_40_DATA 0x081C
> +#define DDRSS_CTL_40_DATA 0x0A1C
> #define DDRSS_CTL_41_DATA 0x
> -#define DDRSS_CTL_42_DATA 0x081C
> +#define DDRSS_CTL_42_DATA 0x0A1C
> #define DDRSS_CTL_43_DATA 0x
> #define DDRSS_CTL_44_DATA 0x05000804
> #define DDRSS_CTL_45_DATA 0x0B00
> #define DDRSS_CTL_46_DATA 0x09090004
> -#define DDRSS_CTL_47_DATA 0x0204
> +#define DDRSS_CTL_47_DATA 0x0304
> #define DDRSS_CTL_48_DATA 0x00370008
> #define DDRSS_CTL_49_DATA 0x09090024
> -#define DDRSS_CTL_50_DATA 0x1910
> +#define DDRSS_CTL_50_DATA 0x2110
> #define DDRSS_CTL_51_DATA 0x00370008
> #define DDRSS_CTL_52_DATA 0x09090024
> -#define DDRSS_CTL_53_DATA 0x09001910
> +#define DDRSS_CTL_53_DATA 0x09002110
> #define DDRSS_CTL_54_DATA 0x000A0A09
> #define DDRSS_CTL_55_DATA 0x0400036D
> #define DDRSS_CTL_56_DATA 0x09092004
> @@ -223,19 +224,19 @@
> #define DDRSS_CTL_206_DATA 0x
> #define DDRSS_CTL_207_DATA 0x
> #define DDRSS_CTL_208_DATA 0x0024
> -#define DDRSS_CTL_209_DATA 0x0012
> +#define DDRSS_CTL_209_DATA 0x001A
> #define DDRSS_CTL_210_DATA 0x
> #define DDRSS_CTL_211_DATA 0x0024
> -#define DDRSS_CTL_212_DATA 0x0012
> +#define DDRSS_CTL_212_DATA 0x001A
> #define DDRSS_CTL_213_DATA 0x
> #define DDRSS_CTL_214_DATA 0x0004
> #define DDRSS_CTL_215_DATA 0x
> #define DDRSS_CTL_216_DATA 0x
> #define DDRSS_CTL_217_DATA 0x0024
> -#define DDRSS_CTL_218_DATA 0x0012
> +#define DDRSS_CTL_218_DATA 0x001A
> #define DDRSS_CTL_219_DATA 0x
> #define DDRSS_CTL_220_DATA 0x0024
> -#define DDRSS_CTL_221_DATA 0x0012
> +#define DDRSS_CTL_221_DATA 0x001A
> #define DDRSS_CTL_222_DATA 0x
> #define DDRSS_CTL_223_DATA 0x
> #define DDRSS_CTL_224_DATA 0x0031
> @@ -268,21 +269,21 @@
> #define DDRSS_CTL_251_DATA 0x
> #define DDRSS_CTL_252_DATA 0x
> #define DDRSS_CTL_253_DATA 0x
> -#define DDRSS_CTL_254_DATA 0x46004646
> -#define DDRSS_CTL_255_DATA 0x2746
> -#define DDRSS_CTL_256_DATA 0x0027
> -#define DDRSS_CTL_257_DATA 0x0027
> -#define DDRSS_CTL_258_DATA 0x0027
> -#define DDRSS_CTL_259_DATA 0x0027
> -#define DDRSS_CTL_260_DATA 0x0027
> +#define DDRSS_CTL_254_DATA 0x4400
> +#define DDRSS_CTL_255_DATA 0x4D44
> +#define DDRSS_CTL_256_DATA 0x004D
> +#define DDRSS_CTL_257_DATA 0x004D
> +#define DDRSS_CTL_258_DATA 0x004D
> +#define DDRSS_CTL_259_DATA 0x004D
> +#define DDRSS_CTL_260_DATA 0x004D
> #defi
Re: Using uart1 on mediatek mt8195 derived board
El 2023-12-08 17:06, Thomas Schaefer va escriure:
Hi Macpaul, Fabien,
I'm referring to patch series
https://patchwork.ozlabs.org/project/uboot/patch/20230804110448.24589-1-macpaul@mediatek.com/
where support for the mediatek mt8195 SOC is introduced into u-boot.
We are developing a board based on the mt8195 as well but we want to
use UART1 instead of UART0 for debug output messages.
Our board is booting and we see boot messages on a debug pin header
connected to UART0 when using the settings from the demo board, but
when trying to switch to UART1, no more messages appear on the
console. What we have tried is the following:
- Adaptation of the dts and dtsi files with uart1 settings taken from
linux device tree:
diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
index a7e4db5aa7..53eb437fad 100644
--- a/arch/arm/dts/mt8195.dtsi
+++ b/arch/arm/dts/mt8195.dtsi
@@ -245,6 +245,17 @@
status = "disabled";
};
+ uart1: serial@11001200 {
+ compatible = "mediatek,mt8195-uart",
+"mediatek,hsuart";
+ reg = <0 0x11001200 0 0x1000>;
+ interrupts = ;
+ clock-frequency = <2600>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
pericfg_ao: syscon@11003000 {
compatible = "mediatek,mt8195-pericfg_ao",
"syscon";
reg = <0 0x11003000 0 0x1000>;
diff --git a/arch/arm/dts/mt8195-kontron-sbc-i1200.dts
b/arch/arm/dts/mt8195-kontron-sbc-i1200.dts
index c6ea7e8f3d..4700a6d303 100644
--- a/arch/arm/dts/mt8195-kontron-sbc-i1200.dts
+++ b/arch/arm/dts/mt8195-kontron-sbc-i1200.dts
@@ -58,7 +58,7 @@
};
chosen {
- stdout-path = &uart0;
+ stdout-path = &uart1;
};
reg_1p8v: regulator-1p8v {
@@ -121,7 +121,7 @@
status = "okay";
};
-&uart0 {
+&uart1 {
status = "okay";
};
We also tried to change the DEBUG_UART settings in the defconfig to
match with UART1, but without success.
Are there any special means to make UART1 interface run?
Did you had a look in the DTS from the kernel:
https://elixir.bootlin.com/linux/v6.7-rc6/source/arch/arm64/boot/dts/mediatek/mt8195.dtsi#L1040
My bet would be that infracfg_ao CLK_INFRA_AO_UART1 is not configured
correctly.
Best regards,
Matthias.
Best regards,
Thomas
Thomas Schäfer
SW Design Engineer
T:
+49 681 95916 203
thomas.schae...@kontron.com
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Re: [PATCH v3 1/7] rpi5: add initial memory map for bcm2712
On 12-18 23:25, Stefan Wahren wrote:
> >
> > +static struct mm_region bcm2712_mem_map[MEM_MAP_MAX_ENTRIES] = {
> > + {
> in comparison to mach-imx/imx9/soc.c most of the memory maps doesn't
> have a describing comment.
Yep, I have thinking to add more comments, but decided to not modify too
much patch from Dmitry. On the other side there is not much excitement
stuff here.
> > + .virt = 0xUL,
> > + .phys = 0xUL,
> > + .size = 0x3f80UL,
> > + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> > +PTE_BLOCK_INNER_SHARE
> > + }, {
> > + .virt = 0x3f80UL,
> > + .phys = 0x3f80UL,
> > + .size = 0x0080UL,
> > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> > +PTE_BLOCK_NON_SHARE |
> > +PTE_BLOCK_PXN | PTE_BLOCK_UXN
> > + }, {
> > + /* Beginning of AXI bus where uSD controller lives */
> > + .virt = 0x10UL,
> > + .phys = 0x10UL,
> > + .size = 0x000200UL,
> > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> > +PTE_BLOCK_NON_SHARE |
> > +PTE_BLOCK_PXN | PTE_BLOCK_UXN
> > + }, {
> > + .virt = 0x107c00UL,
> > + .phys = 0x107c00UL,
> > + .size = 0x000400UL,
> > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> > +PTE_BLOCK_NON_SHARE |
> > +PTE_BLOCK_PXN | PTE_BLOCK_UXN
> > + }, {
> > + /* List terminator */
> > + 0,
> > + }
> > +};
> > +
> > struct mm_region *mem_map = bcm283x_mem_map;
> >
> > /*
> > @@ -78,6 +113,7 @@ static const struct udevice_id board_ids[] = {
> > { .compatible = "brcm,bcm2837", .data = (ulong)&bcm283x_mem_map},
> > { .compatible = "brcm,bcm2838", .data = (ulong)&bcm2711_mem_map},
> > { .compatible = "brcm,bcm2711", .data = (ulong)&bcm2711_mem_map},
> > + { .compatible = "brcm,bcm2712", .data = (ulong)&bcm2712_mem_map},
> > { },
> > };
> >
> Looking at the complete file, i saw the function print_cpuinfo().
> Personally i think it's wrong to print BCM283x in case of a RPI 4 or 5.
CONFIG_DISPLAY_CPUINFO is not set for RPi's, but I suppose this could be nice
aesthetic enhancement.
Thanks,
Ivan
Re:Re: [PATCH v2 13/17] video: rockchip: Add rk3328 vop support
Hi Jaqan，
在 2023-12-19 15:42:26，"Jagan Teki" 写道：
>Hi Andy,
>
>On Tue, Dec 19, 2023 at 6:50 AM Andy Yan wrote:
>>
>>
>> Hi Jaqan：
>>
>> At 2023-12-19 03:11:10, "Jagan Teki" wrote:
>> >From: Jagan Teki
>> >
>> >Add support for Rockchip RK3328 VOP.
>> >
>> >Require VOP cleanup before handoff to Linux by writing reset values to
>> >WIN registers. Without this Linux VOP trigger page fault as below
>> >[0.752016] Loading compiled-in X.509 certificates
>> >[0.787796] inno_hdmi_phy_rk3328_clk_recalc_rate: parent 2400
>> >[0.788391] inno-hdmi-phy ff43.phy:
>> >inno_hdmi_phy_rk3328_clk_recalc_rate rate 14850 vco 14850
>> >[0.798353] rockchip-drm display-subsystem: bound ff37.vop (ops
>> >vop_component_ops)
>> >[0.799403] dwhdmi-rockchip ff3c.hdmi: supply avdd-0v9 not found,
>> >using dummy regulator
>> >[0.800288] rk_iommu ff373f00.iommu: Enable stall request timed out,
>> >status: 0x4b
>> >[0.801131] dwhdmi-rockchip ff3c.hdmi: supply avdd-1v8 not found,
>> >using dummy regulator
>> >[0.802056] rk_iommu ff373f00.iommu: Disable paging request timed out,
>> >status: 0x4b
>> >[0.803233] dwhdmi-rockchip ff3c.hdmi: Detected HDMI TX controller
>> >v2.11a with HDCP (inno_dw_hdmi_phy2)
>> >[0.805355] dwhdmi-rockchip ff3c.hdmi: registered DesignWare HDMI
>> >I2C bus driver
>> >[0.808769] rockchip-drm display-subsystem: bound ff3c.hdmi (ops
>> >dw_hdmi_rockchip_ops)
>> >[0.810869] [drm] Initialized rockchip 1.0.0 20140818 for
>> >display-subsystem on minor 0
>> >
>> >Signed-off-by: Jagan Teki
>> >---
>> >Changes for v2:
>> >- Add VOP cleanup
>> >- Update commit
>> >
>> > drivers/video/rockchip/Makefile | 1 +
>> > drivers/video/rockchip/rk3328_vop.c | 83 +
>> > 2 files changed, 84 insertions(+)
>> > create mode 100644 drivers/video/rockchip/rk3328_vop.c
>> >
>> >diff --git a/drivers/video/rockchip/Makefile
>> >b/drivers/video/rockchip/Makefile
>> >index 4991303c73..f55beceebf 100644
>> >--- a/drivers/video/rockchip/Makefile
>> >+++ b/drivers/video/rockchip/Makefile
>> >@@ -6,6 +6,7 @@
>> > ifdef CONFIG_VIDEO_ROCKCHIP
>> > obj-y += rk_vop.o
>> > obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288_vop.o
>> >+obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328_vop.o
>> > obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399_vop.o
>> > obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o
>> > obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
>> >diff --git a/drivers/video/rockchip/rk3328_vop.c
>> >b/drivers/video/rockchip/rk3328_vop.c
>> >new file mode 100644
>> >index 00..a4da3a91e8
>> >--- /dev/null
>> >+++ b/drivers/video/rockchip/rk3328_vop.c
>> >@@ -0,0 +1,83 @@
>> >+// SPDX-License-Identifier: GPL-2.0+
>> >+/*
>> >+ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
>> >+ */
>> >+
>> >+#include
>> >+#include
>> >+#include
>> >+#include "rk_vop.h"
>> >+
>> >+DECLARE_GLOBAL_DATA_PTR;
>> >+
>> >+static void rk3328_set_pin_polarity(struct udevice *dev,
>> >+ enum vop_modes mode, u32 polarity)
>> >+{
>> >+ struct rk_vop_priv *priv = dev_get_priv(dev);
>> >+ struct rk3288_vop *regs = priv->regs;
>> >+
>> >+ switch (mode) {
>> >+ case VOP_MODE_HDMI:
>> >+ clrsetbits_le32(®s->dsp_ctrl1,
>> >+ M_RK3399_DSP_HDMI_POL,
>> >+ V_RK3399_DSP_HDMI_POL(polarity));
>> >+ break;
>> >+ default:
>> >+ debug("%s: unsupported output mode %x\n", __func__, mode);
>> >+ }
>> >+}
>> >+
>> >+static int rk3328_vop_probe(struct udevice *dev)
>> >+{
>> >+ /* Before relocation we don't need to do anything */
>> >+ if (!(gd->flags & GD_FLG_RELOC))
>> >+ return 0;
>> >+
>> >+ return rk_vop_probe(dev);
>> >+}
>> >+
>> >+static int rk3328_vop_remove(struct udevice *dev)
>> >+{
>> >+ struct rk_vop_priv *priv = dev_get_priv(dev);
>> >+ struct rk3288_vop *regs = priv->regs;
>> >+ struct rk3288_vop *win_regs = priv->regs + priv->win_offset;
>> >+
>> >+ /* write reset values */
>> >+ writel(0xef013f, &win_regs->win0_act_info);
>> >+ writel(0xef013f, &win_regs->win0_dsp_info);
>> >+ writel(0xa000a, &win_regs->win0_dsp_st);
>> >+ writel(0x0, &win_regs->win0_yrgb_mst);
>> >+ writel(0x01, ®s->reg_cfg_done);
>> >+
>> >+ return 0;
>> >+}
>>
>> I think this just workaround Linux iommu page fault by luck。
>> The reset value（what you called it is）your write just let win0 read a
>> 320x240 rectangular from address 0 and display it at next frame（maybe 16ms
>> later if your
>> current display is run at 60HZ）。
>>
>> 1. we don't know what content is at address 0, so you will see something
>> strange on your monitor.
>> 2. there is no guarantee that address 0 is really readable（maybe a security
>> memory space， or maybe
>> it is not a valid address）， this may cause another issue that not easy
>> to detect。
>
>Okay. Can you
Re: [RFC PATCH] mxs: Don't enable 4P2 reg if mx28 is powered only from DCDC_BATT without 5V
On Fri, Dec 15, 2023 at 7:23 PM Fabio Estevam wrote: > > On Fri, Dec 15, 2023 at 1:20 PM Fabio Estevam wrote: > > > Ok, what about the patch below? > > > > https://patchwork.ozlabs.org/project/uboot/patch/20230703205700.9120-1-c...@londelec.com/ > > > > Is this still needed? > > I looked in the i.MX28 Reference Manual, and the one above looks a > correct fix. I will queue it. Yes, this patch is needed, thank you for queuing it.
Re: [PATCH v3 4/7] bcm2835: brcm,bcm2708-fb device is using r5g6b5 format
On 12-18 23:32, Stefan Wahren wrote:
> >
> > static const struct udevice_id bcm2835_video_ids[] = {
> > - { .compatible = "brcm,bcm2835-hdmi" },
> > - { .compatible = "brcm,bcm2711-hdmi0" },
> > - { .compatible = "brcm,bcm2708-fb" },
> > + { .compatible = "brcm,bcm2835-hdmi", .data = VIDEO_BPP32},
> > + { .compatible = "brcm,bcm2711-hdmi0", .data = VIDEO_BPP32},
> > + { .compatible = "brcm,bcm2708-fb",.data = VIDEO_BPP16 },
> this change looks wrong to me. Before we used VIDEO_BPP32 for
> brcm,bcm2708-fb. I think it's hard to explain why we should downgrade
> the other boards. I would expect some brcm,bcm2712 compatible at least
> this needs an explanation in the commit message.
>
If you are confident that this semi device was working before with
BPP32 I will try to find better way to handle this. Do you remember
which RPi version was this?
Thanks,
Ivan
Re: [PATCH v2 02/17] video: dw_hdmi: Add Vendor PHY handling
On 18/12/2023 20:10, Jagan Teki wrote:
From: Jagan Teki
DW HDMI support Vendor PHY like Rockchip RK3328 Inno HDMI PHY.
Extend the vendor phy handling by adding platform phy hooks.
Signed-off-by: Jagan Teki
---
Changes for v2:
- fix meson cfg
drivers/video/dw_hdmi.c | 29 +++-
drivers/video/meson/meson_dw_hdmi.c | 11 ++-
drivers/video/rockchip/rk3399_hdmi.c | 8 +++-
drivers/video/rockchip/rk_hdmi.c | 2 +-
drivers/video/sunxi/sunxi_dw_hdmi.c | 11 ++-
include/dw_hdmi.h| 14 +-
6 files changed, 69 insertions(+), 6 deletions(-)
diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
index c4fbb18294..ea12a09407 100644
--- a/drivers/video/dw_hdmi.c
+++ b/drivers/video/dw_hdmi.c
@@ -988,7 +988,7 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct
display_timing *edid)
hdmi_av_composer(hdmi, edid);
- ret = hdmi->phy_set(hdmi, edid->pixelclock.typ);
+ ret = hdmi->ops->phy_set(hdmi, edid->pixelclock.typ);
if (ret)
return ret;
@@ -1009,10 +1009,37 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid)
return 0;
}
+static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
+ .phy_set = dw_hdmi_phy_cfg,
+};
+
+static void dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
+{
+ if (!hdmi->data)
+ return;
+
+ /* hook Synopsys PHYs ops */
+ if (!hdmi->data->phy_force_vendor) {
+ hdmi->ops = &dw_hdmi_synopsys_phy_ops;
+ return;
+ }
+
+ /* Vendor HDMI PHYs must assign phy_ops in plat_data */
+ if (!hdmi->data->phy_ops) {
+ printf("Unsupported Vendor HDMI phy_ops\n");
+ return;
+ }
+
+ /* hook Vendor HDMI PHYs ops */
+ hdmi->ops = hdmi->data->phy_ops;
Sorry but I still don't understand why you need phy_force_vendor & phy_ops,
this code clearly fails if you have phy_force_vendor=true && phy_ops=NULL,
so drop phy_force_vendor and simply use phy_ops if != NULL, and since it's
the only element of dw_hdmi_plat_data, drop dw_hdmi_plat_data and pass
dw_hdmi_phy_ops directly in the dw_hdmi struct.
So in dw_hdmi_detect_phy(), if hdmi->ops is NULL, set it to
dw_hdmi_synopsys_phy_ops.
Neil
+}
+
void dw_hdmi_init(struct dw_hdmi *hdmi)
{
uint ih_mute;
+ dw_hdmi_detect_phy(hdmi);
+
/*
* boot up defaults are:
* hdmi_ih_mute = 0x03 (disabled)
diff --git a/drivers/video/meson/meson_dw_hdmi.c
b/drivers/video/meson/meson_dw_hdmi.c
index 5db01904b5..d0d878b6af 100644
--- a/drivers/video/meson/meson_dw_hdmi.c
+++ b/drivers/video/meson/meson_dw_hdmi.c
@@ -375,6 +375,15 @@ static int meson_dw_hdmi_wait_hpd(struct dw_hdmi *hdmi)
return -ETIMEDOUT;
}
+static const struct dw_hdmi_phy_ops dw_hdmi_meson_phy_ops = {
+ .phy_set = meson_dw_hdmi_phy_init,
+};
+
+static const struct dw_hdmi_plat_data dw_hdmi_meson_plat_data = {
+ .phy_force_vendor = true,
+ .phy_ops = &dw_hdmi_meson_phy_ops,
+};
+
static int meson_dw_hdmi_probe(struct udevice *dev)
{
struct meson_dw_hdmi *priv = dev_get_priv(dev);
@@ -397,7 +406,7 @@ static int meson_dw_hdmi_probe(struct udevice *dev)
priv->hdmi.hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
priv->hdmi.hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
- priv->hdmi.phy_set = meson_dw_hdmi_phy_init;
+ priv->hdmi.data = &dw_hdmi_meson_plat_data;
if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
priv->hdmi.reg_io_width = 1;
else {
diff --git a/drivers/video/rockchip/rk3399_hdmi.c
b/drivers/video/rockchip/rk3399_hdmi.c
index 3041360c6e..b32139a8a6 100644
--- a/drivers/video/rockchip/rk3399_hdmi.c
+++ b/drivers/video/rockchip/rk3399_hdmi.c
@@ -64,8 +64,14 @@ static const struct dm_display_ops rk3399_hdmi_ops = {
.enable = rk3399_hdmi_enable,
};
+static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
+};
+
static const struct udevice_id rk3399_hdmi_ids[] = {
- { .compatible = "rockchip,rk3399-dw-hdmi" },
+ {
+ .compatible = "rockchip,rk3399-dw-hdmi",
+ .data = (ulong)&rk3399_hdmi_drv_data
+ },
{ }
};
diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index b75a174489..e34f532cd6 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -83,6 +83,7 @@ int rk_hdmi_of_to_plat(struct udevice *dev)
struct rk_hdmi_priv *priv = dev_get_priv(dev);
struct dw_hdmi *hdmi = &priv->hdmi;
+ hdmi->data = (const struct dw_hdmi_plat_data *)dev_get_driver_data(dev);
hdmi->ioaddr = (ulong)dev_read_addr(dev);
hdmi->mpll_cfg = rockchip_mpll_cfg;
hdmi->phy_cfg = rockchip_phy_config;
@@ -90,7 +91,6 @@ int rk_hdmi_of_to_plat(struct udevice *dev)
/* hdmi
Re: [PATHv11 28/43] configs/turris_omnia_defconfig: enable LTO
On Mon, 27 Nov 2023 18:57:11 +0600 Maxim Uvarov wrote: > Decrease allowed binary size to fit lwip code. > u-boot-with-spl.kwb exceeds file size limit: > limit: 0xf6000 bytes > actual: 0xf8600 bytes > excess: 0x2600 bytes > > Signed-off-by: Maxim Uvarov > --- > configs/turris_omnia_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig > index afcd4a1eb7..4e965c795a 100644 > --- a/configs/turris_omnia_defconfig > +++ b/configs/turris_omnia_defconfig > @@ -118,3 +118,4 @@ CONFIG_USB_EHCI_HCD=y > CONFIG_WDT=y > CONFIG_WDT_ORION=y > CONFIG_EXT4_WRITE=y > +CONFIG_LTO=y I finally tested it and LTO is currently broken on Omnia: Missing DTB spl_init() failed: -2 ### ERROR ### Please RESET the board ### Marek
Re: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA
On 12/19/23 08:03, Chee, Tien Fong wrote:
Hi,
-Original Message-
From: Lau, Wan Yee
Sent: Friday, December 8, 2023 4:37 PM
To: u-boot@lists.denx.de
Cc: Simon Glass ; Kever Yang ; Bin Meng ; Jonas Karlman
; Jean-Marie Lemetayer ; Peng
Fan ; Vladimir Zapolskiy
; Konrad Dybcio ;
Marek Vasut ; Simon Goldschmidt
; Chee, Tien Fong
; Hea, Kok Kiang ;
Maniyam, Dinesh ; Ng, Boon Khai
; Yuslaimi, Alif Zakuan
; Chong, Teik Heng
; Zamri, Muhammad Hazim Izzat
; Lim, Jit Loon
; Tang, Sieu Mun
Subject: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel
SoCFPGA
From: Wan Yee Lau
This driver can be used to provide user a clean interface and all register
settings are centralized in one place, device tree without need for
hardcoding in the source code.
Signed-off-by: Wan Yee Lau
---
.../misc/socfpga_dtreg.txt| 66 ++
drivers/misc/Kconfig | 7 ++
drivers/misc/Makefile | 1 +
drivers/misc/socfpga_dtreg.c | 117 ++
4 files changed, 191 insertions(+)
create mode 100644 doc/device-tree-bindings/misc/socfpga_dtreg.txt
create mode 100644 drivers/misc/socfpga_dtreg.c
diff --git a/doc/device-tree-bindings/misc/socfpga_dtreg.txt b/doc/device-
tree-bindings/misc/socfpga_dtreg.txt
new file mode 100644
index 00..5458103f88
--- /dev/null
+++ b/doc/device-tree-bindings/misc/socfpga_dtreg.txt
@@ -0,0 +1,66 @@
+* Firewall and privilege register settings in device tree
+
+Required properties:
+
+
+- compatible: should contain "intel,socfpga-dtreg"
+- reg: Physical base address and size of block register.
+- intel,offset-settings: 32-bit offset address of block register,
+followed by 32-bit value settings and
+the masking bits, only masking bit
+set to 1 allows modification.
+
+This driver can be used to provide user a clean interface and all
+register settings are centralized in one place, device tree without
+need for hardcoding in the source code.
+
+General setup would be to set the memory address used by the register,
+followed by the offset-settings containing the 32-bit offset address of
+the block register, then the 32-bit value settings and lastly the
+masking bits.
+
+Example:
+
+
+Configuration for multiple dtreg node support in device tree:
+
+ socfpga_mainfirewall: socfpga-mainfirewall {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+#size-cells = <1>;
+ bootph-all;
+
+coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 {
+ reg = <0xf7100200 0x0014>;
+intel,offset-settings =
+ /* Disable ocram security at CCU for
non secure
access */
+<0x004 0x8000 0xe007>,
+<0x008 0x8000 0xe007>,
+<0x00c 0x8000 0xe007>,
+<0x010 0x8000 0xe007>;
+bootph-all;
+};
+};
+
+ socfpga_mpfefirewall: socfpga-mpfefirewall {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+#size-cells = <1>;
+ bootph-all;
+
+soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f802 {
+reg = <0xf802 0x001c>;
+intel,offset-settings =
+/* Disable MPFE firewall for SMMU */
+<0x 0x00010101 0x00010101>,
+/* Disable MPFE firewall for HMC
adapter */
+<0x0004 0x0001 0x00010101>;
+ bootph-all;
+};
+};
+
+To call the nodes use:
+
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-
mainfirewall", &dev);
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-
mpfefirewall",
+&dev);
+
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
fccd9b89b8..c423905ba2 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -683,4 +683,11 @@ config SL28CPLD
the base driver which provides common access methods for the
sub-drivers.
+config SPL_SOCFPGA_DT_REG
+ bool "Enable register setting from device tree in SPL"
+ depends on SPL
+ help
+ Enable register setting from device tree. This also
+ provides user a clean interface and all register settings are
+ centralized in one place, device tree.
endmenu
diff --git a/dr
Re: [PATCH 4/4] nvmem: layouts: add U-Boot env layout
On 19.12.2023 08:55, Miquel Raynal wrote:
Hi Rafał,
zaj...@gmail.com wrote on Mon, 18 Dec 2023 23:10:20 +0100:
On 18.12.2023 15:21, Miquel Raynal wrote:
Hi Rafał,
zaj...@gmail.com wrote on Mon, 18 Dec 2023 14:37:22 +0100:
From: Rafał Miłecki
This patch moves all generic (NVMEM devices independent) code from NVMEM
device driver to NVMEM layout driver. Then it adds a simple NVMEM layout
code on top of it.
Thanks to proper layout it's possible to support U-Boot env data stored
on any kind of NVMEM device.
For backward compatibility with old DT bindings we need to keep old
NVMEM device driver functional. To avoid code duplication a parsing
function is exported and reused in it.
Signed-off-by: Rafał Miłecki
---
I have a couple of comments about the original driver which gets
copy-pasted in the new layout driver, maybe you could clean these
(the memory leak should be fixed before the migration so it can be
backported easily, the others are just style so it can be done after, I
don't mind).
...
+int u_boot_env_parse(struct device *dev, struct nvmem_device *nvmem,
+enum u_boot_env_format format)
+{
+ size_t crc32_data_offset;
+ size_t crc32_data_len;
+ size_t crc32_offset;
+ size_t data_offset;
+ size_t data_len;
+ size_t dev_size;
+ uint32_t crc32;
+ uint32_t calc;
+ uint8_t *buf;
+ int bytes;
+ int err;
+
+ dev_size = nvmem_dev_size(nvmem);
+
+ buf = kcalloc(1, dev_size, GFP_KERNEL);
Out of curiosity, why kcalloc(1,...) rather than kzalloc() ?
I used kcalloc() initially as I didn't need buffer to be zeroed.
I think kcalloc() initializes the memory to zero.
https://elixir.bootlin.com/linux/latest/source/include/linux/slab.h#L659
If you don't need it you can switch to kmalloc() instead, I don't mind,
but kcalloc() is meant to be used with arrays, I don't see the point of
using kcalloc() in this case.
I see that memory-allocation.rst however says:
> And, to be on the safe side it's best to use routines that set memory to
zero, like kzalloc().
It's probably close to zero cost to zero that buffer so it could be kzalloc().
+ if (!buf) {
+ err = -ENOMEM;
+ goto err_out;
We could directly return ENOMEM here I guess.
+ }
+
+ bytes = nvmem_device_read(nvmem, 0, dev_size, buf);
+ if (bytes < 0)
+ return bytes;
+ else if (bytes != dev_size)
+ return -EIO;
Don't we need to free buf in the above cases?
+ switch (format) {
+ case U_BOOT_FORMAT_SINGLE:
+ crc32_offset = offsetof(struct u_boot_env_image_single, crc32);
+ crc32_data_offset = offsetof(struct u_boot_env_image_single,
data);
+ data_offset = offsetof(struct u_boot_env_image_single, data);
+ break;
+ case U_BOOT_FORMAT_REDUNDANT:
+ crc32_offset = offsetof(struct u_boot_env_image_redundant,
crc32);
+ crc32_data_offset = offsetof(struct u_boot_env_image_redundant,
data);
+ data_offset = offsetof(struct u_boot_env_image_redundant, data);
+ break;
+ case U_BOOT_FORMAT_BROADCOM:
+ crc32_offset = offsetof(struct u_boot_env_image_broadcom,
crc32);
+ crc32_data_offset = offsetof(struct u_boot_env_image_broadcom,
data);
+ data_offset = offsetof(struct u_boot_env_image_broadcom, data);
+ break;
+ }
+ crc32 = le32_to_cpu(*(__le32 *)(buf + crc32_offset));
Looks a bit convoluted, any chances we can use intermediate variables
to help decipher this?
+ crc32_data_len = dev_size - crc32_data_offset;
+ data_len = dev_size - data_offset;
+
+ calc = crc32(~0, buf + crc32_data_offset, crc32_data_len) ^ ~0L;
+ if (calc != crc32) {
+ dev_err(dev, "Invalid calculated CRC32: 0x%08x (expected:
0x%08x)\n", calc, crc32);
+ err = -EINVAL;
+ goto err_kfree;
+ }
+
+ buf[dev_size - 1] = '\0';
+ err = u_boot_env_parse_cells(dev, nvmem, buf, data_offset, data_len);
+ if (err)
+ dev_err(dev, "Failed to add cells: %d\n", err);
Please drop this error message, the only reason for which the function
call would fail is apparently an ENOMEM case.
+
+err_kfree:
+ kfree(buf);
+err_out:
+ return err;
+}
+EXPORT_SYMBOL_GPL(u_boot_env_parse);
+
+static int u_boot_env_add_cells(struct device *dev, struct nvmem_device *nvmem)
+{
+ const struct of_device_id *match;
+ struct device_node *layout_np;
+ enum u_boot_env_format format;
+
+ layout_np = of_nvmem_layout_get_container(nvmem);
+ if (!layout_np)
+ return -ENOENT;
+
+ match = of_match_node(u_boot_env_of_match_table, layout_np);
+ if (!match)
+ return -ENOENT;
+
+ format = (uintptr_t)match->data;
In the core there is
[PATCH u-boot-marvell] arm: mvebu: turris_omnia: Enable networking via ethernet switch
From: Marek Mojík
The Turris Omnia contains the Marvell 88E6176 ethernet switch. Add
config options and device tree to enable the support.
Signed-off-by: Marek Mojík
Signed-off-by: Marek Behún
---
Stefan, this patch depends on
[v2] net: mv88e6xxx: fix missing SMI address initialization
https://patchwork.ozlabs.org/project/uboot/patch/62eoapvurxkedw74vpzb55q3nuqgb4cef3bl2laayx57cpjzus@vlpx57cjc4ph/
---
.../dts/armada-385-turris-omnia-u-boot.dtsi | 51 +++
configs/turris_omnia_defconfig| 2 +
2 files changed, 53 insertions(+)
diff --git a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi
b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi
index 509d6ca69c..c63a331d69 100644
--- a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi
+++ b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi
@@ -35,6 +35,57 @@
};
};
+&mdio {
+ switch@10 {
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sw_phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+
+ sw_phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ sw_phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ sw_phy3: ethernet-phy@3 {
+ reg = <0x3>;
+ };
+
+ sw_phy4: ethernet-phy@4 {
+ reg = <0x4>;
+ };
+ };
+ ports {
+ ports@0 {
+ phy-handle = <&sw_phy0>;
+ phy-mode = "internal";
+ };
+ ports@1 {
+ phy-handle = <&sw_phy1>;
+ phy-mode = "internal";
+ };
+ ports@2 {
+ phy-handle = <&sw_phy2>;
+ phy-mode = "internal";
+ };
+ ports@3 {
+ phy-handle = <&sw_phy3>;
+ phy-mode = "internal";
+ };
+ ports@4 {
+ phy-handle = <&sw_phy4>;
+ phy-mode = "internal";
+ };
+ };
+ };
+};
+
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
&spi0 {
flash@0 {
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index 65d4a296e7..3aaee276ea 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -96,7 +96,9 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_FIXED=y
+CONFIG_DM_DSA=y
CONFIG_PHY_GIGE=y
+CONFIG_MV88E6XXX=y
CONFIG_MVNETA=y
CONFIG_MII=y
CONFIG_MVMDIO=y
--
2.41.0
Re: [PATCH 4/4] nvmem: layouts: add U-Boot env layout
On 19.12.2023 10:55, Rafał Miłecki wrote:
On 19.12.2023 08:55, Miquel Raynal wrote:
Hi Rafał,
zaj...@gmail.com wrote on Mon, 18 Dec 2023 23:10:20 +0100:
On 18.12.2023 15:21, Miquel Raynal wrote:
Hi Rafał,
zaj...@gmail.com wrote on Mon, 18 Dec 2023 14:37:22 +0100:
From: Rafał Miłecki
This patch moves all generic (NVMEM devices independent) code from NVMEM
device driver to NVMEM layout driver. Then it adds a simple NVMEM layout
code on top of it.
Thanks to proper layout it's possible to support U-Boot env data stored
on any kind of NVMEM device.
For backward compatibility with old DT bindings we need to keep old
NVMEM device driver functional. To avoid code duplication a parsing
function is exported and reused in it.
Signed-off-by: Rafał Miłecki
---
I have a couple of comments about the original driver which gets
copy-pasted in the new layout driver, maybe you could clean these
(the memory leak should be fixed before the migration so it can be
backported easily, the others are just style so it can be done after, I
don't mind).
...
+int u_boot_env_parse(struct device *dev, struct nvmem_device *nvmem,
+ enum u_boot_env_format format)
+{
+ size_t crc32_data_offset;
+ size_t crc32_data_len;
+ size_t crc32_offset;
+ size_t data_offset;
+ size_t data_len;
+ size_t dev_size;
+ uint32_t crc32;
+ uint32_t calc;
+ uint8_t *buf;
+ int bytes;
+ int err;
+
+ dev_size = nvmem_dev_size(nvmem);
+
+ buf = kcalloc(1, dev_size, GFP_KERNEL);
Out of curiosity, why kcalloc(1,...) rather than kzalloc() ?
I used kcalloc() initially as I didn't need buffer to be zeroed.
I think kcalloc() initializes the memory to zero.
https://elixir.bootlin.com/linux/latest/source/include/linux/slab.h#L659
If you don't need it you can switch to kmalloc() instead, I don't mind,
but kcalloc() is meant to be used with arrays, I don't see the point of
using kcalloc() in this case.
I see that memory-allocation.rst however says:
> And, to be on the safe side it's best to use routines that set memory to
zero, like kzalloc().
It's probably close to zero cost to zero that buffer so it could be kzalloc().
+ if (!buf) {
+ err = -ENOMEM;
+ goto err_out;
We could directly return ENOMEM here I guess.
+ }
+
+ bytes = nvmem_device_read(nvmem, 0, dev_size, buf);
+ if (bytes < 0)
+ return bytes;
+ else if (bytes != dev_size)
+ return -EIO;
Don't we need to free buf in the above cases?
+ switch (format) {
+ case U_BOOT_FORMAT_SINGLE:
+ crc32_offset = offsetof(struct u_boot_env_image_single, crc32);
+ crc32_data_offset = offsetof(struct u_boot_env_image_single, data);
+ data_offset = offsetof(struct u_boot_env_image_single, data);
+ break;
+ case U_BOOT_FORMAT_REDUNDANT:
+ crc32_offset = offsetof(struct u_boot_env_image_redundant, crc32);
+ crc32_data_offset = offsetof(struct u_boot_env_image_redundant, data);
+ data_offset = offsetof(struct u_boot_env_image_redundant, data);
+ break;
+ case U_BOOT_FORMAT_BROADCOM:
+ crc32_offset = offsetof(struct u_boot_env_image_broadcom, crc32);
+ crc32_data_offset = offsetof(struct u_boot_env_image_broadcom, data);
+ data_offset = offsetof(struct u_boot_env_image_broadcom, data);
+ break;
+ }
+ crc32 = le32_to_cpu(*(__le32 *)(buf + crc32_offset));
Looks a bit convoluted, any chances we can use intermediate variables
to help decipher this?
+ crc32_data_len = dev_size - crc32_data_offset;
+ data_len = dev_size - data_offset;
+
+ calc = crc32(~0, buf + crc32_data_offset, crc32_data_len) ^ ~0L;
+ if (calc != crc32) {
+ dev_err(dev, "Invalid calculated CRC32: 0x%08x (expected: 0x%08x)\n",
calc, crc32);
+ err = -EINVAL;
+ goto err_kfree;
+ }
+
+ buf[dev_size - 1] = '\0';
+ err = u_boot_env_parse_cells(dev, nvmem, buf, data_offset, data_len);
+ if (err)
+ dev_err(dev, "Failed to add cells: %d\n", err);
Please drop this error message, the only reason for which the function
call would fail is apparently an ENOMEM case.
+
+err_kfree:
+ kfree(buf);
+err_out:
+ return err;
+}
+EXPORT_SYMBOL_GPL(u_boot_env_parse);
+
+static int u_boot_env_add_cells(struct device *dev, struct nvmem_device *nvmem)
+{
+ const struct of_device_id *match;
+ struct device_node *layout_np;
+ enum u_boot_env_format format;
+
+ layout_np = of_nvmem_layout_get_container(nvmem);
+ if (!layout_np)
+ return -ENOENT;
+
+ match = of_match_node(u_boot_env_of_match_table, layout_np);
+ if (!match)
+ return -ENOENT;
+
+ format = (uintptr_t)match->data;
In the core there is currently an unused helper called
nvmem_layout_get_match_data() which does that. I think the original
intent of this function was to be used in this driver, so depending on
your preference, can you please either use it or remove it?
The problem is that nvmem_layout_get_m
Re: Adding EFI runtime support to the Arm's FF-A bus
Hi Heinrich, > Any runtime device drivers for variable storage should not be in the > U-Boot runtime but live in the secure world (e.g. OP-TEE) FF-A is the > new ARM protocol for talking to the secure world and hence fits into > the picture. What if I just want a simple embedded boot stack where I don't want any secure world and just want to be able to boot a COTS linux distribution via EFI? Assuming, that there might be a simple dedicated EEPROM to store the variables which is not exposed to linux, is that something which would be rejected by u-boot mainline now? -michael
Re: [PATHv11 00/43] net/lwip: add lwip library for the network stack
Hello Maxim, Am Mon, Nov 27, 2023 at 06:56:43PM +0600 schrieb Maxim Uvarov: > Hello, > > Please find updated version of lwip patches. Changes are in the > changelog bellow. > > Thank you, > Maxim. > > changelog: > v11: - v11 is mosly respin of v10 patches with CI error fixes. > Gitlab CI: > > https://source.denx.de/u-boot/custodians/u-boot-tpm/-/pipelines/18368 > Azure CI: > > https://dev.azure.com/u-boot/u-boot/_build/results?buildId=7366&view=results > (Azure CI, which is connected to github. Sometime I can see > tftp timeout after some part of download there, but that can > not be > reproduced locally. While Gitblab CI is stable. Because of > num tries in > CI I suspect this CI was not always reliable.) > Azure and Gitlab also have different toolchains and I > would say Gitlab generates bigger code then Azure CI. > > Also many boards have a binary limit size of 800k (even > qemu has limits). And increased limits to fit all the code. > Specially did it > patch by board config to show which boards are failing to > build. There I have > a question if we really want to support new functionality for > old boards (mips, > arm32 and etc...). I hope board owners can help me if > it's valid to increase these limits. In general one can not simply increase that limit without knowing details on where U-Boot binary is supposed to be stored on a particular board. For example there are boards where U-Boot is stored on NAND flash with fixed sized (mtd) partitions. Changing the partition layout on a running board is quite risky from my point of view, so you can assume that partition sizes fixed at all times. Those sizes determine the limit however. That said: it has to be checked board by board if such a limit can be increased at all. Greets Alex > > In this version I used git submodules and friend CI with > submodules. But I don't mind if you decide to maintain it in a > different > way. > > > v10: - fix ping with following tftp command issue with incorrect > ping timeout clear. >- Makefile on make will init submodules and if needed will > do git clone. >- wget - some minor code style changes. > v9: - added first patch describing git submodule for lwip. So > the build procedure is: > git submodule init > git submodule update > make > - reworked a little bit dhcp cmd state polling > - fixed review comments for v8 > v8: - comments for previous review > - removed lwip timeout callback pointer > - made lwip timeouts works, that also allowed to remove > static vars. > - setenv for filesize tftp and wget has to be in hex. > - Makefile changes always compile it tftp,dns,wget,ping due > to it can be used not only by CONFIG_CMD_. > - Kconfig changes - simplify lwIP settings and support only > one configuration. > - tested with mini debian.iso load over http or tftp, mount > and boot it (qemu, arm64). > v7: - more review fixes. > - support of multiply eth devices, were "ethact" selects the > active device. > v6: - fixed review comments for v5 (thanks Ilias and Simon). > v5: - fixed Iliases comments and split big patch on the small > ones. > v4: - tested with tests/py/ did some minor fixes (out of tree > build, variables set after downloads). > - accounted review comments for documentation. > - implemented dns command > - corrected wget command to not use serverip variable and use just > url string. > v3: - use lwip commands for ping,tftp,wget,dhcp if this patch > applied. Drop CONFIG_LIB_LWIP_REPLACE_ option. > - docs: use rst variant and drop references to RFC. > > Maxim Uvarov (43): > submodule: add lwIP as git submodule > net/lwip: add doc/develop/net_lwip.rst > net/lwip: integrate lwIP library > net/lwip: implement dns cmd > net/lwip: implement dhcp cmd > net/lwip: implement tftp cmd > net/lwip: implement wget cmd > net/lwip: implement ping cmd > net/lwip: add lwIP configuration > net/lwip: implement lwIP port to U-Boot > net/lwip: update .gitignore with lwIP > net/lwip: connection between cmd and lwip apps > net/lwip: replace original net commands with lwip > net/lwip: split net.h to net.h, arp.h and eth.h > test_efi_loader.py: use $filesize var > test_net: print out net list > net: sandbox: fix NULL pointer derefences > net/smc911x: fix return from smc91
Re: [PATCH v2 0/2] ARM: meson: introduce GXL MDIO mux driver and switch to Linux v6.4 DT
Hi, On Wed, 13 Dec 2023 10:30:11 +0100, Neil Armstrong wrote: > Linux v6.4 uses a new MDIO mux driver for GXL boards, let's port the driver > to U-Boot and sync the GXBB/GXL/GXM DT to make use of this driver. > > Thanks, Applied to https://source.denx.de/u-boot/custodians/u-boot-amlogic (u-boot-amlogic-next) [1/2] net: Add Amlogic GXL MDIO Mux driver https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/b4534ddefff07a083c84c11d944460ed528df435 [2/2] ARM: dts: sync Amlogic GX DT to Linux v6.4 https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/4d4fbf04158a5b2d4fff5a35ea0a2d6c18d250cb -- Neil
AW: Using uart1 on mediatek mt8195 derived board
>El 2023-12-08 17:06, Thomas Schaefer va escriure:
>> Hi Macpaul, Fabien,
>>
>> I'm referring to patch series
>> https://patc/
>> hwork.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20230804110448.24589-1-ma
>> cpaul.lin%40mediatek.com%2F&data=05%7C02%7CThomas.Schaefer%40kontron.c
>> om%7C7254656e8bcd4aaa665608dc006d75f3%7C8c9d3c973fd941c8a2b1646f3942da
>> f1%7C0%7C0%7C638385717332491611%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLj
>> AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&s
>> data=eNa2nC%2BcBA8g8GC2z32nBO%2B4MvKIJGb2XU2lw3EqzTE%3D&reserved=0
>> where support for the mediatek mt8195 SOC is introduced into u-boot.
>> We are developing a board based on the mt8195 as well but we want to
>> use UART1 instead of UART0 for debug output messages.
>>
>> Our board is booting and we see boot messages on a debug pin header
>> connected to UART0 when using the settings from the demo board, but
>> when trying to switch to UART1, no more messages appear on the
>> console. What we have tried is the following:
>>
>> - Adaptation of the dts and dtsi files with uart1 settings taken from
>> linux device tree:
>>
>> diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi index
>> a7e4db5aa7..53eb437fad 100644
>> --- a/arch/arm/dts/mt8195.dtsi
>> +++ b/arch/arm/dts/mt8195.dtsi
>> @@ -245,6 +245,17 @@
>> status = "disabled";
>> };
>>
>> + uart1: serial@11001200 {
>> + compatible = "mediatek,mt8195-uart",
>> +"mediatek,hsuart";
>> + reg = <0 0x11001200 0 0x1000>;
>> + interrupts = ;
>> + clock-frequency = <2600>;
>> + clocks = <&clk26m>, <&clk26m>;
>> + clock-names = "baud", "bus";
>> + status = "disabled";
>> + };
>> +
>> pericfg_ao: syscon@11003000 {
>> compatible = "mediatek,mt8195-pericfg_ao",
>> "syscon";
>> reg = <0 0x11003000 0 0x1000>;
>>
>> diff --git a/arch/arm/dts/mt8195-kontron-sbc-i1200.dts
>> b/arch/arm/dts/mt8195-kontron-sbc-i1200.dts
>> index c6ea7e8f3d..4700a6d303 100644
>> --- a/arch/arm/dts/mt8195-kontron-sbc-i1200.dts
>> +++ b/arch/arm/dts/mt8195-kontron-sbc-i1200.dts
>> @@ -58,7 +58,7 @@
>> };
>>
>> chosen {
>> - stdout-path = &uart0;
>> + stdout-path = &uart1;
>> };
>>
>> reg_1p8v: regulator-1p8v {
>> @@ -121,7 +121,7 @@
>> status = "okay";
>> };
>>
>> -&uart0 {
>> +&uart1 {
>> status = "okay";
>> };
>>
>> We also tried to change the DEBUG_UART settings in the defconfig to
>> match with UART1, but without success.
>>
>> Are there any special means to make UART1 interface run?
>
>Did you had a look in the DTS from the kernel:
>https://elixir.bootlin.com/linux/v6.7-rc6/source/arch/arm64/boot/dts/mediatek/mt8195.dtsi#L1040
>
>My bet would be that infracfg_ao CLK_INFRA_AO_UART1 is not configured
>correctly.
>
>Best regards,
>Matthias.
>
Hi Matthias,
actually the problem was that we didn't enable some transceivers on UART1 line.
After fixing this, UART1 now works without problems.
Best regards,
Thomas
>>
>> Best regards,
>> Thomas
>>
>> Thomas Schäfer
>> SW Design Engineer
>>
>>
>> Kontron Europe GmbH
>> Heinrich-Barth-Straße 1-1a | 66115 Saarbrücken | Germany
Re: [PATCH v3 4/7] bcm2835: brcm,bcm2708-fb device is using r5g6b5 format
Hi Ivan,
Am 19.12.23 um 09:51 schrieb Ivan T. Ivanov:
On 12-18 23:32, Stefan Wahren wrote:
static const struct udevice_id bcm2835_video_ids[] = {
- { .compatible = "brcm,bcm2835-hdmi" },
- { .compatible = "brcm,bcm2711-hdmi0" },
- { .compatible = "brcm,bcm2708-fb" },
+ { .compatible = "brcm,bcm2835-hdmi", .data = VIDEO_BPP32},
+ { .compatible = "brcm,bcm2711-hdmi0", .data = VIDEO_BPP32},
+ { .compatible = "brcm,bcm2708-fb",.data = VIDEO_BPP16 },
this change looks wrong to me. Before we used VIDEO_BPP32 for
brcm,bcm2708-fb. I think it's hard to explain why we should downgrade
the other boards. I would expect some brcm,bcm2712 compatible at least
this needs an explanation in the commit message.
If you are confident that this semi device was working before with
BPP32 I will try to find better way to handle this. Do you remember
which RPi version was this?
as said before i'm don't have much experience with U-Boot, so i'm not
confident. But downgrading the bpp value for an existing setting only to
make RPi 5 work, isn't a good approach. It's a hack.
A quick search for the compatible revealed this [1], so it looks like a
fallback which applies to all Raspberry Pi boards with a firmware
provided DTB.
In case all of them uses 16 bit, i'm fine with this change but then the
commit log should mention this. I think these are points which needs to
be discussed with the Raspberry Pi guys.
Best regards
[1] - https://lists.denx.de/pipermail/u-boot/2018-July/333476.html
Thanks,
Ivan
RE: [PATCH 09/13] pinctrl: exynos: Add pinctrl support for Exynos850
> -Original Message- > From: U-Boot On Behalf Of Sam Protsenko > Sent: Wednesday, December 13, 2023 12:17 PM > To: Minkyu Kang ; Tom Rini ; > Lukasz Majewski ; Sean Anderson > Cc: Simon Glass ; Heinrich Schuchardt > ; u-boot@lists.denx.de > Subject: [PATCH 09/13] pinctrl: exynos: Add pinctrl support for Exynos850 > > Add pinctrl support for Exynos850 SoC. It was mostly extracted from > corresponding Linux kernel code [1]. Power down modes and external > interrupt data were removed while converting the code for U-Boot, but > everything else was kept almost unchanged. > > [1] drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > > Signed-off-by: Sam Protsenko > --- > drivers/pinctrl/exynos/Kconfig | 8 ++ > drivers/pinctrl/exynos/Makefile| 1 + > drivers/pinctrl/exynos/pinctrl-exynos850.c | 125 + > 3 files changed, 134 insertions(+) > create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos850.c > > diff --git a/drivers/pinctrl/exynos/Kconfig > b/drivers/pinctrl/exynos/Kconfig > index a60f49869b45..1b7fb62bc4ba 100644 > --- a/drivers/pinctrl/exynos/Kconfig > +++ b/drivers/pinctrl/exynos/Kconfig > @@ -16,3 +16,11 @@ config PINCTRL_EXYNOS78x0 > help > Support pin multiplexing and pin configuration control on > Samsung's Exynos78x0 SoC. > + > +config PINCTRL_EXYNOS850 > + bool "Samsung Exynos850 pinctrl driver" > + depends on ARCH_EXYNOS && PINCTRL_FULL > + select PINCTRL_EXYNOS > + help > + Support pin multiplexing and pin configuration control on > + Samsung's Exynos850 SoC. > diff --git a/drivers/pinctrl/exynos/Makefile > b/drivers/pinctrl/exynos/Makefile > index 07db970ca942..3abe1226eb74 100644 > --- a/drivers/pinctrl/exynos/Makefile > +++ b/drivers/pinctrl/exynos/Makefile > @@ -6,3 +6,4 @@ > obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o > obj-$(CONFIG_PINCTRL_EXYNOS7420) += pinctrl-exynos7420.o > obj-$(CONFIG_PINCTRL_EXYNOS78x0) += pinctrl-exynos78x0.o > +obj-$(CONFIG_PINCTRL_EXYNOS850) += pinctrl-exynos850.o > diff --git a/drivers/pinctrl/exynos/pinctrl-exynos850.c > b/drivers/pinctrl/exynos/pinctrl-exynos850.c > new file mode 100644 > index ..2445dd752ea8 > --- /dev/null > +++ b/drivers/pinctrl/exynos/pinctrl-exynos850.c > @@ -0,0 +1,125 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2023 Linaro Ltd. > + * Author: Sam Protsenko > + * > + * Samsung Exynos USI driver (Universal Serial Interface). Typo. It should be a subject for the pinctrl driver. Otherwise, Reviewed-by: Chanho Park
[RFC PATCH 01/16] dma: ti: k3-udma: Use ring_idx to pair k3 nav rings
Use ring_idx to pair rings. ring_idx will be same as tx flow_id for all
non-negative flow_ids. For negative flow_ids, ring_idx will be tchan->id
added with bchan_cnt.
Signed-off-by: MD Danish Anwar
---
drivers/dma/ti/k3-udma.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 8a62d63dfe..eea9ec9659 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -876,13 +876,20 @@ static int udma_alloc_tx_resources(struct udma_chan *uc)
{
struct k3_nav_ring_cfg ring_cfg;
struct udma_dev *ud = uc->ud;
- int ret;
+ struct udma_tchan *tchan;
+ int ring_idx, ret;
ret = udma_get_tchan(uc);
if (ret)
return ret;
- ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, uc->tchan->id, -1,
+ tchan = uc->tchan;
+ if (tchan->tflow_id >= 0)
+ ring_idx = tchan->tflow_id;
+ else
+ ring_idx = ud->bchan_cnt + tchan->id;
+
+ ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1,
&uc->tchan->t_ring,
&uc->tchan->tc_ring);
if (ret) {
--
2.34.1
[RFC PATCH 00/16] Introduce ICSSG Ethernet driver
Introduce ICSSG PRUETH support in uboot. The ICSSG driver is used in TI
AM654 SR2.0.
The ICSSG PRU Sub-system runs on EMAC firmware. This series Introduces
support for ICSSG driver in uboot. This series also adds the driver's
dependencies.
The ICSSG2 node is added in device tree overlay so that it remains in
sync with linux kernel.
The series introduces device tree and config changes and AM65x
to enable ICSSG driver. The series also enables SPL_LOAD_FIT_APPLY_OVERLAY
for AM65x in order to load overlay over spl.
This series has been tested on AM65x SR2.0, and the ICSSG interface is
able to ping / dhcp and boot kernel using tftp in uboot.
To use ICSSG2 ethernet, the ICSSG firmware needs to be loaded to PRU RPROC
cores and RPROC cores need to be booted with the firmware. This step is
done inside driver in kernel as kernel supports APIs like
rproc_set_firmware() and rproc_fw_boot(). But as u-boot doesn't have these
APIs, the same needs to be done via u-boot cmds.
To make sure icssg-eth works we need to do below steps.
1. Initialize rproc cores i.e. rproc_init()
2. Load $firmware_file from partition '1:2' (root) on device (mmc in this
example)
3. Load the firmware file to rproc cores passing. i.e. rproc_load()
taking rproc_id, loadaddr and file size as arguments.
4. Start rproc cores. i.e. rproc_start() taking rproc_id as arguments
The above steps are done by running the below commands at u-boot prompt.
=> setenv start_icssg2 'rproc start 14; rproc start 15; rproc start 16; rproc
start 17; rproc start 18; rproc start 19'
=> setenv stop_icssg2 'rproc stop 14; rproc stop 15; rproc stop 16; rproc stop
17; rproc stop 18; rproc stop 19'
=> setenv firmware_dir '/lib/firmware/ti-pruss'
=> setenv get_firmware_mmc 'load mmc ${bootpart} ${loadaddr}
${firmware_dir}/${firmware_file}'
=> setenv init_icssg2 'setenv ethact icssg2-eth; setenv autoload no; rproc
init; setenv loadaddr 0x8000; \
setenv firmware_file am65x-sr2-pru0-prueth-fw.elf; run get_firmware_mmc;
rproc load 14 0x8000 ${filesize}; \
setenv loadaddr 0x8900; setenv firmware_file
am65x-sr2-rtu0-prueth-fw.elf; run get_firmware_mmc; rproc load 15 0x8900
${filesize}; \
setenv loadaddr 0x9000; setenv firmware_file
am65x-sr2-txpru0-prueth-fw.elf; run get_firmware_mmc; rproc load 16 0x9000
${filesize}; \
setenv loadaddr 0x8000; setenv firmware_file
am65x-sr2-pru1-prueth-fw.elf; run get_firmware_mmc; rproc load 17 0x8000
${filesize}; \
setenv loadaddr 0x8900; setenv firmware_file
am65x-sr2-rtu1-prueth-fw.elf; run get_firmware_mmc; rproc load 18 0x8900
${filesize}; \
setenv loadaddr 0x9000; setenv firmware_file
am65x-sr2-txpru1-prueth-fw.elf; run get_firmware_mmc; rproc load 19 0x9000
${filesize}; \
run start_icssg2;'
=> run init_icssg2
=> dhcp
k3-navss-ringacc ringacc@3c00: Ring Accelerator probed rings:818,
gp-rings[304,100] sci-dev-id:187
k3-navss-ringacc ringacc@3c00: dma-ring-reset-quirk: disabled
prueth icssg2-eth: K3 ICSSG: rflow_id_base: 8, chn_name = rx0
link up on port 0, speed 1000, full duplex
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
DHCP client bound to address 192.168.4.58 (1020 ms)
Thanks and Regards,
MD Danish Anwar
MD Danish Anwar (16):
net: ti: icssg: Add Firmware Interface for ICSSG Ethernet driver.
net: ti: icssg: Add Firmware config and classification APIs.
net: ti: icssg: Add icssg queues APIs and macros
net: ti: icssg: Add ICSSG ethernet driver
net: ti: icssg: Add support sending FDB command to update rx_flow_id
net: ti: icssg: Enforce pinctrl state on the MDIO child node
arm: dts: k3-am65: Add additional regs for DMA components
arm: dts: k3-am65: Add cfg reg region to ringacc node
arm: dts: k3-am65-main: Add ICSSG IEP nodes
arm: dts: k3-am654-base-board: Add ICSSG2 Ethernet support
arm: dts: k3-am65x-binman: Add ICSSG2 overlay and configuration
configs: am65x_evm_a53: Enable ICSSG Driver
configs: am65x_evm_a53_defconfig: add SPL_LOAD_FIT_APPLY_OVERLAY
tools/fdtgrep: Include __symbols__ table
board: ti: am65x: Add check for k3-am654-icssg2 in
board_fit_config_match()
Revert "dm: core: Report bootph-pre-ram/sram node as pre-reloc after
relocation"
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/k3-am65-main.dtsi| 49 ++-
arch/arm/dts/k3-am65-mcu.dtsi | 13 +-
arch/arm/dts/k3-am654-icssg2.dtso | 145 +++
arch/arm/dts/k3-am65x-binman.dtsi | 85
board/ti/am65x/evm.c | 11 +-
configs/am65x_evm_a53_defconfig | 4 +
drivers/core/ofnode.c | 2 +-
drivers/net/ti/Kconfig| 9 +
drivers/net/ti/Makefile | 1 +
drivers/net/ti/icss_mii_rt.h | 192 +
drivers/net/ti/icssg_classifier.c | 376 +
drivers/net/ti/icssg_config.c | 469 +
drivers/net/ti/icssg_config.h | 195 +
drivers/net/ti/icssg_prueth.c | 654 ++
dri
[PATCH V3] ARM add initial support for the Phytium Pe2201 Board.
From: TracyMg_Li
Add pe2201 platform code and the device tree of pe2201 platform board.
The initial support comprises the UART and PCIe.
Signed-off-by: TracyMg_Li
Changes since v1:
fix space corrupt.
Changes since v2:
switch to bootstd and text environment.
---
arch/arm/Kconfig | 7 ++
arch/arm/dts/Makefile| 1 +
arch/arm/dts/phytium-pe2201.dts | 43 +++
board/phytium/pe2201/Kconfig | 12 ++
board/phytium/pe2201/MAINTAINERS | 8 ++
board/phytium/pe2201/Makefile| 12 ++
board/phytium/pe2201/cpu.h | 64 +++
board/phytium/pe2201/ddr.c | 190 +++
board/phytium/pe2201/pcie.c | 60 ++
board/phytium/pe2201/pe2201.c| 92 +++
board/phytium/pe2201/pe2201.env | 12 ++
board/phytium/pe2201/pll.c | 75
board/phytium/pe2201/sec.c | 37 ++
configs/pe2201_defconfig | 41 +++
include/configs/pe2201.h | 22
15 files changed, 676 insertions(+)
create mode 100644 arch/arm/dts/phytium-pe2201.dts
create mode 100644 board/phytium/pe2201/Kconfig
create mode 100644 board/phytium/pe2201/MAINTAINERS
create mode 100644 board/phytium/pe2201/Makefile
create mode 100644 board/phytium/pe2201/cpu.h
create mode 100644 board/phytium/pe2201/ddr.c
create mode 100644 board/phytium/pe2201/pcie.c
create mode 100644 board/phytium/pe2201/pe2201.c
create mode 100644 board/phytium/pe2201/pe2201.env
create mode 100644 board/phytium/pe2201/pll.c
create mode 100644 board/phytium/pe2201/sec.c
create mode 100644 configs/pe2201_defconfig
create mode 100644 include/configs/pe2201.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d812685c98..358c515a93 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2060,6 +2060,12 @@ config TARGET_POMELO
Support for pomelo platform.
It has 8GB Sdram, uart and pcie.
+config TARGET_PE2201
+ bool "Support Phytium PE2201 Platform"
+ select ARM64
+ help
+ Support for pe2201 platform.It has 2GB Sdram, uart and pcie.
+
config TARGET_PRESIDIO_ASIC
bool "Support Cortina Presidio ASIC Platform"
select ARM64
@@ -2336,6 +2342,7 @@ source "board/variscite/dart_6ul/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/phytium/durian/Kconfig"
source "board/phytium/pomelo/Kconfig"
+source "board/phytium/pe2201/Kconfig"
source "board/xen/xenguest_arm64/Kconfig"
source "arch/arm/Kconfig.debug"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5fc888680b..ce2fc626b0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1469,6 +1469,7 @@ dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb
+dtb-$(CONFIG_TARGET_PE2201) += phytium-pe2201.dtb
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
diff --git a/arch/arm/dts/phytium-pe2201.dts b/arch/arm/dts/phytium-pe2201.dts
new file mode 100644
index 00..959584fbbb
--- /dev/null
+++ b/arch/arm/dts/phytium-pe2201.dts
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Phytium pe2201 board
+ * Copyright (C) 2023, Phytium Technology Co., Ltd.
+ * lixinde
+ * weichangzheng
+ */
+/dts-v1/;
+
+/ {
+ model = "Phytium pe2201 Board";
+ compatible = "phytium,pe2201";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ uart0: serial@2800c000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x2800c000 0x0 0x1000>;
+ clock = <1>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ pcie@4000 {
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0x0 0x4000 0x0 0x1000>;
+ ranges = <0x0100 0x00 0x 0x0 0x5000 0x0
0x00F0>,
+ <0x0200 0x00 0x5800 0x0 0x5800 0x0
0x2800>,
+ <0x4300 0x10 0x 0x10 0x 0x10
0x>;
+ };
+ };
+};
diff --git a/board/phytium/pe2201/Kconfig b/board/phytium/pe2201/Kconfig
new file mode 100644
index 00..f2f222b5d3
--- /dev/null
+++ b/board/phytium/pe2201/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PE2201
+
+config SYS_BOARD
+ default "pe2201"
+
+config SYS_VENDOR
+ default "phytium"
+
+config SYS_CONFIG_NAME
+ default "pe2201"
+
+endif
diff --git a/board/phytium/pe2201/MAINTAINERS b/board/phytium/pe2201/MAINTAINERS
new file mode 100644
ind
[RFC PATCH 01/16] net: ti: icssg: Add Firmware Interface for ICSSG Ethernet driver.
Add firmware interface related headers and macros for ICSSG Ethernet driver. These macros will be later used by the ICSSG ethernet driver. Signed-off-by: MD Danish Anwar --- drivers/net/ti/icssg_switch_map.h | 209 ++ 1 file changed, 209 insertions(+) create mode 100644 drivers/net/ti/icssg_switch_map.h diff --git a/drivers/net/ti/icssg_switch_map.h b/drivers/net/ti/icssg_switch_map.h new file mode 100644 index 00..ba87a44023 --- /dev/null +++ b/drivers/net/ti/icssg_switch_map.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Texas Instruments ICSSG Ethernet driver + * + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#ifndef __NET_TI_ICSSG_SWITCH_MAP_H +#define __NET_TI_ICSSG_SWITCH_MAP_H + +/*Time after which FDB entries are checked for aged out values. Value in nanoseconds*/ +#define FDB_AGEING_TIMEOUT_OFFSET 0x0014 + +/*default VLAN tag for Host Port*/ +#define HOST_PORT_DF_VLAN_OFFSET 0x001C + +/*Same as HOST_PORT_DF_VLAN_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET HOST_PORT_DF_VLAN_OFFSET + +/*default VLAN tag for P1 Port*/ +#define P1_PORT_DF_VLAN_OFFSET 0x0020 + +/*Same as P1_PORT_DF_VLAN_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET P1_PORT_DF_VLAN_OFFSET + +/*default VLAN tag for P2 Port*/ +#define P2_PORT_DF_VLAN_OFFSET 0x0024 + +/*Same as P2_PORT_DF_VLAN_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET P2_PORT_DF_VLAN_OFFSET + +/*VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000*/ +#define VLAN_STATIC_REG_TABLE_OFFSET 0x0100 + +/*VLAN-FID Table offset for EMAC*/ +#define EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET VLAN_STATIC_REG_TABLE_OFFSET + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC0_HI 0x2104 + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC0_LO 0x2F6C + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC1_HI 0x3DD4 + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC1_LO 0x4C3C + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC0_HI 0x5AA4 + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC0_LO 0x5F0C + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC1_HI 0x6374 + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC1_LO 0x67DC + +/*special packet descriptor Q reserved memory*/ +#define HOST_SPPD0 0x7AAC + +/*special packet descriptor Q reserved memory*/ +#define HOST_SPPD1 0x7EAC + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_CYCLECOUNT_OFFSET 0x83EC + +/*IEP count hi roll over count*/ +#define TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET0x83F4 + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET 0x83F8 + +/*Set clock descriptor*/ +#define TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET0x83FC + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET 0x843C + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_COUNT_OFFSET 0x8440 + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET 0x8444 + +/*Control variable to generate SYNC1*/ +#define TIMESYNC_FW_WC_ISOM_PIN_SIGNAL_EN_OFFSET 0x844C + +/*SystemTime Sync0 periodicity*/ +#define TIMESYNC_FW_ST_SYNCOUT_PERIOD_OFFSET 0x8450 + +/*pktTxDelay for P1 = link speed dependent p1 mac delay + p1 phy delay*/ +#define TIMESYNC_FW_WC_PKTTXDELAY_P1_OFFSET0x8454 + +/*pktTxDelay for P2 = link speed dependent p2 mac delay + p2 phy delay*/ +#define TIMESYNC_FW_WC_PKTTXDELAY_P2_OFFSET0x8458 + +/*Set clock operation done signal for next task*/ +#define TIMESYNC_FW_SIG_PNFW_OFFSET0x845C + +/*Set clock operation done signal for next task*/ +#define TIMESYNC_FW_SIG_TIMESYNCFW_OFFSET 0x8460 + +/*New list is copied at this time*/ +#define TAS_CONFIG_CHANGE_TIME 0x000C + +/*config change error counter*/ +#define TAS_CONFIG_CHANGE_ERROR_COUNTER0x0014 + +/*TAS List update pending flag*/ +#define TAS_CONFIG_PENDING 0x0018 + +/*TAS list update trigger flag*/ +#define TAS_CONFIG_CHANGE 0x0019 + +/*List length for new TAS schedule*/ +#define TAS_ADMIN_LIST_LENGTH 0x001A + +/*Currently active TAS list index*/ +#define TAS_ACTIVE_LI
[RFC PATCH 02/16] net: ti: icssg: Add Firmware Interface for ICSSG Ethernet driver.
Add firmware interface related headers and macros for ICSSG Ethernet driver. These macros will be later used by the ICSSG ethernet driver. Signed-off-by: MD Danish Anwar --- drivers/net/ti/icssg_switch_map.h | 209 ++ 1 file changed, 209 insertions(+) create mode 100644 drivers/net/ti/icssg_switch_map.h diff --git a/drivers/net/ti/icssg_switch_map.h b/drivers/net/ti/icssg_switch_map.h new file mode 100644 index 00..ba87a44023 --- /dev/null +++ b/drivers/net/ti/icssg_switch_map.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Texas Instruments ICSSG Ethernet driver + * + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#ifndef __NET_TI_ICSSG_SWITCH_MAP_H +#define __NET_TI_ICSSG_SWITCH_MAP_H + +/*Time after which FDB entries are checked for aged out values. Value in nanoseconds*/ +#define FDB_AGEING_TIMEOUT_OFFSET 0x0014 + +/*default VLAN tag for Host Port*/ +#define HOST_PORT_DF_VLAN_OFFSET 0x001C + +/*Same as HOST_PORT_DF_VLAN_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET HOST_PORT_DF_VLAN_OFFSET + +/*default VLAN tag for P1 Port*/ +#define P1_PORT_DF_VLAN_OFFSET 0x0020 + +/*Same as P1_PORT_DF_VLAN_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET P1_PORT_DF_VLAN_OFFSET + +/*default VLAN tag for P2 Port*/ +#define P2_PORT_DF_VLAN_OFFSET 0x0024 + +/*Same as P2_PORT_DF_VLAN_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET P2_PORT_DF_VLAN_OFFSET + +/*VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000*/ +#define VLAN_STATIC_REG_TABLE_OFFSET 0x0100 + +/*VLAN-FID Table offset for EMAC*/ +#define EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET VLAN_STATIC_REG_TABLE_OFFSET + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC0_HI 0x2104 + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC0_LO 0x2F6C + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC1_HI 0x3DD4 + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC1_LO 0x4C3C + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC0_HI 0x5AA4 + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC0_LO 0x5F0C + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC1_HI 0x6374 + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC1_LO 0x67DC + +/*special packet descriptor Q reserved memory*/ +#define HOST_SPPD0 0x7AAC + +/*special packet descriptor Q reserved memory*/ +#define HOST_SPPD1 0x7EAC + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_CYCLECOUNT_OFFSET 0x83EC + +/*IEP count hi roll over count*/ +#define TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET0x83F4 + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET 0x83F8 + +/*Set clock descriptor*/ +#define TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET0x83FC + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET 0x843C + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_COUNT_OFFSET 0x8440 + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET 0x8444 + +/*Control variable to generate SYNC1*/ +#define TIMESYNC_FW_WC_ISOM_PIN_SIGNAL_EN_OFFSET 0x844C + +/*SystemTime Sync0 periodicity*/ +#define TIMESYNC_FW_ST_SYNCOUT_PERIOD_OFFSET 0x8450 + +/*pktTxDelay for P1 = link speed dependent p1 mac delay + p1 phy delay*/ +#define TIMESYNC_FW_WC_PKTTXDELAY_P1_OFFSET0x8454 + +/*pktTxDelay for P2 = link speed dependent p2 mac delay + p2 phy delay*/ +#define TIMESYNC_FW_WC_PKTTXDELAY_P2_OFFSET0x8458 + +/*Set clock operation done signal for next task*/ +#define TIMESYNC_FW_SIG_PNFW_OFFSET0x845C + +/*Set clock operation done signal for next task*/ +#define TIMESYNC_FW_SIG_TIMESYNCFW_OFFSET 0x8460 + +/*New list is copied at this time*/ +#define TAS_CONFIG_CHANGE_TIME 0x000C + +/*config change error counter*/ +#define TAS_CONFIG_CHANGE_ERROR_COUNTER0x0014 + +/*TAS List update pending flag*/ +#define TAS_CONFIG_PENDING 0x0018 + +/*TAS list update trigger flag*/ +#define TAS_CONFIG_CHANGE 0x0019 + +/*List length for new TAS schedule*/ +#define TAS_ADMIN_LIST_LENGTH 0x001A + +/*Currently active TAS list index*/ +#define TAS_ACTIVE_LI
[RFC PATCH 02/16] net: ti: icssg: Add Firmware config and classification APIs.
Add icssg_config.h / .c and icssg_classifier.c files. These are firmware configuration and classification related files. Add MII helper APIs and MACROs. These APIs and MACROs will be later used by ICSSG Ethernet driver. Also introduce icssg_prueth.h which has definition of prueth related structures. Signed-off-by: MD Danish Anwar --- drivers/net/ti/icss_mii_rt.h | 192 ++ drivers/net/ti/icssg_classifier.c | 376 drivers/net/ti/icssg_config.c | 403 ++ drivers/net/ti/icssg_config.h | 177 + drivers/net/ti/icssg_prueth.h | 78 ++ 5 files changed, 1226 insertions(+) create mode 100644 drivers/net/ti/icss_mii_rt.h create mode 100644 drivers/net/ti/icssg_classifier.c create mode 100644 drivers/net/ti/icssg_config.c create mode 100644 drivers/net/ti/icssg_config.h create mode 100644 drivers/net/ti/icssg_prueth.h diff --git a/drivers/net/ti/icss_mii_rt.h b/drivers/net/ti/icss_mii_rt.h new file mode 100644 index 00..6b2449e736 --- /dev/null +++ b/drivers/net/ti/icss_mii_rt.h @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* PRU-ICSS MII_RT register definitions + * + * Copyright (C) 2015-2020 Texas Instruments Incorporated - http://www.ti.com + */ + +#ifndef __NET_PRUSS_MII_RT_H__ +#define __NET_PRUSS_MII_RT_H__ + +#include + +/* PRUSS_MII_RT Registers */ +#define PRUSS_MII_RT_RXCFG00x0 +#define PRUSS_MII_RT_RXCFG10x4 +#define PRUSS_MII_RT_TXCFG00x10 +#define PRUSS_MII_RT_TXCFG10x14 +#define PRUSS_MII_RT_TX_CRC0 0x20 +#define PRUSS_MII_RT_TX_CRC1 0x24 +#define PRUSS_MII_RT_TX_IPG0 0x30 +#define PRUSS_MII_RT_TX_IPG1 0x34 +#define PRUSS_MII_RT_PRS0 0x38 +#define PRUSS_MII_RT_PRS1 0x3c +#define PRUSS_MII_RT_RX_FRMS0 0x40 +#define PRUSS_MII_RT_RX_FRMS1 0x44 +#define PRUSS_MII_RT_RX_PCNT0 0x48 +#define PRUSS_MII_RT_RX_PCNT1 0x4c +#define PRUSS_MII_RT_RX_ERR0 0x50 +#define PRUSS_MII_RT_RX_ERR1 0x54 + +/* PRUSS_MII_RT_RXCFG0/1 bits */ +#define PRUSS_MII_RT_RXCFG_RX_ENABLE BIT(0) +#define PRUSS_MII_RT_RXCFG_RX_DATA_RDY_MODE_DISBIT(1) +#define PRUSS_MII_RT_RXCFG_RX_CUT_PREAMBLE BIT(2) +#define PRUSS_MII_RT_RXCFG_RX_MUX_SEL BIT(3) +#define PRUSS_MII_RT_RXCFG_RX_L2_ENBIT(4) +#define PRUSS_MII_RT_RXCFG_RX_BYTE_SWAPBIT(5) +#define PRUSS_MII_RT_RXCFG_RX_AUTO_FWD_PRE BIT(6) +#define PRUSS_MII_RT_RXCFG_RX_L2_EOF_SCLR_DIS BIT(9) + +/* PRUSS_MII_RT_TXCFG0/1 bits */ +#define PRUSS_MII_RT_TXCFG_TX_ENABLE BIT(0) +#define PRUSS_MII_RT_TXCFG_TX_AUTO_PREAMBLEBIT(1) +#define PRUSS_MII_RT_TXCFG_TX_EN_MODE BIT(2) +#define PRUSS_MII_RT_TXCFG_TX_BYTE_SWAPBIT(3) +#define PRUSS_MII_RT_TXCFG_TX_MUX_SEL BIT(8) +#define PRUSS_MII_RT_TXCFG_PRE_TX_AUTO_SEQUENCEBIT(9) +#define PRUSS_MII_RT_TXCFG_PRE_TX_AUTO_ESC_ERR BIT(10) +#define PRUSS_MII_RT_TXCFG_TX_32_MODE_EN BIT(11) +#define PRUSS_MII_RT_TXCFG_TX_IPG_WIRE_CLK_EN BIT(12) /* SR2.0 onwards */ + +#define PRUSS_MII_RT_TXCFG_TX_START_DELAY_SHIFT16 +#define PRUSS_MII_RT_TXCFG_TX_START_DELAY_MASK GENMASK(25, 16) + +#define PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_SHIFT 28 +#define PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_MASK GENMASK(30, 28) + +/* PRUSS_MII_RT_TX_IPG0/1 bits */ +#define PRUSS_MII_RT_TX_IPG_IPG_SHIFT 0 +#define PRUSS_MII_RT_TX_IPG_IPG_MASK GENMASK(9, 0) + +/* PRUSS_MII_RT_PRS0/1 bits */ +#define PRUSS_MII_RT_PRS_COL BIT(0) +#define PRUSS_MII_RT_PRS_CRS BIT(1) + +/* PRUSS_MII_RT_RX_FRMS0/1 bits */ +#define PRUSS_MII_RT_RX_FRMS_MIN_FRM_SHIFT 0 +#define PRUSS_MII_RT_RX_FRMS_MIN_FRM_MASK GENMASK(15, 0) + +#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_SHIFT 16 +#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_MASK GENMASK(31, 16) + +/* Min/Max in MII_RT_RX_FRMS */ +/* For EMAC and Switch */ +#define PRUSS_MII_RT_RX_FRMS_MAX (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) +#define PRUSS_MII_RT_RX_FRMS_MIN_FRM (64) + +/* for HSR and PRP */ +#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_LRE (PRUSS_MII_RT_RX_FRMS_MAX + \ +ICSS_LRE_TAG_RCT_SIZE) +/* PRUSS_MII_RT_RX_PCNT0/1 bits */ +#define PRUSS_MII_RT_RX_PCNT_MIN_PCNT_SHIFT0 +#define PRUSS_MII_RT_RX_PCNT_MIN_PCNT_MASK GENMASK(3, 0) + +#define PRUSS_MII_RT_RX_PCNT_MAX_PCNT_SHIFT4 +#define PRUSS_MII_RT_RX_PCNT_MAX_PCNT_MASK GENMASK(7, 4) + +/* PRUSS_MII_RT_RX_ERR0/1 bits */ +#define PRUSS_MII_RT_RX_ERR_MIN_PCNT_ERR BIT(0) +#define PRUSS_MII_RT_RX_ERR_MAX_PCNT_ERR BIT(1) +#define PRUSS_MII_RT_RX_ERR_MIN_FRM_ERRBIT(2) +#define PRUSS_MII_RT_RX_ERR_MAX_FRM_ERRBIT(3) + +#define ICSSG_CFG_OFFSET 0 +#define RGMII_CFG_OFFSET 4 + +/* Constant to choose between MII0 and MII1 */ +#define ICSS_MII0 0 +#define ICSS_MII1
[RFC PATCH 03/16] net: ti: icssg: Add Firmware config and classification APIs.
Add icssg_config.h / .c and icssg_classifier.c files. These are firmware configuration and classification related files. Add MII helper APIs and MACROs. These APIs and MACROs will be later used by ICSSG Ethernet driver. Also introduce icssg_prueth.h which has definition of prueth related structures. Signed-off-by: MD Danish Anwar --- drivers/net/ti/icss_mii_rt.h | 192 ++ drivers/net/ti/icssg_classifier.c | 376 drivers/net/ti/icssg_config.c | 403 ++ drivers/net/ti/icssg_config.h | 177 + drivers/net/ti/icssg_prueth.h | 78 ++ 5 files changed, 1226 insertions(+) create mode 100644 drivers/net/ti/icss_mii_rt.h create mode 100644 drivers/net/ti/icssg_classifier.c create mode 100644 drivers/net/ti/icssg_config.c create mode 100644 drivers/net/ti/icssg_config.h create mode 100644 drivers/net/ti/icssg_prueth.h diff --git a/drivers/net/ti/icss_mii_rt.h b/drivers/net/ti/icss_mii_rt.h new file mode 100644 index 00..6b2449e736 --- /dev/null +++ b/drivers/net/ti/icss_mii_rt.h @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* PRU-ICSS MII_RT register definitions + * + * Copyright (C) 2015-2020 Texas Instruments Incorporated - http://www.ti.com + */ + +#ifndef __NET_PRUSS_MII_RT_H__ +#define __NET_PRUSS_MII_RT_H__ + +#include + +/* PRUSS_MII_RT Registers */ +#define PRUSS_MII_RT_RXCFG00x0 +#define PRUSS_MII_RT_RXCFG10x4 +#define PRUSS_MII_RT_TXCFG00x10 +#define PRUSS_MII_RT_TXCFG10x14 +#define PRUSS_MII_RT_TX_CRC0 0x20 +#define PRUSS_MII_RT_TX_CRC1 0x24 +#define PRUSS_MII_RT_TX_IPG0 0x30 +#define PRUSS_MII_RT_TX_IPG1 0x34 +#define PRUSS_MII_RT_PRS0 0x38 +#define PRUSS_MII_RT_PRS1 0x3c +#define PRUSS_MII_RT_RX_FRMS0 0x40 +#define PRUSS_MII_RT_RX_FRMS1 0x44 +#define PRUSS_MII_RT_RX_PCNT0 0x48 +#define PRUSS_MII_RT_RX_PCNT1 0x4c +#define PRUSS_MII_RT_RX_ERR0 0x50 +#define PRUSS_MII_RT_RX_ERR1 0x54 + +/* PRUSS_MII_RT_RXCFG0/1 bits */ +#define PRUSS_MII_RT_RXCFG_RX_ENABLE BIT(0) +#define PRUSS_MII_RT_RXCFG_RX_DATA_RDY_MODE_DISBIT(1) +#define PRUSS_MII_RT_RXCFG_RX_CUT_PREAMBLE BIT(2) +#define PRUSS_MII_RT_RXCFG_RX_MUX_SEL BIT(3) +#define PRUSS_MII_RT_RXCFG_RX_L2_ENBIT(4) +#define PRUSS_MII_RT_RXCFG_RX_BYTE_SWAPBIT(5) +#define PRUSS_MII_RT_RXCFG_RX_AUTO_FWD_PRE BIT(6) +#define PRUSS_MII_RT_RXCFG_RX_L2_EOF_SCLR_DIS BIT(9) + +/* PRUSS_MII_RT_TXCFG0/1 bits */ +#define PRUSS_MII_RT_TXCFG_TX_ENABLE BIT(0) +#define PRUSS_MII_RT_TXCFG_TX_AUTO_PREAMBLEBIT(1) +#define PRUSS_MII_RT_TXCFG_TX_EN_MODE BIT(2) +#define PRUSS_MII_RT_TXCFG_TX_BYTE_SWAPBIT(3) +#define PRUSS_MII_RT_TXCFG_TX_MUX_SEL BIT(8) +#define PRUSS_MII_RT_TXCFG_PRE_TX_AUTO_SEQUENCEBIT(9) +#define PRUSS_MII_RT_TXCFG_PRE_TX_AUTO_ESC_ERR BIT(10) +#define PRUSS_MII_RT_TXCFG_TX_32_MODE_EN BIT(11) +#define PRUSS_MII_RT_TXCFG_TX_IPG_WIRE_CLK_EN BIT(12) /* SR2.0 onwards */ + +#define PRUSS_MII_RT_TXCFG_TX_START_DELAY_SHIFT16 +#define PRUSS_MII_RT_TXCFG_TX_START_DELAY_MASK GENMASK(25, 16) + +#define PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_SHIFT 28 +#define PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_MASK GENMASK(30, 28) + +/* PRUSS_MII_RT_TX_IPG0/1 bits */ +#define PRUSS_MII_RT_TX_IPG_IPG_SHIFT 0 +#define PRUSS_MII_RT_TX_IPG_IPG_MASK GENMASK(9, 0) + +/* PRUSS_MII_RT_PRS0/1 bits */ +#define PRUSS_MII_RT_PRS_COL BIT(0) +#define PRUSS_MII_RT_PRS_CRS BIT(1) + +/* PRUSS_MII_RT_RX_FRMS0/1 bits */ +#define PRUSS_MII_RT_RX_FRMS_MIN_FRM_SHIFT 0 +#define PRUSS_MII_RT_RX_FRMS_MIN_FRM_MASK GENMASK(15, 0) + +#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_SHIFT 16 +#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_MASK GENMASK(31, 16) + +/* Min/Max in MII_RT_RX_FRMS */ +/* For EMAC and Switch */ +#define PRUSS_MII_RT_RX_FRMS_MAX (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) +#define PRUSS_MII_RT_RX_FRMS_MIN_FRM (64) + +/* for HSR and PRP */ +#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_LRE (PRUSS_MII_RT_RX_FRMS_MAX + \ +ICSS_LRE_TAG_RCT_SIZE) +/* PRUSS_MII_RT_RX_PCNT0/1 bits */ +#define PRUSS_MII_RT_RX_PCNT_MIN_PCNT_SHIFT0 +#define PRUSS_MII_RT_RX_PCNT_MIN_PCNT_MASK GENMASK(3, 0) + +#define PRUSS_MII_RT_RX_PCNT_MAX_PCNT_SHIFT4 +#define PRUSS_MII_RT_RX_PCNT_MAX_PCNT_MASK GENMASK(7, 4) + +/* PRUSS_MII_RT_RX_ERR0/1 bits */ +#define PRUSS_MII_RT_RX_ERR_MIN_PCNT_ERR BIT(0) +#define PRUSS_MII_RT_RX_ERR_MAX_PCNT_ERR BIT(1) +#define PRUSS_MII_RT_RX_ERR_MIN_FRM_ERRBIT(2) +#define PRUSS_MII_RT_RX_ERR_MAX_FRM_ERRBIT(3) + +#define ICSSG_CFG_OFFSET 0 +#define RGMII_CFG_OFFSET 4 + +/* Constant to choose between MII0 and MII1 */ +#define ICSS_MII0 0 +#define ICSS_MII1
[RFC PATCH 03/16] net: ti: icssg: Add icssg queues APIs and macros
Add icssg_queue.c file. This file introduces macros and APIs related to
ICSSG queues. These will be used by ICSSG Ethernet driver.
Signed-off-by: MD Danish Anwar
---
drivers/net/ti/icssg_prueth.h | 5
drivers/net/ti/icssg_queues.c | 51 +++
2 files changed, 56 insertions(+)
create mode 100644 drivers/net/ti/icssg_queues.c
diff --git a/drivers/net/ti/icssg_prueth.h b/drivers/net/ti/icssg_prueth.h
index 26b77dd8f3..f34ab5d6d4 100644
--- a/drivers/net/ti/icssg_prueth.h
+++ b/drivers/net/ti/icssg_prueth.h
@@ -75,4 +75,9 @@ void icssg_config_ipg(struct prueth *prueth, int speed, int
mii);
int icssg_config(struct prueth *prueth);
int emac_set_port_state(struct prueth *prueth, enum icssg_port_state_cmd cmd);
+/* Buffer queue helpers */
+int icssg_queue_pop(struct prueth *prueth, u8 queue);
+void icssg_queue_push(struct prueth *prueth, int queue, u16 addr);
+u32 icssg_queue_level(struct prueth *prueth, int queue);
+
#endif /* __NET_TI_ICSSG_PRUETH_H */
diff --git a/drivers/net/ti/icssg_queues.c b/drivers/net/ti/icssg_queues.c
new file mode 100644
index 00..6a95ef5d58
--- /dev/null
+++ b/drivers/net/ti/icssg_queues.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0
+/* ICSSG Buffer queue helpers
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#include
+#include
+#include "icssg_prueth.h"
+
+#define ICSSG_QUEUES_MAX 64
+#define ICSSG_QUEUE_OFFSET 0xd00
+#define ICSSG_QUEUE_PEEK_OFFSET0xe00
+#define ICSSG_QUEUE_CNT_OFFSET 0xe40
+#defineICSSG_QUEUE_RESET_OFFSET0xf40
+
+int icssg_queue_pop(struct prueth *prueth, u8 queue)
+{
+ u32 val, cnt;
+
+ if (queue >= ICSSG_QUEUES_MAX)
+ return -EINVAL;
+
+ regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, &cnt);
+ if (!cnt)
+ return -EINVAL;
+
+ regmap_read(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, &val);
+
+ return val;
+}
+
+void icssg_queue_push(struct prueth *prueth, int queue, u16 addr)
+{
+ if (queue >= ICSSG_QUEUES_MAX)
+ return;
+
+ regmap_write(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, addr);
+}
+
+u32 icssg_queue_level(struct prueth *prueth, int queue)
+{
+ u32 reg;
+
+ if (queue >= ICSSG_QUEUES_MAX)
+ return 0;
+
+ regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, ®);
+
+ return reg;
+}
--
2.34.1
[RFC PATCH 04/16] net: ti: icssg: Add ICSSG ethernet driver
This is the PURSS Ethernet driver for TI AM654 Sr2.0 and laterSoCs
with the ICSSG PRU Sub-system running EMAC firmware.
This driver caters to either of the slices(pru/rtu pair)
of the icssg subsystem.
One and exactly one of the slices is supported
as the u-boot ethernet supports probing one interface
at a time.
Signed-off-by: MD Danish Anwar
---
drivers/net/ti/Kconfig| 8 +
drivers/net/ti/Makefile | 1 +
drivers/net/ti/icssg_prueth.c | 589 ++
3 files changed, 598 insertions(+)
create mode 100644 drivers/net/ti/icssg_prueth.c
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index c75f418628..9fead2c7ce 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -49,3 +49,11 @@ config TI_AM65_CPSW_NUSS
help
This driver supports TI K3 MCU CPSW Nuss Ethernet controller
in Texas Instruments K3 AM65x SoCs.
+
+config TI_ICSSG_PRUETH
+ bool "TI Gigabit PRU Ethernet driver"
+ depends on ARCH_K3
+ select PHYLIB
+ help
+ Support Gigabit Ethernet ports over the ICSSG PRU Subsystem
+ This subsystem is available starting with the AM65 platform.
diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile
index 0ce0cf2828..5af760572f 100644
--- a/drivers/net/ti/Makefile
+++ b/drivers/net/ti/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o
obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o
obj-$(CONFIG_TI_AM65_CPSW_NUSS) += am65-cpsw-nuss.o cpsw_mdio.o
+obj-$(CONFIG_TI_ICSSG_PRUETH) += icssg_prueth.o cpsw_mdio.o icssg_classifier.o
icssg_config.o icssg_queues.o
diff --git a/drivers/net/ti/icssg_prueth.c b/drivers/net/ti/icssg_prueth.c
new file mode 100644
index 00..9cc700eca5
--- /dev/null
+++ b/drivers/net/ti/icssg_prueth.c
@@ -0,0 +1,589 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 AM65 PRU Ethernet Driver
+ *
+ * Copyright (C) 2019-2021, Texas Instruments, Incorporated
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "cpsw_mdio.h"
+#include "icssg_prueth.h"
+#include "icss_mii_rt.h"
+
+#define ICSS_SLICE0 0
+#define ICSS_SLICE1 1
+
+#ifdef PKTSIZE_ALIGN
+#define UDMA_RX_BUF_SIZE PKTSIZE_ALIGN
+#else
+#define UDMA_RX_BUF_SIZE ALIGN(1522, ARCH_DMA_MINALIGN)
+#endif
+
+#ifdef PKTBUFSRX
+#define UDMA_RX_DESC_NUM PKTBUFSRX
+#else
+#define UDMA_RX_DESC_NUM 4
+#endif
+
+/* Config region lies in shared RAM */
+#define ICSS_CONFIG_OFFSET_SLICE0 0
+#define ICSS_CONFIG_OFFSET_SLICE1 0x8000
+
+/* Firmware flags */
+#define ICSS_SET_RUN_FLAG_VLAN_ENABLE BIT(0) /* switch only */
+#define ICSS_SET_RUN_FLAG_FLOOD_UNICASTBIT(1) /* switch only
*/
+#define ICSS_SET_RUN_FLAG_PROMISC BIT(2) /* MAC only */
+#define ICSS_SET_RUN_FLAG_MULTICAST_PROMISCBIT(3) /* MAC only */
+
+/* CTRLMMR_ICSSG_RGMII_CTRL register bits */
+#define ICSSG_CTRL_RGMII_ID_MODE BIT(24)
+
+/* Management packet type */
+#define PRUETH_PKT_TYPE_CMD0x10
+
+static int icssg_phy_init(struct udevice *dev)
+{
+ struct prueth *priv = dev_get_priv(dev);
+ struct phy_device *phydev;
+ u32 supported = PHY_GBIT_FEATURES;
+ int ret;
+
+ phydev = phy_connect(priv->bus,
+priv->phy_addr,
+priv->dev,
+priv->phy_interface);
+
+ if (!phydev) {
+ dev_err(dev, "phy_connect() failed\n");
+ return -ENODEV;
+ }
+
+ /* disable unsupported features */
+ supported &= ~(PHY_10BT_FEATURES |
+ SUPPORTED_100baseT_Half |
+ SUPPORTED_1000baseT_Half |
+ SUPPORTED_Pause |
+ SUPPORTED_Asym_Pause);
+
+ phydev->supported &= supported;
+ phydev->advertising = phydev->supported;
+
+ if (IS_ENABLED(CONFIG_DM_ETH))
+ if (ofnode_valid(priv->phy_node))
+ phydev->node = priv->phy_node;
+
+ priv->phydev = phydev;
+ ret = phy_config(phydev);
+ if (ret < 0)
+ pr_err("phy_config() failed: %d", ret);
+
+ return ret;
+}
+
+static int icssg_mdio_init(struct udevice *dev)
+{
+ struct prueth *prueth = dev_get_priv(dev);
+
+ prueth->bus = cpsw_mdio_init(dev->name, prueth->mdio_base,
+prueth->mdio_freq,
+clk_get_rate(&prueth->mdiofck),
+prueth->mdio_manual_mode);
+ if (!prueth->bus)
+ return -EFAULT;
+
+ return 0;
+}
+
+static void icssg_config_set_speed(struct prueth *priv, int speed)
+{
+
[RFC PATCH 04/16] net: ti: icssg: Add icssg queues APIs and macros
Add icssg_queue.c file. This file introduces macros and APIs related to
ICSSG queues. These will be used by ICSSG Ethernet driver.
Signed-off-by: MD Danish Anwar
---
drivers/net/ti/icssg_prueth.h | 5
drivers/net/ti/icssg_queues.c | 51 +++
2 files changed, 56 insertions(+)
create mode 100644 drivers/net/ti/icssg_queues.c
diff --git a/drivers/net/ti/icssg_prueth.h b/drivers/net/ti/icssg_prueth.h
index 26b77dd8f3..f34ab5d6d4 100644
--- a/drivers/net/ti/icssg_prueth.h
+++ b/drivers/net/ti/icssg_prueth.h
@@ -75,4 +75,9 @@ void icssg_config_ipg(struct prueth *prueth, int speed, int
mii);
int icssg_config(struct prueth *prueth);
int emac_set_port_state(struct prueth *prueth, enum icssg_port_state_cmd cmd);
+/* Buffer queue helpers */
+int icssg_queue_pop(struct prueth *prueth, u8 queue);
+void icssg_queue_push(struct prueth *prueth, int queue, u16 addr);
+u32 icssg_queue_level(struct prueth *prueth, int queue);
+
#endif /* __NET_TI_ICSSG_PRUETH_H */
diff --git a/drivers/net/ti/icssg_queues.c b/drivers/net/ti/icssg_queues.c
new file mode 100644
index 00..6a95ef5d58
--- /dev/null
+++ b/drivers/net/ti/icssg_queues.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0
+/* ICSSG Buffer queue helpers
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#include
+#include
+#include "icssg_prueth.h"
+
+#define ICSSG_QUEUES_MAX 64
+#define ICSSG_QUEUE_OFFSET 0xd00
+#define ICSSG_QUEUE_PEEK_OFFSET0xe00
+#define ICSSG_QUEUE_CNT_OFFSET 0xe40
+#defineICSSG_QUEUE_RESET_OFFSET0xf40
+
+int icssg_queue_pop(struct prueth *prueth, u8 queue)
+{
+ u32 val, cnt;
+
+ if (queue >= ICSSG_QUEUES_MAX)
+ return -EINVAL;
+
+ regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, &cnt);
+ if (!cnt)
+ return -EINVAL;
+
+ regmap_read(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, &val);
+
+ return val;
+}
+
+void icssg_queue_push(struct prueth *prueth, int queue, u16 addr)
+{
+ if (queue >= ICSSG_QUEUES_MAX)
+ return;
+
+ regmap_write(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, addr);
+}
+
+u32 icssg_queue_level(struct prueth *prueth, int queue)
+{
+ u32 reg;
+
+ if (queue >= ICSSG_QUEUES_MAX)
+ return 0;
+
+ regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, ®);
+
+ return reg;
+}
--
2.34.1
[RFC PATCH 05/16] net: ti: icssg: Add support sending FDB command to update rx_flow_id
ICSSG firmware supports FDB commands. Add support to send FDB commands
from driver. Once rx_flow_id is obtained from dma, let firmware know that
we are using this rx_flow_id by sending a FDB command.
Signed-off-by: MD Danish Anwar
---
drivers/net/ti/icssg_config.c | 66 +++
drivers/net/ti/icssg_config.h | 18 ++
drivers/net/ti/icssg_prueth.c | 6
drivers/net/ti/icssg_prueth.h | 6
4 files changed, 96 insertions(+)
diff --git a/drivers/net/ti/icssg_config.c b/drivers/net/ti/icssg_config.c
index 33298c3374..7e11ef128f 100644
--- a/drivers/net/ti/icssg_config.c
+++ b/drivers/net/ti/icssg_config.c
@@ -9,6 +9,7 @@
#include "icssg_switch_map.h"
#include "icss_mii_rt.h"
#include
+#include
/* TX IPG Values to be set for 100M and 1G link speeds. These values are
* in ocp_clk cycles. So need change if ocp_clk is changed for a specific
@@ -401,3 +402,68 @@ int emac_set_port_state(struct prueth *prueth,
return ret;
}
+
+int icssg_send_fdb_msg(struct prueth *prueth, struct mgmt_cmd *cmd,
+ struct mgmt_cmd_rsp *rsp)
+{
+ int slice = prueth->slice;
+ int ret, addr;
+
+ addr = icssg_queue_pop(prueth, slice == 0 ?
+ ICSSG_CMD_POP_SLICE0 : ICSSG_CMD_POP_SLICE1);
+ if (addr < 0)
+ return addr;
+
+ /* First 4 bytes have FW owned buffer linking info which should
+* not be touched
+*/
+ memcpy_toio((void __iomem *)prueth->shram.pa + addr + 4, cmd,
sizeof(*cmd));
+ icssg_queue_push(prueth, slice == 0 ?
+ICSSG_CMD_PUSH_SLICE0 : ICSSG_CMD_PUSH_SLICE1, addr);
+ ret = read_poll_timeout(icssg_queue_pop, addr, addr >= 0,
+ 2000, 2000, prueth, slice == 0 ?
+ ICSSG_RSP_POP_SLICE0 : ICSSG_RSP_POP_SLICE1);
+
+ if (ret) {
+ dev_err(prueth->dev, "Timedout sending HWQ message\n");
+ return ret;
+ }
+
+ memcpy_fromio(rsp, (void __iomem *)prueth->shram.pa + addr,
sizeof(*rsp));
+ /* Return buffer back for to pool */
+ icssg_queue_push(prueth, slice == 0 ?
+ICSSG_RSP_PUSH_SLICE0 : ICSSG_RSP_PUSH_SLICE1, addr);
+
+ return 0;
+}
+
+int emac_fdb_flow_id_updated(struct prueth *prueth)
+{
+ struct mgmt_cmd_rsp fdb_cmd_rsp = { 0 };
+ int slice = prueth->slice;
+ struct mgmt_cmd fdb_cmd = { 0 };
+ int ret = 0;
+
+ fdb_cmd.header = ICSSG_FW_MGMT_CMD_HEADER;
+ fdb_cmd.type = ICSSG_FW_MGMT_FDB_CMD_TYPE_RX_FLOW;
+ fdb_cmd.seqnum = ++(prueth->icssg_hwcmdseq);
+ fdb_cmd.param = 0;
+
+ fdb_cmd.param |= (slice << 4);
+ fdb_cmd.cmd_args[0] = 0;
+
+ ret = icssg_send_fdb_msg(prueth, &fdb_cmd, &fdb_cmd_rsp);
+ if (ret)
+ return ret;
+
+ if (fdb_cmd.seqnum != fdb_cmd_rsp.seqnum) {
+ dev_err(prueth->dev, "seqnum doesn't match, cmd.seqnum %d !=
rsp.seqnum %d\n",
+ fdb_cmd.seqnum, fdb_cmd_rsp.seqnum);
+ return -EINVAL;
+ }
+
+ if (fdb_cmd_rsp.status == 1)
+ return 0;
+
+ return -EINVAL;
+}
diff --git a/drivers/net/ti/icssg_config.h b/drivers/net/ti/icssg_config.h
index fc6eae0426..156127bd3d 100644
--- a/drivers/net/ti/icssg_config.h
+++ b/drivers/net/ti/icssg_config.h
@@ -80,6 +80,7 @@ struct icssg_rxq_ctx {
#define ICSSG_FW_MGMT_FDB_CMD_TYPE 0x03
#define ICSSG_FW_MGMT_CMD_TYPE 0x04
#define ICSSG_FW_MGMT_PKT 0x8000
+#define ICSSG_FW_MGMT_FDB_CMD_TYPE_RX_FLOW 0x05
struct icssg_r30_cmd {
u32 cmd[4];
@@ -156,6 +157,23 @@ struct icssg_setclock_desc {
u32 CMP0_new;
} __packed;
+struct mgmt_cmd {
+ u8 param;
+ u8 seqnum;
+ u8 type;
+ u8 header;
+ u32 cmd_args[3];
+} __packed;
+
+struct mgmt_cmd_rsp {
+ u32 reserved;
+ u8 status;
+ u8 seqnum;
+ u8 type;
+ u8 header;
+ u32 cmd_args[3];
+} __packed;
+
#define ICSSG_CMD_POP_SLICE0 56
#define ICSSG_CMD_POP_SLICE1 60
diff --git a/drivers/net/ti/icssg_prueth.c b/drivers/net/ti/icssg_prueth.c
index 9cc700eca5..1a7445a015 100644
--- a/drivers/net/ti/icssg_prueth.c
+++ b/drivers/net/ti/icssg_prueth.c
@@ -225,6 +225,12 @@ static int prueth_start(struct udevice *dev)
dev_info(dev, "K3 ICSSG: rflow_id_base: %u, chn_name = %s\n",
dma_rx_cfg_data->flow_id_base, chn_name);
+ ret = emac_fdb_flow_id_updated(priv);
+ if (ret) {
+ dev_err(dev, "Failed to update Rx Flow ID %d", ret);
+ goto phy_fail;
+ }
+
ret = phy_startup(priv->phydev);
if (ret) {
dev_err(dev, "phy_startup failed\n");
diff --git a/drivers/net/ti/icssg_prueth.h b/drivers/net/ti/icssg_prueth.h
index f34ab5d6d4..e41ed16a05 100644
--- a/drivers/net/ti/icssg_prueth.h
+++ b/drivers/net/ti/icssg_p
[RFC PATCH 05/16] net: ti: icssg: Add ICSSG ethernet driver
This is the PURSS Ethernet driver for TI AM654 Sr2.0 and laterSoCs
with the ICSSG PRU Sub-system running EMAC firmware.
This driver caters to either of the slices(pru/rtu pair)
of the icssg subsystem.
One and exactly one of the slices is supported
as the u-boot ethernet supports probing one interface
at a time.
Signed-off-by: MD Danish Anwar
---
drivers/net/ti/Kconfig| 8 +
drivers/net/ti/Makefile | 1 +
drivers/net/ti/icssg_prueth.c | 589 ++
3 files changed, 598 insertions(+)
create mode 100644 drivers/net/ti/icssg_prueth.c
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index c75f418628..9fead2c7ce 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -49,3 +49,11 @@ config TI_AM65_CPSW_NUSS
help
This driver supports TI K3 MCU CPSW Nuss Ethernet controller
in Texas Instruments K3 AM65x SoCs.
+
+config TI_ICSSG_PRUETH
+ bool "TI Gigabit PRU Ethernet driver"
+ depends on ARCH_K3
+ select PHYLIB
+ help
+ Support Gigabit Ethernet ports over the ICSSG PRU Subsystem
+ This subsystem is available starting with the AM65 platform.
diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile
index 0ce0cf2828..5af760572f 100644
--- a/drivers/net/ti/Makefile
+++ b/drivers/net/ti/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o
obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o
obj-$(CONFIG_TI_AM65_CPSW_NUSS) += am65-cpsw-nuss.o cpsw_mdio.o
+obj-$(CONFIG_TI_ICSSG_PRUETH) += icssg_prueth.o cpsw_mdio.o icssg_classifier.o
icssg_config.o icssg_queues.o
diff --git a/drivers/net/ti/icssg_prueth.c b/drivers/net/ti/icssg_prueth.c
new file mode 100644
index 00..9cc700eca5
--- /dev/null
+++ b/drivers/net/ti/icssg_prueth.c
@@ -0,0 +1,589 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 AM65 PRU Ethernet Driver
+ *
+ * Copyright (C) 2019-2021, Texas Instruments, Incorporated
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "cpsw_mdio.h"
+#include "icssg_prueth.h"
+#include "icss_mii_rt.h"
+
+#define ICSS_SLICE0 0
+#define ICSS_SLICE1 1
+
+#ifdef PKTSIZE_ALIGN
+#define UDMA_RX_BUF_SIZE PKTSIZE_ALIGN
+#else
+#define UDMA_RX_BUF_SIZE ALIGN(1522, ARCH_DMA_MINALIGN)
+#endif
+
+#ifdef PKTBUFSRX
+#define UDMA_RX_DESC_NUM PKTBUFSRX
+#else
+#define UDMA_RX_DESC_NUM 4
+#endif
+
+/* Config region lies in shared RAM */
+#define ICSS_CONFIG_OFFSET_SLICE0 0
+#define ICSS_CONFIG_OFFSET_SLICE1 0x8000
+
+/* Firmware flags */
+#define ICSS_SET_RUN_FLAG_VLAN_ENABLE BIT(0) /* switch only */
+#define ICSS_SET_RUN_FLAG_FLOOD_UNICASTBIT(1) /* switch only
*/
+#define ICSS_SET_RUN_FLAG_PROMISC BIT(2) /* MAC only */
+#define ICSS_SET_RUN_FLAG_MULTICAST_PROMISCBIT(3) /* MAC only */
+
+/* CTRLMMR_ICSSG_RGMII_CTRL register bits */
+#define ICSSG_CTRL_RGMII_ID_MODE BIT(24)
+
+/* Management packet type */
+#define PRUETH_PKT_TYPE_CMD0x10
+
+static int icssg_phy_init(struct udevice *dev)
+{
+ struct prueth *priv = dev_get_priv(dev);
+ struct phy_device *phydev;
+ u32 supported = PHY_GBIT_FEATURES;
+ int ret;
+
+ phydev = phy_connect(priv->bus,
+priv->phy_addr,
+priv->dev,
+priv->phy_interface);
+
+ if (!phydev) {
+ dev_err(dev, "phy_connect() failed\n");
+ return -ENODEV;
+ }
+
+ /* disable unsupported features */
+ supported &= ~(PHY_10BT_FEATURES |
+ SUPPORTED_100baseT_Half |
+ SUPPORTED_1000baseT_Half |
+ SUPPORTED_Pause |
+ SUPPORTED_Asym_Pause);
+
+ phydev->supported &= supported;
+ phydev->advertising = phydev->supported;
+
+ if (IS_ENABLED(CONFIG_DM_ETH))
+ if (ofnode_valid(priv->phy_node))
+ phydev->node = priv->phy_node;
+
+ priv->phydev = phydev;
+ ret = phy_config(phydev);
+ if (ret < 0)
+ pr_err("phy_config() failed: %d", ret);
+
+ return ret;
+}
+
+static int icssg_mdio_init(struct udevice *dev)
+{
+ struct prueth *prueth = dev_get_priv(dev);
+
+ prueth->bus = cpsw_mdio_init(dev->name, prueth->mdio_base,
+prueth->mdio_freq,
+clk_get_rate(&prueth->mdiofck),
+prueth->mdio_manual_mode);
+ if (!prueth->bus)
+ return -EFAULT;
+
+ return 0;
+}
+
+static void icssg_config_set_speed(struct prueth *priv, int speed)
+{
+
[RFC PATCH 06/16] net: ti: icssg: Add support sending FDB command to update rx_flow_id
ICSSG firmware supports FDB commands. Add support to send FDB commands
from driver. Once rx_flow_id is obtained from dma, let firmware know that
we are using this rx_flow_id by sending a FDB command.
Signed-off-by: MD Danish Anwar
---
drivers/net/ti/icssg_config.c | 66 +++
drivers/net/ti/icssg_config.h | 18 ++
drivers/net/ti/icssg_prueth.c | 6
drivers/net/ti/icssg_prueth.h | 6
4 files changed, 96 insertions(+)
diff --git a/drivers/net/ti/icssg_config.c b/drivers/net/ti/icssg_config.c
index 33298c3374..7e11ef128f 100644
--- a/drivers/net/ti/icssg_config.c
+++ b/drivers/net/ti/icssg_config.c
@@ -9,6 +9,7 @@
#include "icssg_switch_map.h"
#include "icss_mii_rt.h"
#include
+#include
/* TX IPG Values to be set for 100M and 1G link speeds. These values are
* in ocp_clk cycles. So need change if ocp_clk is changed for a specific
@@ -401,3 +402,68 @@ int emac_set_port_state(struct prueth *prueth,
return ret;
}
+
+int icssg_send_fdb_msg(struct prueth *prueth, struct mgmt_cmd *cmd,
+ struct mgmt_cmd_rsp *rsp)
+{
+ int slice = prueth->slice;
+ int ret, addr;
+
+ addr = icssg_queue_pop(prueth, slice == 0 ?
+ ICSSG_CMD_POP_SLICE0 : ICSSG_CMD_POP_SLICE1);
+ if (addr < 0)
+ return addr;
+
+ /* First 4 bytes have FW owned buffer linking info which should
+* not be touched
+*/
+ memcpy_toio((void __iomem *)prueth->shram.pa + addr + 4, cmd,
sizeof(*cmd));
+ icssg_queue_push(prueth, slice == 0 ?
+ICSSG_CMD_PUSH_SLICE0 : ICSSG_CMD_PUSH_SLICE1, addr);
+ ret = read_poll_timeout(icssg_queue_pop, addr, addr >= 0,
+ 2000, 2000, prueth, slice == 0 ?
+ ICSSG_RSP_POP_SLICE0 : ICSSG_RSP_POP_SLICE1);
+
+ if (ret) {
+ dev_err(prueth->dev, "Timedout sending HWQ message\n");
+ return ret;
+ }
+
+ memcpy_fromio(rsp, (void __iomem *)prueth->shram.pa + addr,
sizeof(*rsp));
+ /* Return buffer back for to pool */
+ icssg_queue_push(prueth, slice == 0 ?
+ICSSG_RSP_PUSH_SLICE0 : ICSSG_RSP_PUSH_SLICE1, addr);
+
+ return 0;
+}
+
+int emac_fdb_flow_id_updated(struct prueth *prueth)
+{
+ struct mgmt_cmd_rsp fdb_cmd_rsp = { 0 };
+ int slice = prueth->slice;
+ struct mgmt_cmd fdb_cmd = { 0 };
+ int ret = 0;
+
+ fdb_cmd.header = ICSSG_FW_MGMT_CMD_HEADER;
+ fdb_cmd.type = ICSSG_FW_MGMT_FDB_CMD_TYPE_RX_FLOW;
+ fdb_cmd.seqnum = ++(prueth->icssg_hwcmdseq);
+ fdb_cmd.param = 0;
+
+ fdb_cmd.param |= (slice << 4);
+ fdb_cmd.cmd_args[0] = 0;
+
+ ret = icssg_send_fdb_msg(prueth, &fdb_cmd, &fdb_cmd_rsp);
+ if (ret)
+ return ret;
+
+ if (fdb_cmd.seqnum != fdb_cmd_rsp.seqnum) {
+ dev_err(prueth->dev, "seqnum doesn't match, cmd.seqnum %d !=
rsp.seqnum %d\n",
+ fdb_cmd.seqnum, fdb_cmd_rsp.seqnum);
+ return -EINVAL;
+ }
+
+ if (fdb_cmd_rsp.status == 1)
+ return 0;
+
+ return -EINVAL;
+}
diff --git a/drivers/net/ti/icssg_config.h b/drivers/net/ti/icssg_config.h
index fc6eae0426..156127bd3d 100644
--- a/drivers/net/ti/icssg_config.h
+++ b/drivers/net/ti/icssg_config.h
@@ -80,6 +80,7 @@ struct icssg_rxq_ctx {
#define ICSSG_FW_MGMT_FDB_CMD_TYPE 0x03
#define ICSSG_FW_MGMT_CMD_TYPE 0x04
#define ICSSG_FW_MGMT_PKT 0x8000
+#define ICSSG_FW_MGMT_FDB_CMD_TYPE_RX_FLOW 0x05
struct icssg_r30_cmd {
u32 cmd[4];
@@ -156,6 +157,23 @@ struct icssg_setclock_desc {
u32 CMP0_new;
} __packed;
+struct mgmt_cmd {
+ u8 param;
+ u8 seqnum;
+ u8 type;
+ u8 header;
+ u32 cmd_args[3];
+} __packed;
+
+struct mgmt_cmd_rsp {
+ u32 reserved;
+ u8 status;
+ u8 seqnum;
+ u8 type;
+ u8 header;
+ u32 cmd_args[3];
+} __packed;
+
#define ICSSG_CMD_POP_SLICE0 56
#define ICSSG_CMD_POP_SLICE1 60
diff --git a/drivers/net/ti/icssg_prueth.c b/drivers/net/ti/icssg_prueth.c
index 9cc700eca5..1a7445a015 100644
--- a/drivers/net/ti/icssg_prueth.c
+++ b/drivers/net/ti/icssg_prueth.c
@@ -225,6 +225,12 @@ static int prueth_start(struct udevice *dev)
dev_info(dev, "K3 ICSSG: rflow_id_base: %u, chn_name = %s\n",
dma_rx_cfg_data->flow_id_base, chn_name);
+ ret = emac_fdb_flow_id_updated(priv);
+ if (ret) {
+ dev_err(dev, "Failed to update Rx Flow ID %d", ret);
+ goto phy_fail;
+ }
+
ret = phy_startup(priv->phydev);
if (ret) {
dev_err(dev, "phy_startup failed\n");
diff --git a/drivers/net/ti/icssg_prueth.h b/drivers/net/ti/icssg_prueth.h
index f34ab5d6d4..e41ed16a05 100644
--- a/drivers/net/ti/icssg_prueth.h
+++ b/drivers/net/ti/icssg_p
[RFC PATCH 06/16] net: ti: icssg: Enforce pinctrl state on the MDIO child node
The binding represents the MDIO controller as a child device tree
node of the MAC device tree node.
The U-Boot driver mostly ignores that child device tree node and just
hardcodes the resources it uses to support both the MAC and MDIO in a
single driver.
However, some resources like pinctrl muxing states are thus ignored.
This has been a problem with some device trees that will put some
pinctrl states on the MDIO device tree node.
Let's rework the driver a bit to create a dummy MDIO driver that we will
then get during our initialization to force the core to select the right
muxing.
Signed-off-by: MD Danish Anwar
---
drivers/net/ti/Kconfig| 1 +
drivers/net/ti/icssg_prueth.c | 59 +++
2 files changed, 60 insertions(+)
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index 9fead2c7ce..6935b70e12 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -53,6 +53,7 @@ config TI_AM65_CPSW_NUSS
config TI_ICSSG_PRUETH
bool "TI Gigabit PRU Ethernet driver"
depends on ARCH_K3
+ imply DM_MDIO
select PHYLIB
help
Support Gigabit Ethernet ports over the ICSSG PRU Subsystem
diff --git a/drivers/net/ti/icssg_prueth.c b/drivers/net/ti/icssg_prueth.c
index 1a7445a015..40ad827e49 100644
--- a/drivers/net/ti/icssg_prueth.c
+++ b/drivers/net/ti/icssg_prueth.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -100,9 +101,56 @@ static int icssg_phy_init(struct udevice *dev)
return ret;
}
+static ofnode prueth_find_mdio(ofnode parent)
+{
+ ofnode node;
+
+ ofnode_for_each_subnode(node, parent)
+ if (ofnode_device_is_compatible(node, "ti,davinci_mdio"))
+ return node;
+
+ return ofnode_null();
+}
+
+static int prueth_mdio_setup(struct udevice *dev)
+{
+ struct prueth *priv = dev_get_priv(dev);
+ struct udevice *mdio_dev;
+ ofnode mdio;
+ int ret;
+
+ mdio = prueth_find_mdio(dev_ofnode(priv->pruss));
+ if (!ofnode_valid(mdio))
+ return 0;
+
+ /*
+* The MDIO controller is represented in the DT binding by a
+* subnode of the MAC controller.
+*
+* We don't have a DM driver for the MDIO device yet, and thus any
+* pinctrl setting on its node will be ignored.
+*
+* However, we do need to make sure the pins states tied to the
+* MDIO node are configured properly. Fortunately, the core DM
+* does that for use when we get a device, so we can work around
+* that whole issue by just requesting a dummy MDIO driver to
+* probe, and our pins will get muxed.
+*/
+ ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, &mdio_dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static int icssg_mdio_init(struct udevice *dev)
{
struct prueth *prueth = dev_get_priv(dev);
+ int ret;
+
+ ret = prueth_mdio_setup(dev);
+ if (ret)
+ return ret;
prueth->bus = cpsw_mdio_init(dev->name, prueth->mdio_base,
prueth->mdio_freq,
@@ -593,3 +641,14 @@ U_BOOT_DRIVER(prueth) = {
.plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
+
+static const struct udevice_id prueth_mdio_ids[] = {
+ { .compatible = "ti,davinci_mdio" },
+ { }
+};
+
+U_BOOT_DRIVER(prueth_mdio) = {
+ .name = "prueth_mdio",
+ .id = UCLASS_MDIO,
+ .of_match = prueth_mdio_ids,
+};
--
2.34.1
[RFC PATCH 07/16] arm: dts: k3-am65: Add additional regs for DMA components
Add additional reg properties for UDMA and RingAcc nodes which are mostly used by bootloader components before Device Manager firmware services are available, in order to setup DMA transfers. Signed-off-by: MD Danish Anwar --- arch/arm/dts/k3-am65-main.dtsi | 8 ++-- arch/arm/dts/k3-am65-mcu.dtsi | 8 ++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index ba4e5d3e1e..691c9978e6 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -616,8 +616,12 @@ compatible = "ti,am654-navss-main-udmap"; reg = <0x0 0x3115 0x0 0x100>, <0x0 0x3400 0x0 0x10>, - <0x0 0x3500 0x0 0x10>; - reg-names = "gcfg", "rchanrt", "tchanrt"; + <0x0 0x3500 0x0 0x10>, + <0x0 0x30b0 0x0 0x2>, + <0x0 0x30c0 0x0 0x8000>, + <0x0 0x30d0 0x0 0x4000>; + reg-names = "gcfg", "rchanrt", "tchanrt", + "tchan", "rchan", "rflow"; msi-parent = <&inta_main_udmass>; #dma-cells = <1>; diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi index c93ff1520a..d7111aa8b2 100644 --- a/arch/arm/dts/k3-am65-mcu.dtsi +++ b/arch/arm/dts/k3-am65-mcu.dtsi @@ -142,8 +142,12 @@ compatible = "ti,am654-navss-mcu-udmap"; reg = <0x0 0x285c 0x0 0x100>, <0x0 0x2a80 0x0 0x4>, - <0x0 0x2aa0 0x0 0x4>; - reg-names = "gcfg", "rchanrt", "tchanrt"; + <0x0 0x2aa0 0x0 0x4>, + <0x0 0x284a 0x0 0x4000>, + <0x0 0x284c 0x0 0x4000>, + <0x0 0x2840 0x0 0x2000>; + reg-names = "gcfg", "rchanrt", "tchanrt", + "tchan", "rchan", "rflow"; msi-parent = <&inta_main_udmass>; #dma-cells = <1>; -- 2.34.1
[RFC PATCH 08/16] arm: dts: k3-am65: Add additional regs for DMA components
Add additional reg properties for UDMA and RingAcc nodes which are mostly used by bootloader components before Device Manager firmware services are available, in order to setup DMA transfers. Signed-off-by: MD Danish Anwar --- arch/arm/dts/k3-am65-main.dtsi | 8 ++-- arch/arm/dts/k3-am65-mcu.dtsi | 8 ++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index ba4e5d3e1e..691c9978e6 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -616,8 +616,12 @@ compatible = "ti,am654-navss-main-udmap"; reg = <0x0 0x3115 0x0 0x100>, <0x0 0x3400 0x0 0x10>, - <0x0 0x3500 0x0 0x10>; - reg-names = "gcfg", "rchanrt", "tchanrt"; + <0x0 0x3500 0x0 0x10>, + <0x0 0x30b0 0x0 0x2>, + <0x0 0x30c0 0x0 0x8000>, + <0x0 0x30d0 0x0 0x4000>; + reg-names = "gcfg", "rchanrt", "tchanrt", + "tchan", "rchan", "rflow"; msi-parent = <&inta_main_udmass>; #dma-cells = <1>; diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi index c93ff1520a..d7111aa8b2 100644 --- a/arch/arm/dts/k3-am65-mcu.dtsi +++ b/arch/arm/dts/k3-am65-mcu.dtsi @@ -142,8 +142,12 @@ compatible = "ti,am654-navss-mcu-udmap"; reg = <0x0 0x285c 0x0 0x100>, <0x0 0x2a80 0x0 0x4>, - <0x0 0x2aa0 0x0 0x4>; - reg-names = "gcfg", "rchanrt", "tchanrt"; + <0x0 0x2aa0 0x0 0x4>, + <0x0 0x284a 0x0 0x4000>, + <0x0 0x284c 0x0 0x4000>, + <0x0 0x2840 0x0 0x2000>; + reg-names = "gcfg", "rchanrt", "tchanrt", + "tchan", "rchan", "rflow"; msi-parent = <&inta_main_udmass>; #dma-cells = <1>; -- 2.34.1
[RFC PATCH 09/16] arm: dts: k3-am65: Add cfg reg region to ringacc node
Add register range of ringacc cfg node to k3-am65* dtsi files. This is normally under Device Management firmware control but some entities like bootloader have to access directly and thus required to be present in DT. Signed-off-by: MD Danish Anwar --- arch/arm/dts/k3-am65-main.dtsi | 5 +++-- arch/arm/dts/k3-am65-mcu.dtsi | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index 691c9978e6..7f10520236 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -603,8 +603,9 @@ reg = <0x0 0x3c00 0x0 0x40>, <0x0 0x3800 0x0 0x40>, <0x0 0x3112 0x0 0x100>, - <0x0 0x3300 0x0 0x4>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x3300 0x0 0x4>, + <0x0 0x3108 0x0 0x4>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <818>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi index d7111aa8b2..b7f0456de7 100644 --- a/arch/arm/dts/k3-am65-mcu.dtsi +++ b/arch/arm/dts/k3-am65-mcu.dtsi @@ -129,8 +129,9 @@ reg = <0x0 0x2b80 0x0 0x40>, <0x0 0x2b00 0x0 0x40>, <0x0 0x2859 0x0 0x100>, - <0x0 0x2a50 0x0 0x4>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x2a50 0x0 0x4>, + <0x0 0x2844 0x0 0x4>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; -- 2.34.1
[RFC PATCH 07/16] net: ti: icssg: Enforce pinctrl state on the MDIO child node
The binding represents the MDIO controller as a child device tree
node of the MAC device tree node.
The U-Boot driver mostly ignores that child device tree node and just
hardcodes the resources it uses to support both the MAC and MDIO in a
single driver.
However, some resources like pinctrl muxing states are thus ignored.
This has been a problem with some device trees that will put some
pinctrl states on the MDIO device tree node.
Let's rework the driver a bit to create a dummy MDIO driver that we will
then get during our initialization to force the core to select the right
muxing.
Signed-off-by: MD Danish Anwar
---
drivers/net/ti/Kconfig| 1 +
drivers/net/ti/icssg_prueth.c | 59 +++
2 files changed, 60 insertions(+)
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index 9fead2c7ce..6935b70e12 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -53,6 +53,7 @@ config TI_AM65_CPSW_NUSS
config TI_ICSSG_PRUETH
bool "TI Gigabit PRU Ethernet driver"
depends on ARCH_K3
+ imply DM_MDIO
select PHYLIB
help
Support Gigabit Ethernet ports over the ICSSG PRU Subsystem
diff --git a/drivers/net/ti/icssg_prueth.c b/drivers/net/ti/icssg_prueth.c
index 1a7445a015..40ad827e49 100644
--- a/drivers/net/ti/icssg_prueth.c
+++ b/drivers/net/ti/icssg_prueth.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -100,9 +101,56 @@ static int icssg_phy_init(struct udevice *dev)
return ret;
}
+static ofnode prueth_find_mdio(ofnode parent)
+{
+ ofnode node;
+
+ ofnode_for_each_subnode(node, parent)
+ if (ofnode_device_is_compatible(node, "ti,davinci_mdio"))
+ return node;
+
+ return ofnode_null();
+}
+
+static int prueth_mdio_setup(struct udevice *dev)
+{
+ struct prueth *priv = dev_get_priv(dev);
+ struct udevice *mdio_dev;
+ ofnode mdio;
+ int ret;
+
+ mdio = prueth_find_mdio(dev_ofnode(priv->pruss));
+ if (!ofnode_valid(mdio))
+ return 0;
+
+ /*
+* The MDIO controller is represented in the DT binding by a
+* subnode of the MAC controller.
+*
+* We don't have a DM driver for the MDIO device yet, and thus any
+* pinctrl setting on its node will be ignored.
+*
+* However, we do need to make sure the pins states tied to the
+* MDIO node are configured properly. Fortunately, the core DM
+* does that for use when we get a device, so we can work around
+* that whole issue by just requesting a dummy MDIO driver to
+* probe, and our pins will get muxed.
+*/
+ ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, &mdio_dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static int icssg_mdio_init(struct udevice *dev)
{
struct prueth *prueth = dev_get_priv(dev);
+ int ret;
+
+ ret = prueth_mdio_setup(dev);
+ if (ret)
+ return ret;
prueth->bus = cpsw_mdio_init(dev->name, prueth->mdio_base,
prueth->mdio_freq,
@@ -593,3 +641,14 @@ U_BOOT_DRIVER(prueth) = {
.plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
+
+static const struct udevice_id prueth_mdio_ids[] = {
+ { .compatible = "ti,davinci_mdio" },
+ { }
+};
+
+U_BOOT_DRIVER(prueth_mdio) = {
+ .name = "prueth_mdio",
+ .id = UCLASS_MDIO,
+ .of_match = prueth_mdio_ids,
+};
--
2.34.1
[RFC PATCH 09/16] arm: dts: k3-am65-main: Add ICSSG IEP nodes
The ICSSG IP on AM65x SoCs have two Industrial Ethernet Peripherals (IEPs)
to manage/generate Industrial Ethernet functions such as time stamping.
Each IEP sub-module is sourced from an internal clock mux that can be
sourced from either of the IP instance's ICSSG_IEP_GCLK or ICSSG_ICLK.
Add the IEP nodes for all the ICSSG instances.
Signed-off-by: MD Danish Anwar
---
arch/arm/dts/k3-am65-main.dtsi | 36 ++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index 7f10520236..da48887559 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -969,6 +969,18 @@
};
};
+ icssg0_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
+ icssg0_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
icssg0_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1110,6 +1122,18 @@
};
};
+ icssg1_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
+ icssg1_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
icssg1_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1256,6 +1280,18 @@
reg = <0x32000 0x100>;
};
+ icssg2_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
+ icssg2_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
icssg2_mii_g_rt: mii-g-rt@33000 {
compatible = "ti,pruss-mii-g", "syscon";
reg = <0x33000 0x1000>;
--
2.34.1
[RFC PATCH 10/16] arm: dts: k3-am654-base-board: Add ICSSG2 Ethernet support
ICSSG2 provides dual Gigabit Ethernet support.
Add ICSSG2 ethernet node to an overlay k3-am654-icssg2.dtso
Signed-off-by: MD Danish Anwar
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/k3-am654-icssg2.dtso | 145 ++
2 files changed, 147 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/k3-am654-icssg2.dtso
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e9e58c5478..2bc53fba89 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1396,7 +1396,8 @@ dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am6548-iot2050-advanced-pg2.dtb \
k3-am6548-iot2050-advanced-m2.dtb \
k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo \
- k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo
+ k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo \
+ k3-am654-icssg2.dtbo
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
diff --git a/arch/arm/dts/k3-am654-icssg2.dtso
b/arch/arm/dts/k3-am654-icssg2.dtso
new file mode 100644
index 00..faefa2febc
--- /dev/null
+++ b/arch/arm/dts/k3-am654-icssg2.dtso
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT overlay for enabling ICSSG2 on AM654 EVM
+ *
+ * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include
+#include "k3-pinctrl.h"
+
+&{/} {
+ aliases {
+ ethernet1 = "/icssg2-eth/ethernet-ports/port@0";
+ ethernet2 = "/icssg2-eth/ethernet-ports/port@1";
+ };
+
+ /* Ethernet node on PRU-ICSSG2 */
+ icssg2_eth: icssg2-eth {
+ compatible = "ti,am654-icssg-prueth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg2_rgmii_pins_default>;
+ sram = <&msmc_ram>;
+ ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>,
+ <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>;
+ firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
+
+ ti,pruss-gp-mux-sel = <2>, /* MII mode */
+ <2>,
+ <2>,
+ <2>, /* MII mode */
+ <2>,
+ <2>;
+
+ ti,mii-g-rt = <&icssg2_mii_g_rt>;
+ ti,mii-rt = <&icssg2_mii_rt>;
+ ti,iep = <&icssg2_iep0>, <&icssg2_iep1>;
+
+ interrupt-parent = <&icssg2_intc>;
+ interrupts = <24 0 2>, <25 1 3>;
+ interrupt-names = "tx_ts0", "tx_ts1";
+
+ dmas = <&main_udmap 0xc300>, /* egress slice 0 */
+ <&main_udmap 0xc301>, /* egress slice 0 */
+ <&main_udmap 0xc302>, /* egress slice 0 */
+ <&main_udmap 0xc303>, /* egress slice 0 */
+ <&main_udmap 0xc304>, /* egress slice 1 */
+ <&main_udmap 0xc305>, /* egress slice 1 */
+ <&main_udmap 0xc306>, /* egress slice 1 */
+ <&main_udmap 0xc307>, /* egress slice 1 */
+ <&main_udmap 0x4300>, /* ingress slice 0 */
+ <&main_udmap 0x4301>; /* ingress slice 1 */
+
+ dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
+ "tx1-0", "tx1-1", "tx1-2", "tx1-3",
+ "rx0", "rx1";
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ icssg2_emac0: port@0 {
+ reg = <0>;
+ phy-handle = <&icssg2_phy0>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4120>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ icssg2_emac1: port@1 {
+ reg = <1>;
+ phy-handle = <&icssg2_phy1>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4124>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+
[RFC PATCH 08/16] arm: dts: k3-am65: Add cfg reg region to ringacc node
Add register range of ringacc cfg node to k3-am65* dtsi files. This is normally under Device Management firmware control but some entities like bootloader have to access directly and thus required to be present in DT. Signed-off-by: MD Danish Anwar --- arch/arm/dts/k3-am65-main.dtsi | 5 +++-- arch/arm/dts/k3-am65-mcu.dtsi | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index 691c9978e6..7f10520236 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -603,8 +603,9 @@ reg = <0x0 0x3c00 0x0 0x40>, <0x0 0x3800 0x0 0x40>, <0x0 0x3112 0x0 0x100>, - <0x0 0x3300 0x0 0x4>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x3300 0x0 0x4>, + <0x0 0x3108 0x0 0x4>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <818>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi index d7111aa8b2..b7f0456de7 100644 --- a/arch/arm/dts/k3-am65-mcu.dtsi +++ b/arch/arm/dts/k3-am65-mcu.dtsi @@ -129,8 +129,9 @@ reg = <0x0 0x2b80 0x0 0x40>, <0x0 0x2b00 0x0 0x40>, <0x0 0x2859 0x0 0x100>, - <0x0 0x2a50 0x0 0x4>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x2a50 0x0 0x4>, + <0x0 0x2844 0x0 0x4>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; -- 2.34.1
[RFC PATCH 10/16] arm: dts: k3-am65-main: Add ICSSG IEP nodes
The ICSSG IP on AM65x SoCs have two Industrial Ethernet Peripherals (IEPs)
to manage/generate Industrial Ethernet functions such as time stamping.
Each IEP sub-module is sourced from an internal clock mux that can be
sourced from either of the IP instance's ICSSG_IEP_GCLK or ICSSG_ICLK.
Add the IEP nodes for all the ICSSG instances.
Signed-off-by: MD Danish Anwar
---
arch/arm/dts/k3-am65-main.dtsi | 36 ++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index 7f10520236..da48887559 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -969,6 +969,18 @@
};
};
+ icssg0_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
+ icssg0_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
icssg0_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1110,6 +1122,18 @@
};
};
+ icssg1_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
+ icssg1_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
icssg1_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1256,6 +1280,18 @@
reg = <0x32000 0x100>;
};
+ icssg2_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
+ icssg2_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
icssg2_mii_g_rt: mii-g-rt@33000 {
compatible = "ti,pruss-mii-g", "syscon";
reg = <0x33000 0x1000>;
--
2.34.1
[RFC PATCH 11/16] arm: dts: k3-am654-base-board: Add ICSSG2 Ethernet support
ICSSG2 provides dual Gigabit Ethernet support.
Add ICSSG2 ethernet node to an overlay k3-am654-icssg2.dts
Signed-off-by: MD Danish Anwar
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/k3-am654-icssg2.dtso | 145 ++
2 files changed, 147 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/k3-am654-icssg2.dtso
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e9e58c5478..2bc53fba89 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1396,7 +1396,8 @@ dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am6548-iot2050-advanced-pg2.dtb \
k3-am6548-iot2050-advanced-m2.dtb \
k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo \
- k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo
+ k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo \
+ k3-am654-icssg2.dtbo
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
diff --git a/arch/arm/dts/k3-am654-icssg2.dtso
b/arch/arm/dts/k3-am654-icssg2.dtso
new file mode 100644
index 00..faefa2febc
--- /dev/null
+++ b/arch/arm/dts/k3-am654-icssg2.dtso
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT overlay for enabling ICSSG2 on AM654 EVM
+ *
+ * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include
+#include "k3-pinctrl.h"
+
+&{/} {
+ aliases {
+ ethernet1 = "/icssg2-eth/ethernet-ports/port@0";
+ ethernet2 = "/icssg2-eth/ethernet-ports/port@1";
+ };
+
+ /* Ethernet node on PRU-ICSSG2 */
+ icssg2_eth: icssg2-eth {
+ compatible = "ti,am654-icssg-prueth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg2_rgmii_pins_default>;
+ sram = <&msmc_ram>;
+ ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>,
+ <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>;
+ firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
+
+ ti,pruss-gp-mux-sel = <2>, /* MII mode */
+ <2>,
+ <2>,
+ <2>, /* MII mode */
+ <2>,
+ <2>;
+
+ ti,mii-g-rt = <&icssg2_mii_g_rt>;
+ ti,mii-rt = <&icssg2_mii_rt>;
+ ti,iep = <&icssg2_iep0>, <&icssg2_iep1>;
+
+ interrupt-parent = <&icssg2_intc>;
+ interrupts = <24 0 2>, <25 1 3>;
+ interrupt-names = "tx_ts0", "tx_ts1";
+
+ dmas = <&main_udmap 0xc300>, /* egress slice 0 */
+ <&main_udmap 0xc301>, /* egress slice 0 */
+ <&main_udmap 0xc302>, /* egress slice 0 */
+ <&main_udmap 0xc303>, /* egress slice 0 */
+ <&main_udmap 0xc304>, /* egress slice 1 */
+ <&main_udmap 0xc305>, /* egress slice 1 */
+ <&main_udmap 0xc306>, /* egress slice 1 */
+ <&main_udmap 0xc307>, /* egress slice 1 */
+ <&main_udmap 0x4300>, /* ingress slice 0 */
+ <&main_udmap 0x4301>; /* ingress slice 1 */
+
+ dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
+ "tx1-0", "tx1-1", "tx1-2", "tx1-3",
+ "rx0", "rx1";
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ icssg2_emac0: port@0 {
+ reg = <0>;
+ phy-handle = <&icssg2_phy0>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4120>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ icssg2_emac1: port@1 {
+ reg = <1>;
+ phy-handle = <&icssg2_phy1>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4124>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+
[RFC PATCH 11/16] arm: dts: k3-am65x-binman: Add ICSSG2 overlay and configuration
Add ICSSG2 overlay and configuration to tispl and u-boot images.
Signed-off-by: MD Danish Anwar
---
arch/arm/dts/k3-am65x-binman.dtsi | 85 +++
1 file changed, 85 insertions(+)
diff --git a/arch/arm/dts/k3-am65x-binman.dtsi
b/arch/arm/dts/k3-am65x-binman.dtsi
index 8cc24da1f3..9a0c0fca47 100644
--- a/arch/arm/dts/k3-am65x-binman.dtsi
+++ b/arch/arm/dts/k3-am65x-binman.dtsi
@@ -98,6 +98,8 @@
#define SPL_AM654_EVM_DTB "spl/dts/k3-am654-base-board.dtb"
#define AM654_EVM_DTB "u-boot.dtb"
+#define AM654_EVM_ICSSG2_DTBO "arch/arm/dts/k3-am654-icssg2.dtbo"
+
&binman {
ti-spl {
insert-template = <&ti_spl_template>;
@@ -124,6 +126,20 @@
filename = SPL_AM654_EVM_DTB;
};
};
+
+ fdt-1 {
+ description = "k3-am654-icssg2 overlay";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content =
<&spl_am65x_evm_icssg2_dtb>;
+ keyfile = "custMpk.pem";
+ };
+ spl_am65x_evm_icssg2_dtb: blob-ext {
+ filename =
AM654_EVM_ICSSG2_DTBO;
+ };
+ };
};
configurations {
@@ -135,6 +151,13 @@
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
+
+ conf-1 {
+ description = "k3-am654-icssg2";
+ firmware = "atf";
+ loadables = "tee", "dm", "spl";
+ fdt = "fdt-0", "fdt-1";
+ };
};
};
};
@@ -168,6 +191,24 @@
};
};
+ fdt-1 {
+ description = "k3-am654-icssg2 overlay";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content =
<&am65x_evm_icssg2_dtb>;
+ keyfile = "custMpk.pem";
+
+ };
+ am65x_evm_icssg2_dtb: blob-ext {
+ filename =
AM654_EVM_ICSSG2_DTBO;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+
};
configurations {
@@ -179,6 +220,13 @@
loadables = "uboot";
fdt = "fdt-0";
};
+
+ conf-1 {
+ description = "k3-am654-icssg2";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-0", "fdt-1";
+ };
};
};
};
@@ -205,6 +253,16 @@
filename = SPL_AM654_EVM_DTB;
};
};
+
+ fdt-1 {
+ description = "k3-am654-icssg2 overlay";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ blob {
+ filename =
AM654_EVM_ICSSG2_DTBO;
+ };
+ };
};
configurations {
@@ -216,6 +274,13 @@
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
+
+ conf-1 {
+ descri
[RFC PATCH 12/16] arm: dts: k3-am65x-binman: Add ICSSG2 overlay and configuration
Add ICSSG2 overlay and configuration to tispl and u-boot images.
Signed-off-by: MD Danish Anwar
---
arch/arm/dts/k3-am65x-binman.dtsi | 85 +++
1 file changed, 85 insertions(+)
diff --git a/arch/arm/dts/k3-am65x-binman.dtsi
b/arch/arm/dts/k3-am65x-binman.dtsi
index 8cc24da1f3..9a0c0fca47 100644
--- a/arch/arm/dts/k3-am65x-binman.dtsi
+++ b/arch/arm/dts/k3-am65x-binman.dtsi
@@ -98,6 +98,8 @@
#define SPL_AM654_EVM_DTB "spl/dts/k3-am654-base-board.dtb"
#define AM654_EVM_DTB "u-boot.dtb"
+#define AM654_EVM_ICSSG2_DTBO "arch/arm/dts/k3-am654-icssg2.dtbo"
+
&binman {
ti-spl {
insert-template = <&ti_spl_template>;
@@ -124,6 +126,20 @@
filename = SPL_AM654_EVM_DTB;
};
};
+
+ fdt-1 {
+ description = "k3-am654-icssg2 overlay";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content =
<&spl_am65x_evm_icssg2_dtb>;
+ keyfile = "custMpk.pem";
+ };
+ spl_am65x_evm_icssg2_dtb: blob-ext {
+ filename =
AM654_EVM_ICSSG2_DTBO;
+ };
+ };
};
configurations {
@@ -135,6 +151,13 @@
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
+
+ conf-1 {
+ description = "k3-am654-icssg2";
+ firmware = "atf";
+ loadables = "tee", "dm", "spl";
+ fdt = "fdt-0", "fdt-1";
+ };
};
};
};
@@ -168,6 +191,24 @@
};
};
+ fdt-1 {
+ description = "k3-am654-icssg2 overlay";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content =
<&am65x_evm_icssg2_dtb>;
+ keyfile = "custMpk.pem";
+
+ };
+ am65x_evm_icssg2_dtb: blob-ext {
+ filename =
AM654_EVM_ICSSG2_DTBO;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+
};
configurations {
@@ -179,6 +220,13 @@
loadables = "uboot";
fdt = "fdt-0";
};
+
+ conf-1 {
+ description = "k3-am654-icssg2";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-0", "fdt-1";
+ };
};
};
};
@@ -205,6 +253,16 @@
filename = SPL_AM654_EVM_DTB;
};
};
+
+ fdt-1 {
+ description = "k3-am654-icssg2 overlay";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ blob {
+ filename =
AM654_EVM_ICSSG2_DTBO;
+ };
+ };
};
configurations {
@@ -216,6 +274,13 @@
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
+
+ conf-1 {
+ descri
[RFC PATCH 12/16] configs: am65x_evm_a53: Enable ICSSG Driver
Enable ICSSG driver in am65x_evm_a53_defconfig Signed-off-by: MD Danish Anwar --- configs/am65x_evm_a53_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 55289b967b..e79a961317 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -130,6 +130,7 @@ CONFIG_PHY_FIXED=y CONFIG_E1000=y CONFIG_CMD_E1000=y CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_TI_ICSSG_PRUETH=y CONFIG_PCI_KEYSTONE=y CONFIG_PHY=y CONFIG_SPL_PHY=y -- 2.34.1
[RFC PATCH 13/16] configs: am65x_evm_a53_defconfig: add SPL_LOAD_FIT_APPLY_OVERLAY
We want SPL to apply DTB overlays (e.g. NAND card overlay) so enable SPL_LOAD_FIT_APPLY_OVERLAY. Increase SPL_LOAD_FIT_APPLY_OVERLAY_BUF_SZ and SPL_STACK_R_MALLOC_SIMPLE_LEN. Without this SPL hangs. Signed-off-by: MD Danish Anwar --- configs/am65x_evm_a53_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index e79a961317..2755d7082f 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -70,6 +70,9 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY_BUF_SZ=0x10 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x100 CONFIG_CMD_USB=y CONFIG_CMD_TIME=y CONFIG_MTDIDS_DEFAULT="nor0=4704.spi.0" -- 2.34.1
[RFC PATCH 13/16] configs: am65x_evm_a53: Enable ICSSG Driver
Enable ICSSG driver in am65x_evm_a53_defconfig Signed-off-by: MD Danish Anwar --- configs/am65x_evm_a53_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 55289b967b..e79a961317 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -130,6 +130,7 @@ CONFIG_PHY_FIXED=y CONFIG_E1000=y CONFIG_CMD_E1000=y CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_TI_ICSSG_PRUETH=y CONFIG_PCI_KEYSTONE=y CONFIG_PHY=y CONFIG_SPL_PHY=y -- 2.34.1
[RFC PATCH 14/16] configs: am65x_evm_a53_defconfig: add SPL_LOAD_FIT_APPLY_OVERLAY
We want SPL to apply DTB overlays (e.g. NAND card overlay) so enable SPL_LOAD_FIT_APPLY_OVERLAY. Increase SPL_LOAD_FIT_APPLY_OVERLAY_BUF_SZ and SPL_STACK_R_MALLOC_SIMPLE_LEN. Without this SPL hangs. Signed-off-by: MD Danish Anwar --- configs/am65x_evm_a53_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index e79a961317..2755d7082f 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -70,6 +70,9 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY_BUF_SZ=0x10 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x100 CONFIG_CMD_USB=y CONFIG_CMD_TIME=y CONFIG_MTDIDS_DEFAULT="nor0=4704.spi.0" -- 2.34.1
[RFC PATCH 14/16] tools/fdtgrep: Include __symbols__ table
This is required for overlays to work at SPL.
Loading of symbol table depends on DT Overlay support in SPL
so make it compile-time dependent. Without this SPL fails to
boot some platforms where this feature is not enabled
(e.g. dra71-evm.)
Without including the file, the symbol
CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY will not be visible and
we will never include the symbol table.
So include
Due to some reason it needs to be included after
[#include "fdt_host.h"] otherwise it causes a build error.
Signed-off-by: MD Danish Anwar
---
tools/fdtgrep.c | 8
1 file changed, 8 insertions(+)
diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c
index 7eabcab439..706b4a35f4 100644
--- a/tools/fdtgrep.c
+++ b/tools/fdtgrep.c
@@ -22,6 +22,8 @@
#include "fdt_host.h"
#include "libfdt_internal.h"
+#include
+
/* Define DEBUG to get some debugging output on stderr */
#ifdef DEBUG
#define debug(a, b...) fprintf(stderr, a, ## b)
@@ -1234,6 +1236,12 @@ int main(int argc, char *argv[])
disp.fout = stdout;
}
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY)) {
+ /* include symbol table */
+ if (value_add(&disp, &disp.value_head, FDT_IS_NODE, 1,
"/__symbols__"))
+ usage("Cannot add __symbols__ value");
+ }
+
/* Run the grep and output the results */
ret = do_fdtgrep(&disp, filename);
if (disp.output_fname)
--
2.34.1
[RFC PATCH 15/16] board: ti: am65x: Add check for k3-am654-icssg2 in board_fit_config_match()
When CONFIG_TI_ICSSG_PRUETH is enabled, add config name check for the
icssg2 overlay in board_fit_config_match() API.
Signed-off-by: MD Danish Anwar
---
board/ti/am65x/evm.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index df209021c1..0b661f0084 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -90,10 +90,13 @@ int dram_init_banksize(void)
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
-#ifdef CONFIG_TARGET_AM654_A53_EVM
- if (!strcmp(name, "k3-am654-base-board"))
- return 0;
-#endif
+ if (IS_ENABLED(CONFIG_TI_ICSSG_PRUETH)) {
+ if (!strcmp(name, "k3-am654-icssg2"))
+ return 0;
+ } else {
+ if (!strcmp(name, "k3-am654-base-board"))
+ return 0;
+ }
return -1;
}
--
2.34.1
[RFC PATCH 15/16] tools/fdtgrep: Include __symbols__ table
This is required for overlays to work at SPL.
Loading of symbol table depends on DT Overlay support in SPL
so make it compile-time dependent. Without this SPL fails to
boot some platforms where this feature is not enabled
(e.g. dra71-evm.)
Without including the file, the symbol
CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY will not be visible and
we will never include the symbol table.
So include
Due to some reason it needs to be included after
[#include "fdt_host.h"] otherwise it causes a build error.
Signed-off-by: MD Danish Anwar
---
tools/fdtgrep.c | 8
1 file changed, 8 insertions(+)
diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c
index 7eabcab439..706b4a35f4 100644
--- a/tools/fdtgrep.c
+++ b/tools/fdtgrep.c
@@ -22,6 +22,8 @@
#include "fdt_host.h"
#include "libfdt_internal.h"
+#include
+
/* Define DEBUG to get some debugging output on stderr */
#ifdef DEBUG
#define debug(a, b...) fprintf(stderr, a, ## b)
@@ -1234,6 +1236,12 @@ int main(int argc, char *argv[])
disp.fout = stdout;
}
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY)) {
+ /* include symbol table */
+ if (value_add(&disp, &disp.value_head, FDT_IS_NODE, 1,
"/__symbols__"))
+ usage("Cannot add __symbols__ value");
+ }
+
/* Run the grep and output the results */
ret = do_fdtgrep(&disp, filename);
if (disp.output_fname)
--
2.34.1
[RFC PATCH 16/16] board: ti: am65x: Add check for k3-am654-icssg2 in board_fit_config_match()
When CONFIG_TI_ICSSG_PRUETH is enabled, add config name check for the
icssg2 overlay in board_fit_config_match() API.
Signed-off-by: MD Danish Anwar
---
board/ti/am65x/evm.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index df209021c1..0b661f0084 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -90,10 +90,13 @@ int dram_init_banksize(void)
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
-#ifdef CONFIG_TARGET_AM654_A53_EVM
- if (!strcmp(name, "k3-am654-base-board"))
- return 0;
-#endif
+ if (IS_ENABLED(CONFIG_TI_ICSSG_PRUETH)) {
+ if (!strcmp(name, "k3-am654-icssg2"))
+ return 0;
+ } else {
+ if (!strcmp(name, "k3-am654-base-board"))
+ return 0;
+ }
return -1;
}
--
2.34.1
[RFC PATCH 16/16] Revert "dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation"
This reverts commit 9e644284ab812f2db23f6185af77c0e771b0be73.
---
drivers/core/ofnode.c | 2 +-
include/dm/ofnode.h | 8
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 21a233f90f..cc2029e62d 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -1485,7 +1485,7 @@ bool ofnode_pre_reloc(ofnode node)
*/
if (ofnode_read_bool(node, "bootph-pre-ram") ||
ofnode_read_bool(node, "bootph-pre-sram"))
- return gd->flags & GD_FLG_RELOC;
+ return true;
if (IS_ENABLED(CONFIG_OF_TAG_MIGRATE)) {
/* detect and handle old tags */
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 5795115c49..5f1c8c2787 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -1254,15 +1254,15 @@ int ofnode_read_simple_size_cells(ofnode node);
* determine if a node was bound in one of SPL/TPL stages.
*
* There are 4 settings currently in use
- * - bootph-some-ram: U-Boot proper pre-relocation phase
+ * - bootph-some-ram: U-Boot proper pre-relocation only
* - bootph-all: all phases
* Existing platforms only use it to indicate nodes needed in
* SPL. Should probably be replaced by bootph-pre-ram for new platforms.
- * - bootph-pre-ram: SPL phase
- * - bootph-pre-sram: TPL phase
+ * - bootph-pre-ram: SPL and U-Boot pre-relocation
+ * - bootph-pre-sram: TPL and U-Boot pre-relocation
*
* @node: node to check
- * Return: true if node should be or was bound, false otherwise
+ * Return: true if node is needed in SPL/TL, false otherwise
*/
bool ofnode_pre_reloc(ofnode node);
--
2.34.1
Re: [RFC PATCH 00/16] Introduce ICSSG Ethernet driver
Hi All,
Please ignore this thread. Some mails seems to have been duplicated.
I will post another thread soon. Pls ignore this.
Sorry for the inconvenience.
On 19/12/23 3:41 pm, MD Danish Anwar wrote:
> Introduce ICSSG PRUETH support in uboot. The ICSSG driver is used in TI
> AM654 SR2.0.
>
> The ICSSG PRU Sub-system runs on EMAC firmware. This series Introduces
> support for ICSSG driver in uboot. This series also adds the driver's
> dependencies.
>
> The ICSSG2 node is added in device tree overlay so that it remains in
> sync with linux kernel.
>
> The series introduces device tree and config changes and AM65x
> to enable ICSSG driver. The series also enables SPL_LOAD_FIT_APPLY_OVERLAY
> for AM65x in order to load overlay over spl.
>
> This series has been tested on AM65x SR2.0, and the ICSSG interface is
> able to ping / dhcp and boot kernel using tftp in uboot.
>
> To use ICSSG2 ethernet, the ICSSG firmware needs to be loaded to PRU RPROC
> cores and RPROC cores need to be booted with the firmware. This step is
> done inside driver in kernel as kernel supports APIs like
> rproc_set_firmware() and rproc_fw_boot(). But as u-boot doesn't have these
> APIs, the same needs to be done via u-boot cmds.
>
> To make sure icssg-eth works we need to do below steps.
>
> 1. Initialize rproc cores i.e. rproc_init()
> 2. Load $firmware_file from partition '1:2' (root) on device (mmc in this
>example)
> 3. Load the firmware file to rproc cores passing. i.e. rproc_load()
>taking rproc_id, loadaddr and file size as arguments.
> 4. Start rproc cores. i.e. rproc_start() taking rproc_id as arguments
>
> The above steps are done by running the below commands at u-boot prompt.
>
> => setenv start_icssg2 'rproc start 14; rproc start 15; rproc start 16; rproc
> start 17; rproc start 18; rproc start 19'
> => setenv stop_icssg2 'rproc stop 14; rproc stop 15; rproc stop 16; rproc
> stop 17; rproc stop 18; rproc stop 19'
> => setenv firmware_dir '/lib/firmware/ti-pruss'
> => setenv get_firmware_mmc 'load mmc ${bootpart} ${loadaddr}
> ${firmware_dir}/${firmware_file}'
>
> => setenv init_icssg2 'setenv ethact icssg2-eth; setenv autoload no; rproc
> init; setenv loadaddr 0x8000; \
> setenv firmware_file am65x-sr2-pru0-prueth-fw.elf; run get_firmware_mmc;
> rproc load 14 0x8000 ${filesize}; \
> setenv loadaddr 0x8900; setenv firmware_file
> am65x-sr2-rtu0-prueth-fw.elf; run get_firmware_mmc; rproc load 15 0x8900
> ${filesize}; \
> setenv loadaddr 0x9000; setenv firmware_file
> am65x-sr2-txpru0-prueth-fw.elf; run get_firmware_mmc; rproc load 16
> 0x9000 ${filesize}; \
> setenv loadaddr 0x8000; setenv firmware_file
> am65x-sr2-pru1-prueth-fw.elf; run get_firmware_mmc; rproc load 17 0x8000
> ${filesize}; \
> setenv loadaddr 0x8900; setenv firmware_file
> am65x-sr2-rtu1-prueth-fw.elf; run get_firmware_mmc; rproc load 18 0x8900
> ${filesize}; \
> setenv loadaddr 0x9000; setenv firmware_file
> am65x-sr2-txpru1-prueth-fw.elf; run get_firmware_mmc; rproc load 19
> 0x9000 ${filesize}; \
> run start_icssg2;'
>
> => run init_icssg2
> => dhcp
> k3-navss-ringacc ringacc@3c00: Ring Accelerator probed rings:818,
> gp-rings[304,100] sci-dev-id:187
> k3-navss-ringacc ringacc@3c00: dma-ring-reset-quirk: disabled
> prueth icssg2-eth: K3 ICSSG: rflow_id_base: 8, chn_name = rx0
> link up on port 0, speed 1000, full duplex
> BOOTP broadcast 1
> BOOTP broadcast 2
> BOOTP broadcast 3
> DHCP client bound to address 192.168.4.58 (1020 ms)
>
> Thanks and Regards,
> MD Danish Anwar
>
> MD Danish Anwar (16):
> net: ti: icssg: Add Firmware Interface for ICSSG Ethernet driver.
> net: ti: icssg: Add Firmware config and classification APIs.
> net: ti: icssg: Add icssg queues APIs and macros
> net: ti: icssg: Add ICSSG ethernet driver
> net: ti: icssg: Add support sending FDB command to update rx_flow_id
> net: ti: icssg: Enforce pinctrl state on the MDIO child node
> arm: dts: k3-am65: Add additional regs for DMA components
> arm: dts: k3-am65: Add cfg reg region to ringacc node
> arm: dts: k3-am65-main: Add ICSSG IEP nodes
> arm: dts: k3-am654-base-board: Add ICSSG2 Ethernet support
> arm: dts: k3-am65x-binman: Add ICSSG2 overlay and configuration
> configs: am65x_evm_a53: Enable ICSSG Driver
> configs: am65x_evm_a53_defconfig: add SPL_LOAD_FIT_APPLY_OVERLAY
> tools/fdtgrep: Include __symbols__ table
> board: ti: am65x: Add check for k3-am654-icssg2 in
> board_fit_config_match()
> Revert "dm: core: Report bootph-pre-ram/sram node as pre-reloc after
> relocation"
>
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/k3-am65-main.dtsi| 49 ++-
> arch/arm/dts/k3-am65-mcu.dtsi | 13 +-
> arch/arm/dts/k3-am654-icssg2.dtso | 145 +++
> arch/arm/dts/k3-am65x-binman.dtsi | 85
> board/ti/am65x/evm.c | 11 +-
> configs/am65x_evm_a53_defconfig | 4 +
> drivers/core/of
[RFC PATCH 01/16] dma: ti: k3-udma: Use ring_idx to pair k3 nav rings
Use ring_idx to pair rings. ring_idx will be same as tx flow_id for all
non-negative flow_ids. For negative flow_ids, ring_idx will be tchan->id
added with bchan_cnt.
Signed-off-by: MD Danish Anwar
---
drivers/dma/ti/k3-udma.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 8a62d63dfe..eea9ec9659 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -876,13 +876,20 @@ static int udma_alloc_tx_resources(struct udma_chan *uc)
{
struct k3_nav_ring_cfg ring_cfg;
struct udma_dev *ud = uc->ud;
- int ret;
+ struct udma_tchan *tchan;
+ int ring_idx, ret;
ret = udma_get_tchan(uc);
if (ret)
return ret;
- ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, uc->tchan->id, -1,
+ tchan = uc->tchan;
+ if (tchan->tflow_id >= 0)
+ ring_idx = tchan->tflow_id;
+ else
+ ring_idx = ud->bchan_cnt + tchan->id;
+
+ ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1,
&uc->tchan->t_ring,
&uc->tchan->tc_ring);
if (ret) {
--
2.34.1
[RFC PATCH 00/16] Introduce ICSSG Ethernet driver
Introduce ICSSG PRUETH support in uboot. The ICSSG driver is used in TI
AM654 SR2.0.
The ICSSG PRU Sub-system runs on EMAC firmware. This series Introduces
support for ICSSG driver in uboot. This series also adds the driver's
dependencies.
The ICSSG2 node is added in device tree overlay so that it remains in
sync with linux kernel.
The series introduces device tree and config changes and AM65x
to enable ICSSG driver. The series also enables SPL_LOAD_FIT_APPLY_OVERLAY
for AM65x in order to load overlay over spl.
This series has been tested on AM65x SR2.0, and the ICSSG interface is
able to ping / dhcp and boot kernel using tftp in uboot.
To use ICSSG2 ethernet, the ICSSG firmware needs to be loaded to PRU RPROC
cores and RPROC cores need to be booted with the firmware. This step is
done inside driver in kernel as kernel supports APIs like
rproc_set_firmware() and rproc_fw_boot(). But as u-boot doesn't have these
APIs, the same needs to be done via u-boot cmds.
To make sure icssg-eth works we need to
do below steps.
1. Initialize rproc cores i.e. rproc_init()
2. Load $firmware_file from partition '1:2' (root) on device (mmc in this
example)
3. Load the firmware file to rproc cores passing. i.e. rproc_load()
taking rproc_id, loadaddr and file size as arguments.
4. Start rproc cores. i.e. rproc_start() taking rproc_id as arguments
The above steps are done by running the below commands at u-boot prompt.
=> setenv start_icssg2 'rproc start 14; rproc start 15; rproc start 16; rproc
start 17; rproc start 18; rproc start 19'
=> setenv stop_icssg2 'rproc stop 14; rproc stop 15; rproc stop 16; rproc stop
17; rproc stop 18; rproc stop 19'
=> setenv firmware_dir '/lib/firmware/ti-pruss'
=> setenv get_firmware_mmc 'load mmc ${bootpart} ${loadaddr}
${firmware_dir}/${firmware_file}'
=> setenv init_icssg2 'setenv ethact icssg2-eth; setenv autoload no; rproc
init; setenv loadaddr 0x8000; \
setenv firmware_file am65x-sr2-pru0-prueth-fw.elf; run get_firmware_mmc;
rproc load 14 0x8000 ${filesize}; \
setenv loadaddr 0x8900; setenv firmware_file
am65x-sr2-rtu0-prueth-fw.elf; run get_firmware_mmc; rproc load 15 0x8900
${filesize}; \
setenv loadaddr 0x9000; setenv firmware_file
am65x-sr2-txpru0-prueth-fw.elf; run get_firmware_mmc; rproc load 16 0x9000
${filesize}; \
setenv loadaddr 0x8000; setenv firmware_file
am65x-sr2-pru1-prueth-fw.elf; run get_firmware_mmc; rproc load 17 0x8000
${filesize}; \
setenv loadaddr 0x8900; setenv firmware_file
am65x-sr2-rtu1-prueth-fw.elf; run get_firmware_mmc; rproc load 18 0x8900
${filesize}; \
setenv loadaddr 0x9000; setenv firmware_file
am65x-sr2-txpru1-prueth-fw.elf; run get_firmware_mmc; rproc load 19 0x9000
${filesize}; \
run start_icssg2;'
=> run init_icssg2
=> dhcp
k3-navss-ringacc ringacc@3c00: Ring Accelerator probed rings:818,
gp-rings[304,100] sci-dev-id:187
k3-navss-ringacc ringacc@3c00: dma-ring-reset-quirk: disabled
prueth icssg2-eth: K3 ICSSG: rflow_id_base: 8, chn_name = rx0
link up on port 0, speed 1000, full duplex
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
DHCP client bound to address 192.168.4.58 (1020 ms)
Thanks and Regards,
MD Danish Anwar
MD Danish Anwar (16):
dma: ti: k3-udma: Use ring_idx to pair k3 nav rings
net: ti: icssg: Add Firmware Interface for ICSSG Ethernet driver.
net: ti: icssg: Add Firmware config and classification APIs.
net: ti: icssg: Add icssg queues APIs and macros
net: ti: icssg: Add ICSSG ethernet driver
net: ti: icssg: Add support sending FDB command to update rx_flow_id
net: ti: icssg: Enforce pinctrl state on the MDIO child node
arm: dts: k3-am65: Add additional regs for DMA components
arm: dts: k3-am65: Add cfg reg region to ringacc node
arm: dts: k3-am65-main: Add ICSSG IEP nodes
arm: dts: k3-am654-base-board: Add ICSSG2 Ethernet support
arm: dts: k3-am65x-binman: Add ICSSG2 overlay and configuration
configs: am65x_evm_a53: Enable ICSSG Driver
configs: am65x_evm_a53_defconfig: add SPL_LOAD_FIT_APPLY_OVERLAY
tools/fdtgrep: Include __symbols__ table
board: ti: am65x: Add check for k3-am654-icssg2 in
board_fit_config_match()
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/k3-am65-main.dtsi| 49 ++-
arch/arm/dts/k3-am65-mcu.dtsi | 13 +-
arch/arm/dts/k3-am654-icssg2.dtso | 145 +++
arch/arm/dts/k3-am65x-binman.dtsi | 85
board/ti/am65x/evm.c | 11 +-
configs/am65x_evm_a53_defconfig | 4 +
drivers/dma/ti/k3-udma.c | 11 +-
drivers/net/ti/Kconfig| 9 +
drivers/net/ti/Makefile | 1 +
drivers/net/ti/icss_mii_rt.h | 192 +
drivers/net/ti/icssg_classifier.c | 376 +
drivers/net/ti/icssg_config.c | 469 +
drivers/net/ti/icssg_config.h | 195 +
drivers/net/ti/icssg_prueth.c | 654 ++
drivers/net/ti/icssg_prueth.h |
[RFC PATCH 05/16] net: ti: icssg: Add ICSSG ethernet driver
This is the PURSS Ethernet driver for TI AM654 Sr2.0 and laterSoCs
with the ICSSG PRU Sub-system running EMAC firmware.
This driver caters to either of the slices(pru/rtu pair)
of the icssg subsystem.
One and exactly one of the slices is supported
as the u-boot ethernet supports probing one interface
at a time.
Signed-off-by: MD Danish Anwar
---
drivers/net/ti/Kconfig| 8 +
drivers/net/ti/Makefile | 1 +
drivers/net/ti/icssg_prueth.c | 589 ++
3 files changed, 598 insertions(+)
create mode 100644 drivers/net/ti/icssg_prueth.c
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index c75f418628..9fead2c7ce 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -49,3 +49,11 @@ config TI_AM65_CPSW_NUSS
help
This driver supports TI K3 MCU CPSW Nuss Ethernet controller
in Texas Instruments K3 AM65x SoCs.
+
+config TI_ICSSG_PRUETH
+ bool "TI Gigabit PRU Ethernet driver"
+ depends on ARCH_K3
+ select PHYLIB
+ help
+ Support Gigabit Ethernet ports over the ICSSG PRU Subsystem
+ This subsystem is available starting with the AM65 platform.
diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile
index 0ce0cf2828..5af760572f 100644
--- a/drivers/net/ti/Makefile
+++ b/drivers/net/ti/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o
obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o
obj-$(CONFIG_TI_AM65_CPSW_NUSS) += am65-cpsw-nuss.o cpsw_mdio.o
+obj-$(CONFIG_TI_ICSSG_PRUETH) += icssg_prueth.o cpsw_mdio.o icssg_classifier.o
icssg_config.o icssg_queues.o
diff --git a/drivers/net/ti/icssg_prueth.c b/drivers/net/ti/icssg_prueth.c
new file mode 100644
index 00..9cc700eca5
--- /dev/null
+++ b/drivers/net/ti/icssg_prueth.c
@@ -0,0 +1,589 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 AM65 PRU Ethernet Driver
+ *
+ * Copyright (C) 2019-2021, Texas Instruments, Incorporated
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "cpsw_mdio.h"
+#include "icssg_prueth.h"
+#include "icss_mii_rt.h"
+
+#define ICSS_SLICE0 0
+#define ICSS_SLICE1 1
+
+#ifdef PKTSIZE_ALIGN
+#define UDMA_RX_BUF_SIZE PKTSIZE_ALIGN
+#else
+#define UDMA_RX_BUF_SIZE ALIGN(1522, ARCH_DMA_MINALIGN)
+#endif
+
+#ifdef PKTBUFSRX
+#define UDMA_RX_DESC_NUM PKTBUFSRX
+#else
+#define UDMA_RX_DESC_NUM 4
+#endif
+
+/* Config region lies in shared RAM */
+#define ICSS_CONFIG_OFFSET_SLICE0 0
+#define ICSS_CONFIG_OFFSET_SLICE1 0x8000
+
+/* Firmware flags */
+#define ICSS_SET_RUN_FLAG_VLAN_ENABLE BIT(0) /* switch only */
+#define ICSS_SET_RUN_FLAG_FLOOD_UNICASTBIT(1) /* switch only
*/
+#define ICSS_SET_RUN_FLAG_PROMISC BIT(2) /* MAC only */
+#define ICSS_SET_RUN_FLAG_MULTICAST_PROMISCBIT(3) /* MAC only */
+
+/* CTRLMMR_ICSSG_RGMII_CTRL register bits */
+#define ICSSG_CTRL_RGMII_ID_MODE BIT(24)
+
+/* Management packet type */
+#define PRUETH_PKT_TYPE_CMD0x10
+
+static int icssg_phy_init(struct udevice *dev)
+{
+ struct prueth *priv = dev_get_priv(dev);
+ struct phy_device *phydev;
+ u32 supported = PHY_GBIT_FEATURES;
+ int ret;
+
+ phydev = phy_connect(priv->bus,
+priv->phy_addr,
+priv->dev,
+priv->phy_interface);
+
+ if (!phydev) {
+ dev_err(dev, "phy_connect() failed\n");
+ return -ENODEV;
+ }
+
+ /* disable unsupported features */
+ supported &= ~(PHY_10BT_FEATURES |
+ SUPPORTED_100baseT_Half |
+ SUPPORTED_1000baseT_Half |
+ SUPPORTED_Pause |
+ SUPPORTED_Asym_Pause);
+
+ phydev->supported &= supported;
+ phydev->advertising = phydev->supported;
+
+ if (IS_ENABLED(CONFIG_DM_ETH))
+ if (ofnode_valid(priv->phy_node))
+ phydev->node = priv->phy_node;
+
+ priv->phydev = phydev;
+ ret = phy_config(phydev);
+ if (ret < 0)
+ pr_err("phy_config() failed: %d", ret);
+
+ return ret;
+}
+
+static int icssg_mdio_init(struct udevice *dev)
+{
+ struct prueth *prueth = dev_get_priv(dev);
+
+ prueth->bus = cpsw_mdio_init(dev->name, prueth->mdio_base,
+prueth->mdio_freq,
+clk_get_rate(&prueth->mdiofck),
+prueth->mdio_manual_mode);
+ if (!prueth->bus)
+ return -EFAULT;
+
+ return 0;
+}
+
+static void icssg_config_set_speed(struct prueth *priv, int speed)
+{
+
[RFC PATCH 06/16] net: ti: icssg: Add support sending FDB command to update rx_flow_id
ICSSG firmware supports FDB commands. Add support to send FDB commands
from driver. Once rx_flow_id is obtained from dma, let firmware know that
we are using this rx_flow_id by sending a FDB command.
Signed-off-by: MD Danish Anwar
---
drivers/net/ti/icssg_config.c | 66 +++
drivers/net/ti/icssg_config.h | 18 ++
drivers/net/ti/icssg_prueth.c | 6
drivers/net/ti/icssg_prueth.h | 6
4 files changed, 96 insertions(+)
diff --git a/drivers/net/ti/icssg_config.c b/drivers/net/ti/icssg_config.c
index 33298c3374..7e11ef128f 100644
--- a/drivers/net/ti/icssg_config.c
+++ b/drivers/net/ti/icssg_config.c
@@ -9,6 +9,7 @@
#include "icssg_switch_map.h"
#include "icss_mii_rt.h"
#include
+#include
/* TX IPG Values to be set for 100M and 1G link speeds. These values are
* in ocp_clk cycles. So need change if ocp_clk is changed for a specific
@@ -401,3 +402,68 @@ int emac_set_port_state(struct prueth *prueth,
return ret;
}
+
+int icssg_send_fdb_msg(struct prueth *prueth, struct mgmt_cmd *cmd,
+ struct mgmt_cmd_rsp *rsp)
+{
+ int slice = prueth->slice;
+ int ret, addr;
+
+ addr = icssg_queue_pop(prueth, slice == 0 ?
+ ICSSG_CMD_POP_SLICE0 : ICSSG_CMD_POP_SLICE1);
+ if (addr < 0)
+ return addr;
+
+ /* First 4 bytes have FW owned buffer linking info which should
+* not be touched
+*/
+ memcpy_toio((void __iomem *)prueth->shram.pa + addr + 4, cmd,
sizeof(*cmd));
+ icssg_queue_push(prueth, slice == 0 ?
+ICSSG_CMD_PUSH_SLICE0 : ICSSG_CMD_PUSH_SLICE1, addr);
+ ret = read_poll_timeout(icssg_queue_pop, addr, addr >= 0,
+ 2000, 2000, prueth, slice == 0 ?
+ ICSSG_RSP_POP_SLICE0 : ICSSG_RSP_POP_SLICE1);
+
+ if (ret) {
+ dev_err(prueth->dev, "Timedout sending HWQ message\n");
+ return ret;
+ }
+
+ memcpy_fromio(rsp, (void __iomem *)prueth->shram.pa + addr,
sizeof(*rsp));
+ /* Return buffer back for to pool */
+ icssg_queue_push(prueth, slice == 0 ?
+ICSSG_RSP_PUSH_SLICE0 : ICSSG_RSP_PUSH_SLICE1, addr);
+
+ return 0;
+}
+
+int emac_fdb_flow_id_updated(struct prueth *prueth)
+{
+ struct mgmt_cmd_rsp fdb_cmd_rsp = { 0 };
+ int slice = prueth->slice;
+ struct mgmt_cmd fdb_cmd = { 0 };
+ int ret = 0;
+
+ fdb_cmd.header = ICSSG_FW_MGMT_CMD_HEADER;
+ fdb_cmd.type = ICSSG_FW_MGMT_FDB_CMD_TYPE_RX_FLOW;
+ fdb_cmd.seqnum = ++(prueth->icssg_hwcmdseq);
+ fdb_cmd.param = 0;
+
+ fdb_cmd.param |= (slice << 4);
+ fdb_cmd.cmd_args[0] = 0;
+
+ ret = icssg_send_fdb_msg(prueth, &fdb_cmd, &fdb_cmd_rsp);
+ if (ret)
+ return ret;
+
+ if (fdb_cmd.seqnum != fdb_cmd_rsp.seqnum) {
+ dev_err(prueth->dev, "seqnum doesn't match, cmd.seqnum %d !=
rsp.seqnum %d\n",
+ fdb_cmd.seqnum, fdb_cmd_rsp.seqnum);
+ return -EINVAL;
+ }
+
+ if (fdb_cmd_rsp.status == 1)
+ return 0;
+
+ return -EINVAL;
+}
diff --git a/drivers/net/ti/icssg_config.h b/drivers/net/ti/icssg_config.h
index fc6eae0426..156127bd3d 100644
--- a/drivers/net/ti/icssg_config.h
+++ b/drivers/net/ti/icssg_config.h
@@ -80,6 +80,7 @@ struct icssg_rxq_ctx {
#define ICSSG_FW_MGMT_FDB_CMD_TYPE 0x03
#define ICSSG_FW_MGMT_CMD_TYPE 0x04
#define ICSSG_FW_MGMT_PKT 0x8000
+#define ICSSG_FW_MGMT_FDB_CMD_TYPE_RX_FLOW 0x05
struct icssg_r30_cmd {
u32 cmd[4];
@@ -156,6 +157,23 @@ struct icssg_setclock_desc {
u32 CMP0_new;
} __packed;
+struct mgmt_cmd {
+ u8 param;
+ u8 seqnum;
+ u8 type;
+ u8 header;
+ u32 cmd_args[3];
+} __packed;
+
+struct mgmt_cmd_rsp {
+ u32 reserved;
+ u8 status;
+ u8 seqnum;
+ u8 type;
+ u8 header;
+ u32 cmd_args[3];
+} __packed;
+
#define ICSSG_CMD_POP_SLICE0 56
#define ICSSG_CMD_POP_SLICE1 60
diff --git a/drivers/net/ti/icssg_prueth.c b/drivers/net/ti/icssg_prueth.c
index 9cc700eca5..1a7445a015 100644
--- a/drivers/net/ti/icssg_prueth.c
+++ b/drivers/net/ti/icssg_prueth.c
@@ -225,6 +225,12 @@ static int prueth_start(struct udevice *dev)
dev_info(dev, "K3 ICSSG: rflow_id_base: %u, chn_name = %s\n",
dma_rx_cfg_data->flow_id_base, chn_name);
+ ret = emac_fdb_flow_id_updated(priv);
+ if (ret) {
+ dev_err(dev, "Failed to update Rx Flow ID %d", ret);
+ goto phy_fail;
+ }
+
ret = phy_startup(priv->phydev);
if (ret) {
dev_err(dev, "phy_startup failed\n");
diff --git a/drivers/net/ti/icssg_prueth.h b/drivers/net/ti/icssg_prueth.h
index f34ab5d6d4..e41ed16a05 100644
--- a/drivers/net/ti/icssg_prueth.h
+++ b/drivers/net/ti/icssg_p
[RFC PATCH 02/16] net: ti: icssg: Add Firmware Interface for ICSSG Ethernet driver.
Add firmware interface related headers and macros for ICSSG Ethernet driver. These macros will be later used by the ICSSG ethernet driver. Signed-off-by: MD Danish Anwar --- drivers/net/ti/icssg_switch_map.h | 209 ++ 1 file changed, 209 insertions(+) create mode 100644 drivers/net/ti/icssg_switch_map.h diff --git a/drivers/net/ti/icssg_switch_map.h b/drivers/net/ti/icssg_switch_map.h new file mode 100644 index 00..ba87a44023 --- /dev/null +++ b/drivers/net/ti/icssg_switch_map.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Texas Instruments ICSSG Ethernet driver + * + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#ifndef __NET_TI_ICSSG_SWITCH_MAP_H +#define __NET_TI_ICSSG_SWITCH_MAP_H + +/*Time after which FDB entries are checked for aged out values. Value in nanoseconds*/ +#define FDB_AGEING_TIMEOUT_OFFSET 0x0014 + +/*default VLAN tag for Host Port*/ +#define HOST_PORT_DF_VLAN_OFFSET 0x001C + +/*Same as HOST_PORT_DF_VLAN_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET HOST_PORT_DF_VLAN_OFFSET + +/*default VLAN tag for P1 Port*/ +#define P1_PORT_DF_VLAN_OFFSET 0x0020 + +/*Same as P1_PORT_DF_VLAN_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET P1_PORT_DF_VLAN_OFFSET + +/*default VLAN tag for P2 Port*/ +#define P2_PORT_DF_VLAN_OFFSET 0x0024 + +/*Same as P2_PORT_DF_VLAN_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET P2_PORT_DF_VLAN_OFFSET + +/*VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000*/ +#define VLAN_STATIC_REG_TABLE_OFFSET 0x0100 + +/*VLAN-FID Table offset for EMAC*/ +#define EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET VLAN_STATIC_REG_TABLE_OFFSET + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC0_HI 0x2104 + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC0_LO 0x2F6C + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC1_HI 0x3DD4 + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC1_LO 0x4C3C + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC0_HI 0x5AA4 + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC0_LO 0x5F0C + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC1_HI 0x6374 + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC1_LO 0x67DC + +/*special packet descriptor Q reserved memory*/ +#define HOST_SPPD0 0x7AAC + +/*special packet descriptor Q reserved memory*/ +#define HOST_SPPD1 0x7EAC + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_CYCLECOUNT_OFFSET 0x83EC + +/*IEP count hi roll over count*/ +#define TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET0x83F4 + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET 0x83F8 + +/*Set clock descriptor*/ +#define TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET0x83FC + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET 0x843C + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_COUNT_OFFSET 0x8440 + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET 0x8444 + +/*Control variable to generate SYNC1*/ +#define TIMESYNC_FW_WC_ISOM_PIN_SIGNAL_EN_OFFSET 0x844C + +/*SystemTime Sync0 periodicity*/ +#define TIMESYNC_FW_ST_SYNCOUT_PERIOD_OFFSET 0x8450 + +/*pktTxDelay for P1 = link speed dependent p1 mac delay + p1 phy delay*/ +#define TIMESYNC_FW_WC_PKTTXDELAY_P1_OFFSET0x8454 + +/*pktTxDelay for P2 = link speed dependent p2 mac delay + p2 phy delay*/ +#define TIMESYNC_FW_WC_PKTTXDELAY_P2_OFFSET0x8458 + +/*Set clock operation done signal for next task*/ +#define TIMESYNC_FW_SIG_PNFW_OFFSET0x845C + +/*Set clock operation done signal for next task*/ +#define TIMESYNC_FW_SIG_TIMESYNCFW_OFFSET 0x8460 + +/*New list is copied at this time*/ +#define TAS_CONFIG_CHANGE_TIME 0x000C + +/*config change error counter*/ +#define TAS_CONFIG_CHANGE_ERROR_COUNTER0x0014 + +/*TAS List update pending flag*/ +#define TAS_CONFIG_PENDING 0x0018 + +/*TAS list update trigger flag*/ +#define TAS_CONFIG_CHANGE 0x0019 + +/*List length for new TAS schedule*/ +#define TAS_ADMIN_LIST_LENGTH 0x001A + +/*Currently active TAS list index*/ +#define TAS_ACTIVE_LI
[RFC PATCH 04/16] net: ti: icssg: Add icssg queues APIs and macros
Add icssg_queue.c file. This file introduces macros and APIs related to
ICSSG queues. These will be used by ICSSG Ethernet driver.
Signed-off-by: MD Danish Anwar
---
drivers/net/ti/icssg_prueth.h | 5
drivers/net/ti/icssg_queues.c | 51 +++
2 files changed, 56 insertions(+)
create mode 100644 drivers/net/ti/icssg_queues.c
diff --git a/drivers/net/ti/icssg_prueth.h b/drivers/net/ti/icssg_prueth.h
index 26b77dd8f3..f34ab5d6d4 100644
--- a/drivers/net/ti/icssg_prueth.h
+++ b/drivers/net/ti/icssg_prueth.h
@@ -75,4 +75,9 @@ void icssg_config_ipg(struct prueth *prueth, int speed, int
mii);
int icssg_config(struct prueth *prueth);
int emac_set_port_state(struct prueth *prueth, enum icssg_port_state_cmd cmd);
+/* Buffer queue helpers */
+int icssg_queue_pop(struct prueth *prueth, u8 queue);
+void icssg_queue_push(struct prueth *prueth, int queue, u16 addr);
+u32 icssg_queue_level(struct prueth *prueth, int queue);
+
#endif /* __NET_TI_ICSSG_PRUETH_H */
diff --git a/drivers/net/ti/icssg_queues.c b/drivers/net/ti/icssg_queues.c
new file mode 100644
index 00..6a95ef5d58
--- /dev/null
+++ b/drivers/net/ti/icssg_queues.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0
+/* ICSSG Buffer queue helpers
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#include
+#include
+#include "icssg_prueth.h"
+
+#define ICSSG_QUEUES_MAX 64
+#define ICSSG_QUEUE_OFFSET 0xd00
+#define ICSSG_QUEUE_PEEK_OFFSET0xe00
+#define ICSSG_QUEUE_CNT_OFFSET 0xe40
+#defineICSSG_QUEUE_RESET_OFFSET0xf40
+
+int icssg_queue_pop(struct prueth *prueth, u8 queue)
+{
+ u32 val, cnt;
+
+ if (queue >= ICSSG_QUEUES_MAX)
+ return -EINVAL;
+
+ regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, &cnt);
+ if (!cnt)
+ return -EINVAL;
+
+ regmap_read(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, &val);
+
+ return val;
+}
+
+void icssg_queue_push(struct prueth *prueth, int queue, u16 addr)
+{
+ if (queue >= ICSSG_QUEUES_MAX)
+ return;
+
+ regmap_write(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, addr);
+}
+
+u32 icssg_queue_level(struct prueth *prueth, int queue)
+{
+ u32 reg;
+
+ if (queue >= ICSSG_QUEUES_MAX)
+ return 0;
+
+ regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, ®);
+
+ return reg;
+}
--
2.34.1
[RFC PATCH 10/16] arm: dts: k3-am65-main: Add ICSSG IEP nodes
The ICSSG IP on AM65x SoCs have two Industrial Ethernet Peripherals (IEPs)
to manage/generate Industrial Ethernet functions such as time stamping.
Each IEP sub-module is sourced from an internal clock mux that can be
sourced from either of the IP instance's ICSSG_IEP_GCLK or ICSSG_ICLK.
Add the IEP nodes for all the ICSSG instances.
Signed-off-by: MD Danish Anwar
---
arch/arm/dts/k3-am65-main.dtsi | 36 ++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index 7f10520236..da48887559 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -969,6 +969,18 @@
};
};
+ icssg0_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
+ icssg0_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
icssg0_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1110,6 +1122,18 @@
};
};
+ icssg1_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
+ icssg1_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
icssg1_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1256,6 +1280,18 @@
reg = <0x32000 0x100>;
};
+ icssg2_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
+ icssg2_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
icssg2_mii_g_rt: mii-g-rt@33000 {
compatible = "ti,pruss-mii-g", "syscon";
reg = <0x33000 0x1000>;
--
2.34.1
[RFC PATCH 03/16] net: ti: icssg: Add Firmware config and classification APIs.
Add icssg_config.h / .c and icssg_classifier.c files. These are firmware configuration and classification related files. Add MII helper APIs and MACROs. These APIs and MACROs will be later used by ICSSG Ethernet driver. Also introduce icssg_prueth.h which has definition of prueth related structures. Signed-off-by: MD Danish Anwar --- drivers/net/ti/icss_mii_rt.h | 192 ++ drivers/net/ti/icssg_classifier.c | 376 drivers/net/ti/icssg_config.c | 403 ++ drivers/net/ti/icssg_config.h | 177 + drivers/net/ti/icssg_prueth.h | 78 ++ 5 files changed, 1226 insertions(+) create mode 100644 drivers/net/ti/icss_mii_rt.h create mode 100644 drivers/net/ti/icssg_classifier.c create mode 100644 drivers/net/ti/icssg_config.c create mode 100644 drivers/net/ti/icssg_config.h create mode 100644 drivers/net/ti/icssg_prueth.h diff --git a/drivers/net/ti/icss_mii_rt.h b/drivers/net/ti/icss_mii_rt.h new file mode 100644 index 00..6b2449e736 --- /dev/null +++ b/drivers/net/ti/icss_mii_rt.h @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* PRU-ICSS MII_RT register definitions + * + * Copyright (C) 2015-2020 Texas Instruments Incorporated - http://www.ti.com + */ + +#ifndef __NET_PRUSS_MII_RT_H__ +#define __NET_PRUSS_MII_RT_H__ + +#include + +/* PRUSS_MII_RT Registers */ +#define PRUSS_MII_RT_RXCFG00x0 +#define PRUSS_MII_RT_RXCFG10x4 +#define PRUSS_MII_RT_TXCFG00x10 +#define PRUSS_MII_RT_TXCFG10x14 +#define PRUSS_MII_RT_TX_CRC0 0x20 +#define PRUSS_MII_RT_TX_CRC1 0x24 +#define PRUSS_MII_RT_TX_IPG0 0x30 +#define PRUSS_MII_RT_TX_IPG1 0x34 +#define PRUSS_MII_RT_PRS0 0x38 +#define PRUSS_MII_RT_PRS1 0x3c +#define PRUSS_MII_RT_RX_FRMS0 0x40 +#define PRUSS_MII_RT_RX_FRMS1 0x44 +#define PRUSS_MII_RT_RX_PCNT0 0x48 +#define PRUSS_MII_RT_RX_PCNT1 0x4c +#define PRUSS_MII_RT_RX_ERR0 0x50 +#define PRUSS_MII_RT_RX_ERR1 0x54 + +/* PRUSS_MII_RT_RXCFG0/1 bits */ +#define PRUSS_MII_RT_RXCFG_RX_ENABLE BIT(0) +#define PRUSS_MII_RT_RXCFG_RX_DATA_RDY_MODE_DISBIT(1) +#define PRUSS_MII_RT_RXCFG_RX_CUT_PREAMBLE BIT(2) +#define PRUSS_MII_RT_RXCFG_RX_MUX_SEL BIT(3) +#define PRUSS_MII_RT_RXCFG_RX_L2_ENBIT(4) +#define PRUSS_MII_RT_RXCFG_RX_BYTE_SWAPBIT(5) +#define PRUSS_MII_RT_RXCFG_RX_AUTO_FWD_PRE BIT(6) +#define PRUSS_MII_RT_RXCFG_RX_L2_EOF_SCLR_DIS BIT(9) + +/* PRUSS_MII_RT_TXCFG0/1 bits */ +#define PRUSS_MII_RT_TXCFG_TX_ENABLE BIT(0) +#define PRUSS_MII_RT_TXCFG_TX_AUTO_PREAMBLEBIT(1) +#define PRUSS_MII_RT_TXCFG_TX_EN_MODE BIT(2) +#define PRUSS_MII_RT_TXCFG_TX_BYTE_SWAPBIT(3) +#define PRUSS_MII_RT_TXCFG_TX_MUX_SEL BIT(8) +#define PRUSS_MII_RT_TXCFG_PRE_TX_AUTO_SEQUENCEBIT(9) +#define PRUSS_MII_RT_TXCFG_PRE_TX_AUTO_ESC_ERR BIT(10) +#define PRUSS_MII_RT_TXCFG_TX_32_MODE_EN BIT(11) +#define PRUSS_MII_RT_TXCFG_TX_IPG_WIRE_CLK_EN BIT(12) /* SR2.0 onwards */ + +#define PRUSS_MII_RT_TXCFG_TX_START_DELAY_SHIFT16 +#define PRUSS_MII_RT_TXCFG_TX_START_DELAY_MASK GENMASK(25, 16) + +#define PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_SHIFT 28 +#define PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_MASK GENMASK(30, 28) + +/* PRUSS_MII_RT_TX_IPG0/1 bits */ +#define PRUSS_MII_RT_TX_IPG_IPG_SHIFT 0 +#define PRUSS_MII_RT_TX_IPG_IPG_MASK GENMASK(9, 0) + +/* PRUSS_MII_RT_PRS0/1 bits */ +#define PRUSS_MII_RT_PRS_COL BIT(0) +#define PRUSS_MII_RT_PRS_CRS BIT(1) + +/* PRUSS_MII_RT_RX_FRMS0/1 bits */ +#define PRUSS_MII_RT_RX_FRMS_MIN_FRM_SHIFT 0 +#define PRUSS_MII_RT_RX_FRMS_MIN_FRM_MASK GENMASK(15, 0) + +#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_SHIFT 16 +#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_MASK GENMASK(31, 16) + +/* Min/Max in MII_RT_RX_FRMS */ +/* For EMAC and Switch */ +#define PRUSS_MII_RT_RX_FRMS_MAX (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) +#define PRUSS_MII_RT_RX_FRMS_MIN_FRM (64) + +/* for HSR and PRP */ +#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_LRE (PRUSS_MII_RT_RX_FRMS_MAX + \ +ICSS_LRE_TAG_RCT_SIZE) +/* PRUSS_MII_RT_RX_PCNT0/1 bits */ +#define PRUSS_MII_RT_RX_PCNT_MIN_PCNT_SHIFT0 +#define PRUSS_MII_RT_RX_PCNT_MIN_PCNT_MASK GENMASK(3, 0) + +#define PRUSS_MII_RT_RX_PCNT_MAX_PCNT_SHIFT4 +#define PRUSS_MII_RT_RX_PCNT_MAX_PCNT_MASK GENMASK(7, 4) + +/* PRUSS_MII_RT_RX_ERR0/1 bits */ +#define PRUSS_MII_RT_RX_ERR_MIN_PCNT_ERR BIT(0) +#define PRUSS_MII_RT_RX_ERR_MAX_PCNT_ERR BIT(1) +#define PRUSS_MII_RT_RX_ERR_MIN_FRM_ERRBIT(2) +#define PRUSS_MII_RT_RX_ERR_MAX_FRM_ERRBIT(3) + +#define ICSSG_CFG_OFFSET 0 +#define RGMII_CFG_OFFSET 4 + +/* Constant to choose between MII0 and MII1 */ +#define ICSS_MII0 0 +#define ICSS_MII1
[RFC PATCH 13/16] configs: am65x_evm_a53: Enable ICSSG Driver
Enable ICSSG driver in am65x_evm_a53_defconfig Signed-off-by: MD Danish Anwar --- configs/am65x_evm_a53_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 55289b967b..e79a961317 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -130,6 +130,7 @@ CONFIG_PHY_FIXED=y CONFIG_E1000=y CONFIG_CMD_E1000=y CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_TI_ICSSG_PRUETH=y CONFIG_PCI_KEYSTONE=y CONFIG_PHY=y CONFIG_SPL_PHY=y -- 2.34.1
[RFC PATCH 07/16] net: ti: icssg: Enforce pinctrl state on the MDIO child node
The binding represents the MDIO controller as a child device tree
node of the MAC device tree node.
The U-Boot driver mostly ignores that child device tree node and just
hardcodes the resources it uses to support both the MAC and MDIO in a
single driver.
However, some resources like pinctrl muxing states are thus ignored.
This has been a problem with some device trees that will put some
pinctrl states on the MDIO device tree node.
Let's rework the driver a bit to create a dummy MDIO driver that we will
then get during our initialization to force the core to select the right
muxing.
Signed-off-by: MD Danish Anwar
---
drivers/net/ti/Kconfig| 1 +
drivers/net/ti/icssg_prueth.c | 59 +++
2 files changed, 60 insertions(+)
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index 9fead2c7ce..6935b70e12 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -53,6 +53,7 @@ config TI_AM65_CPSW_NUSS
config TI_ICSSG_PRUETH
bool "TI Gigabit PRU Ethernet driver"
depends on ARCH_K3
+ imply DM_MDIO
select PHYLIB
help
Support Gigabit Ethernet ports over the ICSSG PRU Subsystem
diff --git a/drivers/net/ti/icssg_prueth.c b/drivers/net/ti/icssg_prueth.c
index 1a7445a015..40ad827e49 100644
--- a/drivers/net/ti/icssg_prueth.c
+++ b/drivers/net/ti/icssg_prueth.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -100,9 +101,56 @@ static int icssg_phy_init(struct udevice *dev)
return ret;
}
+static ofnode prueth_find_mdio(ofnode parent)
+{
+ ofnode node;
+
+ ofnode_for_each_subnode(node, parent)
+ if (ofnode_device_is_compatible(node, "ti,davinci_mdio"))
+ return node;
+
+ return ofnode_null();
+}
+
+static int prueth_mdio_setup(struct udevice *dev)
+{
+ struct prueth *priv = dev_get_priv(dev);
+ struct udevice *mdio_dev;
+ ofnode mdio;
+ int ret;
+
+ mdio = prueth_find_mdio(dev_ofnode(priv->pruss));
+ if (!ofnode_valid(mdio))
+ return 0;
+
+ /*
+* The MDIO controller is represented in the DT binding by a
+* subnode of the MAC controller.
+*
+* We don't have a DM driver for the MDIO device yet, and thus any
+* pinctrl setting on its node will be ignored.
+*
+* However, we do need to make sure the pins states tied to the
+* MDIO node are configured properly. Fortunately, the core DM
+* does that for use when we get a device, so we can work around
+* that whole issue by just requesting a dummy MDIO driver to
+* probe, and our pins will get muxed.
+*/
+ ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, &mdio_dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static int icssg_mdio_init(struct udevice *dev)
{
struct prueth *prueth = dev_get_priv(dev);
+ int ret;
+
+ ret = prueth_mdio_setup(dev);
+ if (ret)
+ return ret;
prueth->bus = cpsw_mdio_init(dev->name, prueth->mdio_base,
prueth->mdio_freq,
@@ -593,3 +641,14 @@ U_BOOT_DRIVER(prueth) = {
.plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
+
+static const struct udevice_id prueth_mdio_ids[] = {
+ { .compatible = "ti,davinci_mdio" },
+ { }
+};
+
+U_BOOT_DRIVER(prueth_mdio) = {
+ .name = "prueth_mdio",
+ .id = UCLASS_MDIO,
+ .of_match = prueth_mdio_ids,
+};
--
2.34.1
[RFC PATCH 09/16] arm: dts: k3-am65: Add cfg reg region to ringacc node
Add register range of ringacc cfg node to k3-am65* dtsi files. This is normally under Device Management firmware control but some entities like bootloader have to access directly and thus required to be present in DT. Signed-off-by: MD Danish Anwar --- arch/arm/dts/k3-am65-main.dtsi | 5 +++-- arch/arm/dts/k3-am65-mcu.dtsi | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index 691c9978e6..7f10520236 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -603,8 +603,9 @@ reg = <0x0 0x3c00 0x0 0x40>, <0x0 0x3800 0x0 0x40>, <0x0 0x3112 0x0 0x100>, - <0x0 0x3300 0x0 0x4>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x3300 0x0 0x4>, + <0x0 0x3108 0x0 0x4>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <818>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi index d7111aa8b2..b7f0456de7 100644 --- a/arch/arm/dts/k3-am65-mcu.dtsi +++ b/arch/arm/dts/k3-am65-mcu.dtsi @@ -129,8 +129,9 @@ reg = <0x0 0x2b80 0x0 0x40>, <0x0 0x2b00 0x0 0x40>, <0x0 0x2859 0x0 0x100>, - <0x0 0x2a50 0x0 0x4>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x2a50 0x0 0x4>, + <0x0 0x2844 0x0 0x4>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; -- 2.34.1
[RFC PATCH 08/16] arm: dts: k3-am65: Add additional regs for DMA components
Add additional reg properties for UDMA and RingAcc nodes which are mostly used by bootloader components before Device Manager firmware services are available, in order to setup DMA transfers. Signed-off-by: MD Danish Anwar --- arch/arm/dts/k3-am65-main.dtsi | 8 ++-- arch/arm/dts/k3-am65-mcu.dtsi | 8 ++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index ba4e5d3e1e..691c9978e6 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -616,8 +616,12 @@ compatible = "ti,am654-navss-main-udmap"; reg = <0x0 0x3115 0x0 0x100>, <0x0 0x3400 0x0 0x10>, - <0x0 0x3500 0x0 0x10>; - reg-names = "gcfg", "rchanrt", "tchanrt"; + <0x0 0x3500 0x0 0x10>, + <0x0 0x30b0 0x0 0x2>, + <0x0 0x30c0 0x0 0x8000>, + <0x0 0x30d0 0x0 0x4000>; + reg-names = "gcfg", "rchanrt", "tchanrt", + "tchan", "rchan", "rflow"; msi-parent = <&inta_main_udmass>; #dma-cells = <1>; diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi index c93ff1520a..d7111aa8b2 100644 --- a/arch/arm/dts/k3-am65-mcu.dtsi +++ b/arch/arm/dts/k3-am65-mcu.dtsi @@ -142,8 +142,12 @@ compatible = "ti,am654-navss-mcu-udmap"; reg = <0x0 0x285c 0x0 0x100>, <0x0 0x2a80 0x0 0x4>, - <0x0 0x2aa0 0x0 0x4>; - reg-names = "gcfg", "rchanrt", "tchanrt"; + <0x0 0x2aa0 0x0 0x4>, + <0x0 0x284a 0x0 0x4000>, + <0x0 0x284c 0x0 0x4000>, + <0x0 0x2840 0x0 0x2000>; + reg-names = "gcfg", "rchanrt", "tchanrt", + "tchan", "rchan", "rflow"; msi-parent = <&inta_main_udmass>; #dma-cells = <1>; -- 2.34.1
[RFC PATCH 16/16] board: ti: am65x: Add check for k3-am654-icssg2 in board_fit_config_match()
When CONFIG_TI_ICSSG_PRUETH is enabled, add config name check for the
icssg2 overlay in board_fit_config_match() API.
Signed-off-by: MD Danish Anwar
---
board/ti/am65x/evm.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index df209021c1..0b661f0084 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -90,10 +90,13 @@ int dram_init_banksize(void)
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
-#ifdef CONFIG_TARGET_AM654_A53_EVM
- if (!strcmp(name, "k3-am654-base-board"))
- return 0;
-#endif
+ if (IS_ENABLED(CONFIG_TI_ICSSG_PRUETH)) {
+ if (!strcmp(name, "k3-am654-icssg2"))
+ return 0;
+ } else {
+ if (!strcmp(name, "k3-am654-base-board"))
+ return 0;
+ }
return -1;
}
--
2.34.1
[RFC PATCH 12/16] arm: dts: k3-am65x-binman: Add ICSSG2 overlay and configuration
Add ICSSG2 overlay and configuration to tispl and u-boot images.
Signed-off-by: MD Danish Anwar
---
arch/arm/dts/k3-am65x-binman.dtsi | 85 +++
1 file changed, 85 insertions(+)
diff --git a/arch/arm/dts/k3-am65x-binman.dtsi
b/arch/arm/dts/k3-am65x-binman.dtsi
index 8cc24da1f3..9a0c0fca47 100644
--- a/arch/arm/dts/k3-am65x-binman.dtsi
+++ b/arch/arm/dts/k3-am65x-binman.dtsi
@@ -98,6 +98,8 @@
#define SPL_AM654_EVM_DTB "spl/dts/k3-am654-base-board.dtb"
#define AM654_EVM_DTB "u-boot.dtb"
+#define AM654_EVM_ICSSG2_DTBO "arch/arm/dts/k3-am654-icssg2.dtbo"
+
&binman {
ti-spl {
insert-template = <&ti_spl_template>;
@@ -124,6 +126,20 @@
filename = SPL_AM654_EVM_DTB;
};
};
+
+ fdt-1 {
+ description = "k3-am654-icssg2 overlay";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content =
<&spl_am65x_evm_icssg2_dtb>;
+ keyfile = "custMpk.pem";
+ };
+ spl_am65x_evm_icssg2_dtb: blob-ext {
+ filename =
AM654_EVM_ICSSG2_DTBO;
+ };
+ };
};
configurations {
@@ -135,6 +151,13 @@
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
+
+ conf-1 {
+ description = "k3-am654-icssg2";
+ firmware = "atf";
+ loadables = "tee", "dm", "spl";
+ fdt = "fdt-0", "fdt-1";
+ };
};
};
};
@@ -168,6 +191,24 @@
};
};
+ fdt-1 {
+ description = "k3-am654-icssg2 overlay";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content =
<&am65x_evm_icssg2_dtb>;
+ keyfile = "custMpk.pem";
+
+ };
+ am65x_evm_icssg2_dtb: blob-ext {
+ filename =
AM654_EVM_ICSSG2_DTBO;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+
};
configurations {
@@ -179,6 +220,13 @@
loadables = "uboot";
fdt = "fdt-0";
};
+
+ conf-1 {
+ description = "k3-am654-icssg2";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-0", "fdt-1";
+ };
};
};
};
@@ -205,6 +253,16 @@
filename = SPL_AM654_EVM_DTB;
};
};
+
+ fdt-1 {
+ description = "k3-am654-icssg2 overlay";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ blob {
+ filename =
AM654_EVM_ICSSG2_DTBO;
+ };
+ };
};
configurations {
@@ -216,6 +274,13 @@
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
+
+ conf-1 {
+ descri
[RFC PATCH 14/16] configs: am65x_evm_a53_defconfig: add SPL_LOAD_FIT_APPLY_OVERLAY
We want SPL to apply DTB overlays (e.g. NAND card overlay) so enable SPL_LOAD_FIT_APPLY_OVERLAY. Increase SPL_LOAD_FIT_APPLY_OVERLAY_BUF_SZ and SPL_STACK_R_MALLOC_SIMPLE_LEN. Without this SPL hangs. Signed-off-by: MD Danish Anwar --- configs/am65x_evm_a53_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index e79a961317..2755d7082f 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -70,6 +70,9 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY_BUF_SZ=0x10 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x100 CONFIG_CMD_USB=y CONFIG_CMD_TIME=y CONFIG_MTDIDS_DEFAULT="nor0=4704.spi.0" -- 2.34.1
[RFC PATCH 11/16] arm: dts: k3-am654-base-board: Add ICSSG2 Ethernet support
ICSSG2 provides dual Gigabit Ethernet support.
Add ICSSG2 ethernet node to an overlay k3-am654-icssg2.dtso
Signed-off-by: MD Danish Anwar
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/k3-am654-icssg2.dtso | 145 ++
2 files changed, 147 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/k3-am654-icssg2.dtso
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e9e58c5478..2bc53fba89 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1396,7 +1396,8 @@ dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am6548-iot2050-advanced-pg2.dtb \
k3-am6548-iot2050-advanced-m2.dtb \
k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo \
- k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo
+ k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo \
+ k3-am654-icssg2.dtbo
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
diff --git a/arch/arm/dts/k3-am654-icssg2.dtso
b/arch/arm/dts/k3-am654-icssg2.dtso
new file mode 100644
index 00..faefa2febc
--- /dev/null
+++ b/arch/arm/dts/k3-am654-icssg2.dtso
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT overlay for enabling ICSSG2 on AM654 EVM
+ *
+ * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include
+#include "k3-pinctrl.h"
+
+&{/} {
+ aliases {
+ ethernet1 = "/icssg2-eth/ethernet-ports/port@0";
+ ethernet2 = "/icssg2-eth/ethernet-ports/port@1";
+ };
+
+ /* Ethernet node on PRU-ICSSG2 */
+ icssg2_eth: icssg2-eth {
+ compatible = "ti,am654-icssg-prueth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg2_rgmii_pins_default>;
+ sram = <&msmc_ram>;
+ ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>,
+ <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>;
+ firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
+
+ ti,pruss-gp-mux-sel = <2>, /* MII mode */
+ <2>,
+ <2>,
+ <2>, /* MII mode */
+ <2>,
+ <2>;
+
+ ti,mii-g-rt = <&icssg2_mii_g_rt>;
+ ti,mii-rt = <&icssg2_mii_rt>;
+ ti,iep = <&icssg2_iep0>, <&icssg2_iep1>;
+
+ interrupt-parent = <&icssg2_intc>;
+ interrupts = <24 0 2>, <25 1 3>;
+ interrupt-names = "tx_ts0", "tx_ts1";
+
+ dmas = <&main_udmap 0xc300>, /* egress slice 0 */
+ <&main_udmap 0xc301>, /* egress slice 0 */
+ <&main_udmap 0xc302>, /* egress slice 0 */
+ <&main_udmap 0xc303>, /* egress slice 0 */
+ <&main_udmap 0xc304>, /* egress slice 1 */
+ <&main_udmap 0xc305>, /* egress slice 1 */
+ <&main_udmap 0xc306>, /* egress slice 1 */
+ <&main_udmap 0xc307>, /* egress slice 1 */
+ <&main_udmap 0x4300>, /* ingress slice 0 */
+ <&main_udmap 0x4301>; /* ingress slice 1 */
+
+ dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
+ "tx1-0", "tx1-1", "tx1-2", "tx1-3",
+ "rx0", "rx1";
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ icssg2_emac0: port@0 {
+ reg = <0>;
+ phy-handle = <&icssg2_phy0>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4120>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ icssg2_emac1: port@1 {
+ reg = <1>;
+ phy-handle = <&icssg2_phy1>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4124>;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+
[RFC PATCH 15/16] tools/fdtgrep: Include __symbols__ table
This is required for overlays to work at SPL.
Loading of symbol table depends on DT Overlay support in SPL
so make it compile-time dependent. Without this SPL fails to
boot some platforms where this feature is not enabled
(e.g. dra71-evm.)
Without including the file, the symbol
CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY will not be visible and
we will never include the symbol table.
So include
Due to some reason it needs to be included after
[#include "fdt_host.h"] otherwise it causes a build error.
Signed-off-by: MD Danish Anwar
---
tools/fdtgrep.c | 8
1 file changed, 8 insertions(+)
diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c
index 7eabcab439..706b4a35f4 100644
--- a/tools/fdtgrep.c
+++ b/tools/fdtgrep.c
@@ -22,6 +22,8 @@
#include "fdt_host.h"
#include "libfdt_internal.h"
+#include
+
/* Define DEBUG to get some debugging output on stderr */
#ifdef DEBUG
#define debug(a, b...) fprintf(stderr, a, ## b)
@@ -1234,6 +1236,12 @@ int main(int argc, char *argv[])
disp.fout = stdout;
}
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY)) {
+ /* include symbol table */
+ if (value_add(&disp, &disp.value_head, FDT_IS_NODE, 1,
"/__symbols__"))
+ usage("Cannot add __symbols__ value");
+ }
+
/* Run the grep and output the results */
ret = do_fdtgrep(&disp, filename);
if (disp.output_fname)
--
2.34.1
RE: [PATCH 08/13] clk: exynos: Add Exynos850 clock driver
> -Original Message- > From: U-Boot On Behalf Of Sam Protsenko > Sent: Wednesday, December 13, 2023 12:17 PM > To: Minkyu Kang ; Tom Rini ; > Lukasz Majewski ; Sean Anderson > Cc: Simon Glass ; Heinrich Schuchardt > ; u-boot@lists.denx.de > Subject: [PATCH 08/13] clk: exynos: Add Exynos850 clock driver > > Heavily influenced by its Linux kernel counterpart. It's implemented on > top of recently added Samsung CCF clock framework API. For now only UART > leaf clocks are implemented, along with all preceding clocks in CMU_TOP > and CMU_PERI. The UART baud clock is required in the serial driver, to > get its rate for the consequent baud rate calculation. > > Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park
RE: [PATCH 07/13] clk: exynos: Add Samsung clock framework
> -Original Message-
> From: U-Boot On Behalf Of Sam Protsenko
> Sent: Wednesday, December 13, 2023 12:17 PM
> To: Minkyu Kang ; Tom Rini ;
> Lukasz Majewski ; Sean Anderson
> Cc: Simon Glass ; Heinrich Schuchardt
> ; u-boot@lists.denx.de
> Subject: [PATCH 07/13] clk: exynos: Add Samsung clock framework
>
> Heavily based on Linux kernel Samsung clock framework, with some changes
> to accommodate the differences in U-Boot CCF implementation. It's also
> quite minimal as compared to the Linux version.
>
> Signed-off-by: Sam Protsenko
> ---
> drivers/clk/exynos/Makefile | 9 +-
> drivers/clk/exynos/clk-pll.c | 167 +
> drivers/clk/exynos/clk-pll.h | 23
> drivers/clk/exynos/clk.c | 121 +++
> drivers/clk/exynos/clk.h | 228 +++
> 5 files changed, 546 insertions(+), 2 deletions(-)
> create mode 100644 drivers/clk/exynos/clk-pll.c
> create mode 100644 drivers/clk/exynos/clk-pll.h
> create mode 100644 drivers/clk/exynos/clk.c
> create mode 100644 drivers/clk/exynos/clk.h
>
> diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile
> index 7faf238571ef..04c5b9a39e16 100644
> --- a/drivers/clk/exynos/Makefile
> +++ b/drivers/clk/exynos/Makefile
> @@ -1,6 +1,11 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
> # Copyright (C) 2016 Samsung Electronics
> -# Thomas Abraham
> +# Copyright (C) 2023 Linaro Ltd.
> +#
> +# Authors:
> +# Thomas Abraham
> +# Sam Protsenko
>
> -obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
> +obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-pll.o
> +obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
> diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c
> new file mode 100644
> index ..9e496ff83aaf
> --- /dev/null
> +++ b/drivers/clk/exynos/clk-pll.c
> @@ -0,0 +1,167 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2016 Samsung Electronics
> + * Copyright (C) 2023 Linaro Ltd.
> + *
> + * Authors:
> + * Thomas Abraham
Need to correct Thomas's email to samsung.com if you want to keep his
original credit even though his e-mail was already stale since he left the
company.
> + * Sam Protsenko
> + *
> + * This file contains the utility functions to register the pll clocks.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "clk.h"
> +
> +#define UBOOT_DM_CLK_SAMSUNG_PLL0822X"samsung_clk_pll0822x"
> +#define UBOOT_DM_CLK_SAMSUNG_PLL0831X"samsung_clk_pll0831x"
> +
> +struct samsung_clk_pll {
> + struct clk clk;
> + void __iomem*con_reg;
> + enum samsung_pll_type type;
> +};
> +
> +#define to_clk_pll(_clk) container_of(_clk, struct samsung_clk_pll, clk)
> +
> +/*
> + * PLL0822x Clock Type
> + */
> +
> +#define PLL0822X_MDIV_MASK 0x3ff
> +#define PLL0822X_PDIV_MASK 0x3f
> +#define PLL0822X_SDIV_MASK 0x7
> +#define PLL0822X_MDIV_SHIFT 16
> +#define PLL0822X_PDIV_SHIFT 8
> +#define PLL0822X_SDIV_SHIFT 0
> +
> +static unsigned long samsung_pll0822x_recalc_rate(struct clk *clk)
> +{
> + struct samsung_clk_pll *pll = to_clk_pll(clk);
> + u32 mdiv, pdiv, sdiv, pll_con3;
> + u64 fvco = clk_get_parent_rate(clk);
> +
> + pll_con3 = readl_relaxed(pll->con_reg);
> + mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;
> + pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
> + sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
> +
> + fvco *= mdiv;
> + do_div(fvco, (pdiv << sdiv));
> + return (unsigned long)fvco;
> +}
> +
> +static const struct clk_ops samsung_pll0822x_clk_min_ops = {
> + .get_rate = samsung_pll0822x_recalc_rate,
> +};
> +
> +/*
> + * PLL0831x Clock Type
> + */
> +
> +#define PLL0831X_KDIV_MASK 0x
> +#define PLL0831X_MDIV_MASK 0x1ff
> +#define PLL0831X_PDIV_MASK 0x3f
> +#define PLL0831X_SDIV_MASK 0x7
> +#define PLL0831X_MDIV_SHIFT 16
> +#define PLL0831X_PDIV_SHIFT 8
> +#define PLL0831X_SDIV_SHIFT 0
> +#define PLL0831X_KDIV_SHIFT 0
> +
> +static unsigned long samsung_pll0831x_recalc_rate(struct clk *clk)
> +{
> + struct samsung_clk_pll *pll = to_clk_pll(clk);
> + u32 mdiv, pdiv, sdiv, pll_con3, pll_con5;
> + s16 kdiv;
> + u64 fvco = clk_get_parent_rate(clk);
> +
> + pll_con3 = readl_relaxed(pll->con_reg);
> + pll_con5 = readl_relaxed(pll->con_reg + 8);
> + mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK;
> + pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK;
> + sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK;
> + kdiv = (s16)((pll_con5 >> PLL0831X_KDIV_SHIFT) &
> PLL0831X_KDIV_MASK);
> +
> + fvco *= (mdiv << 16) + kdiv;
> + do_div(fvco, (pdiv << sdiv));
> + fvco >>= 16;
> +
> + return (unsigne
RE: [PATCH 05/13] soc: samsung: Add Exynos PMU driver
> -Original Message- > From: U-Boot On Behalf Of Sam Protsenko > Sent: Wednesday, December 13, 2023 12:17 PM > To: Minkyu Kang ; Tom Rini ; > Lukasz Majewski ; Sean Anderson > Cc: Simon Glass ; Heinrich Schuchardt > ; u-boot@lists.denx.de > Subject: [PATCH 05/13] soc: samsung: Add Exynos PMU driver > > Add basic Power Management Unit (PMU) driver for Exynos SoCs. For now > it's only capable of changing UART path in PMU, which is needed for > E850-96 board. The driver's structure resembles the exynos-pmu driver > from Linux kernel, and although it's very basic and slim at the moment, > it can be easily extended in future if the need arises. > > UCLASS_NOP is used, as there are no benefits in using more elaborate > classes like UCLASS_MISC in this case. The DM_FLAG_PROBE_AFTER_BIND flag > is added in bind function, as the probe function must be always called > for this driver. > > Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park
RE: [PATCH 04/13] soc: samsung: Add Exynos USI driver
> -Original Message- > From: U-Boot On Behalf Of Sam Protsenko > Sent: Wednesday, December 13, 2023 12:17 PM > To: Minkyu Kang ; Tom Rini ; > Lukasz Majewski ; Sean Anderson > Cc: Simon Glass ; Heinrich Schuchardt > ; u-boot@lists.denx.de > Subject: [PATCH 04/13] soc: samsung: Add Exynos USI driver > > USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and > provides selectable serial protocol (one of: UART, SPI, I2C). USIv2 > registers usually reside in the same register map as a particular > underlying protocol it implements, but have some particular offset. E.g. > on Exynos850 the USI_UART has 0x1382 base address, where UART > registers have 0x00..0x40 offsets, and USI registers have 0xc0..0xdc > offsets. Desired protocol can be chosen via SW_CONF register from System > Register block of the same domain as USI. > > Before starting to use a particular protocol, USIv2 must be configured > properly: > 1. Select protocol to be used via System Register > 2. Clear "reset" flag in USI_CON > 3. Configure HWACG behavior (e.g. for UART Rx the HWACG must be > disabled, so that the IP clock is not gated automatically); this is > done using USI_OPTION register > 4. Keep both USI clocks (PCLK and IPCLK) running during USI registers > modification > > This driver implements the above behavior. Of course, USIv2 driver > should be probed before UART/I2C/SPI drivers. It can be achieved by > embedding UART/I2C/SPI nodes inside of the USI node (in Device Tree); > driver then walks underlying nodes and instantiates those. Driver also > handles USI configuration on PM resume, as register contents can be lost > during CPU suspend. > > This driver is designed with different USI versions in mind. So it > should be relatively easy to add new USI revisions to it later. > > Driver's code was copied over from Linux kernel [1] and adapted > correspondingly for U-Boot API. UCLASS_MISC is used, and although no > misc operations are implemented, it makes it easier to probe the driver > this way (as compared to UCLASS_NOP) and keep the code compact. > > [1] drivers/soc/samsung/exynos-usi.c > > Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park
RE: [PATCH 06/13] clk: exynos: Move pll code into clk-exynos7420
> -Original Message- > From: U-Boot On Behalf Of Sam Protsenko > Sent: Wednesday, December 13, 2023 12:17 PM > To: Minkyu Kang ; Tom Rini ; > Lukasz Majewski ; Sean Anderson > Cc: Simon Glass ; Heinrich Schuchardt > ; u-boot@lists.denx.de > Subject: [PATCH 06/13] clk: exynos: Move pll code into clk-exynos7420 > > PLL utilities code is only used by clk-exynos7420 driver at the moment. > Move it into clk-exynos7420 to make clk-pll.c file available for CCF PLL > clocks implementation, which is coming in the next patches. > > Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park
Re: [PATCH v2 02/17] video: dw_hdmi: Add Vendor PHY handling
On Tue, Dec 19, 2023 at 2:34 PM Neil Armstrong
wrote:
>
> On 18/12/2023 20:10, Jagan Teki wrote:
> > From: Jagan Teki
> >
> > DW HDMI support Vendor PHY like Rockchip RK3328 Inno HDMI PHY.
> >
> > Extend the vendor phy handling by adding platform phy hooks.
> >
> > Signed-off-by: Jagan Teki
> > ---
> > Changes for v2:
> > - fix meson cfg
> >
> > drivers/video/dw_hdmi.c | 29 +++-
> > drivers/video/meson/meson_dw_hdmi.c | 11 ++-
> > drivers/video/rockchip/rk3399_hdmi.c | 8 +++-
> > drivers/video/rockchip/rk_hdmi.c | 2 +-
> > drivers/video/sunxi/sunxi_dw_hdmi.c | 11 ++-
> > include/dw_hdmi.h| 14 +-
> > 6 files changed, 69 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
> > index c4fbb18294..ea12a09407 100644
> > --- a/drivers/video/dw_hdmi.c
> > +++ b/drivers/video/dw_hdmi.c
> > @@ -988,7 +988,7 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct
> > display_timing *edid)
> >
> > hdmi_av_composer(hdmi, edid);
> >
> > - ret = hdmi->phy_set(hdmi, edid->pixelclock.typ);
> > + ret = hdmi->ops->phy_set(hdmi, edid->pixelclock.typ);
> > if (ret)
> > return ret;
> >
> > @@ -1009,10 +1009,37 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const
> > struct display_timing *edid)
> > return 0;
> > }
> >
> > +static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
> > + .phy_set = dw_hdmi_phy_cfg,
> > +};
> > +
> > +static void dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
> > +{
> > + if (!hdmi->data)
> > + return;
> > +
> > + /* hook Synopsys PHYs ops */
> > + if (!hdmi->data->phy_force_vendor) {
> > + hdmi->ops = &dw_hdmi_synopsys_phy_ops;
> > + return;
> > + }
> > +
> > + /* Vendor HDMI PHYs must assign phy_ops in plat_data */
> > + if (!hdmi->data->phy_ops) {
> > + printf("Unsupported Vendor HDMI phy_ops\n");
> > + return;
> > + }
> > +
> > + /* hook Vendor HDMI PHYs ops */
> > + hdmi->ops = hdmi->data->phy_ops;
>
> Sorry but I still don't understand why you need phy_force_vendor & phy_ops,
> this code clearly fails if you have phy_force_vendor=true && phy_ops=NULL,
> so drop phy_force_vendor and simply use phy_ops if != NULL, and since it's
> the only element of dw_hdmi_plat_data, drop dw_hdmi_plat_data and pass
> dw_hdmi_phy_ops directly in the dw_hdmi struct.
>
> So in dw_hdmi_detect_phy(), if hdmi->ops is NULL, set it to
> dw_hdmi_synopsys_phy_ops.
Let me elaborate more.
DW HDMI IP must have phy ops. It never be NULL. Either it uses
1. Internal PHY via DW called them Synopsys PHYs ops - for example, rk3399
2. Vendor PHY via vendor phy meson, sunxi, rk3328
For case 1) phy_force_vendor is false so it uses dw_hdmi_synopsys_phy_ops
For case 2) phy_force_vendor is true so it uses dw_hdmi_plat_data phy ops
dw_hdmi_detect_phy assigns internal phy ops first and then vendor phy
ops based on phy_force_vendor flag.
If we remove dw_hdmi_plat_data how can we assign or differentiate two
types of phy ops hooks? can you explain?
Thanks,
Jagan.
[PATCH] cmd/mem.c: use memmove in do_mem_cp()
There's no 'mv' shell command for handling overlapping src and dst regions, and there's no point introducing one, when we can just make the existing 'cp' command DTRT in all cases. memmove() should at most be a few instructions more then memcpy() (to detect the appropriate direction to do the copy), which is of course completely in the noise with all the string processing that a shell command does. Signed-off-by: Rasmus Villemoes --- cmd/mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/mem.c b/cmd/mem.c index 66c2d36a148..c696b92a274 100644 --- a/cmd/mem.c +++ b/cmd/mem.c @@ -361,7 +361,7 @@ static int do_mem_cp(struct cmd_tbl *cmdtp, int flag, int argc, } #endif - memcpy(dst, src, count * size); + memmove(dst, src, count * size); unmap_sysmem(src); unmap_sysmem(dst); -- 2.40.1.1.g1c60b9335d
[PATCH] test/py: mdio: Add tests for mdio command
Add below test cases for mdio commands:
mdio_list - To list MDIO buses
mdio_read - To read PHY's register at .
mdio_write - To write PHY's register at .
Signed-off-by: Love Kumar
---
test/py/tests/test_mdio.py | 79 ++
1 file changed, 79 insertions(+)
create mode 100644 test/py/tests/test_mdio.py
diff --git a/test/py/tests/test_mdio.py b/test/py/tests/test_mdio.py
new file mode 100644
index ..89711e70b559
--- /dev/null
+++ b/test/py/tests/test_mdio.py
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0
+# (C) Copyright 2023, Advanced Micro Devices, Inc.
+
+import pytest
+import re
+
+"""
+Note: This test relies on boardenv_* containing configuration values to define
+the PHY device info including the device name, address, register address/value
+and write data value. This test will be automatically skipped without this.
+
+For example:
+
+# Setup env__mdio_util_test to set the PHY address, device names, register
+# address, register address value, and write data value to test mdio commands.
+# Test will be skipped if env_mdio_util_test is not set
+env__mdio_util_test = {
+"eth0": {"phy_addr": 0xc, "device_name": "TI DP83867", "reg": 0,
+ "reg_val": 0x1000, "write_val": 0x100},
+"eth1": {"phy_addr": 0xa0, "device_name": "TI DP83867", "reg": 1,
+ "reg_val": 0x2000, "write_val": 0x100},
+}
+"""
+
+def get_mdio_test_env(u_boot_console):
+f = u_boot_console.config.env.get("env__mdio_util_test", None)
+if not f or len(f) == 0:
+pytest.skip("No PHY device to test!")
+else:
+return f
+
+@pytest.mark.buildconfigspec("cmd_mii")
+@pytest.mark.buildconfigspec("phylib")
+def test_mdio_list(u_boot_console):
+f = get_mdio_test_env(u_boot_console)
+output = u_boot_console.run_command("mdio list")
+for dev, val in f.items():
+phy_addr = val.get("phy_addr")
+dev_name = val.get("device_name")
+
+assert f"{phy_addr:x} -" in output
+assert dev_name in output
+
+@pytest.mark.buildconfigspec("cmd_mii")
+@pytest.mark.buildconfigspec("phylib")
+def test_mdio_read(u_boot_console):
+f = get_mdio_test_env(u_boot_console)
+output = u_boot_console.run_command("mdio list")
+for dev, val in f.items():
+phy_addr = hex(val.get("phy_addr"))
+dev_name = val.get("device_name")
+reg = hex(val.get("reg"))
+reg_val = hex(val.get("reg_val"))
+
+output = u_boot_console.run_command(f"mdio read {phy_addr} {reg}")
+assert f"PHY at address {int(phy_addr, 16):x}:" in output
+assert f"{int(reg, 16):x} - {reg_val}" in output
+
+@pytest.mark.buildconfigspec("cmd_mii")
+@pytest.mark.buildconfigspec("phylib")
+def test_mdio_write(u_boot_console):
+f = get_mdio_test_env(u_boot_console)
+output = u_boot_console.run_command("mdio list")
+for dev, val in f.items():
+phy_addr = hex(val.get("phy_addr"))
+dev_name = val.get("device_name")
+reg = hex(val.get("reg"))
+reg_val = hex(val.get("reg_val"))
+wr_val = hex(val.get("write_val"))
+
+u_boot_console.run_command(f"mdio write {phy_addr} {reg} {wr_val}")
+output = u_boot_console.run_command(f"mdio read {phy_addr} {reg}")
+assert f"PHY at address {int(phy_addr, 16):x}:" in output
+assert f"{int(reg, 16):x} - {wr_val}" in output
+
+u_boot_console.run_command(f"mdio write {phy_addr} {reg} {reg_val}")
+output = u_boot_console.run_command(f"mdio read {phy_addr} {reg}")
+assert f"PHY at address {int(phy_addr, 16):x}:" in output
+assert f"{int(reg, 16):x} - {reg_val}" in output
--
2.25.1
[PATCH v3 0/9] acpi: add ACPI support on QEMU ARM and RISC-V
QEMU 8.1.2 can create ACPI tables for the ARM and RISC-V architectures Allow passing them through to the operating system. Provide a new config fragment that enables this. v3: let tables in global data depend on CONFIG_(SPL_)ACPI v2: consider ARM architecture too invoke write_acpi_tables() via EVT_LAST_STAGE_INIT Heinrich Schuchardt (9): acpi: Kconfig symbol CONFIG_QFW_ACPI acpi: carve out qfw_acpi.c arm: add ACPI fields to global data risc-v: add ACPI fields to global data acpi: enable writing ACPI tables on QEMU risc-v: add support for QEMU firmware tables riscv: allow usage of ACPI configs: qemu: add config fragment for ACPI arm: enable support for QEMU firmware tables MAINTAINERS | 1 + arch/Kconfig | 1 + arch/arm/include/asm/global_data.h | 7 +- arch/riscv/include/asm/global_data.h | 6 + board/emulation/configs/acpi.config | 3 + board/emulation/qemu-arm/Kconfig | 1 + board/emulation/qemu-riscv/Kconfig | 2 + doc/board/emulation/acpi.rst | 23 +++ doc/board/emulation/index.rst| 1 + drivers/misc/Kconfig | 7 + drivers/misc/Makefile| 1 + drivers/misc/qfw.c | 240 --- drivers/misc/qfw_acpi.c | 281 +++ lib/acpi/Makefile| 2 +- lib/acpi/acpi_writer.c | 4 +- 15 files changed, 336 insertions(+), 244 deletions(-) create mode 100644 board/emulation/configs/acpi.config create mode 100644 doc/board/emulation/acpi.rst create mode 100644 drivers/misc/qfw_acpi.c -- 2.40.1
[PATCH v3 1/9] acpi: Kconfig symbol CONFIG_QFW_ACPI
We have two implementations of write_acpi_tables(). One for writing ACPI
tables based on ACPI_WRITER() entries another based on copying tables from
QEMU.
Create a symbol CONFIG_QFW_ACPI that signifies copying ACPI tables from
QEMU and use it consistently.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Simon Glass
---
v3:
no change
v2:
no change
---
drivers/misc/Kconfig | 7 +++
drivers/misc/qfw.c | 4 ++--
lib/acpi/Makefile | 2 +-
lib/acpi/acpi_writer.c | 4 ++--
4 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index ed7ecedd3a..e8e4400516 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -540,6 +540,13 @@ config QFW
Hidden option to enable QEMU fw_cfg interface and uclass. This will
be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
+config QFW_ACPI
+ bool
+ default y
+ depends on QFW && GENERATE_ACPI_TABLE && !SANDBOX
+ help
+ Hidden option to read ACPI tables from QEMU.
+
config QFW_PIO
bool
depends on QFW
diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c
index e3b6b4cd74..307334faf4 100644
--- a/drivers/misc/qfw.c
+++ b/drivers/misc/qfw.c
@@ -21,7 +21,7 @@
#include
#include
-#if defined(CONFIG_GENERATE_ACPI_TABLE) && !defined(CONFIG_SANDBOX)
+#ifdef QFW_ACPI
/*
* This function allocates memory for ACPI tables
*
@@ -259,7 +259,7 @@ ulong acpi_get_rsdp_addr(void)
file = qfw_find_file(dev, "etc/acpi/rsdp");
return file->addr;
}
-#endif
+#endif /* QFW_ACPI */
static void qfw_read_entry_io(struct qfw_dev *qdev, u16 entry, u32 size,
void *address)
diff --git a/lib/acpi/Makefile b/lib/acpi/Makefile
index c1c9675b5d..cc2868488a 100644
--- a/lib/acpi/Makefile
+++ b/lib/acpi/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_$(SPL_)ACPIGEN) += acpi_table.o
obj-y += acpi_writer.o
# With QEMU the ACPI tables come from there, not from U-Boot
-ifndef CONFIG_QEMU
+ifndef CONFIG_QFW_ACPI
obj-y += base.o
obj-y += csrt.o
obj-y += mcfg.o
diff --git a/lib/acpi/acpi_writer.c b/lib/acpi/acpi_writer.c
index 946f90e8e7..9b9fdc190b 100644
--- a/lib/acpi/acpi_writer.c
+++ b/lib/acpi/acpi_writer.c
@@ -48,7 +48,7 @@ int acpi_write_one(struct acpi_ctx *ctx, const struct
acpi_writer *entry)
return 0;
}
-#ifndef CONFIG_QEMU
+#ifndef CONFIG_QFW_ACPI
static int acpi_write_all(struct acpi_ctx *ctx)
{
const struct acpi_writer *writer =
@@ -115,7 +115,7 @@ ulong acpi_get_rsdp_addr(void)
return map_to_sysmem(gd->acpi_ctx->rsdp);
}
-#endif /* QEMU */
+#endif /* QFW_ACPI */
void acpi_setup_ctx(struct acpi_ctx *ctx, ulong start)
{
--
2.40.1
[PATCH v3 3/9] arm: add ACPI fields to global data
Add fields for the location of ACPI tables to the global data.
Signed-off-by: Heinrich Schuchardt
---
v3:
let tables in global data depend on CONFIG_(SPL_)ACPI
v2:
new patch
---
arch/arm/include/asm/global_data.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/global_data.h
b/arch/arm/include/asm/global_data.h
index 75bd9d56f8..c3d87caa0b 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -19,7 +19,12 @@ struct arch_global_data {
#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_FSL_ESDHC_IMX)
u32 sdhc_clk;
#endif
-
+#if CONFIG_IS_ENABLED(ACPI)
+ ulong table_start; /* Start address of ACPI tables */
+ ulong table_end;/* End address of ACPI tables */
+ ulong table_start_high; /* Start address of high ACPI tables */
+ ulong table_end_high; /* End address of high ACPI tables */
+#endif
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_per_clk;
#endif
--
2.40.1
[PATCH v3 2/9] acpi: carve out qfw_acpi.c
Move the code related to copying tables from QEMU to a separate code
module.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Tom Rini
Reviewed-by: Simon Glass
---
v3:
no change
v2:
add missing blank line
---
drivers/misc/Makefile | 1 +
drivers/misc/qfw.c | 240 -
drivers/misc/qfw_acpi.c | 256
3 files changed, 257 insertions(+), 240 deletions(-)
create mode 100644 drivers/misc/qfw_acpi.c
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index b67b82358a..cda701d38e 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
ifdef CONFIG_QFW
obj-y += qfw.o
+obj-$(CONFIG_QFW_ACPI) += qfw_acpi.o
obj-$(CONFIG_QFW_PIO) += qfw_pio.o
obj-$(CONFIG_QFW_MMIO) += qfw_mmio.o
obj-$(CONFIG_SANDBOX) += qfw_sandbox.o
diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c
index 307334faf4..db98619fdf 100644
--- a/drivers/misc/qfw.c
+++ b/drivers/misc/qfw.c
@@ -21,246 +21,6 @@
#include
#include
-#ifdef QFW_ACPI
-/*
- * This function allocates memory for ACPI tables
- *
- * @entry : BIOS linker command entry which tells where to allocate memory
- * (either high memory or low memory)
- * @addr : The address that should be used for low memory allcation. If the
- * memory allocation request is 'ZONE_HIGH' then this parameter will
- * be ignored.
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_allocate(struct udevice *dev,
- struct bios_linker_entry *entry, ulong *addr)
-{
- uint32_t size, align;
- struct fw_file *file;
- unsigned long aligned_addr;
-
- align = le32_to_cpu(entry->alloc.align);
- /* align must be power of 2 */
- if (align & (align - 1)) {
- printf("error: wrong alignment %u\n", align);
- return -EINVAL;
- }
-
- file = qfw_find_file(dev, entry->alloc.file);
- if (!file) {
- printf("error: can't find file %s\n", entry->alloc.file);
- return -ENOENT;
- }
-
- size = be32_to_cpu(file->cfg.size);
-
- /*
-* ZONE_HIGH means we need to allocate from high memory, since
-* malloc space is already at the end of RAM, so we directly use it.
-* If allocation zone is ZONE_FSEG, then we use the 'addr' passed
-* in which is low memory
-*/
- if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
- aligned_addr = (unsigned long)memalign(align, size);
- if (!aligned_addr) {
- printf("error: allocating resource\n");
- return -ENOMEM;
- }
- if (aligned_addr < gd->arch.table_start_high)
- gd->arch.table_start_high = aligned_addr;
- if (aligned_addr + size > gd->arch.table_end_high)
- gd->arch.table_end_high = aligned_addr + size;
-
- } else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) {
- aligned_addr = ALIGN(*addr, align);
- } else {
- printf("error: invalid allocation zone\n");
- return -EINVAL;
- }
-
- debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align
%u, addr 0x%lx\n",
- file->cfg.name, size, entry->alloc.zone, align, aligned_addr);
-
- qfw_read_entry(dev, be16_to_cpu(file->cfg.select), size,
- (void *)aligned_addr);
- file->addr = aligned_addr;
-
- /* adjust address for low memory allocation */
- if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
- *addr = (aligned_addr + size);
-
- return 0;
-}
-
-/*
- * This function patches ACPI tables previously loaded
- * by bios_linker_allocate()
- *
- * @entry : BIOS linker command entry which tells how to patch
- * ACPI tables
- * @return: 0 on success, or negative value on failure
- */
-static int bios_linker_add_pointer(struct udevice *dev,
- struct bios_linker_entry *entry)
-{
- struct fw_file *dest, *src;
- uint32_t offset = le32_to_cpu(entry->pointer.offset);
- uint64_t pointer = 0;
-
- dest = qfw_find_file(dev, entry->pointer.dest_file);
- if (!dest || !dest->addr)
- return -ENOENT;
- src = qfw_find_file(dev, entry->pointer.src_file);
- if (!src || !src->addr)
- return -ENOENT;
-
- debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx,
offset 0x%x size %u, 0x%llx\n",
- dest->addr, src->addr, offset, entry->pointer.size, pointer);
-
- memcpy(&pointer, (char *)dest->addr + offset, entry->pointer.size);
- pointer = le64_to_cpu(pointer);
- pointer += (unsigned long)src->addr;
-
[PATCH v3 4/9] risc-v: add ACPI fields to global data
Add fields for the location of ACPI tables to the global data.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Simon Glass
---
v3:
let tables in global data depend on CONFIG_(SPL_)ACPI
v2:
no change
---
arch/riscv/include/asm/global_data.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/include/asm/global_data.h
b/arch/riscv/include/asm/global_data.h
index 937fa4d154..0f7c08a49d 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -32,6 +32,12 @@ struct arch_global_data {
ulong available_harts;
#endif
#endif
+#if CONFIG_IS_ENABLED(ACPI)
+ ulong table_start; /* Start address of ACPI tables */
+ ulong table_end;/* End address of ACPI tables */
+ ulong table_start_high; /* Start address of high ACPI tables */
+ ulong table_end_high; /* End address of high ACPI tables */
+#endif
#ifdef CONFIG_SMBIOS
ulong smbios_start; /* Start address of SMBIOS table */
#endif
--
2.40.1
[PATCH v3 5/9] acpi: enable writing ACPI tables on QEMU
Invoke write_acpi_tables() via EVT_LAST_STAGE_INIT on QEMU except on X86.
X86 calls write_acpi_tables() in write_tables().
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Simon Glass
---
v3:
no change
v2:
new patch
---
drivers/misc/qfw_acpi.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/misc/qfw_acpi.c b/drivers/misc/qfw_acpi.c
index 6e14b2a504..7ffed1e8c0 100644
--- a/drivers/misc/qfw_acpi.c
+++ b/drivers/misc/qfw_acpi.c
@@ -9,9 +9,11 @@
#include
#include
#include
+#include
#include
#include
#include
+#include
#include
#include
@@ -254,3 +256,26 @@ ulong acpi_get_rsdp_addr(void)
file = qfw_find_file(dev, "etc/acpi/rsdp");
return file->addr;
}
+
+#ifndef CONFIG_X86
+static int evt_write_acpi_tables(void)
+{
+ ulong addr, end;
+ void *ptr;
+
+ /* Reserve 64K for ACPI tables, aligned to a 4K boundary */
+ ptr = memalign(SZ_4K, SZ_64K);
+ if (!ptr)
+ return -ENOMEM;
+ addr = map_to_sysmem(ptr);
+
+ /* Generate ACPI tables */
+ end = write_acpi_tables(addr);
+ gd->arch.table_start = addr;
+ gd->arch.table_end = addr;
+
+ return 0;
+}
+
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, evt_write_acpi_tables);
+#endif
--
2.40.1
[PATCH v3 7/9] risc-v: allow usage of ACPI
Select CONFIG_SUPPORT_ACPI to allow usage of ACPI tables with RISC-V. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- v3: no change v2: no change --- arch/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/Kconfig b/arch/Kconfig index 2e0528d819..c23d57e4c4 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -108,6 +108,7 @@ config PPC config RISCV bool "RISC-V architecture" select CREATE_ARCH_SYMLINK + select SUPPORT_ACPI select SUPPORT_OF_CONTROL select OF_CONTROL select DM -- 2.40.1
[PATCH v3 6/9] risc-v: add support for QEMU firmware tables
Enable the QEMU firmware interface if ACPI tables are to be supported on the QEMU platform. Enable the QFW MMIO interface if the QEMU firmware interface is enabled. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass Reviewed-by: Ilias Apalodimas --- v3: no change v2: no change --- board/emulation/qemu-riscv/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index cdd0d0d95f..d5f302ffda 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -33,6 +33,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select GENERIC_RISCV select SUPPORT_SPL + select QFW if ACPI + select QFW_MMIO if QFW imply AHCI imply SMP imply BOARD_LATE_INIT -- 2.40.1
[PATCH v3 9/9] arm: enable support for QEMU firmware tables
Enable the QEMU firmware interface if ACPI tables are to be supported on the QEMU platform. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- v3: no change v2: new patch --- board/emulation/qemu-arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/emulation/qemu-arm/Kconfig b/board/emulation/qemu-arm/Kconfig index ac2d078f42..e21c135e86 100644 --- a/board/emulation/qemu-arm/Kconfig +++ b/board/emulation/qemu-arm/Kconfig @@ -5,6 +5,7 @@ config TEXT_BASE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select QFW if ACPI select QFW_MMIO if CMD_QFW imply VIRTIO_MMIO imply VIRTIO_PCI -- 2.40.1
[PATCH v3 8/9] configs: qemu: add config fragment for ACPI
Provide a configuration fragment to enable ACPI on QEMU. Signed-off-by: Heinrich Schuchardt Acked-by: Ilias Apalodimas Reviewed-by: Simon Glass --- v3: no change v2: no change --- MAINTAINERS | 1 + board/emulation/configs/acpi.config | 3 +++ doc/board/emulation/acpi.rst| 23 +++ doc/board/emulation/index.rst | 1 + 4 files changed, 28 insertions(+) create mode 100644 board/emulation/configs/acpi.config create mode 100644 doc/board/emulation/acpi.rst diff --git a/MAINTAINERS b/MAINTAINERS index 25f2bb80de..bf437b253b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -53,6 +53,7 @@ Maintainers List (try to look for most precise areas first) ACPI: M: Simon Glass S: Maintained +F: board/emulation/configs/acpi.config F: cmd/acpi.c F: lib/acpi/ diff --git a/board/emulation/configs/acpi.config b/board/emulation/configs/acpi.config new file mode 100644 index 00..b7ed811e33 --- /dev/null +++ b/board/emulation/configs/acpi.config @@ -0,0 +1,3 @@ +CONFIG_CMD_QFW=y +CONFIG_ACPI=y +CONFIG_GENERATE_ACPI_TABLE=y diff --git a/doc/board/emulation/acpi.rst b/doc/board/emulation/acpi.rst new file mode 100644 index 00..e1208ca51e --- /dev/null +++ b/doc/board/emulation/acpi.rst @@ -0,0 +1,23 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +ACPI on QEMU + + +QEMU can provide ACPI tables on ARM, RISC-V, and x86. + +The following settings are needed:: + +CONFIG_CMD_QFW=y +CONFIG_ACPI=y +CONFIG_GENERATE_ACPI_TABLE=y + +On x86 these settings are already included in the defconfig files. ARM and +RISC-V default to use device-trees. + +Instead of updating the configuration manually you can add the configuration +fragment `acpi.config` to the make command for initializing the configuration. +E.g. + +.. code-block:: bash + +make qemu-riscv64_smode_defconfig acpi.config diff --git a/doc/board/emulation/index.rst b/doc/board/emulation/index.rst index 932c65adeb..d3d6b8f3d8 100644 --- a/doc/board/emulation/index.rst +++ b/doc/board/emulation/index.rst @@ -6,6 +6,7 @@ Emulation .. toctree:: :maxdepth: 1 + acpi blkdev ../../usage/semihosting qemu-arm -- 2.40.1
Re: Adding EFI runtime support to the Arm's FF-A bus
> From: Michael Walle > Date: Tue, 19 Dec 2023 11:11:24 +0100 > > Hi Heinrich, Hi Michael, > > Any runtime device drivers for variable storage should not be in the > > U-Boot runtime but live in the secure world (e.g. OP-TEE) FF-A is the > > new ARM protocol for talking to the secure world and hence fits into > > the picture. > > What if I just want a simple embedded boot stack where I don't > want any secure world and just want to be able to boot a COTS linux > distribution via EFI? That already works for many Linux distros. As long as the distro installs the appropriate BOOTxxx.EFI file you don't actually need to set any EFI variables for the OS to boot. It can't get any simpler than that. Of the main Linux distros it seems that only Debian doesn't do this. Someone should probably lobby Debian to do this as well as it would mean that Debian would just work on an EBBR compliant system. Things get more complicated if you want to install multiple OSes. Then having EFI variable support makes things a lot more straightforward. And of course EFI secure boot needs EFI variable support as well (with proper support) for authenticated EFI variables. But IMHO that no longer falls into "simple embedded boot stack" territory. > Assuming, that there might be a simple dedicated EEPROM to store the > variables which is not exposed to linux, is that something which would > be rejected by u-boot mainline now? Not necessarily. But such an approach will have limitations: * Completely hiding the EEPROM from the OS may be hard. Even if you have a dedicated SPI controller for the EEPROM things like the SPI bus clock or power domains may still be under OS control. * It is not possible to properly implement authenticated variables for secure boot if the EEPROM and associated hardware is just removed from the device tree but still accessable to the OS. An implementation that pretends the variables are "secure" will probably be rejected. Cheers, Mark
Re: Proposal: U-Boot memory management
On Tue, Dec 19, 2023 at 03:15:38AM +0100, Heinrich Schuchardt wrote: > > > Am 19. Dezember 2023 02:26:00 MEZ schrieb Tom Rini : > >On Tue, Dec 19, 2023 at 01:01:51AM +0100, Heinrich Schuchardt wrote: > >> > >> > >> Am 19. Dezember 2023 00:31:30 MEZ schrieb Tom Rini : > >> >On Tue, Dec 19, 2023 at 12:29:19AM +0100, Heinrich Schuchardt wrote: > >> >> > >> >> > >> >> Am 19. Dezember 2023 00:16:40 MEZ schrieb Tom Rini : > >> >> >On Tue, Dec 19, 2023 at 12:08:31AM +0100, Heinrich Schuchardt wrote: > >> >> >> > >> >> >> > >> >> >> Am 18. Dezember 2023 23:41:08 MEZ schrieb Tom Rini > >> >> >> : > >> >> >> >On Mon, Dec 18, 2023 at 11:34:16PM +0100, Heinrich Schuchardt wrote: > >> >> >> > > >> >> >> >[snip] > >> >> >> >> Or take: > >> >> >> >> > >> >> >> >> load host 0:1 $c kernel.efi > >> >> >> >> load host 0:1 $d initrd.img > >> >> >> >> > >> >> >> >> How could we ensure that initrd.img is not overwriting a part of > >> >> >> >> kernel.efi without memory allocation? > >> >> >> > > >> >> >> >Today, invalid checksum as part of some part of the kernel fails. > >> >> >> >But > >> >> >> >how do we do this tomorrow, are you suggesting that "load" perform > >> >> >> >malloc() in some predefined size? If $c is below $d and $c + > >> >> >> >kernel.efi > >> >> >> >is now above $d we can throw an error before trying to load, yes. > >> >> >> >But > >> >> >> >what about: > >> >> >> >load host 0:1 $d initrd.img > >> >> >> >load host 0:1 $c kernel.efi > >> >> >> > > >> >> >> >In that case (which is only marginally contrived, the more real > >> >> >> >case is > >> >> >> >loading device tree in to unexpectedly large ramdisk because someone > >> >> >> >didn't understand the general advice on why device tree is lower > >> >> >> >than > >> >> >> >ramdisk address) I'm fine with an error that amounts to "you just > >> >> >> >corrupted another allocation" and then "fail, reset the board" or > >> >> >> >so. > >> >> >> > > >> >> >> > >> >> >> Our current malloc library cannot manage the complete memory. We > >> >> >> need a library like lmb which should also cover the memory > >> >> >> management that we currently have in lib/efi/efi_memory.c. This must > >> >> >> include a memory type attribute for usage in the GetMemoryMap() > >> >> >> service. A management on page level seems sufficient. > >> >> >> > >> >> >> The load command should permanently allocate memory in that lmb+ > >> >> >> library. > >> >> >> > >> >> >> We need an unload command to free the memory if we want to reuse the > >> >> >> memory or we might let the load comand free the memory if exactly > >> >> >> the same start address is reused. > >> >> > > >> >> >Our current way of loading things in to memory does not handle the case > >> >> >I described, yes. How would what you're proposing handle it? > >> >> > >> >> If the load command has to allocate memory for the image and that > >> >> allocation is kept, any attempt to allocate overlapping memory would > >> >> fail. > >> > > >> >So you're saying that the load command has to pre-allocate memory? Or as > >> >it goes? If the latter, in what size chunks? This starts to get at what > >> >Simon was talking about with respect to memory fragmentation. Which to > >> >be clear is a problem we have today, we just let things overlap and hope > >> >something later catches an incorrect checksum. > >> > > >> > >> I don't want to replace the malloc library which handles large numbets of > >> allocations. > > > >I'm confused. The normal malloc library is not involved with current > >image loading, it's direct to memory (with some attempts at sanity > >checking by lmb). Are you proposing a different allocator with > >malloc/free like behavior? If so, please outline how it will determine > >pool size, and how we'll use it to load thing to memory. > > All memory below the stack needs to be managed. Malloc uses a small memory > area (a few MiB) above the stack. That's a rather huge change for how U-Boot works. > >> Closing the eyes when the user loads multiple files does not solve the > >> fragmentation problem. > > > >Yes. I'm only noting that today we just ignore the problem and sometimes > >catch it via checksums. > > > >> Fragmentation only happens if we have many concurrent allocations. In EFI > >> we are allocating top down. The number of concurrent allocations is low. > >> Typically a few dozen at most. After terminating an application these > >> should be freed again. > > > >OK, so are you saying that we would no longer be loading _to_ a location > >in memory and instead just be saying "load this thing" and picking where > >dynamically? > > Both preassigned and allocator assigned adresses are compatible with memory > management. > > Architectures and binaries have different requirements. On riscv64 you can > load Linux kernel, initrd, fdt anywhere. We don't need predefined addresses > there. Other architectures have restrictions. Yes, 64 bit architecture tend to only have alignment requ
Re: Adding EFI runtime support to the Arm's FF-A bus
Hi Mark, > Any runtime device drivers for variable storage should not be in the > U-Boot runtime but live in the secure world (e.g. OP-TEE) FF-A is the > new ARM protocol for talking to the secure world and hence fits into > the picture. What if I just want a simple embedded boot stack where I don't want any secure world and just want to be able to boot a COTS linux distribution via EFI? That already works for many Linux distros. As long as the distro installs the appropriate BOOTxxx.EFI file you don't actually need to set any EFI variables for the OS to boot. It can't get any simpler than that. Of the main Linux distros it seems that only Debian doesn't do this. Someone should probably lobby Debian to do this as well as it would mean that Debian would just work on an EBBR compliant system. I know. Last time I checked CentOS (or was it Ubuntu?) tried to set EFI variables and the installer just failed. Might be fixed now, though. Things get more complicated if you want to install multiple OSes. Then having EFI variable support makes things a lot more straightforward. And of course EFI secure boot needs EFI variable support as well (with proper support) for authenticated EFI variables. But IMHO that no longer falls into "simple embedded boot stack" territory. Thats clear. Assuming, that there might be a simple dedicated EEPROM to store the variables which is not exposed to linux, is that something which would be rejected by u-boot mainline now? Not necessarily. But such an approach will have limitations: * Completely hiding the EEPROM from the OS may be hard. Even if you have a dedicated SPI controller for the EEPROM things like the SPI bus clock or power domains may still be under OS control. Fair point, but I was thinking about the ls1028a for example, where - if I remember correctly - there was one dedicated i2c controller in a sense of isolation, probably to use with a secure OS. Also there is no dynamic clocking. So, technically it should be possible, even with a low overhead, like no device model etc, which could reside in the efi os services. Just testing the waters here, not that I'm interested in adding support for that in u-boot. Just a bit concerned that it (EFI variables) will only work with a full stack (tf-a, optee) in the future. * It is not possible to properly implement authenticated variables for secure boot if the EEPROM and associated hardware is just removed from the device tree but still accessable to the OS. An implementation that pretends the variables are "secure" will probably be rejected. Sure. I excluded any secure stuff. But, with that i2c controller i was talking about earlier, it should be possible to mark it as EL3 access only. Thanks, -michael
Re: [PATCH V3] ARM add initial support for the Phytium Pe2201 Board.
On Tue, Dec 19, 2023 at 10:27:27AM +0800, tracymg...@outlook.com wrote: > From: TracyMg_Li > > Add pe2201 platform code and the device tree of pe2201 platform board. > The initial support comprises the UART and PCIe. > > Signed-off-by: TracyMg_Li > Changes since v1: > fix space corrupt. > Changes since v2: > switch to bootstd and text environment. Changes go below "---". And: [snip] > diff --git a/board/phytium/pe2201/pe2201.env b/board/phytium/pe2201/pe2201.env > new file mode 100644 > index 00..46f68ede2f > --- /dev/null > +++ b/board/phytium/pe2201/pe2201.env > @@ -0,0 +1,12 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2023, Phytium Technology Co., Ltd. > + */ > + > +/* Initial environment variables */ > +image=Image > +scriptaddr=0x9010 > +kernel_addr_r=0x9020 > +fdt_addr_r=0x9500 > +boot_fit=no > +fdtfile=phytium-pe2201.dtb Please see doc/develop/bootstd.rst as there's environment variables you should be setting and.. [snip] > +/* BOOT */ > +#define BOOT_TARGET_DEVICES(func)\ > + func(SCSI, scsi, 0) \ > + > +#include This can be removed. -- Tom signature.asc Description: PGP signature
[PATCH v2] arm: spl: Use separate fault handlers instead of a single common one
It may be necessary to set breakpoints etc. on a specific fault handler in SPL. Add a Kconfig option to separate the different handlers into their own individual infinite loops. Signed-off-by: Csókás Bence --- Notes: Changes in v2: * Change `depends`: add `&& !ARM64 && !CPU_V7M` * Remove `default n` arch/arm/Kconfig | 9 + arch/arm/lib/vectors.S | 18 ++ 2 files changed, 27 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 328e2ddc33..a6ddbad30c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -79,6 +79,15 @@ config SPL_SYS_NO_VECTOR_TABLE depends on SPL bool +config SPL_USE_SEPARATE_FAULT_HANDLERS + bool "Use separate fault handlers instead of a single common one" + depends on !SPL_SYS_NO_VECTOR_TABLE && !ARM64 && !CPU_V7M + help + Instead of a common fault handler, generate a separate one for + undefined_instruction, software_interrupt, prefetch_abort etc. + This is for debugging purposes, when you want to set breakpoints + on them separately. + config LINUX_KERNEL_IMAGE_HEADER depends on ARM64 bool diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 7cf7d1636f..a14bca6fb8 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -138,11 +138,29 @@ _fiq: .word fiq #if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE) .align 5 undefined_instruction: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b undefined_instruction +#endif software_interrupt: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b software_interrupt +#endif prefetch_abort: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b prefetch_abort +#endif data_abort: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b data_abort +#endif not_used: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b not_used +#endif irq: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b irq +#endif fiq: 1: b 1b /* hang and never return */ -- 2.25.1
Re: [PATCH v3 8/9] configs: qemu: add config fragment for ACPI
Hi Heinrich, On Tue, Dec 19, 2023 at 8:25 PM Heinrich Schuchardt wrote: > > Provide a configuration fragment to enable ACPI on QEMU. > > Signed-off-by: Heinrich Schuchardt > Acked-by: Ilias Apalodimas > Reviewed-by: Simon Glass > --- > v3: > no change > v2: > no change > --- > MAINTAINERS | 1 + > board/emulation/configs/acpi.config | 3 +++ > doc/board/emulation/acpi.rst| 23 +++ > doc/board/emulation/index.rst | 1 + > 4 files changed, 28 insertions(+) > create mode 100644 board/emulation/configs/acpi.config > create mode 100644 doc/board/emulation/acpi.rst > > diff --git a/MAINTAINERS b/MAINTAINERS > index 25f2bb80de..bf437b253b 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -53,6 +53,7 @@ Maintainers List (try to look for most precise areas first) > ACPI: > M: Simon Glass > S: Maintained > +F: board/emulation/configs/acpi.config > F: cmd/acpi.c > F: lib/acpi/ > > diff --git a/board/emulation/configs/acpi.config > b/board/emulation/configs/acpi.config > new file mode 100644 > index 00..b7ed811e33 > --- /dev/null > +++ b/board/emulation/configs/acpi.config > @@ -0,0 +1,3 @@ > +CONFIG_CMD_QFW=y > +CONFIG_ACPI=y > +CONFIG_GENERATE_ACPI_TABLE=y > diff --git a/doc/board/emulation/acpi.rst b/doc/board/emulation/acpi.rst > new file mode 100644 > index 00..e1208ca51e > --- /dev/null > +++ b/doc/board/emulation/acpi.rst > @@ -0,0 +1,23 @@ > +.. SPDX-License-Identifier: GPL-2.0+ > + > +ACPI on QEMU > + > + > +QEMU can provide ACPI tables on ARM, RISC-V, and x86. ACPI support on RISC-V landed on QEMU in a pretty recent version. Would you mind documenting its version? I haven't checked QEMU yet. Is ACPI default on in QEMU for Arm and RISC-V virt? If not, we should document QEMU commands to enable ACPI. > + > +The following settings are needed:: > + > +CONFIG_CMD_QFW=y > +CONFIG_ACPI=y > +CONFIG_GENERATE_ACPI_TABLE=y > + > +On x86 these settings are already included in the defconfig files. ARM and > +RISC-V default to use device-trees. > + > +Instead of updating the configuration manually you can add the configuration > +fragment `acpi.config` to the make command for initializing the > configuration. > +E.g. > + > +.. code-block:: bash > + > +make qemu-riscv64_smode_defconfig acpi.config > diff --git a/doc/board/emulation/index.rst b/doc/board/emulation/index.rst > index 932c65adeb..d3d6b8f3d8 100644 > --- a/doc/board/emulation/index.rst > +++ b/doc/board/emulation/index.rst > @@ -6,6 +6,7 @@ Emulation > .. toctree:: > :maxdepth: 1 > > + acpi > blkdev > ../../usage/semihosting > qemu-arm > -- Regards, Bin
Re: [PATCH] lib: rsa: Print detailed error info in rsa_engine_init() on engine resolution failure
On Tue, Dec 19, 2023 at 02:38:59PM +0100, Csókás Bence wrote: > Thank you. Just one question: When can we expect it to be applied? General rule is at least 2 weeks. This will get pulled in for v2024.04. > > 2023. 12. 14. 18:54 keltezéssel, Tom Rini írta: > > On Thu, Dec 14, 2023 at 05:54:17PM +0100, Csókás Bence wrote: > > > > > Signed-off-by: Csókás Bence > > > > Reviewed-by: Tom Rini > > > > Bence > -- Tom signature.asc Description: PGP signature
Re: [PATCH] lib: rsa: Print detailed error info in rsa_engine_init() on engine resolution failure
Thank you. Just one question: When can we expect it to be applied? 2023. 12. 14. 18:54 keltezéssel, Tom Rini írta: On Thu, Dec 14, 2023 at 05:54:17PM +0100, Csókás Bence wrote: Signed-off-by: Csókás Bence Reviewed-by: Tom Rini Bence
Re: [PATCH v3 4/9] risc-v: add ACPI fields to global data
On Tue, Dec 19, 2023 at 8:24 PM Heinrich Schuchardt wrote: > > Add fields for the location of ACPI tables to the global data. nits: I believe the tag should be 'riscv' instead of 'risc-v'. > > Signed-off-by: Heinrich Schuchardt > Reviewed-by: Simon Glass > --- > v3: > let tables in global data depend on CONFIG_(SPL_)ACPI > v2: > no change > --- > arch/riscv/include/asm/global_data.h | 6 ++ > 1 file changed, 6 insertions(+) > Otherwise, Reviewed-by: Bin Meng
[PATCH] ti: am335x: Remove unused linker script
The board specific linker script has not been used in a long time here,
remove it.
Signed-off-by: Tom Rini
---
board/ti/am335x/u-boot.lds | 164 -
1 file changed, 164 deletions(-)
delete mode 100644 board/ti/am335x/u-boot.lds
diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds
deleted file mode 100644
index 087dee8bb2ed..
--- a/board/ti/am335x/u-boot.lds
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering,
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x;
-
- . = ALIGN(4);
- .text :
- {
- *(.__image_copy_start)
- *(.vectors)
- CPUDIR/start.o (.text*)
- board/ti/am335x/built-in.o (.text*)
- }
-
- /* This needs to come before *(.text*) */
- .__efi_runtime_start : {
- *(.__efi_runtime_start)
- }
-
- .efi_runtime : {
- *(.text.efi_runtime*)
- *(.rodata.efi_runtime*)
- *(.data.efi_runtime*)
- }
-
- .__efi_runtime_stop : {
- *(.__efi_runtime_stop)
- }
-
- .text_rest :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- . = .;
-
- . = ALIGN(4);
- __u_boot_list : {
- KEEP(*(SORT(__u_boot_list*)));
- }
-
- . = ALIGN(4);
-
- .efi_runtime_rel_start :
- {
- *(.__efi_runtime_rel_start)
- }
-
- .efi_runtime_rel : {
- *(.rel*.efi_runtime)
- *(.rel*.efi_runtime.*)
- }
-
- .efi_runtime_rel_stop :
- {
- *(.__efi_runtime_rel_stop)
- }
-
- . = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- .hash : { *(.hash*) }
-
- .end :
- {
- *(.__end)
- }
-
- _image_binary_end = .;
-
- /*
-* Deprecated: this MMU section is used by pxa at present but
-* should not be used by new boards/CPUs.
-*/
- . = ALIGN(4096);
- .mmutable : {
- *(.mmutable)
- }
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
-. = ALIGN(4);
-__bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _image_binary_end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .gnu.hash : { *(.gnu.hash) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
--
2.34.1
