Re: [PATCH 1/1] lib: disable CONFIG_SPL_HEXDUMP by default
Am 2021-07-24 17:35, schrieb Heinrich Schuchardt: CONFIG_HEXDUMP is needed to display UEFI variables using 'printenv -e'. Enabling CONFIG_SPL_HEXDUMP only makes sense for debugging purposes. Hence CONFIG_SPL_HEXDUMP should not be enabled by default. The following boards currently have CONFIG_SPL_HEXDUMP=y: axm_defconfig imx8mm-cl-iot-gate_defconfig imx8mm_venice_defconfig imxrt1020-evk_defconfig imxrt1050-evk_defconfig kontron_sl28_defconfig kp_imx53_defconfig lx2160ardb_tfa_stmm_defconfig mt7622_rfb_defconfig octeon_ebb7304_defconfig octeon_nic23_defconfig qemu_arm64_defconfig qemu_arm_defconfig qemu-riscv32_defconfig qemu-riscv32_smode_defconfig qemu-riscv64_defconfig qemu-riscv64_smode_defconfig qemu-x86_64_defconfig qemu-x86_defconfig sandbox64_defconfig sandbox_defconfig stm32mp15_basic_defconfig stm32mp15_trusted_defconfig synquacer_developerbox_defconfig taurus_defconfig xilinx_versal_virt_defconfig The patch only keeps it enabled on sandbox64_defconfig sandbox_defconfig Signed-off-by: Heinrich Schuchardt Acked-by: Michael Walle # for kontron_sl28_defconfig
Re: Nokia RX51 U-Boot USB support updates?
Hi Tom, On 13/07/2021 22:33, Tom Rini wrote: > Hey all, > > So, the DM_USB migration deadline issue has been addressed by the series > here: > https://patchwork.ozlabs.org/project/uboot/list/?series=252793&state=* > which splits out host and gadget support from the CONFIG_USB symbol > itself. The migration deadline was for host support, and as noted, N900 > is gadget only. That particular issue is resolved. Thanks a lot for doing that! > But investigating that issue lead me to figure out some other problems, > that I do need someone to say how will be addressed. Now that the other > board removal series has been applied, and then with: > https://patchwork.ozlabs.org/project/uboot/patch/20210708014348.4010-1-tr...@konsulko.com/ > also applied (for which the maintainer is happy to take), this brings > N900 as the last and only user of the "old" musb driver (the "new" musb > driver is now almost 9 years old) and also the last and only user of the > usbtty driver. > > I suspect that moving to the "new" MUSB driver, for gadget only, and > with that enabling DM_USB_GADGET should be a mechanical affair, so long > as you can fit within the space constraints of the platform. I'm not > immediately sure how hard it will be to update usbtty.c to modern gadget > APIs. If there are size problems, then, well, we need solutions > proposed (it's possible that some of the usb-uclass.c code is host-only > and needs moving, but that likely won't stop gadget from needing it for > gadget related information, to bring up a specific example). > > It's also likely that the MUSB support needs a little further > clean-up for supporting building as gadget-only when there's some common > code under a host-only check. > > What I would like is for someone to step forward and say they'll pick up > this work. Is there an immediate deadline? No. I don't think that > would be helpful. I'm not going to dictate how long it takes for > someone to do the work, that's for the person doing the work to say how > long they think it'll take. I have a nokia serial device for the N900, which makes debugging significantly easier. I have some experience with u-boot (not that much with u-boot on omap though), but I imagine that Ivaylo and/or Pali can help me if I run into problems. So I'll try to pick this up. As for a time frame, I imagine I should be able to find some time for this in the next couple of months. Thanks, Merlijn
Re: [PATCH] sandbox: Reduce keyed autoboot delay
Hi Simon,
On 7/24/21 11:14 PM, Simon Glass wrote:
> The autoboot tests are a recent addition to U-Boot, providing much-needed
> coverage in this area.
>
> A side effect of the keyed autoboot test is that this feature is enabled
> in sandbox always. This changes the autoboot prompt and confuses the
> pytests. Some tests become slower, for example the vboot tests take about
> 27s now instead of 3s.
>
> We don't actually need this feature enabled to be able to run the tests.
> Add a switch to allow sandbox to turn it on and off as needed. Use this
> in the one test that needs it.
>
> Add a command-line flag in case this is desired in normal use.
>
> Signed-off-by: Simon Glass
> Fixes: 25c8b9f298e ("test: add first autoboot unit tests")
Reviewed-by: Steffen Jaeckel
Cheers
Steffen
Re: Nokia RX51 U-Boot USB support updates?
On Sun, Jul 25, 2021 at 12:40:13PM +0200, Merlijn Wajer wrote: > Hi Tom, > > On 13/07/2021 22:33, Tom Rini wrote: > > Hey all, > > > > So, the DM_USB migration deadline issue has been addressed by the series > > here: > > https://patchwork.ozlabs.org/project/uboot/list/?series=252793&state=* > > which splits out host and gadget support from the CONFIG_USB symbol > > itself. The migration deadline was for host support, and as noted, N900 > > is gadget only. That particular issue is resolved. > > Thanks a lot for doing that! > > > But investigating that issue lead me to figure out some other problems, > > that I do need someone to say how will be addressed. Now that the other > > board removal series has been applied, and then with: > > https://patchwork.ozlabs.org/project/uboot/patch/20210708014348.4010-1-tr...@konsulko.com/ > > also applied (for which the maintainer is happy to take), this brings > > N900 as the last and only user of the "old" musb driver (the "new" musb > > driver is now almost 9 years old) and also the last and only user of the > > usbtty driver. > > > > I suspect that moving to the "new" MUSB driver, for gadget only, and > > with that enabling DM_USB_GADGET should be a mechanical affair, so long > > as you can fit within the space constraints of the platform. I'm not > > immediately sure how hard it will be to update usbtty.c to modern gadget > > APIs. If there are size problems, then, well, we need solutions > > proposed (it's possible that some of the usb-uclass.c code is host-only > > and needs moving, but that likely won't stop gadget from needing it for > > gadget related information, to bring up a specific example). > > > > It's also likely that the MUSB support needs a little further > > clean-up for supporting building as gadget-only when there's some common > > code under a host-only check. > > > > What I would like is for someone to step forward and say they'll pick up > > this work. Is there an immediate deadline? No. I don't think that > > would be helpful. I'm not going to dictate how long it takes for > > someone to do the work, that's for the person doing the work to say how > > long they think it'll take. > > I have a nokia serial device for the N900, which makes debugging > significantly easier. I have some experience with u-boot (not that much > with u-boot on omap though), but I imagine that Ivaylo and/or Pali can > help me if I run into problems. So I'll try to pick this up. > > As for a time frame, I imagine I should be able to find some time for > this in the next couple of months. A couple of months sounds great, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v6 2/4] rockchip: rk3066: add clock driver for rk3066 soc
Hi Simon,
sorry for late response i was offline a bit
W dniu 13.07.2021 o 22:17, Simon Glass pisze:
> Hi Paweł,
>
> On Tue, 13 Jul 2021 at 12:59, Paweł Jarosz wrote:
>> Add clock driver for rk3066 platform.
>>
>> Signed-off-by: Paweł Jarosz
>> Acked-by: Philipp Tomsich
>> ---
>>
>> Changes since v1:
>> - updated to shifted masks
>> - moved clk init to tpl
>>
>> Changes since v2:
>> - none
>>
>> Changes since v3:
>> - none
>>
>> Changes since v4:
>> - updated to current codebase
>> - fixed compilation errors
>>
>> Changes since v5:
>> - various style changes
>> - added clk_enable/clk_disable support for nand and mmc clocks
>> - updated maintainer email
>> - renamed uint32_t to u32
>> - used #if IS_ENABLED macro instead #ifdef
>>
>>
>>
>> .../include/asm/arch-rockchip/cru_rk3066.h| 203 +
>> drivers/clk/rockchip/Makefile | 1 +
>> drivers/clk/rockchip/clk_rk3066.c | 704 ++
>> 3 files changed, 908 insertions(+)
>> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3066.h
>> create mode 100644 drivers/clk/rockchip/clk_rk3066.c
>>
> [..]
>
>> +
>> +static int rk3066_clk_of_to_plat(struct udevice *dev)
>> +{
>> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
>> + struct rk3066_clk_priv *priv = dev_get_priv(dev);
>> +
>> + priv->cru = dev_read_addr_ptr(dev);
>> +#endif
>> +
>> + return 0;
>> +}
>> +
>> +static int rk3066_clk_probe(struct udevice *dev)
>> +{
>> + struct rk3066_clk_priv *priv = dev_get_priv(dev);
>> +
>> + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
>> + if (IS_ERR(priv->grf))
>> + return PTR_ERR(priv->grf);
>> +
>> +#if IS_ENABLED(CONFIG_TPL_BUILD)
> Do you need that? The line below should take care of it.
Yep. Later rkclk_init and rkclk_configure_cpu should be only executed in TPL.
>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> + struct rk3066_clk_plat *plat = dev_get_plat(dev);
>> +
>> + priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
>> +#endif
>> +
>> + rkclk_init(priv->cru, priv->grf);
>> +
>> + /* Init CPU frequency */
>> + rkclk_configure_cpu(priv->cru, priv->grf, APLL_SAFE_HZ);
>> +#endif
>> +
>> + return 0;
>> +}
>> +
>> +static int rk3066_clk_bind(struct udevice *dev)
>> +{
>> + int ret;
>> + struct udevice *sys_child;
>> + struct sysreset_reg *priv;
>> +
>> + /* The reset driver does not have a device node, so bind it here */
>> + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
>> +&sys_child);
>> + if (ret) {
>> + debug("Warning: No sysreset driver: ret=%d\n", ret);
>> + } else {
>> + priv = malloc(sizeof(struct sysreset_reg));
>> + priv->glb_srst_fst_value = offsetof(struct rk3066_cru,
>> + cru_glb_srst_fst_value);
>> + priv->glb_srst_snd_value = offsetof(struct rk3066_cru,
>> + cru_glb_srst_snd_value);
>> + dev_set_priv(sys_child, priv);
>> + }
>> +
>> +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
> Can you use if() instead of #if ?
Yes, but what is the difference? Sorry ... I don't know what to ask google to
get the answer.
Is it in this case doing the same thing and just looking better?
Regards,
Paweł Jarosz
>> + ret = offsetof(struct rk3066_cru, cru_softrst_con[0]);
>> + ret = rockchip_reset_bind(dev, ret, 9);
>> + if (ret)
>> + debug("Warning: software reset driver bind failed\n");
>> +#endif
>> +
>> + return 0;
>> +}
>> +
>> +static const struct udevice_id rk3066_clk_ids[] = {
>> + { .compatible = "rockchip,rk3066a-cru" },
>> + { }
>> +};
>> +
>> +U_BOOT_DRIVER(rockchip_rk3066a_cru) = {
>> + .name = "rockchip_rk3066a_cru",
>> + .id = UCLASS_CLK,
>> + .of_match = rk3066_clk_ids,
>> + .priv_auto = sizeof(struct rk3066_clk_priv),
>> + .plat_auto = sizeof(struct rk3066_clk_plat),
>> + .ops= &rk3066_clk_ops,
>> + .bind = rk3066_clk_bind,
>> + .of_to_plat = rk3066_clk_of_to_plat,
>> + .probe = rk3066_clk_probe,
>> +};
>> --
>> 2.32.0
>>
> Regards,
> Simon
Re: [PATCH v5 0/5] stm32mp: Enable OP-TEE and TZC support in SPL
On 7/15/21 2:19 PM, Alexandru Gagniuc wrote: v4 branch was reported to have some issues with SPL becoming too big on some platforms (e.g. imx6dl_mamoj) This is fixed by dropping the call to genimg_get_os_name(). Ping for merge window. Alexandru Gagniuc (5): spl: mmc: Support OP-TEE payloads in Falcon mode spl: Introduce spl_board_prepare_for_optee() hook arm: stm32mp: Implement support for TZC 400 controller stm32mp1: spl: Configure TrustZone controller for OP-TEE ARM: dts: stm32mp: Add OP-TEE reserved memory to SPL dtb arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 3 + arch/arm/mach-stm32mp/Makefile | 1 + arch/arm/mach-stm32mp/include/mach/tzc.h | 33 ++ arch/arm/mach-stm32mp/spl.c | 92 +++ arch/arm/mach-stm32mp/tzc400.c | 136 +++ common/spl/spl.c | 5 + common/spl/spl_mmc.c | 4 +- include/spl.h| 14 +++ 8 files changed, 286 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-stm32mp/include/mach/tzc.h create mode 100644 arch/arm/mach-stm32mp/tzc400.c
[PATCH v6 0/5] of-platdata: Avoid building libfdt
The original patch of this series was sent in September 2019 but unfortunately caused build problems on some boards, since they don't comply with the of-platdata rules. With of-platdata, the idea is to compile the device tree into C structures to save space and avoid needing to use libfdt. But some boards use of-platdata while also using libfdt in a few areas, thus defeating the purpose of of-platdata. This series includes the original two patches http://patchwork.ozlabs.org/patch/1167420/ http://patchwork.ozlabs.org/patch/1167367/ as well as a few other patches to fix the build errors. Overall this reduces code size and provides better error messages when unavailable functions are used. Board maintainers should still take a look at the result, adjusting the of-platdata support as needed. Note: This series was resent a year ago but not applied. Since then, some boards have ended up using drivers in SPL which require OF_CONTROL, but SPL_OF_CONTROL is not enabled. So now we have two problems. This series fixes that one also. The problems will keep getting worse if people are not aware that something is wrong. Therefore I think this patch series should be applied ASAP. Changes in v6: - Add new patch for atheros - Add new patch for SPI flash - Rebase to master Changes in v5: - Drop rockchip patches as those boards have been fixed Changes in v4: - Add new patch for rockchip build errors - Add new patch for omap MMC build errors - Add new patch for rockchip chromebook build errors - Pull out patches into a new series - Add new patches to handle build failures Changes in v3: - Fix eth_dev_get_mac_address() call dev_read...() only when available Simon Glass (5): omap: mmc: Avoid using libfdt with of-platdata net: atheros: Add a check for OF_CONTROL spi: Add checks for OF_CONTROL spl: Allow SPL/TPL to use of-platdata without libfdt dm: core: Don't include ofnode functions with of-platdata drivers/core/Makefile | 4 +++- drivers/mmc/davinci_mmc.c | 6 ++ drivers/net/phy/atheros.c | 11 +++ drivers/spi/spi-uclass.c | 16 +--- lib/Kconfig | 4 ++-- 5 files changed, 35 insertions(+), 6 deletions(-) -- 2.32.0.432.gabb21c7263-goog
[PATCH v6 1/5] omap: mmc: Avoid using libfdt with of-platdata
At present this driver is enabled in SPL on omapl138_lcdk, which uses
of-platdata. The driver needs to be ported to use of-platdata properly.
For now, avoid a build error by returning an error.
Signed-off-by: Simon Glass
---
(no changes since v1)
drivers/mmc/davinci_mmc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c
index 05ca3612809..7016649524f 100644
--- a/drivers/mmc/davinci_mmc.c
+++ b/drivers/mmc/davinci_mmc.c
@@ -506,6 +506,12 @@ static int davinci_mmc_of_to_plat(struct udevice *dev)
struct davinci_mmc_plat *plat = dev_get_plat(dev);
struct mmc_config *cfg = &plat->cfg;
+ /* FIXME: Cannot read from device tree with of-platdata */
+ if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
+ printf("Please fix this driver to use of-platdata");
+ return -ENOSYS;
+ }
+
plat->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
cfg->f_min = 20;
cfg->f_max = 2500;
--
2.32.0.432.gabb21c7263-goog
[PATCH v6 3/5] spi: Add checks for OF_CONTROL
This uclass requires OF_CONTROL to be enabled but some boards use it in
SPL without doing that. Add a warning so that the maintainer can fix it.
Expand the check in spi_post_probe() too.
Signed-off-by: Simon Glass
---
Changes in v6:
- Add new patch for SPI flash
drivers/spi/spi-uclass.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index d867b278064..2ae3e075993 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -176,11 +176,11 @@ static int spi_child_post_bind(struct udevice *dev)
static int spi_post_probe(struct udevice *bus)
{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
- spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
-#endif
+ if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA))
+ spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
+
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
struct dm_spi_ops *ops = spi_get_ops(bus);
static int reloc_done;
@@ -471,6 +471,16 @@ int spi_slave_of_to_plat(struct udevice *dev, struct
dm_spi_slave_plat *plat)
int mode = 0;
int value;
+ /*
+* This uclass requires OF_CONTROL but this is included on some boards
+* that don't support it in SPL. Return an error so the board vendor
+* can resolve this.
+*/
+ if (!CONFIG_IS_ENABLED(OF_CONTROL)) {
+ log_err("SPI flash requires OF_CONTROL enabled");
+ return -ENOSYS;
+ }
+
plat->cs = dev_read_u32_default(dev, "reg", -1);
plat->max_hz = dev_read_u32_default(dev, "spi-max-frequency",
SPI_DEFAULT_SPEED_HZ);
--
2.32.0.432.gabb21c7263-goog
[PATCH v6 2/5] net: atheros: Add a check for OF_CONTROL
This phy cannot be used when OF_CONTROL is not enabled. A few boards
expect it to build, though, so add a runtime check for this case.
Signed-off-by: Simon Glass
---
Changes in v6:
- Add new patch for atheros
drivers/net/phy/atheros.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index f922fecd6b5..cc772f3060f 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -7,6 +7,7 @@
* Copyright (c) 2019 Michael Walle
*/
#include
+#include
#include
#include
#include
@@ -197,6 +198,16 @@ static int ar803x_of_init(struct phy_device *phydev)
u32 strength, freq, min_uV, max_uV;
int sel;
+ /*
+* This driver requires OF_CONTROL but this is included on some boards
+* that don't support it in SPL. Return an error so the board vendor
+* can resolve this.
+*/
+ if (!CONFIG_IS_ENABLED(OF_CONTROL)) {
+ log_err("atheros driver requires OF_CONTROL enabled");
+ return -ENOSYS;
+ }
+
node = phy_get_ofnode(phydev);
if (!ofnode_valid(node))
return -EINVAL;
--
2.32.0.432.gabb21c7263-goog
[PATCH v6 4/5] spl: Allow SPL/TPL to use of-platdata without libfdt
At present libfdt is included in SPL/TPL if SPL/TPL_OF_CONTROL is enabled. But if of-platdata is in use this is not required. Update the condition to avoid building this extra code. This ensures that if a libfdt function is used it will produce a link error rather than silently increasing the build size. Signed-off-by: Simon Glass --- Changes in v6: - Rebase to master Changes in v5: - Drop rockchip patches as those boards have been fixed Changes in v4: - Add new patch for rockchip build errors - Add new patch for omap MMC build errors - Add new patch for rockchip chromebook build errors - Pull out patches into a new series - Add new patches to handle build failures lib/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Kconfig b/lib/Kconfig index ad4d75e0a40..ef1235bf0c8 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -599,7 +599,7 @@ config OF_LIBFDT_OVERLAY config SPL_OF_LIBFDT bool "Enable the FDT library for SPL" - default y if SPL_OF_CONTROL + default y if SPL_OF_CONTROL && !SPL_OF_PLATDATA help This enables the FDT library (libfdt). It provides functions for accessing binary device tree images in memory, such as adding and @@ -620,7 +620,7 @@ config SPL_OF_LIBFDT_ASSUME_MASK config TPL_OF_LIBFDT bool "Enable the FDT library for TPL" - default y if TPL_OF_CONTROL + default y if TPL_OF_CONTROL && !TPL_OF_PLATDATA help This enables the FDT library (libfdt). It provides functions for accessing binary device tree images in memory, such as adding and -- 2.32.0.432.gabb21c7263-goog
[PATCH v6 5/5] dm: core: Don't include ofnode functions with of-platdata
These functions cannot work with of-platdata since libfdt is not available. At present when dev_read_...() functions are used it produces error messages about ofnode which is confusing. Adjust the Makefile and header to produce an error message for the actual dev_read...() function which is called. This makes it easier to see what code needs to be converted for use with of-platdata. Signed-off-by: Simon Glass --- (no changes since v3) Changes in v3: - Fix eth_dev_get_mac_address() call dev_read...() only when available drivers/core/Makefile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/core/Makefile b/drivers/core/Makefile index 5edd4e41357..725e6e94cd2 100644 --- a/drivers/core/Makefile +++ b/drivers/core/Makefile @@ -15,6 +15,8 @@ obj-$(CONFIG_$(SPL_)OF_LIVE) += of_access.o of_addr.o ifndef CONFIG_DM_DEV_READ_INLINE obj-$(CONFIG_OF_CONTROL) += read.o endif -obj-$(CONFIG_OF_CONTROL) += of_extra.o ofnode.o read_extra.o +ifdef CONFIG_$(SPL_TPL_)OF_LIBFDT +obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += of_extra.o ofnode.o read_extra.o +endif ccflags-$(CONFIG_DM_DEBUG) += -DDEBUG -- 2.32.0.432.gabb21c7263-goog
[PATCH 1/3] doc: Move devicetree control doc to rST
Move this to rST format, largely unchanged to start with. Add an index
for this topic, as well as an empty intro.
Signed-off-by: Simon Glass
---
.../devicetree/control.rst} | 50 +--
doc/develop/devicetree/index.rst | 13 +
doc/develop/devicetree/intro.rst | 4 ++
doc/develop/index.rst | 1 +
4 files changed, 43 insertions(+), 25 deletions(-)
rename doc/{README.fdt-control => develop/devicetree/control.rst} (89%)
create mode 100644 doc/develop/devicetree/index.rst
create mode 100644 doc/develop/devicetree/intro.rst
diff --git a/doc/README.fdt-control b/doc/develop/devicetree/control.rst
similarity index 89%
rename from doc/README.fdt-control
rename to doc/develop/devicetree/control.rst
index 424d13fc5b1..1289b6156fe 100644
--- a/doc/README.fdt-control
+++ b/doc/develop/devicetree/control.rst
@@ -1,6 +1,5 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2011 The Chromium OS Authors.
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Copyright 2011 The Chromium OS Authors
Device Tree Control in U-Boot
=
@@ -37,9 +36,7 @@ What is a Flat Device Tree?
---
An fdt can be specified in source format as a text file. To read about
-the fdt syntax, take a look at the specification here:
-
-https://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf
+the fdt syntax, take a look at the specification (dtspec_).
You also might find this section of the Linux kernel documentation
useful: (access this in the Linux kernel source code)
@@ -60,18 +57,18 @@ To use this feature you will need to get the device tree
compiler. This is
provided by U-Boot automatically. If you have a system version of dtc
(typically in the 'device-tree-compiler' package), it is currently not used.
-If you want to build your own dtc, it is kept here:
+If you want to build your own dtc, it is kept here::
git://git.kernel.org/pub/scm/utils/dtc/dtc.git
-For example:
+For example::
$ git clone git://git.kernel.org/pub/scm/utils/dtc/dtc.git
$ cd dtc
$ make
$ sudo make install
-Then run the compiler (your version will vary):
+Then run the compiler (your version will vary)::
$ dtc -v
Version: DTC 1.2.0-g2cb4b51f
@@ -105,14 +102,14 @@ Failing that, you could write one from scratch yourself!
Configuration
-
-Use:
+Use::
-#define CONFIG_DEFAULT_DEVICE_TREE ""
+ #define CONFIG_DEFAULT_DEVICE_TREE ""
to set the filename of the device tree source. Then put your device tree
-file into
+file into::
- board//dts/.dts
+ board//dts/.dts
This should include your CPU or SOC's device tree file, placed in
arch//dts, and then make any adjustments required.
@@ -123,9 +120,9 @@ and development only and is not recommended for production
devices.
If CONFIG_OF_SEPARATE is defined, then it will be built and placed in
a u-boot.dtb file alongside u-boot-nodtb.bin. A common approach is then to
-join the two:
+join the two::
- cat u-boot-nodtb.bin u-boot.dtb >image.bin
+ cat u-boot-nodtb.bin u-boot.dtb >image.bin
and then flash image.bin onto your board. Note that U-Boot creates
u-boot-dtb.bin which does the above step for you also. Resulting
@@ -144,9 +141,9 @@ specify the file to read.
You cannot use more than one of these options at the same time.
To use a device tree file that you have compiled yourself, pass
-EXT_DTB= to 'make', as in:
+EXT_DTB= to 'make', as in::
- make EXT_DTB=boot/am335x-boneblack-pubkey.dtb
+ make EXT_DTB=boot/am335x-boneblack-pubkey.dtb
Then U-Boot will copy that file to u-boot.dtb, put it in the .img file
if used, and u-boot-dtb.bin.
@@ -162,16 +159,21 @@ variable will be set to the address of the newly
relocated fdt blob.
It is read-only and cannot be changed. It can optionally be used to
control the boot process of Linux with bootm/bootz commands.
-To use this, put something like this in your board header file:
+To use this, put something like this in your board header file::
-#define CONFIG_EXTRA_ENV_SETTINGS "fdtcontroladdr=1\0"
+ #define CONFIG_EXTRA_ENV_SETTINGS "fdtcontroladdr=1\0"
Build:
-After board configuration is done, fdt supported u-boot can be build in two
ways:
-1) build the default dts which is defined from CONFIG_DEFAULT_DEVICE_TREE
+After board configuration is done, fdt supported u-boot can be build in two
+ways:
+
+# build the default dts which is defined from CONFIG_DEFAULT_DEVICE_TREE::
+
$ make
-2) build the user specified dts file
+
+# build the user specified dts file::
+
$ make DEVICE_TREE=
@@ -225,6 +227,4 @@ but can use the fdt to specific the UART clock, peripheral
address, etc.
In very broad terms, the CONFIG options in general control *what* driver
files are pulled in, and the fdt controls *how* those files work.
---
-Simon Glass
-1-Sep-
[PATCH 3/3] doc: Add a note about why devicetree is used
This question comes up every now and then with people coming from Linux. Add some notes about it so we can point to it in the mailing list. Signed-off-by: Simon Glass --- doc/develop/devicetree/control.rst | 2 ++ doc/develop/devicetree/intro.rst | 39 ++ 2 files changed, 41 insertions(+) diff --git a/doc/develop/devicetree/control.rst b/doc/develop/devicetree/control.rst index ac5f7989cc6..f98faee20d1 100644 --- a/doc/develop/devicetree/control.rst +++ b/doc/develop/devicetree/control.rst @@ -174,6 +174,8 @@ ways: $ make DEVICE_TREE= +.. _dttweaks: + Adding tweaks for U-Boot diff --git a/doc/develop/devicetree/intro.rst b/doc/develop/devicetree/intro.rst index 344851327c7..e03d8e1ae66 100644 --- a/doc/develop/devicetree/intro.rst +++ b/doc/develop/devicetree/intro.rst @@ -2,3 +2,42 @@ Devicetree Introduction === + +U-Boot uses devicetree for configuration. This includes the devices used by +the board, the format of the image created with binman, which UART to use for +the console, public keys used for secure boot and many other things. + +See :doc:`control` for more information. + +Why does U-Boot put in the devicetree? +-- + +This question comes up a lot with people new to U-Boot, particular those coming +from Linux who are used to quite strict rules about what can go in the +devicetree. + +U-Boot uses the same devicetree as Linux but adds more things necessary for the +bootloader environment (see :ref:`dttweaks`). + +U-Boot does not have a user space to provide policy and configuration. It cannot +do what Linux does and run programs and look up filesystems to figure out how to +boot. So configuration / runtime info go in the devicetree in U-Boot. + +Of course it is possible to: + +- add tables into the rodata +- append some info to the end of U-Boot in a different format +- modify the link script to bring in a file with some info in it +- put things in ACPI tables +- compile in a UEFI hand-off block structure and put things in there + +but *please don't*. In general, devicetree is the sane place to hold U-Boot's +configuration. + +So please...do NOT ask why U-Boot puts in the devicetree. It is the only +place it can go. It is a highly suitable data structure for just about anything +that U-Boot needs to know at runtime. + +Note, it is possible to use platdata directly so drivers avoid devicetreee in +SPL. But of-platdata is the modern way of avoiding devicetree overhead, so +please use that instead. -- 2.32.0.432.gabb21c7263-goog
[PATCH 2/3] doc: Update devicedocs including how to add tweaks
This file is about 10 years old and the updates have not covered everything that has changed, particularly in the last few years. Update the information and add mention of the u-boot.dtsi files. Signed-off-by: Simon Glass --- doc/develop/devicetree/control.rst | 107 - 1 file changed, 74 insertions(+), 33 deletions(-) diff --git a/doc/develop/devicetree/control.rst b/doc/develop/devicetree/control.rst index 1289b6156fe..ac5f7989cc6 100644 --- a/doc/develop/devicetree/control.rst +++ b/doc/develop/devicetree/control.rst @@ -1,26 +1,27 @@ .. SPDX-License-Identifier: GPL-2.0+ .. sectionauthor:: Copyright 2011 The Chromium OS Authors -Device Tree Control in U-Boot -= +Devicetree Control in U-Boot + This feature provides for run-time configuration of U-Boot via a flat -device tree (fdt). U-Boot configuration has traditionally been done -using CONFIG options in the board config file. This feature aims to -make it possible for a single U-Boot binary to support multiple boards, -with the exact configuration of each board controlled by a flat device -tree (fdt). This is the approach recently taken by the ARM Linux kernel -and has been used by PowerPC for some time. +device tree (fdt). + +This feature aims to make it possible for a single U-Boot binary to support +multiple boards, with the exact configuration of each board controlled by +a flat device tree (fdt). This is the approach recently taken by Linux (e.g. +for PowerPC and ARM). The fdt is a convenient vehicle for implementing run-time configuration -for three reasons. Firstly it is easy to use, being a simple text file. -It is extensible since it consists of nodes and properties in a nice -hierarchical format. +for three reasons: -Finally, there is already excellent infrastructure for the fdt: a -compiler checks the text file and converts it to a compact binary -format, and a library is already available in U-Boot (libfdt) for -handling this format. +- Firstly it is easy to use, being a simple text file +- It is extensible since it consists of nodes and properties in a nice + hierarchical format +- There is already excellent infrastructure for the fdt: a compiler checks + the text file and converts it to a compact binary format, and a library + is already available in U-Boot (libfdt) for handling this format\ +- It is fairly efficient to read incrementally The dts directory contains a Makefile for building the device tree blob and embedding it in your U-Boot image. This is useful since it allows @@ -38,14 +39,8 @@ What is a Flat Device Tree? An fdt can be specified in source format as a text file. To read about the fdt syntax, take a look at the specification (dtspec_). -You also might find this section of the Linux kernel documentation -useful: (access this in the Linux kernel source code) - - Documentation/devicetree/booting-without-of.txt - -There is also a mailing list: - - http://lists.ozlabs.org/listinfo/devicetree-discuss +There is also a mailing list (dtlist_) for the compiler and associated +tools. In case you are wondering, OF stands for Open Firmware. @@ -82,8 +77,9 @@ Then run the compiler (your version will vary):: * Bad configuration: 0 * Strange test result: 0 -You will also find a useful fdtdump utility for decoding a binary file, as -well as fdtget/fdtput for reading and writing properties in a binary file. +You will also find a useful `fdtdump` utility for decoding a binary file, as +well as `fdtget`/`fdtput` for reading and writing properties in a binary file. +U-Boot adds its own `fdtgrep` for creating subsets of the file. Where do I get an fdt file for my board? @@ -109,10 +105,11 @@ Use:: to set the filename of the device tree source. Then put your device tree file into:: - board//dts/.dts + arch//dts/.dts This should include your CPU or SOC's device tree file, placed in -arch//dts, and then make any adjustments required. +`arch//dts`, and then make any adjustments required using a u-boot-dtsi +file for your board. If CONFIG_OF_EMBED is defined, then it will be picked up and built into the U-Boot image (including u-boot.bin). This is suitable for debugging @@ -122,11 +119,10 @@ If CONFIG_OF_SEPARATE is defined, then it will be built and placed in a u-boot.dtb file alongside u-boot-nodtb.bin. A common approach is then to join the two:: - cat u-boot-nodtb.bin u-boot.dtb >image.bin + cat u-boot-nodtb.bin u-boot.dtb >u-boot.bin and then flash image.bin onto your board. Note that U-Boot creates -u-boot-dtb.bin which does the above step for you also. Resulting -u-boot.bin is a copy of u-boot-dtb.bin in this case. If you are using +u-boot.bin so does the above step for you automatically. If you are using CONFIG_SPL_FRAMEWORK, then u-boot.img will be built to include the device tree binary. @@ -136,7 +132,8 @@ it and passes it to U-Boot. If CONFIG_OF_HOSTFI
[PATCH v2 1/3] imx8: Drop raw image support
The CONFIG_SPL_RAW_IMAGE_SUPPORT option requires that binman provides an offset for the image (see spl_set_header_raw_uboot()), if binman is used. These boards use FIT to store U-Boot, so raw image support is not used. Drop this option to avoid errors once binman starts checking this. Signed-off-by: Simon Glass --- Changes in v2: - Add a new patch to drop raw image support for some imx8 boards configs/imx8mm-cl-iot-gate_defconfig | 1 + configs/imx8mm_evk_defconfig | 1 + configs/imx8mn_ddr4_evk_defconfig| 1 + configs/imx8mp_evk_defconfig | 1 + configs/imx8mq_cm_defconfig | 1 + configs/kontron_sl28_defconfig | 1 + configs/phycore-imx8mp_defconfig | 1 + 7 files changed, 7 insertions(+) diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index f46f45bda91..a1ded18f7e8 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -30,6 +30,7 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index a06c6f9794a..9dc0be6b09e 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -27,6 +27,7 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 205757da229..a96f729bde9 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -30,6 +30,7 @@ CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index d0f390ed776..df4463ca2b6 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -31,6 +31,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C_SUPPORT=y diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig index e11122e645f..72d9ec8b258 100644 --- a/configs/imx8mq_cm_defconfig +++ b/configs/imx8mq_cm_defconfig @@ -25,6 +25,7 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ronetix/imx8mq-cm/imximage-8mq-lpddr4.cfg" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SYS_PROMPT="u-boot=> " diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 29a45ec54bc..3868d7c39b0 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -31,6 +31,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOARD_LATE_INIT=y CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 32d538c8bbb..d63cba70108 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -27,6 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C_SUPPORT=y -- 2.32.0.432.gabb21c7263-goog
[PATCH v2 2/3] arm: Add an __image_copy_start symbol for ARMv8
This symbol is needed for binman to locate the start of the image. Add it.
Note: the existing line to bring in the .__image_copy_start symbol does
not appear to do anything.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add new patch to add an __image_copy_start symbol for ARMv8
arch/arm/cpu/armv8/u-boot-spl.lds | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds
b/arch/arm/cpu/armv8/u-boot-spl.lds
index 9edb662b094..2827a07590d 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -22,6 +22,7 @@ ENTRY(_start)
SECTIONS
{
.text : {
+ __image_copy_start = .;
. = ALIGN(8);
*(.__image_copy_start)
CPUDIR/start.o (.text*)
--
2.32.0.432.gabb21c7263-goog
[PATCH v2 3/3] binman: Show an error if __image_copy_start is missing
Binman needs this symbol to be able to figure out the start of the image.
Detect if it is missing and report an error if any symbols are needed.
Add more documentation about possible binman warnings.
Signed-off-by: Simon Glass
---
(no changes since v1)
tools/binman/binman.rst | 109 +++
tools/binman/elf.py | 6 ++-
tools/binman/elf_test.py | 7 ++-
3 files changed, 118 insertions(+), 4 deletions(-)
diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst
index 09e7b571982..81e0a1364ff 100644
--- a/tools/binman/binman.rst
+++ b/tools/binman/binman.rst
@@ -1158,6 +1158,115 @@ development, since dealing with exceptions and problems
in threads is more
difficult. This avoids any use of ThreadPoolExecutor.
+Dealing with warnings and errors
+
+
+__image_copy_start
+~~
+
+If you see::
+
+ Cannot process symbol 'xxx' since there is no __image_copy_start
+
+this means that your SPL image does not include an `__image_copy_start` symbol.
+You can check this with::
+
+ nm spl/u-boot-spl |grep __image_copy_start
+
+If there is no output them you don't have that symbol. It is normally created
+in a `u-boot-spl.lds` file, like this::
+
+ text :
+ {
+ __image_copy_start = .;
+ *(.vectors)
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ *(.glue*)
+ }
+
+Check the appropriate file for your board, typically in the `arch/xxx/cpu`
+or `arch/xxx/cpu/xxx` directory.
+
+Entry xx not found in list
+~~
+
+If you see something like::
+
+ output: 'binman: Section '/binman/u-boot-spl-ddr':
+ Symbol '_binman_u_boot_any_prop_image_pos'
+ in entry '/binman/u-boot-spl-ddr/u-boot-spl/u-boot-spl-nodtb':
+ Entry 'u-boot-any' not found in list (u-boot-spl-nodtb,u-boot-spl-dtb,
+ u-boot-spl,blob-ext@1,blob-ext@2,blob-ext@3,blob-ext@4,main-section)
+
+this means that binman knows it should set the value of a symbol called
+`_binman_u_boot_any_prop_image_pos` but does not know how. That symbol name is
+generated by the `binman_symname` macro (see `binman_sym.h`)::
+
+ #define binman_symname(_entry_name, _prop_name) \
+ _binman_ ## _entry_name ## _prop_ ## _prop_name
+
+so binman decodes it into:
+
+_binman_
+prefix for all symbols
+u_boot_any
+entry to find
+_prop_
+prefix for property
+image_pos
+image_pos property
+
+It therefore looks for u-boot-any, which means any U-Boot symbol. Supported
ones
+are:
+
+- u-boot
+- u-boot-img
+- u-boot-nodtb
+
+You can see a list of the symbols it tried, in brackets. None of these matches
+the above list. The source definition in this example is::
+
+&binman {
+u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob-ext-1 {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob-ext-2 {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ };
+
+ blob-ext-3 {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob-ext-4 {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ };
+ };
+
+and you can see that, while `u-boot-spl` is present, `u-boot` is not. Binman
+must find the required symbol somewhere in the same image.
+
+In this case the problem is that CONFIG_SPL_RAW_IMAGE_SUPPORT is enabled, even
+though U-Boot is actually stored in a FIT. This means that
+spl_set_header_raw_uboot() is called and it looks for a symbol for U-Boot.
+Disabling that option fixes the error.
+
History / Credits
-
diff --git a/tools/binman/elf.py b/tools/binman/elf.py
index 03b49d7163c..f14d07da157 100644
--- a/tools/binman/elf.py
+++ b/tools/binman/elf.py
@@ -112,12 +112,14 @@ def LookupAndWriteSymbols(elf_fname, entry, section):
if not syms:
return
base = syms.get('__image_copy_start')
-if not base:
-return
for name, sym in syms.items():
if name.startswith('_binman'):
msg = ("Section '%s': Symbol '%s'\n in entry '%s'" %
(section.GetPath(), name, entry.GetPath()))
+if not base:
+raise ValueError("Cannot process symbol '%s' since there is no
__image_copy_start" %
+ name)
+
offset = sym.address - base.address
if offset < 0 or offset + sym.size > entry.contents_size:
raise ValueError('%s has offset %x (size %x) but the contents '
diff --git a/tools/binman/elf_test.py b/tools/binman/elf_test.py
index 7a128018d9f..96630502b2f 100644
--- a/tools/binman/elf_test.py
+++ b/tools/binman/elf_test.py
@@ -134,8 +134,
Re: [PATCH v6 0/5] of-platdata: Avoid building libfdt
On Sun, Jul 25, 2021 at 10:13:42AM -0600, Simon Glass wrote: > The original patch of this series was sent in September 2019 but > unfortunately caused build problems on some boards, since they don't > comply with the of-platdata rules. > > With of-platdata, the idea is to compile the device tree into C structures > to save space and avoid needing to use libfdt. But some boards use > of-platdata while also using libfdt in a few areas, thus defeating the > purpose of of-platdata. > > This series includes the original two patches > >http://patchwork.ozlabs.org/patch/1167420/ >http://patchwork.ozlabs.org/patch/1167367/ > > as well as a few other patches to fix the build errors. Overall this > reduces code size and provides better error messages when unavailable > functions are used. > > Board maintainers should still take a look at the result, adjusting the > of-platdata support as needed. > > Note: This series was resent a year ago but not applied. Since then, some > boards have ended up using drivers in SPL which require OF_CONTROL, but > SPL_OF_CONTROL is not enabled. So now we have two problems. This series > fixes that one also. > > The problems will keep getting worse if people are not aware that > something is wrong. Therefore I think this patch series should be applied > ASAP. OK, so I took 5/6 and 6/6 and fired off a build. The only fails-to-link now are: am335x_boneblack_vboot am335x_evm am335x_evm_spiboot So are all of the other problems still present? I'm going to look in to the am335x failures. -- Tom signature.asc Description: PGP signature
Debugging dtoc?
So, I'm trying to fix the problem on am335x_evm (and some family
configs) with needing SPL_OF_CONTROL enabled. This is mostly fine just
enabling the option, except on am335x_evm itself, which is the
kitchen-sink config and overflows memory. I've gone with switching to
SPL_OF_PLATDATA there as am335x in general has all of the U_BOOT_DRVINFO
entries it needs I believe. But, with the following patch:
diff --git a/arch/arm/dts/am335x-evm-u-boot.dtsi
b/arch/arm/dts/am335x-evm-u-boot.dtsi
index 4cf5f9928d58..514f682cac99 100644
--- a/arch/arm/dts/am335x-evm-u-boot.dtsi
+++ b/arch/arm/dts/am335x-evm-u-boot.dtsi
@@ -8,6 +8,7 @@
&l4_per {
segment@30 {
+ u-boot,dm-pre-reloc;
target-module@e000 {
u-boot,dm-pre-reloc;
diff --git a/configs/am335x_boneblack_vboot_defconfig
b/configs/am335x_boneblack_vboot_defconfig
index a0baeec79edd..ffeefd1a0087 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -31,6 +31,7 @@ CONFIG_CMD_SPL=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_DNS2=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index a33efff42a74..f35b2a02f56b 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -37,13 +37,16 @@ CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk
am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
+CONFIG_SPL_OF_PLATDATA=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_ENV_IS_NOWHERE=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
+# CONFIG_SPL_SIMPLE_BUS is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_CLK=y
CONFIG_CLK_CDCE9XX=y
diff --git a/configs/am335x_evm_spiboot_defconfig
b/configs/am335x_evm_spiboot_defconfig
index 8f0c330674a9..4a2a56a9af9e 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -32,6 +32,7 @@ CONFIG_BOOTP_DNS2=y
CONFIG_CMD_MTDPARTS=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk
am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
CONFIG_ENV_OVERWRITE=y
# CONFIG_ENV_IS_IN_FAT is not set
I get the following failure and I don't see how to debug this:
DTOCspl/dts/dt-plat.c
Traceback (most recent call last):
File "./tools/dtoc/dtoc", line 115, in
args.phase, instantiate=args.instantiate)
File "/home/trini/work/u-boot/u-boot/tools/dtoc/../dtoc/dtb_platdata.py",
line 1223, in run_steps
outfile.method(plat)
File "/home/trini/work/u-boot/u-boot/tools/dtoc/../dtoc/dtb_platdata.py",
line 1081, in generate_plat
self.output_node_plat(node)
File "/home/trini/work/u-boot/u-boot/tools/dtoc/../dtoc/dtb_platdata.py",
line 1023, in output_node_plat
self._output_values(node)
File "/home/trini/work/u-boot/u-boot/tools/dtoc/../dtoc/dtb_platdata.py",
line 812, in _output_values
self._output_prop(node, node.props[pname])
File "/home/trini/work/u-boot/u-boot/tools/dtoc/../dtoc/dtb_platdata.py",
line 798, in _output_prop
self._output_list(node, prop)
File "/home/trini/work/u-boot/u-boot/tools/dtoc/../dtoc/dtb_platdata.py",
line 628, in _output_list
vals.append(get_value(prop.type, val))
File "/home/trini/work/u-boot/u-boot/tools/dtoc/../dtoc/dtb_platdata.py",
line 126, in get_value
val = '%#x' % fdt_util.fdt32_to_cpu(value)
File "/home/trini/work/u-boot/u-boot/tools/dtoc/../dtoc/fdt_util.py", line
28, in fdt32_to_cpu
return struct.unpack('>I', val)[0]
TypeError: a bytes-like object is required, not 'bool'
scripts/Makefile.spl:352: recipe for target 'spl/dts/dt-plat.c' failed
make[1]: *** [spl/dts/dt-plat.c] Error 1
make[1]: *** Deleting file 'spl/dts/dt-plat.c'
Makefile:1999: recipe for target 'spl/u-boot-spl' failed
make: *** [spl/u-boot-spl] Error 2
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH 1/7] mmc: sdhci: Return error in case of failure
Hi Ashok,
On 7/24/21 5:10 PM, Ashok Reddy Soma wrote:
> From: T Karthik Reddy
>
> set_delay() function is from sdhci host ops, which does not return
> any error due to void return type. Get return values from input and
> output set clock phase functions inside arasan_sdhci_set_tapdelay()
> and return the errors.
>
> Change return type to int for arasan_sdhci_set_tapdelay() and also for
> set_delay() in sdhci_ops structure.
Could you separate the patch to sdhci and zync_sdhci part?
>
> Signed-off-by: T Karthik Reddy
> Signed-off-by: Ashok Reddy Soma
> ---
>
> drivers/mmc/sdhci.c | 8 ++--
> drivers/mmc/zynq_sdhci.c | 21 -
> include/sdhci.h | 2 +-
> 3 files changed, 23 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
> index d9ab6a0a83..f144602eec 100644
> --- a/drivers/mmc/sdhci.c
> +++ b/drivers/mmc/sdhci.c
> @@ -366,6 +366,7 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
> {
> struct sdhci_host *host = mmc->priv;
> unsigned int div, clk = 0, timeout;
> + int ret;
>
> /* Wait max 20 ms */
> timeout = 200;
> @@ -386,8 +387,11 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
> if (clock == 0)
> return 0;
>
> - if (host->ops && host->ops->set_delay)
> - host->ops->set_delay(host);
> + if (host->ops && host->ops->set_delay) {
> + ret = host->ops->set_delay(host);
> + if (ret)
> + return ret;
how about adding debug(). It's helpful to debug when it's failed.
Best Regards,
Jaehoon Chung
> + }
>
> if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
> /*
> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
> index ba87ee8dd5..9fb3603c7e 100644
> --- a/drivers/mmc/zynq_sdhci.c
> +++ b/drivers/mmc/zynq_sdhci.c
> @@ -422,7 +422,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
> sdhci_host *host,
> return 0;
> }
>
> -static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
> +static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
> {
> struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
> struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
> @@ -431,18 +431,29 @@ static void arasan_sdhci_set_tapdelay(struct sdhci_host
> *host)
> u8 timing = mode2timing[mmc->selected_mode];
> u32 iclk_phase = clk_data->clk_phase_in[timing];
> u32 oclk_phase = clk_data->clk_phase_out[timing];
> + int ret;
>
> dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name, timing);
>
> if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
> device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
> - sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
> - sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
> + ret = sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
> + if (ret)
> + return ret;
> + ret = sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
> + if (ret)
> + return ret;
> } else if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
> device_is_compatible(dev, "xlnx,versal-8.9a")) {
> - sdhci_versal_sampleclk_set_phase(host, iclk_phase);
> - sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
> + ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase);
> + if (ret)
> + return ret;
> + ret = sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
> + if (ret)
> + return ret;
> }
> +
> + return 0;
> }
>
> static void arasan_dt_read_clk_phase(struct udevice *dev, unsigned char
> timing,
> diff --git a/include/sdhci.h b/include/sdhci.h
> index 0ae9471ad7..44a0d84e5a 100644
> --- a/include/sdhci.h
> +++ b/include/sdhci.h
> @@ -268,7 +268,7 @@ struct sdhci_ops {
> int (*set_ios_post)(struct sdhci_host *host);
> void(*set_clock)(struct sdhci_host *host, u32 div);
> int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
> - void (*set_delay)(struct sdhci_host *host);
> + int (*set_delay)(struct sdhci_host *host);
> int (*deferred_probe)(struct sdhci_host *host);
> };
>
>
[PATCH] arm: mvebu: sata_mv failed to identify HDDs during cold start
During cold start, with some HDDs, mv_sata_identify() does not populate
the ID words on the 1st ATA ID command. In fact, the first ATA ID
command will only power up the drive, and then the ATA ID command
processing is lost in the process.
Tests with:
- Seagate ST9250320AS 250GB HDD and Seagate ST4000DM004-2CV104 4TB HDD.
- Zyxel NSA310S (Kirkwood 88F6702), Marvell Dreamplug (Kirkwood 88F6281),
Seagate GoFlex Home (Kirkwood 88F6281), Pogoplug V4 (Kirkwood 88F6192).
Observation:
- The Seagate ST9250320AS 250GB took about 3 seconds to spin up.
- The Seagate ST4000DM004-2CV104 4TB took about 8 seconds to spin up.
- mv_sata_identify() did not populate the ID words after the call to
mv_ata_exec_ata_cmd_nondma().
- Attempt to insert a long delay of 30 seconds, ie. mdelay(30_000), after
the call to ata_wait_register() inside mv_ata_exec_ata_cmd_nondma() did
not help with the 4TB drive. The ID words were still empty after that 30s
delay.
Patch Description:
- Added a second ATA ID command in mv_sata_identify(), which will be
executed if the 1st ATA ID command did not return with valid ID words.
- Use the HDD drive capacity in the ID words as a successful indicator of
ATA ID command.
- In the scenario where a box is rebooted, the 1st ATA ID command is always
successful, so there is no extra time wasted.
- In the scenario where a box is cold started, the 1st ATA command is the
power up command. The 2nd ATA ID command alleviates the uncertainty of
how long we have to wait for the ID words to be populated by the SATA
controller.
Signed-off-by: Tony Dinh
---
drivers/ata/sata_mv.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 1012cb5374..7d1515d5f8 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -809,6 +809,7 @@ static int mv_ata_exec_ata_cmd_nondma(struct udevice *dev,
int port,
static int mv_sata_identify(struct udevice *dev, int port, u16 *id)
{
struct sata_fis_h2d h2d;
+ int len;
memset(&h2d, 0, sizeof(struct sata_fis_h2d));
@@ -818,8 +819,32 @@ static int mv_sata_identify(struct udevice *dev, int port,
u16 *id)
/* Give device time to get operational */
mdelay(10);
- return mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id,
- ATA_ID_WORDS * 2, READ_CMD);
+ /* During cold start, with some HDDs, the first ATA ID command does
+* not populate the ID words. In fact, the first ATA ID
+* command will only power up the drive, and then the ATA ID command
+* processing is lost in the process.
+*/
+ len = mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id,
+ATA_ID_WORDS * 2, READ_CMD);
+
+ /* If drive capacity has been filled in, then it was successfully
+* identified (the drive has been powered up before, i.e.
+* this function is invoked during a reboot)
+*/
+ if (ata_id_n_sectors(id) != 0)
+ return len;
+
+ /* Issue the 2nd ATA ID command to make sure the ID words are
+* populated properly.
+*/
+ mdelay(10);
+ len = mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id,
+ATA_ID_WORDS * 2, READ_CMD);
+ if (ata_id_n_sectors(id) != 0)
+ return len;
+
+ printf("Err: Failed to identify SATA device %d\n", port);
+ return -1;
}
static void mv_sata_xfer_mode(struct udevice *dev, int port, u16 *id)
--
2.20.1
Re: [PATCH 1/2] GPIO: fxl6408: Add support for FXL6408 GPIO expander
Hi Simon,
On Sun, Jul 25, 2021 at 1:01 AM Simon Glass wrote:
>
> Hi Oleksandr,
>
> On Wed, 21 Jul 2021 at 06:21, Oleksandr Suvorov
> wrote:
> >
> > Initial support for Fairchild's 8 bit I2C gpio expander FXL6408.
> > The CONFIG_FXL6408_GPIO define enables support for such devices.
> >
> > Based on: https://patchwork.kernel.org/patch/9148419/
> >
> > Signed-off-by: Oleksandr Suvorov
> > ---
> >
> > drivers/gpio/Kconfig| 7 +
> > drivers/gpio/Makefile | 1 +
> > drivers/gpio/gpio-fxl6408.c | 371
> > 3 files changed, 379 insertions(+)
> > create mode 100644 drivers/gpio/gpio-fxl6408.c
>
> Reviewed-by: Simon Glass
>
> Lots of nits below
Thanks for your detailed and extremely useful review!
> >
> > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> > index 0817b12c5f..5883582a7f 100644
> > --- a/drivers/gpio/Kconfig
> > +++ b/drivers/gpio/Kconfig
> > @@ -123,6 +123,13 @@ config DA8XX_GPIO
> > help
> > This driver supports the DA8xx GPIO controller
> >
> > +config FXL6408_GPIO
> > + bool "FXL6408 I2C GPIO driver"
> > + depends on DM_GPIO && DM_I2C
> > + help
> > + Support for Fairchild Semiconductor FXL6408 I2C 8-bit GPIO
> > + expander.
>
> Please add some more details here.
Some details are being added to the next version of the patch set.
> [..]
>
> > diff --git a/drivers/gpio/gpio-fxl6408.c b/drivers/gpio/gpio-fxl6408.c
> > new file mode 100644
> > index 00..282ec0a69c
> > --- /dev/null
> > +++ b/drivers/gpio/gpio-fxl6408.c
> > @@ -0,0 +1,371 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2021 Toradex
> > + * Copyright (C) 2016 Broadcom
> > + */
> > +
> > +/**
> > + * DOC: FXL6408 I2C to GPIO expander.
> > + *
> > + * This chip has 8 GPIO lines out of it, and is controlled by an I2C
> > + * bus (a pair of lines), providing 4x expansion of GPIO lines. It
> > + * also provides an interrupt line out for notifying of state changes.
> > + *
> > + * Any preconfigured state will be left in place until the GPIO lines
> > + * get activated. At power on, everything is treated as an input,
> > + * default input is HIGH and pulled-up, all interrupts are masked.
> > + *
> > + * Documentation can be found at:
> > + * https://www.fairchildsemi.com/datasheets/FX/FXL6408.pdf
> > + *
> > + * This driver bases on:
> > + * - the original driver by Eric Anholt :
> > + * https://patchwork.kernel.org/patch/9148419/
> > + * - the Toradex version by Max Krummenacher
> > :
> > + *
> > http://git.toradex.com/cgit/linux-toradex.git/tree/drivers/gpio/gpio-fxl6408.c?h=toradex_5.4-2.3.x-imx
> > + * - the U-boot PCA953x driver by Peng Fan :
> > + * drivers/gpio/pca953x_gpio.c
> > + *
> > + * TODO: Add interrupts support
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#define FXL6408_DEVID_CTRL 0x01
>
> Do you need the FXL6408 prefix?
Actually, no :) Thanks, I renamed all registers in a straight manner.
They'll be introduced in the next patchset version.
> > +# define FXL6408_SW_RSTBIT(0)
> > +# define FXL6408_RST_INT BIT(1)
> > +
> > +/* 3-bit manufacturer ID */
> > +# define FXL6408_MF_MASK GENMASK(7, 5)
> > +# define FXL6408_MF_ID(devid) (((devid) & FXL6408_MF_MASK) >> 5)
> > +/* 0b101 is for Fairchild assigned by Nokia */
> > +# define FXL6408_FAIRCHILD_MF 5
> > +
> > +/* 3-bit firmware revision */
> > +# define FXL6408_FW_MASK GENMASK(4, 2)
> > +# define FXL6408_FW_REV(devid) (((devid) & FXL6408_FW_MASK) >> 2)
>
> This is only used once, so why not include that code inline below?
This way is clearer to read as for me. Moreover, if we include only
FW_REV()'s code inline,
the shifting and the purpose of such shifting were in different places.
Don't you mind leaving it as is? (with some names simplifying)
> > +
> > +/*
> > + * Bits set here indicate that the GPIO is an output.
>
> single-line comment style is /* ... */
Thanks, fixed!
> > + */
> > +#define FXL6408_DIRECTION 0x03
>
> Then call it DIR_MASK ?
Formally, it is not a mask but a register.
All register names will be tuned in the next patchset version.
> > +
> > +enum {
> > + FXL6408_DIRECTION_IN,
> > + FXL6408_DIRECTION_OUT,
> > +};
> > +
> > +/*
> > + * Bits set here, when the corresponding bit of IO_DIR is set, drive
> > + * the output high instead of low.
> > + */
> > +#define FXL6408_OUTPUT 0x05
> > +
> > +/*
> > + * Bits here make the output High-Z, instead of the OUTPUT value.
> > + */
> > +#define FXL6408_OUTPUT_HIGH_Z 0x07
> > +
> > +/*
> > + * Bits here define the expected input state of the GPIO.
> > + * INTERRUPT_STATUS bits will be set when the INPUT transitions away
> > + * from this value.
> > + */
> > +#define FXL6408_INPUT_DEF_STATE0x09
> > +
[PATCH] rockchip: Fix u-boot-rockchip.bin build
Currently there are a few arm32 rockchip board configs that don't generate u-boot-rockchip.bin when running make because CONFIG_BINMAN is not enabled. This patch changes CONFIG_ARCH_ROCKCHIP to also select CONFIG_BINMAN if CONFIG_SPL and !CONFIG_ARM64. Example builds that don't generate u-boot-rockchip.bin without this patch: export ARCH=arm export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf- make kylin-rk3036_defconfig make export ARCH=arm export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf- make rock_defconfig make export ARCH=arm export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf- make tinker-rk3288_defconfig make Signed-off-by: Johan Gunnarsson --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9de97cc101..5a8672cdd6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1791,7 +1791,7 @@ config ARCH_STM32MP config ARCH_ROCKCHIP bool "Support Rockchip SoCs" select BLK - select BINMAN if SPL_OPTEE + select BINMAN if SPL_OPTEE || (SPL && !ARM64) select DM select DM_GPIO select DM_I2C -- 2.25.1
[PATCH 00/27] Add F1C100s based PocketGo handheld support
This series add support for the PocketGo handheld, a low cost portable gaming console that is based on the Allwinner F1C100s chip. A significant portion of this patchset is authored by: - Icenowy Zheng - George Hilliard This patchset includes 4 parts necessary to make PocketGo work: - suniv + f1c100s support by Icenowy Zheng , rebased by George Hilliard and then by me. See: https://github.com/Icenowy/u-boot/commits/f1c100s-spiflash - additional support for suniv clock and MMC controller by George Hilliard, rebased. See: https://github.com/thirtythreeforty/u-boot/tree/f1c100s-v2019.04 - additional support for serial uart1, and misc fixes for compilation, SPL -> U-Boot proper load on F1C100s. - DTS and defconfig for PocketGo I have accidentally CC'ed a few people while testing git send-email, I am awfully sorry for my lack of experience in email-patch based workflows. This is my first time attempting to contribute to U-Boot. Cc: Jagan Teki Cc: Andre Przywara Cc: Icenowy Zheng Cc: George Hilliard George Hilliard (6): sunxi: Don't provide enable_cache() on suniv sunxi: implement clock driver for suniv f1c100s sunxi: gpio: Add support for suniv-f1c100s sunxi: spi: restore bus speed and mode after reset sunxi: spi: Add suniv pin controller support sunxi: suniv: add device tree nodes for f1c100s MMC controllers Icenowy Zheng (12): arm: arm926ejs: start.S: port save_boot_params support from armv7 code arm: arm926ej-s: add sunxi code sunxi: add support for suniv architecture sunxi: suniv: add support for Lichee Pi Nano sunxi: suniv: add boot sequence for SPL to try sunxi: spi-spl: add support for SUNIV sunxi: add SPI0 node for suniv sunxi: enable SPI NOR on Lichee Pi Nano sunxi: add defconfig for Lichee Pi Nano with SPI Flash support sunxi: add support for UART at PF for suniv sunxi: do not set PF MMC0 pinmux when PF uart is used sunxi: allow to enable MMC driver when using PF UART0 Yifan Gu (9): arm: dts: sunxi: do not renumber if mmc2 does not exist board: licheepi_nano: set CONFIG_MMC_SUNXI_SLOT_EXTRA sunxi: suniv: add missing header include for udelay sunxi: suniv: allow serial connection on uart1 sunxi: suniv: do not detect boot sector on suniv sunxi: suniv: set SYS_TEXT_BASE default sunxi: suniv: disable mmc optimization for suniv arm: dts: suniv: define uart1 pins arm: dts: add pocketgo handheld support arch/arm/cpu/arm926ejs/Makefile | 1 + arch/arm/cpu/arm926ejs/start.S| 19 + arch/arm/cpu/arm926ejs/sunxi/Makefile | 16 + arch/arm/cpu/arm926ejs/sunxi/config.mk| 6 + arch/arm/cpu/arm926ejs/sunxi/fel_utils.S | 38 ++ arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S | 68 +++ arch/arm/cpu/arm926ejs/sunxi/start.c | 1 + arch/arm/cpu/arm926ejs/sunxi/timer.c | 114 arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds | 63 +++ arch/arm/dts/Makefile | 3 + arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 58 ++ arch/arm/dts/suniv-f1c100s-pocketgo.dts | 48 ++ arch/arm/dts/suniv-f1c100s.dtsi | 6 + arch/arm/dts/suniv.dtsi | 253 + arch/arm/dts/sunxi-u-boot.dtsi| 2 + arch/arm/include/asm/arch-sunxi/clock.h | 2 +- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 21 + arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 8 + arch/arm/include/asm/arch-sunxi/dram.h| 2 + arch/arm/include/asm/arch-sunxi/dram_suniv.h | 47 ++ arch/arm/include/asm/arch-sunxi/gpio.h| 3 + arch/arm/mach-sunxi/Kconfig | 16 +- arch/arm/mach-sunxi/Makefile | 2 + arch/arm/mach-sunxi/board.c | 37 +- arch/arm/mach-sunxi/clock.c | 3 +- arch/arm/mach-sunxi/clock_sun6i.c | 47 +- arch/arm/mach-sunxi/cpu_info.c| 2 + arch/arm/mach-sunxi/dram_helpers.c| 4 + arch/arm/mach-sunxi/dram_suniv.c | 497 ++ arch/arm/mach-sunxi/spl_spi_sunxi.c | 13 + board/sunxi/board.c | 8 +- common/Kconfig.boot | 3 +- configs/licheepi_nano_defconfig | 10 + configs/licheepi_nano_spiflash_defconfig | 26 + configs/pocketgo_defconfig| 12 + drivers/clk/sunxi/Kconfig | 7 + drivers/clk/sunxi/Makefile| 1 + drivers/clk/sunxi/clk_f1c100s.c | 66 +++ drivers/gpio/sunxi_gpio.c | 6 + drivers/mmc/Kconfig | 2 +- drivers/mmc/sunxi_mmc.c | 6 +- drivers/spi/spi-sunxi.c | 12 +- include/configs/suniv.h | 15 + include/configs/sunxi-common.h| 69 ++- include/dt-bindings/clock/suniv-ccu.h | 69 +++ include/dt-bindings/reset/suniv-ccu.h
[PATCH 04/27] sunxi: suniv: add support for Lichee Pi Nano
From: Icenowy Zheng
Lichee Pi Nano is a board based on F1C100s.
Add support for it.
Signed-off-by: Icenowy Zheng
Signed-off-by: Yifan Gu
---
arch/arm/dts/Makefile| 2 +
arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 43
configs/licheepi_nano_defconfig | 9
3 files changed, 54 insertions(+)
create mode 100644 arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
create mode 100644 configs/licheepi_nano_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3941a08cf4..a1207a33f5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -665,6 +665,8 @@ dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb \
sun9i-a80-cx-a99.dtb
+dtb-$(CONFIG_MACH_SUNIV) += \
+ suniv-f1c100s-licheepi-nano.dtb
dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
vf610-colibri.dtb \
diff --git a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
new file mode 100644
index 00..2820f8238d
--- /dev/null
+++ b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2018 Icenowy Zheng
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+#include
+
+/ {
+ model = "Lichee Pi Nano";
+ compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s",
+"allwinner,suniv";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pe_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpio = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
+ status = "okay";
+};
diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig
new file mode 100644
index 00..6e455baadf
--- /dev/null
+++ b/configs/licheepi_nano_defconfig
@@ -0,0 +1,9 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUNIV=y
+CONFIG_DRAM_CLK=156
+CONFIG_DRAM_ZQ=0
+# CONFIG_VIDEO_SUNXI is not set
+CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano"
+CONFIG_SPL=y
+# CONFIG_SPL_DM_SERIAL is not set
--
2.25.1
[PATCH 05/27] sunxi: suniv: add boot sequence for SPL to try
From: Icenowy Zheng
The BROM of suniv do not pass the info of boot media to SPL.
Add boot sequence for SPL to try again for the available boot media.
Signed-off-by: Icenowy Zheng
Signed-off-by: Yifan Gu
---
arch/arm/mach-sunxi/board.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 3b1a79eb5e..e84687973a 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -334,10 +334,32 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc
*mmc,
return sector;
}
+
+#ifndef CONFIG_MACH_SUNIV
u32 spl_boot_device(void)
{
return sunxi_get_boot_device();
}
+#else
+/*
+ * suniv BROM do not pass the boot media type to SPL, so we try with the
+ * boot sequence in BROM: mmc0->spinor->fail.
+ */
+void board_boot_order(u32 *spl_boot_list)
+{
+ /*
+* See the comments above in sunxi_get_boot_device() for infomation
+* about FEL boot.
+*/
+ if (!is_boot0_magic(SPL_ADDR + 4)) {
+ spl_boot_list[0] = BOOT_DEVICE_BOARD;
+ return;
+ }
+
+ spl_boot_list[0] = BOOT_DEVICE_MMC1;
+ spl_boot_list[1] = BOOT_DEVICE_SPI;
+}
+#endif
void board_init_f(ulong dummy)
{
--
2.25.1
[PATCH 07/27] sunxi: add SPI0 node for suniv
From: Icenowy Zheng
The suniv SoC has two SPI controllers, in which SPI0 is bootable.
Add device tree node of the controller and its bootable pinmux node.
Signed-off-by: Icenowy Zheng
Signed-off-by: Yifan Gu
---
arch/arm/dts/suniv.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/dts/suniv.dtsi b/arch/arm/dts/suniv.dtsi
index a5673f5006..b11d9eb57a 100644
--- a/arch/arm/dts/suniv.dtsi
+++ b/arch/arm/dts/suniv.dtsi
@@ -76,6 +76,19 @@
};
};
+ spi0: spi@1c05000 {
+ compatible = "allwinner,suniv-spi",
+"allwinner,sun8i-h3-spi";
+ reg = <0x01c05000 0x1000>;
+ interrupts = <10>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
ccu: clock@1c2 {
compatible = "allwinner,suniv-f1c100s-ccu";
reg = <0x01c2 0x400>;
@@ -103,6 +116,11 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ spi0_pins_a: spi0-pins-pc {
+ pins = "PC0", "PC1", "PC2", "PC3";
+ function = "spi0";
+ };
+
uart0_pe_pins: uart-pins-pe {
pins = "PE0", "PE1";
function = "uart0";
--
2.25.1
[PATCH 08/27] sunxi: enable SPI NOR on Lichee Pi Nano
From: Icenowy Zheng
The Lichee Pi Nano board has a Winbond W25Q128 SPI flash on it.
Enable it.
Signed-off-by: Icenowy Zheng
Signed-off-by: Yifan Gu
---
arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
index 2820f8238d..f2794e46f2 100644
--- a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
@@ -15,6 +15,7 @@
aliases {
serial0 = &uart0;
+ spi0 = &spi0;
};
chosen {
@@ -26,6 +27,20 @@
status = "okay";
};
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins_a>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "winbond,w25q128", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <4000>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pe_pins>;
--
2.25.1
[PATCH 10/27] sunxi: add support for UART at PF for suniv
From: Icenowy Zheng Signed-off-by: Icenowy Zheng Signed-off-by: Yifan Gu --- arch/arm/mach-sunxi/board.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index e84687973a..b471933ec8 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -87,7 +87,8 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); #endif -#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40) +#if (defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)) || \ +defined(CONFIG_MACH_SUNIV) sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); #else -- 2.25.1
[PATCH 09/27] sunxi: add defconfig for Lichee Pi Nano with SPI Flash support
From: Icenowy Zheng Signed-off-by: Icenowy Zheng Signed-off-by: Yifan Gu --- configs/licheepi_nano_spiflash_defconfig | 25 1 file changed, 25 insertions(+) create mode 100644 configs/licheepi_nano_spiflash_defconfig diff --git a/configs/licheepi_nano_spiflash_defconfig b/configs/licheepi_nano_spiflash_defconfig new file mode 100644 index 00..07b6a27dbe --- /dev/null +++ b/configs/licheepi_nano_spiflash_defconfig @@ -0,0 +1,25 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_ENV_SIZE=0x8000 +CONFIG_ENV_OFFSET=0xf8000 +CONFIG_MACH_SUNIV=y +CONFIG_DRAM_CLK=156 +CONFIG_DRAM_ZQ=0 +# CONFIG_VIDEO_SUNXI is not set +CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano" +CONFIG_SPL=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPL_SPI_SUNXI=y +# CONFIG_SPL_DM_SERIAL is not set +CONFIG_DM_SPI=y +CONFIG_SUN6I_SPI=y -- 2.25.1
[PATCH 01/27] arm: arm926ejs: start.S: port save_boot_params support from armv7 code
From: Icenowy Zheng The ARMv7 start code has support for saving some boot params at the entry point, which is used by some SoCs to return to BROM. Port this to ARM926EJ-S start code. Signed-off-by: Icenowy Zheng Signed-off-by: Yifan Gu --- arch/arm/cpu/arm926ejs/start.S | 19 +++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index ff592ba810..9011afed3f 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -17,6 +17,7 @@ #include #include #include +#include /* * @@ -32,8 +33,13 @@ */ .globl reset + .globl save_boot_params_ret + .type save_boot_params_ret,%function reset: + /* Allow the board to save important registers */ + b save_boot_params +save_boot_params_ret: /* * set the cpu to SVC32 mode */ @@ -110,3 +116,16 @@ flush_dcache: #endif mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +/* + * + * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) + * __attribute__((weak)); + * + * Stack pointer is not yet initialized at this moment + * Don't save anything to stack even if compiled with -O0 + * + */ +WEAK(save_boot_params) + b save_boot_params_ret/* back to my caller */ +ENDPROC(save_boot_params) -- 2.25.1
[PATCH 11/27] sunxi: do not set PF MMC0 pinmux when PF uart is used
From: Icenowy Zheng
Signed-off-by: Icenowy Zheng
Signed-off-by: Yifan Gu
---
board/sunxi/board.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 27ab44b67c..748c1a8673 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -412,17 +412,19 @@ void board_nand_init(void)
#ifdef CONFIG_MMC
static void mmc_pinmux_setup(int sdc)
{
- unsigned int pin;
+ __maybe_unused unsigned int pin;
__maybe_unused int pins;
switch (sdc) {
case 0:
/* SDC0: PF0-PF5 */
+#ifndef CONFIG_UART0_PORT_F
for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
+#endif
break;
case 1:
--
2.25.1
[PATCH 03/27] sunxi: add support for suniv architecture
From: Icenowy Zheng
Add support for the suniv architecture, which is newer ARM9 SoCs by
Allwinner. The design of it seems to be a mixture of sun3i, sun4i and
sun6i.
Signed-off-by: Icenowy Zheng
Rebased-by: George Hilliard
Signed-off-by: Yifan Gu
---
arch/arm/dts/suniv-f1c100s.dtsi | 6 +
arch/arm/dts/suniv.dtsi | 183 +++
arch/arm/include/asm/arch-sunxi/clock.h | 2 +-
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 21 +
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 8 +
arch/arm/include/asm/arch-sunxi/dram.h| 2 +
arch/arm/include/asm/arch-sunxi/dram_suniv.h | 47 ++
arch/arm/include/asm/arch-sunxi/gpio.h| 1 +
arch/arm/mach-sunxi/Kconfig | 14 +-
arch/arm/mach-sunxi/Makefile | 2 +
arch/arm/mach-sunxi/board.c | 7 +-
arch/arm/mach-sunxi/clock.c | 3 +-
arch/arm/mach-sunxi/clock_sun6i.c | 47 +-
arch/arm/mach-sunxi/cpu_info.c| 2 +
arch/arm/mach-sunxi/dram_helpers.c| 4 +
arch/arm/mach-sunxi/dram_suniv.c | 496 ++
board/sunxi/board.c | 4 +-
include/configs/suniv.h | 15 +
include/configs/sunxi-common.h| 69 ++-
include/dt-bindings/clock/suniv-ccu.h | 69 +++
include/dt-bindings/reset/suniv-ccu.h | 37 ++
21 files changed, 1013 insertions(+), 26 deletions(-)
create mode 100644 arch/arm/dts/suniv-f1c100s.dtsi
create mode 100644 arch/arm/dts/suniv.dtsi
create mode 100644 arch/arm/include/asm/arch-sunxi/dram_suniv.h
create mode 100644 arch/arm/mach-sunxi/dram_suniv.c
create mode 100644 include/configs/suniv.h
create mode 100644 include/dt-bindings/clock/suniv-ccu.h
create mode 100644 include/dt-bindings/reset/suniv-ccu.h
diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi
new file mode 100644
index 00..f084bc8dd1
--- /dev/null
+++ b/arch/arm/dts/suniv-f1c100s.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2018 Icenowy Zheng
+ */
+
+#include "suniv.dtsi"
diff --git a/arch/arm/dts/suniv.dtsi b/arch/arm/dts/suniv.dtsi
new file mode 100644
index 00..a5673f5006
--- /dev/null
+++ b/arch/arm/dts/suniv.dtsi
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2018 Icenowy Zheng
+ */
+
+#include
+#include
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: clk-24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: clk-32k {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ fake100M: clk-100M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+ clock-output-names = "fake-100M";
+ };
+ };
+
+ cpus {
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram-controller@1c0 {
+ compatible = "allwinner,sun4i-a10-sram-controller";
+ reg = <0x01c0 0x30>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_d: sram@1 {
+ compatible = "mmio-sram";
+ reg = <0x0001 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0001 0x1000>;
+
+ otg_sram: sram-section@0 {
+ compatible =
"allwinner,sun4i-a10-sram-d";
+ reg = <0x 0x1000>;
+ status = "disabled";
+ };
+ };
+ };
+
+ ccu: clock@1c2 {
+ compatible = "allwinner,suniv-f1c100s-ccu";
+ reg = <
[PATCH 12/27] sunxi: allow to enable MMC driver when using PF UART0
From: Icenowy Zheng As the pinmux setup of MMC0 at PF is masked, the sunxi MMC driver is now harmless for PF uart setup, and it may be used for the extra MMC port. Signed-off-by: Icenowy Zheng Signed-off-by: Yifan Gu --- drivers/mmc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 717ce5a62f..5c363972ec 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -723,7 +723,7 @@ config ZYNQ_HISPD_BROKEN config MMC_SUNXI bool "Allwinner sunxi SD/MMC Host Controller support" - depends on ARCH_SUNXI && !UART0_PORT_F + depends on ARCH_SUNXI default y help This selects support for the SD/MMC Host Controller on -- 2.25.1
[PATCH 24/27] sunxi: suniv: set SYS_TEXT_BASE default
suniv ddr memory starts at 0x800. Set SYS_TEXT_BASE accordingly so SPL can copy U-Boot proper to DRAM. Signed-off-by: Yifan Gu --- common/Kconfig.boot | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/Kconfig.boot b/common/Kconfig.boot index 642dd9bcfb..23c6db286a 100644 --- a/common/Kconfig.boot +++ b/common/Kconfig.boot @@ -360,9 +360,10 @@ config SYS_TEXT_BASE depends on HAVE_SYS_TEXT_BASE default 0x0 if POSITION_INDEPENDENT default 0x8080 if ARCH_OMAP2PLUS || ARCH_K3 - default 0x4a00 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S + default 0x4a00 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S && !MACH_SUNIV default 0x2a00 if ARCH_SUNXI && MACH_SUN9I default 0x42e0 if ARCH_SUNXI && MACH_SUN8I_V3S + default 0x81c0 if ARCH_SUNXI && MACH_SUNIV hex "Text Base" help The address in memory that U-Boot will be running from, initially. -- 2.25.1
[PATCH 26/27] arm: dts: suniv: define uart1 pins
Signed-off-by: Yifan Gu
---
arch/arm/dts/suniv.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/suniv.dtsi b/arch/arm/dts/suniv.dtsi
index bea7c08e7d..5d84f1e1af 100644
--- a/arch/arm/dts/suniv.dtsi
+++ b/arch/arm/dts/suniv.dtsi
@@ -126,6 +126,11 @@
function = "uart0";
};
+ uart1_pa_pins: uart-pins-pa {
+ pins = "PA2", "PA3";
+ function = "uart1";
+ };
+
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
function = "mmc0";
--
2.25.1
[PATCH 22/27] sunxi: suniv: allow serial connection on uart1
Signed-off-by: Yifan Gu
---
arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
arch/arm/mach-sunxi/board.c| 4
2 files changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 26c900fb11..2b03325adf 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -180,6 +180,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPD_PWM 2
#define SUNIV_GPE_UART05
+#define SUNIV_GPA_UART15
#define SUN5I_GPE_SDC2 3
#define SUN8I_GPE_TWI2 3
#define SUN50I_GPE_TWI23
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 6dd2c6a4d8..7fa44b6f3a 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -100,6 +100,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0);
sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPA_UART1);
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPA_UART1);
+ sunxi_gpio_set_pull(SUNXI_GPA(2), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40))
--
2.25.1
[PATCH 06/27] sunxi: spi-spl: add support for SUNIV
From: Icenowy Zheng
The suniv SoC come with a sun6i-style SPI controller at the base address
of sun4i SPI controller. The module clock of the SPI controller is also
missing.
Add support for it.
Signed-off-by: Icenowy Zheng
Signed-off-by: Yifan Gu
---
arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
arch/arm/mach-sunxi/Kconfig| 2 +-
arch/arm/mach-sunxi/spl_spi_sunxi.c| 13 +
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index b0b86b812a..26c900fb11 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -170,6 +170,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPC_NAND 2
#define SUNXI_GPC_SPI0 3
#define SUNXI_GPC_SDC2 3
+#define SUNIV_GPC_SPI0 2
#define SUN6I_GPC_SDC3 4
#define SUN50I_GPC_SPI04
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index f15b4e8bda..4fde7e1da1 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1067,7 +1067,7 @@ config SPL_STACK_R_ADDR
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"
- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5
|| MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
+ depends on MACH_SUNIV || MACH_SUN4I || MACH_SUN5I || MACH_SUN7I ||
MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
help
Enable support for SPI Flash. This option allows SPL to read from
sunxi SPI Flash. It uses the same method as the boot ROM, so does
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 15e86cbac8..f6f65a0e3d 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -89,6 +89,7 @@
#define SPI0_CLK_DIV_BY_2 0x1000
#define SPI0_CLK_DIV_BY_4 0x1001
+#define SPI0_CLK_DIV_BY_32 0x100f
/*/
@@ -120,6 +121,7 @@ static void spi0_pinmux_setup(unsigned int pin_function)
static bool is_sun6i_gen_spi(void)
{
return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ||
+ IS_ENABLED(CONFIG_MACH_SUNIV) ||
IS_ENABLED(CONFIG_MACH_SUN50I_H6);
}
@@ -155,11 +157,17 @@ static void spi0_enable_clock(void)
if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
+#ifdef CONFIG_MACH_SUNIV
+ /* Divide by 32, clock source is AHB clock 200MHz */
+ writel(SPI0_CLK_DIV_BY_32, base + (is_sun6i_gen_spi() ?
+ SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
+#else
/* Divide by 4 */
writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ?
SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
/* 24MHz from OSC24M */
writel((1 << 31), CCM_SPI0_CLK);
+#endif
if (is_sun6i_gen_spi()) {
/* Enable SPI in the master mode and do a soft reset */
@@ -189,8 +197,10 @@ static void spi0_disable_clock(void)
clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
SUN4I_CTL_ENABLE);
+#ifndef CONFIG_MACH_SUNIV
/* Disable the SPI0 clock */
writel(0, CCM_SPI0_CLK);
+#endif
/* Close the SPI0 gate */
if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
@@ -212,6 +222,9 @@ static void spi0_init(void)
IS_ENABLED(CONFIG_MACH_SUN50I_H6))
pin_function = SUN50I_GPC_SPI0;
+ if (IS_ENABLED(CONFIG_MACH_SUNIV))
+ pin_function = SUNIV_GPC_SPI0;
+
spi0_pinmux_setup(pin_function);
spi0_enable_clock();
}
--
2.25.1
[PATCH 02/27] arm: arm926ej-s: add sunxi code
From: Icenowy Zheng Some Allwinner SoCs use ARM926EJ-S core. Add Allwinner/sunXi specific code to ARM926EJ-S CPU dircetory. Signed-off-by: Icenowy Zheng Signed-off-by: Yifan Gu --- arch/arm/cpu/arm926ejs/Makefile | 1 + arch/arm/cpu/arm926ejs/sunxi/Makefile| 16 +++ arch/arm/cpu/arm926ejs/sunxi/config.mk | 6 + arch/arm/cpu/arm926ejs/sunxi/fel_utils.S | 38 +++ arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S | 68 +++ arch/arm/cpu/arm926ejs/sunxi/start.c | 1 + arch/arm/cpu/arm926ejs/sunxi/timer.c | 114 +++ arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds | 63 ++ 8 files changed, 307 insertions(+) create mode 100644 arch/arm/cpu/arm926ejs/sunxi/Makefile create mode 100644 arch/arm/cpu/arm926ejs/sunxi/config.mk create mode 100644 arch/arm/cpu/arm926ejs/sunxi/fel_utils.S create mode 100644 arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S create mode 100644 arch/arm/cpu/arm926ejs/sunxi/start.c create mode 100644 arch/arm/cpu/arm926ejs/sunxi/timer.c create mode 100644 arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index 98aafe805a..5cf089d8e5 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_MX25) += mx25/ obj-$(CONFIG_MX27) += mx27/ obj-$(if $(filter mxs,$(SOC)),y) += mxs/ obj-$(if $(filter spear,$(SOC)),y) += spear/ +obj-$(CONFIG_ARCH_SUNXI) += sunxi/ # some files can only build in ARM or THUMB2, not THUMB1 diff --git a/arch/arm/cpu/arm926ejs/sunxi/Makefile b/arch/arm/cpu/arm926ejs/sunxi/Makefile new file mode 100644 index 00..61b9864f6a --- /dev/null +++ b/arch/arm/cpu/arm926ejs/sunxi/Makefile @@ -0,0 +1,16 @@ +# +# (C) Copyright 2012 Henrik Nordstrom +# +# Based on some other Makefile +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y += timer.o +obj-y += lowlevel_init.o + +ifdef CONFIG_SPL_BUILD +obj-y += fel_utils.o +CFLAGS_fel_utils.o := -marm +endif diff --git a/arch/arm/cpu/arm926ejs/sunxi/config.mk b/arch/arm/cpu/arm926ejs/sunxi/config.mk new file mode 100644 index 00..76ffec9df6 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/sunxi/config.mk @@ -0,0 +1,6 @@ +# Build a combined spl + u-boot image +ifdef CONFIG_SPL +ifndef CONFIG_SPL_BUILD +ALL-y += u-boot-sunxi-with-spl.bin +endif +endif diff --git a/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S b/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S new file mode 100644 index 00..ca91377008 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/sunxi/fel_utils.S @@ -0,0 +1,38 @@ +/* + * Utility functions for FEL mode. + * + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include +#include +#include +#include + +ENTRY(save_boot_params) + ldr r0, =fel_stash + str sp, [r0, #0] + str lr, [r0, #4] + mrs lr, cpsr@ Read CPSR + str lr, [r0, #8] + mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register + str lr, [r0, #12] + mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register + str lr, [r0, #16] + b save_boot_params_ret +ENDPROC(save_boot_params) + +ENTRY(return_to_fel) + mov sp, r0 + mov lr, r1 + ldr r0, =fel_stash + ldr r1, [r0, #16] + mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register + ldr r1, [r0, #12] + mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register + ldr r1, [r0, #8] + msr cpsr, r1@ Write CPSR + bx lr +ENDPROC(return_to_fel) diff --git a/arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S b/arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S new file mode 100644 index 00..2bfd907026 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S @@ -0,0 +1,68 @@ +/* + * A lowlevel_init function that sets up the stack to call a C function to + * perform further init. + * + * Based on lowlevel_init.S in armv7 directory, which is: + * (C) Copyright 2010 Texas Instruments, + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include +#include +#include + +.pushsection .text.s_init, "ax" +WEAK(s_init) + bx lr +ENDPROC(s_init) +.popsection + +.pushsection .text.lowlevel_init, "ax" +WEAK(lowlevel_init) + /* +* Setup a temporary stack. Global data is not available yet. +*/ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) + ldr sp, =CONFIG_SPL_STACK +#else + ldr sp, =CONFIG_SYS_INIT_SP_ADDR +#endif + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ +#ifdef CONFIG_SPL_DM + mov r9, #0 +#else + /* +* Set up global data for boards that still need it. This will be +* removed soon. +*/ +#ifdef CONFIG_SPL_BUILD + ldr
[PATCH 13/27] sunxi: Don't provide enable_cache() on suniv
From: George Hilliard
The arm926 code provides this function. Disable it here.
Signed-off-by: George Hilliard
Signed-off-by: Yifan Gu
---
arch/arm/mach-sunxi/board.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index b471933ec8..6dd2c6a4d8 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -406,7 +406,7 @@ void reset_cpu(void)
#endif
}
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) &&
!defined(CONFIG_CPU_ARM926EJS)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
--
2.25.1
[PATCH 25/27] sunxi: suniv: disable mmc optimization for suniv
suniv cannot boot with this mmc optimization, as suniv fifo level
register is only 4 bits.
Disable this optimization for suniv for now.
Signed-off-by: Yifan Gu
---
drivers/mmc/sunxi_mmc.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 178b8cf106..779c10407a 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -324,7 +324,7 @@ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv
*priv, struct mmc *mmc,
start = get_timer(0);
for (i = 0; i < word_cnt;) {
- unsigned int in_fifo;
+ __maybe_unused unsigned int in_fifo;
while ((status = readl(&priv->reg->status)) & status_bit) {
if (get_timer(start) > timeout_msecs)
@@ -343,6 +343,9 @@ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv
*priv, struct mmc *mmc,
continue;
}
+#ifdef CONFIG_MACH_SUNIV
+ buff[i++] = readl(&priv->reg->fifo);
+#else
/*
* The status register holds the current FIFO level, so we
* can be sure to collect as many words from the FIFO
@@ -355,6 +358,7 @@ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv
*priv, struct mmc *mmc,
in_fifo--)
buff[i++] = readl_relaxed(&priv->reg->fifo);
dmb();
+#endif
}
return 0;
--
2.25.1
[PATCH 27/27] arm: dts: add pocketgo handheld support
Signed-off-by: Yifan Gu
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/suniv-f1c100s-pocketgo.dts | 48 +
configs/pocketgo_defconfig | 12 +++
3 files changed, 62 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/suniv-f1c100s-pocketgo.dts
create mode 100644 configs/pocketgo_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a1207a33f5..a2287f5b35 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -666,7 +666,8 @@ dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-cubieboard4.dtb \
sun9i-a80-cx-a99.dtb
dtb-$(CONFIG_MACH_SUNIV) += \
- suniv-f1c100s-licheepi-nano.dtb
+ suniv-f1c100s-licheepi-nano.dtb \
+ suniv-f1c100s-pocketgo.dtb
dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
vf610-colibri.dtb \
diff --git a/arch/arm/dts/suniv-f1c100s-pocketgo.dts
b/arch/arm/dts/suniv-f1c100s-pocketgo.dts
new file mode 100644
index 00..9fdb646ac8
--- /dev/null
+++ b/arch/arm/dts/suniv-f1c100s-pocketgo.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2018 Icenowy Zheng
+ * Copyright 2021 Yifan Gu
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+#include
+
+/ {
+ model = "PocketGo Handheld";
+ compatible = "miyoo,pocketgo", "allwinner,suniv-f1c100s",
+"allwinner,suniv";
+
+ aliases {
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pa_pins>;
+ status = "okay";
+};
+
+&mmc0 {
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpio = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
+ status = "okay";
+};
diff --git a/configs/pocketgo_defconfig b/configs/pocketgo_defconfig
new file mode 100644
index 00..1f9bf4001f
--- /dev/null
+++ b/configs/pocketgo_defconfig
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUNIV=y
+CONFIG_DRAM_CLK=156
+CONFIG_DRAM_ZQ=0
+# CONFIG_VIDEO_SUNXI is not set
+CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-pocketgo"
+CONFIG_SPL=y
+# CONFIG_SPL_DM_SERIAL is not set
+CONFIG_MMC_SUNXI=y
+CONFIG_CONS_INDEX=2
+CONFIG_NET=n
--
2.25.1
[PATCH 23/27] sunxi: suniv: do not detect boot sector on suniv
The BROM of suniv does not pass info to SPL, and it should always boot
from the 8KB offset.
Signed-off-by: Yifan Gu
---
arch/arm/mach-sunxi/board.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 7fa44b6f3a..90c58ce86c 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -305,6 +305,7 @@ uint32_t sunxi_get_boot_device(void)
}
#ifdef CONFIG_SPL_BUILD
+#ifndef CONFIG_MACH_SUNIV
static u32 sunxi_get_spl_size(void)
{
if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
@@ -339,8 +340,6 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
return sector;
}
-
-#ifndef CONFIG_MACH_SUNIV
u32 spl_boot_device(void)
{
return sunxi_get_boot_device();
--
2.25.1
[PATCH 17/27] sunxi: spi: Add suniv pin controller support
From: George Hilliard suniv needs slightly different register settings to enable the SPI peripheral. The magic numbers are already provided by the architecture support; we just have to check for them here. Signed-off-by: George Hilliard Signed-off-by: Yifan Gu --- drivers/spi/spi-sunxi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index aa392502b7..320bd61d13 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c @@ -255,6 +255,8 @@ static int sun4i_spi_parse_pins(struct udevice *dev) if (IS_ENABLED(CONFIG_MACH_SUN50I)) sunxi_gpio_set_cfgpin(pin, SUN50I_GPC_SPI0); + else if (IS_ENABLED(CONFIG_MACH_SUNIV)) + sunxi_gpio_set_cfgpin(pin, SUNIV_GPC_SPI0); else sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0); sunxi_gpio_set_drv(pin, drive); -- 2.25.1
[PATCH 20/27] board: licheepi_nano: set CONFIG_MMC_SUNXI_SLOT_EXTRA
--- configs/licheepi_nano_defconfig | 1 + configs/licheepi_nano_spiflash_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig index 6e455baadf..6ea73c6408 100644 --- a/configs/licheepi_nano_defconfig +++ b/configs/licheepi_nano_defconfig @@ -7,3 +7,4 @@ CONFIG_DRAM_ZQ=0 CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano" CONFIG_SPL=y # CONFIG_SPL_DM_SERIAL is not set +CONFIG_MMC_SUNXI_SLOT_EXTRA=1 diff --git a/configs/licheepi_nano_spiflash_defconfig b/configs/licheepi_nano_spiflash_defconfig index 07b6a27dbe..c3b7fdd67d 100644 --- a/configs/licheepi_nano_spiflash_defconfig +++ b/configs/licheepi_nano_spiflash_defconfig @@ -23,3 +23,4 @@ CONFIG_SPL_SPI_SUNXI=y # CONFIG_SPL_DM_SERIAL is not set CONFIG_DM_SPI=y CONFIG_SUN6I_SPI=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=1 -- 2.25.1
[PATCH 21/27] sunxi: suniv: add missing header include for udelay
Signed-off-by: Yifan Gu --- arch/arm/mach-sunxi/dram_suniv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c index 40aebf6eba..e7460ec3c3 100644 --- a/arch/arm/mach-sunxi/dram_suniv.c +++ b/arch/arm/mach-sunxi/dram_suniv.c @@ -15,6 +15,7 @@ #include #include #include +#include #define SDR_T_CAS (0x2) #define SDR_T_RAS (0x8) -- 2.25.1
[PATCH 16/27] sunxi: spi: restore bus speed and mode after reset
From: George Hilliard
The sunxi SPI peripheral driver resets the device completely (disabling
clocks and power) when the bus is released and turns it back on when
claiming. On the F1C100s (and maybe others), the peripheral resets back
to default register settings, losing speed and mode settings.
Restore these settings when resetting the peripheral.
Signed-off-by: George Hilliard
Signed-off-by: Yifan Gu
---
drivers/spi/spi-sunxi.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index 4ca5d3a93a..aa392502b7 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -39,6 +39,10 @@
DECLARE_GLOBAL_DATA_PTR;
+/* Forward declarations of some reused functions */
+static int sun4i_spi_set_speed(struct udevice *dev, uint speed);
+static int sun4i_spi_set_mode(struct udevice *dev, uint mode);
+
/* sun4i spi registers */
#define SUN4I_RXDATA_REG 0x00
#define SUN4I_TXDATA_REG 0x04
@@ -304,7 +308,8 @@ err_ahb:
static int sun4i_spi_claim_bus(struct udevice *dev)
{
- struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
+ struct udevice *bus = dev->parent;
+ struct sun4i_spi_priv *priv = dev_get_priv(bus);
int ret;
ret = sun4i_spi_set_clock(dev->parent, true);
@@ -321,6 +326,9 @@ static int sun4i_spi_claim_bus(struct udevice *dev)
setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) |
SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW));
+ sun4i_spi_set_speed(bus, priv->freq);
+ sun4i_spi_set_mode(bus, priv->mode);
+
return 0;
}
--
2.25.1
[PATCH 15/27] sunxi: gpio: Add support for suniv-f1c100s
From: George Hilliard
The f1c100s has a controller pretty similar to that of most sunxi parts,
but there are only 6 banks. Add a new compatible entry for this
peripheral.
Signed-off-by: George Hilliard
Signed-off-by: Yifan Gu
---
drivers/gpio/sunxi_gpio.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 24cb604e3e..c7bdb3d3f3 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -319,6 +319,11 @@ static const struct sunxi_gpio_soc_data soc_data_a_all = {
.no_banks = SUNXI_GPIO_BANKS,
};
+static const struct sunxi_gpio_soc_data soc_data_a_6 = {
+ .start = 0,
+ .no_banks = 6,
+};
+
static const struct sunxi_gpio_soc_data soc_data_l_1 = {
.start = 'L' - 'A',
.no_banks = 1,
@@ -364,6 +369,7 @@ static const struct udevice_id sunxi_gpio_ids[] = {
ID("allwinner,sun50i-a64-r-pinctrl",l_1),
ID("allwinner,sun50i-h6-r-pinctrl", l_2),
ID("allwinner,sun50i-h616-r-pinctrl", l_1),
+ ID("allwinner,suniv-pinctrl", a_6),
{ }
};
--
2.25.1
[PATCH 14/27] sunxi: implement clock driver for suniv f1c100s
From: George Hilliard
The f1c100s has a simple clock tree similar to those of other sunxi
parts. Add support for it.
Signed-off-by: George Hilliard
Signed-off-by: Yifan Gu
---
drivers/clk/sunxi/Kconfig | 7
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_f1c100s.c | 66 +
3 files changed, 74 insertions(+)
create mode 100644 drivers/clk/sunxi/clk_f1c100s.c
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index bf084fa7a8..28928fef1f 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -9,6 +9,13 @@ config CLK_SUNXI
if CLK_SUNXI
+config CLK_SUNIV_F1C100S
+ bool "Clock driver for Allwinner F1C100s"
+ default MACH_SUNIV
+ help
+ This enables common clock driver support for platforms based
+ on Allwinner F1C100s SoC.
+
config CLK_SUN4I_A10
bool "Clock driver for Allwinner A10/A20"
default MACH_SUN4I || MACH_SUN7I
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 4f9282a8b9..da43f8a0ed 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
obj-$(CONFIG_CLK_SUNXI) += clk_sun6i_rtc.o
+obj-$(CONFIG_CLK_SUNIV_F1C100S) += clk_f1c100s.o
obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
diff --git a/drivers/clk/sunxi/clk_f1c100s.c b/drivers/clk/sunxi/clk_f1c100s.c
new file mode 100644
index 00..3b64445d89
--- /dev/null
+++ b/drivers/clk/sunxi/clk_f1c100s.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: (GPL-2.0+)
+/*
+ * Copyright (C) 2019 George Hilliard .
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static struct ccu_clk_gate f1c100s_gates[] = {
+ [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
+ [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
+ [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
+ [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
+ [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
+
+ [CLK_BUS_UART0] = GATE(0x06c, BIT(20)),
+ [CLK_BUS_UART1] = GATE(0x06c, BIT(21)),
+ [CLK_BUS_UART2] = GATE(0x06c, BIT(22)),
+
+ [CLK_USB_PHY0] = GATE(0x0cc, BIT(1)),
+};
+
+static struct ccu_reset f1c100s_resets[] = {
+ [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
+
+ [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
+ [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
+ [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
+ [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
+ [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
+
+ [RST_BUS_UART0] = RESET(0x2d0, BIT(20)),
+ [RST_BUS_UART1] = RESET(0x2d0, BIT(21)),
+ [RST_BUS_UART2] = RESET(0x2d0, BIT(22)),
+};
+
+static const struct ccu_desc f1c100s_ccu_desc = {
+ .gates = f1c100s_gates,
+ .resets = f1c100s_resets,
+};
+
+static int f1c100s_clk_bind(struct udevice *dev)
+{
+ return sunxi_reset_bind(dev, ARRAY_SIZE(f1c100s_resets));
+}
+
+static const struct udevice_id f1c100s_clk_ids[] = {
+ { .compatible = "allwinner,suniv-f1c100s-ccu",
+ .data = (ulong)&f1c100s_ccu_desc },
+ { }
+};
+
+U_BOOT_DRIVER(clk_suniv_f1c100s) = {
+ .name = "suniv_f1c100s_ccu",
+ .id = UCLASS_CLK,
+ .of_match = f1c100s_clk_ids,
+ .priv_auto = sizeof(struct ccu_priv),
+ .ops= &sunxi_clk_ops,
+ .probe = sunxi_clk_probe,
+ .bind = f1c100s_clk_bind,
+};
--
2.25.1
[PATCH 18/27] sunxi: suniv: add device tree nodes for f1c100s MMC controllers
From: George Hilliard
The f1c100s has two MMC controllers. Add device tree nodes for them.
Signed-off-by: George Hilliard
Signed-off-by: Yifan Gu
---
arch/arm/dts/suniv.dtsi | 47 +
1 file changed, 47 insertions(+)
diff --git a/arch/arm/dts/suniv.dtsi b/arch/arm/dts/suniv.dtsi
index b11d9eb57a..bea7c08e7d 100644
--- a/arch/arm/dts/suniv.dtsi
+++ b/arch/arm/dts/suniv.dtsi
@@ -125,6 +125,11 @@
pins = "PE0", "PE1";
function = "uart0";
};
+
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+ function = "mmc0";
+ };
};
timer@1c20c00 {
@@ -197,5 +202,47 @@
#phy-cells = <1>;
status = "disabled";
};
+
+ mmc0: mmc@1c0f000 {
+ compatible = "allwinner,suniv-f1c100s-mmc",
+"allwinner,sun7i-a20-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>,
+<&ccu CLK_MMC0>,
+<&ccu CLK_MMC0_OUTPUT>,
+<&ccu CLK_MMC0_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <23>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@1c1 {
+ compatible = "allwinner,suniv-f1c100s-mmc",
+"allwinner,sun7i-a20-mmc";
+ reg = <0x01c1 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>,
+<&ccu CLK_MMC1>,
+<&ccu CLK_MMC1_OUTPUT>,
+<&ccu CLK_MMC1_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <24>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
};
--
2.25.1
[PATCH 19/27] arm: dts: sunxi: do not renumber if mmc2 does not exist
We renumber mmc2 to mmc1 for sunxi devices, but if mmc2 does not exist
dts will not build.
This patch prevents that by checking CONFIG_MMC_SUNXI_SLOT_EXTRA.
---
arch/arm/dts/sunxi-u-boot.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
index 06da009fa2..53db622144 100644
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -13,7 +13,9 @@
/ {
aliases {
mmc0 = &mmc0;
+#if CONFIG_MMC_SUNXI_SLOT_EXTRA > 1
mmc1 = &mmc2;
+#endif
};
binman: binman {
--
2.25.1
RE: [PATCH v3 06/14] common: fit: Use hash.c to call CRC/SHA function
Hi Tom, > From: Tom Rini > Sent: Saturday, July 24, 2021 8:57 PM > > On Tue, Jul 20, 2021 at 02:38:31PM +0800, Chia-Wei Wang wrote: > > > From: Joel Stanley > > > > Currently the FIT verification calls directly into SW implemented > > functions to get a CRC/SHA/MD5 hash. > > > > This patch removes duplcated algorithm lookup and use hash_lookup_algo > > to get the hashing function with HW accelearation supported if > > configured. > > > > The MD5 direct call remains as it is not included in the hash lookup > > table of hash.c. > > > > Signed-off-by: Joel Stanley > > Signed-off-by: Chia-Wei Wang > > While this is a good idea, there's some required prep work. At least the > following platforms don't compile due to this patch: > ls1046ardb_qspi imx8mm_beacon imx8mn_beacon imx8mn_beacon_2g > imx8mm-icore-mx8mm-ctouch2 imx8mm-icore-mx8mm-edimm2.2 > imx8mm_evk imx8mn_ddr4_evk imx8mn_evk imx8mp_evk imx8mq_evk > imx8mm_venice imx8mq_phanbell phycore-imx8mm phycore-imx8mp > pico-imx8mq verdin-imx8mm mt8183_pumpkin mt8516_pumpkin mscc_jr2 > mscc_luton mscc_ocelot mscc_serval mscc_servalt mt7620_mt7530_rfb > mt7620_rfb mt7628_rfb > > Which is likely due to cases where HASH or SPL_HASH_SUPPORT are not being > selected as it was not previously required. > Thanks for the notification of this error. I will examine the code flow to figure out the root cause on these platforms. Meanwhile, Simon also suggested the need to add a new UCLASS_HASH to refactor the hash structure. http://patchwork.ozlabs.org/project/uboot/patch/20210720063839.1518-4-chiawei_w...@aspeedtech.com/ I was wondering if I can prepare another leading patch for UCLASS_HASH and also to make sure the current codebase works fine? After that, we can restart this patch series for Aspeed FIT booting. Regards, Chiawei
Re: [PATCH] dtoc: Check that a parent is not missing
Hi Simon,
Thanks for the patch, it will be a nice way to spot errors and avoid
headaches!
On 7/7/21 8:22 AM, Simon Glass wrote:
With of-platdata-inst we want to set up a reference to each devices'
parent device, if there is one. If we find that the device has a parent
(i.e. is not a root node) but it is not in the list of devices being
written, then we cannot create the reference.
Report an error in this case, since it indicates that the parent node
is either missing a compatible string, is disabled, or perhaps does not
have any properties because it was not tagged for SPL.
Signed-off-by: Simon Glass
---
tools/dtoc/dtb_platdata.py | 9
tools/dtoc/test/dtoc_test_noparent.dts | 32 ++
tools/dtoc/test_dtoc.py| 10
3 files changed, 51 insertions(+)
create mode 100644 tools/dtoc/test/dtoc_test_noparent.dts
diff --git a/tools/dtoc/dtb_platdata.py b/tools/dtoc/dtb_platdata.py
index 2d42480a9a5..a951a5a2264 100644
--- a/tools/dtoc/dtb_platdata.py
+++ b/tools/dtoc/dtb_platdata.py
@@ -749,6 +749,15 @@ class DtbPlatdata():
break
if node.parent and node.parent.parent:
+if node.parent not in self._valid_nodes:
+# This might indicate that the parent node is not in the
+# SPL/TPL devicetree but the child is. For example if we are
+# dealing with of-platdata in TPL, the parent has a
+# u-boot,dm-spl tag but the child has u-boot,dm-pre-reloc. In
+# this case the child node exists in TPL but the parent does
+# not.
+raise ValueError("Node '%s' requires parent node '%s' but it is not
in the valid list" %
+ (node.path, node.parent.path))
self.buf('\t.parent\t\t= DM_DEVICE_REF(%s),\n' %
node.parent.var_name)
if priv_name:
diff --git a/tools/dtoc/test/dtoc_test_noparent.dts
b/tools/dtoc/test/dtoc_test_noparent.dts
new file mode 100644
index 000..5a820301e72
--- /dev/null
+++ b/tools/dtoc/test/dtoc_test_noparent.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test device tree file for dtoc
+ *
+ * Copyright 2017 Google, Inc
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ i2c@0 {
+ compatible = "sandbox,i2c";
+ u-boot,dm-pre-tpl;
Does u-boot,dm-pre-tpl exists? Probably I'm missing something here but I
was expecting u-boot,dm-spl.
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spl-test {
+ u-boot,dm-pre-reloc;
+ compatible = "sandbox,spl-test";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ pmic@9 {
+ compatible = "sandbox,pmic";
+ u-boot,dm-pre-reloc;
+ reg = <9>;
+ low-power;
+ };
+ };
+ };
+};
diff --git a/tools/dtoc/test_dtoc.py b/tools/dtoc/test_dtoc.py
index 0b2805feed2..863ede90b7a 100755
--- a/tools/dtoc/test_dtoc.py
+++ b/tools/dtoc/test_dtoc.py
@@ -1830,3 +1830,13 @@ U_BOOT_DRVINFO(spl_test2) = {
dtb_file = get_dtb_file('dtoc_test_single_reg.dts')
output = tools.GetOutputFilename('output')
self.run_test(['struct'], dtb_file, output)
+
+def test_missing_parent(self):
+"""Test detection of a parent node with no properties"""
+dtb_file = get_dtb_file('dtoc_test_noparent.dts', capture_stderr=True)
+output = tools.GetOutputFilename('output')
+with self.assertRaises(ValueError) as exc:
+self.run_test(['device'], dtb_file, output, instantiate=True)
+self.assertIn("Node '/i2c@0/spl-test/pmic@9' requires parent node "
+ "'/i2c@0/spl-test' but it is not in the valid list",
+ str(exc.exception))
Regards,
Walter
Re: [PATCH 19/27] arm: dts: sunxi: do not renumber if mmc2 does not exist
在 2021-07-25星期日的 19:16 -0400，Yifan Gu写道：
> We renumber mmc2 to mmc1 for sunxi devices, but if mmc2 does not exist
> dts will not build.
>
> This patch prevents that by checking CONFIG_MMC_SUNXI_SLOT_EXTRA.
I have a similar patch at
https://patchwork.ozlabs.org/project/uboot/patch/20210722063015.421923-3-icen...@sipeed.com/
> ---
> arch/arm/dts/sunxi-u-boot.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-
> boot.dtsi
> index 06da009fa2..53db622144 100644
> --- a/arch/arm/dts/sunxi-u-boot.dtsi
> +++ b/arch/arm/dts/sunxi-u-boot.dtsi
> @@ -13,7 +13,9 @@
> / {
> aliases {
> mmc0 = &mmc0;
> +#if CONFIG_MMC_SUNXI_SLOT_EXTRA > 1
> mmc1 = &mmc2;
> +#endif
> };
>
> binman: binman {
Re: [PATCH v3 06/14] common: fit: Use hash.c to call CRC/SHA function
On Mon, Jul 26, 2021 at 12:06:28AM +, ChiaWei Wang wrote: > Hi Tom, > > > From: Tom Rini > > Sent: Saturday, July 24, 2021 8:57 PM > > > > On Tue, Jul 20, 2021 at 02:38:31PM +0800, Chia-Wei Wang wrote: > > > > > From: Joel Stanley > > > > > > Currently the FIT verification calls directly into SW implemented > > > functions to get a CRC/SHA/MD5 hash. > > > > > > This patch removes duplcated algorithm lookup and use hash_lookup_algo > > > to get the hashing function with HW accelearation supported if > > > configured. > > > > > > The MD5 direct call remains as it is not included in the hash lookup > > > table of hash.c. > > > > > > Signed-off-by: Joel Stanley > > > Signed-off-by: Chia-Wei Wang > > > > While this is a good idea, there's some required prep work. At least the > > following platforms don't compile due to this patch: > > ls1046ardb_qspi imx8mm_beacon imx8mn_beacon imx8mn_beacon_2g > > imx8mm-icore-mx8mm-ctouch2 imx8mm-icore-mx8mm-edimm2.2 > > imx8mm_evk imx8mn_ddr4_evk imx8mn_evk imx8mp_evk imx8mq_evk > > imx8mm_venice imx8mq_phanbell phycore-imx8mm phycore-imx8mp > > pico-imx8mq verdin-imx8mm mt8183_pumpkin mt8516_pumpkin mscc_jr2 > > mscc_luton mscc_ocelot mscc_serval mscc_servalt mt7620_mt7530_rfb > > mt7620_rfb mt7628_rfb > > > > Which is likely due to cases where HASH or SPL_HASH_SUPPORT are not being > > selected as it was not previously required. > > > > Thanks for the notification of this error. I will examine the code flow to > figure out the root cause on these platforms. > > Meanwhile, Simon also suggested the need to add a new UCLASS_HASH to refactor > the hash structure. > http://patchwork.ozlabs.org/project/uboot/patch/20210720063839.1518-4-chiawei_w...@aspeedtech.com/ > > I was wondering if I can prepare another leading patch for UCLASS_HASH and > also to make sure the current codebase works fine? > After that, we can restart this patch series for Aspeed FIT booting. OK, sounds like a good plan, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v6 0/5] of-platdata: Avoid building libfdt
Hi Tom, On Sun, 25 Jul 2021 at 14:32, Tom Rini wrote: > > On Sun, Jul 25, 2021 at 10:13:42AM -0600, Simon Glass wrote: > > > The original patch of this series was sent in September 2019 but > > unfortunately caused build problems on some boards, since they don't > > comply with the of-platdata rules. > > > > With of-platdata, the idea is to compile the device tree into C structures > > to save space and avoid needing to use libfdt. But some boards use > > of-platdata while also using libfdt in a few areas, thus defeating the > > purpose of of-platdata. > > > > This series includes the original two patches > > > >http://patchwork.ozlabs.org/patch/1167420/ > >http://patchwork.ozlabs.org/patch/1167367/ > > > > as well as a few other patches to fix the build errors. Overall this > > reduces code size and provides better error messages when unavailable > > functions are used. > > > > Board maintainers should still take a look at the result, adjusting the > > of-platdata support as needed. > > > > Note: This series was resent a year ago but not applied. Since then, some > > boards have ended up using drivers in SPL which require OF_CONTROL, but > > SPL_OF_CONTROL is not enabled. So now we have two problems. This series > > fixes that one also. > > > > The problems will keep getting worse if people are not aware that > > something is wrong. Therefore I think this patch series should be applied > > ASAP. > > OK, so I took 5/6 and 6/6 and fired off a build. The only fails-to-link > now are: > am335x_boneblack_vboot am335x_evm am335x_evm_spiboot > > So are all of the other problems still present? I'm going to look in to > the am335x failures. I got a passing build here: https://source.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/8398 I am wondering if I did something wrong when sending? Regards, SImon
RE: [PATCH 1/7] mmc: sdhci: Return error in case of failure
Hi Jaehoon,
Thanks for the review.
> -Original Message-
> From: Jaehoon Chung
> Sent: Monday, July 26, 2021 3:18 AM
> To: Ashok Reddy Soma ; u-boot@lists.denx.de
> Cc: peng@nxp.com; faiz_ab...@ti.com; s...@chromium.org;
> mich...@walle.cc; git ; mon...@monstr.eu;
> somaashokre...@gmail.com; T Karthik Reddy
> Subject: Re: [PATCH 1/7] mmc: sdhci: Return error in case of failure
>
> Hi Ashok,
>
> On 7/24/21 5:10 PM, Ashok Reddy Soma wrote:
> > From: T Karthik Reddy
> >
> > set_delay() function is from sdhci host ops, which does not return any
> > error due to void return type. Get return values from input and output
> > set clock phase functions inside arasan_sdhci_set_tapdelay() and
> > return the errors.
> >
> > Change return type to int for arasan_sdhci_set_tapdelay() and also for
> > set_delay() in sdhci_ops structure.
>
> Could you separate the patch to sdhci and zync_sdhci part?
Sure, i will split in to two patches.
>
> >
> > Signed-off-by: T Karthik Reddy
> > Signed-off-by: Ashok Reddy Soma
> > ---
> >
> > drivers/mmc/sdhci.c | 8 ++--
> > drivers/mmc/zynq_sdhci.c | 21 -
> > include/sdhci.h | 2 +-
> > 3 files changed, 23 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index
> > d9ab6a0a83..f144602eec 100644
> > --- a/drivers/mmc/sdhci.c
> > +++ b/drivers/mmc/sdhci.c
> > @@ -366,6 +366,7 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int
> > clock) {
> > struct sdhci_host *host = mmc->priv;
> > unsigned int div, clk = 0, timeout;
> > + int ret;
> >
> > /* Wait max 20 ms */
> > timeout = 200;
> > @@ -386,8 +387,11 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int
> clock)
> > if (clock == 0)
> > return 0;
> >
> > - if (host->ops && host->ops->set_delay)
> > - host->ops->set_delay(host);
> > + if (host->ops && host->ops->set_delay) {
> > + ret = host->ops->set_delay(host);
> > + if (ret)
> > + return ret;
>
> how about adding debug(). It's helpful to debug when it's failed.
Ok, I will add a debug print here.
Any comments for other patches in this series or shall I send V2 with these
changes ?
Thanks,
Ashok
>
> Best Regards,
> Jaehoon Chung
>
> > + }
> >
> > if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
> > /*
> > diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index
> > ba87ee8dd5..9fb3603c7e 100644
> > --- a/drivers/mmc/zynq_sdhci.c
> > +++ b/drivers/mmc/zynq_sdhci.c
> > @@ -422,7 +422,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
> sdhci_host *host,
> > return 0;
> > }
> >
> > -static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
> > +static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
> > {
> > struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
> > struct arasan_sdhci_clk_data *clk_data = &priv->clk_data; @@ -431,18
> > +431,29 @@ static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
> > u8 timing = mode2timing[mmc->selected_mode];
> > u32 iclk_phase = clk_data->clk_phase_in[timing];
> > u32 oclk_phase = clk_data->clk_phase_out[timing];
> > + int ret;
> >
> > dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name,
> > timing);
> >
> > if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
> > device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
> > - sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
> > - sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
> > + ret = sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
> > + if (ret)
> > + return ret;
> > + ret = sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
> > + if (ret)
> > + return ret;
> > } else if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
> >device_is_compatible(dev, "xlnx,versal-8.9a")) {
> > - sdhci_versal_sampleclk_set_phase(host, iclk_phase);
> > - sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
> > + ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase);
> > + if (ret)
> > + return ret;
> > + ret = sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
> > + if (ret)
> > + return ret;
> > }
> > +
> > + return 0;
> > }
> >
> > static void arasan_dt_read_clk_phase(struct udevice *dev, unsigned
> > char timing, diff --git a/include/sdhci.h b/include/sdhci.h index
> > 0ae9471ad7..44a0d84e5a 100644
> > --- a/include/sdhci.h
> > +++ b/include/sdhci.h
> > @@ -268,7 +268,7 @@ struct sdhci_ops {
> > int (*set_ios_post)(struct sdhci_host *host);
> > void(*set_clock)(struct sdhci_host *host, u32 div);
> > int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
> > - void (*set_delay)(struct sdhci_host *host);
> > + int (*set_delay)(struct sdhci_host *host);
> > int (*deferr
Re: [PATCH 1/7] mmc: sdhci: Return error in case of failure
Hi Ashok,
On 7/26/21 2:33 PM, Ashok Reddy Soma wrote:
> Hi Jaehoon,
>
> Thanks for the review.
>
>> -Original Message-
>> From: Jaehoon Chung
>> Sent: Monday, July 26, 2021 3:18 AM
>> To: Ashok Reddy Soma ; u-boot@lists.denx.de
>> Cc: peng@nxp.com; faiz_ab...@ti.com; s...@chromium.org;
>> mich...@walle.cc; git ; mon...@monstr.eu;
>> somaashokre...@gmail.com; T Karthik Reddy
>> Subject: Re: [PATCH 1/7] mmc: sdhci: Return error in case of failure
>>
>> Hi Ashok,
>>
>> On 7/24/21 5:10 PM, Ashok Reddy Soma wrote:
>>> From: T Karthik Reddy
>>>
>>> set_delay() function is from sdhci host ops, which does not return any
>>> error due to void return type. Get return values from input and output
>>> set clock phase functions inside arasan_sdhci_set_tapdelay() and
>>> return the errors.
>>>
>>> Change return type to int for arasan_sdhci_set_tapdelay() and also for
>>> set_delay() in sdhci_ops structure.
>>
>> Could you separate the patch to sdhci and zync_sdhci part?
> Sure, i will split in to two patches.
>>
>>>
>>> Signed-off-by: T Karthik Reddy
>>> Signed-off-by: Ashok Reddy Soma
>>> ---
>>>
>>> drivers/mmc/sdhci.c | 8 ++--
>>> drivers/mmc/zynq_sdhci.c | 21 -
>>> include/sdhci.h | 2 +-
>>> 3 files changed, 23 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index
>>> d9ab6a0a83..f144602eec 100644
>>> --- a/drivers/mmc/sdhci.c
>>> +++ b/drivers/mmc/sdhci.c
>>> @@ -366,6 +366,7 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int
>>> clock) {
>>> struct sdhci_host *host = mmc->priv;
>>> unsigned int div, clk = 0, timeout;
>>> + int ret;
>>>
>>> /* Wait max 20 ms */
>>> timeout = 200;
>>> @@ -386,8 +387,11 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int
>> clock)
>>> if (clock == 0)
>>> return 0;
>>>
>>> - if (host->ops && host->ops->set_delay)
>>> - host->ops->set_delay(host);
>>> + if (host->ops && host->ops->set_delay) {
>>> + ret = host->ops->set_delay(host);
>>> + if (ret)
>>> + return ret;
>>
>> how about adding debug(). It's helpful to debug when it's failed.
>
> Ok, I will add a debug print here.
>
> Any comments for other patches in this series or shall I send V2 with these
> changes ?
I didn't see other patch yet. Sorry.
After checked other patch, I will reply ASAP.
Best Regards,
Jaehoon Chung
>
> Thanks,
> Ashok
>>
>> Best Regards,
>> Jaehoon Chung
>>
>>> + }
>>>
>>> if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
>>> /*
>>> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index
>>> ba87ee8dd5..9fb3603c7e 100644
>>> --- a/drivers/mmc/zynq_sdhci.c
>>> +++ b/drivers/mmc/zynq_sdhci.c
>>> @@ -422,7 +422,7 @@ static int sdhci_versal_sampleclk_set_phase(struct
>> sdhci_host *host,
>>> return 0;
>>> }
>>>
>>> -static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
>>> +static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
>>> {
>>> struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
>>> struct arasan_sdhci_clk_data *clk_data = &priv->clk_data; @@ -431,18
>>> +431,29 @@ static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
>>> u8 timing = mode2timing[mmc->selected_mode];
>>> u32 iclk_phase = clk_data->clk_phase_in[timing];
>>> u32 oclk_phase = clk_data->clk_phase_out[timing];
>>> + int ret;
>>>
>>> dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name,
>>> timing);
>>>
>>> if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
>>> device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
>>> - sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
>>> - sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
>>> + ret = sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
>>> + if (ret)
>>> + return ret;
>>> + ret = sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
>>> + if (ret)
>>> + return ret;
>>> } else if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
>>>device_is_compatible(dev, "xlnx,versal-8.9a")) {
>>> - sdhci_versal_sampleclk_set_phase(host, iclk_phase);
>>> - sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
>>> + ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase);
>>> + if (ret)
>>> + return ret;
>>> + ret = sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
>>> + if (ret)
>>> + return ret;
>>> }
>>> +
>>> + return 0;
>>> }
>>>
>>> static void arasan_dt_read_clk_phase(struct udevice *dev, unsigned
>>> char timing, diff --git a/include/sdhci.h b/include/sdhci.h index
>>> 0ae9471ad7..44a0d84e5a 100644
>>> --- a/include/sdhci.h
>>> +++ b/include/sdhci.h
>>> @@ -268,7 +268,7 @@ struct sdhci_ops {
>>> int (*set_ios_post)(struct sdhci_host *host);
>>> void(*set_clock)(struct sdhci_host *h
[PATCH 0/3] Convert the Dreamplug Ethernet and SATA to Driver Model.
- Enable DM SATA, removed IDE driver, add SATA MV driver. - Use Ethernet PHY names from device tree. - Replace the old Ethernet PHY addr lookup with a device tree parsing lookup function. Tony Dinh (3): arm: kirkwood: Dreamplug: Add DM Ethernet and DM SATA configs arm: kirkwood: Dreamplug: Use Ethernet PHY name and address from device tree arm: kirkwood: Dreamplug: Add DM SATA and remove IDE configs board/Marvell/dreamplug/dreamplug.c | 62 ++--- configs/dreamplug_defconfig | 4 ++ include/configs/dreamplug.h | 12 +- 3 files changed, 62 insertions(+), 16 deletions(-) -- 2.20.1
[PATCH 1/3] arm: kirkwood: Dreamplug: Add DM Ethernet and DM SATA configs
Add DM_ETH, SATA_MV and associated configs to dreamplug_defconfig Signed-off-by: Tony Dinh --- configs/dreamplug_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index 8956d2f3c5..516e28752c 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -51,3 +51,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y +CONFIG_DM_ETH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CMD_SATA=y +CONFIG_SATA_MV=y -- 2.20.1
[PATCH 2/3] arm: kirkwood: Dreamplug: Use Ethernet PHY name and address from device tree
In DM Ethernet, the old "egiga0" and 'egiga1" names are no longer valid,
so replace these with Ethernet PHY names from device tree. Also, read
Ethernet PHY address for each port from device tree.
Signed-off-by: Tony Dinh
---
board/Marvell/dreamplug/dreamplug.c | 62 ++---
1 file changed, 48 insertions(+), 14 deletions(-)
diff --git a/board/Marvell/dreamplug/dreamplug.c
b/board/Marvell/dreamplug/dreamplug.c
index e1c64b5224..d5b6b22ddf 100644
--- a/board/Marvell/dreamplug/dreamplug.c
+++ b/board/Marvell/dreamplug/dreamplug.c
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
+ * Copyright (C) 2021 Tony Dinh
* (C) Copyright 2011
* Jason Cooper
*
@@ -97,42 +98,75 @@ int board_init(void)
return 0;
}
+static int fdt_get_phy_addr(const char *path)
+{
+ const void *fdt = gd->fdt_blob;
+ const u32 *reg;
+ const u32 *val;
+ int node, phandle, addr;
+
+ /* Find the node by its full path */
+ node = fdt_path_offset(fdt, path);
+ if (node >= 0) {
+ /* Look up phy-handle */
+ val = fdt_getprop(fdt, node, "phy-handle", NULL);
+ if (val) {
+ phandle = fdt32_to_cpu(*val);
+ if (!phandle)
+ return -1;
+ /* Follow it to its node */
+ node = fdt_node_offset_by_phandle(fdt, phandle);
+ if (node) {
+ /* Look up reg */
+ reg = fdt_getprop(fdt, node, "reg", NULL);
+ if (reg) {
+ addr = fdt32_to_cpu(*reg);
+ return addr;
+ }
+ }
+ }
+ }
+ return -1;
+}
+
#ifdef CONFIG_RESET_PHY_R
-void mv_phy_88e1116_init(char *name)
+void mv_phy_88e1116_init(const char *name, const char *path)
{
u16 reg;
- u16 devadr;
+ int phyaddr;
if (miiphy_set_current_dev(name))
return;
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..%s could not read PHY dev address\n",
- __func__);
+ phyaddr = fdt_get_phy_addr(path);
+ if (phyaddr < 0)
return;
- }
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
+ miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL2_REG, ®);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+ miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL2_REG, reg);
+ miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
/* reset the phy */
- miiphy_reset(name, devadr);
+ miiphy_reset(name, phyaddr);
printf("88E1116 Initialized on %s\n", name);
}
void reset_phy(void)
{
+ char *eth0_name = "ethernet-controller@72000";
+ char *eth0_path =
"/ocp@f100/ethernet-controller@72000/ethernet0-port@0";
+ char *eth1_name = "ethernet-controller@76000";
+ char *eth1_path =
"/ocp@f100/ethernet-controller@72000/ethernet1-port@0";
+
/* configure and initialize both PHY's */
- mv_phy_88e1116_init("egiga0");
- mv_phy_88e1116_init("egiga1");
+ mv_phy_88e1116_init(eth0_name, eth0_path);
+ mv_phy_88e1116_init(eth1_name, eth1_path);
}
#endif /* CONFIG_RESET_PHY_R */
--
2.20.1
[PATCH 3/3] arm: kirkwood: Dreamplug: Add DM SATA and remove IDE configs
- Enable DM SATA, removed IDE driver, and add SATA MV driver.
- Use ethernet PHY names from device tree in default boot command
Signed-off-by: Tony Dinh
---
include/configs/dreamplug.h | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h
index 9106203ebc..65962ee733 100644
--- a/include/configs/dreamplug.h
+++ b/include/configs/dreamplug.h
@@ -31,8 +31,8 @@
/*
* Default environment variables
*/
-#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \
- "${x_bootcmd_ethernet}; setenv ethact egiga1; " \
+#define CONFIG_BOOTCOMMAND "setenv ethact
ethernet-controller@72000; " \
+ "${x_bootcmd_ethernet}; setenv ethact ethernet-controller@76000; " \
"${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; "\
"bootm 0x640;"
@@ -52,4 +52,12 @@
#define CONFIG_PHY_BASE_ADR0
#endif /* CONFIG_CMD_NET */
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_LBA48
+#endif /* CONFIG_SATA */
+
#endif /* _CONFIG_DREAMPLUG_H */
--
2.20.1
RE: [PATCH] configs: layerscape: Disable the EFI_LOADER feature
Hi Tom,
> -Original Message-
> From: Tom Rini
> Sent: 2021年7月22日 23:26
> To: Z.Q. Hou ; Michael Walle ;
> Heinrich Schuchardt
> Cc: u-boot@lists.denx.de; Priyanka Jain
> Subject: Re: [PATCH] configs: layerscape: Disable the EFI_LOADER feature
>
> On Thu, Jul 22, 2021 at 02:25:59PM +0800, Zhiqiang Hou wrote:
>
> > From: Hou Zhiqiang
> >
> > The feature BOOTENV_SHARED_EFI is not supported on layerscape boards,
> > it didn't result kernel boot crash previously since there isn't the
> > efi/boot/"BOOTEFI_NAME" and it skip calling of 'boot_efi_binary'.
> >
> > But since the commit f3866909e350 ("distro_bootcmd: call EFI bootmgr
> > even without having /EFI/boot"), it will cause kernel boot crash as
> > there isn't a valid fdt_addr and it finially uses the device tree blob
> > of U-Boot and further cause errors.
> >
> > As this feature is enabled by default for armv7 and armv8, so disable
> > it explicitly to avoid calling the 'scan_dev_for_efi'.
>
> I'm not thrilled with this. Why isn't the solution to get and keep in sync
> the
> device trees, so that the tree U-Boot has is valid for the kernel? I'm also
> open to discussing f3866909e350 more. But I'm really opposed to disabling
> EFI_LOADER on modern platforms as that will make adoption of U-Boot in
> device harder I feel.
>
I think it doesn't make sense for the platforms on which the EFI boot is not
planed.
As there isn't EFI boot needed components in the search path, finally the EFI
boot
will be skipped. I don't want to look into the EFI boot process, so I trend to
disable
the feature, is it acceptable?
Thanks,
Zhiqiang
> --
> Tom
Re: [PATCH] configs: layerscape: Disable the EFI_LOADER feature
Am 2021-07-26 08:18, schrieb Z.Q. Hou:
Hi Tom,
-Original Message-
From: Tom Rini
Sent: 2021年7月22日 23:26
To: Z.Q. Hou ; Michael Walle ;
Heinrich Schuchardt
Cc: u-boot@lists.denx.de; Priyanka Jain
Subject: Re: [PATCH] configs: layerscape: Disable the EFI_LOADER
feature
On Thu, Jul 22, 2021 at 02:25:59PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> The feature BOOTENV_SHARED_EFI is not supported on layerscape boards,
> it didn't result kernel boot crash previously since there isn't the
> efi/boot/"BOOTEFI_NAME" and it skip calling of 'boot_efi_binary'.
>
> But since the commit f3866909e350 ("distro_bootcmd: call EFI bootmgr
> even without having /EFI/boot"), it will cause kernel boot crash as
> there isn't a valid fdt_addr and it finially uses the device tree blob
> of U-Boot and further cause errors.
>
> As this feature is enabled by default for armv7 and armv8, so disable
> it explicitly to avoid calling the 'scan_dev_for_efi'.
I'm not thrilled with this. Why isn't the solution to get and keep in
sync the
device trees, so that the tree U-Boot has is valid for the kernel?
I'm also
open to discussing f3866909e350 more. But I'm really opposed to
disabling
EFI_LOADER on modern platforms as that will make adoption of U-Boot in
device harder I feel.
I think it doesn't make sense for the platforms on which the EFI boot
is not planed.
As there isn't EFI boot needed components in the search path, finally
the EFI boot
will be skipped. I don't want to look into the EFI boot process, so I
trend to disable
the feature, is it acceptable?
Actually, from a customer point of view, this is really annoying. These
platforms should be reference implenention and you're skipping an
important feature, that is booting a generic linux distribution.
Anyway, I don't understand why the efi bootmgr boots on your board
at all. AFAIK it needs the BootOrder/BootNext EFI variables, no?
-michael
Re: [PATCH 1/2] riscv: provide missing base extension functions
On Tue, Jul 20, 2021 at 04:28:34AM +0800, Heinrich Schuchardt wrote: > Provide library functions to read: > > * SBI implementation version > * machine vendor ID > * machine architecture ID > * machine implementation ID > > Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang
