[PATCH] scmi: correctly configure MMU for SCMI buffer

[Patrick Delaunay]

Align the MMU area for SCMI shared buffer on section size;
use the ALIGN macro in mmu_set_region_dcache_behaviour call.

Since commit d877f8fd0f09 ("arm: provide a function for boards init
code to modify MMU virtual-physical map") the parameter of
mmu_set_region_dcache_behaviour need to be MMU_SECTION_SIZE
aligned.

Fixes: 240720e9052f ("firmware: scmi: mailbox/smt agent device")
Signed-off-by: Patrick Delaunay 
---

 drivers/firmware/scmi/smt.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/firmware/scmi/smt.c b/drivers/firmware/scmi/smt.c
index d25478796a..3c41013bca 100644
--- a/drivers/firmware/scmi/smt.c
+++ b/drivers/firmware/scmi/smt.c
@@ -54,8 +54,10 @@ int scmi_dt_get_smt_buffer(struct udevice *dev, struct 
scmi_smt *smt)
 
 #ifdef CONFIG_ARM
if (dcache_status())
-   mmu_set_region_dcache_behaviour((uintptr_t)smt->buf,
-   smt->size, DCACHE_OFF);
+   mmu_set_region_dcache_behaviour(ALIGN_DOWN((uintptr_t)smt->buf, 
MMU_SECTION_SIZE),
+   ALIGN(smt->size, 
MMU_SECTION_SIZE),
+   DCACHE_OFF);
+
 #endif
 
return 0;
-- 
2.17.1

Re: [PATCH u-boot] regmap: fix a serious pointer casting bug

[Bin Meng]

Hi Simon,

On Tue, Mar 16, 2021 at 2:10 PM Simon Glass  wrote:
>
> Hello Marek,
>
> On 03.03.21 14:15, Marek Behún wrote:
> > There is a serious bug in regmap_read() and regmap_write() functions
> > where an uint pointer is cast to (void *) which is then cast to (u8 *),
> > (u16 *), (u32 *) or (u64 *), depending on register width of the map.
> >
> > For example given a regmap with 16-bit register width the code
> >   int val = 0x1234;
> >   regmap_read(map, 0, &val);
> > only changes the lower 16 bits of val on little-endian machines.
> > The upper 16 bits will remain 0x1234.
> >
> > Nobody noticed this probably because this bug can be triggered with
> > regmap_write() only on big-endian architectures (which are not used by
> > many people anymore), and on little endian this bug has consequences
> > only if register width is 8 or 16 bits and also the memory place to
> > which regmap_read() should store it's result has non-zero upper bits,
> > which it seems doesn't happen anywhere in U-Boot normally. CI managed to
> > trigger this bug in unit test of dm_test_devm_regmap_field when compiled
> > for sandbox_defconfig using LTO.
> >
> > Fix this simply by taking into account that regmap_raw_read() and
> > regmap_raw_write() behave as if the data given to these functions were
> > in little-endian format, i.e. use cpu_to_le32() / le32_to_cpu(). In
> > regmap_read() also zero out the space so that we don't get invalid
> > result if regmap_raw_read() does not fill the whole object.
> >
> > Signed-off-by: Marek Behún 
> > ---
> >  drivers/core/regmap.c | 13 -
> >  1 file changed, 12 insertions(+), 1 deletion(-)
>
> Good catch, thanks!
>
> Reviewed-by: Heiko Schocher 
>
> bye,
> Heiko
> --
> DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: h...@denx.de
>
> Applied to u-boot-dm/next, thanks!

This patch is included in the LTO series.

Regards,
Bin

Re: [PATCH] doc: icicle: Fix incorrect board name in HSS docs

[Heinrich Schuchardt]

On 11.03.21 02:48, Sean Anderson wrote:
> The HSS source uses an "mpfs" prefix with the icicle board name. Change our
> documentation to match.
>
> Signed-off-by: Sean Anderson 
> ---
>
>  doc/board/microchip/mpfs_icicle.rst | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/doc/board/microchip/mpfs_icicle.rst 
> b/doc/board/microchip/mpfs_icicle.rst
> index c71c2f3cab..cd18472542 100644
> --- a/doc/board/microchip/mpfs_icicle.rst
> +++ b/doc/board/microchip/mpfs_icicle.rst
> @@ -63,15 +63,15 @@ Build the HSS (Hart Software Services) - Microchip 
> boot-flow
>
>  .. code-block:: none
>
> -   make BOARD=icicle-kit-es config
> +   make BOARD=mpfs-icicle-kit-es config
>
>  Alternatively, copy the default config for Microchip boot-flow.
>
>  .. code-block:: none
>
> -   cp boards/icicle-kit-es/def_config .config
> +   cp boards/mpfs-icicle-kit-es/def_config .config

The directory boards/mpfs-icicle-kit-es does not exist.
defconfigs should only exist in configs

The only defconfig for icicle is

configs/microchip_mpfs_icicle_defconfig

Best regards

Heinrich

>
> -2. make BOARD=icicle-kit-es
> +2. make BOARD=mpfs-icicle-kit-es
>  3. In the Default subdirectory, the standard build will create hss.elf and
> various binary formats (hss.hex and hss.bin).
>
>

Re: [PATCH u-boot v2.1 38/38] ARM: enable LTO for some boards

[Marek Behun]

On Mon, 15 Mar 2021 21:12:32 -0400
Tom Rini  wrote:

> On Mon, Mar 15, 2021 at 10:42:31AM +0100, Marek Behun wrote:
> > On Fri, 12 Mar 2021 15:47:12 -0500
> > Tom Rini  wrote:
> >   
> > > On Fri, Mar 12, 2021 at 06:36:05PM +0100, Marek Behun wrote:  
> > > > On Fri, 12 Mar 2021 18:19:08 +0100
> > > > Heinrich Schuchardt  wrote:
> > > > 
> > > > > On 12.03.21 18:03, Marek Behun wrote:
> > > > > > On Fri, 12 Mar 2021 08:34:41 -0800
> > > > > > Tim Harvey  wrote:
> > > > > >  
> > > > > >> On Fri, Mar 12, 2021 at 5:47 AM Marek Behún  
> > > > > >> wrote:  
> > > > > >>>
> > > > > >>> Enable LTO for some boards that were tested by people on U-Boot 
> > > > > >>> Mailing
> > > > > >>> List.
> > > > > >>>
> > > > > >>> Signed-off-by: Marek Behún 
> > > > > >>> Tested-by: Adam Ford 
> > > > > >>> Tested-by: Pali Rohár 
> > > > > >>> Tested-by: Tim Harvey 
> > > > > >>> ---
> > > > > >>>  configs/am3517_evm_defconfig  | 1 +
> > > > > >>>  configs/da850evm_defconfig| 1 +
> > > > > >>>  configs/da850evm_direct_nor_defconfig | 1 +
> > > > > >>>  configs/da850evm_nand_defconfig   | 1 +
> > > > > >>>  configs/imx6q_logic_defconfig | 1 +
> > > > > >>>  configs/imx8mm_beacon_defconfig   | 1 +
> > > > > >>>  configs/imx8mm_venice_defconfig   | 1 +
> > > > > >>>  configs/imx8mn_beacon_2g_defconfig| 1 +
> > > > > >>>  configs/imx8mn_beacon_defconfig   | 1 +
> > > > > >>>  configs/nokia_rx51_defconfig  | 1 +
> > > > > >>>  configs/omap3_logic_defconfig | 1 +
> > > > > >>>  configs/r8a774a1_beacon_defconfig | 1 +
> > > > > >>>  configs/r8a774b1_beacon_defconfig | 1 +
> > > > > >>>  configs/r8a774e1_beacon_defconfig | 1 +
> > > > > >>>  configs/turris_mox_defconfig  | 1 +
> > > > > >>>  configs/turris_omnia_defconfig| 1 +
> > > > > >>>  16 files changed, 16 insertions(+)
> > > > > >>>
> > > > > >>> diff --git a/configs/am3517_evm_defconfig 
> > > > > >>> b/configs/am3517_evm_defconfig
> > > > > >>> index bae0e0af35..d61eec94a4 100644
> > > > > >>> --- a/configs/am3517_evm_defconfig
> > > > > >>> +++ b/configs/am3517_evm_defconfig
> > > > > >>> @@ -1,3 +1,4 @@
> > > > > >>> +CONFIG_LTO=y
> > > > > >>>  CONFIG_ARM=y
> > > > > >>>  # CONFIG_SPL_USE_ARCH_MEMCPY is not set
> > > > > >>>  # CONFIG_SPL_USE_ARCH_MEMSET is not set
> > > > > >>> diff --git a/configs/da850evm_defconfig 
> > > > > >>> b/configs/da850evm_defconfig
> > > > > >>> index 26e76a2929..6ff5e21bc6 100644
> > > > > >>> --- a/configs/da850evm_defconfig
> > > > > >>> +++ b/configs/da850evm_defconfig
> > > > > >>> @@ -1,3 +1,4 @@
> > > > > >>> +CONFIG_LTO=y
> > > > > >>>  CONFIG_ARM=y
> > > > > >>>  CONFIG_SYS_THUMB_BUILD=y
> > > > > >>>  CONFIG_ARCH_DAVINCI=y
> > > > > >>> diff --git a/configs/da850evm_direct_nor_defconfig 
> > > > > >>> b/configs/da850evm_direct_nor_defconfig
> > > > > >>> index d3860a963d..06c7ce7c47 100644
> > > > > >>> --- a/configs/da850evm_direct_nor_defconfig
> > > > > >>> +++ b/configs/da850evm_direct_nor_defconfig
> > > > > >>> @@ -1,3 +1,4 @@
> > > > > >>> +CONFIG_LTO=y
> > > > > >>>  CONFIG_ARM=y
> > > > > >>>  CONFIG_ARCH_CPU_INIT=y
> > > > > >>>  CONFIG_ARCH_DAVINCI=y
> > > > > >>> diff --git a/configs/da850evm_nand_defconfig 
> > > > > >>> b/configs/da850evm_nand_defconfig
> > > > > >>> index 0d0e9a148d..be737564e1 100644
> > > > > >>> --- a/configs/da850evm_nand_defconfig
> > > > > >>> +++ b/configs/da850evm_nand_defconfig
> > > > > >>> @@ -1,3 +1,4 @@
> > > > > >>> +CONFIG_LTO=y
> > > > > >>>  CONFIG_ARM=y
> > > > > >>>  CONFIG_SYS_THUMB_BUILD=y
> > > > > >>>  CONFIG_ARCH_DAVINCI=y
> > > > > >>> diff --git a/configs/imx6q_logic_defconfig 
> > > > > >>> b/configs/imx6q_logic_defconfig
> > > > > >>> index 36dc24d080..0f8aea6983 100644
> > > > > >>> --- a/configs/imx6q_logic_defconfig
> > > > > >>> +++ b/configs/imx6q_logic_defconfig
> > > > > >>> @@ -1,3 +1,4 @@
> > > > > >>> +CONFIG_LTO=y
> > > > > >>>  CONFIG_ARM=y
> > > > > >>>  CONFIG_ARCH_MX6=y
> > > > > >>>  CONFIG_SYS_TEXT_BASE=0x1780
> > > > > >>> diff --git a/configs/imx8mm_beacon_defconfig 
> > > > > >>> b/configs/imx8mm_beacon_defconfig
> > > > > >>> index 045b19f4f3..e8bb44eea6 100644
> > > > > >>> --- a/configs/imx8mm_beacon_defconfig
> > > > > >>> +++ b/configs/imx8mm_beacon_defconfig
> > > > > >>> @@ -1,3 +1,4 @@
> > > > > >>> +CONFIG_LTO=y
> > > > > >>>  CONFIG_ARM=y
> > > > > >>>  CONFIG_ARCH_IMX8M=y
> > > > > >>>  CONFIG_SYS_TEXT_BASE=0x4020
> > > > > >>> diff --git a/configs/imx8mm_venice_defconfig 
> > > > > >>> b/configs/imx8mm_venice_defconfig
> > > > > >>> index a15c3641f6..dff8f64540 100644
> > > > > >>> --- a/configs/imx8mm_venice_defconfig
> > > > > >>> +++ b/configs/imx8mm_venice_defconfig
> > > > > >>> @@ -1,3 +1,4 @@
> > > > > >>> +CONFIG_LTO=y
> > > > > >>>  CONFIG_ARM=y
> > > > > >>>  CONFIG_ARCH_IMX8M=y
> > > > > >>>  CONFIG_SYS_TEXT_BASE=0x4020
> > > > > >>> diff --git a/configs/imx8mn_beacon_2g_defconfig 
> > > > > >>> b/configs/imx8m

RE: [PATCH] arm: socfpga: smc: Remove unused SMC function ID

[Tan, Ley Foon]

> -Original Message-
> From: Lim, Elly Siew Chin 
> Sent: Friday, March 12, 2021 5:51 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
> 
> Subject: [PATCH] arm: socfpga: smc: Remove unused SMC function ID
> 
> Remove unused SMC function ID 61 and 62.
> 
> Signed-off-by: Siew Chin Lim 
> ---

Reviewed-by: Ley Foon Tan 

Re: [PATCH] pci: layerscape: Change to allocate zeroed memery for struct ls_pcie

[Vladimir Oltean]

On Thu, Mar 11, 2021 at 03:30:51PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang 
> 
> As on some incipient Layerscape platforms (LS1043A series) there isn't
> separate PF control register block, these registers reside in the LUT
> register block, so when the driver detected there isn't 'ctrl', it will
> assign the 'lut' address to the ls_pcie->ctrl.
> 
> The current code allocate memory for the struct ls_pcie with random
> contents, this can result in skipping to assign the ls_pcie->ctrl with
> the 'lut' address, then further crash with the incorrect address.
> 
> Fixes: 118e58e26eba ("pci: layerscape: Split the EP and RC driver")
> Signed-off-by: Hou Zhiqiang 
> ---

Reviewed-by: Vladimir Oltean 

Pull request for efi-2021-04-rc5

[Heinrich Schuchardt]

Dear Tom,

The following changes since commit 4103e13534141c31e4e9bf40848ab3a61dabce81:

  Prepare v2021.04-rc4 (2021-03-15 12:06:41 -0400)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-efi.git
tags/efi-2021-04-rc5

for you to fetch changes up to 75d48d11db2e2f07659abbbf2dc0483e929b3fc2:

  doc: move README.dfu to HTML documentation (2021-03-16 09:37:04 +0100)

Gitlab CI showed no problems:
https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/6789


Pull request for efi-2021-04-rc5

Bug fixes:

* fix memory type for memory reservation block
* illegal cast to pointer in initrddump
* fix compiler warnings

Documentation:

* move README.dfu to HTML documentation


Heinrich Schuchardt (3):
  efi_loader: disable GRUB_ARM32_WORKAROUND on ARCH_SUNXI
  efi_selftest: illegal cast to pointer in initrddump
  doc: move README.dfu to HTML documentation

Ilias Apalodimas (1):
  efi_selftest: Remove loadfile2 for initrd selftests

Mark Kettenis (1):
  efi_loader: fix memory type for memory reservation block

Simon Glass (2):
  mkeficapsule: Correct printf() strings
  efi: Fix compiler warnings

 MAINTAINERS |   1 +
 cmd/efidebug.c  |   2 +-
 doc/README.dfu  | 311 -
 doc/usage/dfu.rst   | 404

 doc/usage/index.rst |   1 +
 lib/efi_loader/Kconfig  |   2 +-
 lib/efi_loader/efi_capsule.c|   4 +-
 lib/efi_loader/efi_dt_fixup.c   |   2 +-
 lib/efi_loader/efi_firmware.c   |   4 +-
 lib/efi_selftest/Makefile   |   1 -
 lib/efi_selftest/efi_selftest_load_initrd.c | 221 ---
 lib/efi_selftest/initrddump.c   |   2 +-
 tools/mkeficapsule.c|  14 +-
 13 files changed, 421 insertions(+), 548 deletions(-)
 delete mode 100644 doc/README.dfu
 create mode 100644 doc/usage/dfu.rst
 delete mode 100644 lib/efi_selftest/efi_selftest_load_initrd.c

Re: [PATCH 6/7] board: sifive: add HiFive Unmatched board support

[Green Wan]

On Thu, Mar 11, 2021 at 10:21 PM Bin Meng  wrote:

> On Thu, Mar 11, 2021 at 9:50 PM Green Wan  wrote:
> >
> > Add dts, defconfig and board support for HiFive Unmatched.
> >
> > Signed-off-by: Green Wan 
> > ---
> >  arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489
> 
> >  arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi|   40 +
> >  arch/riscv/dts/hifive-unmatched-a00.dts|  263 
> >  board/sifive/fu540/Kconfig |1 -
> >  board/sifive/fu540/fu540.c |2 +-
>
> It looks these fu540 changes are not needed?
>
Let me remove the change for fu540 first and check on fu540.


>
> >  board/sifive/hifive_unmatched_fu740/Kconfig|   50 +
> >  board/sifive/hifive_unmatched_fu740/MAINTAINERS|9 +
> >  board/sifive/hifive_unmatched_fu740/Makefile   |9 +

>  .../hifive-unmatched-fu740.c   |   24 +
> >  board/sifive/hifive_unmatched_fu740/spl.c  |   85 ++
> >  configs/sifive_hifive_unmatched_fu740_defconfig|   57 +
>
  I'd like to rename  "board/sifive/hifive_unmatched_fu740" to the shorter
name "board/sifive/unmatched". And
"configs/sifive_hifive_unmatched_fu740_defconfig" to
"configs/sifive_unmatched_defconfig" in v2 patch.


> >  doc/board/sifive/fu540.rst |   19 +-
>
> here?
>
> >  doc/board/sifive/hifive_unmatched_fu740.rst|  532 +++
> >  drivers/reset/Kconfig  |2 +-
> >  include/configs/sifive-fu540.h |5 -
>
> and here?
>
> >  include/configs/sifive-hifive-unmatched-fu740.h|   88 ++
> >  16 files changed, 2656 insertions(+), 19 deletions(-)
> >  create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
> >  create mode 100644 arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
> >  create mode 100644 arch/riscv/dts/hifive-unmatched-a00.dts
> >  create mode 100644 board/sifive/hifive_unmatched_fu740/Kconfig
> >  create mode 100644 board/sifive/hifive_unmatched_fu740/MAINTAINERS
> >  create mode 100644 board/sifive/hifive_unmatched_fu740/Makefile
> >  create mode 100644
> board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c
> >  create mode 100644 board/sifive/hifive_unmatched_fu740/spl.c
> >  create mode 100644 configs/sifive_hifive_unmatched_fu740_defconfig
> >  create mode 100644 doc/board/sifive/hifive_unmatched_fu740.rst
> >  create mode 100644 include/configs/sifive-hifive-unmatched-fu740.h
> >
> > diff --git a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
> b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
> > new file mode 100644
> > index 000..4209491
> > --- /dev/null
> > +++ b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
>
> [snip]
>
> > diff --git a/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
> b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
> > new file mode 100644
> > index 000..3dcd2b4
> > --- /dev/null
> > +++ b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
> > @@ -0,0 +1,40 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2020-2021 SiFive, Inc
> > + */
> > +
> > +#include "fu740-c000-u-boot.dtsi"
> > +#include "fu740-hifive-unmatched-a00-ddr.dtsi"
> > +
> > +/ {
> > +   aliases {
> > +   spi0 = &spi0;
> > +   };
> > +
> > +   memory@8000 {
> > +   u-boot,dm-spl;
> > +   };
> > +
> > +   hfclk {
> > +   u-boot,dm-spl;
> > +   };
> > +
> > +   rtcclk {
> > +   u-boot,dm-spl;
> > +   };
> > +
> > +};
> > +
> > +&clint {
> > +   clocks = <&rtcclk>;
> > +};
> > +
> > +&spi0 {
> > +   mmc@0 {
> > +   u-boot,dm-spl;
> > +   };
> > +};
> > +
> > +&gpio {
> > +   u-boot,dm-spl;
> > +};
> > diff --git a/arch/riscv/dts/hifive-unmatched-a00.dts
> b/arch/riscv/dts/hifive-unmatched-a00.dts
> > new file mode 100644
> > index 000..92410b4
> > --- /dev/null
> > +++ b/arch/riscv/dts/hifive-unmatched-a00.dts
> > @@ -0,0 +1,263 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/* Copyright (c) 2019-2021 SiFive, Inc */
> > +
> > +#include "fu740-c000.dtsi"
> > +#include 
> > +
> > +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
> > +#define RTCCLK_FREQ100
> > +
> > +/ {
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +   model = "SiFive HiFive Unmatched A00";
> > +   compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
> > +"sifive,fu740";
> > +
> > +   chosen {
> > +   stdout-path = "serial0";
> > +   };
> > +
> > +   cpus {
> > +   timebase-frequency = ;
> > +   };
> > +
> > +   memory@8000 {
> > +   device_type = "memory";
> > +   reg = <0x0 0x8000 0x4 0x>;
> > +   };
> > +
> > +   soc {
> > +   };
> > +
> > +   hfclk: hfclk {
> > +   #clock-cells = <0>;
> > +   compatib

[PATCH u-boot v3 01/39] regmap: fix a serious pointer casting bug

[Marek Behún]

There is a serious bug in regmap_read() and regmap_write() functions
where an uint pointer is cast to (void *) which is then cast to (u8 *),
(u16 *), (u32 *) or (u64 *), depending on register width of the map.

For example given a regmap with 16-bit register width the code
int val = 0x1234;
regmap_read(map, 0, &val);
only changes the lower 16 bits of val on little-endian machines.
The upper 16 bits will remain 0x1234.

Nobody noticed this probably because this bug can be triggered with
regmap_write() only on big-endian architectures (which are not used by
many people anymore), and on little endian this bug has consequences
only if register width is 8 or 16 bits and also the memory place to
which regmap_read() should store it's result has non-zero upper bits,
which it seems doesn't happen anywhere in U-Boot normally. CI managed to
trigger this bug in unit test of dm_test_devm_regmap_field when compiled
for sandbox_defconfig using LTO.

Fix this simply by taking into account that regmap_raw_read() and
regmap_raw_write() behave as if the data given to these functions were
in little-endian format, i.e. use cpu_to_le32() / le32_to_cpu(). In
regmap_read() also zero out the space so that we don't get invalid
result if regmap_raw_read() does not fill the whole object.

Signed-off-by: Marek Behún 
Reviewed-by: Simon Glass 
Reviewed-by: Heiko Schocher 
Reviewed-by: Bin Meng 
---
 drivers/core/regmap.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index b51ce108c1..5d37006fff 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -435,7 +435,16 @@ int regmap_raw_read(struct regmap *map, uint offset, void 
*valp, size_t val_len)
 
 int regmap_read(struct regmap *map, uint offset, uint *valp)
 {
-   return regmap_raw_read(map, offset, valp, map->width);
+   int res;
+
+   *valp = 0;
+   res = regmap_raw_read(map, offset, valp, map->width);
+   if (res)
+   return res;
+
+   *valp = le32_to_cpu(*valp);
+
+   return 0;
 }
 
 static inline void __write_8(u8 *addr, const u8 *val,
@@ -546,6 +555,8 @@ int regmap_raw_write(struct regmap *map, uint offset, const 
void *val,
 
 int regmap_write(struct regmap *map, uint offset, uint val)
 {
+   val = cpu_to_le32(val);
+
return regmap_raw_write(map, offset, &val, map->width);
 }
 
-- 
2.26.2

[PATCH u-boot v3 00/39] U-Boot LTO (Sandbox + Some ARM boards)

[Marek Behún]

Hello,

this is version 3 of patches adding support for LTO to U-Boot.

This series was tested by Github/Azure CI at
  https://github.com/u-boot/u-boot/pull/57

Code reduction is on average 4.23% for u-boot.bin and 13.58% for
u-boot-spl.bin.

Changes sinve v2:
- now linking with --build-id=none in order to avoid link failures with
  some toolchains (thanks Herald Seiler)
- we don't use -flto=jobserver anymore, since it causes build errors for
  some people. Instead we link with -flto=NPROC
- removed LTO exception for arch/arm/mach-omap2/omap3/clock.o, Adam Ford
  says it is not needed
- added some Reviewed-by tags

Changes since v1:
- remove patches applied into u-boot-marvell
- added Reviewed-by tags
- addressed some issues discovered by Bin Meng, Marek Vasut,
  Heinrich Schuchardt
- added more ARM boards (thanks to Adam Ford, Tim Harvey and Bin Meng)
- removed --gc-sections for ARM if internal libgcc is used
- remove -fwhole-program in final LTO LDFLAGS
- declared all 4 functions (memcpy, memset, memcmp, memmove) __used,
  (these are mentioned in GCC man page for option -nodefaultlibs that
   the compiler may generate; this seems to be a bug in GCC that linking
   fails with LTO even if these functions are present, because the
   symbols can be renamed on some targets by optimization)

Marek

Marek Behún (39):
  regmap: fix a serious pointer casting bug
  api: fix a potential serious bug caused by undef CONFIG_SYS_64BIT_LBA
  checkpatch: require quotes around section name in the __section()
macro
  treewide: Convert macro and uses of __section(foo) to __section("foo")
  compiler.h: align the __ADDRESSABLE macro with Linux' version
  linker_lists: prepare macros to avoid code repetition
  test/py: improve regular expression for ut subtest symbol matcher
  linker_lists: declare lists and entries as __ADDRESSABLE for LTO
  string: make memcpy(), memset(), memcmp() and memmove() visible for
LTO
  efi_loader: fix warning when linking with LTO
  efi_loader: add Sphinx doc for __efi_runtime and __efi_runtime_data
  efi_loader: add macro for const EFI runtime data
  efi_selftest: compiler flags for efi_selftest_miniapp_exception.o
  lib: crc32: put the crc_table variable into efi_runtime_rodata section
  Makefile, Makefile.spl: cosmetic change
  build: use thin archives instead of incremental linking
  build: support building with Link Time Optimizations
  build: link with --build-id=none
  sandbox: errno: avoid conflict with libc's errno
  sandbox: use sections instead of symbols for getopt array boundaries
  sandbox: make LTO available
  sandbox: enable LTO by default
  ARM: global_data: make set_gd() work for armv5 and armv6
  ARM: make gd a function call for LTO and set via set_gd()
  ARM: fix LTO build for some thumb-interwork cases
  ARM: fix LTO for imx28_xea
  ARM: fix LTO for apf27
  ARM: fix LTO for keystone
  ARM: kona: fix clk_bsc_enable() type mismatch for LTO
  ARM: imx8m: fix imx_eqos_txclk_set_rate() type mismatch for LTO
  ARM: fix LTO for seaboard
  ARM: fix LTO for rockchip and samsung
  ARM: omap3: fix LTO for DM3730 (and possibly other omap3 boards)
  armv8: SPL: discard relocation information
  ata: ahci: fix ahci_link_up() type mismatch for LTO
  ARM: make LTO available
  ARM: don't use -ffunction-sections/-fdata-sections with LTO build
  ARM: don't use --gc-sections with LTO when using private libgcc
  ARM: enable LTO for some boards

 Kbuild |  2 +
 Kconfig| 24 
 Makefile   | 51 +++--
 arch/Kconfig   |  3 +
 arch/arm/config.mk | 10 +++-
 arch/arm/cpu/arm926ejs/Makefile|  2 +
 arch/arm/cpu/arm926ejs/mxs/mxs.c   |  2 +-
 arch/arm/cpu/arm926ejs/mxs/spl_boot.c  |  4 +-
 arch/arm/cpu/arm926ejs/spear/spl.c |  2 +-
 arch/arm/cpu/armv7/kona-common/clk-stubs.c |  2 +-
 arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c  |  2 +-
 arch/arm/cpu/armv8/fsl-layerscape/spl.c|  2 +-
 arch/arm/cpu/armv8/spl_data.c  |  4 +-
 arch/arm/cpu/armv8/u-boot-spl.lds  |  1 +
 arch/arm/include/asm/global_data.h |  6 +-
 arch/arm/include/asm/secure.h  |  6 +-
 arch/arm/include/asm/setup.h   |  2 +-
 arch/arm/lib/Makefile  |  3 +
 arch/arm/lib/sections.c| 31 +-
 arch/arm/lib/spl.c |  2 +-
 arch/arm/mach-at91/spl.c   |  2 +-
 arch/arm/mach-exynos/spl_boot.c|  2 +-
 arch/arm/mach-imx/imx8m/clock_imx8mm.c |  2 +-
 arch/arm/mach-imx/imx8m/soc.c  |  2 +-
 arch/arm/mach-imx/spl_imx_romapi.c | 16 +++---
 arch/arm/mach-k3/am6_init.c|  2 +-
 arch/arm/mach-k3/j721e_init.c  |  4 +-
 arch/arm/mach-keystone/Makefile|  1 +
 arch/arm/mach-mvebu/mbus.c |  4 +-
 arch/arm/mach-mvebu/timer.c   

[PATCH u-boot v3 03/39] checkpatch: require quotes around section name in the __section() macro

[Marek Behún]

This is how Linux does this now, see Linux commit 339f29d91acf.

Signed-off-by: Marek Behún 
---
 scripts/checkpatch.pl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 755f4802a4..fd1e9c4d24 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -6065,7 +6065,7 @@ sub process {
my $old = substr($rawline, $-[1], $+[1] - $-[1]);
my $new = substr($old, 1, -1);
if (WARN("PREFER_SECTION",
-"__section($new) is preferred over 
__attribute__((section($old)))\n" . $herecurr) &&
+"__section(\"$new\") is preferred over 
__attribute__((section($old)))\n" . $herecurr) &&
$fix) {
$fixed[$fixlinenr] =~ 
s/\b__attribute__\s*\(\s*\(\s*_*section_*\s*\(\s*\Q$old\E\s*\)\s*\)\s*\)/__section($new)/;
}
-- 
2.26.2

[PATCH u-boot v3 06/39] linker_lists: prepare macros to avoid code repetition

[Marek Behún]

Prepare private macros expanding to linker list entry symbol name and
declaration to avoid nasty code repetition in the next patch.

We also avoid some code repetition in current code with these macros.

Signed-off-by: Marek Behún 
Reviewed-by: Bin Meng 
---
 include/linker_lists.h | 46 --
 1 file changed, 31 insertions(+), 15 deletions(-)

diff --git a/include/linker_lists.h b/include/linker_lists.h
index 0259d34919..815a90691a 100644
--- a/include/linker_lists.h
+++ b/include/linker_lists.h
@@ -19,6 +19,27 @@
 
 #if !defined(__ASSEMBLY__)
 
+/**
+ * __llname() - Private macro expanding to symbol name for linker list entry
+ * @_name: Name of the entry
+ * @_list: name of the list. Should contain only characters allowed
+ * in a C variable name!
+ */
+#define __llname(_name, _list) \
+   _u_boot_list_2_##_list##_2_##_name
+
+/**
+ * __lldecl() - Private macro expanding to declaration of linker list entry
+ * @_type: Data type of the entry
+ * @_name: Name of the entry
+ * @_list: name of the list. Should contain only characters allowed
+ * in a C variable name!
+ */
+#define __lldecl(_type, _name, _list)  \
+   _type __aligned(4) __attribute__((unused))  \
+   __section(".u_boot_list_2_"#_list"_2_"#_name)   \
+   __llname(_name, _list)
+
 /**
  * llsym() - Access a linker-generated array entry
  * @_type: Data type of the entry
@@ -27,7 +48,7 @@
  * in a C variable name!
  */
 #define llsym(_type, _name, _list) \
-   ((_type *)&_u_boot_list_2_##_list##_2_##_name)
+   ((_type *)&__llname(_name, _list))
 
 /**
  * ll_entry_declare() - Declare linker-generated array entry
@@ -67,10 +88,8 @@
  *   .y = 4,
  *   };
  */
-#define ll_entry_declare(_type, _name, _list)  \
-   _type _u_boot_list_2_##_list##_2_##_name __aligned(4)   \
-   __attribute__((unused)) \
-   __section(".u_boot_list_2_"#_list"_2_"#_name)
+#define ll_entry_declare(_type, _name, _list) \
+   __lldecl(_type, _name, _list)
 
 /**
  * ll_entry_declare_list() - Declare a list of link-generated array entries
@@ -90,10 +109,8 @@
  *{ .x = 1, .y = 7 }
  *   };
  */
-#define ll_entry_declare_list(_type, _name, _list) \
-   _type _u_boot_list_2_##_list##_2_##_name[] __aligned(4) \
-   __attribute__((unused)) \
-   __section(".u_boot_list_2_"#_list"_2_"#_name)
+#define ll_entry_declare_list(_type, _name, _list) \
+   __lldecl(_type, _name, _list)[]
 
 /*
  * We need a 0-byte-size type for iterator symbols, and the compiler
@@ -203,12 +220,11 @@
  *   ...
  *   struct my_sub_cmd *c = ll_entry_get(struct my_sub_cmd, my_sub_cmd, 
cmd_sub);
  */
-#define ll_entry_get(_type, _name, _list)  \
-   ({  \
-   extern _type _u_boot_list_2_##_list##_2_##_name;\
-   _type *_ll_result = \
-   &_u_boot_list_2_##_list##_2_##_name;\
-   _ll_result; \
+#define ll_entry_get(_type, _name, _list)  \
+   ({  \
+   extern _type __llname(_name, _list);\
+   _type *_ll_result = &__llname(_name, _list);\
+   _ll_result; \
})
 
 /**
-- 
2.26.2

[PATCH u-boot v3 05/39] compiler.h: align the __ADDRESSABLE macro with Linux' version

[Marek Behún]

Use UNIQUE_ID in the __ADDRESSABLE macro.

Signed-off-by: Marek Behún 
Reviewed-by: Bin Meng 
---
 include/linux/compiler.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/compiler.h b/include/linux/compiler.h
index 82a8a4ede9..98dd3fc4cc 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -295,7 +295,7 @@ unsigned long read_word_at_a_time(const void *addr)
  */
 #define __ADDRESSABLE(sym) \
static void * __section(".discard.addressable") __used \
-   __PASTE(__addressable_##sym, __LINE__) = (void *)&sym;
+   __UNIQUE_ID(__PASTE(__addressable_,sym)) = (void *)&sym;
 
 /**
  * offset_to_ptr - convert a relative memory offset to an absolute pointer
-- 
2.26.2

[PATCH u-boot v3 02/39] api: fix a potential serious bug caused by undef CONFIG_SYS_64BIT_LBA

[Marek Behún]

The api_public.h header file undefined macro CONFIG_SYS_64BIT_LBA.

But api/api_storage.c includes this header before including part.h,
causing the type of lbaint_t and subsequently the type signature of
blk_dread() and blk_dwrite() functions to change from the rest of U-Boot
(if CONFIG_SYS_64BIT_LBA is defined for the board).

This is of course wrong, because the call to blk_dread() / blk_dwrite()
will receive mangled arguments.

Fix this by removing the undef of macro CONFIG_SYS_64BIT_LBA and instead
make the immediate code do what it would do as if the macro was not
defined.

Add a FIXME to whoever is maintaining this code.

CI managed to trigger this bug when compiling for lsxhl_defconfig, which
has CONFIG_API selected. The compiler complained about blk_dwrite() and
blk_dread() not matching original declarations:

  include/blk.h:280:15: warning: type of ‘blk_dwrite’ does not match
 original declaration
 [-Wlto-type-mismatch]
  280 | unsigned long blk_dwrite(struct blk_desc *block_dev, lbaint_t st
  |   ^
  drivers/block/blk-uclass.c:456:15: note: type mismatch in parameter 2
  456 | unsigned long blk_dwrite(struct blk_desc *block_dev, lbaint_t st
  |   ^

Signed-off-by: Marek Behún 
Reviewed-by: Simon Glass 
---
 include/api_public.h | 23 ++-
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/include/api_public.h b/include/api_public.h
index def103ce22..5a4465ea89 100644
--- a/include/api_public.h
+++ b/include/api_public.h
@@ -70,12 +70,25 @@ struct sys_info {
int mr_no;  /* number of memory regions */
 };
 
-#undef CONFIG_SYS_64BIT_LBA
-#ifdef CONFIG_SYS_64BIT_LBA
-typedefu_int64_t lbasize_t;
-#else
+/*
+ * FIXME: Previously this code was:
+ *
+ *   #undef CONFIG_SYS_64BIT_LBA
+ *   #ifdef CONFIG_SYS_64BIT_LBA
+ *   typedef u_int64_t lbasize_t;
+ *   #else
+ *   typedef unsigned long lbasize_t;
+ *   #endif
+ *
+ * But we cannot just undefine CONFIG_SYS_64BIT_LBA, because then in
+ * api/api_storage.c the type signature of lbaint_t will be different if
+ * CONFIG_SYS_64BIT_LBA is enabled for the board, which can result in various
+ * bugs.
+ * So simply define lbasize_t as an unsigned long, since this was what was done
+ * anyway for at least 13 years, but don't undefine CONFIG_SYS_64BIT_LBA.
+ */
 typedef unsigned long lbasize_t;
-#endif
+
 typedef unsigned long lbastart_t;
 
 #define DEV_TYP_NONE   0x
-- 
2.26.2

[PATCH u-boot v3 07/39] test/py: improve regular expression for ut subtest symbol matcher

[Marek Behún]

Improve the regular expression that matches unittest symbols in
u-boot.sym.

Currently we do not enforce no prefix in symbol string, but with the
soon to come change in linker lists declaring lists and entries with the
__ADDRESSABLE macro (because of LTO), the symbol file will contain for
every symbol of the form
  _u_boot_list_2_X_2_Y
also symbol
  __UNIQUE_ID___addressable__u_boot_list_2_X_2_YN,
(where N at the end is some number).

In order to avoid matching these additional symbols, ensure that the
character before "_u_boot_list_2" is not a symbol name character.

Signed-off-by: Marek Behún 
---
 test/py/conftest.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/test/py/conftest.py b/test/py/conftest.py
index 9bfd926345..3ea3fa5220 100644
--- a/test/py/conftest.py
+++ b/test/py/conftest.py
@@ -226,7 +226,7 @@ def pytest_configure(config):
 import u_boot_console_exec_attach
 console = u_boot_console_exec_attach.ConsoleExecAttach(log, ubconfig)
 
-re_ut_test_list = re.compile(r'_u_boot_list_2_(.*)_test_2_\1_test_(.*)\s*$')
+re_ut_test_list = 
re.compile(r'[^a-zA-Z0-9_]_u_boot_list_2_(.*)_test_2_\1_test_(.*)\s*$')
 def generate_ut_subtest(metafunc, fixture_name, sym_path):
 """Provide parametrization for a ut_subtest fixture.
 
-- 
2.26.2

[PATCH u-boot v3 04/39] treewide: Convert macro and uses of __section(foo) to __section("foo")

[Marek Behún]

This commit does the same thing as Linux commit 33def8498fdd.

Use a more generic form for __section that requires quotes to avoid
complications with clang and gcc differences.

Remove the quote operator # from compiler_attributes.h __section macro.

Convert all unquoted __section(foo) uses to quoted __section("foo").
Also convert __attribute__((section("foo"))) uses to __section("foo")
even if the __attribute__ has multiple list entry forms.

Signed-off-by: Marek Behún 
Reviewed-by: Bin Meng 
---
 arch/arm/cpu/arm926ejs/spear/spl.c|  2 +-
 arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c |  2 +-
 arch/arm/cpu/armv8/fsl-layerscape/spl.c   |  2 +-
 arch/arm/cpu/armv8/spl_data.c |  4 +--
 arch/arm/include/asm/secure.h |  6 ++---
 arch/arm/include/asm/setup.h  |  2 +-
 arch/arm/lib/sections.c   | 31 ---
 arch/arm/lib/spl.c|  2 +-
 arch/arm/mach-at91/spl.c  |  2 +-
 arch/arm/mach-k3/am6_init.c   |  2 +-
 arch/arm/mach-k3/j721e_init.c |  4 +--
 arch/arm/mach-mvebu/mbus.c|  4 +--
 arch/arm/mach-mvebu/timer.c   |  2 +-
 arch/arm/mach-nexell/clock.c  |  6 ++---
 arch/arm/mach-nexell/timer.c  |  6 ++---
 arch/arm/mach-socfpga/spl_a10.c   |  2 +-
 arch/arm/mach-sunxi/board.c   |  2 +-
 arch/arm/mach-tegra/board.c   |  2 +-
 arch/arm/mach-tegra/cboot.c   |  8 +++---
 arch/mips/mach-jz47xx/jz4780/jz4780.c |  2 +-
 arch/nds32/include/asm/setup.h|  6 ++---
 arch/powerpc/include/asm/cache.h  |  4 +--
 arch/riscv/cpu/cpu.c  |  4 +--
 arch/sandbox/include/asm/getopt.h |  2 +-
 arch/sandbox/lib/sections.c   |  9 ---
 arch/x86/cpu/coreboot/tables.c|  2 +-
 arch/x86/cpu/coreboot/timestamp.c |  2 +-
 arch/x86/lib/sections.c   |  9 ---
 arch/xtensa/cpu/cpu.c |  2 +-
 board/bosch/shc/board.c   |  2 +-
 board/broadcom/bcmstb/bcmstb.c|  2 +-
 board/samsung/arndale/arndale_spl.c   |  2 +-
 board/samsung/smdk5250/smdk5250_spl.c |  2 +-
 board/samsung/smdk5420/smdk5420_spl.c |  2 +-
 board/siemens/draco/board.c   |  2 +-
 board/xilinx/common/fru_ops.c |  2 +-
 drivers/bios_emulator/biosemu.c   |  4 +--
 drivers/firmware/psci.c   |  2 +-
 drivers/pinctrl/nxp/pinctrl-imx5.c|  2 +-
 drivers/pinctrl/nxp/pinctrl-imx7.c|  2 +-
 drivers/pinctrl/nxp/pinctrl-imx8m.c   |  2 +-
 drivers/power/pmic/pmic_tps62362.c|  2 +-
 drivers/power/pmic/pmic_tps65217.c|  2 +-
 drivers/power/pmic/pmic_tps65218.c|  2 +-
 drivers/power/pmic/pmic_tps65910.c|  2 +-
 drivers/serial/serial_pl01x.c |  4 +--
 include/efi_loader.h  |  4 +--
 include/linker_lists.h| 24 +-
 include/linux/compiler.h  |  8 +++---
 include/linux/compiler_attributes.h   |  2 +-
 lib/trace.c   |  4 +--
 51 files changed, 108 insertions(+), 105 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c 
b/arch/arm/cpu/arm926ejs/spear/spl.c
index 08b98a2d06..b5b9945a87 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -22,7 +22,7 @@
  * The BSS cannot be used for this purpose because it will be zeroed after
  * having stored the pointer, so force the location to the data section.
  */
-u32 bootrom_stash_sp __attribute__((section(".data")));
+u32 bootrom_stash_sp __section(".data");
 
 static void ddr_clock_init(void)
 {
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c 
b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
index 4a4b3c6f23..28a7945207 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -13,7 +13,7 @@
 #include 
 #include "fsl_epu.h"
 
-#define __secure __attribute__((section("._secure.text")))
+#define __secure __section("._secure.text")
 
 #define CCSR_GICD_CTLR 0x1000
 #define CCSR_GICC_CTLR 0x2000
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c 
b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index d5131bcf4b..f3e7e07412 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -40,7 +40,7 @@ u32 spl_boot_device(void)
 #ifdef CONFIG_SPL_BUILD
 
 /* Define board data structure */
-static struct bd_info bdata __attribute__ ((section(".data")));
+static struct bd_info bdata __section(".data");
 
 void spl_board_init(void)
 {
diff --git a/arch/arm/cpu/armv8/spl_data.c b/arch/arm/cpu/armv8/spl_data.c
index 8fd986a67a..8f1231c86e 100644
--- a/arch/arm/cpu/armv8/spl_data.c
+++ b/arch/arm/cpu/armv8/spl_data.c
@@ -6,8 +6,8 @@
 #include 
 #include 
 
-char __data_save_start[0] __section(.__data_save_start);
-char

[PATCH u-boot v3 09/39] string: make memcpy(), memset(), memcmp() and memmove() visible for LTO

[Marek Behún]

It seems that sometimes (happening on ARM64, for example with
turris_mox_defconfig) GCC, when linking with LTO, changes the symbol
names of some functions, for example lib/string.c's memcpy() function to
memcpy.isra.0.

This is a problem however when GCC for a code such as this:
struct some_struct *info = get_some_struct();
struct some struct tmpinfo;
tmpinfo = *info;
emits a call to memcpy() by builtin behaviour, to copy *info to tmpinfo.

This then results in the following linking error:
  .../lz4.c:93: undefined reference to `memcpy'
  .../uuid.c:206: more undefined references to `memcpy' follow

GCC's documentation says this about -nodefaultlibs option:
  The compiler may generate calls to "memcmp", "memset", "memcpy" and
  "memmove".  These entries are usually resolved by entries in libc.
  These entry points should be supplied through some other mechanism
  when this option is specified.

Make these functions visible by using the __used macro to avoid this
error.

Signed-off-by: Marek Behún 
---
 lib/string.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/lib/string.c b/lib/string.c
index 73b984123d..ab8bed63c0 100644
--- a/lib/string.c
+++ b/lib/string.c
@@ -16,6 +16,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -490,7 +491,7 @@ char *strswab(const char *s)
  *
  * Do not use memset() to access IO space, use memset_io() instead.
  */
-void * memset(void * s,int c,size_t count)
+__used void * memset(void * s,int c,size_t count)
 {
unsigned long *sl = (unsigned long *) s;
char *s8;
@@ -529,7 +530,7 @@ void * memset(void * s,int c,size_t count)
  * You should not use this function to access IO space, use memcpy_toio()
  * or memcpy_fromio() instead.
  */
-void * memcpy(void *dest, const void *src, size_t count)
+__used void * memcpy(void *dest, const void *src, size_t count)
 {
unsigned long *dl = (unsigned long *)dest, *sl = (unsigned long *)src;
char *d8, *s8;
@@ -563,7 +564,7 @@ void * memcpy(void *dest, const void *src, size_t count)
  *
  * Unlike memcpy(), memmove() copes with overlapping areas.
  */
-void * memmove(void * dest,const void *src,size_t count)
+__used void * memmove(void * dest,const void *src,size_t count)
 {
char *tmp, *s;
 
@@ -599,7 +600,7 @@ void * memmove(void * dest,const void *src,size_t count)
  * @ct: Another area of memory
  * @count: The size of the area.
  */
-int memcmp(const void * cs,const void * ct,size_t count)
+__used int memcmp(const void * cs,const void * ct,size_t count)
 {
const unsigned char *su1, *su2;
int res = 0;
-- 
2.26.2

[PATCH u-boot v3 08/39] linker_lists: declare lists and entries as __ADDRESSABLE for LTO

[Marek Behún]

Use the __ADDRESSABLE() macro to make entries and lists declared by
ll_entry_declare() and ll_entry_declare_list() addressable so that when
building with LTO the compiler does not optimize this data away.

Signed-off-by: Marek Behún 
Reviewed-by: Bin Meng 
---
 include/linker_lists.h | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/include/linker_lists.h b/include/linker_lists.h
index 815a90691a..c9c3b3c2ad 100644
--- a/include/linker_lists.h
+++ b/include/linker_lists.h
@@ -88,7 +88,9 @@
  *   .y = 4,
  *   };
  */
-#define ll_entry_declare(_type, _name, _list) \
+#define ll_entry_declare(_type, _name, _list)  \
+   __lldecl(_type, _name, _list);  \
+   __ADDRESSABLE(__llname(_name, _list));  \
__lldecl(_type, _name, _list)
 
 /**
@@ -109,7 +111,9 @@
  *{ .x = 1, .y = 7 }
  *   };
  */
-#define ll_entry_declare_list(_type, _name, _list) \
+#define ll_entry_declare_list(_type, _name, _list) \
+   __lldecl(_type, _name, _list)[];\
+   __ADDRESSABLE(__llname(_name, _list));  \
__lldecl(_type, _name, _list)[]
 
 /*
-- 
2.26.2

[PATCH u-boot v3 10/39] efi_loader: fix warning when linking with LTO

[Marek Behún]

When linking with LTO, the compiler complains about type mismatch of
variables `__efi_runtime_start`, `__efi_runtime_stop`,
`__efi_runtime_rel_start` and `__efi_runtime_rel_stop`:

 include/efi_loader.h:218:21: warning: type of ‘__efi_runtime_start’
   does not match original
   declaration [-Wlto-type-mismatch]
218 | extern unsigned int __efi_runtime_start, __efi_runtime_stop;
| ^
  arch/sandbox/lib/sections.c:7:6: note: ‘__efi_runtime_start’ was
 previously declared here
  7 | char __efi_runtime_start[0] __attribute__((section(".__efi_run
|  ^

Change the type to char[] in include/efi_loader.h.

Signed-off-by: Marek Behún 
Reviewed-by: Bin Meng 
---
 include/efi_loader.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/efi_loader.h b/include/efi_loader.h
index e38b41952d..a8281b3c95 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -215,8 +215,8 @@ extern const efi_guid_t efi_guid_capsule_report;
 /* GUID of firmware management protocol */
 extern const efi_guid_t efi_guid_firmware_management_protocol;
 
-extern unsigned int __efi_runtime_start, __efi_runtime_stop;
-extern unsigned int __efi_runtime_rel_start, __efi_runtime_rel_stop;
+extern char __efi_runtime_start[], __efi_runtime_stop[];
+extern char __efi_runtime_rel_start[], __efi_runtime_rel_stop[];
 
 /**
  * struct efi_open_protocol_info_item - open protocol info item
-- 
2.26.2

[PATCH u-boot v3 11/39] efi_loader: add Sphinx doc for __efi_runtime and __efi_runtime_data

[Marek Behún]

Document the macros __efi_runtime and __efi_runtime_data in Sphinx
style.

Signed-off-by: Marek Behún 
Reviewed-by: Heinrich Schuchardt 
---
 include/efi_loader.h | 29 ++---
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/include/efi_loader.h b/include/efi_loader.h
index a8281b3c95..696f80e9f3 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -666,11 +666,34 @@ ssize_t efi_dp_check_length(const struct efi_device_path 
*dp,
(((_dp)->type == DEVICE_PATH_TYPE_##_type) && \
 ((_dp)->sub_type == DEVICE_PATH_SUB_TYPE_##_subtype))
 
-/*
- * Use these to indicate that your code / data should go into the EFI runtime
- * section and thus still be available when the OS is running
+/**
+ * __efi_runtime_data - declares a non-const variable for EFI runtime section
+ *
+ * This macro indicates that a variable is non-const and should go into the
+ * EFI runtime section, and thus still be available when the OS is running.
+ *
+ * Only use on variables not declared const.
+ *
+ * Example:
+ *
+ * ::
+ *
+ *   static __efi_runtime_data my_computed_table[256];
  */
 #define __efi_runtime_data __section(".data.efi_runtime")
+
+/**
+ * __efi_runtime - declares a function for EFI runtime section
+ *
+ * This macro indicates that a function should go into the EFI runtime section,
+ * and thus still be available when the OS is running.
+ *
+ * Example:
+ *
+ * ::
+ *
+ *   static __efi_runtime compute_my_table(void);
+ */
 #define __efi_runtime __section(".text.efi_runtime")
 
 /* Indicate supported runtime services */
-- 
2.26.2

[PATCH u-boot v3 15/39] Makefile, Makefile.spl: cosmetic change

[Marek Behún]

Indent the linking commands so that they look cosmetically better.

Signed-off-by: Marek Behún 
Reviewed-by: Bin Meng 
---
 Makefile | 12 +++-
 scripts/Makefile.spl | 17 +++--
 2 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/Makefile b/Makefile
index 3ebb38b113..e668940aba 100644
--- a/Makefile
+++ b/Makefile
@@ -1747,11 +1747,13 @@ ARCH_POSTLINK := $(wildcard 
$(srctree)/arch/$(ARCH)/Makefile.postlink)
 # Rule to link u-boot
 # May be overridden by arch/$(ARCH)/config.mk
 quiet_cmd_u-boot__ ?= LD  $@
-  cmd_u-boot__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_u-boot) -o $@ \
-  -T u-boot.lds $(u-boot-init) \
-  --start-group $(u-boot-main) --end-group \
-  $(PLATFORM_LIBS) -Map u-boot.map;\
-  $(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
+  cmd_u-boot__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_u-boot) -o $@  
\
+   -T u-boot.lds $(u-boot-init)
\
+   --start-group   
\
+   $(u-boot-main)  
\
+   --end-group 
\
+   $(PLATFORM_LIBS) -Map u-boot.map;   
\
+   $(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
 
 quiet_cmd_smap = GEN common/system_map.o
 cmd_smap = \
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 1fd63efdfd..297f98dafd 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -427,12 +427,17 @@ $(obj)/$(SPL_BIN).sym: $(obj)/$(SPL_BIN) FORCE
 # Rule to link u-boot-spl
 # May be overridden by arch/$(ARCH)/config.mk
 quiet_cmd_u-boot-spl ?= LD  $@
-  cmd_u-boot-spl ?= (cd $(obj) && $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_$(@F)) 
\
-  $(patsubst $(obj)/%,%,$(u-boot-spl-init)) --start-group \
-  $(patsubst $(obj)/%,%,$(u-boot-spl-main))  \
-  $(patsubst $(obj)/%,%,$(u-boot-spl-platdata)) \
-  --end-group \
-  $(PLATFORM_LIBS) -Map $(SPL_BIN).map -o $(SPL_BIN))
+  cmd_u-boot-spl ?= \
+   (   \
+   cd $(obj) &&\
+   $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_$(@F))\
+   $(patsubst $(obj)/%,%,$(u-boot-spl-init))   \
+   --start-group   \
+   $(patsubst $(obj)/%,%,$(u-boot-spl-main))   \
+   $(patsubst $(obj)/%,%,$(u-boot-spl-platdata))   \
+   --end-group \
+   $(PLATFORM_LIBS) -Map $(SPL_BIN).map -o $(SPL_BIN)  \
+   )
 
 $(obj)/$(SPL_BIN): $(u-boot-spl-platdata) $(u-boot-spl-init) \
$(u-boot-spl-main) $(obj)/u-boot-spl.lds FORCE
-- 
2.26.2

[PATCH u-boot v3 14/39] lib: crc32: put the crc_table variable into efi_runtime_rodata section

[Marek Behún]

When compiling with LTO, the compiler fails with an error saying that
`crc_table` causes a section type conflict with `efi_var_buf`.

This is because both are declared to be in the same section (via macro
`__efi_runtime_data`), but one is const while the other is not.

Put this variable into the section .rodata.efi_runtime, instead of
.data.efi_runtime, via macro __efi_runtime_rodata.

Signed-off-by: Marek Behún 
Reviewed-by: Marek Vasut 
Reviewed-by: Heinrich Schuchardt 
---
 lib/crc32.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/lib/crc32.c b/lib/crc32.c
index e9be3bf386..f2acc107fe 100644
--- a/lib/crc32.c
+++ b/lib/crc32.c
@@ -26,6 +26,7 @@
 #ifdef USE_HOSTCC
 #define __efi_runtime
 #define __efi_runtime_data
+#define __efi_runtime_rodata
 #endif
 
 #define tole(x) cpu_to_le32(x)
@@ -88,7 +89,7 @@ static void __efi_runtime make_crc_table(void)
  * Table of CRC-32's of all single-byte values (made by make_crc_table)
  */
 
-static const uint32_t __efi_runtime_data crc_table[256] = {
+static const uint32_t __efi_runtime_rodata crc_table[256] = {
 tole(0xL), tole(0x77073096L), tole(0xee0e612cL), tole(0x990951baL),
 tole(0x076dc419L), tole(0x706af48fL), tole(0xe963a535L), tole(0x9e6495a3L),
 tole(0x0edb8832L), tole(0x79dcb8a4L), tole(0xe0d5e91eL), tole(0x97d2d988L),
-- 
2.26.2

[PATCH u-boot v3 12/39] efi_loader: add macro for const EFI runtime data

[Marek Behún]

Add macro __efi_runtime_rodata, for const variables with similar purpose
as those using __efi_runtime_data.

Signed-off-by: Marek Behún 
Reviewed-by: Heinrich Schuchardt 
---
 include/efi_loader.h | 17 +
 1 file changed, 17 insertions(+)

diff --git a/include/efi_loader.h b/include/efi_loader.h
index 696f80e9f3..d673ba12e3 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -682,6 +682,22 @@ ssize_t efi_dp_check_length(const struct efi_device_path 
*dp,
  */
 #define __efi_runtime_data __section(".data.efi_runtime")
 
+/**
+ * __efi_runtime_rodata - declares a read-only variable for EFI runtime section
+ *
+ * This macro indicates that a variable is read-only (const) and should go into
+ * the EFI runtime section, and thus still be available when the OS is running.
+ *
+ * Only use on variables also declared const.
+ *
+ * Example:
+ *
+ * ::
+ *
+ *   static const __efi_runtime_rodata my_const_table[] = { 1, 2, 3 };
+ */
+#define __efi_runtime_rodata __section(".rodata.efi_runtime")
+
 /**
  * __efi_runtime - declares a function for EFI runtime section
  *
@@ -893,6 +909,7 @@ efi_status_t efi_launch_capsules(void);
 
 /* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out */
 #define __efi_runtime_data
+#define __efi_runtime_rodata
 #define __efi_runtime
 static inline efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len)
 {
-- 
2.26.2

[PATCH u-boot v3 13/39] efi_selftest: compiler flags for efi_selftest_miniapp_exception.o

[Marek Behún]

Add $(CFLAGS_EFI) and remove $(CFLAGS_NON_EFI) for
efi_selftest_miniapp_exception.o.

The removal is needed when compiling with LTO - this object file needs
to be compiled without -flto.

The adding is for consistency with other miniapps.

Signed-off-by: Marek Behún 
Reviewed-by: Heinrich Schuchardt 
---
 lib/efi_selftest/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile
index b02fd56e0a..8f042ad254 100644
--- a/lib/efi_selftest/Makefile
+++ b/lib/efi_selftest/Makefile
@@ -10,6 +10,8 @@ ccflags-y += -DHOST_ARCH="$(HOST_ARCH)"
 
 CFLAGS_dtbdump.o := $(CFLAGS_EFI) -Os -ffreestanding
 CFLAGS_REMOVE_dtbdump.o := $(CFLAGS_NON_EFI)
+CFLAGS_efi_selftest_miniapp_exception.o := $(CFLAGS_EFI) -Os -ffreestanding
+CFLAGS_REMOVE_efi_selftest_miniapp_exception.o := $(CFLAGS_NON_EFI)
 CFLAGS_efi_selftest_miniapp_exit.o := $(CFLAGS_EFI) -Os -ffreestanding
 CFLAGS_REMOVE_efi_selftest_miniapp_exit.o := $(CFLAGS_NON_EFI)
 CFLAGS_efi_selftest_miniapp_return.o := $(CFLAGS_EFI) -Os -ffreestanding
-- 
2.26.2

[PATCH u-boot v3 19/39] sandbox: errno: avoid conflict with libc's errno

[Marek Behún]

When building with LTO, the system libc's `errno` variable used in
arch/sandbox/cpu/os.c conflicts with U-Boot's `errno` (defined in
lib/errno.c) with the following error:
 .../ld: errno@@GLIBC_PRIVATE: TLS definition in /lib64/libc.so.6
 section .tbss mismatches non-TLS reference in
 /tmp/u-boot.EQlEXz.ltrans0.ltrans.o

To avoid this conflict use different asm label for this variable when
CONFIG_SANDBOX is enabled.

Signed-off-by: Marek Behún 
Reviewed-by: Bin Meng 
Reviewed-by: Simon Glass 
---
 include/errno.h | 8 +++-
 lib/errno.c | 4 +++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/include/errno.h b/include/errno.h
index 3af539b9e9..652ad67306 100644
--- a/include/errno.h
+++ b/include/errno.h
@@ -8,7 +8,13 @@
 
 #include 
 
-extern int errno;
+#ifdef __SANDBOX__
+#define __errno_asm_label asm("__u_boot_errno")
+#else
+#define __errno_asm_label
+#endif
+
+extern int errno __errno_asm_label;
 
 #define __set_errno(val) do { errno = val; } while (0)
 
diff --git a/lib/errno.c b/lib/errno.c
index 8330a8fd14..ca0c756bd9 100644
--- a/lib/errno.c
+++ b/lib/errno.c
@@ -1 +1,3 @@
-int errno = 0;
+#include 
+
+int errno __errno_asm_label = 0;
-- 
2.26.2

[PATCH u-boot v3 18/39] build: link with --build-id=none

[Marek Behún]

Some toolchains are compiled so that they pass a --build-id=something
parameter to the linker implicitly.

This causes U-Boot LTO linking to fail with something like:
  ld: section .note.gnu.build-id LMA ... overlaps section .text LMA ...
because U-Boot's link scripts do not currently handle .note.gnu.build-id
section.

Fix this by explicitly disabling build-id.

Signed-off-by: Marek Behún 
---
 Makefile | 2 ++
 scripts/Makefile.spl | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/Makefile b/Makefile
index 952c165d8f..d806155ede 100644
--- a/Makefile
+++ b/Makefile
@@ -989,6 +989,8 @@ LDFLAGS_u-boot += $(LDFLAGS_FINAL)
 # Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
 LDFLAGS_u-boot += $(call ld-option, --no-dynamic-linker)
 
+LDFLAGS_u-boot += --build-id=none
+
 ifeq ($(CONFIG_ARC)$(CONFIG_NIOS2)$(CONFIG_X86)$(CONFIG_XTENSA),)
 LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE)
 endif
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 9c9d59635d..36a3de815a 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -375,6 +375,8 @@ LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)
 # Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
 LDFLAGS_$(SPL_BIN) += $(call ld-option, --no-dynamic-linker)
 
+LDFLAGS_$(SPL_BIN) += --build-id=none
+
 # Pick the best-match (i.e. SPL_TEXT_BASE for SPL, TPL_TEXT_BASE for TPL)
 ifneq ($(CONFIG_$(SPL_TPL_)TEXT_BASE),)
 LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_$(SPL_TPL_)TEXT_BASE)
-- 
2.26.2

[PATCH u-boot v3 16/39] build: use thin archives instead of incremental linking

[Marek Behún]

Currently we use incremental linking (ld -r) to link several object
files from one directory into one built-in.o object file containing the
linked code from that directory (and its subdirectories).

Linux has, some time ago, moved to thin archives instead.

Thin archives are archives (.a) that do not really contain the object
files, only references to them.

Using thin archives instead of incremental linking
- saves disk space
- apparently works better with dead code elimination
- makes things easier for LTO

The third point is the important one for us. With incremental linking
there are several options how to do LTO, and that would unnecessarily
complicate things.

We have to use the --whole-archive/--no-whole-archive linking option
instead of --start-group/--end-group, otherwise linking may fail because
of unresolved symbols, or the resulting binary will be unusable.

We also need to use the P flag for ar, otherwise final linking may fail.

Signed-off-by: Marek Behún 
---
 Makefile   |  4 ++--
 arch/sandbox/config.mk | 10 +++---
 scripts/Makefile.build | 16 
 scripts/Makefile.spl   |  4 ++--
 4 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/Makefile b/Makefile
index e668940aba..c9b5fac7a9 100644
--- a/Makefile
+++ b/Makefile
@@ -1749,9 +1749,9 @@ ARCH_POSTLINK := $(wildcard 
$(srctree)/arch/$(ARCH)/Makefile.postlink)
 quiet_cmd_u-boot__ ?= LD  $@
   cmd_u-boot__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_u-boot) -o $@  
\
-T u-boot.lds $(u-boot-init)
\
-   --start-group   
\
+   --whole-archive 
\
$(u-boot-main)  
\
-   --end-group 
\
+   --no-whole-archive  
\
$(PLATFORM_LIBS) -Map u-boot.map;   
\
$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
 
diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index 189e9c2b0c..2149771324 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -17,13 +17,17 @@ PLATFORM_CPPFLAGS += $(shell $(SDL_CONFIG) --cflags)
 endif
 
 cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds $(u-boot-init) \
-   -Wl,--start-group $(u-boot-main) -Wl,--end-group \
+   -Wl,--whole-archive \
+   $(u-boot-main) \
+   -Wl,--no-whole-archive \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
 
 cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T u-boot-spl.lds \
$(patsubst $(obj)/%,%,$(u-boot-spl-init)) \
-   -Wl,--start-group $(patsubst $(obj)/%,%,$(u-boot-spl-main)) \
-   $(patsubst $(obj)/%,%,$(u-boot-spl-platdata)) -Wl,--end-group \
+   -Wl,--whole-archive \
+   $(patsubst $(obj)/%,%,$(u-boot-spl-main)) \
+   $(patsubst $(obj)/%,%,$(u-boot-spl-platdata)) \
+   -Wl,--no-whole-archive \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot-spl.map -Wl,--gc-sections)
 
 CONFIG_ARCH_DEVICE_TREE := sandbox
diff --git a/scripts/Makefile.build b/scripts/Makefile.build
index 705a886cb9..7e59ca54cd 100644
--- a/scripts/Makefile.build
+++ b/scripts/Makefile.build
@@ -331,12 +331,11 @@ $(sort $(subdir-obj-y)): $(subdir-ym) ;
 # Rule to compile a set of .o files into one .o file
 #
 ifdef builtin-target
-quiet_cmd_link_o_target = LD  $@
+quiet_cmd_link_o_target = AR  $@
 # If the list of objects to link is empty, just create an empty built-in.o
 cmd_link_o_target = $(if $(strip $(obj-y)),\
- $(LD) $(ld_flags) -r -o $@ $(filter $(obj-y), $^) \
- $(cmd_secanalysis),\
- rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@)
+ rm -f $@; $(AR) cDPrsT $@ $(filter $(obj-y), $^), \
+ rm -f $@; $(AR) cDPrsT$(KBUILD_ARFLAGS) $@)
 
 $(builtin-target): $(obj-y) FORCE
$(call if_changed,link_o_target)
@@ -362,7 +361,7 @@ $(modorder-target): $(subdir-ym) FORCE
 #
 ifdef lib-target
 quiet_cmd_link_l_target = AR  $@
-cmd_link_l_target = rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@ $(lib-y)
+cmd_link_l_target = rm -f $@; $(AR) cDPrsT$(KBUILD_ARFLAGS) $@ $(lib-y)
 
 $(lib-target): $(lib-y) FORCE
$(call if_changed,link_l_target)
@@ -382,10 +381,11 @@ $(filter $(addprefix $(obj)/, \
 $($(subst $(obj)/,,$(@:.o=-objs)))\
 $($(subst $(obj)/,,$(@:.o=-y, $^)
 
-quiet_cmd_link_multi-y = LD  $@
-cmd_link_multi-y = $(LD) $(ld_flags) -r -o $@ $(link_multi_deps) 
$(cmd_secanalysis)
 
-quiet_cmd_link_multi-m = LD [M]  $@
+quiet_cmd_link_multi-y = AR  $@
+cmd_link_multi-y = rm -f $@; $(AR) cDPrsT$(KBUILD_ARFLAGS) $@ 
$(link_multi_deps)
+
+quiet_cmd_link_multi-m = AR [M]  $@
 cmd_link_multi-m = $(cmd_link_multi-y)
 
 $(multi-used-y): FORCE
di

[PATCH u-boot v3 21/39] sandbox: make LTO available

[Marek Behún]

Make LTO available for sandbox architecture.

Signed-off-by: Marek Behún 
Reviewed-by: Bin Meng 
---
 arch/Kconfig   | 1 +
 arch/sandbox/config.mk | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/arch/Kconfig b/arch/Kconfig
index 27843cd79c..a6dab3e56d 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -101,6 +101,7 @@ config RISCV
 
 config SANDBOX
bool "Sandbox"
+   select ARCH_SUPPORTS_LTO
select BOARD_LATE_INIT
select BZIP2
select CMD_POWEROFF
diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index 2149771324..397b7f252b 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -17,12 +17,14 @@ PLATFORM_CPPFLAGS += $(shell $(SDL_CONFIG) --cflags)
 endif
 
 cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds $(u-boot-init) \
+   $(LTO_FINAL_LDFLAGS) \
-Wl,--whole-archive \
$(u-boot-main) \
-Wl,--no-whole-archive \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
 
 cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T u-boot-spl.lds \
+   $(LTO_FINAL_LDFLAGS) \
$(patsubst $(obj)/%,%,$(u-boot-spl-init)) \
-Wl,--whole-archive \
$(patsubst $(obj)/%,%,$(u-boot-spl-main)) \
-- 
2.26.2

[PATCH u-boot v3 20/39] sandbox: use sections instead of symbols for getopt array boundaries

[Marek Behún]

In style of linked lists, instead of declaring symbols for boundaries
of getopt options array in the linker script, declare corresponding
sections and retrieve the boundaries via static inline functions.

Without this clang's LTO produces binary without any getopt options,
because for some reason it thinks that array is empty (start and end
symbols are at the same address).

Signed-off-by: Marek Behún 
---
 arch/sandbox/cpu/os.c   |  3 ++-
 arch/sandbox/cpu/start.c|  3 ++-
 arch/sandbox/cpu/u-boot-spl.lds |  8 +---
 arch/sandbox/cpu/u-boot.lds |  8 +---
 arch/sandbox/include/asm/sections.h | 21 ++---
 5 files changed, 32 insertions(+), 11 deletions(-)

diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 3d8af0a52b..6d4fecee1d 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -327,7 +327,8 @@ static struct option *long_opts;
 
 int os_parse_args(struct sandbox_state *state, int argc, char *argv[])
 {
-   struct sandbox_cmdline_option **sb_opt = __u_boot_sandbox_option_start;
+   struct sandbox_cmdline_option **sb_opt =
+   __u_boot_sandbox_option_start();
size_t num_options = __u_boot_sandbox_option_count();
size_t i;
 
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index 483a264040..05dc04d43a 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -58,7 +58,8 @@ static int h_compare_opt(const void *p1, const void *p2)
 int sandbox_early_getopt_check(void)
 {
struct sandbox_state *state = state_get_current();
-   struct sandbox_cmdline_option **sb_opt = __u_boot_sandbox_option_start;
+   struct sandbox_cmdline_option **sb_opt =
+   __u_boot_sandbox_option_start();
size_t num_options = __u_boot_sandbox_option_count();
size_t i;
int max_arg_len, max_noarg_len;
diff --git a/arch/sandbox/cpu/u-boot-spl.lds b/arch/sandbox/cpu/u-boot-spl.lds
index 649abeb5ee..3a86595e85 100644
--- a/arch/sandbox/cpu/u-boot-spl.lds
+++ b/arch/sandbox/cpu/u-boot-spl.lds
@@ -13,9 +13,11 @@ SECTIONS
KEEP(*(SORT(.u_boot_list*)));
}
 
-   __u_boot_sandbox_option_start = .;
-   _u_boot_sandbox_getopt : { KEEP(*(.u_boot_sandbox_getopt)) }
-   __u_boot_sandbox_option_end = .;
+   _u_boot_sandbox_getopt : {
+   *(.u_boot_sandbox_getopt_start)
+   KEEP(*(.u_boot_sandbox_getopt))
+   *(.u_boot_sandbox_getopt_end)
+   }
 }
 
 INSERT AFTER .data;
diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds
index 936da5e140..1d917a3244 100644
--- a/arch/sandbox/cpu/u-boot.lds
+++ b/arch/sandbox/cpu/u-boot.lds
@@ -13,9 +13,11 @@ SECTIONS
KEEP(*(SORT(.u_boot_list*)));
}
 
-   __u_boot_sandbox_option_start = .;
-   _u_boot_sandbox_getopt : { *(.u_boot_sandbox_getopt) }
-   __u_boot_sandbox_option_end = .;
+   _u_boot_sandbox_getopt : {
+   *(.u_boot_sandbox_getopt_start)
+   *(.u_boot_sandbox_getopt)
+   *(.u_boot_sandbox_getopt_end)
+   }
 
.__efi_runtime_start : {
*(.__efi_runtime_start)
diff --git a/arch/sandbox/include/asm/sections.h 
b/arch/sandbox/include/asm/sections.h
index fbc1bd11a3..f4351ae7db 100644
--- a/arch/sandbox/include/asm/sections.h
+++ b/arch/sandbox/include/asm/sections.h
@@ -13,12 +13,27 @@
 
 struct sandbox_cmdline_option;
 
-extern struct sandbox_cmdline_option *__u_boot_sandbox_option_start[],
-   *__u_boot_sandbox_option_end[];
+static inline struct sandbox_cmdline_option **
+__u_boot_sandbox_option_start(void)
+{
+   static char start[0] __aligned(4) __attribute__((unused))
+   __section(".u_boot_sandbox_getopt_start");
+
+   return (struct sandbox_cmdline_option **)&start;
+}
+
+static inline struct sandbox_cmdline_option **
+__u_boot_sandbox_option_end(void)
+{
+   static char end[0] __aligned(4) __attribute__((unused))
+   __section(".u_boot_sandbox_getopt_end");
+
+   return (struct sandbox_cmdline_option **)&end;
+}
 
 static inline size_t __u_boot_sandbox_option_count(void)
 {
-   return __u_boot_sandbox_option_end - __u_boot_sandbox_option_start;
+   return __u_boot_sandbox_option_end() - __u_boot_sandbox_option_start();
 }
 
 #endif
-- 
2.26.2

[PATCH u-boot v3 17/39] build: support building with Link Time Optimizations

[Marek Behún]

Add plumbing for building U-Boot with Link Time Optimizations.

When building with LTO, $(PLATFORM_LIBS) has to be in --whole-archive /
--no-whole-archive group, otherwise some functions declared in assembly
may not be resolved and linking may fail.

Signed-off-by: Marek Behún 
---
 Kbuild   |  2 ++
 Kconfig  | 24 
 Makefile | 37 +
 scripts/Makefile.lib |  3 +++
 scripts/Makefile.spl | 17 +
 5 files changed, 83 insertions(+)

diff --git a/Kbuild b/Kbuild
index 1eac091594..bf52e54051 100644
--- a/Kbuild
+++ b/Kbuild
@@ -10,6 +10,8 @@ generic-offsets-file := 
include/generated/generic-asm-offsets.h
 always  := $(generic-offsets-file)
 targets := lib/asm-offsets.s
 
+CFLAGS_REMOVE_asm-offsets.o := $(LTO_CFLAGS)
+
 $(obj)/$(generic-offsets-file): $(obj)/lib/asm-offsets.s FORCE
$(call filechk,offsets,__GENERIC_ASM_OFFSETS_H__)
 
diff --git a/Kconfig b/Kconfig
index 86f0a39bb0..f8c1a77bed 100644
--- a/Kconfig
+++ b/Kconfig
@@ -85,6 +85,30 @@ config SPL_OPTIMIZE_INLINING
  do what it thinks is best, which is desirable in some cases for size
  reasons.
 
+config ARCH_SUPPORTS_LTO
+   bool
+
+config LTO
+   bool "Enable Link Time Optimizations"
+   depends on ARCH_SUPPORTS_LTO
+   default n
+   help
+ This option enables Link Time Optimization (LTO), a mechanism which
+ allows the compiler to optimize between different compilation units.
+
+ This can optimize away dead code paths, resulting in smaller binary
+ size (if CC_OPTIMIZE_FOR_SIZE is enabled).
+
+ This option is not available for every architecture and may
+ introduce bugs.
+
+ Currently, when compiling with GCC, due to a weird bug regarding
+ jobserver, the final linking will not respect make's --jobs argument.
+ Instead all available processors will be used (as reported by the
+ nproc command).
+
+ If unsure, say n.
+
 config TPL_OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in TPL"
depends on TPL
diff --git a/Makefile b/Makefile
index c9b5fac7a9..952c165d8f 100644
--- a/Makefile
+++ b/Makefile
@@ -677,6 +677,28 @@ else
 KBUILD_CFLAGS  += -O2
 endif
 
+LTO_CFLAGS :=
+LTO_FINAL_LDFLAGS :=
+export LTO_CFLAGS LTO_FINAL_LDFLAGS
+ifdef CONFIG_LTO
+   ifeq ($(cc-name),clang)
+   LTO_CFLAGS  += -flto
+   LTO_FINAL_LDFLAGS   += -flto
+   else
+   NPROC   := $(shell nproc 2>/dev/null || echo 1)
+   LTO_CFLAGS  += -flto=$(NPROC)
+   LTO_FINAL_LDFLAGS   += -fuse-linker-plugin -flto=$(NPROC)
+
+   # use plugin aware tools
+   AR  = $(CROSS_COMPILE)gcc-ar
+   NM  = $(CROSS_COMPILE)gcc-nm
+   endif
+
+   CFLAGS_NON_EFI  += $(LTO_CFLAGS)
+
+   KBUILD_CFLAGS   += $(LTO_CFLAGS)
+endif
+
 KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
 KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks)
 
@@ -1746,6 +1768,20 @@ ARCH_POSTLINK := $(wildcard 
$(srctree)/arch/$(ARCH)/Makefile.postlink)
 
 # Rule to link u-boot
 # May be overridden by arch/$(ARCH)/config.mk
+ifdef CONFIG_LTO
+quiet_cmd_u-boot__ ?= LTO $@
+  cmd_u-boot__ ?=  
\
+   $(CC) -nostdlib -nostartfiles   
\
+   $(LTO_FINAL_LDFLAGS) $(c_flags) 
\
+   $(KBUILD_LDFLAGS:%=-Wl,%) $(LDFLAGS_u-boot:%=-Wl,%) -o $@   
\
+   -T u-boot.lds $(u-boot-init)
\
+   -Wl,--whole-archive 
\
+   $(u-boot-main)  
\
+   $(PLATFORM_LIBS)
\
+   -Wl,--no-whole-archive  
\
+   -Wl,-Map,u-boot.map;
\
+   $(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
+else
 quiet_cmd_u-boot__ ?= LD  $@
   cmd_u-boot__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_u-boot) -o $@  
\
-T u-boot.lds $(u-boot-init)
\
@@ -1754,6 +1790,7 @@ quiet_cmd_u-boot__ ?= LD  $@
--no-whole-archive  
\
$(PLATFORM_LIBS) -Map u-boot.map;   
\
$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
+endif
 
 quiet_cmd_smap = GEN common/system_map.o
 cmd_smap = \
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 78543c6dd1..78b

[PATCH u-boot v3 22/39] sandbox: enable LTO by default

[Marek Behún]

Build sandbox targets with LTO by default.

Signed-off-by: Marek Behún 
Reviewed-by: Bin Meng 
---
 arch/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/Kconfig b/arch/Kconfig
index a6dab3e56d..b884b7b248 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -123,6 +123,7 @@ config SANDBOX
select SYSRESET_CMD_POWEROFF
imply BITREVERSE
select BLOBLIST
+   imply LTO
imply CMD_DM
imply CMD_EXCEPTION
imply CMD_GETTIME
-- 
2.26.2

[PATCH u-boot v3 23/39] ARM: global_data: make set_gd() work for armv5 and armv6

[Marek Behún]

The Thumb instruction `ldr` is able to move high registers only from
armv7. For armv5 and armv6 we have to use `mov`.

Signed-off-by: Marek Behún 
---
 arch/arm/include/asm/global_data.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/global_data.h 
b/arch/arm/include/asm/global_data.h
index fba655f3b9..bb82efafa6 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -122,8 +122,10 @@ static inline void set_gd(volatile gd_t *gd_ptr)
 {
 #ifdef CONFIG_ARM64
__asm__ volatile("ldr x18, %0\n" : : "m"(gd_ptr));
-#else
+#elif __ARM_ARCH >= 7
__asm__ volatile("ldr r9, %0\n" : : "m"(gd_ptr));
+#else
+   __asm__ volatile("mov r9, %0\n" : : "r"(gd_ptr));
 #endif
 }
 
-- 
2.26.2

[PATCH u-boot v3 25/39] ARM: fix LTO build for some thumb-interwork cases

[Marek Behún]

Fix LTO build for some thumb-interwork usecases (such as for
da850evm_defconfig), where inline assmebly such as
  mrc p15,0,r2,c1,c0,0
causes the compiler to fail during LTO linking with
  Error: selected processor does not support `mrc p15,0,r2,c1,c0,0'
 in Thumb mode

Signed-off-by: Marek Behún 
---
 arch/arm/cpu/arm926ejs/Makefile | 2 ++
 arch/arm/lib/Makefile   | 1 +
 2 files changed, 3 insertions(+)

diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index af63d5cc5e..98aafe805a 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -25,6 +25,8 @@ ifndef CONFIG_HAS_THUMB2
 
 CFLAGS_cpu.o := -marm
 CFLAGS_cache.o := -marm
+CFLAGS_REMOVE_cpu.o := $(LTO_CFLAGS)
+CFLAGS_REMOVE_cache.o := $(LTO_CFLAGS)
 
 endif
 endif
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 27b12e7f2b..61bef1d5af 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -64,6 +64,7 @@ endif
 
 obj-y  += cache.o
 obj-$(CONFIG_SYS_ARM_CACHE_CP15)   += cache-cp15.o
+CFLAGS_REMOVE_cache-cp15.o := $(LTO_CFLAGS)
 
 obj-y  += psci-dt.o
 
-- 
2.26.2

[PATCH u-boot v3 24/39] ARM: make gd a function call for LTO and set via set_gd()

[Marek Behún]

On ARM, the gd pointer is stored in registers r9 / x18. For this the
-ffixed-r9 / -ffixed-x18 flag is used when compiling, but using global
register variables causes errors when building with LTO, and these
errors are very difficult to overcome.

Richard Biener says [1]:
  Note that global register vars shouldn't be used with LTO and if they
  are restricted to just a few compilation units the recommended fix is
  to build those CUs without -flto.

We cannot do this for U-Boot since all CUs use -ffixed-reg flag.

It seems that with LTO we could in fact store the gd pointer differently
and gain performance or size benefit by allowing the compiler to use
r9 / x18. But this would need more work.

So for now, when building with LTO, go the clang way, and instead of
declaring gd a global register variable, we make it a function call via
macro.

[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68384

Signed-off-by: Marek Behún 
---
 arch/arm/cpu/arm926ejs/mxs/spl_boot.c |  2 +-
 arch/arm/include/asm/global_data.h|  2 +-
 arch/arm/mach-exynos/spl_boot.c   |  2 +-
 arch/arm/mach-imx/imx8m/soc.c |  2 +-
 arch/arm/mach-imx/spl_imx_romapi.c| 16 
 5 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c 
b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index a16a15e79d..66406cc857 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -122,7 +122,7 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t 
*resptr,
 {
struct mxs_spl_data *data = MXS_SPL_DATA;
uint8_t bootmode = mxs_get_bootmode_index();
-   gd = &gdata;
+   set_gd(&gdata);
 
mxs_spl_fixup_vectors();
 
diff --git a/arch/arm/include/asm/global_data.h 
b/arch/arm/include/asm/global_data.h
index bb82efafa6..2aff1c467c 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -91,7 +91,7 @@ struct arch_global_data {
 
 #include 
 
-#ifdef __clang__
+#if defined(__clang__) || defined(CONFIG_LTO)
 
 #define DECLARE_GLOBAL_DATA_PTR
 #define gd get_gd()
diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c
index 27f0dac182..722449881a 100644
--- a/arch/arm/mach-exynos/spl_boot.c
+++ b/arch/arm/mach-exynos/spl_boot.c
@@ -279,7 +279,7 @@ void memzero(void *s, size_t n)
  */
 static void setup_global_data(gd_t *gdp)
 {
-   gd = gdp;
+   set_gd(gdp);
memzero((void *)gd, sizeof(gd_t));
gd->flags |= GD_FLG_RELOC;
gd->baudrate = CONFIG_BAUDRATE;
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 5f37282ff1..15d0da7060 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -509,7 +509,7 @@ enum boot_device get_boot_device(void)
 
ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
  ((uintptr_t)&boot) ^ QUERY_BT_DEV);
-   gd = pgd;
+   set_gd(pgd);
 
if (ret != ROM_API_OKAY) {
puts("ROMAPI: failure at query_boot_info\n");
diff --git a/arch/arm/mach-imx/spl_imx_romapi.c 
b/arch/arm/mach-imx/spl_imx_romapi.c
index 9f4d95982e..d2085dabd3 100644
--- a/arch/arm/mach-imx/spl_imx_romapi.c
+++ b/arch/arm/mach-imx/spl_imx_romapi.c
@@ -45,7 +45,7 @@ static ulong spl_romapi_read_seekable(struct spl_load_info 
*load,
 
ret = g_rom_api->download_image(buf, offset, byte,
((uintptr_t)buf) ^ offset ^ byte);
-   gd = pgd;
+   set_gd(pgd);
 
if (ret == ROM_API_OKAY)
return count;
@@ -73,7 +73,7 @@ static int spl_romapi_load_image_seekable(struct 
spl_image_info *spl_image,
ret |= g_rom_api->query_boot_infor(QUERY_IMG_OFF, &image_offset,
   ((uintptr_t)&image_offset) ^ 
QUERY_IMG_OFF);
 
-   gd = pgd;
+   set_gd(pgd);
 
if (ret != ROM_API_OKAY) {
puts("ROMAPI: Failure query boot infor pagesize/offset\n");
@@ -94,7 +94,7 @@ static int spl_romapi_load_image_seekable(struct 
spl_image_info *spl_image,
size = ALIGN(sizeof(struct image_header), pagesize);
ret = g_rom_api->download_image((u8 *)header, offset, size,
((uintptr_t)header) ^ offset ^ size);
-   gd = pgd;
+   set_gd(pgd);
 
if (ret != ROM_API_OKAY) {
printf("ROMAPI: download failure offset 0x%x size 0x%x\n",
@@ -180,7 +180,7 @@ static int spl_romapi_load_image_stream(struct 
spl_image_info *spl_image,
 
ret = g_rom_api->query_boot_infor(QUERY_PAGE_SZ, &pagesize,
  ((uintptr_t)&pagesize) ^ 
QUERY_PAGE_SZ);
-   gd = pgd;
+   set_gd(pgd);
 
if (ret != ROM_API_OKAY)
puts("failure at query_boot_info\n");
@@ -192,7 +192,7 @@ static int spl_romapi_load_image_stream(struct 
spl_image_info *spl_image,
for (i = 0; i < 640; i++) {
 

[PATCH u-boot v3 26/39] ARM: fix LTO for imx28_xea

[Marek Behún]

When imx28_xea_defconfig is built with LTO, the compiler complains about
the two different declarations of _start:
   include/asm-generic/sections.has  extern void _start(void);
   arch/arm/cpu/arm926ejs/mxs/mxs.c  as  extern uint32_t _start;

Fix this.

Signed-off-by: Marek Behún 
Reviewed-by: Bin Meng 
---
 arch/arm/cpu/arm926ejs/mxs/mxs.c  | 2 +-
 arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index c9362136fb..81805e1955 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -25,6 +25,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -98,7 +99,6 @@ int arch_cpu_init(void)
 {
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
-   extern uint32_t _start;
 
mx28_fixup_vt((uint32_t)&_start);
 
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c 
b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index 66406cc857..0a8985b90a 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "mxs_init.h"
@@ -100,7 +101,6 @@ static void mxs_spl_fixup_vectors(void)
 * thus this fixup. Our vectoring table is PIC, so copying is
 * fine.
 */
-   extern uint32_t _start;
 
/* cppcheck-suppress nullPointer */
memcpy(0x0, &_start, 0x60);
-- 
2.26.2

[PATCH u-boot v3 27/39] ARM: fix LTO for apf27

[Marek Behún]

When apf27_defconfig is built with LTO, linking complains about
undefined reference to `nand_boot`. This is because it is referenced
from inline assembly. Make it visible.

Signed-off-by: Marek Behún 
---
 drivers/mtd/nand/raw/mxc_nand_spl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/mxc_nand_spl.c 
b/drivers/mtd/nand/raw/mxc_nand_spl.c
index e1e542519d..2f054b60ed 100644
--- a/drivers/mtd/nand/raw/mxc_nand_spl.c
+++ b/drivers/mtd/nand/raw/mxc_nand_spl.c
@@ -326,7 +326,7 @@ int nand_spl_load_image(uint32_t from, unsigned int size, 
void *buf)
  * configured and available since this code loads the main U-Boot image
  * from NAND into SDRAM and starts it from there.
  */
-void nand_boot(void)
+__used void nand_boot(void)
 {
__attribute__((noreturn)) void (*uboot)(void);
 
-- 
2.26.2

[PATCH u-boot v3 28/39] ARM: fix LTO for keystone

[Marek Behún]

When building keystone with LTO the compiler complains:
  Error: selected processor does not support `smc #0' in Thumb mode

Fix this by removing -flto for the file implementing these SMC calls.

Signed-off-by: Marek Behún 
---
 arch/arm/mach-keystone/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile
index 3e076e12ec..6c7c25090a 100644
--- a/arch/arm/mach-keystone/Makefile
+++ b/arch/arm/mach-keystone/Makefile
@@ -9,6 +9,7 @@ obj-y   += init.o
 obj-y  += psc.o
 obj-y  += clock.o
 obj-y  += mon.o
+CFLAGS_REMOVE_mon.o := $(LTO_CFLAGS)
 ifndef CONFIG_SPL_BUILD
 obj-y  += cmd_clock.o
 obj-y  += cmd_mon.o
-- 
2.26.2

[PATCH u-boot v3 32/39] ARM: fix LTO for rockchip and samsung

[Marek Behún]

When building with LTO, the compiler complains about type mismatch of
function usb_gadget_handle_interrupts(). This function is defined
without parameters in files
  arch/arm/mach-rockchip/board.c
  board/samsung/common/exynos5-dt.c
but it should have one parameter, int index.

Fix this.

Signed-off-by: Marek Behún 
Reviewed-by: Bin Meng 
---
 arch/arm/mach-rockchip/board.c| 2 +-
 board/samsung/common/exynos5-dt.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index c386b52987..5304eb055c 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -139,7 +139,7 @@ static struct dwc3_device dwc3_device_data = {
.hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
 };
 
-int usb_gadget_handle_interrupts(void)
+int usb_gadget_handle_interrupts(int index)
 {
dwc3_uboot_handle_interrupt(0);
return 0;
diff --git a/board/samsung/common/exynos5-dt.c 
b/board/samsung/common/exynos5-dt.c
index 4463cdcb87..1318ea716a 100644
--- a/board/samsung/common/exynos5-dt.c
+++ b/board/samsung/common/exynos5-dt.c
@@ -126,7 +126,7 @@ static struct dwc3_device dwc3_device_data = {
.index = 0,
 };
 
-int usb_gadget_handle_interrupts(void)
+int usb_gadget_handle_interrupts(int index)
 {
dwc3_uboot_handle_interrupt(0);
return 0;
-- 
2.26.2

[PATCH u-boot v3 29/39] ARM: kona: fix clk_bsc_enable() type mismatch for LTO

[Marek Behún]

When building with LTO, the compiler complains about type mismatch of
function clk_bsc_enable() in file:
  arch/arm/cpu/armv7/kona-common/clk-stubs.c
vs other files that define or use this function:
  warning: type of ‘clk_bsc_enable’ does not match original declaration.

Change the type of this function to that of the other usages.

Signed-off-by: Marek Behún 
Reviewed-by: Bin Meng 
---
 arch/arm/cpu/armv7/kona-common/clk-stubs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/kona-common/clk-stubs.c 
b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
index 2dfa3f7e73..4eddaca887 100644
--- a/arch/arm/cpu/armv7/kona-common/clk-stubs.c
+++ b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
@@ -14,7 +14,7 @@ int __weak clk_sdio_enable(void *base, u32 rate, u32 
*actual_ratep)
return 0;
 }
 
-int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep)
+int __weak clk_bsc_enable(void *base)
 {
return 0;
 }
-- 
2.26.2

[PATCH u-boot v3 30/39] ARM: imx8m: fix imx_eqos_txclk_set_rate() type mismatch for LTO

[Marek Behún]

When building imx8mp_evk_defconfig with LTO, the compiler complains
about type mismatch of function imx_eqos_txclk_set_rate() in file
  drivers/net/dwc_eth_qos.c:845:12
which contains a weak definition of this function, vs file
  arch/arm/mach-imx/imx8m/clock_imx8mm.c
which contains an implementation.

Change the type of this function in the implementation to fix this.

Signed-off-by: Marek Behún 
Reviewed-by: Bin Meng 
---
 arch/arm/mach-imx/imx8m/clock_imx8mm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c 
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 4024dafca1..554ff0eaca 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -838,7 +838,7 @@ int set_clk_eqos(enum enet_freq type)
return 0;
 }
 
-int imx_eqos_txclk_set_rate(u32 rate)
+int imx_eqos_txclk_set_rate(ulong rate)
 {
u32 val;
u32 eqos_post_div;
-- 
2.26.2

[PATCH u-boot v3 34/39] armv8: SPL: discard relocation information

[Marek Behún]

For some reason when building SPL for ARMv8 with LTO, the relocation
information is not discarded.

Discard it explicitly in the linker script.

This fixes LTO build for imx8mm_venice_defconfig.

Signed-off-by: Marek Behún 
---
 arch/arm/cpu/armv8/u-boot-spl.lds | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds 
b/arch/arm/cpu/armv8/u-boot-spl.lds
index 0e67ab09d7..9edb662b09 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -77,6 +77,7 @@ SECTIONS
KEEP(*(.__bss_end));
} >.sdram
 
+   /DISCARD/ : { *(.rela*) }
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
-- 
2.26.2

[PATCH u-boot v3 31/39] ARM: fix LTO for seaboard

[Marek Behún]

When seaboard_defconfig is compiled with LTO, the compiler complains
about some instructions not being supported in ARM mode.

This is caused by arch/arm/mach-tegra/tegra20/warmboot_avp.c having
different CFLAGS declared in Makefile. This file needs to be compiled
without LTO.

Fix this by removing -flto for this file.

Signed-off-by: Marek Behún 
---
 arch/arm/mach-tegra/tegra20/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-tegra/tegra20/Makefile 
b/arch/arm/mach-tegra/tegra20/Makefile
index faaf30d068..bb17c90cca 100644
--- a/arch/arm/mach-tegra/tegra20/Makefile
+++ b/arch/arm/mach-tegra/tegra20/Makefile
@@ -10,6 +10,7 @@ endif
 # flags for any startup files it might use.
 CFLAGS_warmboot_avp.o = -march=armv4t -U__LINUX_ARM_ARCH__ \
-D__LINUX_ARM_ARCH__=4
+CFLAGS_REMOVE_warmboot_avp.o := $(LTO_CFLAGS)
 
 obj-y  += clock.o funcmux.o pinmux.o
 obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
-- 
2.26.2

[PATCH u-boot v3 35/39] ata: ahci: fix ahci_link_up() type mismatch for LTO

[Marek Behún]

When building highbank_defconfig with LTO, the compiler complains about
type mismatch of function ahci_link_up().

The third parameter of this function is of type u8 in
drivers/ata/ahci.c, but of type int in board/highbank/ahci.c.

There is no reason in using u8, and the code using this function
actually passes an int variable into the function (so it is implicitly
converted to u8).

Change the type of this parameter to int in drivers/ata/ahci.c.

Signed-off-by: Marek Behún 
Reviewed-by: Bin Meng 
---
 drivers/ata/ahci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 2ef21ec508..3d16bc21a8 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -110,7 +110,7 @@ static int waiting_for_cmd_completed(void __iomem *offset,
return (i < timeout_msec) ? 0 : -1;
 }
 
-int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port)
+int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, int port)
 {
u32 tmp;
int j = 0;
-- 
2.26.2

[PATCH u-boot v3 33/39] ARM: omap3: fix LTO for DM3730 (and possibly other omap3 boards)

[Marek Behún]

Adam Ford says that DM3730 needs board.c compiled without LTO flags.

Signed-off-by: Marek Behún 
Tested-by: Adam Ford 
---
 arch/arm/mach-omap2/omap3/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-omap2/omap3/Makefile 
b/arch/arm/mach-omap2/omap3/Makefile
index 91ed8ebc9f..151bdf6ebc 100644
--- a/arch/arm/mach-omap2/omap3/Makefile
+++ b/arch/arm/mach-omap2/omap3/Makefile
@@ -9,6 +9,7 @@ CFLAGS_clock.o += -marm
 obj-y  := lowlevel_init.o
 
 obj-y  += board.o
+CFLAGS_REMOVE_board.o := $(LTO_CFLAGS)
 obj-y  += boot.o
 obj-y  += clock.o
 obj-y  += sys_info.o
-- 
2.26.2

[PATCH u-boot v3 37/39] ARM: don't use -ffunction-sections/-fdata-sections with LTO build

[Marek Behún]

When building with LTO, using -ffunction-sections/-fdata-sections is not
useful anymore.

Signed-off-by: Marek Behún 
---
 arch/arm/config.mk | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 4153f7e371..2b2c6ad2e5 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -15,8 +15,12 @@ CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections 
-fdata-sections
 CFLAGS_EFI := -fpic -fshort-wchar
 
 LDFLAGS_FINAL += --gc-sections
-PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
--fno-common -ffixed-r9
+
+ifndef CONFIG_LTO
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+endif
+
+PLATFORM_RELFLAGS += -fno-common -ffixed-r9
 PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
   $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
 
-- 
2.26.2

[PATCH u-boot v3 36/39] ARM: make LTO available

[Marek Behún]

Make LTO available for ARM architecture.

Signed-off-by: Marek Behún 
---
 arch/Kconfig  | 1 +
 arch/arm/lib/Makefile | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/arch/Kconfig b/arch/Kconfig
index b884b7b248..bf4b8afcb4 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -33,6 +33,7 @@ config ARC
 
 config ARM
bool "ARM architecture"
+   select ARCH_SUPPORTS_LTO
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC if !ARM64
select SUPPORT_OF_CONTROL
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 61bef1d5af..7f66332715 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -45,6 +45,8 @@ obj-$(CONFIG_SEMIHOSTING) += semihosting.o
 
 obj-y  += bdinfo.o
 obj-y  += sections.o
+CFLAGS_REMOVE_sections.o := $(LTO_CFLAGS)
+
 obj-y  += stack.o
 ifdef CONFIG_CPU_V7M
 obj-y  += interrupts_m.o
-- 
2.26.2

[PATCH u-boot v3 38/39] ARM: don't use --gc-sections with LTO when using private libgcc

[Marek Behún]

When using LTO, we can throw away the --gc-sections flag, but only if
using private libgcc.

When using system's libgcc, --gc-sections is still needed, otherwise
linking will fail due to undefined references to libc's symbols.

Signed-off-by: Marek Behún 
---
 arch/arm/config.mk | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 2b2c6ad2e5..68745d489f 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -14,7 +14,9 @@ endif
 CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections
 CFLAGS_EFI := -fpic -fshort-wchar
 
+ifneq ($(CONFIG_LTO)$(CONFIG_USE_PRIVATE_LIBGCC),yy)
 LDFLAGS_FINAL += --gc-sections
+endif
 
 ifndef CONFIG_LTO
 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
-- 
2.26.2

[PATCH u-boot v3 39/39] ARM: enable LTO for some boards

[Marek Behún]

Enable LTO for some boards that were tested by people on U-Boot Mailing
List.

Signed-off-by: Marek Behún 
Tested-by: Adam Ford 
Tested-by: Pali Rohár 
Tested-by: Tim Harvey 
---
 configs/am3517_evm_defconfig  | 1 +
 configs/da850evm_defconfig| 1 +
 configs/da850evm_direct_nor_defconfig | 1 +
 configs/da850evm_nand_defconfig   | 1 +
 configs/imx6q_logic_defconfig | 1 +
 configs/imx8mm_beacon_defconfig   | 1 +
 configs/imx8mm_venice_defconfig   | 1 +
 configs/imx8mn_beacon_2g_defconfig| 1 +
 configs/imx8mn_beacon_defconfig   | 1 +
 configs/nokia_rx51_defconfig  | 1 +
 configs/omap3_logic_defconfig | 1 +
 configs/r8a774a1_beacon_defconfig | 1 +
 configs/r8a774b1_beacon_defconfig | 1 +
 configs/r8a774e1_beacon_defconfig | 1 +
 configs/turris_mox_defconfig  | 1 +
 configs/turris_omnia_defconfig| 1 +
 16 files changed, 16 insertions(+)

diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index 0bc7bf74f9..5ff1836808 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -1,3 +1,4 @@
+CONFIG_LTO=y
 CONFIG_ARM=y
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 # CONFIG_SPL_USE_ARCH_MEMSET is not set
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 26e76a2929..6ff5e21bc6 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -1,3 +1,4 @@
+CONFIG_LTO=y
 CONFIG_ARM=y
 CONFIG_SYS_THUMB_BUILD=y
 CONFIG_ARCH_DAVINCI=y
diff --git a/configs/da850evm_direct_nor_defconfig 
b/configs/da850evm_direct_nor_defconfig
index d3860a963d..06c7ce7c47 100644
--- a/configs/da850evm_direct_nor_defconfig
+++ b/configs/da850evm_direct_nor_defconfig
@@ -1,3 +1,4 @@
+CONFIG_LTO=y
 CONFIG_ARM=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_ARCH_DAVINCI=y
diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig
index 0d0e9a148d..be737564e1 100644
--- a/configs/da850evm_nand_defconfig
+++ b/configs/da850evm_nand_defconfig
@@ -1,3 +1,4 @@
+CONFIG_LTO=y
 CONFIG_ARM=y
 CONFIG_SYS_THUMB_BUILD=y
 CONFIG_ARCH_DAVINCI=y
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index 36dc24d080..0f8aea6983 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -1,3 +1,4 @@
+CONFIG_LTO=y
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x1780
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index 045b19f4f3..e8bb44eea6 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -1,3 +1,4 @@
+CONFIG_LTO=y
 CONFIG_ARM=y
 CONFIG_ARCH_IMX8M=y
 CONFIG_SYS_TEXT_BASE=0x4020
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index a15c3641f6..dff8f64540 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -1,3 +1,4 @@
+CONFIG_LTO=y
 CONFIG_ARM=y
 CONFIG_ARCH_IMX8M=y
 CONFIG_SYS_TEXT_BASE=0x4020
diff --git a/configs/imx8mn_beacon_2g_defconfig 
b/configs/imx8mn_beacon_2g_defconfig
index 58b8e49486..1c8cbc2c89 100644
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -1,3 +1,4 @@
+CONFIG_LTO=y
 CONFIG_ARM=y
 CONFIG_ARCH_IMX8M=y
 CONFIG_SYS_TEXT_BASE=0x4020
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index d6a3385d8d..6457b9409a 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -1,3 +1,4 @@
+CONFIG_LTO=y
 CONFIG_ARM=y
 CONFIG_ARCH_IMX8M=y
 CONFIG_SYS_TEXT_BASE=0x4020
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index 312ca3a1a9..85ca627790 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -1,3 +1,4 @@
+CONFIG_LTO=y
 CONFIG_ARM=y
 # CONFIG_SYS_THUMB_BUILD is not set
 CONFIG_ARCH_OMAP2PLUS=y
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 5414880baa..af1f7e026a 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -1,3 +1,4 @@
+CONFIG_LTO=y
 CONFIG_ARM=y
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 # CONFIG_SPL_USE_ARCH_MEMSET is not set
diff --git a/configs/r8a774a1_beacon_defconfig 
b/configs/r8a774a1_beacon_defconfig
index 2f45edd92e..9dd5d9192e 100644
--- a/configs/r8a774a1_beacon_defconfig
+++ b/configs/r8a774a1_beacon_defconfig
@@ -1,3 +1,4 @@
+CONFIG_LTO=y
 CONFIG_ARM=y
 CONFIG_ARCH_RMOBILE=y
 CONFIG_SYS_TEXT_BASE=0x5000
diff --git a/configs/r8a774b1_beacon_defconfig 
b/configs/r8a774b1_beacon_defconfig
index ca514bb1aa..b7d7f23f5a 100644
--- a/configs/r8a774b1_beacon_defconfig
+++ b/configs/r8a774b1_beacon_defconfig
@@ -1,3 +1,4 @@
+CONFIG_LTO=y
 CONFIG_ARM=y
 CONFIG_ARCH_RMOBILE=y
 CONFIG_SYS_TEXT_BASE=0x5000
diff --git a/configs/r8a774e1_beacon_defconfig 
b/configs/r8a774e1_beacon_defconfig
index b89729d92a..3e44edf29f 100644
--- a/configs/r8a774e1_beacon_defconfig
+++ b/configs/r8a774e1_beacon_defconfig
@@ -1,3 +1,4 @@
+CONFIG_LTO=y
 CONFIG_ARM=y
 CONFIG_ARCH_RMOB

[PATCH] dm: spi: Prevent setting a speed of 0 Hz in spi_post_probe

[Michal Simek]

The commit 12bfb2e05fc2 ("dm: spi: prevent setting a speed of 0 Hz")
changes default value from 0 to SPI_DEFAULT_SPEED_HZ but spi_post_probe()
hasn't been updated in the same way. It should be also update to be aligned
with previous patch.

Fixes: 12bfb2e05fc2 ("dm: spi: prevent setting a speed of 0 Hz")
Signed-off-by: Michal Simek 
---

 drivers/spi/spi-uclass.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 7155d4aebd6d..dd2c82165684 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -178,7 +178,8 @@ static int spi_post_probe(struct udevice *bus)
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
 
-   spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
+   spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency",
+  SPI_DEFAULT_SPEED_HZ);
 #endif
 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
struct dm_spi_ops *ops = spi_get_ops(bus);
-- 
2.30.1

Ficus EE not working / supported ?

[Ezequiel Garcia]

Hi Mani, Kever,

I tried to bringup (again) my Ficus board, but I've been unable to
boot a kernel.

Seems my old u-boot branch doesn't want to boot, and the only U-Boot I managed
to boot is some recent one (which I guess is better than having an ancient one).

Now, doc/board/rockchip/rockchip.rst mentions TPL but Ficus defconfig
isn't updated
to use that. So I'm using rock960-rk3399_defconfig, with ethernet enabled,
the issue is I can't boot any kernel with that. Seems it hangs up very early,
and doesn't even want to output anything on earlyconsole.

I was wondering if maybe this rings a bell? Maybe DDR setup?

U-Boot TPL 2021.01-dirty (Mar 15 2021 - 17:46:11)
Channel 0: DDR3, 800MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
Channel 1: DDR3, 800MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
256B stride
Trying to boot from BOOTROM
Returning to boot ROM...

U-Boot SPL 2021.01-dirty (Mar 15 2021 - 17:46:11 -0300)
Trying to boot from MMC1
cannot find image node 'atf_1': -1


U-Boot 2021.01-dirty (Mar 15 2021 - 17:46:11 -0300)

SoC: Rockchip rk3399
Reset cause: POR
Model: 96boards RK3399 Ficus
DRAM:  2 GiB
PMIC:  RK808
MMC:   mmc@fe31: 2, mmc@fe32: 1, sdhci@fe33: 0
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Model: 96boards RK3399 Ficus
Net:
Warning: ethernet@fe30 (eth0) using random MAC address - f2:a3:4d:58:42:dd
eth0: ethernet@fe30
starting USB...


rock960 => setenv ipaddr 192.168.0.20
rock960 => setenv ipaddr 192.168.0.200
rock960 => setenv bootcmd "tftpboot 0x0200 rk3399-ficus/Image;
tftpboot 0x01f0 rk3399-ficus/rk3399-ficus.dtb; booti 0x0200 -
0x01f0"
rock960 => boot
Speed: 1000, full duplex
Using ethernet@fe30 device
TFTP from server 192.168.0.20; our IP address is 192.168.0.200
Filename 'rk3399-ficus/Image'.
Load address: 0x200
Loading: #
#
#
#
#
#
#
#
#
#
##
5.1 MiB/s
done
Bytes transferred = 9736704 (949200 hex)
Speed: 1000, full duplex
Using ethernet@fe30 device
TFTP from server 192.168.0.20; our IP address is 192.168.0.200
Filename 'rk3399-ficus/rk3399-ficus.dtb'.
Load address: 0x1f0
Loading: 
3.7 MiB/s
done
Bytes transferred = 50911 (c6df hex)
Moving Image from 0x200 to 0x208, end=2a1f000
## Flattened Device Tree blob at 01f0
   Booting using the fdt blob at 0x1f0
Host not halted after 16000 microseconds.
   Loading Device Tree to 79f16000, end 79f256de ... OK

Starting kernel ...

Thanks,
Ezequiel

Re: [PATCH] doc: icicle: Fix incorrect board name in HSS docs

[Sean Anderson]

On 3/16/21 4:51 AM, Heinrich Schuchardt wrote:

On 11.03.21 02:48, Sean Anderson wrote:

The HSS source uses an "mpfs" prefix with the icicle board name. Change our
documentation to match.

Signed-off-by: Sean Anderson 
---

  doc/board/microchip/mpfs_icicle.rst | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/doc/board/microchip/mpfs_icicle.rst 
b/doc/board/microchip/mpfs_icicle.rst
index c71c2f3cab..cd18472542 100644
--- a/doc/board/microchip/mpfs_icicle.rst
+++ b/doc/board/microchip/mpfs_icicle.rst
@@ -63,15 +63,15 @@ Build the HSS (Hart Software Services) - Microchip boot-flow

  .. code-block:: none

-   make BOARD=icicle-kit-es config
+   make BOARD=mpfs-icicle-kit-es config

  Alternatively, copy the default config for Microchip boot-flow.

  .. code-block:: none

-   cp boards/icicle-kit-es/def_config .config
+   cp boards/mpfs-icicle-kit-es/def_config .config


The directory boards/mpfs-icicle-kit-es does not exist.
defconfigs should only exist in configs

The only defconfig for icicle is

configs/microchip_mpfs_icicle_defconfig


This is documentation for compiling the HSS [1] for the polarfire SoC.

[1] https://github.com/polarfire-soc/hart-software-services



Best regards

Heinrich



-2. make BOARD=icicle-kit-es
+2. make BOARD=mpfs-icicle-kit-es
  3. In the Default subdirectory, the standard build will create hss.elf and
 various binary formats (hss.hex and hss.bin).

Re: [PATCH v2 1/9] ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoM

[Patrick DELAUNAY]

Hi Jagan

On 3/15/21 6:32 PM, Jagan Teki wrote:

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

General features:
- STM32MP157A
- Up to 1GB DDR3L
- 4GB eMMC
- 10/100 Ethernet
- USB 2.0 Host/OTG
- I2S
- MIPI DSI to LVDS
- rest of STM32MP157A features

i.Core STM32MP1 needs to mount on top of Engicam baseboards
for creating complete platform solutions.

Linux commit details:

commit <30f9a9da4ee1> ("ARM: dts: stm32: Add Engicam i.Core STM32MP1
SoM")

Add support for it.

Reviewed-by: Patrice Chotard 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- collect Patrice r-b
- add linux dts commit

  arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi | 196 +++
  1 file changed, 196 insertions(+)
  create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi



Reviewed-by: Patrick Delaunay 

Thanks
Patrick

Re: [PATCH v2 2/9] ARM: dts: stm32: Add Engicam i.Core STM32MP1 1X4Gb DDR3

[Patrick DELAUNAY]

Hi Jagan

On 3/15/21 6:32 PM, Jagan Teki wrote:

Engicam i.Core STM32MP1 SODIMM SoM has mounted 1x4Gb DDR3
which has 32bits width 528000Khz frequency.

Add DDR configuration via dtsi.

Reviewed-by: Patrice Chotard 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- collect Patrice r-b

  .../stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi | 119 ++
  1 file changed, 119 insertions(+)
  create mode 100644 arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi

diff --git a/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi 
b/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi
new file mode 100644
index 00..1a45c6fc63
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved
+ */
+
+/*
+ * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
+ * DDR type: DDR3 / DDR3L
+ * DDR width: 32bits
+ * DDR density: 4Gb
+ * System frequency: 528000Khz
+ * Relaxed Timing Mode: false
+ * Address mapping type: RBC
+ *
+ * Save Date: 2019.05.14, save Time: 11:25:16
+ */
+#define DDR_MEM_COMPATIBLE ddr3-icore-1066-888-bin-g-1x4gb-528mhz
+#define DDR_MEM_NAME   "DDR3-DDR3L 32bits 528000Khz"



cosmetic: you can replace Khz by kHz

    (see commit "ARM: dts: stm32: Fix cosmetic typo: use 
'kHz' as kilohertz")


This modification is also requested in CubeMX for generation file.


Reviewed-by: Patrick Delaunay 

Thanks
Patrick

Re: [PATCH] dm: spi: Prevent setting a speed of 0 Hz in spi_post_probe

[Pratyush Yadav]

On 16/03/21 01:33PM, Michal Simek wrote:
> The commit 12bfb2e05fc2 ("dm: spi: prevent setting a speed of 0 Hz")
> changes default value from 0 to SPI_DEFAULT_SPEED_HZ but spi_post_probe()
> hasn't been updated in the same way. It should be also update to be aligned
> with previous patch.
> 
> Fixes: 12bfb2e05fc2 ("dm: spi: prevent setting a speed of 0 Hz")
> Signed-off-by: Michal Simek 

Reviewed-by: Pratyush Yadav 

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.

Re: [PATCH v2 3/9] ARM: stm32: Imply SPL_SPI_LOAD

[Patrick DELAUNAY]

On 3/15/21 6:32 PM, Jagan Teki wrote:

SPI Load isn't mandatory for STM32 builds.

Let's imply instead of select it to get rid of build
issues for non-SPI defconfigs.

Reviewed-by: Patrice Chotard 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- collect Patrice r-b

  arch/arm/mach-stm32mp/Kconfig | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index f538d7cb83..79ffd5191d 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -16,13 +16,13 @@ config SPL
select SPL_REGMAP
select SPL_DM_RESET
select SPL_SERIAL_SUPPORT
-   select SPL_SPI_LOAD
select SPL_SYSCON
select SPL_WATCHDOG_SUPPORT if WATCHDOG
imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
imply SPL_BOOTSTAGE if BOOTSTAGE
imply SPL_DISPLAY_PRINT
imply SPL_LIBDISK_SUPPORT
+   imply SPL_SPI_LOAD


cosmetic: you can add dependency ?

imply SPL_SPI_LOAD if SPL_SPI_SUPPORT

  
  config SYS_SOC

default "stm32mp"



Anyway



Reviewed-by: Patrick Delaunay 

Thanks
Patrick

Re: [PATCH v2 4/9] board: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit

[Patrick DELAUNAY]

On 3/15/21 6:32 PM, Jagan Teki wrote:

Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.

Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

i.Core STM32MP1 needs to mount on top of this Evaluation board for
creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.

Linux dts commit details:

commit  ("ARM: dts: stm32: Add Engicam i.Core STM32MP1
EDIMM2.2 Starter Kit")

Add support for it.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- collect Patrice r-b
- add linux dts commit
- drop CONFIG_BOARD_EARLY_INIT_F

  arch/arm/dts/Makefile |   1 +
  ...mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi |  51 ++
  .../stm32mp157a-icore-stm32mp1-edimm2.2.dts   |  47 ++
  .../stm32mp157a-icore-stm32mp1-u-boot.dtsi| 146 ++
  arch/arm/mach-stm32mp/Kconfig |  20 +++
  board/engicam/stm32mp1/Kconfig|  12 ++
  board/engicam/stm32mp1/MAINTAINERS|   6 +
  board/engicam/stm32mp1/Makefile   |  10 ++
  board/engicam/stm32mp1/spl.c  |  48 ++
  board/engicam/stm32mp1/stm32mp1.c | 125 +++
  ...tm32mp15-icore-stm32mp1-edimm2.2_defconfig |  79 ++
  11 files changed, 545 insertions(+)
  create mode 100644 
arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi
  create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
  create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi
  create mode 100644 board/engicam/stm32mp1/Kconfig
  create mode 100644 board/engicam/stm32mp1/MAINTAINERS
  create mode 100644 board/engicam/stm32mp1/Makefile
  create mode 100644 board/engicam/stm32mp1/spl.c
  create mode 100644 board/engicam/stm32mp1/stm32mp1.c
  create mode 100644 configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig



Reviewed-by: Patrick Delaunay 

Thanks
Patrick

Re: [PATCH v2 5/9] board: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0

[Patrick DELAUNAY]

Hi Jagan,

On 3/15/21 6:32 PM, Jagan Teki wrote:

Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
board.

Genaral features:
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

i.Core STM32MP1 needs to mount on top of this Carrier board for
creating complete i.Core STM32MP1 C.TOUCH 2.0 board.

Linux dts commit details:

commit <6ca2898df59f> ("ARM: dts: stm32: Add Engicam i.Core STM32MP1
C.TOUCH 2.0")

Add support for it.

Reviewed-by: Patrice Chotard 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- collect Patrice r-b
- add linux dts commit
- drop CONFIG_BOARD_EARLY_INIT_F

  arch/arm/dts/Makefile |  1 +
  ...2mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi | 51 
  .../stm32mp157a-icore-stm32mp1-ctouch2.dts| 47 +++
  arch/arm/mach-stm32mp/Kconfig |  5 ++
  board/engicam/stm32mp1/MAINTAINERS|  6 ++
  ...stm32mp15-icore-stm32mp1-ctouch2_defconfig | 79 +++
  6 files changed, 189 insertions(+)
  create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi
  create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
  create mode 100644 configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig



Reviewed-by: Patrick Delaunay 

Thanks
Patrick

Re: [PATCH v2 6/9] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 Micro SoM

[Patrick DELAUNAY]

Hi Jagan,

On 3/15/21 6:32 PM, Jagan Teki wrote:

MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.

General features:
- STM32MP157AAC
- Up to 1GB DDR3L-800
- 512MB Nand flash
- I2S

MicroGEA STM32MP1 needs to mount on top of Engicam MicroDev carrier
boards for creating complete platform solutions.

Linux dts commit details:

commit <0be81dfaeaf8> ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1
SoM")

Add support for it.

Reviewed-by: Patrice Chotard 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- collect Patrice r-b
- add linux dts commit
- drop CONFIG_BOARD_EARLY_INIT_F

  .../dts/stm32mp157a-microgea-stm32mp1.dtsi| 148 ++
  1 file changed, 148 insertions(+)
  create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi


Reviewed-by: Patrick Delaunay 

Thanks
Patrick

Re: [PATCH v2 7/9] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 1X4Gb DDR3

[Patrick DELAUNAY]

Hi Jagan,

On 3/15/21 6:32 PM, Jagan Teki wrote:

Engicam MicroGEA STM32MP1 Micro SOM has mounted 1x4Gb DDR3
which has 16bits width 533Mhz frequency.

Add DDR configurations via dtsi.

Reviewed-by: Patrice Chotard 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- collect Patrice r-b

  ...m32mp15-ddr3-microgea-1x4Gb-1066-binG.dtsi | 121 ++
  1 file changed, 121 insertions(+)
  create mode 100644 arch/arm/dts/stm32mp15-ddr3-microgea-1x4Gb-1066-binG.dtsi

diff --git a/arch/arm/dts/stm32mp15-ddr3-microgea-1x4Gb-1066-binG.dtsi 
b/arch/arm/dts/stm32mp15-ddr3-microgea-1x4Gb-1066-binG.dtsi
new file mode 100644
index 00..950f292abb
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-ddr3-microgea-1x4Gb-1066-binG.dtsi
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * STM32MP157C DK1/DK2 BOARD configuration
+ * 1x DDR3L 4Gb, 16-bit, 533MHz.
+ * Reference used NT5CC256M16DP-DI from NANYA
+ *
+ * DDR type / Platform DDR3/3L
+ * freq533MHz
+ * width   16
+ * datasheet   0  = MT41J256M16-187 / DDR3-1066 bin G
+ * DDR density 4
+ * timing mode optimized
+ * Scheduling/QoS options : type = 2
+ * address mapping : RBC
+ * Tc > + 85C : N
+ */


This file is identical to stm32mp15-ddr3-1x4Gb-1066-binG.dtsi, because 
it is a files generated


with CubeMX with the same parameters.

Do you any reason to duplicate it ?

Do you expect some board-specific tuning or configuration with be 
integrated latter.


If it is not the case, I think you can reuse the file used by 
STMicroelectronics boards DK1/DK2


in the next patch.

#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"

Regards

Patrick

Re: [PATCH v2 8/9] board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 board

[Patrick DELAUNAY]

On 3/15/21 6:32 PM, Jagan Teki wrote:

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

Genaral features:
- Ethernet 10/100
- USB Type A
- Audio Out
- microSD
- LVDS panel connector
- Wifi/BT (option)
- UMTS LTE with sim connector (option)

MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.

MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.

Linux dts commit details:

commit  ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1
MicroDev 2.0 board")

Add support for it.

Signed-off-by: Jagan Teki 
---
Changes for v2:
- collect Patrice r-b
- add linux dts commit
- drop CONFIG_BOARD_EARLY_INIT_F

  arch/arm/dts/Makefile |   1 +
  ...-microgea-stm32mp1-microdev2.0-u-boot.dtsi |  51 
  ...32mp157a-microgea-stm32mp1-microdev2.0.dts |  55 
  .../stm32mp157a-microgea-stm32mp1-u-boot.dtsi | 118 ++
  arch/arm/mach-stm32mp/Kconfig |  20 +++
  board/engicam/stm32mp1/Kconfig|   2 +-
  board/engicam/stm32mp1/MAINTAINERS|   6 +
  ...mp15-microgea-stm32mp1-microdev2_defconfig |  79 
  8 files changed, 331 insertions(+), 1 deletion(-)
  create mode 100644 
arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-u-boot.dtsi
  create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
  create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi
  create mode 100644 configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ce4521b891..64d73b96ef 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -992,6 +992,7 @@ dtb-$(CONFIG_STM32MP15x) += \
stm32mp157a-avenger96.dtb \
stm32mp157a-icore-stm32mp1-ctouch2.dtb \
stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
+   stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
stm32mp157c-dk2.dtb \
stm32mp157c-ed1.dtb \
stm32mp157c-ev1.dtb \

...

diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi 
b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi
new file mode 100644
index 00..32ce31458a
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Amarula Solutions(India)
+ * Author: Jagan Teki 
+ */
+
+#include 
+#include "stm32mp15-u-boot.dtsi"
+#include "stm32mp15-ddr3-microgea-1x4Gb-1066-binG.dtsi"


#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" ?


Anyway:


Reviewed-by: Patrick Delaunay 

Thanks
Patrick

Re: [PATCH u-boot v3 01/39] regmap: fix a serious pointer casting bug

[Pratyush Yadav]

On 16/03/21 01:25PM, Marek Behún wrote:
> There is a serious bug in regmap_read() and regmap_write() functions
> where an uint pointer is cast to (void *) which is then cast to (u8 *),
> (u16 *), (u32 *) or (u64 *), depending on register width of the map.
> 
> For example given a regmap with 16-bit register width the code
>   int val = 0x1234;
>   regmap_read(map, 0, &val);
> only changes the lower 16 bits of val on little-endian machines.
> The upper 16 bits will remain 0x1234.
> 
> Nobody noticed this probably because this bug can be triggered with
> regmap_write() only on big-endian architectures (which are not used by
> many people anymore), and on little endian this bug has consequences
> only if register width is 8 or 16 bits and also the memory place to
> which regmap_read() should store it's result has non-zero upper bits,
> which it seems doesn't happen anywhere in U-Boot normally. CI managed to
> trigger this bug in unit test of dm_test_devm_regmap_field when compiled
> for sandbox_defconfig using LTO.
> 
> Fix this simply by taking into account that regmap_raw_read() and
> regmap_raw_write() behave as if the data given to these functions were
> in little-endian format, i.e. use cpu_to_le32() / le32_to_cpu(). In
> regmap_read() also zero out the space so that we don't get invalid
> result if regmap_raw_read() does not fill the whole object.
> 
> Signed-off-by: Marek Behún 
> Reviewed-by: Simon Glass 
> Reviewed-by: Heiko Schocher 
> Reviewed-by: Bin Meng 
> ---
>  drivers/core/regmap.c | 13 -
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
> index b51ce108c1..5d37006fff 100644
> --- a/drivers/core/regmap.c
> +++ b/drivers/core/regmap.c
> @@ -435,7 +435,16 @@ int regmap_raw_read(struct regmap *map, uint offset, 
> void *valp, size_t val_len)
>  
>  int regmap_read(struct regmap *map, uint offset, uint *valp)
>  {
> - return regmap_raw_read(map, offset, valp, map->width);
> + int res;
> +
> + *valp = 0;
> + res = regmap_raw_read(map, offset, valp, map->width);
> + if (res)
> + return res;
> +
> + *valp = le32_to_cpu(*valp);

Looks like I'm a bit late to the party and Simon has already applied 
this patch. Anyway, I don't see why this is correct. regmap_raw_read() 
calls regmap_raw_read_range(), which calls the helpers __read_16(), 
__read_32() and so on.

Take __read_16() for example. It takes the regmap's endianness and then 
based on that calls in_le16() or in_be16(). These calls translate to 
le16_to_cpu(__raw_readw(a)) or be16_to_cpu(__raw_readw(a)). Or the 
regmap is native endian in which case it is a simple readw(a).

In all 3 cases the value returned is in cpu endianness. But you claim 
that "regmap_raw_read() and regmap_raw_write() behave as if the data 
given to these functions were in little-endian format".

This is fine on a little endian cpu but on a big endian cpu you would 
reverse the byte order, no? Same for writes.

> +
> + return 0;
>  }
>  
>  static inline void __write_8(u8 *addr, const u8 *val,
> @@ -546,6 +555,8 @@ int regmap_raw_write(struct regmap *map, uint offset, 
> const void *val,
>  
>  int regmap_write(struct regmap *map, uint offset, uint val)
>  {
> + val = cpu_to_le32(val);
> +
>   return regmap_raw_write(map, offset, &val, map->width);
>  }
>  
> -- 
> 2.26.2
> 

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.

Re: [PATCH u-boot v3 01/39] regmap: fix a serious pointer casting bug

[Marek Behun]

On Tue, 16 Mar 2021 19:28:46 +0530
Pratyush Yadav  wrote:

> On 16/03/21 01:25PM, Marek Behún wrote:
> > There is a serious bug in regmap_read() and regmap_write() functions
> > where an uint pointer is cast to (void *) which is then cast to (u8 *),
> > (u16 *), (u32 *) or (u64 *), depending on register width of the map.
> > 
> > For example given a regmap with 16-bit register width the code
> > int val = 0x1234;
> > regmap_read(map, 0, &val);
> > only changes the lower 16 bits of val on little-endian machines.
> > The upper 16 bits will remain 0x1234.
> > 
> > Nobody noticed this probably because this bug can be triggered with
> > regmap_write() only on big-endian architectures (which are not used by
> > many people anymore), and on little endian this bug has consequences
> > only if register width is 8 or 16 bits and also the memory place to
> > which regmap_read() should store it's result has non-zero upper bits,
> > which it seems doesn't happen anywhere in U-Boot normally. CI managed to
> > trigger this bug in unit test of dm_test_devm_regmap_field when compiled
> > for sandbox_defconfig using LTO.
> > 
> > Fix this simply by taking into account that regmap_raw_read() and
> > regmap_raw_write() behave as if the data given to these functions were
> > in little-endian format, i.e. use cpu_to_le32() / le32_to_cpu(). In
> > regmap_read() also zero out the space so that we don't get invalid
> > result if regmap_raw_read() does not fill the whole object.
> > 
> > Signed-off-by: Marek Behún 
> > Reviewed-by: Simon Glass 
> > Reviewed-by: Heiko Schocher 
> > Reviewed-by: Bin Meng 
> > ---
> >  drivers/core/regmap.c | 13 -
> >  1 file changed, 12 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
> > index b51ce108c1..5d37006fff 100644
> > --- a/drivers/core/regmap.c
> > +++ b/drivers/core/regmap.c
> > @@ -435,7 +435,16 @@ int regmap_raw_read(struct regmap *map, uint offset, 
> > void *valp, size_t val_len)
> >  
> >  int regmap_read(struct regmap *map, uint offset, uint *valp)
> >  {
> > -   return regmap_raw_read(map, offset, valp, map->width);
> > +   int res;
> > +
> > +   *valp = 0;
> > +   res = regmap_raw_read(map, offset, valp, map->width);
> > +   if (res)
> > +   return res;
> > +
> > +   *valp = le32_to_cpu(*valp);  
> 
> Looks like I'm a bit late to the party and Simon has already applied 
> this patch.

Where did he apply? I don't see it applied in u-boot-dm.

> Anyway, I don't see why this is correct. regmap_raw_read() 
> calls regmap_raw_read_range(), which calls the helpers __read_16(), 
> __read_32() and so on.
> 
> Take __read_16() for example. It takes the regmap's endianness and then 
> based on that calls in_le16() or in_be16(). These calls translate to 
> le16_to_cpu(__raw_readw(a)) or be16_to_cpu(__raw_readw(a)). Or the 
> regmap is native endian in which case it is a simple readw(a).
> 
> In all 3 cases the value returned is in cpu endianness. But you claim 
> that "regmap_raw_read() and regmap_raw_write() behave as if the data 
> given to these functions were in little-endian format".
> 
> This is fine on a little endian cpu but on a big endian cpu you would 
> reverse the byte order, no? Same for writes.

I made a mistake.

Somehow I thought that le32_to_cpu() will fix this, because it will
move the read bytes into the correct position. But somehow I forgot that
it will also reverse the byte order /o\ :D

I shall fix this and send a new version :D

Re: [PATCH v2 9/9] board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF

[Patrick DELAUNAY]

On 3/15/21 6:32 PM, Jagan Teki wrote:

7" OF is a capacitive touch 7" Open Frame panel solutions with
- 7" AUO B101AW03 LVDS panel
- EDT, FT5526 Touch

MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0
7" Open Frame Solution board.

Linux dts commit details:

commit <1d278204cbaa> ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1
MicroDev 2.0 7" OF")

Add support for it.

Reviewed-by: Patrice Chotard 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- collect Patrice r-b
- add linux dts commit
- drop CONFIG_BOARD_EARLY_INIT_F

  arch/arm/dts/Makefile |   1 +
  ...rogea-stm32mp1-microdev2.0-of7-u-boot.dtsi |  51 ++
  ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 154 ++
  arch/arm/mach-stm32mp/Kconfig |   7 +
  board/engicam/stm32mp1/MAINTAINERS|   6 +
  ...-microgea-stm32mp1-microdev2-of7_defconfig |  79 +
  6 files changed, 298 insertions(+)
  create mode 100644 
arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7-u-boot.dtsi
  create mode 100644 
arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
  create mode 100644 configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig


...


diff --git a/board/engicam/stm32mp1/MAINTAINERS 
b/board/engicam/stm32mp1/MAINTAINERS
index c0bb767782..712e312665 100644
--- a/board/engicam/stm32mp1/MAINTAINERS
+++ b/board/engicam/stm32mp1/MAINTAINERS
@@ -4,6 +4,12 @@ M: Matteo Lisi 
  S:Maintained
  F:configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
  
+MicroGEA-STM32MP1-MICRODEV2.0-OF7

+M: Jagan Teki 
+M: Matteo Lisi 
+S: Maintained
+F: configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
+


minor: you can add the also added device tree in MAINTAINERS

+F: arch/arm/dts/stm32mp15*microgea*


Anyway


Reviewed-by: Patrick Delaunay 

Thanks
Patrick

Re: [PATCH v2 7/9] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 1X4Gb DDR3

[Jagan Teki]

Hi Patrick,

On Tue, Mar 16, 2021 at 7:16 PM Patrick DELAUNAY
 wrote:
>
> Hi Jagan,
>
> On 3/15/21 6:32 PM, Jagan Teki wrote:
> > Engicam MicroGEA STM32MP1 Micro SOM has mounted 1x4Gb DDR3
> > which has 16bits width 533Mhz frequency.
> >
> > Add DDR configurations via dtsi.
> >
> > Reviewed-by: Patrice Chotard 
> > Signed-off-by: Jagan Teki 
> > ---
> > Changes for v2:
> > - collect Patrice r-b
> >
> >   ...m32mp15-ddr3-microgea-1x4Gb-1066-binG.dtsi | 121 ++
> >   1 file changed, 121 insertions(+)
> >   create mode 100644 
> > arch/arm/dts/stm32mp15-ddr3-microgea-1x4Gb-1066-binG.dtsi
> >
> > diff --git a/arch/arm/dts/stm32mp15-ddr3-microgea-1x4Gb-1066-binG.dtsi 
> > b/arch/arm/dts/stm32mp15-ddr3-microgea-1x4Gb-1066-binG.dtsi
> > new file mode 100644
> > index 00..950f292abb
> > --- /dev/null
> > +++ b/arch/arm/dts/stm32mp15-ddr3-microgea-1x4Gb-1066-binG.dtsi
> > @@ -0,0 +1,121 @@
> > +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
> > +/*
> > + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
> > + *
> > + * STM32MP157C DK1/DK2 BOARD configuration
> > + * 1x DDR3L 4Gb, 16-bit, 533MHz.
> > + * Reference used NT5CC256M16DP-DI from NANYA
> > + *
> > + * DDR type / Platform   DDR3/3L
> > + * freq  533MHz
> > + * width 16
> > + * datasheet 0  = MT41J256M16-187 / DDR3-1066 bin G
> > + * DDR density   4
> > + * timing mode   optimized
> > + * Scheduling/QoS options : type = 2
> > + * address mapping : RBC
> > + * Tc > + 85C : N
> > + */
>
> This file is identical to stm32mp15-ddr3-1x4Gb-1066-binG.dtsi, because
> it is a files generated
>
> with CubeMX with the same parameters.
>
> Do you any reason to duplicate it ?
>
> Do you expect some board-specific tuning or configuration with be
> integrated latter.

Yes, ie reason. You are right, I think will reuse exiting dtsi and
update based on future requirements. I Will update in the next
version, thanks!

-- 
Jagan Teki,
Amarula Solutions India Pvt. Ltd.
Co-Founder & Embedded Linux Architect
405/E-Block, Sri Lakshmi Shubham Arcade, Chandanagar, Hyderabad - 500050, India
M. (+91) 910 009 0959
[`as] http://www.amarulasolutions.com

[PATCH u-boot v3.1 01/39] regmap: fix a serious pointer casting bug

[Marek Behún]

There is a serious bug in regmap_read() and regmap_write() functions
where an uint pointer is cast to (void *) which is then cast to (u8 *),
(u16 *), (u32 *) or (u64 *), depending on register width of the map.

For example given a regmap with 16-bit register width the code
int val = 0x1234;
regmap_read(map, 0, &val);
only changes the lower 16 bits of val on little-endian machines.
The upper 16 bits will remain 0x1234.

Nobody noticed this probably because this bug can be triggered with
regmap_write() only on big-endian architectures (which are not used by
many people anymore), and on little endian this bug has consequences
only if register width is 8 or 16 bits and also the memory place to
which regmap_read() should store it's result has non-zero upper bits,
which it seems doesn't happen anywhere in U-Boot normally. CI managed to
trigger this bug in unit test of dm_test_devm_regmap_field when compiled
for sandbox_defconfig using LTO.

Fix this by utilizing an union { u8; u16; u32; u64; } and reading data
into this union / writing data from this union.

Signed-off-by: Marek Behún 
Cc: Simon Glass 
Cc: Heiko Schocher 
Cc: Bin Meng 
Cc: Pratyush Yadav 
---
 drivers/core/regmap.c | 59 +--
 1 file changed, 57 insertions(+), 2 deletions(-)

diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index b51ce108c1..3206f3d112 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -435,7 +435,36 @@ int regmap_raw_read(struct regmap *map, uint offset, void 
*valp, size_t val_len)
 
 int regmap_read(struct regmap *map, uint offset, uint *valp)
 {
-   return regmap_raw_read(map, offset, valp, map->width);
+   union {
+   u8 v8;
+   u16 v16;
+   u32 v32;
+   u64 v64;
+   } u;
+   int res;
+
+   res = regmap_raw_read(map, offset, &u, map->width);
+   if (res)
+   return res;
+
+   switch (map->width) {
+   case REGMAP_SIZE_8:
+   *valp = u.v8;
+   break;
+   case REGMAP_SIZE_16:
+   *valp = u.v16;
+   break;
+   case REGMAP_SIZE_32:
+   *valp = u.v32;
+   break;
+   case REGMAP_SIZE_64:
+   *valp = u.v64;
+   break;
+   default:
+   unreachable();
+   }
+
+   return 0;
 }
 
 static inline void __write_8(u8 *addr, const u8 *val,
@@ -546,7 +575,33 @@ int regmap_raw_write(struct regmap *map, uint offset, 
const void *val,
 
 int regmap_write(struct regmap *map, uint offset, uint val)
 {
-   return regmap_raw_write(map, offset, &val, map->width);
+   union {
+   u8 v8;
+   u16 v16;
+   u32 v32;
+   u64 v64;
+   } u;
+
+   switch (map->width) {
+   case REGMAP_SIZE_8:
+   u.v8 = val;
+   break;
+   case REGMAP_SIZE_16:
+   u.v16 = val;
+   break;
+   case REGMAP_SIZE_32:
+   u.v32 = val;
+   break;
+   case REGMAP_SIZE_64:
+   u.v64 = val;
+   break;
+   default:
+   debug("%s: regmap size %zu unknown\n", __func__,
+ (size_t)map->width);
+   return -EINVAL;
+   }
+
+   return regmap_raw_write(map, offset, &u, map->width);
 }
 
 int regmap_update_bits(struct regmap *map, uint offset, uint mask, uint val)
-- 
2.26.2

Re: [PATCH] scmi: correctly configure MMU for SCMI buffer

[Etienne Carriere]

Hello Patrick,

On Tue, 16 Mar 2021 at 09:29, Patrick Delaunay
 wrote:
>
> Align the MMU area for SCMI shared buffer on section size;
> use the ALIGN macro in mmu_set_region_dcache_behaviour call.
>
> Since commit d877f8fd0f09 ("arm: provide a function for boards init
> code to modify MMU virtual-physical map") the parameter of
> mmu_set_region_dcache_behaviour need to be MMU_SECTION_SIZE
> aligned.
>
> Fixes: 240720e9052f ("firmware: scmi: mailbox/smt agent device")
> Signed-off-by: Patrick Delaunay 
> ---
>
>  drivers/firmware/scmi/smt.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/firmware/scmi/smt.c b/drivers/firmware/scmi/smt.c
> index d25478796a..3c41013bca 100644
> --- a/drivers/firmware/scmi/smt.c
> +++ b/drivers/firmware/scmi/smt.c
> @@ -54,8 +54,10 @@ int scmi_dt_get_smt_buffer(struct udevice *dev, struct 
> scmi_smt *smt)
>
>  #ifdef CONFIG_ARM
> if (dcache_status())
> -   mmu_set_region_dcache_behaviour((uintptr_t)smt->buf,
> -   smt->size, DCACHE_OFF);
> +   
> mmu_set_region_dcache_behaviour(ALIGN_DOWN((uintptr_t)smt->buf, 
> MMU_SECTION_SIZE),
> +   ALIGN(smt->size, 
> MMU_SECTION_SIZE),
> +   DCACHE_OFF);
> +
>  #endif
>
> return 0;
> --
> 2.17.1
>

Reviewed-by: Etienne Carriere 

This indeed fixes the scmi smt driver.
Thanks Patrick.

Regards,
Etienne

regmap bug fix

[Marek Behun]

Simon, Heiko, Bin,

Pratyush discovered that the solution implemented by the patch
  regmap: fix a serious pointer casting bug
is wrong. The cpu_to_le32() / le32_to_cpu() shifts data to the correct
position, but on big endian machines it also reverses byte order.
Somehow this went right through my head when I thought this up.

I have sent a new version, with subject
  [PATCH u-boot v3.1 01/39] regmap: fix a serious pointer casting bug

The new solution utilizes an union { u8; u16; u32; u64; }, since all
members of an union start at the same address.

Could you please review this? Thanks.

Marek

Re: [PATCH u-boot v3 01/39] regmap: fix a serious pointer casting bug

[Pratyush Yadav]

On 16/03/21 03:15PM, Marek Behun wrote:
> On Tue, 16 Mar 2021 19:28:46 +0530
> Pratyush Yadav  wrote:
> 
> > On 16/03/21 01:25PM, Marek Behún wrote:
> > > There is a serious bug in regmap_read() and regmap_write() functions
> > > where an uint pointer is cast to (void *) which is then cast to (u8 *),
> > > (u16 *), (u32 *) or (u64 *), depending on register width of the map.
> > > 
> > > For example given a regmap with 16-bit register width the code
> > >   int val = 0x1234;
> > >   regmap_read(map, 0, &val);
> > > only changes the lower 16 bits of val on little-endian machines.
> > > The upper 16 bits will remain 0x1234.
> > > 
> > > Nobody noticed this probably because this bug can be triggered with
> > > regmap_write() only on big-endian architectures (which are not used by
> > > many people anymore), and on little endian this bug has consequences
> > > only if register width is 8 or 16 bits and also the memory place to
> > > which regmap_read() should store it's result has non-zero upper bits,
> > > which it seems doesn't happen anywhere in U-Boot normally. CI managed to
> > > trigger this bug in unit test of dm_test_devm_regmap_field when compiled
> > > for sandbox_defconfig using LTO.
> > > 
> > > Fix this simply by taking into account that regmap_raw_read() and
> > > regmap_raw_write() behave as if the data given to these functions were
> > > in little-endian format, i.e. use cpu_to_le32() / le32_to_cpu(). In
> > > regmap_read() also zero out the space so that we don't get invalid
> > > result if regmap_raw_read() does not fill the whole object.
> > > 
> > > Signed-off-by: Marek Behún 
> > > Reviewed-by: Simon Glass 
> > > Reviewed-by: Heiko Schocher 
> > > Reviewed-by: Bin Meng 
> > > ---
> > >  drivers/core/regmap.c | 13 -
> > >  1 file changed, 12 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
> > > index b51ce108c1..5d37006fff 100644
> > > --- a/drivers/core/regmap.c
> > > +++ b/drivers/core/regmap.c
> > > @@ -435,7 +435,16 @@ int regmap_raw_read(struct regmap *map, uint offset, 
> > > void *valp, size_t val_len)
> > >  
> > >  int regmap_read(struct regmap *map, uint offset, uint *valp)
> > >  {
> > > - return regmap_raw_read(map, offset, valp, map->width);
> > > + int res;
> > > +
> > > + *valp = 0;
> > > + res = regmap_raw_read(map, offset, valp, map->width);
> > > + if (res)
> > > + return res;
> > > +
> > > + *valp = le32_to_cpu(*valp);  
> > 
> > Looks like I'm a bit late to the party and Simon has already applied 
> > this patch.
> 
> Where did he apply? I don't see it applied in u-boot-dm.

  Message-ID: 


The quoting is off but look at the last line, it says "applied to 
u-boot-dm/next".

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.

U-boot : Request for support - Adding more u-boot environment variables to /inlcude/configs/.h does not allow u-boot to start

[Kumar, Naveen AVL/DE]

Dear Denx Team,

I was facing an issue with uboot when I add more environment variables to 
#define CONFIG_EXTRA_ENV_SETTINGS in the file /inlcude/configs/.h

CASE 1: WORKING
When I add fewer env variables


CASE 2: HANGS at BL31 before the u-boot is loaded. See logs below:

>[ 0.000147] NOTICE: BL2: R-Car H3 Initial Program Loader(CA57)
[ 0.004586] NOTICE: BL2: Initial Program Loader(Rev.2.0.4)
[ 0.010119] NOTICE: BL2: PRR is R-Car H3 Ver.2.0
[ 0.014787] NOTICE: BL2: Board is Starter Kit Rev.2.0
[ 0.019900] NOTICE: BL2: Boot device is HyperFlash(80MHz)
[ 0.025325] NOTICE: BL2: LCM state is CM
[ 0.029365] NOTICE: BL2: AVS setting succeeded. DVFS_SetVID=0x53
[ 0.035354] NOTICE: BL2: DDR3200(rev.0.37)
[ 0.050622] NOTICE: BL2: [COLD_BOOT]
[ 0.059403] NOTICE: BL2: DRAM Split is 4ch
[ 0.062098] NOTICE: BL2: QoS is default setting(rev.0.21)
[ 0.067541] NOTICE: BL2: DRAM refresh interval 1.95 usec
[ 0.072898] NOTICE: BL2: Periodic Write DQ Training
[ 0.077927] NOTICE: BL2: Lossy Decomp areas
[ 0.082057] NOTICE: Entry 0: DCMPAREACRAx:0x8540 DCMPAREACRBx:0x570
[ 0.089142] NOTICE: Entry 1: DCMPAREACRAx:0x4000 DCMPAREACRBx:0x0
[ 0.096054] NOTICE: Entry 2: DCMPAREACRAx:0x2000 DCMPAREACRBx:0x0
[ 0.102968] NOTICE: BL2: v1.5(release):236f8fb-dirty
[ 0.107977] NOTICE: BL2: Built : 20:32:45, Mar 3 2020
[ 0.113164] NOTICE: BL2: Normal boot
[ 0.116804] NOTICE: BL2: dst=0xe6325100 src=0x818 len=512(0x200)
[ 0.123192] NOTICE: BL2: dst=0x43f0 src=0x8180400 len=6144(0x1800)
[ 0.129813] NOTICE: BL2: dst=0x4400 src=0x81c len=65536(0x1)
[ 0.137038] NOTICE: BL2: dst=0x4410 src=0x820 len=1048576(0x10)
[ 0.151863] NOTICE: BL2: dst=0x5000 src=0x864 len=1048576(0x10)
[ 0.165837] NOTICE: BL2: Booting BL31

FYI, I am using Renesas h3ulcb board for my work.
Can you please check why am I facing this issue ?


Kind regards,

Naveen KUMAR
Software & Functions Engineer
naveen.ku...@avl.com


AVL Software and Functions GmbH
Im Gewerbepark B29, 93059 Regensburg
Germany
www.avl-functions.com

[cid:image001.png@01D71A4B.3F558E80]

[cid:image002.png@01D71A4B.3F558E80]

Re: [PATCH u-boot v3 01/39] regmap: fix a serious pointer casting bug

[Marek Behun]

On Tue, 16 Mar 2021 20:59:55 +0530
Pratyush Yadav  wrote:

> On 16/03/21 03:15PM, Marek Behun wrote:
> > On Tue, 16 Mar 2021 19:28:46 +0530
> > Pratyush Yadav  wrote:
> >   
> > > On 16/03/21 01:25PM, Marek Behún wrote:  
> > > > There is a serious bug in regmap_read() and regmap_write() functions
> > > > where an uint pointer is cast to (void *) which is then cast to (u8 *),
> > > > (u16 *), (u32 *) or (u64 *), depending on register width of the map.
> > > > 
> > > > For example given a regmap with 16-bit register width the code
> > > > int val = 0x1234;
> > > > regmap_read(map, 0, &val);
> > > > only changes the lower 16 bits of val on little-endian machines.
> > > > The upper 16 bits will remain 0x1234.
> > > > 
> > > > Nobody noticed this probably because this bug can be triggered with
> > > > regmap_write() only on big-endian architectures (which are not used by
> > > > many people anymore), and on little endian this bug has consequences
> > > > only if register width is 8 or 16 bits and also the memory place to
> > > > which regmap_read() should store it's result has non-zero upper bits,
> > > > which it seems doesn't happen anywhere in U-Boot normally. CI managed to
> > > > trigger this bug in unit test of dm_test_devm_regmap_field when compiled
> > > > for sandbox_defconfig using LTO.
> > > > 
> > > > Fix this simply by taking into account that regmap_raw_read() and
> > > > regmap_raw_write() behave as if the data given to these functions were
> > > > in little-endian format, i.e. use cpu_to_le32() / le32_to_cpu(). In
> > > > regmap_read() also zero out the space so that we don't get invalid
> > > > result if regmap_raw_read() does not fill the whole object.
> > > > 
> > > > Signed-off-by: Marek Behún 
> > > > Reviewed-by: Simon Glass 
> > > > Reviewed-by: Heiko Schocher 
> > > > Reviewed-by: Bin Meng 
> > > > ---
> > > >  drivers/core/regmap.c | 13 -
> > > >  1 file changed, 12 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
> > > > index b51ce108c1..5d37006fff 100644
> > > > --- a/drivers/core/regmap.c
> > > > +++ b/drivers/core/regmap.c
> > > > @@ -435,7 +435,16 @@ int regmap_raw_read(struct regmap *map, uint 
> > > > offset, void *valp, size_t val_len)
> > > >  
> > > >  int regmap_read(struct regmap *map, uint offset, uint *valp)
> > > >  {
> > > > -   return regmap_raw_read(map, offset, valp, map->width);
> > > > +   int res;
> > > > +
> > > > +   *valp = 0;
> > > > +   res = regmap_raw_read(map, offset, valp, map->width);
> > > > +   if (res)
> > > > +   return res;
> > > > +
> > > > +   *valp = le32_to_cpu(*valp);
> > > 
> > > Looks like I'm a bit late to the party and Simon has already applied 
> > > this patch.  
> > 
> > Where did he apply? I don't see it applied in u-boot-dm.  
> 
>   Message-ID: 
> 
> 
> The quoting is off but look at the last line, it says "applied to 
> u-boot-dm/next".
> 

Ah, my mail client failed to parse that mail.
Simon, will you drop the patch or shall I write a fix?

Marek

Re: [PATCH v2 2/5] configs: Add imx8mm-common header

[Tim Harvey]

On Mon, Mar 15, 2021 at 10:46 AM Jagan Teki  wrote:
>
> Move the redundant config item like SPL, memory-related
> across all imx8mm config files in the common config header,
> imx8mm-common.h
>
> Verified the built files, seems almost the same as before.
>
> Cc: Tim Harvey 
> Cc: Adam Ford 
> Cc: Peng Fan 
> Cc: Teresa Remmet 
> Cc: Igor Opaniuk 
> Signed-off-by: Jagan Teki 
> ---
> Changes for v2:
> - add venice changes
>
>  include/configs/imx8mm-common.h  | 48 
>  include/configs/imx8mm_beacon.h  | 48 
>  include/configs/imx8mm_evk.h | 45 ++
>  include/configs/imx8mm_venice.h  | 46 --
>  include/configs/phycore_imx8mm.h | 43 ++--
>  include/configs/verdin-imx8mm.h  | 42 +++-
>  6 files changed, 68 insertions(+), 204 deletions(-)
>  create mode 100644 include/configs/imx8mm-common.h
>
> diff --git a/include/configs/imx8mm-common.h b/include/configs/imx8mm-common.h
> new file mode 100644
> index 00..f1afa5c5a9
> --- /dev/null
> +++ b/include/configs/imx8mm-common.h
> @@ -0,0 +1,48 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2019 NXP
> + * Copyright (c) 2020 Amarula Solutions(India)
> + */
> +
> +#ifndef __IMX8MM_COMMON_H
> +#define __IMX8MM_COMMON_H
> +
> +#include 
> +#include 
> +
> +#ifdef CONFIG_SPL_BUILD
> +#define CONFIG_SPL_MAX_SIZE(148 * 1024)
> +#define CONFIG_SPL_STACK   0x92
> +#define CONFIG_SPL_BSS_START_ADDR  0x91
> +#define CONFIG_SPL_BSS_MAX_SIZESZ_8K
> +#define CONFIG_SYS_SPL_MALLOC_START0x4220
> +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K

Jagan,

Seems like a good idea, thanks for your work here!

I ran into an issue with imx8mm-venice due to my FIT image being
larger than 512KiB causing me to bump CONFIG_SYS_SPL_MALLOC_SIZE (I
bumped to 1MiB).

I have a pending patch for that [1] which would collide with this and
I wonder what your feelings are about SYS_SPL_MALLOC_SIZE. When I
started work on imx8mm-venice support the SPL did not use a malloc
buffer for loading the FIT image so I never ran into an issue but that
changed with  commit 03f1f78a9b44 ("spl: fit: Prefer a malloc()'d
buffer for loading images")' and after that I was not able to load my
FIT image. I'm honestly not sure how the other imx8mm boards are not
affected unless they just barely fit with a 512K malloc pool.

I'm not sure what the downside would be to doubling it to 1MiB or even
more and I would be boards using FIT with multiple dtb's would go over
512KiB pretty quickly (as opposed to having to undef and re-define it
per board).

Best regards,

Tim
[1] 
http://patchwork.ozlabs.org/project/uboot/patch/20210308215236.27722-2-thar...@gateworks.com/

[PATCH v3 0/8] stm32: Add Engicam STM32MP1 SoM

[Jagan Teki]

Patch series for Engicam i.Core and MicroGEA SoM and it's
associated carrier board dts(i) support.

Changes for v3:
- collect Patrick Delaunay r-b
- fixed comments from Patrick Delaunay
Changes for v2:
- add Linux dts commit ids in commit messages
- drop CONFIG_BOARD_EARLY_INIT_F
- order dts files in Makefile
- collect Patrice r-b

Any inputs?
Jagan.

Jagan Teki (8):
  ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoM
  ARM: dts: stm32: Add Engicam i.Core STM32MP1 1X4Gb DDR3
  ARM: stm32: Imply SPL_SPI_LOAD
  board: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit
  board: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0
  ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 Micro SoM
  board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 board
  board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF

 arch/arm/dts/Makefile |   4 +
 .../stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi | 119 +++
 ...2mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi |  51 +
 .../stm32mp157a-icore-stm32mp1-ctouch2.dts|  47 +
 ...mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi |  51 +
 .../stm32mp157a-icore-stm32mp1-edimm2.2.dts   |  47 +
 .../stm32mp157a-icore-stm32mp1-u-boot.dtsi| 146 +
 arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi  | 196 ++
 ...rogea-stm32mp1-microdev2.0-of7-u-boot.dtsi |  51 +
 ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 154 ++
 ...-microgea-stm32mp1-microdev2.0-u-boot.dtsi |  51 +
 ...32mp157a-microgea-stm32mp1-microdev2.0.dts |  55 +
 .../stm32mp157a-microgea-stm32mp1-u-boot.dtsi | 118 +++
 .../dts/stm32mp157a-microgea-stm32mp1.dtsi| 148 +
 arch/arm/mach-stm32mp/Kconfig |  54 -
 board/engicam/stm32mp1/Kconfig|  12 ++
 board/engicam/stm32mp1/MAINTAINERS|  26 +++
 board/engicam/stm32mp1/Makefile   |  10 +
 board/engicam/stm32mp1/spl.c  |  48 +
 board/engicam/stm32mp1/stm32mp1.c | 125 +++
 ...stm32mp15-icore-stm32mp1-ctouch2_defconfig |  79 +++
 ...tm32mp15-icore-stm32mp1-edimm2.2_defconfig |  79 +++
 ...-microgea-stm32mp1-microdev2-of7_defconfig |  79 +++
 ...mp15-microgea-stm32mp1-microdev2_defconfig |  79 +++
 24 files changed, 1828 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi
 create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
 create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
 create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi
 create mode 100644 
arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7-u-boot.dtsi
 create mode 100644 
arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
 create mode 100644 
arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
 create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi
 create mode 100644 board/engicam/stm32mp1/Kconfig
 create mode 100644 board/engicam/stm32mp1/MAINTAINERS
 create mode 100644 board/engicam/stm32mp1/Makefile
 create mode 100644 board/engicam/stm32mp1/spl.c
 create mode 100644 board/engicam/stm32mp1/stm32mp1.c
 create mode 100644 configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
 create mode 100644 configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
 create mode 100644 configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
 create mode 100644 configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig

-- 
2.25.1

[PATCH v3 1/8] ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoM

[Jagan Teki]

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

General features:
- STM32MP157A
- Up to 1GB DDR3L
- 4GB eMMC
- 10/100 Ethernet
- USB 2.0 Host/OTG
- I2S
- MIPI DSI to LVDS
- rest of STM32MP157A features

i.Core STM32MP1 needs to mount on top of Engicam baseboards
for creating complete platform solutions.

Linux commit details:

commit <30f9a9da4ee1> ("ARM: dts: stm32: Add Engicam i.Core STM32MP1
SoM")

Add support for it.

Reviewed-by: Patrick Delaunay 
Reviewed-by: Patrice Chotard 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- collect Patrice r-b
Changes for v2:
- collect Patrice r-b
- add linux dts commit 

 arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi | 196 +++
 1 file changed, 196 insertions(+)
 create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi

diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi 
b/arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi
new file mode 100644
index 00..01166ccacf
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/ {
+   compatible = "engicam,icore-stm32mp1", "st,stm32mp157";
+
+   memory@c000 {
+   device_type = "memory";
+   reg = <0xc000 0x2000>;
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   mcuram2: mcuram2@1000 {
+   compatible = "shared-dma-pool";
+   reg = <0x1000 0x4>;
+   no-map;
+   };
+
+   vdev0vring0: vdev0vring0@1004 {
+   compatible = "shared-dma-pool";
+   reg = <0x1004 0x1000>;
+   no-map;
+   };
+
+   vdev0vring1: vdev0vring1@10041000 {
+   compatible = "shared-dma-pool";
+   reg = <0x10041000 0x1000>;
+   no-map;
+   };
+
+   vdev0buffer: vdev0buffer@10042000 {
+   compatible = "shared-dma-pool";
+   reg = <0x10042000 0x4000>;
+   no-map;
+   };
+
+   mcuram: mcuram@3000 {
+   compatible = "shared-dma-pool";
+   reg = <0x3000 0x4>;
+   no-map;
+   };
+
+   retram: retram@3800 {
+   compatible = "shared-dma-pool";
+   reg = <0x3800 0x1>;
+   no-map;
+   };
+   };
+
+   vddcore: regulator-vddcore {
+   compatible = "regulator-fixed";
+   regulator-name = "vddcore";
+   regulator-min-microvolt = <120>;
+   regulator-max-microvolt = <120>;
+   regulator-always-on;
+   };
+
+   vdd: regulator-vdd {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   };
+
+   vdd_usb: regulator-vdd-usb {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd_usb";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   };
+
+   vdda: regulator-vdda {
+   compatible = "regulator-fixed";
+   regulator-name = "vdda";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   };
+
+   vdd_ddr: regulator-vdd-ddr {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd_ddr";
+   regulator-min-microvolt = <135>;
+   regulator-max-microvolt = <135>;
+   regulator-always-on;
+   };
+
+   vtt_ddr: regulator-vtt-ddr {
+   compatible = "regulator-fixed";
+   regulator-name = "vtt_ddr";
+   regulator-min-microvolt = <675000>;
+   regulator-max-microvolt = <675000>;
+   regulator-always-on;
+   vin-supply = <&vdd>;
+   };
+
+   vref_ddr: regulator-vref-ddr {
+   compatible = "regulator-fixed";
+   regulator-name = "vref_ddr";
+   regulator-min-microvolt = <675000>;
+   regulator-max-microvolt = <675000>;
+   regulator-always-on;
+   vin-supply = <&vdd>;
+   };
+
+   vdd_sd: regulator-vdd-sd {
+   compatible = "regulator-fixed";
+   regulator

[PATCH v3 2/8] ARM: dts: stm32: Add Engicam i.Core STM32MP1 1X4Gb DDR3

[Jagan Teki]

Engicam i.Core STM32MP1 SODIMM SoM has mounted 1x4Gb DDR3
which has 32bits width 528000Khz frequency.

Add DDR configuration via dtsi.

Reviewed-by: Patrick Delaunay 
Reviewed-by: Patrice Chotard 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- fixed cosmetic s/Khz/kHz 
- collect Patrice r-b
Changes for v2:
- collect Patrice r-b

 .../stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi | 119 ++
 1 file changed, 119 insertions(+)
 create mode 100644 arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi

diff --git a/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi 
b/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi
new file mode 100644
index 00..24c81269b0
--- /dev/null
+++ b/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved
+ */
+
+/*
+ * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
+ * DDR type: DDR3 / DDR3L
+ * DDR width: 32bits
+ * DDR density: 4Gb
+ * System frequency: 528000Khz
+ * Relaxed Timing Mode: false
+ * Address mapping type: RBC
+ *
+ * Save Date: 2019.05.14, save Time: 11:25:16
+ */
+#define DDR_MEM_COMPATIBLE ddr3-icore-1066-888-bin-g-1x4gb-528mhz
+#define DDR_MEM_NAME   "DDR3-DDR3L 32bits 528000kHz"
+#define DDR_MEM_SPEED  528000
+#define DDR_MEM_SIZE   0x2000
+
+#define DDR_MSTR 0x00040401
+#define DDR_MRCTRL0 0x0010
+#define DDR_MRCTRL1 0x
+#define DDR_DERATEEN 0x
+#define DDR_DERATEINT 0x0080
+#define DDR_PWRCTL 0x
+#define DDR_PWRTMG 0x00400010
+#define DDR_HWLPCTL 0x
+#define DDR_RFSHCTL0 0x0021
+#define DDR_RFSHCTL3 0x
+#define DDR_RFSHTMG 0x0080008A
+#define DDR_CRCPARCTL0 0x
+#define DDR_DRAMTMG0 0x121B2414
+#define DDR_DRAMTMG1 0x000A041B
+#define DDR_DRAMTMG2 0x0607080F
+#define DDR_DRAMTMG3 0x0050400C
+#define DDR_DRAMTMG4 0x07040607
+#define DDR_DRAMTMG5 0x06060403
+#define DDR_DRAMTMG6 0x02020002
+#define DDR_DRAMTMG7 0x0202
+#define DDR_DRAMTMG8 0x1005
+#define DDR_DRAMTMG14 0x00A0
+#define DDR_ZQCTL0 0xC240
+#define DDR_DFITMG0 0x02050105
+#define DDR_DFITMG1 0x0202
+#define DDR_DFILPCFG0 0x0700
+#define DDR_DFIUPD0 0xC043
+#define DDR_DFIUPD1 0x
+#define DDR_DFIUPD2 0x
+#define DDR_DFIPHYMSTR 0x
+#define DDR_ODTCFG 0x06000600
+#define DDR_ODTMAP 0x0001
+#define DDR_SCHED 0x0C01
+#define DDR_SCHED1 0x
+#define DDR_PERFHPR1 0x0101
+#define DDR_PERFLPR1 0x08000200
+#define DDR_PERFWR1 0x08000400
+#define DDR_DBG0 0x
+#define DDR_DBG1 0x
+#define DDR_DBGCMD 0x
+#define DDR_POISONCFG 0x
+#define DDR_PCCFG 0x0010
+#define DDR_PCFGR_0 0x0001
+#define DDR_PCFGW_0 0x
+#define DDR_PCFGQOS0_0 0x02100C03
+#define DDR_PCFGQOS1_0 0x00800100
+#define DDR_PCFGWQOS0_0 0x01100C03
+#define DDR_PCFGWQOS1_0 0x01000200
+#define DDR_PCFGR_1 0x0001
+#define DDR_PCFGW_1 0x
+#define DDR_PCFGQOS0_1 0x02100C03
+#define DDR_PCFGQOS1_1 0x00800040
+#define DDR_PCFGWQOS0_1 0x01100C03
+#define DDR_PCFGWQOS1_1 0x01000200
+#define DDR_ADDRMAP1 0x00080808
+#define DDR_ADDRMAP2 0x
+#define DDR_ADDRMAP3 0x
+#define DDR_ADDRMAP4 0x1F1F
+#define DDR_ADDRMAP5 0x07070707
+#define DDR_ADDRMAP6 0x0F0F0707
+#define DDR_ADDRMAP9 0x
+#define DDR_ADDRMAP10 0x
+#define DDR_ADDRMAP11 0x
+#define DDR_PGCR 0x01442E02
+#define DDR_PTR0 0x0022A41B
+#define DDR_PTR1 0x047C0740
+#define DDR_PTR2 0x042D9C80
+#define DDR_ACIOCR 0x10400812
+#define DDR_DXCCR 0x0C40
+#define DDR_DSGCR 0xF21F
+#define DDR_DCR 0x000B
+#define DDR_DTPR0 0x36D477D0
+#define DDR_DTPR1 0x098A00D8
+#define DDR_DTPR2 0x10023600
+#define DDR_MR0 0x0830
+#define DDR_MR1 0x
+#define DDR_MR2 0x0208
+#define DDR_MR3 0x
+#define DDR_ODTCR 0x0001
+#define DDR_ZQ0CR1 0x0038
+#define DDR_DX0GCR 0xCE81
+#define DDR_DX0DLLCR 0x4000
+#define DDR_DX0DQTR 0x
+#define DDR_DX0DQSTR 0x3DB02000
+#define DDR_DX1GCR 0xCE81
+#define DDR_DX1DLLCR 0x4000
+#define DDR_DX1DQTR 0x
+#define DDR_DX1DQSTR 0x3DB02000
+#define DDR_DX2GCR 0xCE81
+#define DDR_DX2DLLCR 0x4000
+#define DDR_DX2DQTR 0x
+#define DDR_DX2DQSTR 0x3DB02000
+#define DDR_DX3GCR 0xCE81
+#define DDR_DX3DLLCR 0x4000
+#define DDR_DX3DQTR 0x
+#define DDR_DX3DQSTR 0x3DB02000
+
+#include "stm32mp15-ddr.dtsi"
-- 
2.25.1

[PATCH v3 3/8] ARM: stm32: Imply SPL_SPI_LOAD

[Jagan Teki]

SPI Load isn't mandatory for STM32 builds.

Let's imply instead of select it to get rid of build
issues for non-SPI defconfigs.

Reviewed-by: Patrick Delaunay 
Reviewed-by: Patrice Chotard 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- add if SPL_SPI_SUPPORT
- collect Patrice r-b
Changes for v2:
- collect Patrice r-b

 arch/arm/mach-stm32mp/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index f538d7cb83..c61eb424c1 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -16,13 +16,13 @@ config SPL
select SPL_REGMAP
select SPL_DM_RESET
select SPL_SERIAL_SUPPORT
-   select SPL_SPI_LOAD
select SPL_SYSCON
select SPL_WATCHDOG_SUPPORT if WATCHDOG
imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
imply SPL_BOOTSTAGE if BOOTSTAGE
imply SPL_DISPLAY_PRINT
imply SPL_LIBDISK_SUPPORT
+   imply SPL_SPI_LOAD if SPL_SPI_SUPPORT
 
 config SYS_SOC
default "stm32mp"
-- 
2.25.1

[PATCH v3 4/8] board: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit

[Jagan Teki]

Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.

Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

i.Core STM32MP1 needs to mount on top of this Evaluation board for
creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.

Linux dts commit details:

commit  ("ARM: dts: stm32: Add Engicam i.Core STM32MP1
EDIMM2.2 Starter Kit")

Add support for it.

Reviewed-by: Patrick Delaunay 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- include dts in MAINTAINERS
- collect Patrice r-b
Changes for v2:
- collect Patrice r-b
- add linux dts commit
- drop CONFIG_BOARD_EARLY_INIT_F

 arch/arm/dts/Makefile |   1 +
 ...mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi |  51 ++
 .../stm32mp157a-icore-stm32mp1-edimm2.2.dts   |  47 ++
 .../stm32mp157a-icore-stm32mp1-u-boot.dtsi| 146 ++
 arch/arm/mach-stm32mp/Kconfig |  20 +++
 board/engicam/stm32mp1/Kconfig|  12 ++
 board/engicam/stm32mp1/MAINTAINERS|   7 +
 board/engicam/stm32mp1/Makefile   |  10 ++
 board/engicam/stm32mp1/spl.c  |  48 ++
 board/engicam/stm32mp1/stm32mp1.c | 125 +++
 ...tm32mp15-icore-stm32mp1-edimm2.2_defconfig |  79 ++
 11 files changed, 546 insertions(+)
 create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
 create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi
 create mode 100644 board/engicam/stm32mp1/Kconfig
 create mode 100644 board/engicam/stm32mp1/MAINTAINERS
 create mode 100644 board/engicam/stm32mp1/Makefile
 create mode 100644 board/engicam/stm32mp1/spl.c
 create mode 100644 board/engicam/stm32mp1/stm32mp1.c
 create mode 100644 configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 17cf936a1f..9d13045f21 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -990,6 +990,7 @@ dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
 dtb-$(CONFIG_STM32MP15x) += \
stm32mp157a-dk1.dtb \
stm32mp157a-avenger96.dtb \
+   stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
stm32mp157c-dk2.dtb \
stm32mp157c-ed1.dtb \
stm32mp157c-ev1.dtb \
diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi 
b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi
new file mode 100644
index 00..96fe461235
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Amarula Solutions(India)
+ * Author: Jagan Teki 
+ */
+
+#include "stm32mp157a-icore-stm32mp1-u-boot.dtsi"
+
+/{
+   aliases {
+   mmc0 = &sdmmc1;
+   };
+
+   chosen {
+   stdout-path = &uart4;
+   };
+};
+
+&sdmmc1 {
+   u-boot,dm-pre-reloc;
+};
+
+&sdmmc1_b4_pins_a {
+   u-boot,dm-pre-reloc;
+
+   pins1 {
+   u-boot,dm-pre-reloc;
+   };
+
+   pins2 {
+   u-boot,dm-pre-reloc;
+   };
+};
+
+&uart4 {
+   u-boot,dm-pre-reloc;
+};
+
+&uart4_pins_a {
+   u-boot,dm-pre-reloc;
+
+   pins1 {
+   u-boot,dm-pre-reloc;
+   };
+
+   pins2 {
+   u-boot,dm-pre-reloc;
+   bias-pull-up;
+   };
+};
diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts 
b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
new file mode 100644
index 00..ec9f1d1cd5
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+#include "stm32mp157.dtsi"
+#include "stm32mp157a-icore-stm32mp1.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include 
+
+/ {
+   model = "Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit";
+   compatible = "engicam,icore-stm32mp1-edimm2.2",
+"engicam,icore-stm32mp1", "st,stm32mp157";
+
+   aliases {
+   serial0 = &uart4;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+&sdmmc1 {
+   bus-width = <4>;
+   disable-wp;
+   pinctrl-names = "default", "opendrain", "sleep";
+   pinctrl-0 = <&sdmmc1_b4_pins_a>;
+   pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+   pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+   st,neg-edge;
+   vmmc-supply = <&v3v3>;
+   status =

[PATCH v3 5/8] board: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0

[Jagan Teki]

Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
board.

Genaral features:
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector

i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.

i.Core STM32MP1 needs to mount on top of this Carrier board for
creating complete i.Core STM32MP1 C.TOUCH 2.0 board.

Linux dts commit details:

commit <6ca2898df59f> ("ARM: dts: stm32: Add Engicam i.Core STM32MP1
C.TOUCH 2.0")

Add support for it.

Reviewed-by: Patrick Delaunay 
Reviewed-by: Patrice Chotard 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- collect Patrice r-b
Changes for v2:
- collect Patrice r-b
- add linux dts commit
- drop CONFIG_BOARD_EARLY_INIT_F

 arch/arm/dts/Makefile |  1 +
 ...2mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi | 51 
 .../stm32mp157a-icore-stm32mp1-ctouch2.dts| 47 +++
 arch/arm/mach-stm32mp/Kconfig |  5 ++
 board/engicam/stm32mp1/MAINTAINERS|  6 ++
 ...stm32mp15-icore-stm32mp1-ctouch2_defconfig | 79 +++
 6 files changed, 189 insertions(+)
 create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
 create mode 100644 configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9d13045f21..ce4521b891 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -990,6 +990,7 @@ dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
 dtb-$(CONFIG_STM32MP15x) += \
stm32mp157a-dk1.dtb \
stm32mp157a-avenger96.dtb \
+   stm32mp157a-icore-stm32mp1-ctouch2.dtb \
stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
stm32mp157c-dk2.dtb \
stm32mp157c-ed1.dtb \
diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi 
b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi
new file mode 100644
index 00..96fe461235
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Amarula Solutions(India)
+ * Author: Jagan Teki 
+ */
+
+#include "stm32mp157a-icore-stm32mp1-u-boot.dtsi"
+
+/{
+   aliases {
+   mmc0 = &sdmmc1;
+   };
+
+   chosen {
+   stdout-path = &uart4;
+   };
+};
+
+&sdmmc1 {
+   u-boot,dm-pre-reloc;
+};
+
+&sdmmc1_b4_pins_a {
+   u-boot,dm-pre-reloc;
+
+   pins1 {
+   u-boot,dm-pre-reloc;
+   };
+
+   pins2 {
+   u-boot,dm-pre-reloc;
+   };
+};
+
+&uart4 {
+   u-boot,dm-pre-reloc;
+};
+
+&uart4_pins_a {
+   u-boot,dm-pre-reloc;
+
+   pins1 {
+   u-boot,dm-pre-reloc;
+   };
+
+   pins2 {
+   u-boot,dm-pre-reloc;
+   bias-pull-up;
+   };
+};
diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts 
b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
new file mode 100644
index 00..d3058a036c
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+#include "stm32mp157.dtsi"
+#include "stm32mp157a-icore-stm32mp1.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include 
+
+/ {
+   model = "Engicam i.Core STM32MP1 C.TOUCH 2.0";
+   compatible = "engicam,icore-stm32mp1-ctouch2",
+"engicam,icore-stm32mp1", "st,stm32mp157";
+
+   aliases {
+   serial0 = &uart4;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+&sdmmc1 {
+   bus-width = <4>;
+   disable-wp;
+   pinctrl-names = "default", "opendrain", "sleep";
+   pinctrl-0 = <&sdmmc1_b4_pins_a>;
+   pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+   pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+   st,neg-edge;
+   vmmc-supply = <&v3v3>;
+   status = "okay";
+};
+
+&uart4 {
+   pinctrl-names = "default", "sleep", "idle";
+   pinctrl-0 = <&uart4_pins_a>;
+   pinctrl-1 = <&uart4_sleep_pins_a>;
+   pinctrl-2 = <&uart4_idle_pins_a>;
+   status = "okay";
+};
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index 8d1db70cc3..b809488ca3 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -96,6 +96,11 @@ config TARGET_ICORE_STM32MP1
  * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for
creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.
 
+ i.Core STM32MP1 C.TOUCH 2.0
+ * C.TOUCH 2.0 is a general purpose Carrier board.
+ * i.Core STM32MP1 needs 

[PATCH v3 6/8] ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 Micro SoM

[Jagan Teki]

MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.

General features:
- STM32MP157AAC
- Up to 1GB DDR3L-800
- 512MB Nand flash
- I2S

MicroGEA STM32MP1 needs to mount on top of Engicam MicroDev carrier
boards for creating complete platform solutions.

Linux dts commit details:

commit <0be81dfaeaf8> ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1
SoM")

Add support for it.

Reviewed-by: Patrick Delaunay 
Reviewed-by: Patrice Chotard 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- collect Patrice r-b
Changes for v2:
- collect Patrice r-b
- add linux dts commit
- drop CONFIG_BOARD_EARLY_INIT_F

 .../dts/stm32mp157a-microgea-stm32mp1.dtsi| 148 ++
 1 file changed, 148 insertions(+)
 create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi

diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi 
b/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi
new file mode 100644
index 00..0b85175f15
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/ {
+   compatible = "engicam,microgea-stm32mp1", "st,stm32mp157";
+
+   memory@c000 {
+   device_type = "memory";
+   reg = <0xc000 0x1000>;
+   };
+
+   reserved-memory {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   mcuram2: mcuram2@1000 {
+   compatible = "shared-dma-pool";
+   reg = <0x1000 0x4>;
+   no-map;
+   };
+
+   vdev0vring0: vdev0vring0@1004 {
+   compatible = "shared-dma-pool";
+   reg = <0x1004 0x1000>;
+   no-map;
+   };
+
+   vdev0vring1: vdev0vring1@10041000 {
+   compatible = "shared-dma-pool";
+   reg = <0x10041000 0x1000>;
+   no-map;
+   };
+
+   vdev0buffer: vdev0buffer@10042000 {
+   compatible = "shared-dma-pool";
+   reg = <0x10042000 0x4000>;
+   no-map;
+   };
+
+   mcuram: mcuram@3000 {
+   compatible = "shared-dma-pool";
+   reg = <0x3000 0x4>;
+   no-map;
+   };
+
+   retram: retram@3800 {
+   compatible = "shared-dma-pool";
+   reg = <0x3800 0x1>;
+   no-map;
+   };
+   };
+
+   vin: regulator-vin {
+   compatible = "regulator-fixed";
+   regulator-name = "vin";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   regulator-always-on;
+   };
+
+   vddcore: regulator-vddcore {
+   compatible = "regulator-fixed";
+   regulator-name = "vddcore";
+   regulator-min-microvolt = <120>;
+   regulator-max-microvolt = <120>;
+   regulator-always-on;
+   vin-supply = <&vin>;
+   };
+
+   vdd: regulator-vdd {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   vin-supply = <&vin>;
+   };
+
+   vddq_ddr: regulator-vddq-ddr {
+   compatible = "regulator-fixed";
+   regulator-name = "vddq_ddr";
+   regulator-min-microvolt = <135>;
+   regulator-max-microvolt = <135>;
+   regulator-always-on;
+   vin-supply = <&vin>;
+   };
+};
+
+&dts {
+   status = "okay";
+};
+
+&fmc {
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <&fmc_pins_a>;
+   pinctrl-1 = <&fmc_sleep_pins_a>;
+   status = "okay";
+
+   nand-controller@4,0 {
+   status = "okay";
+
+   nand@0 {
+   reg = <0>;
+   nand-on-flash-bbt;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   };
+   };
+};
+
+&ipcc {
+   status = "okay";
+};
+
+&iwdg2{
+   timeout-sec = <32>;
+   status = "okay";
+};
+
+&m4_rproc{
+   memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
+   <&vdev0vring1>, <&vdev0buffer>;
+   mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
+   mbox-names = "vq0", "vq1", "shutdown";
+   interrupt-parent = <&exti>;
+   interrupts = <68 1>;
+   status = "okay";
+};
+
+&rng1 {
+ 

[PATCH v3 7/8] board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 board

[Jagan Teki]

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

Genaral features:
- Ethernet 10/100
- USB Type A
- Audio Out
- microSD
- LVDS panel connector
- Wifi/BT (option)
- UMTS LTE with sim connector (option)

MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.

MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.

Linux dts commit details:

commit  ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1
MicroDev 2.0 board")

Add support for it.

Reviewed-by: Patrick Delaunay 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- include stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
- include dts files in MAINTAINERS
- collect Patrice r-b
Changes for v2:
- collect Patrice r-b
- add linux dts commit
- drop CONFIG_BOARD_EARLY_INIT_F

 arch/arm/dts/Makefile |   1 +
 ...-microgea-stm32mp1-microdev2.0-u-boot.dtsi |  51 
 ...32mp157a-microgea-stm32mp1-microdev2.0.dts |  55 
 .../stm32mp157a-microgea-stm32mp1-u-boot.dtsi | 118 ++
 arch/arm/mach-stm32mp/Kconfig |  20 +++
 board/engicam/stm32mp1/Kconfig|   2 +-
 board/engicam/stm32mp1/MAINTAINERS|   7 ++
 ...mp15-microgea-stm32mp1-microdev2_defconfig |  79 
 8 files changed, 332 insertions(+), 1 deletion(-)
 create mode 100644 
arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
 create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi
 create mode 100644 configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ce4521b891..64d73b96ef 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -992,6 +992,7 @@ dtb-$(CONFIG_STM32MP15x) += \
stm32mp157a-avenger96.dtb \
stm32mp157a-icore-stm32mp1-ctouch2.dtb \
stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
+   stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
stm32mp157c-dk2.dtb \
stm32mp157c-ed1.dtb \
stm32mp157c-ev1.dtb \
diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-u-boot.dtsi 
b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-u-boot.dtsi
new file mode 100644
index 00..e4bd215812
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-u-boot.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Amarula Solutions(India)
+ * Author: Jagan Teki 
+ */
+
+#include "stm32mp157a-microgea-stm32mp1-u-boot.dtsi"
+
+/{
+   aliases {
+   mmc0 = &sdmmc1;
+   };
+
+   chosen {
+   stdout-path = &uart4;
+   };
+};
+
+&sdmmc1 {
+   u-boot,dm-pre-reloc;
+};
+
+&sdmmc1_b4_pins_a {
+   u-boot,dm-pre-reloc;
+
+   pins1 {
+   u-boot,dm-pre-reloc;
+   };
+
+   pins2 {
+   u-boot,dm-pre-reloc;
+   };
+};
+
+&uart4 {
+   u-boot,dm-pre-reloc;
+};
+
+&uart4_pins_a {
+   u-boot,dm-pre-reloc;
+
+   pins1 {
+   u-boot,dm-pre-reloc;
+   };
+
+   pins2 {
+   u-boot,dm-pre-reloc;
+   bias-pull-up;
+   };
+};
diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts 
b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
new file mode 100644
index 00..7a75868164
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+#include "stm32mp157.dtsi"
+#include "stm32mp157a-microgea-stm32mp1.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include 
+
+/ {
+   model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 Carrier Board";
+   compatible = "engicam,microgea-stm32mp1-microdev2.0",
+"engicam,microgea-stm32mp1", "st,stm32mp157";
+
+   aliases {
+   serial0 = &uart4;
+   serial1 = &uart8;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+&sdmmc1 {
+   bus-width = <4>;
+   disable-wp;
+   pinctrl-names = "default", "opendrain", "sleep";
+   pinctrl-0 = <&sdmmc1_b4_pins_a>;
+   pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+   pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+   st,neg-edge;
+   vmmc-supply = <&vdd>;
+   status = "okay";
+};
+
+&uart4 {
+   pinctrl-names = "default", "sleep", "idle";
+   pinctrl-0 = <&uart4_pins_a>;
+   pinctrl-1 = <&uart4_sleep_pins_a>;
+   pinctrl-2 = <&uart4_idle_pins_a>;
+   status = "okay";
+};
+
+/* J31: RS323 */
+&uart

[PATCH v3 8/8] board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF

[Jagan Teki]

7" OF is a capacitive touch 7" Open Frame panel solutions with
- 7" AUO B101AW03 LVDS panel
- EDT, FT5526 Touch

MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.

MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.

MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with
pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0
7" Open Frame Solution board.

Linux dts commit details:

commit <1d278204cbaa> ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1
MicroDev 2.0 7" OF")

Add support for it.

Reviewed-by: Patrick Delaunay 
Reviewed-by: Patrice Chotard 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- collect Patrice r-b
Changes for v2:
- collect Patrice r-b
- add linux dts commit
- drop CONFIG_BOARD_EARLY_INIT_F

 arch/arm/dts/Makefile |   1 +
 ...rogea-stm32mp1-microdev2.0-of7-u-boot.dtsi |  51 ++
 ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 154 ++
 arch/arm/mach-stm32mp/Kconfig |   7 +
 board/engicam/stm32mp1/MAINTAINERS|   6 +
 ...-microgea-stm32mp1-microdev2-of7_defconfig |  79 +
 6 files changed, 298 insertions(+)
 create mode 100644 
arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7-u-boot.dtsi
 create mode 100644 
arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
 create mode 100644 configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 64d73b96ef..43c604f2f8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -993,6 +993,7 @@ dtb-$(CONFIG_STM32MP15x) += \
stm32mp157a-icore-stm32mp1-ctouch2.dtb \
stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
+   stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
stm32mp157c-dk2.dtb \
stm32mp157c-ed1.dtb \
stm32mp157c-ev1.dtb \
diff --git 
a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7-u-boot.dtsi 
b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7-u-boot.dtsi
new file mode 100644
index 00..e4bd215812
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7-u-boot.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Amarula Solutions(India)
+ * Author: Jagan Teki 
+ */
+
+#include "stm32mp157a-microgea-stm32mp1-u-boot.dtsi"
+
+/{
+   aliases {
+   mmc0 = &sdmmc1;
+   };
+
+   chosen {
+   stdout-path = &uart4;
+   };
+};
+
+&sdmmc1 {
+   u-boot,dm-pre-reloc;
+};
+
+&sdmmc1_b4_pins_a {
+   u-boot,dm-pre-reloc;
+
+   pins1 {
+   u-boot,dm-pre-reloc;
+   };
+
+   pins2 {
+   u-boot,dm-pre-reloc;
+   };
+};
+
+&uart4 {
+   u-boot,dm-pre-reloc;
+};
+
+&uart4_pins_a {
+   u-boot,dm-pre-reloc;
+
+   pins1 {
+   u-boot,dm-pre-reloc;
+   };
+
+   pins2 {
+   u-boot,dm-pre-reloc;
+   bias-pull-up;
+   };
+};
diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts 
b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
new file mode 100644
index 00..674b2d330d
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+#include "stm32mp157.dtsi"
+#include "stm32mp157a-microgea-stm32mp1.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include 
+
+/ {
+   model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 7\" Open Frame";
+   compatible = "engicam,microgea-stm32mp1-microdev2.0-of7",
+"engicam,microgea-stm32mp1", "st,stm32mp157";
+
+   aliases {
+   serial0 = &uart4;
+   serial1 = &uart8;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   backlight: backlight {
+   compatible = "gpio-backlight";
+   gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>;
+   default-on;
+   };
+
+   lcd_3v3: regulator-lcd-3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "lcd_3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = <&gpiof 10 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   regulator-always-on;
+   power-supply = <&panel_pwr>;
+   };
+
+   panel_pwr: regulator-panel-pwr {
+   compatible = "regulator-fixed";
+   regulator-name = "panel_pwr";
+   regulator-min-microvolt 

[PATCH v2 1/8] riscv: dts: add fu740 support

[Green Wan]

Add dts support for fu740. The HiFive Unmatched support is based on
fu740 cpu and drivers in following patch set.

Signed-off-by: Green Wan 
Reviewed-by: Bin Meng 
---
 arch/riscv/dts/Makefile   |   1 +
 arch/riscv/dts/fu740-c000-u-boot.dtsi | 105 
 arch/riscv/dts/fu740-c000.dtsi| 329 ++
 include/dt-bindings/clock/sifive-fu740-prci.h |  25 ++
 include/dt-bindings/reset/sifive-fu740-prci.h |  19 ++
 5 files changed, 479 insertions(+)
 create mode 100644 arch/riscv/dts/fu740-c000-u-boot.dtsi
 create mode 100644 arch/riscv/dts/fu740-c000.dtsi
 create mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h
 create mode 100644 include/dt-bindings/reset/sifive-fu740-prci.h

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 8138d89..ed32f56 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,6 +2,7 @@
 
 dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
+dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
 dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
 
diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi 
b/arch/riscv/dts/fu740-c000-u-boot.dtsi
new file mode 100644
index 000..0115a44
--- /dev/null
+++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2020-2021 SiFive, Inc
+ */
+
+#include 
+
+/ {
+   cpus {
+   assigned-clocks = <&prci PRCI_CLK_COREPLL>;
+   assigned-clock-rates = <100100>;
+   u-boot,dm-spl;
+   cpu0: cpu@0 {
+   clocks = <&prci PRCI_CLK_COREPLL>;
+   u-boot,dm-spl;
+   status = "okay";
+   cpu0_intc: interrupt-controller {
+   u-boot,dm-spl;
+   };
+   };
+   cpu1: cpu@1 {
+   clocks = <&prci PRCI_CLK_COREPLL>;
+   u-boot,dm-spl;
+   cpu1_intc: interrupt-controller {
+   u-boot,dm-spl;
+   };
+   };
+   cpu2: cpu@2 {
+   clocks = <&prci PRCI_CLK_COREPLL>;
+   u-boot,dm-spl;
+   cpu2_intc: interrupt-controller {
+u-boot,dm-spl;
+   };
+   };
+   cpu3: cpu@3 {
+   clocks = <&prci PRCI_CLK_COREPLL>;
+   u-boot,dm-spl;
+   cpu3_intc: interrupt-controller {
+   u-boot,dm-spl;
+   };
+   };
+   cpu4: cpu@4 {
+   clocks = <&prci PRCI_CLK_COREPLL>;
+   u-boot,dm-spl;
+   cpu4_intc: interrupt-controller {
+   u-boot,dm-spl;
+   };
+   };
+   };
+
+   soc {
+   u-boot,dm-spl;
+   clint: clint@200 {
+   compatible = "riscv,clint0";
+   interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
+  &cpu1_intc 3 &cpu1_intc 7
+  &cpu2_intc 3 &cpu2_intc 7
+  &cpu3_intc 3 &cpu3_intc 7
+  &cpu4_intc 3 &cpu4_intc 7>;
+   reg = <0x0 0x200 0x0 0x1>;
+   u-boot,dm-spl;
+   };
+   prci: clock-controller@1000 {
+   #reset-cells = <1>;
+   resets = <&prci PRCI_RST_DDR_CTRL_N>,
+<&prci PRCI_RST_DDR_AXI_N>,
+<&prci PRCI_RST_DDR_AHB_N>,
+<&prci PRCI_RST_DDR_PHY_N>,
+<&prci PRCI_RST_GEMGXL_N>,
+<&prci PRCI_RST_CLTX_N>;
+   reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
+   "ddr_phy", "gemgxl_reset", "cltx_reset";
+   };
+   dmc: dmc@100b {
+   compatible = "sifive,fu740-c000-ddr";
+   reg = <0x0 0x100b 0x0 0x0800
+  0x0 0x100b2000 0x0 0x2000
+  0x0 0x100b8000 0x0 0x1000>;
+   clocks = <&prci PRCI_CLK_DDRPLL>;
+   clock-frequency = <93324>;
+   u-boot,dm-spl;
+   };
+   };
+};
+
+&prci {
+   u-boot,dm-spl;
+};
+
+&uart0 {
+   u-boot,dm-spl;
+};
+
+&spi0 {
+   u-boot,dm

[PATCH v2 2/8] riscv: cpu: fu740: Add support for cpu fu740

[Green Wan]

Add SiFive fu740 cpu to support RISC-V arch

Signed-off-by: Green Wan 
Reviewed-by: Bin Meng 
---
 arch/riscv/Kconfig|  1 +
 arch/riscv/cpu/fu740/Kconfig  | 37 +
 arch/riscv/cpu/fu740/Makefile | 12 +++
 arch/riscv/cpu/fu740/cache.c  | 55 +++
 arch/riscv/cpu/fu740/cpu.c| 22 +
 arch/riscv/cpu/fu740/dram.c   | 38 +
 arch/riscv/cpu/fu740/spl.c| 23 +
 arch/riscv/include/asm/arch-fu740/cache.h | 14 
 arch/riscv/include/asm/arch-fu740/clk.h   | 14 
 arch/riscv/include/asm/arch-fu740/gpio.h  | 38 +
 arch/riscv/include/asm/arch-fu740/reset.h | 13 
 arch/riscv/include/asm/arch-fu740/spl.h   | 14 
 arch/riscv/lib/sifive_clint.c |  1 -
 13 files changed, 281 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/cpu/fu740/Kconfig
 create mode 100644 arch/riscv/cpu/fu740/Makefile
 create mode 100644 arch/riscv/cpu/fu740/cache.c
 create mode 100644 arch/riscv/cpu/fu740/cpu.c
 create mode 100644 arch/riscv/cpu/fu740/dram.c
 create mode 100644 arch/riscv/cpu/fu740/spl.c
 create mode 100644 arch/riscv/include/asm/arch-fu740/cache.h
 create mode 100644 arch/riscv/include/asm/arch-fu740/clk.h
 create mode 100644 arch/riscv/include/asm/arch-fu740/gpio.h
 create mode 100644 arch/riscv/include/asm/arch-fu740/reset.h
 create mode 100644 arch/riscv/include/asm/arch-fu740/spl.h

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index e8494c2..323c358 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -61,6 +61,7 @@ source "board/sipeed/maix/Kconfig"
 # platform-specific options below
 source "arch/riscv/cpu/ax25/Kconfig"
 source "arch/riscv/cpu/fu540/Kconfig"
+source "arch/riscv/cpu/fu740/Kconfig"
 source "arch/riscv/cpu/generic/Kconfig"
 
 # architecture-specific options below
diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
new file mode 100644
index 000..689e54d
--- /dev/null
+++ b/arch/riscv/cpu/fu740/Kconfig
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020-2021 SiFive, Inc
+# Pragnesh Patel 
+
+config SIFIVE_FU740
+   bool
+   select ARCH_EARLY_INIT_R
+   select RAM
+   select SPL_RAM if SPL
+   imply CPU
+   imply CPU_RISCV
+   imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+   imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
+   imply CMD_CPU
+   imply SPL_CPU_SUPPORT
+   imply SPL_OPENSBI
+   imply SPL_LOAD_FIT
+   imply SMP
+   imply CLK_SIFIVE
+   imply CLK_SIFIVE_PRCI
+   imply SIFIVE_SERIAL
+   imply MACB
+   imply MII
+   imply SPI
+   imply SPI_SIFIVE
+   imply MMC
+   imply MMC_SPI
+   imply MMC_BROKEN_CD
+   imply CMD_MMC
+   imply DM_GPIO
+   imply SIFIVE_GPIO
+   imply CMD_GPIO
+   imply MISC
+   imply SIFIVE_OTP
+   imply DM_PWM
+   imply PWM_SIFIVE
diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile
new file mode 100644
index 000..5ef8ac1
--- /dev/null
+++ b/arch/riscv/cpu/fu740/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020-2021 SiFive, Inc
+# Pragnesh Patel 
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += spl.o
+else
+obj-y += dram.o
+obj-y += cpu.o
+obj-y += cache.o
+endif
diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c
new file mode 100644
index 000..680955c
--- /dev/null
+++ b/arch/riscv/cpu/fu740/cache.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc
+ *
+ * Authors:
+ *   Pragnesh Patel 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+/* Register offsets */
+#define L2_CACHE_CONFIG0x000
+#define L2_CACHE_ENABLE0x008
+
+#define MASK_NUM_WAYS  GENMASK(15, 8)
+#define NUM_WAYS_SHIFT 8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int cache_enable_ways(void)
+{
+   const void *blob = gd->fdt_blob;
+   int node;
+   fdt_addr_t base;
+   u32 config;
+   u32 ways;
+
+   volatile u32 *enable;
+
+   node = fdt_node_offset_by_compatible(blob, -1,
+"sifive,fu740-c000-ccache");
+
+   if (node < 0)
+   return node;
+
+   base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
+   NULL, false);
+   if (base == FDT_ADDR_T_NONE)
+   return FDT_ADDR_T_NONE;
+
+   config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
+   ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
+
+   enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
+
+   /* memory barrier */
+   mb();
+   (*enable) = ways - 1;
+   /* memory barrier */
+   mb();
+   return 0;
+}
diff --git a/arch/riscv/cpu/fu740/cpu.c b/arch/riscv/cpu/fu740/cpu.c
new f

[PATCH v2 0/8] Add FU740 chip and HiFive Unmatched board support

[Green Wan]

This patch set is to add SiFive fu740 chip and HiFive Unmatched board
support. Patches are split into several parts:

  - [PATCH 1/8] dts for fu740
  - [PATCH 2/8] support for fu740 cpu
  - [PATCH 3/8- 5/8] support for fu740 clk and ram
  - [PATCH 6/8] add pcie driver
  - [PATCH 7/8] add unmatched board
  - [PATCH 8/8] add fu740 support to macb driver

Description

  - For fu740 cpu support, reuse most of fu540 cpu.
  - For prci driver, add one abstract layer to separate fu540 and
fu740. Move orignal fu540 code to separate files.
  - For pcie driver, it depends on gpio, prci, clk and reset drivers
to do init&reset works.
  - Align with Linux DT file.

Tests and patch checks

  - Able to boot both unmatched and unleashed boards.
  - PCIe tests
. M.2 NVMe SSD
. e1000 compatibale ethernet adapter (ping&tftpboot)
. pci-to-usb adapter(usb mass storage)
  - checkpatch is performed. To keep code derived from other boards
the same, ignore some warnings/errors in [PATCH 7/8].

Changlogs
  - V2
. Rebase to unleashed rename patch
. remove unnessaary fu540 changes
. split ram driver patch into 2 to keep 'git mv' info
. use a shorter name for unmatched support
. Remove redundant&incorrect temperature-sensor in DT
. Remove unnecessary USB EHCI & OHCI from defconfig
. Revised fu740 doc
. Fixed year of copyright
. Add reviewed-by received in v1 patch

David Abdurachmanov (1):
  drivers: net: macb: add fu740 support

Green Wan (7):
  riscv: dts: add fu740 support
  riscv: cpu: fu740: Add support for cpu fu740
  drivers: clk: add fu740 support
  drivers: ram: sifive: rename fu540_ddr to sifive_ddr
  drivers: ram: add fu740 support
  drivers: pci: add pcie support for fu740
  board: sifive: add HiFive Unmatched board support

 arch/riscv/Kconfig |5 +
 arch/riscv/cpu/fu740/Kconfig   |   37 +
 arch/riscv/cpu/fu740/Makefile  |   12 +
 arch/riscv/cpu/fu740/cache.c   |   55 +
 arch/riscv/cpu/fu740/cpu.c |   22 +
 arch/riscv/cpu/fu740/dram.c|   38 +
 arch/riscv/cpu/fu740/spl.c |   23 +
 arch/riscv/dts/Makefile|1 +
 arch/riscv/dts/fu740-c000-u-boot.dtsi  |  105 ++
 arch/riscv/dts/fu740-c000.dtsi |  329 +
 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489 
 arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi|   40 +
 arch/riscv/dts/hifive-unmatched-a00.dts|  253 
 arch/riscv/include/asm/arch-fu740/cache.h  |   14 +
 arch/riscv/include/asm/arch-fu740/clk.h|   14 +
 arch/riscv/include/asm/arch-fu740/gpio.h   |   38 +
 arch/riscv/include/asm/arch-fu740/reset.h  |   13 +
 arch/riscv/include/asm/arch-fu740/spl.h|   14 +
 arch/riscv/lib/sifive_clint.c  |1 -
 board/sifive/unmatched/Kconfig |   50 +
 board/sifive/unmatched/MAINTAINERS |9 +
 board/sifive/unmatched/Makefile|9 +
 board/sifive/unmatched/hifive-unmatched-fu740.c|   24 +
 board/sifive/unmatched/spl.c   |   85 ++
 common/spl/Kconfig |4 +-
 configs/sifive_unmatched_defconfig |   53 +
 doc/board/sifive/hifive_unmatched_fu740.rst|  536 +++
 drivers/clk/sifive/Kconfig |8 +-
 drivers/clk/sifive/Makefile|4 +-
 drivers/clk/sifive/fu540-prci.c|  769 +-
 drivers/clk/sifive/fu540-prci.h|   22 +
 drivers/clk/sifive/fu740-prci.c|  158 +++
 drivers/clk/sifive/fu740-prci.h|   22 +
 drivers/clk/sifive/sifive-prci.c   |  733 ++
 drivers/clk/sifive/sifive-prci.h   |  323 +
 drivers/net/macb.c |8 +-
 drivers/pci/Kconfig|9 +
 drivers/pci/Makefile   |1 +
 drivers/pci/pcie_sifive.c  |  797 +++
 drivers/pci/pcie_sifive.h  |  374 +
 drivers/ram/sifive/Kconfig |8 +-
 drivers/ram/sifive/Makefile|2 +-
 drivers/ram/sifive/fu540_ddr.c |  410 --
 drivers/ram/sifive/sifive_ddr.c|  410 ++
 drivers/reset/Kconfig  |2 +-
 include/configs/sifive-unmatched.h |   85 ++
 include/dt-bindings/clock/sifive-fu740-prci.h  |   25 +
 include/dt-bindings/reset/sifive-fu740-prci.h  |   19 +
 48 files changed, 6289 insertions(+), 1173 deletions(-)
 create mode 100644 arch/riscv/cpu/fu740/Kconfig
 create mode 100644 arch/riscv/cpu/fu740/Makefile
 create mode 100644 arch/ris

[PATCH v2 4/8] drivers: ram: sifive: rename fu540_ddr to sifive_ddr

[Green Wan]

Rename fu540_ddr.c to sifive_ddr.c for supporting both of fu540 and
fu740. To avoid 'git mv' info missing, sifive_ddr.c chagnes are
included in next patch.

Signed-off-by: Green Wan 
---
 drivers/ram/sifive/Kconfig  |   6 +-
 drivers/ram/sifive/Makefile |   2 +-
 drivers/ram/sifive/fu540_ddr.c  | 410 
 drivers/ram/sifive/sifive_ddr.c | 410 
 4 files changed, 414 insertions(+), 414 deletions(-)
 delete mode 100644 drivers/ram/sifive/fu540_ddr.c
 create mode 100644 drivers/ram/sifive/sifive_ddr.c

diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig
index 08de692..a93cd0e 100644
--- a/drivers/ram/sifive/Kconfig
+++ b/drivers/ram/sifive/Kconfig
@@ -5,9 +5,9 @@ config RAM_SIFIVE
help
  This enables support for ram drivers of SiFive SoCs.
 
-config SIFIVE_FU540_DDR
-   bool "SiFive FU540 DDR driver"
+config SIFIVE_DDR
+   bool "SiFive DDR driver"
depends on RAM_SIFIVE
default y if TARGET_SIFIVE_UNLEASHED
help
- This enables DDR support for the platforms based on SiFive FU540 SoC.
+ This enables DDR support for the platforms based on SiFive SoC.
diff --git a/drivers/ram/sifive/Makefile b/drivers/ram/sifive/Makefile
index d66efec..4ef89f8 100644
--- a/drivers/ram/sifive/Makefile
+++ b/drivers/ram/sifive/Makefile
@@ -3,4 +3,4 @@
 # Copyright (c) 2020 SiFive, Inc
 #
 
-obj-$(CONFIG_SIFIVE_FU540_DDR) += fu540_ddr.o
+obj-$(CONFIG_SIFIVE_DDR) += sifive_ddr.o
diff --git a/drivers/ram/sifive/fu540_ddr.c b/drivers/ram/sifive/fu540_ddr.c
deleted file mode 100644
index c0653bb..000
--- a/drivers/ram/sifive/fu540_ddr.c
+++ /dev/null
@@ -1,410 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * (C) Copyright 2020 SiFive, Inc.
- *
- * Authors:
- *   Pragnesh Patel 
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#define DENALI_CTL_0   0
-#define DENALI_CTL_21  21
-#define DENALI_CTL_120 120
-#define DENALI_CTL_132 132
-#define DENALI_CTL_136 136
-#define DENALI_CTL_170 170
-#define DENALI_CTL_181 181
-#define DENALI_CTL_182 182
-#define DENALI_CTL_184 184
-#define DENALI_CTL_208 208
-#define DENALI_CTL_209 209
-#define DENALI_CTL_210 210
-#define DENALI_CTL_212 212
-#define DENALI_CTL_214 214
-#define DENALI_CTL_216 216
-#define DENALI_CTL_224 224
-#define DENALI_CTL_225 225
-#define DENALI_CTL_260 260
-
-#define DENALI_PHY_11521152
-#define DENALI_PHY_12141214
-
-#define DRAM_CLASS_OFFSET  8
-#define DRAM_CLASS_DDR40xA
-#define OPTIMAL_RMODW_EN_OFFSET0
-#define DISABLE_RD_INTERLEAVE_OFFSET   16
-#define OUT_OF_RANGE_OFFSET1
-#define MULTIPLE_OUT_OF_RANGE_OFFSET   2
-#define PORT_COMMAND_CHANNEL_ERROR_OFFSET  7
-#define MC_INIT_COMPLETE_OFFSET8
-#define LEVELING_OPERATION_COMPLETED_OFFSET22
-#define DFI_PHY_WRLELV_MODE_OFFSET 24
-#define DFI_PHY_RDLVL_MODE_OFFSET  24
-#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
-#define VREF_EN_OFFSET 24
-#define PORT_ADDR_PROTECTION_EN_OFFSET 0
-#define AXI0_ADDRESS_RANGE_ENABLE  8
-#define AXI0_RANGE_PROT_BITS_0_OFFSET  24
-#define RDLVL_EN_OFFSET16
-#define RDLVL_GATE_EN_OFFSET   24
-#define WRLVL_EN_OFFSET0
-
-#define PHY_RX_CAL_DQ0_0_OFFSET0
-#define PHY_RX_CAL_DQ1_0_OFFSET16
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct fu540_ddrctl {
-   volatile u32 denali_ctl[265];
-};
-
-struct fu540_ddrphy {
-   volatile u32 denali_phy[1215];
-};
-
-/**
- * struct fu540_ddr_info
- *
- * @dev : pointer for the device
- * @info: UCLASS RAM information
- * @ctl : DDR controller base address
- * @phy : DDR PHY base address
- * @ctrl: DDR control base address
- * @physical_filter_ctrl: DDR physical filter control base address
- */
-struct fu540_ddr_info {
-   struct udevice *dev;
-   struct ram_info info;
-   struct fu540_ddrctl *ctl;
-   struct fu540_ddrphy *phy;
-   struct clk ddr_clk;
-   u32 *physical_filter_ctrl;
-};
-
-#if defined(CONFIG_SPL_BUILD)
-struct fu540_ddr_params {
-   struct fu540_ddrctl pctl_regs;
-   struct fu540_ddrphy phy_regs;
-};
-
-struct sifive_dmc_plat {
-   struct fu540_ddr_params ddr_params;
-};
-
-/*
- * TODO : It can be possible to use common sdram_copy_to_reg() API
- * n: Unit bytes
- */
-static void sdram_copy_to_reg(volatile u32 *dest,
- volatile u32 *src, u32 n)
-{
-   int i;
-
-   for (i = 0; i < n / sizeof(u32); i++) {
-   writel(

[PATCH v2 5/8] drivers: ram: add fu740 support

[Green Wan]

Add fu740 support for ram

Signed-off-by: Green Wan 
---
 drivers/ram/sifive/Kconfig  |  2 +-
 drivers/ram/sifive/sifive_ddr.c | 88 -
 2 files changed, 45 insertions(+), 45 deletions(-)

diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig
index a93cd0e..0aaac02 100644
--- a/drivers/ram/sifive/Kconfig
+++ b/drivers/ram/sifive/Kconfig
@@ -8,6 +8,6 @@ config RAM_SIFIVE
 config SIFIVE_DDR
bool "SiFive DDR driver"
depends on RAM_SIFIVE
-   default y if TARGET_SIFIVE_UNLEASHED
+   default y if TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED
help
  This enables DDR support for the platforms based on SiFive SoC.
diff --git a/drivers/ram/sifive/sifive_ddr.c b/drivers/ram/sifive/sifive_ddr.c
index b7c3ae1..2b23c87 100644
--- a/drivers/ram/sifive/sifive_ddr.c
+++ b/drivers/ram/sifive/sifive_ddr.c
@@ -12,7 +12,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -65,16 +64,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct fu540_ddrctl {
+struct sifive_ddrctl {
volatile u32 denali_ctl[265];
 };
 
-struct fu540_ddrphy {
+struct sifive_ddrphy {
volatile u32 denali_phy[1215];
 };
 
 /**
- * struct fu540_ddr_info
+ * struct sifive_ddr_info
  *
  * @dev : pointer for the device
  * @info: UCLASS RAM information
@@ -83,23 +82,23 @@ struct fu540_ddrphy {
  * @ctrl: DDR control base address
  * @physical_filter_ctrl: DDR physical filter control base address
  */
-struct fu540_ddr_info {
+struct sifive_ddr_info {
struct udevice *dev;
struct ram_info info;
-   struct fu540_ddrctl *ctl;
-   struct fu540_ddrphy *phy;
+   struct sifive_ddrctl *ctl;
+   struct sifive_ddrphy *phy;
struct clk ddr_clk;
u32 *physical_filter_ctrl;
 };
 
 #if defined(CONFIG_SPL_BUILD)
-struct fu540_ddr_params {
-   struct fu540_ddrctl pctl_regs;
-   struct fu540_ddrphy phy_regs;
+struct sifive_ddr_params {
+   struct sifive_ddrctl pctl_regs;
+   struct sifive_ddrphy phy_regs;
 };
 
 struct sifive_dmc_plat {
-   struct fu540_ddr_params ddr_params;
+   struct sifive_ddr_params ddr_params;
 };
 
 /*
@@ -118,7 +117,7 @@ static void sdram_copy_to_reg(volatile u32 *dest,
}
 }
 
-static void fu540_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr)
+static void sifive_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr)
 {
u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7F) - 1;
 
@@ -135,8 +134,8 @@ static void fu540_ddr_setup_range_protection(volatile u32 
*ctl, u64 end_addr)
 0x1 << PORT_ADDR_PROTECTION_EN_OFFSET);
 }
 
-static void fu540_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl,
-   u64 ddr_end)
+static void sifive_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl,
+u64 ddr_end)
 {
volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl;
 
@@ -149,7 +148,7 @@ static void fu540_ddr_start(volatile u32 *ctl, u32 
*physical_filter_ctrl,
filterreg[0] = 0x0f00UL | (ddr_end >> 2);
 }
 
-static void fu540_ddr_check_errata(u32 regbase, u32 updownreg)
+static void sifive_ddr_check_errata(u32 regbase, u32 updownreg)
 {
u64 fails = 0;
u32 dq= 0;
@@ -202,7 +201,7 @@ static void fu540_ddr_check_errata(u32 regbase, u32 
updownreg)
}
 }
 
-static u64 fu540_ddr_phy_fixup(volatile u32 *ddrphyreg)
+static u64 sifive_ddr_phy_fixup(volatile u32 *ddrphyreg)
 {
u32 slicebase = 0;
 
@@ -213,7 +212,7 @@ static u64 fu540_ddr_phy_fixup(volatile u32 *ddrphyreg)
for (u32 reg = 0; reg < 4; reg++) {
u32 updownreg = readl(regbase + reg + ddrphyreg);
 
-   fu540_ddr_check_errata(regbase, updownreg);
+   sifive_ddr_check_errata(regbase, updownreg);
}
slicebase += 128;
}
@@ -221,18 +220,18 @@ static u64 fu540_ddr_phy_fixup(volatile u32 *ddrphyreg)
return(0);
 }
 
-static u32 fu540_ddr_get_dram_class(volatile u32 *ctl)
+static u32 sifive_ddr_get_dram_class(volatile u32 *ctl)
 {
u32 reg = readl(DENALI_CTL_0 + ctl);
 
return ((reg >> DRAM_CLASS_OFFSET) & 0xF);
 }
 
-static int fu540_ddr_setup(struct udevice *dev)
+static int sifive_ddr_setup(struct udevice *dev)
 {
-   struct fu540_ddr_info *priv = dev_get_priv(dev);
+   struct sifive_ddr_info *priv = dev_get_priv(dev);
struct sifive_dmc_plat *plat = dev_get_plat(dev);
-   struct fu540_ddr_params *params = &plat->ddr_params;
+   struct sifive_ddr_params *params = &plat->ddr_params;
volatile u32 *denali_ctl =  priv->ctl->denali_ctl;
volatile u32 *denali_phy =  priv->phy->denali_phy;
const u64 ddr_size = priv->info.size;
@@ -251,7 +250,7 @@ static int fu540_ddr_setup

[PATCH v2 8/8] drivers: net: macb: add fu740 support

[Green Wan]

From: David Abdurachmanov 

Add fu740 support to macb ethernet driver

Signed-off-by: David Abdurachmanov 
Signed-off-by: Green Wan 
Reviewed-by: Ramon Fried 
---
 drivers/net/macb.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 57ea45e..df65d82 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -592,7 +592,11 @@ static int macb_sifive_clk_init(struct udevice *dev, ulong 
rate)
 * and output clock on GMII output signal GTX_CLK
 * 1 = MII mode. Use MII input signal TX_CLK in TX logic
 */
-   writel(rate != 12500, gemgxl_regs);
+   if (device_is_compatible(dev, "sifive,fu540-c000-gem"))
+   writel(rate != 12500, gemgxl_regs);
+   else if (device_is_compatible(dev, "sifive,fu740-c000-gem"))
+   writel(rate != 125125000, gemgxl_regs);
+
return 0;
 }
 
@@ -1507,6 +1511,8 @@ static const struct udevice_id macb_eth_ids[] = {
{ .compatible = "cdns,zynq-gem" },
{ .compatible = "sifive,fu540-c000-gem",
  .data = (ulong)&sifive_config },
+   { .compatible = "sifive,fu740-c000-gem",
+ .data = (ulong)&sifive_config },
{ .compatible = "microchip,mpfs-mss-gem",
  .data = (ulong)µchip_config },
{ }
-- 
2.7.4

[PATCH v2 3/8] drivers: clk: add fu740 support

[Green Wan]

Add fu740 support. One abstract layer is added for supporting
multiple chips such as fu540 and fu740.

Signed-off-by: Green Wan 
---
 drivers/clk/sifive/Kconfig   |   8 +-
 drivers/clk/sifive/Makefile  |   4 +-
 drivers/clk/sifive/fu540-prci.c  | 769 ++-
 drivers/clk/sifive/fu540-prci.h  |  22 ++
 drivers/clk/sifive/fu740-prci.c  | 158 
 drivers/clk/sifive/fu740-prci.h  |  22 ++
 drivers/clk/sifive/sifive-prci.c | 733 +
 drivers/clk/sifive/sifive-prci.h | 323 
 8 files changed, 1286 insertions(+), 753 deletions(-)
 create mode 100644 drivers/clk/sifive/fu540-prci.h
 create mode 100644 drivers/clk/sifive/fu740-prci.c
 create mode 100644 drivers/clk/sifive/fu740-prci.h
 create mode 100644 drivers/clk/sifive/sifive-prci.c
 create mode 100644 drivers/clk/sifive/sifive-prci.h

diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
index c4d0a1f..20fc004 100644
--- a/drivers/clk/sifive/Kconfig
+++ b/drivers/clk/sifive/Kconfig
@@ -6,11 +6,11 @@ config CLK_SIFIVE
help
  SoC drivers for SiFive Linux-capable SoCs.
 
-config CLK_SIFIVE_FU540_PRCI
-   bool "PRCI driver for SiFive FU540 SoCs"
+config CLK_SIFIVE_PRCI
+   bool "PRCI driver for SiFive SoCs"
depends on CLK_SIFIVE
select CLK_ANALOGBITS_WRPLL_CLN28HPC
help
  Supports the Power Reset Clock interface (PRCI) IP block found in
- FU540 SoCs.  If this kernel is meant to run on a SiFive FU540 SoC,
- enable this driver.
+ FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/
+ FU740 SoCs, enable this driver.
diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
index b224279..51348b1 100644
--- a/drivers/clk/sifive/Makefile
+++ b/drivers/clk/sifive/Makefile
@@ -1,3 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI)+= fu540-prci.o
+obj-y += sifive-prci.o
+
+obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu540-prci.o fu740-prci.o
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index b3882d0..ceb2c6f 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -5,6 +5,8 @@
  * Copyright (C) 2018 SiFive, Inc.
  * Wesley Terpstra
  * Paul Walmsley
+ * Zong Li
+ * Pragnesh Patel
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -15,632 +17,48 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
- * The FU540 PRCI implements clock and reset control for the SiFive
- * FU540-C000 chip.   This driver assumes that it has sole control
- * over all PRCI resources.
- *
- * This driver is based on the PRCI driver written by Wesley Terpstra.
- *
- * Refer, commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
- * https://github.com/riscv/riscv-linux
- *
  * References:
  * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
  */
 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
 #include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-/*
- * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
- * hfclk and rtcclk
- */
-#define EXPECTED_CLK_PARENT_COUNT  2
-
-/*
- * Register offsets and bitmasks
- */
-
-/* COREPLLCFG0 */
-#define PRCI_COREPLLCFG0_OFFSET0x4
-#define PRCI_COREPLLCFG0_DIVR_SHIFT0
-#define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT)
-#define PRCI_COREPLLCFG0_DIVF_SHIFT6
-#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
-#define PRCI_COREPLLCFG0_DIVQ_SHIFT15
-#define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
-#define PRCI_COREPLLCFG0_RANGE_SHIFT   18
-#define PRCI_COREPLLCFG0_RANGE_MASK(0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
-#define PRCI_COREPLLCFG0_BYPASS_SHIFT  24
-#define PRCI_COREPLLCFG0_BYPASS_MASK   (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
-#define PRCI_COREPLLCFG0_FSE_SHIFT 25
-#define PRCI_COREPLLCFG0_FSE_MASK  (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
-#define PRCI_COREPLLCFG0_LOCK_SHIFT31
-#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
-
-/* COREPLLCFG1 */
-#define PRCI_COREPLLCFG1_OFFSET0x8
-#define PRCI_COREPLLCFG1_CKE_SHIFT 31
-#define PRCI_COREPLLCFG1_CKE_MASK  (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT)
-
-/* DDRPLLCFG0 */
-#define PRCI_DDRPLLCFG0_OFFSET 0xc
-#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
-#define PRCI_DDRPLLCFG0_DIVR_MASK  (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
-#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6
-#define PRCI_DDRPLLCFG0_DIVF_MASK  (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
-#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15
-#define PRCI_DDRPLLCFG0_DIVQ_MASK  (0x7

[PATCH v2 6/8] drivers: pci: add pcie support for fu740

[Green Wan]

Add pcie driver for SiFive fu740, the driver depends on
fu740 gpio, clk and reset driver to do init. Force running at Gen1
for better capatible enumeration.

Several devices are tested:
a) M.2 NVMe SSD
b) USB-to-PCI adapter
c) Ethernet adapter (E1000 compatible)

Signed-off-by: Green Wan 
---
 drivers/pci/Kconfig   |   9 +
 drivers/pci/Makefile  |   1 +
 drivers/pci/pcie_sifive.c | 797 ++
 drivers/pci/pcie_sifive.h | 374 ++
 4 files changed, 1181 insertions(+)
 create mode 100644 drivers/pci/pcie_sifive.c
 create mode 100644 drivers/pci/pcie_sifive.h

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ba41787..b078e76 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -97,6 +97,15 @@ config PCIE_DW_MVEBU
  Armada-8K SoCs. The PCIe controller on Armada-8K is based on
  DesignWare hardware.
 
+config PCIE_SIFIVE_FU740
+   bool "Enable SiFive FU740 PCIe"
+   depends on CLK_SIFIVE_PRCI
+   depends on RESET_SIFIVE
+   depends on SIFIVE_GPIO
+   help
+ Say Y here if you want to enable PCIe controller support on
+ FU740.
+
 config PCIE_FSL
bool "FSL PowerPC PCIe support"
depends on DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 5ed94bc..5400d59 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -51,3 +51,4 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o
 obj-$(CONFIG_PCIE_DW_ROCKCHIP) += pcie_dw_rockchip.o
 obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
 obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
+obj-$(CONFIG_PCIE_SIFIVE_FU740) += pcie_sifive.o
diff --git a/drivers/pci/pcie_sifive.c b/drivers/pci/pcie_sifive.c
new file mode 100644
index 000..ada6087
--- /dev/null
+++ b/drivers/pci/pcie_sifive.c
@@ -0,0 +1,797 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SiFive FU740 DesignWare PCIe Controller
+ *
+ * Copyright (C) 2020-2021 SiFive, Inc.
+ *
+ * Based in early part on the i.MX6 PCIe host controller shim which is:
+ *
+ * Copyright (C) 2013 Kosagi
+ * http://www.kosagi.com
+ *
+ * Based on driver from author: Alan Mikhak 
+ */
+#include "pcie_sifive.h"
+#include 
+#include 
+
+/* Host Bridge Identification */
+#define DEVICE_NAME"SiFive FU740 PCIe Host Controller"
+#define VENDOR_ID  0x51fe
+#define DEVICE_ID  0x51fe
+
+static enum pcie_sifive_devtype pcie_sifive_get_devtype(struct pcie_sifive *sv)
+{
+   u32 val;
+
+   val = readl(sv->priv.iobase + MGMT_MISC_DEVICE_TYPE_OFFSET);
+   switch (val) {
+   case MGMT_MISC_DEVICE_TYPE_RC:
+   return SV_PCIE_HOST_TYPE;
+   case MGMT_MISC_DEVICE_TYPE_EP:
+   return SV_PCIE_ENDPOINT_TYPE;
+   default:
+   return SV_PCIE_UNKNOWN_TYPE;
+   }
+}
+
+static void pcie_sifive_priv_set_state(struct pcie_sifive *sv, u32 reg,
+  u32 bits, int state)
+{
+   u32 val;
+
+   val = readl(sv->priv.iobase + reg);
+   val = state ? (val | bits) : (val & !bits);
+   writel(val, sv->priv.iobase + reg);
+}
+
+static void pcie_sifive_assert_perstn(struct pcie_sifive *sv)
+{
+   dm_gpio_set_value(&sv->perstn_gpio, 0);
+   writel(0x0, sv->priv.iobase + PCIEX8MGMT_PERST_N);
+   mdelay(100);
+}
+
+static void pcie_sifive_power_on(struct pcie_sifive *sv)
+{
+   dm_gpio_set_value(&sv->pwren_gpio, 1);
+   mdelay(100);
+}
+
+static void pcie_sifive_deassert_perstn(struct pcie_sifive *sv)
+{
+   writel(0x1, sv->priv.iobase + PCIEX8MGMT_PERST_N);
+   dm_gpio_set_value(&sv->perstn_gpio, 1);
+   mdelay(100);
+}
+
+static int pcie_sifive_setphy(const u8 phy, const u8 write,
+ const u16 addr, const u16 wrdata,
+ u16 *rddata, struct pcie_sifive *sv)
+{
+   unsigned char ack = 0;
+
+   if (!(phy == 0 || phy == 1))
+   return -2;
+
+   /* setup phy para */
+   writel(addr, sv->priv.iobase +
+  (phy ? PCIEX8MGMT_PHY1_CR_PARA_ADDR :
+   PCIEX8MGMT_PHY0_CR_PARA_ADDR));
+
+   if (write)
+   writel(wrdata, sv->priv.iobase +
+  (phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_DATA :
+   PCIEX8MGMT_PHY0_CR_PARA_WR_DATA));
+
+   /* enable access if write */
+   if (write)
+   writel(1, sv->priv.iobase +
+  (phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_EN :
+   PCIEX8MGMT_PHY0_CR_PARA_WR_EN));
+   else
+   writel(1, sv->priv.iobase +
+  (phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_EN :
+   PCIEX8MGMT_PHY0_CR_PARA_RD_EN));
+
+   /* wait for wait_idle */
+   do {
+   u32 val;
+
+   val = readl(sv->priv.iobase +
+   (phy ? PCIEX8MGMT_PHY1_CR_PARA_ACK :
+PCIEX8MGMT_PHY0_CR_PARA_ACK));
+   if (val) {
+ 

Re: [PATCH u-boot v3.1 01/39] regmap: fix a serious pointer casting bug

[Pratyush Yadav]

Hi Marek,

On 16/03/21 04:07PM, Marek Behún wrote:
> There is a serious bug in regmap_read() and regmap_write() functions
> where an uint pointer is cast to (void *) which is then cast to (u8 *),
> (u16 *), (u32 *) or (u64 *), depending on register width of the map.
> 
> For example given a regmap with 16-bit register width the code
>   int val = 0x1234;
>   regmap_read(map, 0, &val);
> only changes the lower 16 bits of val on little-endian machines.
> The upper 16 bits will remain 0x1234.
> 
> Nobody noticed this probably because this bug can be triggered with
> regmap_write() only on big-endian architectures (which are not used by
> many people anymore), and on little endian this bug has consequences
> only if register width is 8 or 16 bits and also the memory place to
> which regmap_read() should store it's result has non-zero upper bits,
> which it seems doesn't happen anywhere in U-Boot normally. CI managed to
> trigger this bug in unit test of dm_test_devm_regmap_field when compiled
> for sandbox_defconfig using LTO.
> 
> Fix this by utilizing an union { u8; u16; u32; u64; } and reading data
> into this union / writing data from this union.
> 
> Signed-off-by: Marek Behún 
> Cc: Simon Glass 
> Cc: Heiko Schocher 
> Cc: Bin Meng 
> Cc: Pratyush Yadav 
> ---
>  drivers/core/regmap.c | 59 +--
>  1 file changed, 57 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
> index b51ce108c1..3206f3d112 100644
> --- a/drivers/core/regmap.c
> +++ b/drivers/core/regmap.c
> @@ -435,7 +435,36 @@ int regmap_raw_read(struct regmap *map, uint offset, 
> void *valp, size_t val_len)
>  
>  int regmap_read(struct regmap *map, uint offset, uint *valp)
>  {
> - return regmap_raw_read(map, offset, valp, map->width);
> + union {
> + u8 v8;
> + u16 v16;
> + u32 v32;
> + u64 v64;
> + } u;
> + int res;
> +
> + res = regmap_raw_read(map, offset, &u, map->width);
> + if (res)
> + return res;
> +
> + switch (map->width) {
> + case REGMAP_SIZE_8:
> + *valp = u.v8;
> + break;
> + case REGMAP_SIZE_16:
> + *valp = u.v16;
> + break;
> + case REGMAP_SIZE_32:
> + *valp = u.v32;
> + break;
> + case REGMAP_SIZE_64:
> + *valp = u.v64;
> + break;

I think this should fix the problem you are trying to solve.

But I see another problem with this code. What if someone wants to read 
8 bytes? IIUC, since valp points to a uint, *valp = u.v64 will result in 
4 bytes being truncated from the result.

I see two options:

- Change the uint pointer to u64 pointer and update every driver to use 
  a u64 when using the regmap.

- Change the uint pointer to void pointer and expect every driver to 
  pass a container with exactly the required size, based on map->width. 
  Update the ones that don't follow this.

I prefer the latter option.

> + default:
> + unreachable();
> + }
> +
> + return 0;
>  }
>  
>  static inline void __write_8(u8 *addr, const u8 *val,
> @@ -546,7 +575,33 @@ int regmap_raw_write(struct regmap *map, uint offset, 
> const void *val,
>  
>  int regmap_write(struct regmap *map, uint offset, uint val)
>  {
> - return regmap_raw_write(map, offset, &val, map->width);
> + union {
> + u8 v8;
> + u16 v16;
> + u32 v32;
> + u64 v64;
> + } u;
> +
> + switch (map->width) {
> + case REGMAP_SIZE_8:
> + u.v8 = val;
> + break;
> + case REGMAP_SIZE_16:
> + u.v16 = val;
> + break;
> + case REGMAP_SIZE_32:
> + u.v32 = val;
> + break;
> + case REGMAP_SIZE_64:
> + u.v64 = val;
> + break;
> + default:
> + debug("%s: regmap size %zu unknown\n", __func__,
> +   (size_t)map->width);
> + return -EINVAL;
> + }
> +
> + return regmap_raw_write(map, offset, &u, map->width);
>  }
>  
>  int regmap_update_bits(struct regmap *map, uint offset, uint mask, uint val)
> -- 
> 2.26.2
> 

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.

Re: Pull request for efi-2021-04-rc5

[Tom Rini]

On Tue, Mar 16, 2021 at 12:34:42PM +0100, Heinrich Schuchardt wrote:

> Dear Tom,
> 
> The following changes since commit 4103e13534141c31e4e9bf40848ab3a61dabce81:
> 
>   Prepare v2021.04-rc4 (2021-03-15 12:06:41 -0400)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-efi.git
> tags/efi-2021-04-rc5
> 
> for you to fetch changes up to 75d48d11db2e2f07659abbbf2dc0483e929b3fc2:
> 
>   doc: move README.dfu to HTML documentation (2021-03-16 09:37:04 +0100)
> 
> Gitlab CI showed no problems:
> https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/6789
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Description: PGP signature

Re: [PATCH u-boot v3.1 01/39] regmap: fix a serious pointer casting bug

[Marek Behun]

On Tue, 16 Mar 2021 22:04:17 +0530
Pratyush Yadav  wrote:

> > +   switch (map->width) {
> > +   case REGMAP_SIZE_8:
> > +   *valp = u.v8;
> > +   break;
> > +   case REGMAP_SIZE_16:
> > +   *valp = u.v16;
> > +   break;
> > +   case REGMAP_SIZE_32:
> > +   *valp = u.v32;
> > +   break;
> > +   case REGMAP_SIZE_64:
> > +   *valp = u.v64;
> > +   break;  
> 
> I think this should fix the problem you are trying to solve.
> 
> But I see another problem with this code. What if someone wants to read 
> 8 bytes? IIUC, since valp points to a uint, *valp = u.v64 will result in 
> 4 bytes being truncated from the result.
> 
> I see two options:
> 
> - Change the uint pointer to u64 pointer and update every driver to use 
>   a u64 when using the regmap.
> 
> - Change the uint pointer to void pointer and expect every driver to 
>   pass a container with exactly the required size, based on map->width. 
>   Update the ones that don't follow this.
> 
> I prefer the latter option.

If only these two options are possible, then the first option is
better. The regmap_read function ought to be simple, so no void *
pointer.

There is another option: if a value greater than ULONG_MAX is read, the
regmap_read() function will return -ERANGE. This way this function
will remain simple. ulong is 64-bit wide on 64-bit devices, so this
only is a problem when a 64-bit wide regmap is used on a 32-bit device.
I think we should keep regmap_read() simple, and for people who use a
64-bit wide regmap on 32-bit device, there is regmap_raw_read().

But I think this problem should be solved (however we decide) in a
follow-up patch. This patch fixes the pointer casting bug, and commits
should remain atomic (fixing one thing).

Marek

[PATCH] efi_loader: NULL dereference in EFI console

[Heinrich Schuchardt]

Even if CONFIG_DM_VIDEO=y and stdout="vidconsole" a video device may not be
available. Check the return values of the relevant functions.

If no video output device is available, assume that the serial console is
in use.

Signed-off-by: Heinrich Schuchardt 
---
 lib/efi_loader/efi_console.c | 51 +++-
 1 file changed, 38 insertions(+), 13 deletions(-)

diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
index c4003554c2..6040f3a99a 100644
--- a/lib/efi_loader/efi_console.c
+++ b/lib/efi_loader/efi_console.c
@@ -254,7 +254,7 @@ static bool cout_mode_matches(struct cout_mode *mode, int 
rows, int cols)
 }

 /**
- * query_console_serial() - query console size
+ * query_console_serial() - query serial console size
  *
  * When using a serial console or the net console we can only devise the
  * terminal size by querying the terminal using ECMA-48 control sequences.
@@ -299,6 +299,37 @@ out:
return ret;
 }

+/**
+ * query_vidconsole() - query video console size
+ *
+ *
+ * @rows:  pointer to return number of rows
+ * @cols:  pointer to return number of columns
+ * Returns:0 on success
+ */
+static int __maybe_unused query_vidconsole(int *rows, int *cols)
+{
+   const char *stdout_name = env_get("stdout");
+   struct stdio_dev *stdout_dev;
+   struct udevice *dev;
+   struct vidconsole_priv *priv;
+
+   if (!stdout_name || strncmp(stdout_name, "vidconsole", 10))
+   return -ENODEV;
+   stdout_dev = stdio_get_by_name("vidconsole");
+   if (!stdout_dev)
+   return -ENODEV;
+   dev = stdout_dev->priv;
+   if (!dev)
+   return -ENODEV;
+   priv = dev_get_uclass_priv(dev);
+   if (!priv)
+   return -ENODEV;
+   *rows = priv->rows;
+   *cols = priv->cols;
+   return 0;
+}
+
 /**
  * query_console_size() - update the mode table.
  *
@@ -308,21 +339,15 @@ out:
  */
 static void query_console_size(void)
 {
-   const char *stdout_name = env_get("stdout");
int rows = 25, cols = 80;
+   int ret = -ENODEV;

-   if (stdout_name && !strncmp(stdout_name, "vidconsole", 10) &&
-   IS_ENABLED(CONFIG_DM_VIDEO)) {
-   struct stdio_dev *stdout_dev =
-   stdio_get_by_name("vidconsole");
-   struct udevice *dev = stdout_dev->priv;
-   struct vidconsole_priv *priv =
-   dev_get_uclass_priv(dev);
-   rows = priv->rows;
-   cols = priv->cols;
-   } else if (query_console_serial(&rows, &cols)) {
+   if IS_ENABLED(CONFIG_DM_VIDEO)
+   ret = query_vidconsole(&rows, &cols);
+   if (ret)
+   ret = query_console_serial(&rows, &cols);
+   if (ret)
return;
-   }

/* Test if we can have Mode 1 */
if (cols >= 80 && rows >= 50) {
--
2.30.2

Re: [PATCH] arm: omap3: Make try_unlock_memory() static

[Adam Ford]

On Mon, Mar 15, 2021 at 1:43 AM Lokesh Vutla  wrote:
>
>
>
> On 07/03/21 9:23 am, Adam Ford wrote:
> > try_unlock_memory() is only used in one file, so make it static
> > in that file and remove it from the sys_proto header file. This
> > may help with some further optimization in the future.
> >
> > Signed-off-by: Adam Ford 
>
> one of omap3 board is failing to build. Can you take a look?
>
> https://source.denx.de/u-boot/custodians/u-boot-ti/-/jobs/237886
>

Question on preference...Would you prefer I move the unused function
into the #ifdef area, or should I just mark the function as
__maybe_unused?   I am not a fan of #ifdef, but I can move the
function there that is your preference.

adam

> Thanks and regards,
> Lokesh
>
> >
> > diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h 
> > b/arch/arm/include/asm/arch-omap3/sys_proto.h
> > index 32ac033515..656f848a73 100644
> > --- a/arch/arm/include/asm/arch-omap3/sys_proto.h
> > +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
> > @@ -60,7 +60,6 @@ u32 is_running_in_sram(void);
> >  u32 is_running_in_flash(void);
> >  u32 get_device_type(void);
> >  void secureworld_exit(void);
> > -void try_unlock_memory(void);
> >  u32 get_boot_type(void);
> >  void invalidate_dcache(u32);
> >  u32 wait_on_value(u32, u32, void *, u32);
> > diff --git a/arch/arm/mach-omap2/omap3/board.c 
> > b/arch/arm/mach-omap2/omap3/board.c
> > index 029bd54595..c621177580 100644
> > --- a/arch/arm/mach-omap2/omap3/board.c
> > +++ b/arch/arm/mach-omap2/omap3/board.c
> > @@ -145,7 +145,7 @@ void secureworld_exit(void)
> >   * Description: If chip is GP/EMU(special) type, unlock the SRAM for
> >   *  general use.
> >   
> > */
> > -void try_unlock_memory(void)
> > +static void try_unlock_memory(void)
> >  {
> >   int mode;
> >   int in_sdram = is_running_in_sdram();
> >

Re: [PATCH] arm: omap3: Make try_unlock_memory() static

[Tom Rini]

On Tue, Mar 16, 2021 at 12:18:05PM -0500, Adam Ford wrote:
> On Mon, Mar 15, 2021 at 1:43 AM Lokesh Vutla  wrote:
> >
> >
> >
> > On 07/03/21 9:23 am, Adam Ford wrote:
> > > try_unlock_memory() is only used in one file, so make it static
> > > in that file and remove it from the sys_proto header file. This
> > > may help with some further optimization in the future.
> > >
> > > Signed-off-by: Adam Ford 
> >
> > one of omap3 board is failing to build. Can you take a look?
> >
> > https://source.denx.de/u-boot/custodians/u-boot-ti/-/jobs/237886
> >
> 
> Question on preference...Would you prefer I move the unused function
> into the #ifdef area, or should I just mark the function as
> __maybe_unused?   I am not a fan of #ifdef, but I can move the
> function there that is your preference.

If there's already an #ifdef we should restructure the code to live
there, yes.

-- 
Tom


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Description: PGP signature

[PATCH v2 7/8] board: sifive: add HiFive Unmatched board support

[Green Wan]

Add dts, defconfig and board support for HiFive Unmatched.

Signed-off-by: Green Wan 
---
 arch/riscv/Kconfig |4 +
 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489 
 arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi|   40 +
 arch/riscv/dts/hifive-unmatched-a00.dts|  253 
 board/sifive/unmatched/Kconfig |   50 +
 board/sifive/unmatched/MAINTAINERS |9 +
 board/sifive/unmatched/Makefile|9 +
 board/sifive/unmatched/hifive-unmatched-fu740.c|   24 +
 board/sifive/unmatched/spl.c   |   85 ++
 common/spl/Kconfig |4 +-
 configs/sifive_unmatched_defconfig |   53 +
 doc/board/sifive/hifive_unmatched_fu740.rst|  536 +++
 drivers/reset/Kconfig  |2 +-
 include/configs/sifive-unmatched.h |   85 ++
 14 files changed, 2640 insertions(+), 3 deletions(-)
 create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
 create mode 100644 arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
 create mode 100644 arch/riscv/dts/hifive-unmatched-a00.dts
 create mode 100644 board/sifive/unmatched/Kconfig
 create mode 100644 board/sifive/unmatched/MAINTAINERS
 create mode 100644 board/sifive/unmatched/Makefile
 create mode 100644 board/sifive/unmatched/hifive-unmatched-fu740.c
 create mode 100644 board/sifive/unmatched/spl.c
 create mode 100644 configs/sifive_unmatched_defconfig
 create mode 100644 doc/board/sifive/hifive_unmatched_fu740.rst
 create mode 100644 include/configs/sifive-unmatched.h

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 323c358..7c053ac 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -20,6 +20,9 @@ config TARGET_QEMU_VIRT
 config TARGET_SIFIVE_UNLEASHED
bool "Support SiFive Unleashed Board"
 
+config TARGET_SIFIVE_UNMATCHED
+   bool "Support SiFive Unmatched Board"
+
 config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board"
 
@@ -56,6 +59,7 @@ source "board/AndesTech/ax25-ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
 source "board/microchip/mpfs_icicle/Kconfig"
 source "board/sifive/unleashed/Kconfig"
+source "board/sifive/unmatched/Kconfig"
 source "board/sipeed/maix/Kconfig"
 
 # platform-specific options below
diff --git a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi 
b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
new file mode 100644
index 000..fc3dfd1
--- /dev/null
+++ b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
@@ -0,0 +1,1489 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2020-2021 SiFive, Inc
+ */
+
+&dmc {
+   sifive,ddr-params = <
+   0x0a00  /* DENALI_CTL_00_DATA */
+   0x  /* DENALI_CTL_01_DATA */
+   0x  /* DENALI_CTL_02_DATA */
+   0x  /* DENALI_CTL_03_DATA */
+   0x  /* DENALI_CTL_04_DATA */
+   0x  /* DENALI_CTL_05_DATA */
+   0x000a  /* DENALI_CTL_06_DATA */
+   0x0002d362  /* DENALI_CTL_07_DATA */
+   0x00071073  /* DENALI_CTL_08_DATA */
+   0x0a1c0255  /* DENALI_CTL_09_DATA */
+   0x1c1c0400  /* DENALI_CTL_10_DATA */
+   0x0404c90b  /* DENALI_CTL_11_DATA */
+   0x2b050405  /* DENALI_CTL_12_DATA */
+   0x0d0c081e  /* DENALI_CTL_13_DATA */
+   0x08090914  /* DENALI_CTL_14_DATA */
+   0x00fde718  /* DENALI_CTL_15_DATA */
+   0x00180a05  /* DENALI_CTL_16_DATA */
+   0x008b130d  /* DENALI_CTL_17_DATA */
+   0x01000118  /* DENALI_CTL_18_DATA */
+   0x0d032001  /* DENALI_CTL_19_DATA */
+   0x  /* DENALI_CTL_20_DATA */
+   0x0101  /* DENALI_CTL_21_DATA */
+   0x  /* DENALI_CTL_22_DATA */
+   0x0a00  /* DENALI_CTL_23_DATA */
+   0x  /* DENALI_CTL_24_DATA */
+   0x01450100  /* DENALI_CTL_25_DATA */
+   0x1c36  /* DENALI_CTL_26_DATA */
+   0x0005  /* DENALI_CTL_27_DATA */
+   0x00170006  /* DENALI_CTL_28_DATA */
+   0x014e0400  /* DENALI_CTL_29_DATA */
+   0x0301  /* DENALI_CTL_30_DATA */
+   0x000a0e00  /* DENALI_CTL_31_DATA */
+   0x04030200  /* DENALI_CTL_32_DATA */
+   0x031f  /* DENALI_CTL_33_DATA */
+   0x00070004  /* DENALI_CTL_34_DATA */
+   0x  /* DENALI_CTL_35_DATA */
+   0x  /* DENALI_CTL_36_DATA */
+   0x  /* DENALI_CTL_37_DATA */
+   0x  /* DENALI_CTL_38_DATA 

[PATCH] ahci: mediatek: fix undefined reference of dev_err

[Frank Wunderlich]

From: Frank Wunderlich 

building with MTK_AHCI enabled results in implicit declaration and
undefined reference of dev_err followed by a segfault of gcc

drivers/ata/mtk_ahci.c: In function 'mtk_ahci_parse_property':
drivers/ata/mtk_ahci.c:65:4: warning:
implicit declaration of function 'dev_err'
drivers/ata/mtk_ahci.c:65: undefined reference to `dev_err'
in function `mtk_ahci_probe':
drivers/ata/mtk_ahci.c:92: undefined reference to `dev_err'
Segmentation fault

fix this by adding the dm/device_compat.h to includes

Signed-off-by: Frank Wunderlich 
---
 drivers/ata/mtk_ahci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/ata/mtk_ahci.c b/drivers/ata/mtk_ahci.c
index 554175bc0051..2c5227df306b 100644
--- a/drivers/ata/mtk_ahci.c
+++ b/drivers/ata/mtk_ahci.c
@@ -21,6 +21,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define SYS_CFG0x14
 #define SYS_CFG_SATA_MSK   GENMASK(31, 30)
-- 
2.25.1

Re: Flaky EFI test

[Heinrich Schuchardt]

On 16.03.21 02:57, Bin Meng wrote:
> On Tue, Mar 16, 2021 at 3:08 AM Tom Rini  wrote:
>>
>> On Tue, Mar 16, 2021 at 07:23:23AM +1300, Simon Glass wrote:
>>
>>> Hi Heinrich,
>>>
>>> This job failed:
>>>
>>> https://source.denx.de/u-boot/custodians/u-boot-sh/-/jobs/238476
>>>
>>> Do you think this is a flaky test or something else?
>>
>> It looks like qemu-x86 crashed on boot?
>
> Do we have better output of the tests?
>
> Regards,
> Bin
>
https://source.denx.de/u-boot/custodians/u-boot-sh/-/jobs/238476/raw

stops with this console output:

U-Boot 2021.04-rc4-69437-g60228ba289 (Mar 15 2021 - 17:34:22 +)
CPU:   QEMU Virtual CPU version 2.5+
DRAM:  128 MiB

So the last message is from announce_dram_init(). The console prompt is
not reached.

The normal output is:

U-Boot 2021.04-rc3-00017-gb764bf21e6 (Mar 16 2021 - 18:11:41 +0100)

CPU:   QEMU Virtual CPU version 2.5+
DRAM:  128 MiB
Video: 1024x768x32
Model: QEMU x86 (I440FX)
Net:   e1000: 52:54:00:12:34:56
   eth0: e1000#0

You will have to enable more debug output to find out where the failure
occurs.

Interestingly when I set CONFIG_LOG=y and CONFIG_LOG_DEFAULT_LEVEL=8
U-Boot's hangs in an endless loop in initcall_run_list() repeating:

include/initcall.h:44-initcall_run_list() initcall: fff05638
include/initcall.h:44-initcall_run_list() initcall: fff05638
include/initcall.h:44-initcall_run_list() initcall: fff05638

You will have to comment out debug statements in initcall_run_list() and
mtrr_commit().

You can reduce .gitlab.yaml to run multiple instances of only this
board. And then retry until you hopefully hit the problem.

The problem seems not to be easily reproducible, cf.

https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/6797

Best regards

Heinrich

Re: [PATCH 1/6 v3] efi_selftest: Remove loadfile2 for initrd selftests

[Heinrich Schuchardt]

On 3/14/21 8:05 PM, Ilias Apalodimas wrote:

We are redefining how u-boot locates the initrd to load via the kernel
LoadFile2 protocol.  This selftest is not relevant any more, so remove
it. A new one will be added later

Signed-off-by: Ilias Apalodimas 
Reviewed-by: Heinrich Schuchardt 


Applied to origin/master

Re: [PATCH 5/6 v3] efidebug: add multiple device path instances on Boot####

[Heinrich Schuchardt]

On 3/14/21 8:05 PM, Ilias Apalodimas wrote:

The UEFI spec allows a packed array of UEFI device paths in the
FilePathList[] of an EFI_LOAD_OPTION. The first file path must
describe the loaded image but the rest are OS specific.

Previous patches parse the device path and try to use the second
member of the array as an initrd. So let's modify efidebug slightly
and install the second file described in the command line as the
initrd device path.

Signed-off-by: Ilias Apalodimas 


efidebug boot add \
-b d00d label host 0:1 initrddump.efi \
-i host 0:1 startup.sh SUPERFLUOUS

efidebug boot add \
-b d00d label host 0:1 initrddump.efi SUPERFLUOUS \
-i host 0:1 startup.sh -s

efidebug boot add SUPERFLUOUS \
-b d00d label host 0:1 initrddump.efi \
-i host 0:1 startup.sh -s

These incorrect commands are accepted.

Please, correct the parsing routine.

Best regards

Heinrich


---
  cmd/efidebug.c| 193 ++
  doc/board/emulation/qemu_capsule_update.rst   |   4 +-
  doc/uefi/uefi.rst |   2 +-
  .../test_efi_capsule/test_capsule_firmware.py |   6 +-
  test/py/tests/test_efi_secboot/test_signed.py |  16 +-
  .../test_efi_secboot/test_signed_intca.py |   8 +-
  .../tests/test_efi_secboot/test_unsigned.py   |   8 +-
  7 files changed, 178 insertions(+), 59 deletions(-)

diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index bbbcb0a54643..a96146748c61 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -9,6 +9,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -19,6 +20,7 @@
  #include 
  #include 
  #include 
+#include 

  #define BS systab.boottime
  #define RT systab.runtime
@@ -794,6 +796,64 @@ static int do_efi_show_tables(struct cmd_tbl *cmdtp, int 
flag,
return CMD_RET_SUCCESS;
  }

+/**
+ * add_initrd_instance() - Append a device path to load_options pointing to an
+ *inirtd
+ *
+ * @dev:   Device
+ * @part:  Partition of thge disk
+ * @file:  Filename
+ * @fp:Device Path containing the existing load_options
+ * @fp_size:   New size of the device path after the addition
+ * Return: Pointer to the device path or ERR_PTR
+ *
+ */
+static
+struct efi_device_path *add_initrd_instance(const char *dev, const char *part,
+   const char *file,
+   const struct efi_device_path *fp,
+   efi_uintn_t *fp_size)
+{
+   struct efi_device_path *tmp_dp = NULL, *tmp_fp = NULL;
+   struct efi_device_path *final_fp = NULL, *initrd_dp = NULL;
+   efi_status_t ret;
+   const struct efi_initrd_dp id_dp = {
+   .vendor = {
+   {
+   DEVICE_PATH_TYPE_MEDIA_DEVICE,
+   DEVICE_PATH_SUB_TYPE_VENDOR_PATH,
+   sizeof(id_dp.vendor),
+   },
+   EFI_INITRD_MEDIA_GUID,
+   },
+   .end = {
+   DEVICE_PATH_TYPE_END,
+   DEVICE_PATH_SUB_TYPE_END,
+   sizeof(id_dp.end),
+   }
+   };
+
+   ret = efi_dp_from_name(dev, part, file, &tmp_dp, &tmp_fp);
+   if (ret != EFI_SUCCESS) {
+   printf("Cannot create device path for \"%s %s\"\n", part, file);
+   goto out;
+   }
+
+   initrd_dp = efi_dp_append((const struct efi_device_path *)&id_dp,
+ tmp_fp);
+   if (!initrd_dp)
+   goto out;
+   final_fp = efi_dp_concat(fp, initrd_dp);
+   *fp_size = efi_dp_size(fp) + efi_dp_size(initrd_dp) +
+   (2 * sizeof(struct efi_device_path));
+
+out:
+   efi_free_pool(initrd_dp);
+   efi_free_pool(tmp_dp);
+   efi_free_pool(tmp_fp);
+   return final_fp;
+}
+
  /**
   * do_efi_boot_add() - set UEFI load option
   *
@@ -806,7 +866,9 @@ static int do_efi_show_tables(struct cmd_tbl *cmdtp, int 
flag,
   *
   * Implement efidebug "boot add" sub-command. Create or change UEFI load 
option.
   *
- * efidebug boot add[:]  

+ * efidebug boot add -b[:] 
+ *   -i   [:] 
+ *   -s ''
   */
  static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag,
   int argc, char *const argv[])
@@ -819,55 +881,98 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int 
flag,
size_t label_len, label_len16;
u16 *label;
struct efi_device_path *device_path = NULL, *file_path = NULL;
+   struct efi_device_path *final_fp = NULL;
struct efi_load_option lo;
void *data = NULL;
efi_uintn_t size;
+   efi_uintn_t fp_size;
efi_status_t ret;
int r = CMD_RET_SUCCESS;
-
-   if (argc < 6 || argc > 7)
-   return CMD_RET_USAGE;
-
-   id = (int)simple_strtoul(argv[1], &endp, 16

[PATCH 1/1] imx6: icorem6: chmod 644 enigcam.bmp

[Heinrich Schuchardt]

Bitmap files should not be executable.

Signed-off-by: Heinrich Schuchardt 
---
 tools/logos/engicam.bmp | Bin
 1 file changed, 0 insertions(+), 0 deletions(-)
 mode change 100755 => 100644 tools/logos/engicam.bmp

diff --git a/tools/logos/engicam.bmp b/tools/logos/engicam.bmp
old mode 100755
new mode 100644
--
2.30.2