Re: [PATCH 1/2] drivers/rng: simplify Kconfig
On 3/7/20 7:58 AM, Sughosh Ganu wrote: hi Tom, On Wed, 4 Mar 2020 at 06:47, Heinrich Schuchardt mailto:xypron.g...@gmx.de>> wrote: For all sandbox systems with DM_RNG we enable RNG_SANDBOX. So we can simply set the default to yes. All rng drivers depend on DM_RNG. Use a single 'if' instead of individual dependencies. Now 'make menuconfig' shows the individual drivers neatly indented under the DM_RNG entry. Signed-off-by: Heinrich Schuchardt mailto:xypron.g...@gmx.de>> --- Can you please pick up the two patches of the series directly. Thanks. -sughosh This series has been applied to origin/master (bc40eb278b0c14b990556ea). Best regards Heinrich
Re: [PATCH v5 06/14] sifive: fu540: add ddr driver
On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
wrote:
>
> Add driver for fu540 to support ddr initialization in SPL.
> This driver is based on FSBL
> (https://github.com/sifive/freedom-u540-c000-bootloader.git)
>
> Signed-off-by: Pragnesh Patel
> ---
> drivers/ram/Kconfig | 7 +
> drivers/ram/Makefile | 2 +
> drivers/ram/sifive/Kconfig | 8 +
> drivers/ram/sifive/Makefile | 6 +
> drivers/ram/sifive/sdram_fu540.c | 295 +++
> drivers/ram/sifive/sdram_fu540.h | 94 ++
> 6 files changed, 412 insertions(+)
> create mode 100644 drivers/ram/sifive/Kconfig
> create mode 100644 drivers/ram/sifive/Makefile
> create mode 100644 drivers/ram/sifive/sdram_fu540.c
> create mode 100644 drivers/ram/sifive/sdram_fu540.h
>
> diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
> index 56fea7c94c..c60c63204c 100644
> --- a/drivers/ram/Kconfig
> +++ b/drivers/ram/Kconfig
> @@ -73,5 +73,12 @@ config IMXRT_SDRAM
> to support external memories like sdram, psram & nand.
> This driver is for the sdram memory interface with the SEMC.
>
> +config SIFIVE_DDR
> + bool "Enable SiFive DDR support"
> + depends on RAM
> + help
> + Enable support for the internal DDR Memory Controller of SiFive
> SoCs.
> +
> source "drivers/ram/rockchip/Kconfig"
> source "drivers/ram/stm32mp1/Kconfig"
> +source "drivers/ram/sifive/Kconfig"
> diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
> index 5c897410c6..12bf61510b 100644
> --- a/drivers/ram/Makefile
> +++ b/drivers/ram/Makefile
> @@ -17,3 +17,5 @@ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
> obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
>
> obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
> +
> +obj-$(CONFIG_SIFIVE_DDR) += sifive/
> diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig
> new file mode 100644
> index 00..b754700db8
> --- /dev/null
> +++ b/drivers/ram/sifive/Kconfig
> @@ -0,0 +1,8 @@
> +config SIFIVE_FU540_DDR
> + bool "SiFive FU540 DDR driver"
> + depends on DM && OF_CONTROL
> + select RAM
Do we need this driver for U-Boot proper?
> + select SPL_RAM if SPL
> + select SIFIVE_DDR
> + help
> + This enables DDR support for the platforms based on SiFive FU540
> SoC.
> diff --git a/drivers/ram/sifive/Makefile b/drivers/ram/sifive/Makefile
> new file mode 100644
> index 00..0187805199
> --- /dev/null
> +++ b/drivers/ram/sifive/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (c) 2020 SiFive, Inc
> +#
> +
> +obj-$(CONFIG_SIFIVE_FU540_DDR) += sdram_fu540.o
> diff --git a/drivers/ram/sifive/sdram_fu540.c
> b/drivers/ram/sifive/sdram_fu540.c
> new file mode 100644
> index 00..18926dbe15
> --- /dev/null
> +++ b/drivers/ram/sifive/sdram_fu540.c
> @@ -0,0 +1,295 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
> +/*
> + * (C) Copyright 2020 SiFive, Inc.
> + *
> + * Authors:
> + * Pragnesh Patel
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "sdram_fu540.h"
> +
> +/* n: Unit bytes */
> +void sdram_copy_to_reg(volatile u32 *dest, volatile u32 *src, u32 n)
This should be static, also use "int n"?
> +{
> + int i;
> +
> + for (i = 0; i < n / sizeof(u32); i++) {
> + writel(*src, dest);
> + src++;
> + dest++;
> + }
> +}
> +
> +static void ddr_setuprangeprotection(volatile u32 *ctl, u64 end_addr)
__maybe_unused ? Otherwise use #ifdef #endif ?
> +{
> + writel(0x0, DENALI_CTL_209 + ctl);
> + u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7F) - 1;
nits: move the variable declaration
> +
> + writel(end_addr_16kblocks, DENALI_CTL_210 + ctl);
> + writel(0x0, DENALI_CTL_212 + ctl);
> + writel(0x0, DENALI_CTL_214 + ctl);
> + writel(0x0, DENALI_CTL_216 + ctl);
> + setbits_le32(DENALI_CTL_224 + ctl,
> +0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
> + writel(0x, DENALI_CTL_225 + ctl);
> + setbits_le32(DENALI_CTL_208 + ctl, 0x1 << AXI0_ADDRESS_RANGE_ENABLE);
> + setbits_le32(DENALI_CTL_208 + ctl,
> +0x1 << PORT_ADDR_PROTECTION_EN_OFFSET);
> +}
> +
> +static void ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl, u64
> ddr_end)
__maybe_unused ?
> +{
> + setbits_le32(DENALI_CTL_0 + ctl, 0x1);
> + while ((readl(DENALI_CTL_132 + ctl) & (1 << MC_INIT_COMPLETE_OFFSET))
> + == 0) {
> + }
> +
Use
do {
val = readl(DENALI_CTL_132 + ctl) & (1 << MC_INIT_COMPLETE_OFFSET);
} while (val == 0)
?
> + // Disable the BusBlocker in front of the controller AXI slave ports
nits: use /* */
> + volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl;
Please move the variable declaration to the beginning of this function
> +
> + filterreg[0] = 0x0f
Re: [PATCH v5 07/14] sifive: dts: fu540: Add DDR controller and phy register settings
On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
wrote:
>
> Add DDR controller and phy register settings, taken from fsbl
> (https://github.com/sifive/freedom-u540-c000-bootloader.git)
>
> Signed-off-by: Pragnesh Patel
> ---
> arch/riscv/dts/fu540-c000-u-boot.dtsi |7 +
> arch/riscv/dts/fu540-sdram-ddr4.dtsi | 1489 +
> .../dts/hifive-unleashed-a00-u-boot.dtsi |1 +
> 3 files changed, 1497 insertions(+)
> create mode 100644 arch/riscv/dts/fu540-sdram-ddr4.dtsi
>
> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
> b/arch/riscv/dts/fu540-c000-u-boot.dtsi
> index 2d3d62801f..b8cef67885 100644
> --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
> @@ -40,6 +40,13 @@
> reg = <0x0 0x200 0x0 0xc>;
> u-boot,dm-spl;
> };
> + dmc: dmc@100b {
> + compatible = "sifive,fu540-ddr";
> + reg = <0x0 0x100b 0x0 0x0800
> + 0x0 0x100b2000 0x0 0x2000
> + 0x0 0x100b8000 0x0 0x0fff>;
> + u-boot,dm-spl;
> + };
> };
> };
>
> diff --git a/arch/riscv/dts/fu540-sdram-ddr4.dtsi
> b/arch/riscv/dts/fu540-sdram-ddr4.dtsi
> new file mode 100644
> index 00..370c53800d
> --- /dev/null
> +++ b/arch/riscv/dts/fu540-sdram-ddr4.dtsi
> @@ -0,0 +1,1489 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2020 SiFive, Inc
> + */
> +
> +&dmc {
> + sifive,sdram-params = <
Are these parameter values SoC specific, or board specific? If it's
board specific, it should be renamed to
hifive-unleashed-a00_sdram_ddr4.dtsi, or put it directly into
hifive-unleashed-a00-u-boot.dtsi
> + 0x0a00 /* DENALI_CTL_00_DATA */
> + 0x /* DENALI_CTL_01_DATA */
> + 0x /* DENALI_CTL_02_DATA */
> + 0x /* DENALI_CTL_03_DATA */
> + 0x /* DENALI_CTL_04_DATA */
> + 0x /* DENALI_CTL_05_DATA */
> + 0x000a /* DENALI_CTL_06_DATA */
> + 0x0002d362 /* DENALI_CTL_07_DATA */
> + 0x00071073 /* DENALI_CTL_08_DATA */
> + 0x0a1c0255 /* DENALI_CTL_09_DATA */
> + 0x1c1c0400 /* DENALI_CTL_10_DATA */
[snip]
Regards,
Bin
Re: [PATCH v5 08/14] clk: sifive: fu540-prci: Add clock enable and disable ops
On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
wrote:
>
> Added clock enable and disable functions in prci ops
>
> Signed-off-by: Pragnesh Patel
> ---
> drivers/clk/sifive/fu540-prci.c | 75 +++--
> 1 file changed, 72 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
> index 8847178001..c02c0466a8 100644
> --- a/drivers/clk/sifive/fu540-prci.c
> +++ b/drivers/clk/sifive/fu540-prci.c
> @@ -68,6 +68,11 @@
> #define PRCI_COREPLLCFG0_LOCK_SHIFT31
> #define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
>
> +/* COREPLLCFG1 */
> +#define PRCI_COREPLLCFG1_OFFSET0x8
> +#define PRCI_COREPLLCFG1_CKE_SHIFT 31
> +#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT)
> +
> /* DDRPLLCFG0 */
> #define PRCI_DDRPLLCFG0_OFFSET 0xc
> #define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
> @@ -87,7 +92,7 @@
>
> /* DDRPLLCFG1 */
> #define PRCI_DDRPLLCFG1_OFFSET 0x10
> -#define PRCI_DDRPLLCFG1_CKE_SHIFT 24
> +#define PRCI_DDRPLLCFG1_CKE_SHIFT 31
> #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
>
> /* GEMGXLPLLCFG0 */
> @@ -114,7 +119,7 @@
>
> /* GEMGXLPLLCFG1 */
> #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
> -#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24
> +#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31
> #define PRCI_GEMGXLPLLCFG1_CKE_MASK(0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
>
> /* CORECLKSEL */
> @@ -142,7 +147,7 @@
> (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
>
> /* CLKMUXSTATUSREG */
> -#define PRCI_CLKMUXSTATUSREG_OFFSET0x2c
> +#define PRCI_CLKMUXSTATUSREG_OFFSET0x2c
> #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
> #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
> (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
> @@ -170,6 +175,7 @@ struct __prci_data {
> * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else
> NULL)
> * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
> * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base
> address
> + * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base
> address
> *
> * @enable_bypass and @disable_bypass are used for WRPLL instances
> * that contain a separate external glitchless clock mux downstream
> @@ -180,6 +186,7 @@ struct __prci_wrpll_data {
> void (*enable_bypass)(struct __prci_data *pd);
> void (*disable_bypass)(struct __prci_data *pd);
> u8 cfg0_offs;
> + u8 cfg1_offs;
> };
>
> struct __prci_clock;
> @@ -194,6 +201,7 @@ struct __prci_clock_ops {
> unsigned long *parent_rate);
> unsigned long (*recalc_rate)(struct __prci_clock *pc,
> unsigned long parent_rate);
> + int (*enable_clk)(struct __prci_clock *pc, bool enable);
> };
>
> /**
> @@ -356,6 +364,13 @@ static void __prci_wrpll_write_cfg(struct __prci_data
> *pd,
> memcpy(&pwd->c, c, sizeof(*c));
> }
>
> +static void __prci_wrpll_write_cfg1(struct __prci_data *pd,
nits: we should also rename the existing function
__prci_wrpll_write_cfg() to __prci_wrpll_write_cfg0()
> + struct __prci_wrpll_data *pwd,
> + u32 enable)
> +{
> + __prci_writel(enable, pwd->cfg1_offs, pd);
> +}
> +
[snip]
Regards,
Bin
Re: [PATCH v5 09/14] clk: sifive: fu540-prci: Add clock initialization for SPL
On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
wrote:
>
> Set corepll, ddrpll and ethernet PLL for u-boot-spl
>
> Signed-off-by: Pragnesh Patel
> ---
> drivers/clk/sifive/fu540-prci.c | 94 +
> 1 file changed, 94 insertions(+)
>
> diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
> index c02c0466a8..f043b0eccb 100644
> --- a/drivers/clk/sifive/fu540-prci.c
> +++ b/drivers/clk/sifive/fu540-prci.c
> @@ -41,6 +41,10 @@
> #include
> #include
>
> +#define DDRCTLPLL_F55
> +#define DDRCTLPLL_Q2
> +#define MHz100
> +
> /*
> * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
> * hfclk and rtcclk
> @@ -152,6 +156,27 @@
> #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
> (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
>
> +/* PROCMONCFG */
> +#define PRCI_PROCMONCFG_OFFSET 0xF0
> +#define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24
> +#define PRCI_PROCMONCFG_CORE_CLOCK_MASK \
> + (0x1 << PRCI_PROCMONCFG_CORE_CLOCK_SHIFT)
> +
> +#define PLL_R(x) \
> + ((x) << PRCI_DDRPLLCFG0_DIVR_SHIFT) & PRCI_DDRPLLCFG0_DIVR_MASK
> +#define PLL_F(x) \
> + ((x) << PRCI_DDRPLLCFG0_DIVF_SHIFT) & PRCI_DDRPLLCFG0_DIVF_MASK
> +#define PLL_Q(x) \
> + ((x) << PRCI_DDRPLLCFG0_DIVQ_SHIFT) & PRCI_DDRPLLCFG0_DIVQ_MASK
> +#define PLL_RANGE(x) \
> + ((x) << PRCI_DDRPLLCFG0_RANGE_SHIFT) & PRCI_DDRPLLCFG0_RANGE_MASK
> +#define PLL_BYPASS(x) \
> + ((x) << PRCI_DDRPLLCFG0_BYPASS_SHIFT) & PRCI_DDRPLLCFG0_BYPASS_MASK
> +#define PLL_FSE(x) \
> + ((x) << PRCI_DDRPLLCFG0_FSE_SHIFT) & PRCI_DDRPLLCFG0_FSE_MASK
> +#define PLL_LOCK(x) \
> + ((x) << PRCI_DDRPLLCFG0_LOCK_SHIFT) & PRCI_DDRPLLCFG0_LOCK_MASK
> +
> /*
> * Private structures
> */
> @@ -672,6 +697,75 @@ static int sifive_fu540_prci_probe(struct udevice *dev)
> __prci_wrpll_read_cfg(pd, pc->pwd);
> }
>
> +#ifdef CONFIG_SPL_BUILD
I think the correct way is to add clocks property to each device node
that use the clock, e.g.:
clocks = <&prci PRCI_CLK_COREPLL>;
Then we don't need anything added here, instead we call clk_enable()
from the device driver to enable their clock.
> + u32 v;
> + struct clk clock;
> +
> + v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
> + v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
> +
> + clock.id = PRCI_CLK_COREPLL;
> +
> + if (v) {
> + /* corepll 500 Mhz */
> + sifive_fu540_prci_set_rate(&clock, 500UL * MHz);
> + } else {
> + /* corepll 1 Ghz */
> + sifive_fu540_prci_set_rate(&clock, 1000UL * MHz);
> + }
> +
> + sifive_fu540_prci_clock_enable(&__prci_init_clocks[clock.id], 1);
> +
> + //DDR init
> + u32 ddrctlmhz =
> + (PLL_R(0)) |
> + (PLL_F(DDRCTLPLL_F)) |
> + (PLL_Q(DDRCTLPLL_Q)) |
> + (PLL_RANGE(0x4)) |
> + (PLL_BYPASS(0)) |
> + (PLL_FSE(1));
> + __prci_writel(ddrctlmhz, PRCI_DDRPLLCFG0_OFFSET, pd);
> +
> + clock.id = PRCI_CLK_DDRPLL;
> + sifive_fu540_prci_clock_enable(&__prci_init_clocks[clock.id], 1);
> +
> + /* Release DDR reset */
> + v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
> + v |= PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK;
> + __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
> +
> + // HACK to get the '1 full controller clock cycle'.
> + asm volatile ("fence");
> + v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
> + v |= (PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK |
> + PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK |
> + PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK);
> + __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
> + // HACK to get the '1 full controller clock cycle'.
> + asm volatile ("fence");
> +
> + /* These take like 16 cycles to actually propagate. We can't go
> sending
> +* stuff before they come out of reset. So wait. (TODO: Add a register
> +* to read the current reset states, or DDR Control device?)
> +*/
> + for (int i = 0; i < 256; i++)
> + asm volatile ("nop");
> +
> + /* GEMGXL init */
> + clock.id = PRCI_CLK_GEMGXLPLL;
> + sifive_fu540_prci_set_rate(&clock, 125UL * MHz);
> + sifive_fu540_prci_clock_enable(&__prci_init_clocks[clock.id], 1);
> +
> + /* Release GEMGXL reset */
> + v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
> + v |= PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK;
> + __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
> +
> + /* Procmon => core clock */
> + __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
> + pd);
> +#endif
> +
> return 0;
> }
Regards,
Bin
RE: [PATCH v5 08/14] clk: sifive: fu540-prci: Add clock enable and disable ops
Hi Bin,
>-Original Message-
>From: Bin Meng
>Sent: 13 March 2020 13:27
>To: Pragnesh Patel
>Cc: U-Boot Mailing List ; Atish Patra
>; Palmer Dabbelt ; Paul
>Walmsley ; Jagan Teki
>; Troy Benjegerdes
>; Anup Patel ; Sagar
>Kadam ; Rick Chen ; Lukasz
>Majewski ; Anatolij Gustschin ; Simon
>Glass
>Subject: Re: [PATCH v5 08/14] clk: sifive: fu540-prci: Add clock enable and
>disable ops
>
>On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
> wrote:
>>
>> Added clock enable and disable functions in prci ops
>>
>> Signed-off-by: Pragnesh Patel
>> ---
>> drivers/clk/sifive/fu540-prci.c | 75
>> +++--
>> 1 file changed, 72 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/sifive/fu540-prci.c
>> b/drivers/clk/sifive/fu540-prci.c index 8847178001..c02c0466a8 100644
>> --- a/drivers/clk/sifive/fu540-prci.c
>> +++ b/drivers/clk/sifive/fu540-prci.c
>> @@ -68,6 +68,11 @@
>> #define PRCI_COREPLLCFG0_LOCK_SHIFT31
>> #define PRCI_COREPLLCFG0_LOCK_MASK (0x1 <<
>PRCI_COREPLLCFG0_LOCK_SHIFT)
>>
>> +/* COREPLLCFG1 */
>> +#define PRCI_COREPLLCFG1_OFFSET0x8
>> +#define PRCI_COREPLLCFG1_CKE_SHIFT 31
>> +#define PRCI_COREPLLCFG1_CKE_MASK (0x1 <<
>PRCI_COREPLLCFG1_CKE_SHIFT)
>> +
>> /* DDRPLLCFG0 */
>> #define PRCI_DDRPLLCFG0_OFFSET 0xc
>> #define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
>> @@ -87,7 +92,7 @@
>>
>> /* DDRPLLCFG1 */
>> #define PRCI_DDRPLLCFG1_OFFSET 0x10
>> -#define PRCI_DDRPLLCFG1_CKE_SHIFT 24
>> +#define PRCI_DDRPLLCFG1_CKE_SHIFT 31
>> #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 <<
>PRCI_DDRPLLCFG1_CKE_SHIFT)
>>
>> /* GEMGXLPLLCFG0 */
>> @@ -114,7 +119,7 @@
>>
>> /* GEMGXLPLLCFG1 */
>> #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
>> -#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24
>> +#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31
>> #define PRCI_GEMGXLPLLCFG1_CKE_MASK(0x1 <<
>PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
>>
>> /* CORECLKSEL */
>> @@ -142,7 +147,7 @@
>> (0x1 <<
>> PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
>>
>> /* CLKMUXSTATUSREG */
>> -#define PRCI_CLKMUXSTATUSREG_OFFSET0x2c
>> +#define PRCI_CLKMUXSTATUSREG_OFFSET0x2c
>> #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 #define
>> PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
>> (0x1 <<
>> PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
>> @@ -170,6 +175,7 @@ struct __prci_data {
>> * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else
>NULL)
>> * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
>> * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI
>> base address
>> + * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI
>> + base address
>> *
>> * @enable_bypass and @disable_bypass are used for WRPLL instances
>> * that contain a separate external glitchless clock mux downstream
>> @@ -180,6 +186,7 @@ struct __prci_wrpll_data {
>> void (*enable_bypass)(struct __prci_data *pd);
>> void (*disable_bypass)(struct __prci_data *pd);
>> u8 cfg0_offs;
>> + u8 cfg1_offs;
>> };
>>
>> struct __prci_clock;
>> @@ -194,6 +201,7 @@ struct __prci_clock_ops {
>> unsigned long *parent_rate);
>> unsigned long (*recalc_rate)(struct __prci_clock *pc,
>> unsigned long parent_rate);
>> + int (*enable_clk)(struct __prci_clock *pc, bool enable);
>> };
>>
>> /**
>> @@ -356,6 +364,13 @@ static void __prci_wrpll_write_cfg(struct
>__prci_data *pd,
>> memcpy(&pwd->c, c, sizeof(*c)); }
>>
>> +static void __prci_wrpll_write_cfg1(struct __prci_data *pd,
>
>nits: we should also rename the existing function
>__prci_wrpll_write_cfg() to __prci_wrpll_write_cfg0()
>
I think you are right. I will check and update in v6.
>> + struct __prci_wrpll_data *pwd,
>> + u32 enable) {
>> + __prci_writel(enable, pwd->cfg1_offs, pd); }
>> +
>
>[snip]
>
>Regards,
>Bin
Re: [PATCH v5 10/14] riscv: sifive: fu540: add SPL configuration
On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
wrote:
>
> Add a support for SPL which will boot from L2 LIM (0x0800_) and
> then boot U-boot FIT image including OpenSBI FW_DYNAMIC firmware
nits: U-Boot
> and U-Boot proper images from 1st partition of MMC boot devices.
>
> SPL related code is leverage from FSBL
> (https://github.com/sifive/freedom-u540-c000-bootloader.git)
>
> Signed-off-by: Pragnesh Patel
> ---
> board/sifive/fu540/Kconfig| 8 +++
> board/sifive/fu540/Makefile | 4 ++
> board/sifive/fu540/fu540-memory-map.h | 23
> board/sifive/fu540/fu540.c| 24 +
> board/sifive/fu540/spl.c | 78 +++
> include/configs/sifive-fu540.h| 18 +++
> 6 files changed, 155 insertions(+)
> create mode 100644 board/sifive/fu540/fu540-memory-map.h
> create mode 100644 board/sifive/fu540/spl.c
>
> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
> index 900197bbb2..ebe3472f9a 100644
> --- a/board/sifive/fu540/Kconfig
> +++ b/board/sifive/fu540/Kconfig
> @@ -13,12 +13,20 @@ config SYS_CONFIG_NAME
> default "sifive-fu540"
>
> config SYS_TEXT_BASE
> + default 0x8020 if SPL
> default 0x8000 if !RISCV_SMODE
> default 0x8020 if RISCV_SMODE
>
> +config SPL_TEXT_BASE
> + default 0x0800
> +
> +config SPL_OPENSBI_LOAD_ADDR
> + default 0x8000
> +
> config BOARD_SPECIFIC_OPTIONS # dummy
> def_bool y
> select GENERIC_RISCV
> + select SUPPORT_SPL
> imply CMD_DHCP
> imply CMD_EXT2
> imply CMD_EXT4
> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
> index 6e1862c475..b05e2f5807 100644
> --- a/board/sifive/fu540/Makefile
> +++ b/board/sifive/fu540/Makefile
> @@ -3,3 +3,7 @@
> # Copyright (c) 2019 Western Digital Corporation or its affiliates.
>
> obj-y += fu540.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +endif
> diff --git a/board/sifive/fu540/fu540-memory-map.h
> b/board/sifive/fu540/fu540-memory-map.h
> new file mode 100644
> index 00..cba464652b
> --- /dev/null
> +++ b/board/sifive/fu540/fu540-memory-map.h
This file is not needed. See below.
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +
> +#ifndef FU540_MEMORY_MAP
> +#define FU540_MEMORY_MAP
> +
> +#include
> +
> +/
> + * Platform definitions
> +
> */
> +
> +/* Memory map */
> +#define GPIO_CTRL_ADDR _AC(0x1006, UL)
> +
> +/* Helper functions */
> +#define _REG32(p, i)(*(volatile uint32_t *)((p) + (i)))
> +
> +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
> +
> +#endif /* FU540_MEMORY_MAP */
> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
> index 6c642b3082..89a65eb3fb 100644
> --- a/board/sifive/fu540/fu540.c
> +++ b/board/sifive/fu540/fu540.c
> @@ -11,6 +11,7 @@
> #include
> #include
> #include
> +#include
>
> /*
> * This define is a value used for error/unknown serial.
> @@ -114,3 +115,26 @@ int board_init(void)
>
> return 0;
> }
> +
> +#ifdef CONFIG_SPL
> +void board_boot_order(u32 *spl_boot_list)
> +{
> + u8 i;
> + u32 boot_devices[] = {
> +#ifdef CONFIG_SPL_MMC_SUPPORT
> + BOOT_DEVICE_MMC1,
> +#endif
> + };
> +
> + for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
> + spl_boot_list[i] = boot_devices[i];
> +}
> +#endif
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> + /* boot using first FIT config */
> + return 0;
> +}
> +#endif
> diff --git a/board/sifive/fu540/spl.c b/board/sifive/fu540/spl.c
> new file mode 100644
> index 00..522bc24753
> --- /dev/null
> +++ b/board/sifive/fu540/spl.c
> @@ -0,0 +1,78 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + *
> + * Authors:
> + * Pragnesh Patel
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#include "fu540-memory-map.h"
> +
> +#define DDRCTLPLL_F 55
> +#define DDRCTLPLL_Q 2
These 2 macros are not needed.
> +
> +#define PHY_NRESET 0x1000
> +
> +long nsec_per_cyc = 300; /* 33.333MHz */
> +void nsleep(long nsec)
> +{
> + long step = nsec_per_cyc * 2;
> +
> + while (nsec > 0)
> + nsec -= step;
> +}
> +
> +void init_clk_and_ddr(void)
> +{
> + int ret;
> + struct udevice *dev;
> +
> + /* PRCI init */
> + ret = uclass_get_device(UCLASS_CLK, 0, &dev);
> + if (ret) {
> + debug("Clock init failed: %d\n", ret);
> + return;
> + }
> +
> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (ret) {
> + printf("DRAM init failed: %d\n", ret);
> + return;
>
Re: [PATCH v5 11/14] configs: fu540: Add config options for U-boot SPL
On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel wrote: > > With sifive_fu540_defconfig: Please use "U-Boot" in the commit title > > User can use FSBL or u-boot-spl.bin anyone at a time. > > For FSBL, > fsbl->fw_payload.bin(opensbi+u-boot) > > For u-boot-spl.bin, > u-boot-spl.bin->FIT image(opensbi+u-boot+dtb) > > U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with > u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT > image u-boot.itb from 1st partition of SD card (replace fw_payload.bin > with u-boot.itb) into RAM. > > U-boot SPL expects u-boot.itb FIT image in the 1st partition of SD U-Boot > card irrespective of GUID > > Signed-off-by: Pragnesh Patel > --- > configs/sifive_fu540_defconfig | 11 +++ > 1 file changed, 11 insertions(+) > > diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig > index 6d61e6c960..1b33c81be4 100644 > --- a/configs/sifive_fu540_defconfig > +++ b/configs/sifive_fu540_defconfig > @@ -12,3 +12,14 @@ CONFIG_DISPLAY_BOARDINFO=y > CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00" > CONFIG_SYS_RELOC_GD_ENV_ADDR=y > CONFIG_DM_MTD=y > +CONFIG_SPL_SEPARATE_BSS=y > +CONFIG_SPL=y > +CONFIG_SPL_MMC_SUPPORT=y > +CONFIG_SPL_SPI_SUPPORT=y > +CONFIG_SPL_YMODEM_SUPPORT=y > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=1 > +CONFIG_SPL_CLK=y > +CONFIG_SPL_PAYLOAD="u-boot.itb" > +CONFIG_SYS_MALLOC_F_LEN=0x3000 > +CONFIG_SIFIVE_FU540_DDR=y > -- Please make sure this is exactly the same as: $ make sifive_fu540_defconfig $ make savedefconfig Compare the generated defconfig with sifive_fu540_defconfig Regards, Bin
Re: [PATCH v5 12/14] riscv: sifive: fu540: enable all cache ways from u-boot proper
On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
wrote:
>
> Enable all cache ways from u-boot proper.
U-Boot
>
> Signed-off-by: Pragnesh Patel
> ---
> board/sifive/fu540/Makefile | 1 +
> board/sifive/fu540/cache.c | 20
> board/sifive/fu540/cache.h | 13 +
> board/sifive/fu540/fu540.c | 6 --
> 4 files changed, 38 insertions(+), 2 deletions(-)
> create mode 100644 board/sifive/fu540/cache.c
> create mode 100644 board/sifive/fu540/cache.h
>
> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
> index b05e2f5807..3b867bbd89 100644
> --- a/board/sifive/fu540/Makefile
> +++ b/board/sifive/fu540/Makefile
> @@ -3,6 +3,7 @@
> # Copyright (c) 2019 Western Digital Corporation or its affiliates.
>
> obj-y += fu540.o
> +obj-y += cache.o
>
> ifdef CONFIG_SPL_BUILD
> obj-y += spl.o
> diff --git a/board/sifive/fu540/cache.c b/board/sifive/fu540/cache.c
> new file mode 100644
> index 00..a0bcd2ba48
> --- /dev/null
> +++ b/board/sifive/fu540/cache.c
This should be put into arch/riscv/cpu/fu540/cache.c
> @@ -0,0 +1,20 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +#include
> +
> +/* Register offsets */
> +#define CACHE_ENABLE 0x008
> +
> +/* Enable ways; allow cache to use these ways */
> +void cache_enable_ways(u64 base_addr, u8 value)
> +{
> + volatile u32 *enable = (volatile u32 *)(base_addr +
> + CACHE_ENABLE);
> + /* memory barrier */
> + mb();
> + (*enable) = value;
> + /* memory barrier */
> + mb();
> +}
> diff --git a/board/sifive/fu540/cache.h b/board/sifive/fu540/cache.h
> new file mode 100644
> index 00..425124a23b
> --- /dev/null
> +++ b/board/sifive/fu540/cache.h
arch/riscv/include/asm/arch-fu540/cache.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +
> +#ifndef FU540_CACHE_H
> +#define FU540_CACHE_H
> +
> +#define CACHE_CTRL_ADDR _AC(0x201, UL)
> +
> +void cache_enable_ways(u64 base_addr, u8 value);
> +
> +#endif /* FU540_CACHE_H */
> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
> index 89a65eb3fb..1d6c0c9bba 100644
> --- a/board/sifive/fu540/fu540.c
> +++ b/board/sifive/fu540/fu540.c
> @@ -13,6 +13,8 @@
> #include
> #include
>
> +#include "cache.h"
> +
> /*
> * This define is a value used for error/unknown serial.
> * If we really care about distinguishing errors and 0 is
> @@ -111,8 +113,8 @@ int misc_init_r(void)
>
> int board_init(void)
> {
> - /* For now nothing to do here. */
> -
> + /* enable all cache ways */
> + cache_enable_ways(CACHE_CTRL_ADDR, 15);
> return 0;
> }
>
Regards,
Bin
Re: [PATCH v5 13/14] sifive: fix palmer's email address
On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel wrote: > > Fix Palmer's email address > > Signed-off-by: Pragnesh Patel > --- > board/sifive/fu540/MAINTAINERS | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Bin Meng
Re: [PATCH v5 14/14] doc: update FU540 RISC-V documentation
On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel wrote: > > Add descriptions about U-Boot SPL feature and how to build and run. > > Signed-off-by: Pragnesh Patel > --- > doc/board/sifive/fu540.rst | 409 ++--- > 1 file changed, 385 insertions(+), 24 deletions(-) > > diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst > index 3937222c6c..e5414f4eef 100644 > --- a/doc/board/sifive/fu540.rst > +++ b/doc/board/sifive/fu540.rst > @@ -42,8 +42,60 @@ Building > export ARCH=riscv > export CROSS_COMPILE= > > -3. make sifive_fu540_defconfig > -4. make > +User can use FSBL or u-boot-spl as a 1st stage bootloader. > + > +1) Use FSBL as a 1st stage bootloader The 1st stage. Please fix this globally in this file. > + > +.. code-block:: console > + > + git clone https://github.com/sifive/freedom-u540-c000-bootloader.git > + cd freedom-u540-c000-bootloader > + make > + > + cd > + make sifive_fu540_defconfig > + make > + > + git clone https://github.com/riscv/opensbi.git > + cd opensbi > + make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH= It should be u-boot-dtb.bin > + > +This will generate a > fw_payload.bin(build/platform/sifive/fu540/firmware/fw_payload.bin) nits: needs one space after fw_payload.bin > + > +u-boot.bin is used as a payload of the OpenSBI FW_PAYLOAD firmware. u-boot-dtb.bin > + > +More detailed description of steps required to build FW_PAYLOAD firmware > +is beyond the scope of this document. Please refer OpenSBI documenation. > +(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git) > + > +2) Use u-boot-spl as a 1st stage bootloader > + > +Before building U-Boot SPL, OpenSBI must be build first. OpenSBI can be must be built > +cloned and build for FU540 as below: built > + > +.. code-block:: console > + > + git clone https://github.com/riscv/opensbi.git > + cd opensbi > + make PLATFORM=sifive/fu540 > + > +Copy OpenSBI FW_DYNAMIC image > (build/platform/sifive/fu540/firmware/fw_dynamic.bin) > +into U-Boot root directory > + > +.. code-block:: console > + > + cp build/platform/sifive/fu540/firmware/fw_dynamic.bin > + > +Now build the u-boot-spl and u-boot proper nits: U-Boot proper > + > +.. code-block:: console > + > + cd > + make sifive_fu540_defconfig > + make > + > +This will generate spl/u-boot-spl.bin and FIT image(u-boot.itb) need one space after image > + > > Flashing > > @@ -53,28 +105,55 @@ The current U-Boot port is supported in S-mode only and > loaded from DRAM. > A prior stage M-mode firmware/bootloader (e.g OpenSBI) is required to > boot the u-boot.bin in S-mode and provide M-mode runtime services. > > -Currently, the u-boot.bin is used as a payload of the OpenSBI FW_PAYLOAD > -firmware. We need to compile OpenSBI with below command: > +1) Use FSBL as a 1st stage bootloader > + > +ZSBL loads the FSBL(fsbl.bin) from a partition with GUID type need one space after FSBL > +5B193300-FC78-40CD-8002-E86C45580B47 > + > +FSBL loads the fw_payload.bin from a partition with GUID type > +2E54B353-1271-4842-806F-E436D6AF6985 > + > +Once the prior stage firmware/bootloader binary is generated, it should be > +copied to the first partition of the sdcard. > > .. code-block:: none > > -make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH= > + sudo dd if=fsbl.bin of=/dev/disk2s4 bs=1024 > + sudo dd if=fw_payload.bin of=/dev/disk2s1 bs=1024 > > -More detailed description of steps required to build FW_PAYLOAD firmware > -is beyond the scope of this document. Please refer OpenSBI documenation. > -(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git) > +Assuming that /dev/disk2s4 partition is of GUID type > +5B193300-FC78-40CD-8002-E86C45580B47 and /dev/disk2s1 partition > +is of GUID type 2E54B353-1271-4842-806F-E436D6AF6985 > + > +2) Use u-boot-spl as a 1st stage bootloader > + > +ZSBL loads the U-boot SPL(u-boot-spl.bin) from a partition with GUID type U-Boot, and need one space after SPL > +5B193300-FC78-40CD-8002-E86C45580B47 > + > +U-boot SPL expects a u-boot FIT image(u-boot.itb) from 1st > partition(/dev/sdc1) U-Boot, and need one space after image > +of SD card irrespective of GUID > + > +FIT image(u-boot.itb) is a combination of fw_dynamic.bin, u-boot-nodtb.bin > and need one space after image > +device tree blob(hifive-unleashed-a00.dtb) need one space after blob > > Once the prior stage firmware/bootloader binary is generated, it should be > copied to the first partition of the sdcard. > > .. code-block:: none > > -sudo dd if= of=/dev/disk2s1 bs=1024 > +sudo dd if=spl/u-boot-spl.bin of=/dev/disk2s4 bs=1024 > +sudo dd if=u-boot.itb of=/dev/disk2s1 bs=1024 > + > +Assuming that /dev/disk2s4 partition is of GUID type > +5B193300-FC78-40CD-8002-E86C45580B47 and /dev/disk2s1 is of > +any GUID type raw partition. > > Booting > --- > Once you plugin the sdcard and powe
Antwort: [PATCH v2 30/39] acpi: Add functions to generate ACPI code
Hi Simon, -"Simon Glass" schrieb: - > > Sometimes we need to generate ACPI code on the fly based on things only > known at run time. Add a new 'acpigen' library to handle this. This code > comes from coreboot and has been modified to support the acpi_ctx struct. > > Also add acpi_device.c to the build, since these files are co-dependent. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > include/acpigen.h | 482 + > include/dm/acpi.h |7 + > include/irq.h |2 + > lib/acpi/Makefile |2 + > lib/acpi/acpigen.c | 1683 > 5 files changed, 2176 insertions(+) > create mode 100644 include/acpigen.h > create mode 100644 lib/acpi/acpigen.c What coreboot version is this based on? I have compared it to the current master in coreboot and there are some differences (ignoring the changes for acpi_ctx support). regards, Wolfgang
Re: [PATCH v5 12/14] riscv: sifive: fu540: enable all cache ways from u-boot proper
On Fri, Mar 13, 2020 at 2:31 PM Bin Meng wrote:
>
> On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
> wrote:
> >
> > Enable all cache ways from u-boot proper.
>
> U-Boot
>
> >
> > Signed-off-by: Pragnesh Patel
> > ---
> > board/sifive/fu540/Makefile | 1 +
> > board/sifive/fu540/cache.c | 20
> > board/sifive/fu540/cache.h | 13 +
> > board/sifive/fu540/fu540.c | 6 --
> > 4 files changed, 38 insertions(+), 2 deletions(-)
> > create mode 100644 board/sifive/fu540/cache.c
> > create mode 100644 board/sifive/fu540/cache.h
> >
> > diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
> > index b05e2f5807..3b867bbd89 100644
> > --- a/board/sifive/fu540/Makefile
> > +++ b/board/sifive/fu540/Makefile
> > @@ -3,6 +3,7 @@
> > # Copyright (c) 2019 Western Digital Corporation or its affiliates.
> >
> > obj-y += fu540.o
> > +obj-y += cache.o
> >
> > ifdef CONFIG_SPL_BUILD
> > obj-y += spl.o
> > diff --git a/board/sifive/fu540/cache.c b/board/sifive/fu540/cache.c
> > new file mode 100644
> > index 00..a0bcd2ba48
> > --- /dev/null
> > +++ b/board/sifive/fu540/cache.c
>
> This should be put into arch/riscv/cpu/fu540/cache.c
>
> > @@ -0,0 +1,20 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2019 SiFive, Inc
> > + */
> > +#include
> > +
> > +/* Register offsets */
> > +#define CACHE_ENABLE 0x008
> > +
> > +/* Enable ways; allow cache to use these ways */
> > +void cache_enable_ways(u64 base_addr, u8 value)
> > +{
> > + volatile u32 *enable = (volatile u32 *)(base_addr +
> > + CACHE_ENABLE);
> > + /* memory barrier */
> > + mb();
> > + (*enable) = value;
> > + /* memory barrier */
> > + mb();
> > +}
> > diff --git a/board/sifive/fu540/cache.h b/board/sifive/fu540/cache.h
> > new file mode 100644
> > index 00..425124a23b
> > --- /dev/null
> > +++ b/board/sifive/fu540/cache.h
>
> arch/riscv/include/asm/arch-fu540/cache.h
Let's not entire FU540 directory under arch/riscv/cpu directory
just to have cache functions. The arch/riscv/cpu/generic is perfectly
suitable for FU540.
If we re-use arch/riscv/cpu/generic as-much as possible then
arch/riscv will be easy to maintain in future.
We can add arch/riscv/cpu/generic/cache.c which will do
things FU540 specific based on "#ifdef" or "DT compatible string".
>
> > @@ -0,0 +1,13 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (c) 2019 SiFive, Inc
> > + */
> > +
> > +#ifndef FU540_CACHE_H
> > +#define FU540_CACHE_H
> > +
> > +#define CACHE_CTRL_ADDR _AC(0x201, UL)
> > +
> > +void cache_enable_ways(u64 base_addr, u8 value);
> > +
> > +#endif /* FU540_CACHE_H */
> > diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
> > index 89a65eb3fb..1d6c0c9bba 100644
> > --- a/board/sifive/fu540/fu540.c
> > +++ b/board/sifive/fu540/fu540.c
> > @@ -13,6 +13,8 @@
> > #include
> > #include
> >
> > +#include "cache.h"
> > +
> > /*
> > * This define is a value used for error/unknown serial.
> > * If we really care about distinguishing errors and 0 is
> > @@ -111,8 +113,8 @@ int misc_init_r(void)
> >
> > int board_init(void)
> > {
> > - /* For now nothing to do here. */
> > -
> > + /* enable all cache ways */
> > + cache_enable_ways(CACHE_CTRL_ADDR, 15);
> > return 0;
> > }
> >
>
> Regards,
> Bin
Regards,
Anup
Re: [PATCH v1] colibri_imx6: set gpr1 ENET_CLK_SEL
On Thu, Mar 12, 2020 at 11:37 PM Igor Opaniuk wrote:
>
> From: Igor Opaniuk
>
> This fixes the issue when PHY auto negotiation never completes.
>
> Fixes: 431cd76dd8("colibri_imx6: migrate to DM_ETH")
> Signed-off-by: Igor Opaniuk
Reviewed-by: Oleksandr Suvorov
> ---
>
> board/toradex/colibri_imx6/colibri_imx6.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/board/toradex/colibri_imx6/colibri_imx6.c
> b/board/toradex/colibri_imx6/colibri_imx6.c
> index f04b749311..d11401ecab 100644
> --- a/board/toradex/colibri_imx6/colibri_imx6.c
> +++ b/board/toradex/colibri_imx6/colibri_imx6.c
> @@ -354,12 +354,15 @@ int board_phy_config(struct phy_device *phydev)
> int setup_fec(void)
> {
> int ret;
> + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
>
> /* provide the PHY clock from the i.MX 6 */
> ret = enable_fec_anatop_clock(0, ENET_50MHZ);
> if (ret)
> return ret;
>
> + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
> +
> return 0;
> }
>
> --
> 2.17.1
>
--
Best regards
Oleksandr Suvorov
Toradex AG
Ebenaustrasse 10 | 6048 Horw | Switzerland | T: +41 41 500 48 00
Re: [PATCH v5 12/14] riscv: sifive: fu540: enable all cache ways from u-boot proper
Hi Anup,
On Fri, Mar 13, 2020 at 6:02 PM Anup Patel wrote:
>
> On Fri, Mar 13, 2020 at 2:31 PM Bin Meng wrote:
> >
> > On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
> > wrote:
> > >
> > > Enable all cache ways from u-boot proper.
> >
> > U-Boot
> >
> > >
> > > Signed-off-by: Pragnesh Patel
> > > ---
> > > board/sifive/fu540/Makefile | 1 +
> > > board/sifive/fu540/cache.c | 20
> > > board/sifive/fu540/cache.h | 13 +
> > > board/sifive/fu540/fu540.c | 6 --
> > > 4 files changed, 38 insertions(+), 2 deletions(-)
> > > create mode 100644 board/sifive/fu540/cache.c
> > > create mode 100644 board/sifive/fu540/cache.h
> > >
> > > diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
> > > index b05e2f5807..3b867bbd89 100644
> > > --- a/board/sifive/fu540/Makefile
> > > +++ b/board/sifive/fu540/Makefile
> > > @@ -3,6 +3,7 @@
> > > # Copyright (c) 2019 Western Digital Corporation or its affiliates.
> > >
> > > obj-y += fu540.o
> > > +obj-y += cache.o
> > >
> > > ifdef CONFIG_SPL_BUILD
> > > obj-y += spl.o
> > > diff --git a/board/sifive/fu540/cache.c b/board/sifive/fu540/cache.c
> > > new file mode 100644
> > > index 00..a0bcd2ba48
> > > --- /dev/null
> > > +++ b/board/sifive/fu540/cache.c
> >
> > This should be put into arch/riscv/cpu/fu540/cache.c
> >
> > > @@ -0,0 +1,20 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright (c) 2019 SiFive, Inc
> > > + */
> > > +#include
> > > +
> > > +/* Register offsets */
> > > +#define CACHE_ENABLE 0x008
> > > +
> > > +/* Enable ways; allow cache to use these ways */
> > > +void cache_enable_ways(u64 base_addr, u8 value)
> > > +{
> > > + volatile u32 *enable = (volatile u32 *)(base_addr +
> > > + CACHE_ENABLE);
> > > + /* memory barrier */
> > > + mb();
> > > + (*enable) = value;
> > > + /* memory barrier */
> > > + mb();
> > > +}
> > > diff --git a/board/sifive/fu540/cache.h b/board/sifive/fu540/cache.h
> > > new file mode 100644
> > > index 00..425124a23b
> > > --- /dev/null
> > > +++ b/board/sifive/fu540/cache.h
> >
> > arch/riscv/include/asm/arch-fu540/cache.h
>
> Let's not entire FU540 directory under arch/riscv/cpu directory
> just to have cache functions. The arch/riscv/cpu/generic is perfectly
> suitable for FU540.
I doubt arch/riscv/cpu/generic can be generic if we consider U-Boot
SPL phase. It can be generic for S-mode U-Boot though.
>
> If we re-use arch/riscv/cpu/generic as-much as possible then
> arch/riscv will be easy to maintain in future.
>
> We can add arch/riscv/cpu/generic/cache.c which will do
> things FU540 specific based on "#ifdef" or "DT compatible string".
>
Regards,
Bin
Re: [PATCH v5 12/14] riscv: sifive: fu540: enable all cache ways from u-boot proper
On Fri, Mar 13, 2020 at 3:52 PM Bin Meng wrote:
>
> Hi Anup,
>
> On Fri, Mar 13, 2020 at 6:02 PM Anup Patel wrote:
> >
> > On Fri, Mar 13, 2020 at 2:31 PM Bin Meng wrote:
> > >
> > > On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
> > > wrote:
> > > >
> > > > Enable all cache ways from u-boot proper.
> > >
> > > U-Boot
> > >
> > > >
> > > > Signed-off-by: Pragnesh Patel
> > > > ---
> > > > board/sifive/fu540/Makefile | 1 +
> > > > board/sifive/fu540/cache.c | 20
> > > > board/sifive/fu540/cache.h | 13 +
> > > > board/sifive/fu540/fu540.c | 6 --
> > > > 4 files changed, 38 insertions(+), 2 deletions(-)
> > > > create mode 100644 board/sifive/fu540/cache.c
> > > > create mode 100644 board/sifive/fu540/cache.h
> > > >
> > > > diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
> > > > index b05e2f5807..3b867bbd89 100644
> > > > --- a/board/sifive/fu540/Makefile
> > > > +++ b/board/sifive/fu540/Makefile
> > > > @@ -3,6 +3,7 @@
> > > > # Copyright (c) 2019 Western Digital Corporation or its affiliates.
> > > >
> > > > obj-y += fu540.o
> > > > +obj-y += cache.o
> > > >
> > > > ifdef CONFIG_SPL_BUILD
> > > > obj-y += spl.o
> > > > diff --git a/board/sifive/fu540/cache.c b/board/sifive/fu540/cache.c
> > > > new file mode 100644
> > > > index 00..a0bcd2ba48
> > > > --- /dev/null
> > > > +++ b/board/sifive/fu540/cache.c
> > >
> > > This should be put into arch/riscv/cpu/fu540/cache.c
> > >
> > > > @@ -0,0 +1,20 @@
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > +/*
> > > > + * Copyright (c) 2019 SiFive, Inc
> > > > + */
> > > > +#include
> > > > +
> > > > +/* Register offsets */
> > > > +#define CACHE_ENABLE 0x008
> > > > +
> > > > +/* Enable ways; allow cache to use these ways */
> > > > +void cache_enable_ways(u64 base_addr, u8 value)
> > > > +{
> > > > + volatile u32 *enable = (volatile u32 *)(base_addr +
> > > > + CACHE_ENABLE);
> > > > + /* memory barrier */
> > > > + mb();
> > > > + (*enable) = value;
> > > > + /* memory barrier */
> > > > + mb();
> > > > +}
> > > > diff --git a/board/sifive/fu540/cache.h b/board/sifive/fu540/cache.h
> > > > new file mode 100644
> > > > index 00..425124a23b
> > > > --- /dev/null
> > > > +++ b/board/sifive/fu540/cache.h
> > >
> > > arch/riscv/include/asm/arch-fu540/cache.h
> >
> > Let's not entire FU540 directory under arch/riscv/cpu directory
> > just to have cache functions. The arch/riscv/cpu/generic is perfectly
> > suitable for FU540.
>
> I doubt arch/riscv/cpu/generic can be generic if we consider U-Boot
> SPL phase. It can be generic for S-mode U-Boot though.
Its really very easy to do. We are already doing this in Xvisor.
As an example, of DT based operations in a generic board support refer:
https://github.com/avpatel/xvisor-next/blob/master/arch/arm/board/generic/brd_main.c
https://github.com/avpatel/xvisor-next/blob/master/arch/arm/board/generic/foundation-v8.c
Using the above approach, we are able to boot same Xvisor ARM/ARM64
binary on multiple boards.
>
> >
> > If we re-use arch/riscv/cpu/generic as-much as possible then
> > arch/riscv will be easy to maintain in future.
> >
> > We can add arch/riscv/cpu/generic/cache.c which will do
> > things FU540 specific based on "#ifdef" or "DT compatible string".
> >
>
> Regards,
> Bin
Regards,
Anup
Re: [PATCH v5 12/14] riscv: sifive: fu540: enable all cache ways from u-boot proper
On Fri, Mar 13, 2020 at 3:52 PM Bin Meng wrote:
>
> Hi Anup,
>
> On Fri, Mar 13, 2020 at 6:02 PM Anup Patel wrote:
> >
> > On Fri, Mar 13, 2020 at 2:31 PM Bin Meng wrote:
> > >
> > > On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
> > > wrote:
> > > >
> > > > Enable all cache ways from u-boot proper.
> > >
> > > U-Boot
> > >
> > > >
> > > > Signed-off-by: Pragnesh Patel
> > > > ---
> > > > board/sifive/fu540/Makefile | 1 +
> > > > board/sifive/fu540/cache.c | 20
> > > > board/sifive/fu540/cache.h | 13 +
> > > > board/sifive/fu540/fu540.c | 6 --
> > > > 4 files changed, 38 insertions(+), 2 deletions(-)
> > > > create mode 100644 board/sifive/fu540/cache.c
> > > > create mode 100644 board/sifive/fu540/cache.h
> > > >
> > > > diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
> > > > index b05e2f5807..3b867bbd89 100644
> > > > --- a/board/sifive/fu540/Makefile
> > > > +++ b/board/sifive/fu540/Makefile
> > > > @@ -3,6 +3,7 @@
> > > > # Copyright (c) 2019 Western Digital Corporation or its affiliates.
> > > >
> > > > obj-y += fu540.o
> > > > +obj-y += cache.o
> > > >
> > > > ifdef CONFIG_SPL_BUILD
> > > > obj-y += spl.o
> > > > diff --git a/board/sifive/fu540/cache.c b/board/sifive/fu540/cache.c
> > > > new file mode 100644
> > > > index 00..a0bcd2ba48
> > > > --- /dev/null
> > > > +++ b/board/sifive/fu540/cache.c
> > >
> > > This should be put into arch/riscv/cpu/fu540/cache.c
> > >
> > > > @@ -0,0 +1,20 @@
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > +/*
> > > > + * Copyright (c) 2019 SiFive, Inc
> > > > + */
> > > > +#include
> > > > +
> > > > +/* Register offsets */
> > > > +#define CACHE_ENABLE 0x008
> > > > +
> > > > +/* Enable ways; allow cache to use these ways */
> > > > +void cache_enable_ways(u64 base_addr, u8 value)
> > > > +{
> > > > + volatile u32 *enable = (volatile u32 *)(base_addr +
> > > > + CACHE_ENABLE);
> > > > + /* memory barrier */
> > > > + mb();
> > > > + (*enable) = value;
> > > > + /* memory barrier */
> > > > + mb();
> > > > +}
> > > > diff --git a/board/sifive/fu540/cache.h b/board/sifive/fu540/cache.h
> > > > new file mode 100644
> > > > index 00..425124a23b
> > > > --- /dev/null
> > > > +++ b/board/sifive/fu540/cache.h
> > >
> > > arch/riscv/include/asm/arch-fu540/cache.h
> >
> > Let's not entire FU540 directory under arch/riscv/cpu directory
> > just to have cache functions. The arch/riscv/cpu/generic is perfectly
> > suitable for FU540.
>
> I doubt arch/riscv/cpu/generic can be generic if we consider U-Boot
> SPL phase. It can be generic for S-mode U-Boot though.
We can also have a light weight U-Boot driver framework for cache
operations. This framework will figure-out cache operation based on
SOC compatible string in root DT node or some other way.
This will be useful in long-term when we have complex cache
hierarchy on RISC-V SOCs.
>
> >
> > If we re-use arch/riscv/cpu/generic as-much as possible then
> > arch/riscv will be easy to maintain in future.
> >
> > We can add arch/riscv/cpu/generic/cache.c which will do
> > things FU540 specific based on "#ifdef" or "DT compatible string".
> >
>
> Regards,
> Bin
Regards,
Anup
[PATCH] pci-host-ecam-generic: access config space independent of system-wide bus id
From: Vladimir Oltean
The pci-host-ecam-generic code assumes that the ECAM is the first PCI
bus in the system to be probed. Therefore, the system-wide bus number
allocated by U-Boot in sequence for it is going to be zero, which
corresponds to the memory-mapped config spaces found within it.
Reuse the logic from other PCI bus drivers, and assume that U-Boot will
allocate bus numbers in sequence for all buses within the current ECAM.
So the base number of the bus needs to be subtracted when indexing the
correct config space.
Fixes: 3675cb044e68 ("PCI: Add driver for a 'pci-host-ecam-generic' host
controller")
Signed-off-by: Vladimir Oltean
---
drivers/pci/pcie_ecam_generic.c | 36 +
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c
index 00644edd2646..190919d26a67 100644
--- a/drivers/pci/pcie_ecam_generic.c
+++ b/drivers/pci/pcie_ecam_generic.c
@@ -19,6 +19,8 @@
*/
struct generic_ecam_pcie {
void *cfg_base;
+ pci_size_t size;
+ int first_busno;
};
/**
@@ -42,7 +44,7 @@ static int pci_generic_ecam_conf_address(struct udevice *bus,
pci_dev_t bdf,
void *addr;
addr = pcie->cfg_base;
- addr += PCI_BUS(bdf) << 20;
+ addr += (PCI_BUS(bdf) - pcie->first_busno) << 20;
addr += PCI_DEV(bdf) << 15;
addr += PCI_FUNC(bdf) << 12;
addr += offset;
@@ -51,6 +53,15 @@ static int pci_generic_ecam_conf_address(struct udevice
*bus, pci_dev_t bdf,
return 0;
}
+static bool pci_generic_ecam_addr_valid(struct udevice *bus, pci_dev_t bdf)
+{
+ struct generic_ecam_pcie *pcie = dev_get_priv(bus);
+ int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16);
+
+ return (PCI_BUS(bdf) >= pcie->first_busno &&
+ PCI_BUS(bdf) < pcie->first_busno + num_buses);
+}
+
/**
* pci_generic_ecam_read_config() - Read from configuration space
* @bus: Pointer to the PCI bus
@@ -67,6 +78,11 @@ static int pci_generic_ecam_read_config(struct udevice *bus,
pci_dev_t bdf,
uint offset, ulong *valuep,
enum pci_size_t size)
{
+ if (!pci_generic_ecam_addr_valid(bus, bdf)) {
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
return pci_generic_mmap_read_config(bus, pci_generic_ecam_conf_address,
bdf, offset, valuep, size);
}
@@ -87,6 +103,9 @@ static int pci_generic_ecam_write_config(struct udevice
*bus, pci_dev_t bdf,
uint offset, ulong value,
enum pci_size_t size)
{
+ if (!pci_generic_ecam_addr_valid(bus, bdf))
+ return 0;
+
return pci_generic_mmap_write_config(bus, pci_generic_ecam_conf_address,
bdf, offset, value, size);
}
@@ -115,9 +134,17 @@ static int pci_generic_ecam_ofdata_to_platdata(struct
udevice *dev)
return err;
}
- pcie->cfg_base = map_physmem(reg_res.start,
-fdt_resource_size(®_res),
-MAP_NOCACHE);
+ pcie->size = fdt_resource_size(®_res);
+ pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE);
+
+ return 0;
+}
+
+static int pci_generic_ecam_probe(struct udevice *dev)
+{
+ struct generic_ecam_pcie *pcie = dev_get_priv(dev);
+
+ pcie->first_busno = dev->seq;
return 0;
}
@@ -137,6 +164,7 @@ U_BOOT_DRIVER(pci_generic_ecam) = {
.id = UCLASS_PCI,
.of_match = pci_generic_ecam_ids,
.ops= &pci_generic_ecam_ops,
+ .probe = pci_generic_ecam_probe,
.ofdata_to_platdata = pci_generic_ecam_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct generic_ecam_pcie),
};
--
2.17.1
Antwort: [PATCH v2 31/39] gpio: Add a method to convert a GPIO to ACPI
Hi Simon, -"Simon Glass" schrieb: - > > When generating ACPI tables we need to convert GPIOs in U-Boot to the ACPI > structures required by ACPI. This is a SoC-specific conversion and cannot > be handled by generic code, so add a new GPIO method to do the conversion. > > Signed-off-by: Simon Glass > --- > > Changes in v2: None > > drivers/gpio/gpio-uclass.c | 21 + > include/acpi_device.h | 12 > include/asm-generic/gpio.h | 27 +++ > lib/acpi/acpi_device.c | 16 > 4 files changed, 76 insertions(+) Reviewed-by: Wolfgang Wallner
Re: [PATCH] pci-host-ecam-generic: access config space independent of system-wide bus id
On 3/13/2020 12:04 PM, Vladimir Oltean wrote:
From: Vladimir Oltean
The pci-host-ecam-generic code assumes that the ECAM is the first PCI
bus in the system to be probed. Therefore, the system-wide bus number
allocated by U-Boot in sequence for it is going to be zero, which
corresponds to the memory-mapped config spaces found within it.
Reuse the logic from other PCI bus drivers, and assume that U-Boot will
allocate bus numbers in sequence for all buses within the current ECAM.
So the base number of the bus needs to be subtracted when indexing the
correct config space.
Fixes: 3675cb044e68 ("PCI: Add driver for a 'pci-host-ecam-generic' host
controller")
Signed-off-by: Vladimir Oltean
---
drivers/pci/pcie_ecam_generic.c | 36 +
1 file changed, 32 insertions(+), 4 deletions(-)
Reviewed-by: Alex Marginean
[PATCH v2] pci-host-ecam-generic: access config space independent of system-wide bus id
From: Vladimir Oltean
The pci-host-ecam-generic code assumes that the ECAM is the first PCI
bus in the system to be probed. Therefore, the system-wide bus number
allocated by U-Boot in sequence for it is going to be zero, which
corresponds to the memory-mapped config spaces found within it.
Reuse the logic from other PCI bus drivers, and assume that U-Boot will
allocate bus numbers in sequence for all buses within the current ECAM.
So the base number of the bus needs to be subtracted when indexing the
correct config space.
Fixes: 3675cb044e68 ("PCI: Add driver for a 'pci-host-ecam-generic' host
controller")
Signed-off-by: Vladimir Oltean
Reviewed-by: Alex Marginean
---
Changes in v2:
Rebased on top of current u-boot master. There was a trivial context
difference in pci_generic_ecam_read_config.
drivers/pci/pcie_ecam_generic.c | 36 +
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c
index c875f3a5b7d2..813f9687b6b3 100644
--- a/drivers/pci/pcie_ecam_generic.c
+++ b/drivers/pci/pcie_ecam_generic.c
@@ -19,6 +19,8 @@
*/
struct generic_ecam_pcie {
void *cfg_base;
+ pci_size_t size;
+ int first_busno;
};
/**
@@ -43,7 +45,7 @@ static int pci_generic_ecam_conf_address(const struct udevice
*bus,
void *addr;
addr = pcie->cfg_base;
- addr += PCI_BUS(bdf) << 20;
+ addr += (PCI_BUS(bdf) - pcie->first_busno) << 20;
addr += PCI_DEV(bdf) << 15;
addr += PCI_FUNC(bdf) << 12;
addr += offset;
@@ -52,6 +54,15 @@ static int pci_generic_ecam_conf_address(const struct
udevice *bus,
return 0;
}
+static bool pci_generic_ecam_addr_valid(struct udevice *bus, pci_dev_t bdf)
+{
+ struct generic_ecam_pcie *pcie = dev_get_priv(bus);
+ int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16);
+
+ return (PCI_BUS(bdf) >= pcie->first_busno &&
+ PCI_BUS(bdf) < pcie->first_busno + num_buses);
+}
+
/**
* pci_generic_ecam_read_config() - Read from configuration space
* @bus: Pointer to the PCI bus
@@ -68,6 +79,11 @@ static int pci_generic_ecam_read_config(const struct udevice
*bus,
pci_dev_t bdf, uint offset,
ulong *valuep, enum pci_size_t size)
{
+ if (!pci_generic_ecam_addr_valid(bus, bdf)) {
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
return pci_generic_mmap_read_config(bus, pci_generic_ecam_conf_address,
bdf, offset, valuep, size);
}
@@ -88,6 +104,9 @@ static int pci_generic_ecam_write_config(struct udevice
*bus, pci_dev_t bdf,
uint offset, ulong value,
enum pci_size_t size)
{
+ if (!pci_generic_ecam_addr_valid(bus, bdf))
+ return 0;
+
return pci_generic_mmap_write_config(bus, pci_generic_ecam_conf_address,
bdf, offset, value, size);
}
@@ -116,9 +135,17 @@ static int pci_generic_ecam_ofdata_to_platdata(struct
udevice *dev)
return err;
}
- pcie->cfg_base = map_physmem(reg_res.start,
-fdt_resource_size(®_res),
-MAP_NOCACHE);
+ pcie->size = fdt_resource_size(®_res);
+ pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE);
+
+ return 0;
+}
+
+static int pci_generic_ecam_probe(struct udevice *dev)
+{
+ struct generic_ecam_pcie *pcie = dev_get_priv(dev);
+
+ pcie->first_busno = dev->seq;
return 0;
}
@@ -138,6 +165,7 @@ U_BOOT_DRIVER(pci_generic_ecam) = {
.id = UCLASS_PCI,
.of_match = pci_generic_ecam_ids,
.ops= &pci_generic_ecam_ops,
+ .probe = pci_generic_ecam_probe,
.ofdata_to_platdata = pci_generic_ecam_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct generic_ecam_pcie),
};
--
2.17.1
Re: [PATCH v5 06/14] sifive: fu540: add ddr driver
Hi Pragnesh,
On 3/11/20 8:03 AM, Pragnesh Patel wrote:
Add driver for fu540 to support ddr initialization in SPL.
This driver is based on FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
---
drivers/ram/Kconfig | 7 +
drivers/ram/Makefile | 2 +
drivers/ram/sifive/Kconfig | 8 +
drivers/ram/sifive/Makefile | 6 +
drivers/ram/sifive/sdram_fu540.c | 295 +++
drivers/ram/sifive/sdram_fu540.h | 94 ++
6 files changed, 412 insertions(+)
create mode 100644 drivers/ram/sifive/Kconfig
create mode 100644 drivers/ram/sifive/Makefile
create mode 100644 drivers/ram/sifive/sdram_fu540.c
create mode 100644 drivers/ram/sifive/sdram_fu540.h
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 56fea7c94c..c60c63204c 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -73,5 +73,12 @@ config IMXRT_SDRAM
to support external memories like sdram, psram & nand.
This driver is for the sdram memory interface with the SEMC.
+config SIFIVE_DDR
+ bool "Enable SiFive DDR support"
+ depends on RAM
+ help
+ Enable support for the internal DDR Memory Controller of SiFive SoCs.
+
source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
+source "drivers/ram/sifive/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 5c897410c6..12bf61510b 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -17,3 +17,5 @@ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
+
+obj-$(CONFIG_SIFIVE_DDR) += sifive/
diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig
new file mode 100644
index 00..b754700db8
--- /dev/null
+++ b/drivers/ram/sifive/Kconfig
@@ -0,0 +1,8 @@
+config SIFIVE_FU540_DDR
+ bool "SiFive FU540 DDR driver"
+ depends on DM && OF_CONTROL
+ select RAM
+ select SPL_RAM if SPL
+ select SIFIVE_DDR
+ help
+ This enables DDR support for the platforms based on SiFive FU540 SoC.
diff --git a/drivers/ram/sifive/Makefile b/drivers/ram/sifive/Makefile
new file mode 100644
index 00..0187805199
--- /dev/null
+++ b/drivers/ram/sifive/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2020 SiFive, Inc
+#
+
+obj-$(CONFIG_SIFIVE_FU540_DDR) += sdram_fu540.o
diff --git a/drivers/ram/sifive/sdram_fu540.c b/drivers/ram/sifive/sdram_fu540.c
new file mode 100644
index 00..18926dbe15
--- /dev/null
+++ b/drivers/ram/sifive/sdram_fu540.c
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * (C) Copyright 2020 SiFive, Inc.
+ *
+ * Authors:
+ * Pragnesh Patel
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "sdram_fu540.h"
+
+/* n: Unit bytes */
+void sdram_copy_to_reg(volatile u32 *dest, volatile u32 *src, u32 n)
+{
+ int i;
+
+ for (i = 0; i < n / sizeof(u32); i++) {
+ writel(*src, dest);
+ src++;
+ dest++;
+ }
+}
+
+static void ddr_setuprangeprotection(volatile u32 *ctl, u64 end_addr)
+{
+ writel(0x0, DENALI_CTL_209 + ctl);
+ u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7F) - 1;
+
+ writel(end_addr_16kblocks, DENALI_CTL_210 + ctl);
+ writel(0x0, DENALI_CTL_212 + ctl);
+ writel(0x0, DENALI_CTL_214 + ctl);
+ writel(0x0, DENALI_CTL_216 + ctl);
+ setbits_le32(DENALI_CTL_224 + ctl,
+0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
+ writel(0x, DENALI_CTL_225 + ctl);
+ setbits_le32(DENALI_CTL_208 + ctl, 0x1 << AXI0_ADDRESS_RANGE_ENABLE);
+ setbits_le32(DENALI_CTL_208 + ctl,
+0x1 << PORT_ADDR_PROTECTION_EN_OFFSET);
+}
+
+static void ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl, u64
ddr_end)
+{
+ setbits_le32(DENALI_CTL_0 + ctl, 0x1);
+ while ((readl(DENALI_CTL_132 + ctl) & (1 << MC_INIT_COMPLETE_OFFSET))
+ == 0) {
+ }
+
+ // Disable the BusBlocker in front of the controller AXI slave ports
+ volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl;
+
+ filterreg[0] = 0x0f00UL | (ddr_end >> 2);
+}
+
+static u64 ddr_phy_fixup(volatile u32 *ddrphyreg)
+{
+ // return bitmask of failed lanes
+
+ u64 fails = 0;
+ u32 slicebase = 0;
+ u32 dq= 0;
+
+ // check errata condition
+ for (u32 slice = 0; slice < 8; slice++) {
+ u32 regbase = slicebase + 34;
+
+ for (u32 reg = 0; reg < 4; reg++) {
+ u32 updownreg = readl(regbase + reg + ddrphyreg);
+
+ for (u32 bit = 0; bit < 2; bit++) {
+ u32 phy_rx_cal_dqn_0_offset;
+
+ if (bit == 0) {
+
Re: [PATCH] mkimage: fit_image: Make fit header and data align to 512
On 13/03/2020 03.07, Heinrich Schuchardt wrote: > Am March 13, 2020 1:50:41 AM UTC schrieb Kever Yang > : >> The image is usually stored in block device like emmc, SD card, make >> the >> offset of image data aligned to block(512 byte) can avoid data copy >> during boot process. >> eg. SPL boot from FIT image with external data: >> - SPL read the first block of FIT image, and then parse the header; >> - SPL read image data separately; >> - The first image offset is the base_offset which is the header size; >> - The second image offset is just after the first image; >> - If the offset of imge does not aligned, SPL will do memcpy; >> The header size is a ramdon number, which is very possible not aligned, >> so >> add align for FIT header and image data for better performance. Why not let -B take an integer argument, so the same flag can be used the day someone needs stuff to be aligned on a 4096 byte boundary? Rasmus
Re: [PATCH] mkimage: fit_image: Make fit header and data align to 512
On Fri, Mar 13, 2020 at 02:09:32PM +0100, Rasmus Villemoes wrote: > On 13/03/2020 03.07, Heinrich Schuchardt wrote: > > Am March 13, 2020 1:50:41 AM UTC schrieb Kever Yang > > : > >> The image is usually stored in block device like emmc, SD card, make > >> the > >> offset of image data aligned to block(512 byte) can avoid data copy > >> during boot process. > >> eg. SPL boot from FIT image with external data: > >> - SPL read the first block of FIT image, and then parse the header; > >> - SPL read image data separately; > >> - The first image offset is the base_offset which is the header size; > >> - The second image offset is just after the first image; > >> - If the offset of imge does not aligned, SPL will do memcpy; > >> The header size is a ramdon number, which is very possible not aligned, > >> so > >> add align for FIT header and image data for better performance. > > Why not let -B take an integer argument, so the same flag can be used > the day someone needs stuff to be aligned on a 4096 byte boundary? Agreed, I'm not happy with the 512 byte assumption either. Thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v5 12/14] riscv: sifive: fu540: enable all cache ways from u-boot proper
Hi Anup,
On Fri, Mar 13, 2020 at 6:49 PM Anup Patel wrote:
>
> On Fri, Mar 13, 2020 at 3:52 PM Bin Meng wrote:
> >
> > Hi Anup,
> >
> > On Fri, Mar 13, 2020 at 6:02 PM Anup Patel wrote:
> > >
> > > On Fri, Mar 13, 2020 at 2:31 PM Bin Meng wrote:
> > > >
> > > > On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
> > > > wrote:
> > > > >
> > > > > Enable all cache ways from u-boot proper.
> > > >
> > > > U-Boot
> > > >
> > > > >
> > > > > Signed-off-by: Pragnesh Patel
> > > > > ---
> > > > > board/sifive/fu540/Makefile | 1 +
> > > > > board/sifive/fu540/cache.c | 20
> > > > > board/sifive/fu540/cache.h | 13 +
> > > > > board/sifive/fu540/fu540.c | 6 --
> > > > > 4 files changed, 38 insertions(+), 2 deletions(-)
> > > > > create mode 100644 board/sifive/fu540/cache.c
> > > > > create mode 100644 board/sifive/fu540/cache.h
> > > > >
> > > > > diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
> > > > > index b05e2f5807..3b867bbd89 100644
> > > > > --- a/board/sifive/fu540/Makefile
> > > > > +++ b/board/sifive/fu540/Makefile
> > > > > @@ -3,6 +3,7 @@
> > > > > # Copyright (c) 2019 Western Digital Corporation or its affiliates.
> > > > >
> > > > > obj-y += fu540.o
> > > > > +obj-y += cache.o
> > > > >
> > > > > ifdef CONFIG_SPL_BUILD
> > > > > obj-y += spl.o
> > > > > diff --git a/board/sifive/fu540/cache.c b/board/sifive/fu540/cache.c
> > > > > new file mode 100644
> > > > > index 00..a0bcd2ba48
> > > > > --- /dev/null
> > > > > +++ b/board/sifive/fu540/cache.c
> > > >
> > > > This should be put into arch/riscv/cpu/fu540/cache.c
> > > >
> > > > > @@ -0,0 +1,20 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > +/*
> > > > > + * Copyright (c) 2019 SiFive, Inc
> > > > > + */
> > > > > +#include
> > > > > +
> > > > > +/* Register offsets */
> > > > > +#define CACHE_ENABLE 0x008
> > > > > +
> > > > > +/* Enable ways; allow cache to use these ways */
> > > > > +void cache_enable_ways(u64 base_addr, u8 value)
> > > > > +{
> > > > > + volatile u32 *enable = (volatile u32 *)(base_addr +
> > > > > + CACHE_ENABLE);
> > > > > + /* memory barrier */
> > > > > + mb();
> > > > > + (*enable) = value;
> > > > > + /* memory barrier */
> > > > > + mb();
> > > > > +}
> > > > > diff --git a/board/sifive/fu540/cache.h b/board/sifive/fu540/cache.h
> > > > > new file mode 100644
> > > > > index 00..425124a23b
> > > > > --- /dev/null
> > > > > +++ b/board/sifive/fu540/cache.h
> > > >
> > > > arch/riscv/include/asm/arch-fu540/cache.h
> > >
> > > Let's not entire FU540 directory under arch/riscv/cpu directory
> > > just to have cache functions. The arch/riscv/cpu/generic is perfectly
> > > suitable for FU540.
> >
> > I doubt arch/riscv/cpu/generic can be generic if we consider U-Boot
> > SPL phase. It can be generic for S-mode U-Boot though.
>
> Its really very easy to do. We are already doing this in Xvisor.
>
> As an example, of DT based operations in a generic board support refer:
> https://github.com/avpatel/xvisor-next/blob/master/arch/arm/board/generic/brd_main.c
> https://github.com/avpatel/xvisor-next/blob/master/arch/arm/board/generic/foundation-v8.c
Yes, this can be easy to do if we have everything written based on DT.
But we cannot always assume DT is available in SPL. Some SoCs will not
allow SPL with DT support to run due to constraint resources.
Even for DT, due to SPL initialization codes can be very low-level and
specific to an SoC, not everything can be properly modeled by DT. Take
a look at the u-boot/arch/arm directory. Things are not that easy.
>
> Using the above approach, we are able to boot same Xvisor ARM/ARM64
> binary on multiple boards.
>
Yes, I know. The same as what is done in the Linux kernel. Take x86
for example, the same kernel image can boot on almost every x86
desktop/laptop/server we have today. But we have to understand that
this is built on top of BIOS which does all low-level processor /
chipset initialization and hide that very well for OS.
> >
> > >
> > > If we re-use arch/riscv/cpu/generic as-much as possible then
> > > arch/riscv will be easy to maintain in future.
> > >
> > > We can add arch/riscv/cpu/generic/cache.c which will do
> > > things FU540 specific based on "#ifdef" or "DT compatible string".
> > >
Regards,
Bin
Re: [PATCH v5 10/14] riscv: sifive: fu540: add SPL configuration
On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
wrote:
>
> Add a support for SPL which will boot from L2 LIM (0x0800_) and
> then boot U-boot FIT image including OpenSBI FW_DYNAMIC firmware
> and U-Boot proper images from 1st partition of MMC boot devices.
>
> SPL related code is leverage from FSBL
> (https://github.com/sifive/freedom-u540-c000-bootloader.git)
>
> Signed-off-by: Pragnesh Patel
> ---
> board/sifive/fu540/Kconfig| 8 +++
> board/sifive/fu540/Makefile | 4 ++
> board/sifive/fu540/fu540-memory-map.h | 23
> board/sifive/fu540/fu540.c| 24 +
> board/sifive/fu540/spl.c | 78 +++
> include/configs/sifive-fu540.h| 18 +++
> 6 files changed, 155 insertions(+)
> create mode 100644 board/sifive/fu540/fu540-memory-map.h
> create mode 100644 board/sifive/fu540/spl.c
>
> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
> index 900197bbb2..ebe3472f9a 100644
> --- a/board/sifive/fu540/Kconfig
> +++ b/board/sifive/fu540/Kconfig
> @@ -13,12 +13,20 @@ config SYS_CONFIG_NAME
> default "sifive-fu540"
>
> config SYS_TEXT_BASE
> + default 0x8020 if SPL
> default 0x8000 if !RISCV_SMODE
> default 0x8020 if RISCV_SMODE
>
> +config SPL_TEXT_BASE
> + default 0x0800
> +
> +config SPL_OPENSBI_LOAD_ADDR
> + default 0x8000
> +
> config BOARD_SPECIFIC_OPTIONS # dummy
> def_bool y
> select GENERIC_RISCV
> + select SUPPORT_SPL
> imply CMD_DHCP
> imply CMD_EXT2
> imply CMD_EXT4
> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
> index 6e1862c475..b05e2f5807 100644
> --- a/board/sifive/fu540/Makefile
> +++ b/board/sifive/fu540/Makefile
> @@ -3,3 +3,7 @@
> # Copyright (c) 2019 Western Digital Corporation or its affiliates.
>
> obj-y += fu540.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +endif
> diff --git a/board/sifive/fu540/fu540-memory-map.h
> b/board/sifive/fu540/fu540-memory-map.h
> new file mode 100644
> index 00..cba464652b
> --- /dev/null
> +++ b/board/sifive/fu540/fu540-memory-map.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + */
> +
> +#ifndef FU540_MEMORY_MAP
> +#define FU540_MEMORY_MAP
> +
> +#include
> +
> +/
> + * Platform definitions
> +
> */
> +
> +/* Memory map */
> +#define GPIO_CTRL_ADDR _AC(0x1006, UL)
> +
> +/* Helper functions */
> +#define _REG32(p, i)(*(volatile uint32_t *)((p) + (i)))
> +
> +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
> +
> +#endif /* FU540_MEMORY_MAP */
> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
> index 6c642b3082..89a65eb3fb 100644
> --- a/board/sifive/fu540/fu540.c
> +++ b/board/sifive/fu540/fu540.c
> @@ -11,6 +11,7 @@
> #include
> #include
> #include
> +#include
>
> /*
> * This define is a value used for error/unknown serial.
> @@ -114,3 +115,26 @@ int board_init(void)
>
> return 0;
> }
> +
> +#ifdef CONFIG_SPL
> +void board_boot_order(u32 *spl_boot_list)
> +{
> + u8 i;
> + u32 boot_devices[] = {
> +#ifdef CONFIG_SPL_MMC_SUPPORT
> + BOOT_DEVICE_MMC1,
> +#endif
> + };
> +
> + for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
> + spl_boot_list[i] = boot_devices[i];
> +}
> +#endif
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> + /* boot using first FIT config */
> + return 0;
> +}
> +#endif
> diff --git a/board/sifive/fu540/spl.c b/board/sifive/fu540/spl.c
> new file mode 100644
> index 00..522bc24753
> --- /dev/null
> +++ b/board/sifive/fu540/spl.c
> @@ -0,0 +1,78 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2019 SiFive, Inc
> + *
> + * Authors:
> + * Pragnesh Patel
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#include "fu540-memory-map.h"
> +
> +#define DDRCTLPLL_F 55
> +#define DDRCTLPLL_Q 2
> +
> +#define PHY_NRESET 0x1000
> +
> +long nsec_per_cyc = 300; /* 33.333MHz */
> +void nsleep(long nsec)
> +{
> + long step = nsec_per_cyc * 2;
> +
> + while (nsec > 0)
> + nsec -= step;
> +}
> +
> +void init_clk_and_ddr(void)
> +{
> + int ret;
> + struct udevice *dev;
> +
> + /* PRCI init */
> + ret = uclass_get_device(UCLASS_CLK, 0, &dev);
> + if (ret) {
> + debug("Clock init failed: %d\n", ret);
> + return;
> + }
> +
> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (ret) {
> + printf("DRAM init failed: %d\n", ret);
> + return;
> + }
> +
This should be split into two parts:
SoC specific parts should go to
Re: [PATCH v3 6/6] configs: ls1028a: enable the Ethernet switch driver in defconfig
On Tue, 3 Dec 2019 at 17:23, Alex Marginean wrote: > > The switch driver for LS1028A Ethernet switch is now compiled in for > both LS1028A boards. > > Signed-off-by: Alex Marginean > --- > configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 3 ++- > configs/ls1028aqds_tfa_defconfig | 3 ++- > configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 3 ++- > configs/ls1028ardb_tfa_defconfig | 3 ++- > 4 files changed, 8 insertions(+), 4 deletions(-) > > diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig > b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig > index 4a01cd6715..65e467817e 100644 > --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig > +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig > @@ -50,8 +50,9 @@ CONFIG_PHY_ATHEROS=y > CONFIG_PHY_VITESSE=y > CONFIG_DM_ETH=y > CONFIG_DM_MDIO=y > +CONFIG_DM_DSA=y > CONFIG_E1000=y > -CONFIG_FSL_ENETC=y You surely didn't want to disable FSL_ENETC here, no? > +CONFIG_MSCC_FELIX_SWITCH=y > CONFIG_PCI=y > CONFIG_DM_PCI=y > CONFIG_DM_PCI_COMPAT=y > diff --git a/configs/ls1028aqds_tfa_defconfig > b/configs/ls1028aqds_tfa_defconfig > index 1307f0d951..40d259d907 100644 > --- a/configs/ls1028aqds_tfa_defconfig > +++ b/configs/ls1028aqds_tfa_defconfig > @@ -56,8 +56,9 @@ CONFIG_PHY_ATHEROS=y > CONFIG_PHY_VITESSE=y > CONFIG_DM_ETH=y > CONFIG_DM_MDIO=y > +CONFIG_DM_DSA=y > CONFIG_E1000=y > -CONFIG_FSL_ENETC=y > +CONFIG_MSCC_FELIX_SWITCH=y > CONFIG_PCI=y > CONFIG_DM_PCI=y > CONFIG_DM_PCI_COMPAT=y > diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig > b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig > index d0a3310a4c..f54a6da31b 100644 > --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig > +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig > @@ -49,9 +49,10 @@ CONFIG_PHY_ATHEROS=y > CONFIG_PHY_VITESSE=y > CONFIG_DM_ETH=y > CONFIG_DM_MDIO=y > +CONFIG_DM_DSA=y > CONFIG_PHY_GIGE=y > CONFIG_E1000=y > -CONFIG_FSL_ENETC=y > +CONFIG_MSCC_FELIX_SWITCH=y > CONFIG_PCI=y > CONFIG_DM_PCI=y > CONFIG_DM_PCI_COMPAT=y > diff --git a/configs/ls1028ardb_tfa_defconfig > b/configs/ls1028ardb_tfa_defconfig > index 4ec7ed0920..e018e5a50e 100644 > --- a/configs/ls1028ardb_tfa_defconfig > +++ b/configs/ls1028ardb_tfa_defconfig > @@ -56,9 +56,10 @@ CONFIG_PHY_ATHEROS=y > CONFIG_PHY_VITESSE=y > CONFIG_DM_ETH=y > CONFIG_DM_MDIO=y > +CONFIG_DM_DSA=y > CONFIG_PHY_GIGE=y > CONFIG_E1000=y > -CONFIG_FSL_ENETC=y > +CONFIG_MSCC_FELIX_SWITCH=y > CONFIG_PCI=y > CONFIG_DM_PCI=y > CONFIG_DM_PCI_COMPAT=y > -- > 2.17.1 > Regards, -Vladimir
[PATCH v3] pci-host-ecam-generic: access config space independent of system-wide bus id
From: Vladimir Oltean
The pci-host-ecam-generic code assumes that the ECAM is the first PCI
bus in the system to be probed. Therefore, the system-wide bus number
allocated by U-Boot in sequence for it is going to be zero, which
corresponds to the memory-mapped config spaces found within it.
Reuse the logic from other PCI bus drivers, and assume that U-Boot will
allocate bus numbers in sequence for all buses within the current ECAM.
So the base number of the bus needs to be subtracted when indexing the
correct config space.
Fixes: 3675cb044e68 ("PCI: Add driver for a 'pci-host-ecam-generic' host
controller")
Signed-off-by: Vladimir Oltean
Reviewed-by: Alex Marginean
---
Changes in v3:
Made struct udevice *bus const in pci_generic_ecam_addr_valid.
Changes in v2:
Rebased on top of current u-boot master. There was a trivial context
difference in pci_generic_ecam_read_config.
drivers/pci/pcie_ecam_generic.c | 36 +
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c
index c875f3a5b7d2..811c5fa22e00 100644
--- a/drivers/pci/pcie_ecam_generic.c
+++ b/drivers/pci/pcie_ecam_generic.c
@@ -19,6 +19,8 @@
*/
struct generic_ecam_pcie {
void *cfg_base;
+ pci_size_t size;
+ int first_busno;
};
/**
@@ -43,7 +45,7 @@ static int pci_generic_ecam_conf_address(const struct udevice
*bus,
void *addr;
addr = pcie->cfg_base;
- addr += PCI_BUS(bdf) << 20;
+ addr += (PCI_BUS(bdf) - pcie->first_busno) << 20;
addr += PCI_DEV(bdf) << 15;
addr += PCI_FUNC(bdf) << 12;
addr += offset;
@@ -52,6 +54,15 @@ static int pci_generic_ecam_conf_address(const struct
udevice *bus,
return 0;
}
+static bool pci_generic_ecam_addr_valid(const struct udevice *bus, pci_dev_t
bdf)
+{
+ struct generic_ecam_pcie *pcie = dev_get_priv(bus);
+ int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16);
+
+ return (PCI_BUS(bdf) >= pcie->first_busno &&
+ PCI_BUS(bdf) < pcie->first_busno + num_buses);
+}
+
/**
* pci_generic_ecam_read_config() - Read from configuration space
* @bus: Pointer to the PCI bus
@@ -68,6 +79,11 @@ static int pci_generic_ecam_read_config(const struct udevice
*bus,
pci_dev_t bdf, uint offset,
ulong *valuep, enum pci_size_t size)
{
+ if (!pci_generic_ecam_addr_valid(bus, bdf)) {
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
return pci_generic_mmap_read_config(bus, pci_generic_ecam_conf_address,
bdf, offset, valuep, size);
}
@@ -88,6 +104,9 @@ static int pci_generic_ecam_write_config(struct udevice
*bus, pci_dev_t bdf,
uint offset, ulong value,
enum pci_size_t size)
{
+ if (!pci_generic_ecam_addr_valid(bus, bdf))
+ return 0;
+
return pci_generic_mmap_write_config(bus, pci_generic_ecam_conf_address,
bdf, offset, value, size);
}
@@ -116,9 +135,17 @@ static int pci_generic_ecam_ofdata_to_platdata(struct
udevice *dev)
return err;
}
- pcie->cfg_base = map_physmem(reg_res.start,
-fdt_resource_size(®_res),
-MAP_NOCACHE);
+ pcie->size = fdt_resource_size(®_res);
+ pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE);
+
+ return 0;
+}
+
+static int pci_generic_ecam_probe(struct udevice *dev)
+{
+ struct generic_ecam_pcie *pcie = dev_get_priv(dev);
+
+ pcie->first_busno = dev->seq;
return 0;
}
@@ -138,6 +165,7 @@ U_BOOT_DRIVER(pci_generic_ecam) = {
.id = UCLASS_PCI,
.of_match = pci_generic_ecam_ids,
.ops= &pci_generic_ecam_ops,
+ .probe = pci_generic_ecam_probe,
.ofdata_to_platdata = pci_generic_ecam_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct generic_ecam_pcie),
};
--
2.17.1
[PATCH 2/3] watchdog: move initr_watchdog() to wdt-uclass.c
This function is a bit large for an inline function, and for U-Boot
proper, it is called via a function pointer anyway (in board_r.c), so
cannot be inlined.
It will shortly set a global variable to be used by the
watchdog_reset() function in wdt-uclass.c, so this also allows making
that variable local to wdt-uclass.c.
The WATCHDOG_TIMEOUT_SECS define is not used elsewhere.
Signed-off-by: Rasmus Villemoes
---
drivers/watchdog/wdt-uclass.c | 33 +
include/wdt.h | 35 +--
2 files changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c
index 309a0e9c5b..fb3e247c5f 100644
--- a/drivers/watchdog/wdt-uclass.c
+++ b/drivers/watchdog/wdt-uclass.c
@@ -13,6 +13,39 @@
DECLARE_GLOBAL_DATA_PTR;
+#define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000)
+
+int initr_watchdog(void)
+{
+ u32 timeout = WATCHDOG_TIMEOUT_SECS;
+
+ /*
+* Init watchdog: This will call the probe function of the
+* watchdog driver, enabling the use of the device
+*/
+ if (uclass_get_device_by_seq(UCLASS_WDT, 0,
+(struct udevice **)&gd->watchdog_dev)) {
+ debug("WDT: Not found by seq!\n");
+ if (uclass_get_device(UCLASS_WDT, 0,
+ (struct udevice **)&gd->watchdog_dev)) {
+ printf("WDT: Not found!\n");
+ return 0;
+ }
+ }
+
+ if (CONFIG_IS_ENABLED(OF_CONTROL)) {
+ timeout = dev_read_u32_default(gd->watchdog_dev, "timeout-sec",
+ WATCHDOG_TIMEOUT_SECS);
+ }
+
+ wdt_start(gd->watchdog_dev, timeout * 1000, 0);
+ gd->flags |= GD_FLG_WDT_READY;
+ printf("WDT: Started with%s servicing (%ds timeout)\n",
+ IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out", timeout);
+
+ return 0;
+}
+
int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
const struct wdt_ops *ops = device_get_ops(dev);
diff --git a/include/wdt.h b/include/wdt.h
index e833d3a772..aea5abc768 100644
--- a/include/wdt.h
+++ b/include/wdt.h
@@ -106,39 +106,6 @@ struct wdt_ops {
int (*expire_now)(struct udevice *dev, ulong flags);
};
-#if CONFIG_IS_ENABLED(WDT)
-#define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000)
-
-static inline int initr_watchdog(void)
-{
- u32 timeout = WATCHDOG_TIMEOUT_SECS;
-
- /*
-* Init watchdog: This will call the probe function of the
-* watchdog driver, enabling the use of the device
-*/
- if (uclass_get_device_by_seq(UCLASS_WDT, 0,
-(struct udevice **)&gd->watchdog_dev)) {
- debug("WDT: Not found by seq!\n");
- if (uclass_get_device(UCLASS_WDT, 0,
- (struct udevice **)&gd->watchdog_dev)) {
- printf("WDT: Not found!\n");
- return 0;
- }
- }
-
- if (CONFIG_IS_ENABLED(OF_CONTROL)) {
- timeout = dev_read_u32_default(gd->watchdog_dev, "timeout-sec",
- WATCHDOG_TIMEOUT_SECS);
- }
-
- wdt_start(gd->watchdog_dev, timeout * 1000, 0);
- gd->flags |= GD_FLG_WDT_READY;
- printf("WDT: Started with%s servicing (%ds timeout)\n",
- IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out", timeout);
-
- return 0;
-}
-#endif
+int initr_watchdog(void);
#endif /* _WDT_H_ */
--
2.23.0
[PATCH 0/3] watchdog: honour hw_margin_ms property
Some watchdogs must be reset more often than the once-per-second ratelimit used by the generic watchdog_reset function in wdt-uclass.c. There's precedent (from the gpio-wdt driver in linux) for using a property called hw_margin_ms to let the device tree tell the driver how often the device needs resetting. So use that generically. No change in default behaviour. On top of https://patchwork.ozlabs.org/patch/1242772/ . Stefan, something like this? That at least solves half my problems and might be useful to others as well. Then I'll have to figure out the time-stands-still problem in some other way. Rasmus Villemoes (3): watchdog: remove stale ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS from wdt.h watchdog: move initr_watchdog() to wdt-uclass.c watchdog: honour hw_margin_ms DT property drivers/watchdog/wdt-uclass.c | 43 ++- include/wdt.h | 38 +-- 2 files changed, 43 insertions(+), 38 deletions(-) -- 2.23.0
[PATCH 3/3] watchdog: honour hw_margin_ms DT property
Some watchdog devices, e.g. external gpio-triggered ones, must be
reset more often than once per second, which means that the current
rate-limiting logic in watchdog_reset() fails to keep the board alive.
gpio-wdt.txt in the linux source tree defines a "hw_margin_ms"
property used to specifiy the maximum time allowed between resetting
the device. Allow any watchdog device to specify such a property, and
then use a reset period of one quarter of that. We keep the current
default of resetting once every 1000ms.
Signed-off-by: Rasmus Villemoes
---
drivers/watchdog/wdt-uclass.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c
index fb3e247c5f..436a52fd08 100644
--- a/drivers/watchdog/wdt-uclass.c
+++ b/drivers/watchdog/wdt-uclass.c
@@ -15,6 +15,12 @@ DECLARE_GLOBAL_DATA_PTR;
#define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000)
+/*
+ * Reset every 1000ms, or however often is required as indicated by a
+ * hw_margin_ms property.
+ */
+static ulong reset_period = 1000;
+
int initr_watchdog(void)
{
u32 timeout = WATCHDOG_TIMEOUT_SECS;
@@ -36,6 +42,8 @@ int initr_watchdog(void)
if (CONFIG_IS_ENABLED(OF_CONTROL)) {
timeout = dev_read_u32_default(gd->watchdog_dev, "timeout-sec",
WATCHDOG_TIMEOUT_SECS);
+ reset_period = dev_read_u32_default(gd->watchdog_dev,
"hw_margin_ms",
+ 4*reset_period)/4;
}
wdt_start(gd->watchdog_dev, timeout * 1000, 0);
@@ -117,7 +125,7 @@ void watchdog_reset(void)
/* Do not reset the watchdog too often */
now = get_timer(0);
if (time_after(now, next_reset)) {
- next_reset = now + 1000;/* reset every 1000ms */
+ next_reset = now + reset_period;
wdt_reset(gd->watchdog_dev);
}
}
--
2.23.0
[PATCH 1/3] watchdog: remove stale ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS from wdt.h
Since WATCHDOG_TIMEOUT_MSECS was converted to Kconfig (commit
ca51ef7c0c), CONFIG_WATCHDOG_TIMEOUT_MSECS has been guaranteed to be
defined. So remove the dead fallback ifdeffery.
Signed-off-by: Rasmus Villemoes
---
include/wdt.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/wdt.h b/include/wdt.h
index 5bcff24ab3..e833d3a772 100644
--- a/include/wdt.h
+++ b/include/wdt.h
@@ -107,9 +107,6 @@ struct wdt_ops {
};
#if CONFIG_IS_ENABLED(WDT)
-#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
-#define CONFIG_WATCHDOG_TIMEOUT_MSECS (60 * 1000)
-#endif
#define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000)
static inline int initr_watchdog(void)
--
2.23.0
Re: [PATCH v2] Makefile: doesn't need check stack size when dtb is not built
On Tue, Mar 10, 2020 at 09:20:43AM +0900, AKASHI Takahiro wrote:
> The commit 5fed97af20da ("Makefile: ensure DTB doesn't overflow into
> initial stack") adds an extra check for stack size in BSS if
> CONFIG_SYS_INIT_SP_BSS_OFFSET is enabled.
> This check, however, doesn't make sense under the configuration where
> control dtb won't be built in and it should be void in such cases.
>
> Signed-off-by: AKASHI Takahiro
> Fixes: 5fed97af20da ("Makefile: ensure DTB doesn't overflow into initial
> stack")
> Reviewed-by: Stephen Warren
(I undid the linewrap as requested)
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH] serial: mcfuart: renaming to a more appropriate name
On Sat, Feb 29, 2020 at 01:09:35AM +0100, Angelo Dureghello wrote: > From: Angelo Durgehello > > All drivers seems to align now to serial_xxx maning, so, aligning > also this driver, to allow to be found easily. > > Signed-off-by: Angelo Durgehello After fixing this up to be a 'git mv' of the original file, applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] serial: mcfuart: fix uart port index
On Sat, Feb 29, 2020 at 01:01:32AM +0100, Angelo Dureghello wrote: > From: Angelo Durgehello > > Actually, using dev->seq value before probe to deduce the current > serial port index leads to reading an invalid seq value (-1). > So, getting dev->seq at probe time. > > Signed-off-by: Angelo Durgehello Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/1] fit: check return value of fit_image_get_data_size()
On Wed, Mar 11, 2020 at 09:51:08PM +0100, Heinrich Schuchardt wrote:
> GCC-10 reports:
>
> In file included from tools/common/image-fit.c:1:
> include/image.h: In function ‘fit_image_get_data_and_size’:
> ./tools/../common/image-fit.c:1015:9: warning: ‘len’ may be used
> uninitialized in this function [-Wmaybe-uninitialized]
> 1015 | *size = len;
> | ~~^
> ./tools/../common/image-fit.c:996:6: note: ‘len’ was declared here
> 996 | int len;
> | ^~~
>
> Add the missing check of the return value of fit_image_get_data_size().
>
> Fixes: c3c863880479 ("add FIT data-position & data-offset property support")
> Signed-off-by: Heinrich Schuchardt
> Reviewed-by: Simon Goldschmidt
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH] watchdog: Align Kconfig properties
On Wed, Mar 11, 2020 at 12:26:53PM +0100, Michal Simek wrote: > Just cleanup help indentation to be the same for all options. > It means indentation. > > OMAP3 should be indented by tabs which is also fixed. > > Signed-off-by: Michal Simek Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v2] cmd: gpio: Make `gpio input` return pin value again
On Wed, Mar 11, 2020 at 08:46:29AM +, Alex Kiernan wrote:
> 4dbc107f4683 ("cmd: gpio: Correct do_gpio() return value") correctly
> changed the behaviour of the gpio command to return CMD_RET_SUCCESS or
> CMD_RET_FAILURE, but any existing script which expects the return value
> to be the pin value is broken by this change.
>
> Reinstate the legacy behaviour for `gpio input` only.
>
> Fixes: 4dbc107f4683 ("cmd: gpio: Correct do_gpio() return value")
> Signed-off-by: Alex Kiernan
> Signed-off-by: Alex Kiernan
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH] MAINTAINERS: update entry for ARM STI
On Thu, Mar 12, 2020 at 11:11:18AM +0100, Patrice Chotard wrote: > Add STi drivers/include files and git tree. > > Signed-off-by: Patrice Chotard Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[PATCH 1/4] ARM: dts: Activate pullups in the console pins on rv1108-elgin-r1
In order to make the console pins more robust to noise, activate
the pullups and increase its drive strength.
Signed-off-by: Otavio Salvador
---
arch/arm/dts/rv1108-elgin-r1.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/dts/rv1108-elgin-r1.dts b/arch/arm/dts/rv1108-elgin-r1.dts
index 32b95940b0..83e8b31838 100644
--- a/arch/arm/dts/rv1108-elgin-r1.dts
+++ b/arch/arm/dts/rv1108-elgin-r1.dts
@@ -40,9 +40,20 @@
};
&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m0_xfer_pullup>;
status = "okay";
};
&usb20_otg {
status = "okay";
};
+
+&pinctrl {
+ uart2m0 {
+ uart2m0_xfer_pullup: uart2m0-xfer-pullup {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_1
&pcfg_pull_up_drv_8ma>,
+ <2 RK_PD1 RK_FUNC_1
&pcfg_pull_up_drv_8ma>;
+ };
+ };
+};
--
2.25.1
[PATCH 0/4] Fixes for rv1108 and rv1108-elgin-r1
Those are fixes we've been using and we'd like to upstream. They are fixes and would be great to have them included on 2020.04 release. Otavio Salvador (4): ARM: dts: Activate pullups in the console pins on rv1108-elgin-r1 elgin-rv1108: Use rk_board_late_init() for GPIO settings elgin-rv1108: Avoid adc_channel_single_shot error rv1108: Fix boot regression arch/arm/dts/rv1108-elgin-r1.dts| 11 +++ arch/arm/dts/rv1108-u-boot.dtsi | 6 ++ board/elgin/elgin_rv1108/elgin_rv1108.c | 2 +- configs/elgin-rv1108_defconfig | 2 ++ 4 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rv1108-u-boot.dtsi -- 2.25.1
[PATCH 3/4] elgin-rv1108: Avoid adc_channel_single_shot error
Currently the following error message is seen during boot: U-Boot 2020.01-08751-g55759ae141 (Mar 09 2020 - 14:44:52 -0300) Model: Elgin RV1108 R1 board DRAM: 128 MiB APLL: 6 DPLL:12 GPLL:118800 ACLK_BUS: 14850 ACLK_PERI:14850 HCLK_PERI:14850 PCLK_PERI:7425 MMC: dwmmc@3011: 0 Loading Environment from MMC... OK In:serial@1021 Out: serial@1021 Err: serial@1021 Model: Elgin RV1108 R1 board rockchip_dnl_key_pressed: adc_channel_single_shot fail! Since the elgin-rv1108 does not use ADC to read the download key status, select CONFIG_ROCKCHIP_BOOT_MODE_REG=0 to avoid such error. Signed-off-by: Otavio Salvador --- configs/elgin-rv1108_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig index 80d53f3c10..b6682994f5 100644 --- a/configs/elgin-rv1108_defconfig +++ b/configs/elgin-rv1108_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x6000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ROCKCHIP_RV1108=y CONFIG_TARGET_ELGIN_RV1108=y +CONFIG_ROCKCHIP_BOOT_MODE_REG=0 CONFIG_NR_DRAM_BANKS=1 CONFIG_DEBUG_UART_BASE=0x1021 CONFIG_DEBUG_UART_CLOCK=2400 -- 2.25.1
[PATCH 2/4] elgin-rv1108: Use rk_board_late_init() for GPIO settings
Since commit 8e9a8d0d0c8c ("rockchip: elgin-rv1108: use board_early_init_f
for per-boar init") the function that configure the board GPIOs is no
longer called since CONFIG_BOARD_EARLY_INIT_F=y is not selected.
These GPIOs do not need to be configured in such early stagem, so change it
to rk_board_late_init() and also select CONFIG_BOARD_LATE_INIT=y
to fix the regression.
Signed-off-by: Otavio Salvador
Signed-off-by: Fabio Berton
---
board/elgin/elgin_rv1108/elgin_rv1108.c | 2 +-
configs/elgin-rv1108_defconfig | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c
b/board/elgin/elgin_rv1108/elgin_rv1108.c
index 607667ac63..950ab2 100644
--- a/board/elgin/elgin_rv1108/elgin_rv1108.c
+++ b/board/elgin/elgin_rv1108/elgin_rv1108.c
@@ -50,7 +50,7 @@ int mach_cpu_init(void)
#define MODEM_ENABLE_GPIO 111
-int board_early_init_f(void)
+int rk_board_late_init(void)
{
gpio_request(MODEM_ENABLE_GPIO, "modem_enable");
gpio_direction_output(MODEM_ENABLE_GPIO, 0);
diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig
index 62af7634a3..80d53f3c10 100644
--- a/configs/elgin-rv1108_defconfig
+++ b/configs/elgin-rv1108_defconfig
@@ -10,6 +10,7 @@ CONFIG_DEBUG_UART_CLOCK=2400
CONFIG_DEBUG_UART=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="rv1108-elgin-r1.dtb"
+CONFIG_BOARD_LATE_INIT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GPIO=y
--
2.25.1
[PATCH 4/4] rv1108: Fix boot regression
Since commit 79030a486128 ("rockchip: Add Single boot image
(with binman, pad_cat)") the following boot regression is seen:
U-Boot 2020.04-rc3-00050-gd16e18ca6c-dirty (Mar 09 2020 - 11:40:07 -0300)
Model: Elgin RV1108 R1 board
DRAM: 128 MiB
initcall sequence 67fd12a0 failed at call 6000b927 (err=-22)
This happens because the above commit missed to include the
"rockchip-u-boot.dtsi" for rv1108, so include this file
like it done for other Rockchip SoC dtsi's.
Fixes: 79030a486128 ("rockchip: Add Single boot image (with binman, pad_cat)")
Signed-off-by: Otavio Salvador
---
arch/arm/dts/rv1108-u-boot.dtsi | 6 ++
1 file changed, 6 insertions(+)
create mode 100644 arch/arm/dts/rv1108-u-boot.dtsi
diff --git a/arch/arm/dts/rv1108-u-boot.dtsi b/arch/arm/dts/rv1108-u-boot.dtsi
new file mode 100644
index 00..41ac054b81
--- /dev/null
+++ b/arch/arm/dts/rv1108-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki
+ */
+
+#include "rockchip-u-boot.dtsi"
--
2.25.1
Re: [PATCHv2 6/8] scripts/dtc: Update to upstream version v1.4.6-21-g84e414b0b5bc
On Wed, Mar 11, 2020 at 5:11 PM Tom Rini wrote:
>
> From: Rob Herring
>
> This adds the following commits from upstream:
>
> 84e414b0b5bc tests: Add a test case for the omit-if-no-ref keyword
> 4038fd90056e dtc: add ability to make nodes conditional on them being
> referenced
> e1f139ea4900 checks: drop warning for missing PCI bridge bus-range
> f4eba68d89ee checks: Print duplicate node name instead of parent name
> 46df1fb1b211 .travis.yml: Run valgrind checks via Travis
> 14a3002a1aee tests: Update valgrind suppressions for sw_tree1
> 02c5fe9debc0 tests: Remove valgrind error from tests/get_path
> df536831d02c checks: add graph binding checks
> 2347c96edcbe checks: add a check for duplicate unit-addresses of child nodes
> 8f1b35f88395 Correct overlay syntactic sugar for generating target-path
> fragments
> afbddcd418fb Suppress warnings on overlay fragments
> 119e27300359 Improve tests for dtc overlay generation
That's 100s of commits behind master. Any reason why (IIRC, you revert
the unaligned handling change)? In particular, there's a fix for GCC
10 and clang with commit:
0e9225eb0dfe Remove redundant YYLOC global declaration
Only just now pointed out to me for updating the kernel copy. Though I
guess this could be handled with '-fcommon' instead.
Rob
>
> [From Linux Kernel commit 50aafd60898a8b3edf2f60e014a8288da3b2e5e3]
> Signed-off-by: Rob Herring
>
> [For applying to U-Boot]
> Signed-off-by: Tom Rini
> ---
> scripts/dtc/checks.c | 186 +-
> scripts/dtc/dtc-parser.y | 22 ++---
> scripts/dtc/livetree.c| 12 ++-
> scripts/dtc/version_gen.h | 2 +-
> 4 files changed, 206 insertions(+), 16 deletions(-)
>
> diff --git a/scripts/dtc/checks.c b/scripts/dtc/checks.c
> index 40879677c8c3..c35aa6f88639 100644
> --- a/scripts/dtc/checks.c
> +++ b/scripts/dtc/checks.c
> @@ -255,7 +255,7 @@ static void check_duplicate_node_names(struct check *c,
> struct dt_info *dti,
> child2;
> child2 = child2->next_sibling)
> if (streq(child->name, child2->name))
> - FAIL(c, dti, node, "Duplicate node name");
> + FAIL(c, dti, child2, "Duplicate node name");
> }
> ERROR(duplicate_node_names, check_duplicate_node_names, NULL);
>
> @@ -317,6 +317,11 @@ static void check_unit_address_vs_reg(struct check *c,
> struct dt_info *dti,
> const char *unitname = get_unitname(node);
> struct property *prop = get_property(node, "reg");
>
> + if (get_subnode(node, "__overlay__")) {
> + /* HACK: Overlay fragments are a special case */
> + return;
> + }
> +
> if (!prop) {
> prop = get_property(node, "ranges");
> if (prop && !prop->val.len)
> @@ -1030,6 +1035,36 @@ static void check_avoid_unnecessary_addr_size(struct
> check *c, struct dt_info *d
> }
> WARNING(avoid_unnecessary_addr_size, check_avoid_unnecessary_addr_size,
> NULL, &avoid_default_addr_size);
>
> +static void check_unique_unit_address(struct check *c, struct dt_info *dti,
> + struct node *node)
> +{
> + struct node *childa;
> +
> + if (node->addr_cells < 0 || node->size_cells < 0)
> + return;
> +
> + if (!node->children)
> + return;
> +
> + for_each_child(node, childa) {
> + struct node *childb;
> + const char *addr_a = get_unitname(childa);
> +
> + if (!strlen(addr_a))
> + continue;
> +
> + for_each_child(node, childb) {
> + const char *addr_b = get_unitname(childb);
> + if (childa == childb)
> + break;
> +
> + if (streq(addr_a, addr_b))
> + FAIL(c, dti, childb, "duplicate unit-address
> (also used in node %s)", childa->fullpath);
> + }
> + }
> +}
> +WARNING(unique_unit_address, check_unique_unit_address, NULL,
> &avoid_default_addr_size);
> +
> static void check_obsolete_chosen_interrupt_controller(struct check *c,
>struct dt_info *dti,
>struct node *node)
> @@ -1370,6 +1405,152 @@ static void check_interrupts_property(struct check *c,
> }
> WARNING(interrupts_property, check_interrupts_property, &phandle_references);
>
> +static const struct bus_type graph_port_bus = {
> + .name = "graph-port",
> +};
> +
> +static const struct bus_type graph_ports_bus = {
> + .name = "graph-ports",
> +};
> +
> +static void check_graph_nodes(struct check *c, struct dt_info *dti,
> + struct node *node)
> +{
> + struct node *child;
> +
> + for_each_child(node, child) {
> + if (!(strprefixeq(child->name, child->ba
Re: [PATCHv2 6/8] scripts/dtc: Update to upstream version v1.4.6-21-g84e414b0b5bc
On Fri, Mar 13, 2020 at 03:01:05PM -0500, Rob Herring wrote: > On Wed, Mar 11, 2020 at 5:11 PM Tom Rini wrote: > > > > From: Rob Herring > > > > This adds the following commits from upstream: > > > > 84e414b0b5bc tests: Add a test case for the omit-if-no-ref keyword > > 4038fd90056e dtc: add ability to make nodes conditional on them being > > referenced > > e1f139ea4900 checks: drop warning for missing PCI bridge bus-range > > f4eba68d89ee checks: Print duplicate node name instead of parent name > > 46df1fb1b211 .travis.yml: Run valgrind checks via Travis > > 14a3002a1aee tests: Update valgrind suppressions for sw_tree1 > > 02c5fe9debc0 tests: Remove valgrind error from tests/get_path > > df536831d02c checks: add graph binding checks > > 2347c96edcbe checks: add a check for duplicate unit-addresses of child nodes > > 8f1b35f88395 Correct overlay syntactic sugar for generating target-path > > fragments > > afbddcd418fb Suppress warnings on overlay fragments > > 119e27300359 Improve tests for dtc overlay generation > > That's 100s of commits behind master. Any reason why (IIRC, you revert > the unaligned handling change)? In particular, there's a fix for GCC > 10 and clang with commit: > > 0e9225eb0dfe Remove redundant YYLOC global declaration > > Only just now pointed out to me for updating the kernel copy. Though I > guess this could be handled with '-fcommon' instead. I'm (slowly) getting all of the U-Boot Kbuild/Kconfig (and so, dtc) infrastructure in-line with Linux again, and then try and keep it up to date. -- Tom signature.asc Description: PGP signature
[PATCH v2 1/4] riscv: Add boot hartid to Device tree
Linux booting protocol mandates that register "a0" contains the hartid.
However, U-boot can not pass the hartid via a0 during via standard UEFI
protocol. DT nodes are commonly used to pass such information to the OS.
Add a DT node under chosen node to indicate the boot hartid. EFI stub
in Linux kernel will parse this node and pass it to the real kernel
in "a0" before jumping to it.
Signed-off-by: Atish Patra
Reviewed-by: Rick Chen
---
arch/riscv/lib/bootm.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index fad16901c5f2..f927694ae32f 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -28,6 +28,28 @@ __weak void board_quiesce_devices(void)
int arch_fixup_fdt(void *blob)
{
+ u32 size;
+ int chosen_offset, err;
+
+ size = fdt_totalsize(blob);
+ err = fdt_open_into(blob, blob, size + 32);
+ if (err < 0) {
+ printf("Device Tree can't be expanded to accommodate new node");
+ return -1;
+ }
+ chosen_offset = fdt_path_offset(blob, "/chosen");
+ if (chosen_offset < 0) {
+ err = fdt_add_subnode(blob, 0, "chosen");
+ if (err < 0) {
+ printf("chosen node can not be added\n");
+ return -1;
+ }
+ }
+
+ /* Overwrite the boot-hartid as U-Boot is the last state BL */
+ fdt_setprop_u32(blob, chosen_offset, "boot-hartid",
+ gd->arch.boot_hart);
+
return 0;
}
--
2.25.1
[PATCH v2 3/4] riscv: Provide a mechanism for riscv boards to parse reserved memory
In RISC-V, M-mode software can reserve physical memory regions
by setting appropriate physical memory protection (PMP) csr. As the
PMP csr are accessible only in M-mode, S-mode U-Boot can not read
this configuration directly. However, M-mode software can pass this
information via reserved-memory node in device tree so that S-mode
software can access this information.
In U-boot, any board may use the DT in following ways.
1. OF_SEPARTE: It ignores the DT from previous stage and uses the DT
from U-Boot sources.
2. OF_PRIOR_STATE: It reuses the DT from previous stage.
For case 1: U-Boot needs to parse the reserved-memory node from the
DT passed from the previous stage and update the DT in use.
This patch provides a framework to do that from any RISC-V boards.
Signed-off-by: Atish Patra
---
arch/riscv/cpu/start.S| 1 +
arch/riscv/include/asm/global_data.h | 1 +
arch/riscv/include/asm/u-boot-riscv.h | 1 +
arch/riscv/lib/asm-offsets.c | 1 +
arch/riscv/lib/bootm.c| 37 +++
5 files changed, 41 insertions(+)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 6b3ff99c3882..0282685c2906 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -121,6 +121,7 @@ call_board_init_f_0:
jal board_init_f_init_reserve
+ SREGs1, GD_FIRMWARE_FDT_ADDR(gp)
/* save the boot hart id to global_data */
SREGtp, GD_BOOT_HART(gp)
diff --git a/arch/riscv/include/asm/global_data.h
b/arch/riscv/include/asm/global_data.h
index b74bd7e738bb..51ac8d1c98e2 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -15,6 +15,7 @@
/* Architecture-specific global data */
struct arch_global_data {
long boot_hart; /* boot hart id */
+ phys_addr_t firmware_fdt_addr;
#ifdef CONFIG_SIFIVE_CLINT
void __iomem *clint;/* clint base address */
#endif
diff --git a/arch/riscv/include/asm/u-boot-riscv.h
b/arch/riscv/include/asm/u-boot-riscv.h
index 49febd588102..b7bea0ba184d 100644
--- a/arch/riscv/include/asm/u-boot-riscv.h
+++ b/arch/riscv/include/asm/u-boot-riscv.h
@@ -17,5 +17,6 @@ int cleanup_before_linux(void);
/* board/.../... */
int board_init(void);
void board_quiesce_devices(void);
+int riscv_board_reserved_mem_fixup(void *fdt);
#endif /* _U_BOOT_RISCV_H_ */
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index 4fa4fd371473..7301c1b98e23 100644
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -14,6 +14,7 @@
int main(void)
{
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
+ DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr));
#ifndef CONFIG_XIP
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
#endif
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index f927694ae32f..3a4d0bf14c86 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -26,6 +27,42 @@ __weak void board_quiesce_devices(void)
{
}
+int riscv_board_reserved_mem_fixup(void *fdt)
+{
+ uint32_t phandle;
+ struct fdt_memory pmp_mem;
+ int err;
+ void *src_fdt_addr;
+ int offset, node;
+ phys_addr_t addr, size;
+
+ src_fdt_addr = map_sysmem(gd->arch.firmware_fdt_addr, 0);
+ offset = fdt_path_offset(src_fdt_addr, "/reserved-memory");
+ if (offset < 0) {
+ printf("No reserved memory region found in FDT\n");
+ return offset;
+ }
+
+ fdt_for_each_subnode(node, src_fdt_addr, offset) {
+ const char *name = fdt_get_name(src_fdt_addr, node, NULL);
+
+ addr = fdtdec_get_addr_size(src_fdt_addr, node, "reg", &size);
+ if (addr == FDT_ADDR_T_NONE) {
+ debug("failed to read address/size for %s\n", name);
+ continue;
+ }
+ pmp_mem.start = addr;
+ pmp_mem.end = addr + size;
+ err = fdtdec_add_reserved_memory(fdt, name, &pmp_mem, &phandle);
+ if (err < 0) {
+ printf("failed to add reserved memory: %d\n", err);
+ return err;
+ }
+ }
+
+ return 0;
+}
+
int arch_fixup_fdt(void *blob)
{
u32 size;
--
2.25.1
[PATCH v2 0/4] DT related fixes for RISC-V UEFI
This series adds few DT related fixes required for Linux EFI stub to work on RISC-V. Patch 1 adds the boot hartid property under /chosen node. The related discussion can be found here. https://patchwork.ozlabs.org/patch/1233664/ https://lists.denx.de/pipermail/u-boot/2020-March/402085.html Patch 2 fixes a generic issue in bootefi. Patch 3 & 4 provide one of the option to update reserved-memory node for Linux. It depends on Bin's following series in OpenSBI http://lists.infradead.org/pipermail/opensbi/2020-March/001316.html The other options are SBI extension and trap/emulate on PMP csr access. The detaild discussion can be found here. https://github.com/riscv/riscv-sbi-doc/pull/37 Patch 1 & 2 can be applied indepedently from 3 and 4. I want to keep all the patches together to provide a holistic view of changes required for RISC-V UEFI. Changes from v1->v2: 1. Fix the issue if chosen node is not present. Changes from previous version: 1. Renamed the DT node property to "boot-hartid" from "efi-boot-hartid". 2. Changed the property type to u32 instead of u64 for RV32 compatibility. Atish Patra (4): riscv: Add boot hartid to Device tree cmd: bootefi: Parse reserved-memory node from DT riscv: Provide a mechanism for riscv boards to parse reserved memory riscv: Setup reserved-memory node for FU540 arch/riscv/cpu/start.S| 1 + arch/riscv/include/asm/global_data.h | 1 + arch/riscv/include/asm/u-boot-riscv.h | 1 + arch/riscv/lib/asm-offsets.c | 1 + arch/riscv/lib/bootm.c| 59 +++ board/sifive/fu540/fu540.c| 15 +++ cmd/bootefi.c | 42 +++ configs/sifive_fu540_defconfig| 1 + 8 files changed, 112 insertions(+), 9 deletions(-) -- 2.25.1
[PATCH v2 4/4] riscv: Setup reserved-memory node for FU540
FU540 uses OF_SEPARATE instead of OF_PRIOR.
Enable OF_BOARD_FIXUP to update the DT with reserved-memory node.
Signed-off-by: Atish Patra
---
board/sifive/fu540/fu540.c | 15 +++
configs/sifive_fu540_defconfig | 1 +
2 files changed, 16 insertions(+)
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index 47a20902517c..82b3a9c8e729 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -141,6 +141,21 @@ int misc_init_r(void)
#endif
+#ifdef CONFIG_OF_BOARD_FIXUP
+int board_fix_fdt(void *fdt)
+{
+ int err;
+
+ err = riscv_board_reserved_mem_fixup(fdt);
+ if (err < 0) {
+ printf("failed to fixup DT for reserved memory: %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+#endif
+
int board_init(void)
{
/* For now nothing to do here. */
diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig
index 6d61e6c960ee..8fb3794cd578 100644
--- a/configs/sifive_fu540_defconfig
+++ b/configs/sifive_fu540_defconfig
@@ -12,3 +12,4 @@ CONFIG_DISPLAY_BOARDINFO=y
CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_MTD=y
+CONFIG_OF_BOARD_FIXUP=y
--
2.25.1
[PATCH v2 2/4] cmd: bootefi: Parse reserved-memory node from DT
Currently, bootefi only parses memory reservation block to setup
EFI reserved memory mappings. However, it doesn't parse the
reserved-memory[1] device tree node that also can contain the
reserved memory regions.
Add capability to parse reserved-memory node and update the EFI memory
mappings accordingly.
1. /doc/device-tree-bindings/reserved-memory/reserved-memory.txt]
Signed-off-by: Atish Patra
---
cmd/bootefi.c | 42 +-
1 file changed, 33 insertions(+), 9 deletions(-)
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 24fc42ae898e..43b36fbacfcd 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -149,6 +149,20 @@ done:
return ret;
}
+static void efi_reserve_memory(uint64_t addr, uint64_t size)
+{
+ uint64_t pages;
+
+ /* Convert from sandbox address space. */
+ addr = (uintptr_t)map_sysmem(addr, 0);
+ pages = efi_size_in_pages(size + (addr & EFI_PAGE_MASK));
+ addr &= ~EFI_PAGE_MASK;
+ if (efi_add_memory_map(addr, pages, EFI_RESERVED_MEMORY_TYPE,
+ false) != EFI_SUCCESS)
+ printf("Reserved memory mapping failed addr %llx size %llx\n",
+ (unsigned long long)addr, (unsigned long long)size);
+}
+
/**
* efi_carve_out_dt_rsv() - Carve out DT reserved memory ranges
*
@@ -161,7 +175,8 @@ done:
static void efi_carve_out_dt_rsv(void *fdt)
{
int nr_rsv, i;
- uint64_t addr, size, pages;
+ uint64_t addr, size;
+ int nodeoffset, subnode;
nr_rsv = fdt_num_mem_rsv(fdt);
@@ -169,15 +184,24 @@ static void efi_carve_out_dt_rsv(void *fdt)
for (i = 0; i < nr_rsv; i++) {
if (fdt_get_mem_rsv(fdt, i, &addr, &size) != 0)
continue;
+ efi_reserve_memory(addr, size);
+ }
- /* Convert from sandbox address space. */
- addr = (uintptr_t)map_sysmem(addr, 0);
-
- pages = efi_size_in_pages(size + (addr & EFI_PAGE_MASK));
- addr &= ~EFI_PAGE_MASK;
- if (efi_add_memory_map(addr, pages, EFI_RESERVED_MEMORY_TYPE,
- false) != EFI_SUCCESS)
- printf("FDT memrsv map %d: Failed to add to map\n", i);
+ /* process reserved-memory */
+ nodeoffset = fdt_subnode_offset(fdt, 0, "reserved-memory");
+ if (nodeoffset >= 0) {
+ subnode = fdt_first_subnode(fdt, nodeoffset);
+ while (subnode >= 0) {
+ /* check if this subnode has a reg property */
+ addr = fdtdec_get_addr_size(fdt, subnode, "reg",
+ (fdt_size_t *)&size);
+ if (addr == FDT_ADDR_T_NONE) {
+ debug("failed to read address/size\n");
+ continue;
+ }
+ efi_reserve_memory(addr, size);
+ subnode = fdt_next_subnode(fdt, subnode);
+ }
}
}
--
2.25.1
Re: [PATCH v2 0/4] DT related fixes for RISC-V UEFI
On Fri, Mar 13, 2020 at 5:11 PM Atish Patra wrote: > > This series adds few DT related fixes required for Linux EFI stub to work > on RISC-V. > > Patch 1 adds the boot hartid property under /chosen node. The related > discussion can be found here. > > https://patchwork.ozlabs.org/patch/1233664/ > https://lists.denx.de/pipermail/u-boot/2020-March/402085.html > > Patch 2 fixes a generic issue in bootefi. > > Patch 3 & 4 provide one of the option to update reserved-memory node for > Linux. > It depends on Bin's following series in OpenSBI > http://lists.infradead.org/pipermail/opensbi/2020-March/001316.html > > The other options are SBI extension and trap/emulate on PMP csr access. > The detaild discussion can be found here. > https://github.com/riscv/riscv-sbi-doc/pull/37 > > Patch 1 & 2 can be applied indepedently from 3 and 4. I want to keep all > the patches together to provide a holistic view of changes required for > RISC-V UEFI. > > Changes from v1->v2: > 1. Fix the issue if chosen node is not present. > > Changes from previous version: > 1. Renamed the DT node property to "boot-hartid" from "efi-boot-hartid". > 2. Changed the property type to u32 instead of u64 for RV32 compatibility. > > Atish Patra (4): > riscv: Add boot hartid to Device tree > cmd: bootefi: Parse reserved-memory node from DT > riscv: Provide a mechanism for riscv boards to parse reserved memory > riscv: Setup reserved-memory node for FU540 > > arch/riscv/cpu/start.S| 1 + > arch/riscv/include/asm/global_data.h | 1 + > arch/riscv/include/asm/u-boot-riscv.h | 1 + > arch/riscv/lib/asm-offsets.c | 1 + > arch/riscv/lib/bootm.c| 59 +++ > board/sifive/fu540/fu540.c| 15 +++ > cmd/bootefi.c | 42 +++ > configs/sifive_fu540_defconfig| 1 + > 8 files changed, 112 insertions(+), 9 deletions(-) > > -- > 2.25.1 > Fixed palmer's email address. Sorry for the spam. -- Regards, Atish
Re: [PATCH v2 1/4] riscv: Add boot hartid to Device tree
On Fri, Mar 13, 2020 at 5:12 PM Atish Patra wrote:
>
> Linux booting protocol mandates that register "a0" contains the hartid.
> However, U-boot can not pass the hartid via a0 during via standard UEFI
> protocol. DT nodes are commonly used to pass such information to the OS.
>
> Add a DT node under chosen node to indicate the boot hartid. EFI stub
> in Linux kernel will parse this node and pass it to the real kernel
> in "a0" before jumping to it.
>
> Signed-off-by: Atish Patra
> Reviewed-by: Rick Chen
> ---
> arch/riscv/lib/bootm.c | 22 ++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
> index fad16901c5f2..f927694ae32f 100644
> --- a/arch/riscv/lib/bootm.c
> +++ b/arch/riscv/lib/bootm.c
> @@ -28,6 +28,28 @@ __weak void board_quiesce_devices(void)
>
> int arch_fixup_fdt(void *blob)
> {
> + u32 size;
> + int chosen_offset, err;
> +
> + size = fdt_totalsize(blob);
> + err = fdt_open_into(blob, blob, size + 32);
> + if (err < 0) {
> + printf("Device Tree can't be expanded to accommodate new
> node");
> + return -1;
> + }
> + chosen_offset = fdt_path_offset(blob, "/chosen");
> + if (chosen_offset < 0) {
> + err = fdt_add_subnode(blob, 0, "chosen");
> + if (err < 0) {
> + printf("chosen node can not be added\n");
> + return -1;
> + }
> + }
> +
> + /* Overwrite the boot-hartid as U-Boot is the last state BL */
> + fdt_setprop_u32(blob, chosen_offset, "boot-hartid",
> + gd->arch.boot_hart);
> +
> return 0;
> }
>
> --
> 2.25.1
>
Fixed palmer's email address. Sorry for the spam.
--
Regards,
Atish
Re: [PATCH v2 4/4] riscv: Setup reserved-memory node for FU540
On Fri, Mar 13, 2020 at 5:12 PM Atish Patra wrote:
>
> FU540 uses OF_SEPARATE instead of OF_PRIOR.
>
> Enable OF_BOARD_FIXUP to update the DT with reserved-memory node.
>
> Signed-off-by: Atish Patra
> ---
> board/sifive/fu540/fu540.c | 15 +++
> configs/sifive_fu540_defconfig | 1 +
> 2 files changed, 16 insertions(+)
>
> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
> index 47a20902517c..82b3a9c8e729 100644
> --- a/board/sifive/fu540/fu540.c
> +++ b/board/sifive/fu540/fu540.c
> @@ -141,6 +141,21 @@ int misc_init_r(void)
>
> #endif
>
> +#ifdef CONFIG_OF_BOARD_FIXUP
> +int board_fix_fdt(void *fdt)
> +{
> + int err;
> +
> + err = riscv_board_reserved_mem_fixup(fdt);
> + if (err < 0) {
> + printf("failed to fixup DT for reserved memory: %d\n", err);
> + return err;
> + }
> +
> + return 0;
> +}
> +#endif
> +
> int board_init(void)
> {
> /* For now nothing to do here. */
> diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig
> index 6d61e6c960ee..8fb3794cd578 100644
> --- a/configs/sifive_fu540_defconfig
> +++ b/configs/sifive_fu540_defconfig
> @@ -12,3 +12,4 @@ CONFIG_DISPLAY_BOARDINFO=y
> CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00"
> CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> CONFIG_DM_MTD=y
> +CONFIG_OF_BOARD_FIXUP=y
> --
> 2.25.1
>
Fixed palmer's email address. Sorry for the spam.
--
Regards,
Atish
Re: [PATCH v2 3/4] riscv: Provide a mechanism for riscv boards to parse reserved memory
On Fri, Mar 13, 2020 at 5:12 PM Atish Patra wrote:
>
> In RISC-V, M-mode software can reserve physical memory regions
> by setting appropriate physical memory protection (PMP) csr. As the
> PMP csr are accessible only in M-mode, S-mode U-Boot can not read
> this configuration directly. However, M-mode software can pass this
> information via reserved-memory node in device tree so that S-mode
> software can access this information.
>
> In U-boot, any board may use the DT in following ways.
> 1. OF_SEPARTE: It ignores the DT from previous stage and uses the DT
> from U-Boot sources.
> 2. OF_PRIOR_STATE: It reuses the DT from previous stage.
> For case 1: U-Boot needs to parse the reserved-memory node from the
> DT passed from the previous stage and update the DT in use.
>
> This patch provides a framework to do that from any RISC-V boards.
>
> Signed-off-by: Atish Patra
> ---
> arch/riscv/cpu/start.S| 1 +
> arch/riscv/include/asm/global_data.h | 1 +
> arch/riscv/include/asm/u-boot-riscv.h | 1 +
> arch/riscv/lib/asm-offsets.c | 1 +
> arch/riscv/lib/bootm.c| 37 +++
> 5 files changed, 41 insertions(+)
>
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index 6b3ff99c3882..0282685c2906 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -121,6 +121,7 @@ call_board_init_f_0:
>
> jal board_init_f_init_reserve
>
> + SREGs1, GD_FIRMWARE_FDT_ADDR(gp)
> /* save the boot hart id to global_data */
> SREGtp, GD_BOOT_HART(gp)
>
> diff --git a/arch/riscv/include/asm/global_data.h
> b/arch/riscv/include/asm/global_data.h
> index b74bd7e738bb..51ac8d1c98e2 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -15,6 +15,7 @@
> /* Architecture-specific global data */
> struct arch_global_data {
> long boot_hart; /* boot hart id */
> + phys_addr_t firmware_fdt_addr;
> #ifdef CONFIG_SIFIVE_CLINT
> void __iomem *clint;/* clint base address */
> #endif
> diff --git a/arch/riscv/include/asm/u-boot-riscv.h
> b/arch/riscv/include/asm/u-boot-riscv.h
> index 49febd588102..b7bea0ba184d 100644
> --- a/arch/riscv/include/asm/u-boot-riscv.h
> +++ b/arch/riscv/include/asm/u-boot-riscv.h
> @@ -17,5 +17,6 @@ int cleanup_before_linux(void);
> /* board/.../... */
> int board_init(void);
> void board_quiesce_devices(void);
> +int riscv_board_reserved_mem_fixup(void *fdt);
>
> #endif /* _U_BOOT_RISCV_H_ */
> diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
> index 4fa4fd371473..7301c1b98e23 100644
> --- a/arch/riscv/lib/asm-offsets.c
> +++ b/arch/riscv/lib/asm-offsets.c
> @@ -14,6 +14,7 @@
> int main(void)
> {
> DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
> + DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr));
> #ifndef CONFIG_XIP
> DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
> #endif
> diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
> index f927694ae32f..3a4d0bf14c86 100644
> --- a/arch/riscv/lib/bootm.c
> +++ b/arch/riscv/lib/bootm.c
> @@ -19,6 +19,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -26,6 +27,42 @@ __weak void board_quiesce_devices(void)
> {
> }
>
> +int riscv_board_reserved_mem_fixup(void *fdt)
> +{
> + uint32_t phandle;
> + struct fdt_memory pmp_mem;
> + int err;
> + void *src_fdt_addr;
> + int offset, node;
> + phys_addr_t addr, size;
> +
> + src_fdt_addr = map_sysmem(gd->arch.firmware_fdt_addr, 0);
> + offset = fdt_path_offset(src_fdt_addr, "/reserved-memory");
> + if (offset < 0) {
> + printf("No reserved memory region found in FDT\n");
> + return offset;
> + }
> +
> + fdt_for_each_subnode(node, src_fdt_addr, offset) {
> + const char *name = fdt_get_name(src_fdt_addr, node, NULL);
> +
> + addr = fdtdec_get_addr_size(src_fdt_addr, node, "reg", &size);
> + if (addr == FDT_ADDR_T_NONE) {
> + debug("failed to read address/size for %s\n", name);
> + continue;
> + }
> + pmp_mem.start = addr;
> + pmp_mem.end = addr + size;
> + err = fdtdec_add_reserved_memory(fdt, name, &pmp_mem,
> &phandle);
> + if (err < 0) {
> + printf("failed to add reserved memory: %d\n", err);
> + return err;
> + }
> + }
> +
> + return 0;
> +}
> +
> int arch_fixup_fdt(void *blob)
> {
> u32 size;
> --
> 2.25.1
>
Fixed palmer's email address. Sorry for the spam.
--
Regards,
Atish
Re: [PATCH v2 2/4] cmd: bootefi: Parse reserved-memory node from DT
On Fri, Mar 13, 2020 at 5:12 PM Atish Patra wrote:
>
> Currently, bootefi only parses memory reservation block to setup
> EFI reserved memory mappings. However, it doesn't parse the
> reserved-memory[1] device tree node that also can contain the
> reserved memory regions.
>
> Add capability to parse reserved-memory node and update the EFI memory
> mappings accordingly.
>
> 1. source>/doc/device-tree-bindings/reserved-memory/reserved-memory.txt]
>
> Signed-off-by: Atish Patra
> ---
> cmd/bootefi.c | 42 +-
> 1 file changed, 33 insertions(+), 9 deletions(-)
>
> diff --git a/cmd/bootefi.c b/cmd/bootefi.c
> index 24fc42ae898e..43b36fbacfcd 100644
> --- a/cmd/bootefi.c
> +++ b/cmd/bootefi.c
> @@ -149,6 +149,20 @@ done:
> return ret;
> }
>
> +static void efi_reserve_memory(uint64_t addr, uint64_t size)
> +{
> + uint64_t pages;
> +
> + /* Convert from sandbox address space. */
> + addr = (uintptr_t)map_sysmem(addr, 0);
> + pages = efi_size_in_pages(size + (addr & EFI_PAGE_MASK));
> + addr &= ~EFI_PAGE_MASK;
> + if (efi_add_memory_map(addr, pages, EFI_RESERVED_MEMORY_TYPE,
> + false) != EFI_SUCCESS)
> + printf("Reserved memory mapping failed addr %llx size %llx\n",
> + (unsigned long long)addr, (unsigned long long)size);
> +}
> +
> /**
> * efi_carve_out_dt_rsv() - Carve out DT reserved memory ranges
> *
> @@ -161,7 +175,8 @@ done:
> static void efi_carve_out_dt_rsv(void *fdt)
> {
> int nr_rsv, i;
> - uint64_t addr, size, pages;
> + uint64_t addr, size;
> + int nodeoffset, subnode;
>
> nr_rsv = fdt_num_mem_rsv(fdt);
>
> @@ -169,15 +184,24 @@ static void efi_carve_out_dt_rsv(void *fdt)
> for (i = 0; i < nr_rsv; i++) {
> if (fdt_get_mem_rsv(fdt, i, &addr, &size) != 0)
> continue;
> + efi_reserve_memory(addr, size);
> + }
>
> - /* Convert from sandbox address space. */
> - addr = (uintptr_t)map_sysmem(addr, 0);
> -
> - pages = efi_size_in_pages(size + (addr & EFI_PAGE_MASK));
> - addr &= ~EFI_PAGE_MASK;
> - if (efi_add_memory_map(addr, pages, EFI_RESERVED_MEMORY_TYPE,
> - false) != EFI_SUCCESS)
> - printf("FDT memrsv map %d: Failed to add to map\n",
> i);
> + /* process reserved-memory */
> + nodeoffset = fdt_subnode_offset(fdt, 0, "reserved-memory");
> + if (nodeoffset >= 0) {
> + subnode = fdt_first_subnode(fdt, nodeoffset);
> + while (subnode >= 0) {
> + /* check if this subnode has a reg property */
> + addr = fdtdec_get_addr_size(fdt, subnode, "reg",
> + (fdt_size_t *)&size);
> + if (addr == FDT_ADDR_T_NONE) {
> + debug("failed to read address/size\n");
> + continue;
> + }
> + efi_reserve_memory(addr, size);
> + subnode = fdt_next_subnode(fdt, subnode);
> + }
> }
> }
>
> --
> 2.25.1
>
Fixed palmer's email address. Sorry for the spam.
--
Regards,
Atish
