[U-Boot] [PATCH v8 12/19] arm: agilex: Add clock handoff offset for Agilex

2019-11-27 Thread Ley Foon Tan
Add clock handoff offset for Agilex. Remove S10 prefix to avoid confusion.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v8:
- Fixed missing CONFIG_ prefix for TARGET_SOCFPGA_STRATIX10.
---
 arch/arm/mach-socfpga/include/mach/handoff_s10.h | 9 +++--
 arch/arm/mach-socfpga/wrap_pll_config_s10.c  | 5 +++--
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h 
b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
index ba0f1fd1b2..3e9b606ce2 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_s10.h
@@ -26,8 +26,13 @@
 #define S10_HANDOFF_OFFSET_LENGTH  0x4
 #define S10_HANDOFF_OFFSET_DATA0x10
 
-#define S10_HANDOFF_CLOCK_OSC  (S10_HANDOFF_BASE + 0x608)
-#define S10_HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C)
+#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+#define HANDOFF_CLOCK_OSC  (S10_HANDOFF_BASE + 0x608)
+#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C)
+#else
+#define HANDOFF_CLOCK_OSC  (S10_HANDOFF_BASE + 0x5fc)
+#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x600)
+#endif
 
 #define S10_HANDOFF_SIZE   4096
 
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c 
b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
index b266a5817b..3da85791a1 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
@@ -33,7 +33,8 @@ const struct cm_config * const cm_get_default_config(void)
 const unsigned int cm_get_osc_clk_hz(void)
 {
 #ifdef CONFIG_SPL_BUILD
-   u32 clock = readl(S10_HANDOFF_CLOCK_OSC);
+
+   u32 clock = readl(HANDOFF_CLOCK_OSC);
 
writel(clock,
   socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
@@ -50,7 +51,7 @@ const unsigned int cm_get_intosc_clk_hz(void)
 const unsigned int cm_get_fpga_clk_hz(void)
 {
 #ifdef CONFIG_SPL_BUILD
-   u32 clock = readl(S10_HANDOFF_CLOCK_FPGA);
+   u32 clock = readl(HANDOFF_CLOCK_FPGA);
 
writel(clock,
   socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
-- 
2.19.0

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[U-Boot] [PATCH v8 15/19] board: intel: agilex: Add socdk board support for Intel Agilex SoC

2019-11-27 Thread Ley Foon Tan
Add socdk board support for Intel Agilex SoC

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 
---
 board/intel/agilex-socdk/MAINTAINERS | 7 +++
 board/intel/agilex-socdk/Makefile| 7 +++
 board/intel/agilex-socdk/socfpga.c   | 7 +++
 3 files changed, 21 insertions(+)
 create mode 100644 board/intel/agilex-socdk/MAINTAINERS
 create mode 100644 board/intel/agilex-socdk/Makefile
 create mode 100644 board/intel/agilex-socdk/socfpga.c

diff --git a/board/intel/agilex-socdk/MAINTAINERS 
b/board/intel/agilex-socdk/MAINTAINERS
new file mode 100644
index 00..b8e28f0b24
--- /dev/null
+++ b/board/intel/agilex-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M: Ley Foon Tan 
+M: Chee Hong Ang 
+S: Maintained
+F: board/intel/agilex-socdk/
+F: include/configs/socfpga_agilex_socdk.h
+F: configs/socfpga_agilex_defconfig
diff --git a/board/intel/agilex-socdk/Makefile 
b/board/intel/agilex-socdk/Makefile
new file mode 100644
index 00..b86223a571
--- /dev/null
+++ b/board/intel/agilex-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2019 Intel Corporation 
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y  := socfpga.o
diff --git a/board/intel/agilex-socdk/socfpga.c 
b/board/intel/agilex-socdk/socfpga.c
new file mode 100644
index 00..72a3e0836d
--- /dev/null
+++ b/board/intel/agilex-socdk/socfpga.c
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ *
+ */
+
+#include 
-- 
2.19.0

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[U-Boot] [PATCH v8 13/19] ddr: altera: Restructure Stratix 10 SDRAM driver

2019-11-27 Thread Ley Foon Tan
Restructure Stratix 10 SDRAM driver. Move common code to separate
file, in preparation to support SDRAM driver for Agilex.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v6:
- Remove compatible "intel,sdr-ctl-agilex" from this patch.

v3:
- Change sdram_common.* to sdram_soc64.*
---
 drivers/ddr/altera/Makefile   |   2 +-
 drivers/ddr/altera/sdram_s10.c| 296 +
 drivers/ddr/altera/sdram_s10.h| 148 +
 drivers/ddr/altera/sdram_soc64.c  | 303 ++
 .../ddr/altera/{sdram_s10.h => sdram_soc64.h} |  70 ++--
 5 files changed, 340 insertions(+), 479 deletions(-)
 create mode 100644 drivers/ddr/altera/sdram_soc64.c
 copy drivers/ddr/altera/{sdram_s10.h => sdram_soc64.h} (79%)

diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index 341ac0d73b..eb8da13b7d 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -9,5 +9,5 @@
 ifdef CONFIG_$(SPL_)ALTERA_SDRAM
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
-obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o
+obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
 endif
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index d7e6371ddb..fcab3ae3e4 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -14,28 +14,14 @@
 #include "sdram_s10.h"
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
 
-struct altera_sdram_priv {
-   struct ram_info info;
-   struct reset_ctl_bulk resets;
-};
-
-struct altera_sdram_platdata {
-   void __iomem *hmc;
-   void __iomem *ddr_sch;
-   void __iomem *iomhc;
-};
-
 DECLARE_GLOBAL_DATA_PTR;
 
 #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
 
-#define PGTABLE_OFF0x4000
-
 /* The followring are the supported configurations */
 u32 ddr_config[] = {
/* DDR_CONFIG(Address order,Bank,Column,Row) */
@@ -62,28 +48,6 @@ u32 ddr_config[] = {
DDR_CONFIG(1, 4, 10, 17),
 };
 
-static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
-{
-   return readl(plat->iomhc + reg);
-}
-
-static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
-{
-   return readl(plat->hmc + reg);
-}
-
-static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
- u32 data, u32 reg)
-{
-   return writel(data, plat->hmc + reg);
-}
-
-static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
- u32 reg)
-{
-   return writel(data, plat->ddr_sch + reg);
-}
-
 int match_ddr_conf(u32 ddr_conf)
 {
int i;
@@ -95,193 +59,12 @@ int match_ddr_conf(u32 ddr_conf)
return 0;
 }
 
-static int emif_clear(struct altera_sdram_platdata *plat)
-{
-   hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
-
-   return wait_for_bit_le32((const void *)(plat->hmc +
-RSTHANDSHAKESTAT),
-DDR_HMC_RSTHANDSHAKE_MASK,
-false, 1000, false);
-}
-
-static int emif_reset(struct altera_sdram_platdata *plat)
-{
-   u32 c2s, s2c, ret;
-
-   c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
-   s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
-
-   debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
- c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
- hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
- hmc_readl(plat, DRAMSTS));
-
-   if (s2c && emif_clear(plat)) {
-   printf("DDR: emif_clear() failed\n");
-   return -1;
-   }
-
-   debug("DDR: Triggerring emif reset\n");
-   hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
-
-   /* if seq2core[3] = 0, we are good */
-   ret = wait_for_bit_le32((const void *)(plat->hmc +
-RSTHANDSHAKESTAT),
-DDR_HMC_SEQ2CORE_INT_RESP_MASK,
-false, 1000, false);
-   if (ret) {
-   printf("DDR: failed to get ack from EMIF\n");
-   return ret;
-   }
-
-   ret = emif_clear(plat);
-   if (ret) {
-   printf("DDR: emif_clear() failed\n");
-   return ret;
-   }
-
-   debug("DDR: %s triggered successly\n", __func__);
-   return 0;
-}
-
-static int poll_hmc_clock_status(void)
-{
-   return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
-SYSMGR_SOC64_HMC_CLK),
-SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
-}
-
-static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
-{
-   phys_size_t i;
-
-   if (addr % CONFIG_SYS_CACHELINE_SIZE) {
-   print

[U-Boot] [PATCH v8 06/19] arm: socfpga: agilex: Add system manager support

2019-11-27 Thread Ley Foon Tan
Add system manager support for Agilex.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v5:
- Remove system_manager_agilex.h and use system_manager_soc64.h directly.

v3:
- Change include filename to system_manager_soc64.h.
- Move to use defines instead of struct.

v2:
- Include system_manager_s10_agilex_common.h in system_manager_agilex.h
---
 arch/arm/mach-socfpga/include/mach/system_manager.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 242ef2e8be..6de0a08131 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -8,7 +8,8 @@
 
 phys_addr_t socfpga_get_sysmgr_addr(void);
 
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+   defined(CONFIG_TARGET_SOCFPGA_AGILEX)
 #include 
 #else
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUXBIT(0)
-- 
2.19.0

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[U-Boot] [PATCH v8 05/19] arm: socfpga: Move Stratix10 and Agilex system manager common code

2019-11-27 Thread Ley Foon Tan
Move Stratix10 and Agilex system manager common code to
system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v5:
- Remove system_manager_s10.h and use system_manager_soc64.h.

v4:
- Change prefix from SYSMGR_S10* to SYSMGR_SOC64*.

v3:
- Change filename to system_manager_soc64.h
- Move to use defines instead of struct.

v2:
- Move common defines for Stratix 10 and Agilex to 
system_manager_s10_agilex_common.h
---
 arch/arm/mach-socfpga/clock_manager_s10.c |   3 +-
 arch/arm/mach-socfpga/firewall.c  |   4 +-
 .../include/mach/system_manager.h |   2 +-
 .../include/mach/system_manager_s10.h | 124 --
 .../include/mach/system_manager_soc64.h   | 123 +
 arch/arm/mach-socfpga/mailbox_s10.c   |   2 +-
 arch/arm/mach-socfpga/misc_s10.c  |   2 +-
 arch/arm/mach-socfpga/reset_manager_s10.c |  15 ++-
 arch/arm/mach-socfpga/spl_s10.c   |   2 +-
 arch/arm/mach-socfpga/system_manager_s10.c|  26 ++--
 arch/arm/mach-socfpga/wrap_pll_config_s10.c   |  10 +-
 drivers/ddr/altera/sdram_s10.c|   2 +-
 12 files changed, 159 insertions(+), 156 deletions(-)
 delete mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_soc64.h

diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c 
b/arch/arm/mach-socfpga/clock_manager_s10.c
index 5edeab1792..05e42127b5 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -385,7 +385,8 @@ unsigned int cm_get_l4_sp_clk_hz(void)
 
 unsigned int cm_get_qspi_controller_clk_hz(void)
 {
-   return readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_BOOT_SCRATCH_COLD0);
+   return readl(socfpga_get_sysmgr_addr() +
+SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
 }
 
 unsigned int cm_get_spi_controller_clk_hz(void)
diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach-socfpga/firewall.c
index 9a4111a931..69229dc651 100644
--- a/arch/arm/mach-socfpga/firewall.c
+++ b/arch/arm/mach-socfpga/firewall.c
@@ -101,7 +101,7 @@ void firewall_setup(void)
 
/* enable non-secure interface to DMA330 DMA and peripherals */
writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS,
-  socfpga_get_sysmgr_addr() + SYSMGR_S10_DMA);
+  socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA);
writel(SYSMGR_DMAPERIPH_ALL_NS,
-  socfpga_get_sysmgr_addr() + SYSMGR_S10_DMA_PERIPH);
+  socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA_PERIPH);
 }
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h 
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 7f05029a67..242ef2e8be 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -9,7 +9,7 @@
 phys_addr_t socfpga_get_sysmgr_addr(void);
 
 #if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
-#include 
+#include 
 #else
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUXBIT(0)
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIOBIT(1)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h 
b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
deleted file mode 100644
index 07dd19e06d..00
--- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * Copyright (C) 2016-2018 Intel Corporation 
- *
- */
-
-#ifndef_SYSTEM_MANAGER_S10_
-#define_SYSTEM_MANAGER_S10_
-
-void sysmgr_pinmux_init(void);
-void populate_sysmgr_fpgaintf_module(void);
-void populate_sysmgr_pinmux(void);
-void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
-
-#define SYSMGR_S10_WDDBG   0x08
-#define SYSMGR_S10_DMA 0x20
-#define SYSMGR_S10_DMA_PERIPH  0x24
-#define SYSMGR_S10_SDMMC   0x28
-#define SYSMGR_S10_SDMMC_L3MASTER  0x2c
-#define SYSMGR_S10_EMAC_GLOBAL 0x40
-#define SYSMGR_S10_EMAC0   0x44
-#define SYSMGR_S10_EMAC1   0x48
-#define SYSMGR_S10_EMAC2   0x4c
-#define SYSMGR_S10_EMAC0_ACE   0x50
-#define SYSMGR_S10_EMAC1_ACE   0x54
-#define SYSMGR_S10_EMAC2_ACE   0x58
-#define SYSMGR_S10_NAND_AXUSER 0x5c
-#define SYSMGR_S10_FPGAINTF_EN10x68
-#define SYSMGR_S10_FPGAINTF_EN20x6c
-#define SYSMGR_S10_FPGAINTF_EN30x70
-#define SYSMGR_S10_DMA_L3MASTER0x74
-#def

[U-Boot] [PATCH v8 10/19] arm: socfpga: agilex: Add clock wrapper functions

2019-11-27 Thread Ley Foon Tan
Add clock wrapper functions call to clock DM functions to get clock
frequency and used in cm_print_clock_quick_summary().

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v6:
- Use new macro names from agilex-clock.h.

v4:
- Change to use SYSMGR_SOC64* prefix.

v3:
- Improved commit message.
- Rename STRATIX10_* to SOCFPGA_SOC64_*
- Include clock_manager_soc64.h and clk-agilex.h.

v2:
- Get clocks from clock DM.
---
 arch/arm/mach-socfpga/Makefile|  4 +
 arch/arm/mach-socfpga/clock_manager_agilex.c  | 85 +++
 .../mach-socfpga/include/mach/clock_manager.h |  2 +
 .../include/mach/clock_manager_agilex.h   | 14 +++
 4 files changed, 105 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index dab34d0ef2..a403b46b47 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -39,6 +39,10 @@ obj-y+= wrap_pinmux_config_s10.o
 obj-y  += wrap_pll_config_s10.o
 endif
 
+ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+obj-y  += clock_manager_agilex.o
+endif
+
 ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 obj-y  += spl_gen5.o
diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c 
b/arch/arm/mach-socfpga/clock_manager_agilex.c
new file mode 100644
index 00..791066d25b
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong cm_get_rate_dm(u32 id)
+{
+   struct udevice *dev;
+   struct clk clk;
+   ulong rate;
+   int ret;
+
+   ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(socfpga_agilex_clk),
+ &dev);
+   if (ret)
+   return 0;
+
+   clk.id = id;
+   ret = clk_request(dev, &clk);
+   if (ret < 0)
+   return 0;
+
+   rate = clk_get_rate(&clk);
+
+   clk_free(&clk);
+
+   if ((rate == (unsigned long)-ENOSYS) ||
+   (rate == (unsigned long)-ENXIO) ||
+   (rate == (unsigned long)-EIO)) {
+   debug("%s id %u: clk_get_rate err: %ld\n",
+ __func__, id, rate);
+   return 0;
+   }
+
+   return rate;
+}
+
+static u32 cm_get_rate_dm_khz(u32 id)
+{
+   return cm_get_rate_dm(id) / 1000;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+   return cm_get_rate_dm(AGILEX_MPU_CLK);
+}
+
+unsigned int cm_get_l4_sys_free_clk_hz(void)
+{
+   return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
+}
+
+u32 cm_get_qspi_controller_clk_hz(void)
+{
+   return readl(socfpga_get_sysmgr_addr() +
+SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+}
+
+void cm_print_clock_quick_summary(void)
+{
+   printf("MPU   %10d kHz\n",
+  cm_get_rate_dm_khz(AGILEX_MPU_CLK));
+   printf("L4 Main %8d kHz\n",
+  cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
+   printf("L4 sys free %8d kHz\n",
+  cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
+   printf("L4 MP   %8d kHz\n",
+  cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
+   printf("L4 SP   %8d kHz\n",
+  cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
+   printf("SDMMC   %8d kHz\n",
+  cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));
+}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h 
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 6de7caef19..c6830582a5 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -20,6 +20,8 @@ void cm_print_clock_quick_summary(void);
 #include 
 #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
 #include 
+#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+#include 
 #endif
 
 #endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h 
b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
new file mode 100644
index 00..386e82a4e3
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#ifndef _CLOCK_MANAGER_AGILEX_
+#define _CLOCK_MANAGER_AGILEX_
+
+unsigned long cm_get_mpu_clk_hz(void);
+
+#include 
+#include "../../../../../drivers/clk/altera/clk-agilex.h"
+
+#endif /* _CLOCK_MANAGER_AGILEX_ */
-- 
2.19.0

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[U-Boot] [PATCH v8 16/19] arm: socfpga: agilex: Add SPL for Agilex SoC

2019-11-27 Thread Ley Foon Tan
Add SPL support for Agilex SoC.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v5:
- Probe CCU driver with DM method.

v4:
- Move spl_early_init() to entry of board_init_f
- Add socfpga_get_manager_addr().
- Remove SYSMGR_DMA and SYSMGR_DMA_PERIPH, already set in firewall_setup().

v2:
- Change clock driver probing to DM.
- Remove unused OSC1TIMER0 reset
- Remove debug_uart_init(). UART depends on clock driver setup, no point to call
  debug_uart_init() after spl_early_init() and clock driver initialization.
---
 arch/arm/mach-socfpga/Makefile |  3 +
 arch/arm/mach-socfpga/spl_agilex.c | 98 ++
 2 files changed, 101 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/spl_agilex.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index a403b46b47..81b6ffc675 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -58,6 +58,9 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += firewall.o
 obj-y  += spl_s10.o
 endif
+ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+obj-y  += spl_agilex.o
+endif
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/spl_agilex.c 
b/arch/arm/mach-socfpga/spl_agilex.c
new file mode 100644
index 00..c745d64114
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_agilex.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+   return BOOT_DEVICE_MMC1;
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(const u32 boot_device)
+{
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
+   return MMCSD_MODE_FS;
+#else
+   return MMCSD_MODE_RAW;
+#endif
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+   int ret;
+   struct udevice *dev;
+
+   ret = spl_early_init();
+   if (ret)
+   hang();
+
+   socfpga_get_managers_addr();
+
+#ifdef CONFIG_HW_WATCHDOG
+   /* Ensure watchdog is paused when debugging is happening */
+   writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
+  socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
+
+   /* Enable watchdog before initializing the HW */
+   socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
+   socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
+   hw_watchdog_init();
+#endif
+
+   /* ensure all processors are not released prior Linux boot */
+   writeq(0, CPU_RELEASE_ADDR);
+
+   timer_init();
+
+   sysmgr_pinmux_init();
+
+   ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+   if (ret) {
+   debug("Clock init failed: %d\n", ret);
+   hang();
+   }
+
+   preloader_console_init();
+   cm_print_clock_quick_summary();
+
+   firewall_setup();
+   ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
+   if (ret) {
+   debug("CCU init failed: %d\n", ret);
+   hang();
+   }
+
+#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
+   ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+   if (ret) {
+   debug("DRAM init failed: %d\n", ret);
+   hang();
+   }
+#endif
+
+   mbox_init();
+
+#ifdef CONFIG_CADENCE_QSPI
+   mbox_qspi_open();
+#endif
+}
-- 
2.19.0

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[U-Boot] [PATCH v8 04/19] arm: socfpga: agilex: Add reset manager support

2019-11-27 Thread Ley Foon Tan
Add reset manager support for Agilex.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v5:
- Remove reset_reset_manager_agilex.h and use reset_manager_soc64.h.

v3:
- Add reset_manager_soc64.h
- Convert to use defines instead of struct.
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index af57ab0a32..7844ad14cb 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -43,7 +43,8 @@ void socfpga_per_reset_all(void);
 #include 
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include 
-#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+   defined(CONFIG_TARGET_SOCFPGA_AGILEX)
 #include 
 #endif
 
-- 
2.19.0

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[U-Boot] [PATCH v8 09/19] clk: agilex: Add clock driver for Agilex

2019-11-27 Thread Ley Foon Tan
Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang 
Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v6:
- Use agilex-clock.h from Linux instead of using stratix10-clock.h.

v4:
- Get address from DT.

v3:
- Fixed clear PLL's lostlock bypass mode to ensure the clock manager provide 
glitchless clock
to downstream logic
- Changed CM_REG_CLRBITS(), CM_REG_SETBITS() and CM_REG_CLRSETBITS() macros
argument ordering, to match with clrbits_le32, setbits_le32 and clrsetbits_le32.
- Rename stratix10-clock.h to socfpga-soc64-clock.h.
- Convert struct to defines and move defines to clk-agilex.h

v2:
- Convert Clock driver to DM
---
 arch/arm/mach-socfpga/misc.c |   5 +
 drivers/clk/altera/Makefile  |   1 +
 drivers/clk/altera/clk-agilex.c  | 579 +++
 drivers/clk/altera/clk-agilex.h  | 237 ++
 include/dt-bindings/clock/agilex-clock.h |  71 +++
 5 files changed, 893 insertions(+)
 create mode 100644 drivers/clk/altera/clk-agilex.c
 create mode 100644 drivers/clk/altera/clk-agilex.h
 create mode 100644 include/dt-bindings/clock/agilex-clock.h

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 1c6a0032dd..c95d9f6f43 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -244,7 +244,12 @@ void socfpga_get_managers_addr(void)
if (ret)
hang();
 
+#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+   ret = socfpga_get_base_addr("intel,agilex-clkmgr",
+   &socfpga_clkmgr_base);
+#else
ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
+#endif
if (ret)
hang();
 }
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index a3ae8b24b0..96215ad5c4 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -3,4 +3,5 @@
 # Copyright (C) 2018 Marek Vasut 
 #
 
+obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
new file mode 100644
index 00..5fedec549d
--- /dev/null
+++ b/drivers/clk/altera/clk-agilex.c
@@ -0,0 +1,579 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_clk_platdata {
+   void __iomem *regs;
+};
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat, u32 
val)
+{
+   CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
+   cm_wait_for_fsm();
+}
+
+static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat, u32 val)
+{
+   CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
+   cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val)
+{
+   CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
+   cm_wait_for_fsm();
+}
+
+#define MEMBUS_MAINPLL 0
+#define MEMBUS_PERPLL  1
+#define MEMBUS_TIMEOUT 1000
+#define MEMBUS_ADDR_CLKSLICE   0x27
+#define MEMBUS_CLKSLICE_SYNC_MODE_EN   0x80
+
+static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll,
+  int timeout)
+{
+   int cnt = 0;
+   u32 req_status;
+
+   if (pll == MEMBUS_MAINPLL)
+   req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
+   else
+   req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
+
+   while ((cnt < timeout) && (req_status & CLKMGR_MEM_REQ_SET_MSK)) {
+   if (pll == MEMBUS_MAINPLL)
+   req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
+   else
+   req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
+   cnt++;
+   }
+
+   if (cnt >= timeout)
+   return -ETIMEDOUT;
+
+   return 0;
+}
+
+static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll,
+   u32 addr_offset, u32 wdat, int timeout)
+{
+   u32 addr;
+   u32 val;
+
+   addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);
+
+   val = (CLKMGR_MEM_REQ_SET_MSK | CLKMGR_MEM_WR_SET_MSK |
+  (wdat << CLKMGR_MEM_WDAT_LSB_OFFSET) | addr);
+
+   if (pll == MEMBUS_MAINPLL)
+   CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);
+   else
+   CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);
+
+   debug("MEMBUS: Write 0x%08x to addr = 0x%08x\n", wdat, addr);
+
+   return memb

[U-Boot] [PATCH v8 07/19] arm: socfpga: Move Stratix10 and Agilex clock manager common code

2019-11-27 Thread Ley Foon Tan
Move Stratix10 and Agilex clock manager common code to new header file.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v6:
- Move #include  to top of header file.

v5:
- Revert CLKMGR_INTOSC_HZ to 460MHz.
---
 .../include/mach/clock_manager_s10.h  | 16 +++--
 .../include/mach/clock_manager_soc64.h| 23 +++
 2 files changed, 26 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h

diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h 
b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index 13eb23569c..e710aa2f94 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -1,12 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0
  *
- * Copyright (C) 2016-2018 Intel Corporation 
+ * Copyright (C) 2016-2019 Intel Corporation 
  *
  */
 
 #ifndef_CLOCK_MANAGER_S10_
 #define_CLOCK_MANAGER_S10_
 
+#include 
+
 /* Clock speed accessors */
 unsigned long cm_get_mpu_clk_hz(void);
 unsigned long cm_get_sdram_clk_hz(void);
@@ -14,18 +16,6 @@ unsigned int cm_get_l4_sp_clk_hz(void);
 unsigned int cm_get_mmc_controller_clk_hz(void);
 unsigned int cm_get_qspi_controller_clk_hz(void);
 unsigned int cm_get_spi_controller_clk_hz(void);
-const unsigned int cm_get_osc_clk_hz(void);
-const unsigned int cm_get_f2s_per_ref_clk_hz(void);
-const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
-const unsigned int cm_get_intosc_clk_hz(void);
-const unsigned int cm_get_fpga_clk_hz(void);
-
-#define CLKMGR_EOSC1_HZ2500
-#define CLKMGR_INTOSC_HZ   46000
-#define CLKMGR_FPGA_CLK_HZ 5000
-
-/* Clock configuration accessors */
-const struct cm_config * const cm_get_default_config(void);
 
 struct cm_config {
/* main group */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h 
b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
new file mode 100644
index 00..3b4bb62ca5
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2016-2019 Intel Corporation 
+ *
+ */
+
+#ifndef _CLOCK_MANAGER_SOC64_
+#define _CLOCK_MANAGER_SOC64_
+
+const unsigned int cm_get_osc_clk_hz(void);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+const unsigned int cm_get_intosc_clk_hz(void);
+const unsigned int cm_get_fpga_clk_hz(void);
+
+#define CLKMGR_EOSC1_HZ2500
+#define CLKMGR_INTOSC_HZ   46000
+#define CLKMGR_FPGA_CLK_HZ 5000
+
+/* Clock configuration accessors */
+const struct cm_config * const cm_get_default_config(void);
+
+#endif /* _CLOCK_MANAGER_SOC64_ */
-- 
2.19.0

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[U-Boot] [PATCH v8 08/19] arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz

2019-11-27 Thread Ley Foon Tan
CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz.
Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v6:
- Remove unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ.
---
 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h 
b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
index 3b4bb62ca5..71fbaa7667 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
@@ -13,9 +13,7 @@ const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
 const unsigned int cm_get_intosc_clk_hz(void);
 const unsigned int cm_get_fpga_clk_hz(void);
 
-#define CLKMGR_EOSC1_HZ2500
-#define CLKMGR_INTOSC_HZ   46000
-#define CLKMGR_FPGA_CLK_HZ 5000
+#define CLKMGR_INTOSC_HZ   4
 
 /* Clock configuration accessors */
 const struct cm_config * const cm_get_default_config(void);
-- 
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[U-Boot] [PATCH v8 19/19] arm: socfpga: agilex: Enable Agilex SoC build

2019-11-27 Thread Ley Foon Tan
Add build support for Agilex SoC.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v7:
- Move CONFIG_DW_WDT_CLOCK_KHZ to _soc64_common.h
- Use fdtimage filename from CONFIG_DEFAULT_DEVICE_TREE

v6:
- Include socfpga_soc64_common.h.

v5:
- Enable NCORE_CACHE

v3:
- Disable CONFIG_USE_TINY_PRINTF

v2:
- Remove IC_CLK define, use clock DM method to get i2c clock
- Change CONFIG_ENV_SIZE to 4KB since CONFIG_SPI_FLASH_USE_4K_SECTORS is 
enabled.
---
 arch/arm/Kconfig   |  4 +-
 arch/arm/mach-socfpga/Kconfig  | 16 +++
 arch/arm/mach-socfpga/Makefile |  9 
 configs/socfpga_agilex_defconfig   | 60 ++
 include/configs/socfpga_agilex_socdk.h | 12 ++
 include/configs/socfpga_soc64_common.h |  6 ++-
 6 files changed, 104 insertions(+), 3 deletions(-)
 create mode 100644 configs/socfpga_agilex_defconfig
 create mode 100644 include/configs/socfpga_agilex_socdk.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f96841c777..563d0b7eb8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -905,7 +905,7 @@ config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select ARCH_EARLY_INIT_R
select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
-   select ARM64 if TARGET_SOCFPGA_STRATIX10
+   select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
select DM_SERIAL
@@ -917,7 +917,7 @@ config ARCH_SOCFPGA
select SPL_LIBGENERIC_SUPPORT
select SPL_NAND_SUPPORT if SPL_NAND_DENALI
select SPL_OF_CONTROL
-   select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
+   select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || 
TARGET_SOCFPGA_AGILEX
select SPL_SERIAL_SUPPORT
select SPL_SYSRESET
select SPL_WATCHDOG_SUPPORT
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 3770e07258..969698c83f 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -29,6 +29,15 @@ config SYS_TEXT_BASE
default 0x0140 if TARGET_SOCFPGA_ARRIA10
default 0x0140 if TARGET_SOCFPGA_GEN5
 
+config TARGET_SOCFPGA_AGILEX
+   bool
+   select ARMV8_MULTIENTRY
+   select ARMV8_SET_SMPEN
+   select ARMV8_SPIN_TABLE
+   select CLK
+   select NCORE_CACHE
+   select SPL_CLK if SPL
+
 config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
@@ -75,6 +84,10 @@ choice
prompt "Altera SOCFPGA board select"
optional
 
+config TARGET_SOCFPGA_AGILEX_SOCDK
+   bool "Intel SOCFPGA SoCDK (Agilex)"
+   select TARGET_SOCFPGA_AGILEX
+
 config TARGET_SOCFPGA_ARIES_MCVEVK
bool "Aries MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -135,6 +148,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
 endchoice
 
 config SYS_BOARD
+   default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -151,6 +165,7 @@ config SYS_BOARD
default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 
 config SYS_VENDOR
+   default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -168,6 +183,7 @@ config SYS_SOC
default "socfpga"
 
 config SYS_CONFIG_NAME
+   default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 81b6ffc675..418f543b20 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -41,6 +41,14 @@ endif
 
 ifdef CONFIG_TARGET_SOCFPGA_AGILEX
 obj-y  += clock_manager_agilex.o
+obj-y  += mailbox_s10.o
+obj-y  += misc_s10.o
+obj-y  += mmu-arm64_s10.o
+obj-y  += reset_manager_s10.o
+obj-y  += system_manager_s10.o
+obj-y  += timer_s10.o
+obj-y  += wrap_pinmux_config_s10.o
+obj-y  += wrap_pll_config_s10.o
 endif
 
 ifdef CONFIG_SPL_BUILD
@@ -59,6 +67,7 @@ obj-y += firewall.o
 obj-y  += spl_s10.o
 endif
 ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+obj-y  += firewall.o
 obj-y  += spl_agilex.o
 endif
 endif
diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
new file mode 100644
index 00..cdb93960d0
--- /dev/null
+++ b/configs/socfpga_agilex_defconfig
@@ -0,0 +1,60 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x200
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TAR

[U-Boot] [PATCH v8 11/19] cache: Add Arteris Ncore cache coherent unit driver

2019-11-27 Thread Ley Foon Tan
Add Cache Coherency Unit (CCU) driver.
CCU is to ensures consistency of shared data between multi masters
in the system.

Driver initializes CCU's directories and coherency agent
interfaces in CCU IP.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v5:
- Move CCU driver to DM.
---
 drivers/cache/Kconfig   |   8 ++
 drivers/cache/Makefile  |   1 +
 drivers/cache/cache-ncore.c | 164 
 3 files changed, 173 insertions(+)
 create mode 100644 drivers/cache/cache-ncore.c

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 629039e7a8..1e452ad6d9 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -31,4 +31,12 @@ config V5L2_CACHE
  It will configure tag and data ram timing control from the
  device tree and enable L2 cache.
 
+config NCORE_CACHE
+   bool "Arteris Ncore cache coherent unit driver"
+   select CACHE
+   help
+ This driver is for the Arteris Ncore cache coherent unit (CCU)
+ controller. The driver initializes cache directories and coherent
+ agent interfaces.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index c1f766cfca..6be895a5f7 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -2,4 +2,5 @@
 obj-$(CONFIG_$(SPL_)CACHE) += cache-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
+obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
 obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
diff --git a/drivers/cache/cache-ncore.c b/drivers/cache/cache-ncore.c
new file mode 100644
index 00..e3aca36071
--- /dev/null
+++ b/drivers/cache/cache-ncore.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ *
+ */
+#include 
+#include 
+
+#include 
+
+/* Directory */
+#define DIRUSFER   0x80010
+#define DIRUCASER0 0x80040
+#define DIRUSFMCR  0x80080
+#define DIRUSFMAR  0x80084
+
+#define DIRUSFMCR_SFID_SHIFT   16
+
+/* Coherent cache agent interface */
+#define CAIUIDR0x00ffc
+
+#define CAIUIDR_CA_GET(v)  (((v) & 0x8000) >> 15)
+#define CAIUIDR_TYPE_GET(v)(((v) & 0x000f) >> 16)
+#define CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT   0
+#define CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT   1
+
+/* Coherent subsystem */
+#define CSADSER0   0xff040
+#define CSUIDR 0x8
+#define CSIDR  0xc
+
+#define CSUIDR_NUMCAIUS_GET(v) (((v) & 0x007f) >> 0)
+#define CSUIDR_NUMDIRUS_GET(v) (((v) & 0x003f) >> 16)
+#define CSUIDR_NUMCMIUS_GET(v) (((v) & 0x3f00) >> 24)
+
+#define CSIDR_NUMSFS_GET(v)(((v) & 0x007c) >> 18)
+
+#define DIR_REG_SZ 0x1000
+#define CAIU_REG_SZ0x1000
+
+#define CCU_DIR_REG_ADDR(base, reg, dir)   \
+   ((base) + (reg) + ((dir) * DIR_REG_SZ))
+
+/* OCRAM firewall register */
+#define OCRAM_FW_010x100204
+#define OCRAM_SECURE_REGIONS   4
+
+#define OCRAM_PRIVILEGED_MASK  BIT(29)
+#define OCRAM_SECURE_MASK  BIT(30)
+
+static void ncore_ccu_init_dirs(void __iomem *base)
+{
+   ulong i, f;
+   int ret;
+   u32 num_of_dirs;
+   u32 num_of_snoop_filters;
+   u32 reg;
+
+   num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(base + CSUIDR));
+   num_of_snoop_filters =
+   CSIDR_NUMSFS_GET(readl(base + CSIDR)) + 1;
+
+   /* Initialize each snoop filter in each directory */
+   for (f = 0; f < num_of_snoop_filters; f++) {
+   reg = f << DIRUSFMCR_SFID_SHIFT;
+   for (i = 0; i < num_of_dirs; i++) {
+   /* Initialize all entries */
+   writel(reg, CCU_DIR_REG_ADDR(base, DIRUSFMCR, i));
+
+   /* Poll snoop filter maintenance operation active
+* bit become 0.
+*/
+   ret = wait_for_bit_le32((const void *)
+   CCU_DIR_REG_ADDR(base,
+DIRUSFMAR, i),
+   BIT(0), false, 1000, false);
+   if (ret) {
+   puts("CCU: Directory initialization failed!\n");
+   hang();
+   }
+
+   /* Enable snoop filter, a bit per snoop filter */
+   setbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i),
+BIT(f));
+   }
+   }
+}
+
+static void ncore_ccu_init_coh_agent(void __iomem *base)
+{
+   u32 num_of_coh_agent_intf;
+   u32 num_of_dirs;
+   u32 reg;
+   u32 type;
+   u32 i, dir;
+
+   num_of_coh_agent_intf =
+   CSUIDR_NUMCAIUS_GET(readl(base + CSUIDR));
+   num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(

[U-Boot] [PATCH v8 18/19] configs: socfpga: Move Stratix10 and Agilex common CONFIGs

2019-11-27 Thread Ley Foon Tan
Move Stratix10 and Agilex common CONFIGs to socfpga_soc64_common.h.

Signed-off-by: Ley Foon Tan 
---
 ...ratix10_socdk.h => socfpga_soc64_common.h} |   8 +-
 include/configs/socfpga_stratix10_socdk.h | 193 +-
 2 files changed, 7 insertions(+), 194 deletions(-)
 copy include/configs/{socfpga_stratix10_socdk.h => socfpga_soc64_common.h} 
(96%)

diff --git a/include/configs/socfpga_stratix10_socdk.h 
b/include/configs/socfpga_soc64_common.h
similarity index 96%
copy from include/configs/socfpga_stratix10_socdk.h
copy to include/configs/socfpga_soc64_common.h
index e8e66fa4ae..f69a55c191 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -1,11 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0
  *
- * Copyright (C) 2017-2018 Intel Corporation 
+ * Copyright (C) 2017-2019 Intel Corporation 
  *
  */
 
-#ifndef __CONFIG_SOCFGPA_STRATIX10_H__
-#define __CONFIG_SOCFGPA_STRATIX10_H__
+#ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
+#define __CONFIG_SOCFPGA_SOC64_COMMON_H__
 
 #include 
 #include 
@@ -196,4 +196,4 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
 
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */
diff --git a/include/configs/socfpga_stratix10_socdk.h 
b/include/configs/socfpga_stratix10_socdk.h
index e8e66fa4ae..09b46ba013 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -1,199 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0
  *
- * Copyright (C) 2017-2018 Intel Corporation 
+ * Copyright (C) 2017-2019 Intel Corporation 
  *
  */
 
 #ifndef __CONFIG_SOCFGPA_STRATIX10_H__
 #define __CONFIG_SOCFGPA_STRATIX10_H__
 
-#include 
-#include 
+#include 
 
-/*
- * U-Boot general configurations
- */
-#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE
-#define CONFIG_LOADADDR0x200
-#define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
-#define CONFIG_REMAKE_ELF
-/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
-#define CPU_RELEASE_ADDR   0xFFD12210
-#define CONFIG_SYS_CACHELINE_SIZE  64
-#define CONFIG_SYS_MEM_RESERVE_SECURE  0   /* using OCRAM, not DDR */
-
-/*
- * U-Boot console configurations
- */
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_SYS_CBSIZE  2048
-#define CONFIG_SYS_PBSIZE  (CONFIG_SYS_CBSIZE + \
-   sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE
-
-/* Extend size of kernel image for uncompression */
-#define CONFIG_SYS_BOOTM_LEN   (32 * 1024 * 1024)
-
-/*
- * U-Boot run time memory configurations
- */
-#define CONFIG_SYS_INIT_RAM_ADDR   0xFFE0
-#define CONFIG_SYS_INIT_RAM_SIZE   0x4
-#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_INIT_RAM_ADDR  \
-   + CONFIG_SYS_INIT_RAM_SIZE \
-   - S10_HANDOFF_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET  (CONFIG_SYS_INIT_SP_ADDR)
-#define CONFIG_SYS_MALLOC_LEN  (5 * 1024 * 1024)
-
-/*
- * U-Boot environment configurations
- */
-#define CONFIG_SYS_MMC_ENV_DEV 0   /* device 0 */
-
-/*
- * QSPI support
- */
- #ifdef CONFIG_CADENCE_QSPI
-/* Enable it if you want to use dual-stacked mode */
-/*#define CONFIG_QSPI_RBF_ADDR 0x72*/
-
-/* Flash device info */
-
-/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
-#endif /* CONFIG_SPL_BUILD */
-
-#ifndef __ASSEMBLY__
-unsigned int cm_get_qspi_controller_clk_hz(void);
-#define CONFIG_CQSPI_REF_CLK   cm_get_qspi_controller_clk_hz()
-#endif
-
-#endif /* CONFIG_CADENCE_QSPI */
-
-/*
- * Boot arguments passed to the boot command. The value of
- * CONFIG_BOOTARGS goes into the environment value "bootargs".
- * Do note the value will override also the chosen node in FDT blob.
- */
-#define CONFIG_BOOTARGS "earlycon"
-#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" 
\
-  "run mmcboot"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-   "bootfile=Image\0" \
-   "fdt_addr=800\0" \
-   "fdtimage=socfpga_stratix10_socdk.dtb\0" \
-   "mmcroot=/dev/mmcblk0p2\0" \
-   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-   " root=${mmcroot} rw rootwait;" \
-   "booti ${loadaddr} - ${fdt_addr}\0" \
-   "mmcload=mmc rescan;" \
-   "load mmc 0:1 ${loadaddr} ${bootfile};" \
-   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-   "linux_qspi_enable=if sf probe; then " \
-   "echo Enabling QSPI at Linux DTB...;" \

[U-Boot] [PATCH v8 17/19] arm: dts: agilex: Add base dtsi and devkit dts

2019-11-27 Thread Ley Foon Tan
Add device tree files for Agilex SoC platform.

socfpga_agilex-u-boot.dtsi and socfpga_agilex_socdk-u-boot.dts contains
Uboot specific DT properties.

socfpga_agilex.dtsi and socfpga_agilex_socdk.dts are from Linux
(kernel/git/dinguyen/linux.git, commit 6f0bf971bacacc)

Signed-off-by: Ley Foon Tan 

---
v8:
- Include socfpga_agilex-u-boot.dtsi in socfpga_agilex_socdk-u-boot.dtsi,
  instead of include it in socfpga_agilex_socdk.dts.

v7:
- Update socfpga_agilex.dtsi and socfpga_agilex_socdk.dts from Linux.
- Add new socfpga_agilex_socdk-u-boot.dts file for Uboot specific DT
  properties.

v6:
- Use new macro names from agilex-clock.h.

v5:
- Add CCU DT node.

v4:
- Add u-boot,dm-pre-reloc to sysmgr node.

v3:
- Fixed bank 1 memory alias base address to 0x28000.
- Rename STRATIX10_*_CLK to SOCFPGA_SOC64_*_CLK.
- Include socfpga-soc64-clock.h
- Change to "intel,sdr-ctl-agilex" for SDRAM node.

v2:
- Add clock property to device node.
- Change memory size to 8GB
- Enable i2c1
---
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/socfpga_agilex-u-boot.dtsi   |  96 +++
 arch/arm/dts/socfpga_agilex.dtsi  | 622 ++
 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi |  39 ++
 arch/arm/dts/socfpga_agilex_socdk.dts | 141 
 5 files changed, 899 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_agilex-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_agilex.dtsi
 create mode 100644 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_agilex_socdk.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d8846df1bd..e76f7c1407 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -328,6 +328,7 @@ dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=  \
+   socfpga_agilex_socdk.dtb\
socfpga_arria5_socdk.dtb\
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi 
b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
new file mode 100644
index 00..f0528a9ad9
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2019 Intel Corporation 
+ */
+
+/{
+   memory {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   u-boot,dm-pre-reloc;
+   };
+
+   soc {
+   u-boot,dm-pre-reloc;
+
+   ccu: cache-controller@f700 {
+   compatible = "arteris,ncore-ccu";
+   reg = <0xf700 0x100900>;
+   u-boot,dm-pre-reloc;
+   };
+   };
+};
+
+&clkmgr {
+   u-boot,dm-pre-reloc;
+};
+
+&gmac1 {
+   altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+};
+
+&gmac2 {
+   altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
+};
+
+&i2c0 {
+   reset-names = "i2c";
+};
+
+&i2c1 {
+   reset-names = "i2c";
+};
+
+&i2c2 {
+   reset-names = "i2c";
+};
+
+&i2c3 {
+   reset-names = "i2c";
+};
+
+&mmc {
+   resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
+};
+
+&porta {
+   bank-name = "porta";
+};
+
+&portb {
+   bank-name = "portb";
+};
+
+&qspi {
+   u-boot,dm-pre-reloc;
+};
+
+&rst {
+   compatible = "altr,rst-mgr";
+   altr,modrst-offset = <0x20>;
+   u-boot,dm-pre-reloc;
+};
+
+&sdr {
+   compatible = "intel,sdr-ctl-agilex";
+   reg = <0xf8000400 0x80>,
+ <0xf801 0x190>,
+ <0xf8011000 0x500>;
+   resets = <&rst DDRSCH_RESET>;
+   u-boot,dm-pre-reloc;
+};
+
+&sysmgr {
+   compatible = "altr,sys-mgr", "syscon";
+   u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+   u-boot,dm-pre-reloc;
+};
+
+&watchdog0 {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_agilex.dtsi
new file mode 100644
index 00..179b4d5591
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex.dtsi
@@ -0,0 +1,622 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+
+/dts-v1/;
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "intel,socfpga-agilex";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   reserved-memory {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   service_reserved: svcbuffer@0 {
+   compatible = "shared-dma-pool";
+   reg = <0x0 0x0 0x0 0x100>;
+   alignment = <0x1000>;
+   no-map;
+   };
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   compatible = "arm,cortex-a53";
+ 

[U-Boot] [PATCH v8 14/19] ddr: altera: agilex: Add SDRAM driver for Agilex

2019-11-27 Thread Ley Foon Tan
Add SDRAM driver for Agilex SoC.

Signed-off-by: Tien Fong Chee 
Signed-off-by: Ley Foon Tan 
Reviewed-by: Simon Goldschmidt 

---
v6:
- Add compatible "intel,sdr-ctl-agilex".

v4:
- Fixed checkpatch warnings

v3:
- Use sdmmc_soc64.*
- Change compatible string to use "intel" (intel,sdr-ctl-agilex).
- Improve error handing if DDR size mismatched.
---
 drivers/ddr/altera/Kconfig|   6 +-
 drivers/ddr/altera/Makefile   |   1 +
 drivers/ddr/altera/sdram_agilex.c | 168 ++
 drivers/ddr/altera/sdram_soc64.c  |   1 +
 drivers/ddr/altera/sdram_soc64.h  |   1 +
 5 files changed, 174 insertions(+), 3 deletions(-)
 create mode 100644 drivers/ddr/altera/sdram_agilex.c

diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 2b1c1be3b5..8f590dc5f6 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,8 +1,8 @@
 config SPL_ALTERA_SDRAM
bool "SoCFPGA DDR SDRAM driver in SPL"
depends on SPL
-   depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || 
TARGET_SOCFPGA_STRATIX10
-   select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
-   select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
+   depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || 
TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
+   select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || 
TARGET_SOCFPGA_AGILEX
+   select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || 
TARGET_SOCFPGA_AGILEX
help
  Enable DDR SDRAM controller for the SoCFPGA devices.
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index eb8da13b7d..39dfee5d5a 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -10,4 +10,5 @@ ifdef CONFIG_$(SPL_)ALTERA_SDRAM
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
 obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
+obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
 endif
diff --git a/drivers/ddr/altera/sdram_agilex.c 
b/drivers/ddr/altera/sdram_agilex.c
new file mode 100644
index 00..cc7679a6e4
--- /dev/null
+++ b/drivers/ddr/altera/sdram_agilex.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "sdram_soc64.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int sdram_mmr_init_full(struct udevice *dev)
+{
+   struct altera_sdram_platdata *plat = dev->platdata;
+   struct altera_sdram_priv *priv = dev_get_priv(dev);
+   u32 i;
+   int ret;
+   phys_size_t hw_size;
+   bd_t bd = {0};
+
+   /* Ensure HMC clock is running */
+   if (poll_hmc_clock_status()) {
+   debug("DDR: Error as HMC clock was not running\n");
+   return -EPERM;
+   }
+
+   /* Trying 3 times to do a calibration */
+   for (i = 0; i < 3; i++) {
+   ret = wait_for_bit_le32((const void *)(plat->hmc +
+   DDRCALSTAT),
+   DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
+   false);
+   if (!ret)
+   break;
+
+   emif_reset(plat);
+   }
+
+   if (ret) {
+   puts("DDR: Error as SDRAM calibration failed\n");
+   return -EPERM;
+   }
+   debug("DDR: Calibration success\n");
+
+   /*
+* Configure the DDR IO size
+* niosreserve0: Used to indicate DDR width &
+*  bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
+*  bit[8]   = 1 if user-mode OCT is present
+*  bit[9]   = 1 if warm reset compiled into EMIF Cal Code
+*  bit[10]  = 1 if warm reset is on during generation in EMIF Cal
+* niosreserve1: IP ADCDS version encoded as 16 bit value
+*  bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
+*  3=EAP, 4-6 are reserved)
+*  bit[5:3] = Service Pack # (e.g. 1)
+*  bit[9:6] = Minor Release #
+*  bit[14:10] = Major Release #
+*/
+   /* Configure DDR IO size x16, x32 and x64 mode */
+   u32 update_value;
+
+   update_value = hmc_readl(plat, NIOSRESERVED0);
+   update_value = (update_value & 0xFF) >> 5;
+
+   /* Configure DDR data rate 0-HAlf-rate 1-Quarter-rate */
+   update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4);
+   hmc_ecc_writel(plat, update_value, DDRIOCTRL);
+
+   /* Copy values MMR IOHMC dramaddrw to HMC adp DRAMADDRWIDTH */
+   hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
+
+   /* assigning the SDRAM size */
+   phys_size_t size = sdra

[U-Boot] GPT overlap on i.MX6

2019-11-27 Thread Jagan Teki
Hi,

I have created GPT table start from 8MB for kernel, roots etc.  something like

PartStart LBA   End LBA Name
Attributes
Type GUID
Partition GUID
  1 0x4000  0x00023fff  "boota"
attrs:  0x0004
type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
guid:   c12a7328-f81f-11d2-ba4b-00a0c93ec93b
  2 0x00024000  0x00043fff  "bootb"
attrs:  0x0004
type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
guid:   21686148-6449-6e6f-744e-656564454649
  3 0x00044000  0x00243fff  "rootfsa"
attrs:  0x
type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
guid:   b921b045-1df0-41c3-af44-4c6f280d3fae
  4 0x00244000  0x00443fff  "rootfsb"
attrs:  0x
type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
guid:   8da63339-0007-60c0-c436-083ac8230908
  5 0x00444000  0x0070bfde  "data"
attrs:  0x
type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
guid:   4f72ab70-69be-5948-81ff-4fc3daf24faa

I have not included SPL, U-Boot to the partition list since it start
from 0x400 in i.MX6. So
I'm writing SPL separately using fastboot(with offset) or ums.

But by doing this, the partition header seems overlapped so the output looks

GUID Partition Table Entry Array CRC is wrong: 0x6a1aba0a != 0x8e4fd548
find_valid_gpt: *** ERROR: Invalid GPT ***
find_valid_gpt: ***Using Backup GPT ***
PartStart LBA   End LBA Name
Attributes
Type GUID
Partition GUID
  1 0x4000  0x00023fff  "boota"
attrs:  0x0004
type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
guid:   c12a7328-f81f-11d2-ba4b-00a0c93ec93b
  2 0x00024000  0x00043fff  "bootb"
attrs:  0x0004
type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
guid:   21686148-6449-6e6f-744e-656564454649
  3 0x00044000  0x00243fff  "rootfsa"
attrs:  0x
type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
guid:   b921b045-1df0-41c3-af44-4c6f280d3fae
  4 0x00244000  0x00443fff  "rootfsb"
attrs:  0x
type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
guid:   8da63339-0007-60c0-c436-083ac8230908
  5 0x00444000  0x0070bfde  "data"
attrs:  0x
type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
guid:   4f72ab70-69be-5948-81ff-4fc3daf24faa

So, what I understand is If I create the GPT first and then write the
SPL, the SPL writing process will destroy the GPT Table and if I write
SPL first and then create GPT, the GPT creation process will destroy
the SPL.

Is there any way to fix this? I remember we can prevent this overlap
by preserving GPT Table som other or boot partition instead of having
them at the beginning by default.

Any inputs?

Jagan.
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Re: [U-Boot] [PATCH] board_f.c: Insure gd->new_bootstage alignment

2019-11-27 Thread Patrice CHOTARD
Hi Heinrich

On 11/26/19 6:41 PM, Heinrich Schuchardt wrote:
> On 11/26/19 1:16 PM, Patrick DELAUNAY wrote:
>> Hi,
>>
>>> From: Patrice CHOTARD 
>>> Sent: lundi 25 novembre 2019 14:48
>>>
>>> In reserve_bootstage(), in case size is odd, gd->new_bootstage is not 
>>> aligned. In
>>> bootstage_relocate(), the platform hangs when getting access to data-
 record[i].name.
>>> To avoid this issue, make gd->new_bootstage 16 byte aligned.
>>>
>>> Fixes: ac9cd4805c8b ("bootstage: Correct relocation algorithm")
>>>
>>> Signed-off-by: Patrice Chotard 
>>> Reviewed-by: Vikas MANOCHA 
>>> ---
>>
>> This patch is mandatory for stm32mp1 (ARM plaform with bootstage feature 
>> activated).
>>
>> Without this patch, the boot failed for v2020.01-rc3 (crash has struct 
>> pointer new_bootstage is not aligned).
>>
>> Reviewed-by: Patrick Delaunay 
>> Tested-by: Patrick Delaunay 
>>
>>>   common/board_f.c | 1 +
>>>   1 file changed, 1 insertion(+)
>>>
>>> diff --git a/common/board_f.c b/common/board_f.c index 
>>> e3591cbaeb..9cd4cfaf5f
>>> 100644
>>> --- a/common/board_f.c
>>> +++ b/common/board_f.c
>>> @@ -559,6 +559,7 @@ static int reserve_bootstage(void)
>>>   int size = bootstage_get_size();
>>>
>>>   gd->start_addr_sp -= size;
>>> +    gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp, 16);
>
> A comment in the code describing why this ALIGN_DOWN() is done would be
> helpful.

Ok i will add a comment about that.


>
> Is this value sufficient for all boards?

I simply reuse the same alignment already applied for other memory area :

    _ start_addr_sp in reserve_stacks()

    _ new_bloblist in reserve_bloblist()


Thanks

Patrice


>
> I found references for:
>
> x86_64 ABI: https://reviews.llvm.org/D30049: 16 bytes
> ARMv8: ARMv8 Instruction Set Overview: quad word, 16 bytes
>
> Best regards
>
> Heinrich
>
>>>   gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
>>>   debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
>>>     gd->start_addr_sp);
>>> -- 
>>> 2.17.1
>>
>> Thanks
>>
>> Patrick
>>
>
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[U-Boot] [PATCH v2] board_f.c: Insure gd->new_bootstage alignment

2019-11-27 Thread Patrice Chotard
In reserve_bootstage(), in case size is odd, gd->new_bootstage
is not aligned. In bootstage_relocate(), the platform hangs when
getting access to data->record[i].name.
To avoid this issue, make gd->new_bootstage 16 byte aligned.

To insure that new_bootstage is 16 byte aligned (at least needed for
x86_64 and ARMv8) and new_bootstage starts down to get enough space,
ALIGN_DOWN macro is used.

Fixes: ac9cd4805c8b ("bootstage: Correct relocation algorithm")

Signed-off-by: Patrice Chotard 
Reviewed-by: Vikas MANOCHA 


---

Changes in v2:
  - Update comment to explain the ALIGN_DOWN() usage.

 common/board_f.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/common/board_f.c b/common/board_f.c
index e3591cbaeb..d367f6b044 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -559,6 +559,11 @@ static int reserve_bootstage(void)
int size = bootstage_get_size();
 
gd->start_addr_sp -= size;
+   /*
+* Insure that start_addr_sp is aligned down to reserve enough
+* space for new_bootstage
+*/
+   gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp, 16);
gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
  gd->start_addr_sp);
-- 
2.17.1

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Re: [U-Boot] [PATCH v3 2/2] drivers: usb: host: Add BRCM xHCI driver

2019-11-27 Thread Marek Vasut
On 11/26/19 7:41 PM, Vladimir Olovyannikov wrote:
Hi,

[...]

> +#define USBAXI_AWCACHE   0xF
> +#define USBAXI_ARCACHE   0xF
> +#define USBAXI_AWPROT0x8
> +#define USBAXI_ARPROT0x8
> +#define USBAXIWR_SA_VAL  ((USBAXI_AWCACHE << 4) | USBAXI_AWPROT)
> +#define USBAXIWR_SA_MASK 0xFF
> +#define USBAXIWR_UA_VAL  (((USBAXI_AWCACHE << 4) | 
> USBAXI_AWPROT) << 16)

Maybe you can do "#define USBAXIWR_UA_VAL (USBAXIWR_SA_VAL << 16)" here?

> +#define USBAXIWR_UA_MASK (0xFF << 16)
> +#define USBAXIRD_SA_VAL  ((USBAXI_ARCACHE << 4) | USBAXI_ARPROT)
> +#define USBAXIRD_SA_MASK 0xFF
> +#define USBAXIRD_UA_VAL  (((USBAXI_ARCACHE << 4) | 
> USBAXI_ARPROT) << 16)

And here too ?

> +#define USBAXIRD_UA_MASK (0xFF << 16)

The masks are the same for RD and WR, maybe it makes sense to unify them
into one set of masks ?

> +struct brcm_xhci_platdata {
> + unsigned int arcache;
> + unsigned int awcache;
> +};
> +
> +static int xhci_brcm_probe(struct udevice *dev)
> +{
> + struct xhci_hccr *hcd;
> + struct xhci_hcor *hcor;
> + struct brcm_xhci_platdata *plat = dev_get_platdata(dev);
> + uintptr_t hc_base;
> + int len, ret = 0;
> +
> + if (!plat) {
> + dev_err(dev, "Can't get xHCI Plat data\n");
> + return -ENOMEM;
> + }
> +
> + hcd = dev_read_addr_ptr(dev);
> + if (!hcd) {
> + dev_err(dev, "Can't get the xHCI register base address\n");
> + return -ENXIO;
> + }
> +
> + hc_base = (uintptr_t)hcd;
> + len = HC_LENGTH(xhci_readl(&hcd->cr_capbase));
> + hcor = (struct xhci_hcor *)(hc_base + len);
> +
> + /* Save the default values of AXI read and write attributes */
> + plat->awcache = readl(hc_base + DRD2U3H_XHC_REGS_AXIWRA);
> + plat->arcache = readl(hc_base + DRD2U3H_XHC_REGS_AXIRDA);
> +
> + /* Enable AXI read and write attributes. */
> + clrsetbits_le32((hc_base + DRD2U3H_XHC_REGS_AXIWRA),
> ^
This one is unnecessary too. Please fix them globally.


> + (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK),

Here

> + (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL));

Here

> + clrsetbits_le32((hc_base + DRD2U3H_XHC_REGS_AXIRDA),

Here

> + (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK),

Here

> + (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL));

And here

[...]
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Re: [U-Boot] [PATCH v5 076/101] spi: ich: Add Apollo Lake support

2019-11-27 Thread Bin Meng
On Mon, Nov 25, 2019 at 12:12 PM Simon Glass  wrote:
>
> Add support for Apollo Lake to the ICH driver. This involves adjusting the
> mmio address and skipping setting of the bbar.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v5: None
> Changes in v4:
> - apollolake -> Apollo Lake
>
> Changes in v3: None
> Changes in v2: None
>
>  drivers/spi/ich.c | 19 ++-
>  drivers/spi/ich.h |  1 +
>  2 files changed, 15 insertions(+), 5 deletions(-)
>

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH v5 078/101] x86: Enable pinctrl in SPL and TPL

2019-11-27 Thread Bin Meng
Hi Simon,

On Mon, Nov 25, 2019 at 12:12 PM Simon Glass  wrote:
>
> If these phases are used we typically want to enable pinctrl in then, so
> that pad setup and GPIO access are possible.
>
> Signed-off-by: Simon Glass 
> ---
>
> Changes in v5:
> - Correct build error in chromebook_samus_tpl
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
>  arch/Kconfig   | 2 ++
>  configs/chromebook_samus_tpl_defconfig | 2 ++
>  2 files changed, 4 insertions(+)
>
> diff --git a/arch/Kconfig b/arch/Kconfig
> index 54de91afb3..ae9c93ed7b 100644
> --- a/arch/Kconfig
> +++ b/arch/Kconfig
> @@ -193,6 +193,7 @@ config X86
> imply SPL_OF_LIBFDT
> imply SPL_DRIVERS_MISC_SUPPORT
> imply SPL_GPIO_SUPPORT
> +   imply SPL_PINCTRL
> imply SPL_LIBCOMMON_SUPPORT
> imply SPL_LIBGENERIC_SUPPORT
> imply SPL_SERIAL_SUPPORT
> @@ -206,6 +207,7 @@ config X86
> imply TPL_DM
> imply TPL_DRIVERS_MISC_SUPPORT
> imply TPL_GPIO_SUPPORT
> +   imply TPL_PINCTRL
> imply TPL_LIBCOMMON_SUPPORT
> imply TPL_LIBGENERIC_SUPPORT
> imply TPL_SERIAL_SUPPORT
> diff --git a/configs/chromebook_samus_tpl_defconfig 
> b/configs/chromebook_samus_tpl_defconfig
> index fc6ceeac70..44e6d33181 100644
> --- a/configs/chromebook_samus_tpl_defconfig
> +++ b/configs/chromebook_samus_tpl_defconfig
> @@ -73,6 +73,8 @@ CONFIG_SYS_I2C_DW=y
>  CONFIG_TPL_MISC=y
>  CONFIG_CROS_EC=y
>  CONFIG_CROS_EC_LPC=y
> +# CONFIG_SPL_PINCTRL is not set
> +# CONFIG_TPL_PINCTRL is not set

If we have to disable these 2 options for Samus, I wonder why we imply
these 2 options in arch/Kconfig for x86?

And how about other x86 boards? Do they need unset these 2 options,
eg: QEMU x86_64?

>  CONFIG_SYS_NS16550=y
>  CONFIG_SOUND=y
>  CONFIG_SOUND_I8254=y
> --

Regards,
Bin
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[U-Boot] [PATCH v3] board_f.c: Insure gd->new_bootstage alignment

2019-11-27 Thread Patrice Chotard
In reserve_bootstage(), in case size is odd, gd->new_bootstage
is not aligned. In bootstage_relocate(), the platform hangs when
getting access to data->record[i].name.
To avoid this issue, make gd->new_bootstage 16 byte aligned.

To insure that new_bootstage is 16 byte aligned (at least needed for
x86_64 and ARMv8) and new_bootstage starts down to get enough space,
ALIGN_DOWN macro is used.

Fixes: ac9cd4805c8b ("bootstage: Correct relocation algorithm")

Signed-off-by: Patrice Chotard 
Reviewed-by: Vikas MANOCHA 
Reviewed-by: Patrick Delaunay 
Tested-by: Patrick Delaunay 

---

Changes in v3:
  - Add Patrick Reviewed-by and Tested-by.

Changes in v2:
  - Update comment to explain the ALIGN_DOWN() usage.

 common/board_f.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/common/board_f.c b/common/board_f.c
index e3591cbaeb..d367f6b044 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -559,6 +559,11 @@ static int reserve_bootstage(void)
int size = bootstage_get_size();
 
gd->start_addr_sp -= size;
+   /*
+* Insure that start_addr_sp is aligned down to reserve enough
+* space for new_bootstage
+*/
+   gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp, 16);
gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
  gd->start_addr_sp);
-- 
2.17.1

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Re: [U-Boot] [PATCH v2 2/3] env: Tidy up some of the env code

2019-11-27 Thread James Byrne

On 27/11/2019 05:52, AKASHI Takahiro wrote:

On Thu, Nov 21, 2019 at 02:32:47PM +, James Byrne wrote:

This commit tidies up a few things in the env code to make it safer and
easier to extend:

- The hsearch_r() function took a 'struct env_entry' as its first
parameter, but only used the 'key' and 'data' fields. Some callers would
set the other fields, others would leave them undefined. Another
disadvantage was that the struct 'data' member is a 'char *', but this
function does not modify it, so it should be 'const char *'. To resolve
these issues the function now takes explcit 'key' and 'data' parameters
that are 'const char *', and all the callers have been modified.


I don't have a strong opinion here, but we'd rather maintain the current
interface. Yes, currently no users use any fields other than key/data,
but in the future, this function may be extended to accept additional
*search* parameters in a key, say flag?. At that time, we won't have to
change the interface again.


As I said in my commit log comment, there are two key arguments against 
this:


- The fact that the 'data' member of 'struct env_entry' is a 'char *' is 
really inconvenient because this is a read-only function where most of 
the callers should be using 'const char *' pointers, and having to cast 
away the constness isn't good practice and makes the calling code less 
readable.


- As you can see from the calling code I've had to tidy up, the callers 
were very inconsistent about whether they bothered to initialise any 
fields other than 'key' and 'value', so if you ever wanted to extend the 
interface to check other parameters you'd have to go around and fix them 
all up anyway to avoid unpredictable behaviour.


Given that only 'key' and 'value' are used at the moment I think my 
change is preferable because it makes it explicit what is being used and 
avoids any nasty surprises you might get if you changed hsearch_r() 
without changing all the callers. If you anticipate wanting to match on 
other fields, it might be better to define an alternative query 
structure using 'const char *' pointers for key and value, then extend 
that, but I would argue that that's something you could do at the point 
you find it is needed rather than now.


Regards,

James
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Re: [U-Boot] [PATCH v3 06/22] ram: rockchip: add common code for sdram driver

2019-11-27 Thread Jagan Teki
Hi Kever/YouMin,

On Fri, Nov 15, 2019 at 8:43 AM Kever Yang  wrote:
>
> There are some function like os_reg setting, capacity detect functions,
> can be used as common code for different Rockchip SoCs, add a
> sdram_common.c for all these functions.
>
> Signed-off-by: YouMin Chen 
> Signed-off-by: Kever Yang 
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  .../include/asm/arch-rockchip/sdram_common.h  |  31 ++
>  drivers/ram/rockchip/Kconfig  |   6 +
>  drivers/ram/rockchip/Makefile |   1 +
>  drivers/ram/rockchip/sdram_common.c   | 285 ++
>  4 files changed, 323 insertions(+)
>  create mode 100644 drivers/ram/rockchip/sdram_common.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h 
> b/arch/arm/include/asm/arch-rockchip/sdram_common.h
> index cd3d7f97d8..36d31156be 100644
> --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
> +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
> @@ -6,6 +6,15 @@
>  #ifndef _ASM_ARCH_SDRAM_COMMON_H
>  #define _ASM_ARCH_SDRAM_COMMON_H
>
> +#ifndef MHZ
> +#define MHZ(1000 * 1000)
> +#endif
> +
> +#define PATTERN(0x5aa5f00f)
> +
> +#define MIN(a, b)  (((a) > (b)) ? (b) : (a))
> +#define MAX(a, b)  (((a) > (b)) ? (a) : (b))
> +
>  struct sdram_cap_info {
> unsigned int rank;
> /* dram column number, 0 means this channel is invalid */
> @@ -125,4 +134,26 @@ void sdram_print_ddr_info(struct sdram_cap_info 
> *cap_info,
>  void sdram_print_stride(unsigned int stride);
>  #endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
>
> +void sdram_org_config(struct sdram_cap_info *cap_info,
> + struct sdram_base_params *base,
> + u32 *p_os_reg2, u32 *p_os_reg3, u32 channel);
> +
> +int sdram_detect_bw(struct sdram_cap_info *cap_info);
> +int sdram_detect_cs(struct sdram_cap_info *cap_info);
> +int sdram_detect_col(struct sdram_cap_info *cap_info,
> +u32 coltmp);
> +int sdram_detect_bank(struct sdram_cap_info *cap_info,
> + u32 coltmp, u32 bktmp);
> +int sdram_detect_bg(struct sdram_cap_info *cap_info,
> +   u32 coltmp);
> +int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type);
> +int sdram_detect_row(struct sdram_cap_info *cap_info,
> +u32 coltmp, u32 bktmp, u32 rowtmp);
> +int sdram_detect_row_3_4(struct sdram_cap_info *cap_info,
> +u32 coltmp, u32 bktmp);
> +int sdram_detect_high_row(struct sdram_cap_info *cap_info);
> +int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type);
> +u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type);
> +void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n);
> +
>  #endif
> diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig
> index 4f274e01b3..dcc06b3fd3 100644
> --- a/drivers/ram/rockchip/Kconfig
> +++ b/drivers/ram/rockchip/Kconfig
> @@ -5,6 +5,12 @@ config RAM_ROCKCHIP
> help
>   This enables support for ram drivers Rockchip SoCs.
>
> +config ROCKCHIP_SDRAM_COMMON
> +   bool "Enable rockchip sdram common driver"
> +   depends on TPL_RAM || SPL_RAM
> +   help
> + This enable sdram common driver
> +
>  if RAM_ROCKCHIP
>
>  config RAM_ROCKCHIP_DEBUG
> diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
> index feb1f82d00..2f90f4088e 100644
> --- a/drivers/ram/rockchip/Makefile
> +++ b/drivers/ram/rockchip/Makefile
> @@ -11,3 +11,4 @@ obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
>  obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
>  obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o
>  obj-$(CONFIG_RAM_RK3399) += sdram_rk3399.o
> +obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o
> diff --git a/drivers/ram/rockchip/sdram_common.c 
> b/drivers/ram/rockchip/sdram_common.c
> new file mode 100644
> index 00..3f0e1d9a42
> --- /dev/null
> +++ b/drivers/ram/rockchip/sdram_common.c
> @@ -0,0 +1,285 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* n: Unit bytes */
> +void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n)
> +{
> +   int i;
> +
> +   for (i = 0; i < n / sizeof(u32); i++) {
> +   writel(*src, dest);
> +   src++;
> +   dest++;
> +   }
> +}
> +
> +void sdram_org_config(struct sdram_cap_info *cap_info,
> + struct sdram_base_params *base,
> + u32 *p_os_reg2, u32 *p_os_reg3, u32 channel)
> +{
> +   *p_os_reg2 |= SYS_REG_ENC_DDRTYPE(base->dramtype);
> +   *p_os_reg2 |= SYS_REG_ENC_NUM_CH(base->num_channels);
> +
> +   *p_os_reg2 |= SYS_REG_ENC_ROW_3_4(cap_info->row_3_4, channel);
> +   *p_os_reg2 |= SYS_REG_ENC_CHINFO(channel);
> +   *p_os_reg2 |= SYS_REG_ENC_RANK(cap_info->rank, channel)

Re: [U-Boot] [PATCH v2 2/3] env: Tidy up some of the env code

2019-11-27 Thread Simon Goldschmidt
On Wed, Nov 27, 2019 at 10:39 AM James Byrne
 wrote:
>
> On 27/11/2019 05:52, AKASHI Takahiro wrote:
> > On Thu, Nov 21, 2019 at 02:32:47PM +, James Byrne wrote:
> >> This commit tidies up a few things in the env code to make it safer and
> >> easier to extend:
> >>
> >> - The hsearch_r() function took a 'struct env_entry' as its first
> >> parameter, but only used the 'key' and 'data' fields. Some callers would
> >> set the other fields, others would leave them undefined. Another
> >> disadvantage was that the struct 'data' member is a 'char *', but this
> >> function does not modify it, so it should be 'const char *'. To resolve
> >> these issues the function now takes explcit 'key' and 'data' parameters
> >> that are 'const char *', and all the callers have been modified.
> >
> > I don't have a strong opinion here, but we'd rather maintain the current
> > interface. Yes, currently no users use any fields other than key/data,
> > but in the future, this function may be extended to accept additional
> > *search* parameters in a key, say flag?. At that time, we won't have to
> > change the interface again.
>
> As I said in my commit log comment, there are two key arguments against
> this:
>
> - The fact that the 'data' member of 'struct env_entry' is a 'char *' is
> really inconvenient because this is a read-only function where most of
> the callers should be using 'const char *' pointers, and having to cast
> away the constness isn't good practice and makes the calling code less
> readable.
>
> - As you can see from the calling code I've had to tidy up, the callers
> were very inconsistent about whether they bothered to initialise any
> fields other than 'key' and 'value', so if you ever wanted to extend the
> interface to check other parameters you'd have to go around and fix them
> all up anyway to avoid unpredictable behaviour.
>
> Given that only 'key' and 'value' are used at the moment I think my
> change is preferable because it makes it explicit what is being used and
> avoids any nasty surprises you might get if you changed hsearch_r()
> without changing all the callers. If you anticipate wanting to match on
> other fields, it might be better to define an alternative query
> structure using 'const char *' pointers for key and value, then extend
> that, but I would argue that that's something you could do at the point
> you find it is needed rather than now.

Also, if you add fields without changing the callers to initialize those
new fields, wouldn't you get unpredictive results given that struct env_entry
is often allocated on the stack?

In that case, it might be better to change the signature of hsearch_r() so you
get compiler errors in places that aren't adapted.

Regards,
Simon

>
> Regards,
>
> James
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[U-Boot] [PATCH 1/5] Revert "powerpc: mpc85xx: delete FSL_SATA for T2080QDS board."

2019-11-27 Thread Peng Ma
This reverts commit 856b9cdb53f0e6c8d98f81cf71ef363c16b0aa0e.

Signed-off-by: Peng Ma 
---
 arch/powerpc/cpu/mpc85xx/Kconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 8cc82f80b4..6fc6ea8fef 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -352,6 +352,7 @@ config TARGET_T2080QDS
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
select FSL_DDR_INTERACTIVE
+   imply CMD_SATA
 
 config TARGET_T2080RDB
bool "Support T2080RDB"
@@ -360,7 +361,6 @@ config TARGET_T2080RDB
select SUPPORT_SPL
select PHYS_64BIT
imply CMD_SATA
-   imply FSL_SATA
imply PANIC_HANG
 
 config TARGET_T2081QDS
@@ -1099,8 +1099,10 @@ config ARCH_T2080
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
select FSL_IFC
+   imply CMD_SATA
imply CMD_NAND
imply CMD_REGINFO
+   imply FSL_SATA
 
 config ARCH_T2081
bool
-- 
2.17.1

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[U-Boot] [PATCH 3/5] arch: powerpc: Rewrite the sata node to fit the driver

2019-11-27 Thread Peng Ma
The sata of our powerpc platform are updated. This changed is to
fit the driver init

Signed-off-by: Peng Ma 
---
 arch/powerpc/dts/t2080.dtsi | 15 ---
 1 file changed, 4 insertions(+), 11 deletions(-)

diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi
index 999fa8cec4..458019ae92 100644
--- a/arch/powerpc/dts/t2080.dtsi
+++ b/arch/powerpc/dts/t2080.dtsi
@@ -88,20 +88,13 @@
phy_type = "utmi";
};
 
-   sata0: sata@22 {
+   sata: sata@22 {
compatible = "fsl,pq-sata-v2";
reg = <0x22 0x1000>;
interrupts = <68 0x2 0 0>;
-   sata-number = <0x0>;
-   sata-fpdma = <0x0>;
-   };
-
-   sata1: sata@221000 {
-   compatible = "fsl,pq-sata-v2";
-   reg = <0x221000 0x1000>;
-   interrupts = <69 0x2 0 0>;
-   sata-number = <0x0>;
-   sata-fpdma = <0x0>;
+   sata-offset = <0x1000>;
+   sata-number = <2>;
+   sata-fpdma = <0>;
};
};
 
-- 
2.17.1

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[U-Boot] [PATCH 2/5] Revert "ata: fsl_ahci: Add sata DM support for Freescale powerpc socs"

2019-11-27 Thread Peng Ma
This reverts commit 1ee494291880fd51ef0c5f7342e072bdb069d7ff.

Signed-off-by: Peng Ma 
---
 drivers/ata/Kconfig|   10 -
 drivers/ata/Makefile   |1 -
 drivers/ata/fsl_ahci.c | 1030 
 drivers/ata/fsl_sata.h |1 -
 4 files changed, 1042 deletions(-)
 delete mode 100644 drivers/ata/fsl_ahci.c

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index fe589d3aa8..d8c9756c2a 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -59,16 +59,6 @@ config DWC_AHCI
  Enable this driver to support Sata devices through
  Synopsys DWC AHCI module.
 
-config FSL_AHCI
-   bool "Enable Freescale AHCI driver support"
-   select SCSI_AHCI
-   depends on AHCI
-   depends on DM_SCSI
-   help
- Enable this driver to support Sata devices found in
- some Freescale PowerPC SoCs.
-
-
 config DWC_AHSATA
bool "Enable DWC AHSATA driver support"
select LIBATA
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 6e03384f81..a69edb10f7 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -4,7 +4,6 @@
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 
 obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o
-obj-$(CONFIG_FSL_AHCI) += fsl_ahci.o
 obj-$(CONFIG_AHCI) += ahci-uclass.o
 obj-$(CONFIG_AHCI_PCI) += ahci-pci.o
 obj-$(CONFIG_SCSI_AHCI) += ahci.o
diff --git a/drivers/ata/fsl_ahci.c b/drivers/ata/fsl_ahci.c
deleted file mode 100644
index d04cff3ee7..00
--- a/drivers/ata/fsl_ahci.c
+++ /dev/null
@@ -1,1030 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * NXP PPC SATA platform driver
- *
- * (C) Copyright 2019 NXP, Inc.
- *
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "fsl_sata.h"
-
-struct fsl_ahci_priv {
-   u32 base;
-   u32 flag;
-   u32 number;
-   fsl_sata_t *fsl_sata;
-};
-
-static int fsl_ahci_bind(struct udevice *dev)
-{
-   return device_bind_driver(dev, "fsl_ahci_scsi", "fsl_ahci_scsi", NULL);
-}
-
-static int fsl_ahci_ofdata_to_platdata(struct udevice *dev)
-{
-   struct fsl_ahci_priv *priv = dev_get_priv(dev);
-
-   priv->number = dev_read_u32_default(dev, "sata-number", -1);
-   priv->flag = dev_read_u32_default(dev, "sata-fpdma", -1);
-
-   priv->base = dev_read_addr(dev);
-   if (priv->base == FDT_ADDR_T_NONE)
-   return -EINVAL;
-
-   return 0;
-}
-
-static int ata_wait_register(unsigned __iomem *addr, u32 mask,
-u32 val, u32 timeout_msec)
-{
-   int i;
-
-   for (i = 0; ((in_le32(addr) & mask) != val) && i < timeout_msec; i++)
-   mdelay(1);
-
-   return (i < timeout_msec) ? 0 : -1;
-}
-
-static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
-{
-   printf("Status FIS dump:\n\r");
-   printf("fis_type:   %02x\n\r", s->fis_type);
-   printf("pm_port_i:  %02x\n\r", s->pm_port_i);
-   printf("status: %02x\n\r", s->status);
-   printf("error:  %02x\n\r", s->error);
-   printf("lba_low:%02x\n\r", s->lba_low);
-   printf("lba_mid:%02x\n\r", s->lba_mid);
-   printf("lba_high:   %02x\n\r", s->lba_high);
-   printf("device: %02x\n\r", s->device);
-   printf("lba_low_exp:%02x\n\r", s->lba_low_exp);
-   printf("lba_mid_exp:%02x\n\r", s->lba_mid_exp);
-   printf("lba_high_exp:   %02x\n\r", s->lba_high_exp);
-   printf("res1:   %02x\n\r", s->res1);
-   printf("sector_count:   %02x\n\r", s->sector_count);
-   printf("sector_count_exp:   %02x\n\r", s->sector_count_exp);
-}
-
-static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg)
-{
-   printf("\n\rSATA:   %08x\n\r", (u32)reg);
-   printf("CQR:%08x\n\r", in_le32(®->cqr));
-   printf("CAR:%08x\n\r", in_le32(®->car));
-   printf("CCR:%08x\n\r", in_le32(®->ccr));
-   printf("CER:%08x\n\r", in_le32(®->cer));
-   printf("CQR:%08x\n\r", in_le32(®->cqr));
-   printf("DER:%08x\n\r", in_le32(®->der));
-   printf("CHBA:   %08x\n\r", in_le32(®->chba));
-   printf("HStatus:%08x\n\r", in_le32(®->hstatus));
-   printf("HControl:   %08x\n\r", in_le32(®->hcontrol));
-   printf("CQPMP:  %08x\n\r", in_le32(®->cqpmp));
-   printf("SIG:%08x\n\r", in_le32(®->sig));
-   printf("ICC:%08x\n\r", in_le32(®->icc));
-   printf("SStatus:%08x\n\r", in_le32(®->sstatus));
-   printf("SError: %08x\n\r", in_le32(®->serror));
-   printf("SControl:   %08x\n\r", in_le32(®->scontrol));
-   printf("SNotification:  %08x\n\r", in_le32(®->snotification));
-   printf("TransCfg:   %08x\n\r", in_le32(®->transcfg));
-  

[U-Boot] [PATCH 5/5] ata: fsl_sata: Update fsl sata header file

2019-11-27 Thread Peng Ma
The variable(dma_flag) will be used by both fsl_ahci.c and fsl_sata.c,
Now we support the fsl_sata.c to DM mode and revert fsl_ahci.c(This
variable declare here). So we should Add this changed.

Signed-off-by: Peng Ma 
---
 drivers/ata/fsl_sata.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/ata/fsl_sata.h b/drivers/ata/fsl_sata.h
index 882803c8cd..5b9daa79e0 100644
--- a/drivers/ata/fsl_sata.h
+++ b/drivers/ata/fsl_sata.h
@@ -313,6 +313,7 @@ typedef struct fsl_sata {
int wcache;
int flush;
int flush_ext;
+   u32 dma_flag;
 } fsl_sata_t;
 
 #define READ_CMD   0
-- 
2.17.1

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[U-Boot] [PATCH 4/5] Revert "configs: enable sata device module in T2080QDS"

2019-11-27 Thread Peng Ma
This reverts commit 02dc1599ba0b16eb21ba0c206e5b6f38fe7b67a7
Just reverts some configs about sata to fit fsl_sata.c

Signed-off-by: Peng Ma 
---
 configs/T2080QDS_NAND_defconfig   | 4 
 configs/T2080QDS_SDCARD_defconfig | 4 
 configs/T2080QDS_SECURE_BOOT_defconfig| 4 
 configs/T2080QDS_SPIFLASH_defconfig   | 4 
 configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 4 
 configs/T2080QDS_defconfig| 4 
 6 files changed, 24 deletions(-)

diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 44f0e6c9b6..0b169e4b4e 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -9,7 +9,6 @@ CONFIG_ENV_OFFSET=0x14
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_CUSTOM_LDSCRIPT=y
 CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@@ -47,7 +46,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_DM=y
-CONFIG_FSL_AHCI=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -72,8 +70,6 @@ CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080QDS_SDCARD_defconfig 
b/configs/T2080QDS_SDCARD_defconfig
index e41c005a04..988ffb7e40 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -10,7 +10,6 @@ CONFIG_ENV_OFFSET=0x10
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -45,7 +44,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
-CONFIG_FSL_AHCI=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -69,8 +67,6 @@ CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig 
b/configs/T2080QDS_SECURE_BOOT_defconfig
index f7f59a7a9d..73616d383e 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -5,7 +5,6 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -33,7 +32,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
-CONFIG_FSL_AHCI=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
@@ -56,8 +54,6 @@ CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig 
b/configs/T2080QDS_SPIFLASH_defconfig
index 56d6c241e3..46d2806dc0 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -12,7 +12,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
-CONFIG_AHCI=y
 CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -48,7 +47,6 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_ADDR=0xFFFC9000
 CONFIG_DM=y
-CONFIG_FSL_AHCI=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -72,8 +70,6 @@ CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig 
b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index a1cef08b6e..b9211dbf30 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -4,7 +4,6 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_AHCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -30,7 +29,6 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_IS_IN_REMOTE=y
 CONFIG_ENV_ADDR=0xFFE2
 CONFIG_DM=y
-CONFIG_FSL_AHCI=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC=y
@@ -49,8 +47,6 @@ CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_FSL_ESPI=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 7d7179d4fc..a714c653c1 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -5,7 +5,6 @@ CONFIG_ENV_SECT_SIZE=0x2
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_AHCI=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
@@ -33,7 +32,6 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_IS_IN_FL

[U-Boot] [PATCH 1/2] rockchip: px30: Fixup PMUGRF registers layout order

2019-11-27 Thread Paul Kocialkowski
According to the PX30 TRM, the iomux registers come first, before the pull
and strength control registers.

Signed-off-by: Paul Kocialkowski 
---
 arch/arm/include/asm/arch-rockchip/grf_px30.h | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_px30.h 
b/arch/arm/include/asm/arch-rockchip/grf_px30.h
index c167bb42fac9..3d2a8770322e 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_px30.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_px30.h
@@ -112,18 +112,18 @@ struct px30_grf {
 check_member(px30_grf, mac_con1, 0x904);
 
 struct px30_pmugrf {
-   unsigned int gpio0a_e;
-   unsigned int gpio0b_e;
-   unsigned int gpio0c_e;
-   unsigned int gpio0d_e;
-   unsigned int gpio0a_p;
-   unsigned int gpio0b_p;
-   unsigned int gpio0c_p;
-   unsigned int gpio0d_p;
unsigned int gpio0al_iomux;
unsigned int gpio0bl_iomux;
unsigned int gpio0cl_iomux;
unsigned int gpio0dl_iomux;
+   unsigned int gpio0a_p;
+   unsigned int gpio0b_p;
+   unsigned int gpio0c_p;
+   unsigned int gpio0d_p;
+   unsigned int gpio0a_e;
+   unsigned int gpio0b_e;
+   unsigned int gpio0c_e;
+   unsigned int gpio0d_e;
unsigned int gpio0l_sr;
unsigned int gpio0h_sr;
unsigned int gpio0l_smt;
-- 
2.24.0

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[U-Boot] [PATCH 2/2] rockchip: px30: Add support for using UART3 as debug UART

2019-11-27 Thread Paul Kocialkowski
Some generic PX30 SoMs found in the wild use UART3 as their debug output
instead of UART2 (used for MMC) and UART5.

Make it possible to use UART3 as early debug output, with the associated
clock and pinmux configuration. Two sets of output pins are supported (M0/M1)
so a Kconfig option to select between the two is introduced like it's done
for UART2.

Future users should also note that the pinmux default in the dts is to use
the M1 pins while the Kconfig option takes M0 as a default.

Signed-off-by: Paul Kocialkowski 
---
 arch/arm/include/asm/arch-rockchip/cru_px30.h | 19 +
 arch/arm/mach-rockchip/px30/Kconfig   |  9 +++
 arch/arm/mach-rockchip/px30/px30.c| 77 +++
 3 files changed, 105 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru_px30.h 
b/arch/arm/include/asm/arch-rockchip/cru_px30.h
index 7d9fd181aca2..798444ae49f5 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_px30.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_px30.h
@@ -357,6 +357,25 @@ enum {
UART2_DIVNP5_SHIFT  = 0,
UART2_DIVNP5_MASK   = 0x1f << UART2_DIVNP5_SHIFT,
 
+   /* CRU_CLK_SEL40_CON */
+   UART3_PLL_SEL_SHIFT = 14,
+   UART3_PLL_SEL_MASK  = 3 << UART3_PLL_SEL_SHIFT,
+   UART3_PLL_SEL_GPLL  = 0,
+   UART3_PLL_SEL_24M,
+   UART3_PLL_SEL_480M,
+   UART3_PLL_SEL_NPLL,
+   UART3_DIV_CON_SHIFT = 0,
+   UART3_DIV_CON_MASK  = 0x1f << UART3_DIV_CON_SHIFT,
+
+   /* CRU_CLK_SEL41_CON */
+   UART3_CLK_SEL_SHIFT = 14,
+   UART3_CLK_SEL_MASK  = 3 << UART3_PLL_SEL_SHIFT,
+   UART3_CLK_SEL_UART3 = 0,
+   UART3_CLK_SEL_UART3_NP5,
+   UART3_CLK_SEL_UART3_FRAC,
+   UART3_DIVNP5_SHIFT  = 0,
+   UART3_DIVNP5_MASK   = 0x1f << UART3_DIVNP5_SHIFT,
+
/* CRU_CLK_SEL46_CON */
UART5_PLL_SEL_SHIFT = 14,
UART5_PLL_SEL_MASK  = 3 << UART5_PLL_SEL_SHIFT,
diff --git a/arch/arm/mach-rockchip/px30/Kconfig 
b/arch/arm/mach-rockchip/px30/Kconfig
index 109a37be15ad..167517bbd63f 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -36,6 +36,15 @@ config DEBUG_UART2_CHANNEL
  For using the UART for early debugging the route to use needs
  to be declared (0 or 1).
 
+config DEBUG_UART3_CHANNEL
+   int "Mux channel to use for debug UART3"
+   depends on DEBUG_UART_BOARD_INIT
+   default 0
+   help
+ UART3 can use two different set of pins to route the output.
+ For using the UART for early debugging the route to use needs
+ to be declared (0 or 1).
+
 source "board/rockchip/evb_px30/Kconfig"
 
 endif
diff --git a/arch/arm/mach-rockchip/px30/px30.c 
b/arch/arm/mach-rockchip/px30/px30.c
index bacdcc0b938d..6b12f4f6a502 100644
--- a/arch/arm/mach-rockchip/px30/px30.c
+++ b/arch/arm/mach-rockchip/px30/px30.c
@@ -37,6 +37,7 @@ static struct mm_region px30_mem_map[] = {
 struct mm_region *mem_map = px30_mem_map;
 
 #define PMU_PWRDN_CON  0xff18
+#define PMUGRF_BASE0xff01
 #define GRF_BASE   0xff14
 #define CRU_BASE   0xff2b
 #define VIDEO_PHY_BASE 0xff2e
@@ -49,6 +50,23 @@ struct mm_region *mem_map = px30_mem_map;
 
 #define QOS_PRIORITY_LEVEL(h, l)   h) & 3) << 8) | ((l) & 3))
 
+/* GRF_GPIO1BH_IOMUX */
+enum {
+   GPIO1B7_SHIFT   = 12,
+   GPIO1B7_MASK= 0xf << GPIO1B7_SHIFT,
+   GPIO1B7_GPIO= 0,
+   GPIO1B7_FLASH_RDN,
+   GPIO1B7_UART3_RXM1,
+   GPIO1B7_SPI0_CLK,
+
+   GPIO1B6_SHIFT   = 8,
+   GPIO1B6_MASK= 0xf << GPIO1B6_SHIFT,
+   GPIO1B6_GPIO= 0,
+   GPIO1B6_FLASH_CS1,
+   GPIO1B6_UART3_TXM1,
+   GPIO1B6_SPI0_CSN,
+};
+
 /* GRF_GPIO1CL_IOMUX */
 enum {
GPIO1C1_SHIFT   = 4,
@@ -128,6 +146,23 @@ enum {
GPIO3A1_UART5_RX= 4,
 };
 
+/* PMUGRF_GPIO0CL_IOMUX */
+enum {
+   GPIO0C1_SHIFT   = 2,
+   GPIO0C1_MASK= 0x3 << GPIO0C1_SHIFT,
+   GPIO0C1_GPIO= 0,
+   GPIO0C1_PWM_3,
+   GPIO0C1_UART3_RXM0,
+   GPIO0C1_PMU_DEBUG4,
+
+   GPIO0C0_SHIFT   = 0,
+   GPIO0C0_MASK= 0x3 << GPIO0C0_SHIFT,
+   GPIO0C0_GPIO= 0,
+   GPIO0C0_PWM_1,
+   GPIO0C0_UART3_TXM0,
+   GPIO0C0_PMU_DEBUG3,
+};
+
 int arch_cpu_init(void)
 {
static struct px30_grf * const grf = (void *)GRF_BASE;
@@ -175,6 +210,11 @@ int arch_cpu_init(void)
 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 void board_debug_uart_init(void)
 {
+#if defined(CONFIG_DEBUG_UART_BASE) && \
+   (CONFIG_DEBUG_UART_BASE == 0xff168000) && \
+   (CONFIG_DEBUG_UART3_CHANNEL != 1)
+   static struct px30_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
+#endif
static struct px30_grf * const grf = (void *)GRF_BASE;
static struct px30_cru * const cr

Re: [U-Boot] [PATCH 1/3] mtd: rawnand: denali-spl: Add missing hardware init

2019-11-27 Thread Masahiro Yamada
On Tue, Nov 26, 2019 at 5:25 PM Marek Vasut  wrote:
> >> diff --git a/drivers/mtd/nand/raw/denali_spl.c 
> >> b/drivers/mtd/nand/raw/denali_spl.c
> >> index dbaba3cab2..b8b29812aa 100644
> >> --- a/drivers/mtd/nand/raw/denali_spl.c
> >> +++ b/drivers/mtd/nand/raw/denali_spl.c
> >> @@ -173,6 +173,13 @@ void nand_init(void)
> >> page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE);
> >> oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE);
> >> pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK);
> >> +
> >> +   /* Do as denali_hw_init() does. */
> >> +   writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES,
> >> +  denali_flash_reg + SPARE_AREA_SKIP_BYTES);
> >
> > I guess you tested this for SOCFPGA.
> >
> > Please tell me the value of CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES.
> 2


CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=2 is the only value
that works with the Boot ROM, right?

How did you find the correct value is 2 ?

Is it documented in the SOCFPGA datasheet or somewhere?
Or, did you repeat try-and-error?


-- 
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH v8 17/19] arm: dts: agilex: Add base dtsi and devkit dts

2019-11-27 Thread Simon Goldschmidt
On Wed, Nov 27, 2019 at 8:56 AM Ley Foon Tan  wrote:
>
> Add device tree files for Agilex SoC platform.
>
> socfpga_agilex-u-boot.dtsi and socfpga_agilex_socdk-u-boot.dts contains
> Uboot specific DT properties.
>
> socfpga_agilex.dtsi and socfpga_agilex_socdk.dts are from Linux
> (kernel/git/dinguyen/linux.git, commit 6f0bf971bacacc)
>
> Signed-off-by: Ley Foon Tan 
>
> ---
> v8:
> - Include socfpga_agilex-u-boot.dtsi in socfpga_agilex_socdk-u-boot.dtsi,
>   instead of include it in socfpga_agilex_socdk.dts.
>
> v7:
> - Update socfpga_agilex.dtsi and socfpga_agilex_socdk.dts from Linux.
> - Add new socfpga_agilex_socdk-u-boot.dts file for Uboot specific DT
>   properties.
>
> v6:
> - Use new macro names from agilex-clock.h.
>
> v5:
> - Add CCU DT node.
>
> v4:
> - Add u-boot,dm-pre-reloc to sysmgr node.
>
> v3:
> - Fixed bank 1 memory alias base address to 0x28000.
> - Rename STRATIX10_*_CLK to SOCFPGA_SOC64_*_CLK.
> - Include socfpga-soc64-clock.h
> - Change to "intel,sdr-ctl-agilex" for SDRAM node.
>
> v2:
> - Add clock property to device node.
> - Change memory size to 8GB
> - Enable i2c1
> ---
>  arch/arm/dts/Makefile |   1 +
>  arch/arm/dts/socfpga_agilex-u-boot.dtsi   |  96 +++
>  arch/arm/dts/socfpga_agilex.dtsi  | 622 ++
>  arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi |  39 ++
>  arch/arm/dts/socfpga_agilex_socdk.dts | 141 
>  5 files changed, 899 insertions(+)
>  create mode 100644 arch/arm/dts/socfpga_agilex-u-boot.dtsi
>  create mode 100644 arch/arm/dts/socfpga_agilex.dtsi
>  create mode 100644 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
>  create mode 100644 arch/arm/dts/socfpga_agilex_socdk.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index d8846df1bd..e76f7c1407 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -328,6 +328,7 @@ dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
>  dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
>
>  dtb-$(CONFIG_ARCH_SOCFPGA) +=  \
> +   socfpga_agilex_socdk.dtb\
> socfpga_arria5_socdk.dtb\
> socfpga_arria10_socdk_sdmmc.dtb \
> socfpga_cyclone5_mcvevk.dtb \
> diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi 
> b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
> new file mode 100644
> index 00..f0528a9ad9
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
> @@ -0,0 +1,96 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * U-Boot additions
> + *
> + * Copyright (C) 2019 Intel Corporation 
> + */
> +
> +/{
> +   memory {
> +   #address-cells = <2>;
> +   #size-cells = <2>;
> +   u-boot,dm-pre-reloc;
> +   };
> +
> +   soc {
> +   u-boot,dm-pre-reloc;
> +
> +   ccu: cache-controller@f700 {
> +   compatible = "arteris,ncore-ccu";
> +   reg = <0xf700 0x100900>;
> +   u-boot,dm-pre-reloc;
> +   };
> +   };
> +};
> +
> +&clkmgr {
> +   u-boot,dm-pre-reloc;
> +};
> +
> +&gmac1 {
> +   altr,sysmgr-syscon = <&sysmgr 0x48 0>;
> +};
> +
> +&gmac2 {
> +   altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
> +};
> +
> +&i2c0 {
> +   reset-names = "i2c";
> +};
> +
> +&i2c1 {
> +   reset-names = "i2c";
> +};
> +
> +&i2c2 {
> +   reset-names = "i2c";
> +};
> +
> +&i2c3 {
> +   reset-names = "i2c";
> +};
> +
> +&mmc {
> +   resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
> +};
> +
> +&porta {
> +   bank-name = "porta";
> +};
> +
> +&portb {
> +   bank-name = "portb";
> +};
> +
> +&qspi {
> +   u-boot,dm-pre-reloc;
> +};
> +
> +&rst {
> +   compatible = "altr,rst-mgr";

This and other compatible-changing lines in this file should be synced to the
correct string in all DTs, so please fix this in the upstream Linux DTs.

> +   altr,modrst-offset = <0x20>;
> +   u-boot,dm-pre-reloc;
> +};
> +
> +&sdr {
> +   compatible = "intel,sdr-ctl-agilex";

See above.

> +   reg = <0xf8000400 0x80>,
> + <0xf801 0x190>,
> + <0xf8011000 0x500>;
> +   resets = <&rst DDRSCH_RESET>;
> +   u-boot,dm-pre-reloc;
> +};
> +
> +&sysmgr {
> +   compatible = "altr,sys-mgr", "syscon";

See above.

Ultimately, you should onle need 'u-boot,dm-pre-reloc' tags in this file
and probably some boot source defititions.

However, until that is done, it's probably ok to have this here, so:
Reviewed-by: Simon Goldschmidt 

> +   u-boot,dm-pre-reloc;
> +};
> +
> +&uart0 {
> +   u-boot,dm-pre-reloc;
> +};
> +
> +&watchdog0 {
> +   u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/socfpga_agilex.dtsi 
> b/arch/arm/dts/socfpga_agilex.dtsi
> new file mode 100644
> index 00..179b4d5591
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_agilex.dtsi
> @@ -0,0 +1,622 @@
> +// SPDX-License-Identifier:   

Re: [U-Boot] [PATCH 2/5] Revert "ata: fsl_ahci: Add sata DM support for Freescale powerpc socs"

2019-11-27 Thread Stefan Roese

Hi Peng,

On 27.11.19 11:02, Peng Ma wrote:

This reverts commit 1ee494291880fd51ef0c5f7342e072bdb069d7ff.


I'm missing an explanation for this revert (or even better for this
whole patch-set). Why are you doing this? Is the new DM driver
causing problems?

Thanks,
Stefan
 

Signed-off-by: Peng Ma 
---
  drivers/ata/Kconfig|   10 -
  drivers/ata/Makefile   |1 -
  drivers/ata/fsl_ahci.c | 1030 
  drivers/ata/fsl_sata.h |1 -
  4 files changed, 1042 deletions(-)
  delete mode 100644 drivers/ata/fsl_ahci.c

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index fe589d3aa8..d8c9756c2a 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -59,16 +59,6 @@ config DWC_AHCI
  Enable this driver to support Sata devices through
  Synopsys DWC AHCI module.
  
-config FSL_AHCI

-   bool "Enable Freescale AHCI driver support"
-   select SCSI_AHCI
-   depends on AHCI
-   depends on DM_SCSI
-   help
- Enable this driver to support Sata devices found in
- some Freescale PowerPC SoCs.
-
-
  config DWC_AHSATA
bool "Enable DWC AHSATA driver support"
select LIBATA
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 6e03384f81..a69edb10f7 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -4,7 +4,6 @@
  # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
  
  obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o

-obj-$(CONFIG_FSL_AHCI) += fsl_ahci.o
  obj-$(CONFIG_AHCI) += ahci-uclass.o
  obj-$(CONFIG_AHCI_PCI) += ahci-pci.o
  obj-$(CONFIG_SCSI_AHCI) += ahci.o
diff --git a/drivers/ata/fsl_ahci.c b/drivers/ata/fsl_ahci.c
deleted file mode 100644
index d04cff3ee7..00
--- a/drivers/ata/fsl_ahci.c
+++ /dev/null
@@ -1,1030 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * NXP PPC SATA platform driver
- *
- * (C) Copyright 2019 NXP, Inc.
- *
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "fsl_sata.h"
-
-struct fsl_ahci_priv {
-   u32 base;
-   u32 flag;
-   u32 number;
-   fsl_sata_t *fsl_sata;
-};
-
-static int fsl_ahci_bind(struct udevice *dev)
-{
-   return device_bind_driver(dev, "fsl_ahci_scsi", "fsl_ahci_scsi", NULL);
-}
-
-static int fsl_ahci_ofdata_to_platdata(struct udevice *dev)
-{
-   struct fsl_ahci_priv *priv = dev_get_priv(dev);
-
-   priv->number = dev_read_u32_default(dev, "sata-number", -1);
-   priv->flag = dev_read_u32_default(dev, "sata-fpdma", -1);
-
-   priv->base = dev_read_addr(dev);
-   if (priv->base == FDT_ADDR_T_NONE)
-   return -EINVAL;
-
-   return 0;
-}
-
-static int ata_wait_register(unsigned __iomem *addr, u32 mask,
-u32 val, u32 timeout_msec)
-{
-   int i;
-
-   for (i = 0; ((in_le32(addr) & mask) != val) && i < timeout_msec; i++)
-   mdelay(1);
-
-   return (i < timeout_msec) ? 0 : -1;
-}
-
-static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
-{
-   printf("Status FIS dump:\n\r");
-   printf("fis_type:  %02x\n\r", s->fis_type);
-   printf("pm_port_i: %02x\n\r", s->pm_port_i);
-   printf("status:%02x\n\r", s->status);
-   printf("error: %02x\n\r", s->error);
-   printf("lba_low:   %02x\n\r", s->lba_low);
-   printf("lba_mid:   %02x\n\r", s->lba_mid);
-   printf("lba_high:  %02x\n\r", s->lba_high);
-   printf("device:%02x\n\r", s->device);
-   printf("lba_low_exp:   %02x\n\r", s->lba_low_exp);
-   printf("lba_mid_exp:   %02x\n\r", s->lba_mid_exp);
-   printf("lba_high_exp:  %02x\n\r", s->lba_high_exp);
-   printf("res1:  %02x\n\r", s->res1);
-   printf("sector_count:  %02x\n\r", s->sector_count);
-   printf("sector_count_exp:  %02x\n\r", s->sector_count_exp);
-}
-
-static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg)
-{
-   printf("\n\rSATA:   %08x\n\r", (u32)reg);
-   printf("CQR:%08x\n\r", in_le32(®->cqr));
-   printf("CAR:%08x\n\r", in_le32(®->car));
-   printf("CCR:%08x\n\r", in_le32(®->ccr));
-   printf("CER:%08x\n\r", in_le32(®->cer));
-   printf("CQR:%08x\n\r", in_le32(®->cqr));
-   printf("DER:%08x\n\r", in_le32(®->der));
-   printf("CHBA:   %08x\n\r", in_le32(®->chba));
-   printf("HStatus:%08x\n\r", in_le32(®->hstatus));
-   printf("HControl:   %08x\n\r", in_le32(®->hcontrol));
-   printf("CQPMP:  %08x\n\r", in_le32(®->cqpmp));
-   printf("SIG:%08x\n\r", in_le32(®->sig));
-   printf("ICC:%08x\n\r", in_le32(®->icc));
-   printf("SStatus:%08x\n\r", in_le32(®->sstatus));
-   printf("SError: %08x\n\r", in

Re: [U-Boot] GPT overlap on i.MX6

2019-11-27 Thread Lukasz Majewski
Hi Jagan,

> Hi,
> 
> I have created GPT table start from 8MB for kernel, roots etc.
> something like
> 
> PartStart LBA   End LBA Name
> Attributes
> Type GUID
> Partition GUID
>   1 0x4000  0x00023fff  "boota"
> attrs:  0x0004
> type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> guid:   c12a7328-f81f-11d2-ba4b-00a0c93ec93b
>   2 0x00024000  0x00043fff  "bootb"
> attrs:  0x0004
> type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> guid:   21686148-6449-6e6f-744e-656564454649
>   3 0x00044000  0x00243fff  "rootfsa"
> attrs:  0x
> type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> guid:   b921b045-1df0-41c3-af44-4c6f280d3fae
>   4 0x00244000  0x00443fff  "rootfsb"
> attrs:  0x
> type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> guid:   8da63339-0007-60c0-c436-083ac8230908
>   5 0x00444000  0x0070bfde  "data"
> attrs:  0x
> type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> guid:   4f72ab70-69be-5948-81ff-4fc3daf24faa
> 
> I have not included SPL, U-Boot to the partition list since it start
> from 0x400 in i.MX6. So
> I'm writing SPL separately using fastboot(with offset) or ums.
> 
> But by doing this, the partition header seems overlapped so the
> output looks
> 
> GUID Partition Table Entry Array CRC is wrong: 0x6a1aba0a !=
> 0x8e4fd548 find_valid_gpt: *** ERROR: Invalid GPT ***
> find_valid_gpt: ***Using Backup GPT ***
> PartStart LBA   End LBA Name
> Attributes
> Type GUID
> Partition GUID
>   1 0x4000  0x00023fff  "boota"
> attrs:  0x0004
> type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> guid:   c12a7328-f81f-11d2-ba4b-00a0c93ec93b
>   2 0x00024000  0x00043fff  "bootb"
> attrs:  0x0004
> type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> guid:   21686148-6449-6e6f-744e-656564454649
>   3 0x00044000  0x00243fff  "rootfsa"
> attrs:  0x
> type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> guid:   b921b045-1df0-41c3-af44-4c6f280d3fae
>   4 0x00244000  0x00443fff  "rootfsb"
> attrs:  0x
> type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> guid:   8da63339-0007-60c0-c436-083ac8230908
>   5 0x00444000  0x0070bfde  "data"
> attrs:  0x
> type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> guid:   4f72ab70-69be-5948-81ff-4fc3daf24faa
> 
> So, what I understand is If I create the GPT first and then write the
> SPL, the SPL writing process will destroy the GPT Table and if I write
> SPL first and then create GPT, the GPT creation process will destroy
> the SPL.
> 
> Is there any way to fix this? I remember we can prevent this overlap
> by preserving GPT Table som other or boot partition instead of having
> them at the beginning by default.
> 
> Any inputs?

On the diagram of GPT description [1] there is the info that partitions
can start from LBA 34 (0x200 * 34) = 0x4400 

From the above it seems like you starts from 0x4000 your boota
partition, which then overwrites the "Entries 5-128" which shall be 0
and are protected by CRC written in the Primary GPT Header.

Please try to adjust your partition scheme to start from 0x4400.

> 
> Jagan.


Links:

[1] - https://en.wikipedia.org/wiki/GUID_Partition_Table

Best regards,

Lukasz Majewski

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Re: [U-Boot] [PATCH 1/3] mtd: rawnand: denali-spl: Add missing hardware init

2019-11-27 Thread Marek Vasut
On 11/27/19 11:20 AM, Masahiro Yamada wrote:
> On Tue, Nov 26, 2019 at 5:25 PM Marek Vasut  wrote:
 diff --git a/drivers/mtd/nand/raw/denali_spl.c 
 b/drivers/mtd/nand/raw/denali_spl.c
 index dbaba3cab2..b8b29812aa 100644
 --- a/drivers/mtd/nand/raw/denali_spl.c
 +++ b/drivers/mtd/nand/raw/denali_spl.c
 @@ -173,6 +173,13 @@ void nand_init(void)
 page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE);
 oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE);
 pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK);
 +
 +   /* Do as denali_hw_init() does. */
 +   writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES,
 +  denali_flash_reg + SPARE_AREA_SKIP_BYTES);
>>>
>>> I guess you tested this for SOCFPGA.
>>>
>>> Please tell me the value of CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES.
>> 2
> 
> 
> CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=2 is the only value
> that works with the Boot ROM, right?
> 
> How did you find the correct value is 2 ?
> 
> Is it documented in the SOCFPGA datasheet or somewhere?
> Or, did you repeat try-and-error?

I took it from the old vendoruboot port.
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[U-Boot] [RESEND PATCH] arm: imx6: cm_fx6: Enable DM SPI and SPI_FLASH, fix SPL build errors

2019-11-27 Thread sunil . m
From: Suniel Mahesh 

Enable driver model for SPI and SPI_FLASH to remove the following
compile warning on CM-FX6 SOM:
= WARNING ==
This board does not use CONFIG_DM_SPI_FLASH. Please update
the board to use CONFIG_SPI_FLASH before the v2019.07 release.


This change introduced SPL build error as shown:

In file included from include/common.h:47:0,
 from drivers/mtd/spi/sf_probe.c:10:
drivers/mtd/spi/sf_probe.c: In function 'spi_flash_std_probe':
drivers/mtd/spi/sf_probe.c:149:54: error: dereferencing pointer to incomplete 
type 'struct dm_spi_slave_platdata'
scripts/Makefile.build:278: recipe for target 'spl/drivers/mtd/spi/sf_probe.o' 
failed
make[3]: *** [spl/drivers/mtd/spi/sf_probe.o] Error 1
scripts/Makefile.build:432: recipe for target 'spl/drivers/mtd/spi' failed
make[2]: *** [spl/drivers/mtd/spi] Error 2

Disabling DM for SPI support(SPI and SF) in SPL resolves the issue.
Target was compile tested, build was clean.

Signed-off-by: Suniel Mahesh 
---
 configs/cm_fx6_defconfig | 2 ++
 include/configs/cm_fx6.h | 7 +++
 2 files changed, 9 insertions(+)

diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index 218d3d6..ca9895e 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -66,6 +66,7 @@ CONFIG_FSL_USDHC=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=2500
 CONFIG_SPI_FLASH_ATMEL=y
@@ -82,6 +83,7 @@ CONFIG_MII=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_MXC_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index eb29f07..53ae5f0 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -153,6 +153,13 @@
 /* APBH DMA is required for NAND support */
 #endif
 
+/* SPI Flash Configs */
+#if defined(CONFIG_SPL_BUILD)
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
+#undef CONFIG_SPI_FLASH_MTD
+#endif
+
 /* Ethernet */
 #define CONFIG_FEC_MXC
 #define CONFIG_FEC_MXC_PHYADDR 0
-- 
2.7.4

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Re: [U-Boot] Raspberry Pi Compute Module 1 mini-UART

2019-11-27 Thread edrose
Hi Matthias,

Thank you very much for your help. Unfortunately I'm still a little stuck.


Matthias Brugger wrote
> 1) as you found out U-Boot is using an embedded device tree. The device
> tree it
> uses is specified in configs/rpi_*
> I suppose you are using rpi_3_defconfig, so your device-tree is:
> bcm2837-rpi-3-b
> You can find the device-tree files in arch/arm/dts where you can change
> the files.

I had a go at this, but with little success. The Compute Module 1 is
actually based off the hardware of the original 256Mb Raspberry Pi 1. I've
tried using the bcm2837-rpi-3-b device-tree, but I just get (what I've come
to call) the Rainbow Screen of Death and nothing boots. Using the
bcm2835-rpi-b tree allows it to boot.

I tried modifying the file to include the second UART port, by adding the
following lines to the end (underneath the definition for &uart0), but
unfortunately it doesn't seem to work:

&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_gpio40>;
status = "okay";
};

I'm testing this by calling `coninfo` in the uboot prompt. Two serial ports
show, however only one has an address next to it and it's the address of the
main serial port. It looks like the following:

List of available devices: 
serial@7e201000 0007 IO
serial   0003 IO stdin 
nulldev  0003 IO   
vidconsole 0002 .O stdout stderr

Am I interpreting that correctly? Or is the serial port somehow enabled
without an address?


'Matthias Brugger" wrote
> 2) you can update the config to use CONFIG_OF_BOARD instead of
> CONFIG_OF_EMBED.
> This will take the device-tree from the file specified in config.txt (or
> to be
> correct the RPi FW will pass this device-tree to U-Boot in a register at
> startup). 

Doing this (but leaving the default device tree the same) results in no
changes to the output of `coninfo`. Is there something I need to do to tell
uboot where in memory the device-tree is stored?

I've also tried playing around with CONFIG_SPECIFY_CONSOLE_INDEX but that
had no effect either. Is there something that needs adding to the header
file to specify the serial port?

Thanks once again for your help,
Ed



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Re: [U-Boot] [PATCH v1 1/4] dfu: Drop unused prototype of dfu_trigger_reset()

2019-11-27 Thread Lukasz Majewski
On Wed, 13 Nov 2019 19:43:41 +0200
Andy Shevchenko  wrote:

> After the commit 1cc03c5c53c0 ("dfu: Provide means to find difference
> between dfu-util -e and -R") the dangling ptototype appeared. Remove
> it here.
> 
> Fixes: 1cc03c5c53c0 ("dfu: Provide means to find difference between
> dfu-util -e and -R") Cc: Lukasz Majewski 
> Cc: Stephen Warren 
> Signed-off-by: Andy Shevchenko 
> ---
>  include/dfu.h | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/include/dfu.h b/include/dfu.h
> index 564966333f..2e3e91c8d2 100644
> --- a/include/dfu.h
> +++ b/include/dfu.h
> @@ -171,7 +171,6 @@ const char *dfu_get_dev_type(enum dfu_device_type
> t); const char *dfu_get_layout(enum dfu_layout l);
>  struct dfu_entity *dfu_get_entity(int alt);
>  char *dfu_extract_token(char** e, int *n);
> -void dfu_trigger_reset(void);
>  int dfu_get_alt(char *name);
>  int dfu_init_env_entities(char *interface, char *devstr);
>  unsigned char *dfu_get_buf(struct dfu_entity *dfu);

Acked-by: Lukasz Majewski 


Best regards,

Lukasz Majewski

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Re: [U-Boot] [PATCH v1 2/4] dfu: Refactor do_dfu() to handle optional argument

2019-11-27 Thread Lukasz Majewski
On Wed, 13 Nov 2019 19:43:42 +0200
Andy Shevchenko  wrote:

> In the future we may utilize optional argument in 'dfu' command line.
> As a preparation for this, refactor do_dfu().
> 
> Signed-off-by: Andy Shevchenko 
> ---
>  cmd/dfu.c | 17 ++---
>  1 file changed, 10 insertions(+), 7 deletions(-)
> 
> diff --git a/cmd/dfu.c b/cmd/dfu.c
> index 33491d0bc9..14a8ec879e 100644
> --- a/cmd/dfu.c
> +++ b/cmd/dfu.c
> @@ -30,22 +30,25 @@ static int do_dfu(cmd_tbl_t *cmdtp, int flag, int
> argc, char * const argv[]) #if defined(CONFIG_DFU_OVER_USB) ||
> defined(CONFIG_DFU_OVER_TFTP) char *interface = NULL;
>   char *devstring = NULL;
> +#if defined(CONFIG_DFU_OVER_TFTP)
> + unsigned long value = 0;
> +#endif
>  
>   if (argc >= 4) {
>   interface = argv[2];
>   devstring = argv[3];
>   }
> +
> +#if defined(CONFIG_DFU_OVER_TFTP)
> + if (argc == 5 || argc == 3)
> + value = simple_strtoul(argv[argc - 1], NULL, 0);
> +#endif
>  #endif
>  
>   int ret = 0;
>  #ifdef CONFIG_DFU_OVER_TFTP
> - unsigned long addr = 0;
> - if (!strcmp(argv[1], "tftp")) {
> - if (argc == 5 || argc == 3)
> - addr = simple_strtoul(argv[argc - 1], NULL,
> 0); -
> - return update_tftp(addr, interface, devstring);
> - }
> + if (!strcmp(argv[1], "tftp"))
> + return update_tftp(value, interface, devstring);
>  #endif
>  #ifdef CONFIG_DFU_OVER_USB
>   ret = dfu_init_env_entities(interface, devstring);

Acked-by: Lukasz Majewski 


Best regards,

Lukasz Majewski

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Re: [U-Boot] [PATCH v1 3/4] dfu: Add optional timeout parameter

2019-11-27 Thread Lukasz Majewski
Hi Andy,

Thank you for your work on enhancing DFU. The patch series is generally
Ok.

Please find some minor comments/requests below.

> When the `dfu` command is called from the U-Boot environment,
> it now accepts an optional parameter that specifies a timeout (in
> seconds). If a DFU connection is not made within that time the `dfu`
> command exits (as it would if Ctrl+C was pressed). If the timeout is
> left empty or being zero the `dfu` command behaves as it does now.
> 
> This is useful for allowing U-Boot to check to see if anything wants
> to upload new firmware before continuing to boot.
> 
> The patch is based on the commit
> https://github.com/01org/edison-u-boot/commit/5e966ccc3c65c18c9783741fa04e0c45e021780c
> which has been heavily reworked due to U-Boot changes in the past.
> 
> Signed-off-by: Sebastien Colleur 
> Signed-off-by: Brad Campbell 
> Signed-off-by: Andy Shevchenko 
> ---
>  cmd/dfu.c   | 15 +--
>  common/dfu.c| 17 +
>  drivers/dfu/Kconfig |  6 ++
>  drivers/dfu/dfu.c   | 15 +++
>  include/dfu.h   |  5 +
>  5 files changed, 56 insertions(+), 2 deletions(-)
> 
> diff --git a/cmd/dfu.c b/cmd/dfu.c
> index 14a8ec879e..b30f8a5667 100644
> --- a/cmd/dfu.c
> +++ b/cmd/dfu.c
> @@ -30,7 +30,7 @@ static int do_dfu(cmd_tbl_t *cmdtp, int flag, int
> argc, char * const argv[]) #if defined(CONFIG_DFU_OVER_USB) ||
> defined(CONFIG_DFU_OVER_TFTP) char *interface = NULL;
>   char *devstring = NULL;
> -#if defined(CONFIG_DFU_OVER_TFTP)
> +#if defined(CONFIG_DFU_TIMEOUT) || defined(CONFIG_DFU_OVER_TFTP)
>   unsigned long value = 0;
>  #endif
>  
> @@ -39,7 +39,7 @@ static int do_dfu(cmd_tbl_t *cmdtp, int flag, int
> argc, char * const argv[]) devstring = argv[3];
>   }
>  
> -#if defined(CONFIG_DFU_OVER_TFTP)
> +#if defined(CONFIG_DFU_TIMEOUT) || defined(CONFIG_DFU_OVER_TFTP)
>   if (argc == 5 || argc == 3)
>   value = simple_strtoul(argv[argc - 1], NULL, 0);
>  #endif
> @@ -55,6 +55,10 @@ static int do_dfu(cmd_tbl_t *cmdtp, int flag, int
> argc, char * const argv[]) if (ret)
>   goto done;
>  
> +#ifdef CONFIG_DFU_TIMEOUT
> + dfu_set_timeout(value * 1000);
> +#endif
> +
>   ret = CMD_RET_SUCCESS;
>   if (strcmp(argv[argc - 1], "list") == 0) {
>   dfu_show_entities();
> @@ -75,10 +79,17 @@ U_BOOT_CMD(dfu, CONFIG_SYS_MAXARGS, 1, do_dfu,
>   "Device Firmware Upgrade",
>   ""
>  #ifdef CONFIG_DFU_OVER_USB
> +#ifdef CONFIG_DFU_TIMEOUT
> + " [ ] [] [list]\n"
> +#else
>   " [ ] [list]\n"
> +#endif
>   "  - device firmware upgrade via \n"
>   "on device , attached to interface\n"
>   "\n"
> +#ifdef CONFIG_DFU_TIMEOUT
> + "[] - specify inactivity timeout in seconds\n"
> +#endif
>   "[list] - list available alt settings\n"
>  #endif
>  #ifdef CONFIG_DFU_OVER_TFTP
> diff --git a/common/dfu.c b/common/dfu.c
> index 44d1484d3d..da6289b218 100644
> --- a/common/dfu.c
> +++ b/common/dfu.c
> @@ -35,6 +35,10 @@ int run_usb_dnl_gadget(int usbctrl_index, char
> *usb_dnl_gadget) return CMD_RET_FAILURE;
>   }
>  
> +#ifdef CONFIG_DFU_TIMEOUT
> + unsigned long start_time = get_timer(0);
> +#endif
> +
>   while (1) {
>   if (g_dnl_detach()) {
>   /*
> @@ -79,6 +83,19 @@ int run_usb_dnl_gadget(int usbctrl_index, char
> *usb_dnl_gadget) }
>   }
>  
> +#ifdef CONFIG_DFU_TIMEOUT
> + unsigned long wait_time = dfu_get_timeout();
> +
> + if (wait_time) {
> + unsigned long current_time =
> get_timer(start_time); +
> + if (current_time > wait_time) {
> + debug("Inactivity timeout, abort
> DFU\n");
> + goto exit;
> + }
> + }
> +#endif
> +
>   WATCHDOG_RESET();
>   usb_gadget_handle_interrupts(usbctrl_index);
>   }
> diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig
> index 9fe5bc0f58..e070130b5a 100644
> --- a/drivers/dfu/Kconfig
> +++ b/drivers/dfu/Kconfig
> @@ -23,6 +23,12 @@ config DFU_TFTP
>  
> Detailed description of this feature can be found at
> ./doc/README.dfutftp 
> +config DFU_TIMEOUT
> + bool "Timeout waiting for DFU"
> + help
> +   This option adds an optional timeout parameter for DFU
> which, if set,
> +   will cause DFU to only wait for that many seconds before
> exiting. +
>  config DFU_MMC
>   bool "MMC back end for DFU"
>   help
> diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c
> index 38aecd3a05..df50196dfd 100644
> --- a/drivers/dfu/dfu.c
> +++ b/drivers/dfu/dfu.c
> @@ -21,6 +21,9 @@ static LIST_HEAD(dfu_list);
>  static int dfu_alt_num;
>  static int alt_num_cnt;
>  static struct hash_algo *dfu_hash_algo;
> +#ifdef CONFIG_DFU_TIMEOUT
> +static unsigned long dfu_timeout = 0;
> +#endif
>  
>  /*
>   * The purpose of the dfu_flush_callback() function is to
>

Re: [U-Boot] [PATCH v1 4/4] x86: edison: Enable DFU timeout

2019-11-27 Thread Lukasz Majewski
Hi Andy,

> The stock U-Boot on Intel Edison has timeout parameter for DFU
> command. Enable it here to be compatible with the original U-Boot
> configuration.
> 
> Signed-off-by: Andy Shevchenko 
> ---
>  configs/edison_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/configs/edison_defconfig b/configs/edison_defconfig
> index 1c74ee9709..227e2f750c 100644
> --- a/configs/edison_defconfig
> +++ b/configs/edison_defconfig
> @@ -29,6 +29,7 @@ CONFIG_CMD_FS_GENERIC=y
>  CONFIG_DEFAULT_DEVICE_TREE="edison"
>  CONFIG_ENV_IS_IN_MMC=y
>  CONFIG_CPU=y
> +CONFIG_DFU_TIMEOUT=y
>  CONFIG_DFU_MMC=y
>  CONFIG_DFU_RAM=y
>  CONFIG_SUPPORT_EMMC_BOOT=y

This patch doesn't apply now.

Best regards,

Lukasz Majewski

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Re: [U-Boot] [PATCH v3 1/6] fat: write: fix broken write to fragmented files

2019-11-27 Thread Marek Szyprowski
Hi,

On 27.11.2019 03:26, AKASHI Takahiro wrote:
> Thank you for the heads-up.
>
> On Tue, Nov 26, 2019 at 11:57:29AM -0500, Tom Rini wrote:
>> On Tue, Nov 26, 2019 at 09:15:07AM +0100, Marek Szyprowski wrote:
>>
>>> The code for handing file overwrite incorrectly assumed that the file on
>>> disk is always contiguous. This resulted in corrupting disk structure
>>> every time when write to existing fragmented file happened. Fix this
>>> by adding proper check for cluster discontinuity and adjust chunk size
>>> on each partial write.
>>>
>>> Signed-off-by: Marek Szyprowski 
>>> Reviewed-by: Oleksandr Suvorov 
>>> Reviewed-by: Lukasz Majewski 
>>> ---
>>>   fs/fat/fat_write.c | 6 +++---
>>>   1 file changed, 3 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
>>> index 729cf39630..6cfa5b4565 100644
>>> --- a/fs/fat/fat_write.c
>>> +++ b/fs/fat/fat_write.c
>>> @@ -794,6 +794,8 @@ set_contents(fsdata *mydata, dir_entry *dentptr, loff_t 
>>> pos, __u8 *buffer,
>>>   
>>> newclust = get_fatent(mydata, endclust);
>>>   
>>> +   if ((newclust - 1) != endclust)
> "newclust != (endclust + 1)" would be more intuitive?
> But it's just my preference.

Indeed.

>>> +   break;
>>> if (IS_LAST_CLUST(newclust, mydata->fatsize))
>>> break;
>>> if (CHECK_CLUST(newclust, mydata->fatsize)) {
>>> @@ -811,7 +813,7 @@ set_contents(fsdata *mydata, dir_entry *dentptr, loff_t 
>>> pos, __u8 *buffer,
>>> offset = 0;
>>> else
>>> offset = pos - cur_pos;
>>> -   wsize = min(cur_pos + actsize, filesize) - pos;
>>> +   wsize = min_t(unsigned long long, actsize, filesize - cur_pos);
> This hunk is not directly related to the issue, is it?

It is partially related. I remember that it was not calculated correctly 
for the fragmented files and then discovered that there was one more 
case in which the current formula failed.

>>> if (get_set_cluster(mydata, curclust, offset,
>>> buffer, wsize, &actsize)) {
>>> printf("Error get-and-setting cluster\n");
>>> @@ -824,8 +826,6 @@ set_contents(fsdata *mydata, dir_entry *dentptr, loff_t 
>>> pos, __u8 *buffer,
>>> if (filesize <= cur_pos)
>>> break;
>>>   
>>> -   /* CHECK: newclust = get_fatent(mydata, endclust); */
>>> -
>>> if (IS_LAST_CLUST(newclust, mydata->fatsize))
>>> /* no more clusters */
>>> break;
>> Adding in Heinrich and Akashi-san for more review on this, thanks!
> Otherwise, it looks good.
> Reviewed-by: AKASHI Takahiro 

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

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[U-Boot] [RFC PATCH] ARM: at91: Print CPU serial number in cpuinfo

2019-11-27 Thread Alexander Dahl
The SAMA5D2 and SAMA5D4 series SoCs have a 64-bit Serial Number (unique
ID) burned in, which is displayed with 'print_cpuinfo()' now (in the
same format the SAM-BA applet prints it).

Example output:

CPU: SAMA5D27 1G bits DDR2 SDRAM
Serial number 0: 0x4630394b
  1: 0x190d2750
Crystal frequency:   24 MHz
CPU clock:  492 MHz
Master clock :  164 MHz

Signed-off-by: Alexander Dahl 
---

I looked over lots of other 'print_cpuinfo()' implementations for
different SoCs and found none printing a unique ID at all. Is there
another place for this? Is it just few SoCs have such a serial number
at all? Or is it not desired to print those along with the other CPU
info?

Greets
Alex

---
 arch/arm/mach-at91/armv7/cpu.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c
index 5da067cda1..6d50e1aea4 100644
--- a/arch/arm/mach-at91/armv7/cpu.c
+++ b/arch/arm/mach-at91/armv7/cpu.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #ifndef CONFIG_SYS_AT91_MAIN_CLOCK
@@ -42,9 +43,16 @@ void arch_preboot_os(void)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
+   struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
char buf[32];
 
printf("CPU: %s\n", get_cpu_name());
+
+#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D4)
+   printf("Serial number 0: 0x%08x\n", sfr->sn0);
+   printf("  1: 0x%08x\n", sfr->sn1);
+#endif
+
printf("Crystal frequency: %8s MHz\n",
   strmhz(buf, get_main_clk_rate()));
printf("CPU clock: %8s MHz\n",
-- 
2.20.1

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Re: [U-Boot] [PATCH 4/4] board: amlogic: Add missing config option

2019-11-27 Thread Neil Armstrong
Hi,

On 26/11/2019 22:12, Anand Moon wrote:
> Add missing config option CONFIG_MESON_GXBB and CONFIG_SYS_BOARD,
> for odroid-c2 and nanopi k2 board
> 
> Signed-off-by: Anand Moon 
> ---
>  configs/nanopi-k2_defconfig | 2 ++
>  configs/odroid-c2_defconfig | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig
> index 7bdeb7906a..3d6265c587 100644
> --- a/configs/nanopi-k2_defconfig
> +++ b/configs/nanopi-k2_defconfig
> @@ -1,6 +1,8 @@
>  CONFIG_ARM=y
> +CONFIG_SYS_BOARD="p200"
>  CONFIG_ARCH_MESON=y
>  CONFIG_SYS_TEXT_BASE=0x0100
> +CONFIG_MESON_GXBB=y
>  CONFIG_ENV_SIZE=0x2000
>  CONFIG_NR_DRAM_BANKS=1
>  CONFIG_DEBUG_UART_BASE=0xc81004c0
> diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
> index 1f5a52c57c..700c871918 100644
> --- a/configs/odroid-c2_defconfig
> +++ b/configs/odroid-c2_defconfig
> @@ -1,6 +1,8 @@
>  CONFIG_ARM=y
> +CONFIG_SYS_BOARD="p200"
>  CONFIG_ARCH_MESON=y
>  CONFIG_SYS_TEXT_BASE=0x0100
> +CONFIG_MESON_GXBB=y
>  CONFIG_ENV_SIZE=0x2000
>  CONFIG_NR_DRAM_BANKS=1
>  CONFIG_DEBUG_UART_BASE=0xc81004c0
> 

These are not present since they are the default values, thus not exported in 
savedefconfig.

Neil
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Re: [U-Boot] [PATCH] bootm: vxworks: Support Linux compatible standard DTB for ARM and PPC

2019-11-27 Thread Tom Rini
On Wed, Nov 27, 2019 at 02:03:03PM +0800, Bin Meng wrote:
> Hi Tom,
> 
> On Wed, Nov 20, 2019 at 10:22 PM Tom Rini  wrote:
> >
> > On Wed, Nov 20, 2019 at 10:11:00AM +0800, Bin Meng wrote:
> > > Hi Tom,
> > >
> > > On Fri, Nov 15, 2019 at 4:21 PM Bin Meng  wrote:
> > > >
> > > > From: Lihua Zhao 
> > > >
> > > > Enhance do_bootm_vxworks() to support Linux compatible standard DTB
> > > > for ARM and PPC, when the least significant bit of flags in VxWorks
> > > > bootargs is set. Otherwise it falls back to the existing bootm flow
> > > > which is now legacy.
> > > >
> > > > Signed-off-by: Lihua Zhao 
> > > > Signed-off-by: Bin Meng 
> > > > Reviewed-by: Bin Meng 
> > > > ---
> > > >
> > > >  common/bootm_os.c  | 39 +--
> > > >  doc/README.vxworks | 13 +
> > > >  include/vxworks.h  |  3 +++
> > > >  3 files changed, 53 insertions(+), 2 deletions(-)
> > >
> > > It would be good if you pick this up for v2020.01. Thanks!
> >
> > OK, thanks.  I'll put this on my TODO list for soon.
> 
> A gentle ping?

So the issue now is that this causes size growth and then link failure
on tbs2910.  And I don't think "boot modern VxWorks kernels" is a new
CONFIG option I want to see.  So I'm not quite sure what to do here yet.
Soeren, do you care about VxWorks support on this platform?  Thanks!

-- 
Tom


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Re: [U-Boot] [PATCH 3/4] board: amlogic: select PWRSEQ for all amlogic platform

2019-11-27 Thread Neil Armstrong
On 26/11/2019 22:12, Anand Moon wrote:
> commit a10388dc6982 ("mmc: meson-gx: add support for mmc-pwrseq-emmc")
> introduce CONFIG_PWESEQ for power sequence for eMMC module on
> amlogic platform, so enable this to all amlogic boards.
> 
> Signed-off-by: Anand Moon 
> ---
>  arch/arm/mach-meson/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
> index e29e4c0acc..513a33dae2 100644
> --- a/arch/arm/mach-meson/Kconfig
> +++ b/arch/arm/mach-meson/Kconfig
> @@ -8,6 +8,7 @@ config MESON64_COMMON
>   select DM_SERIAL
>   select SYSCON
>   select REGMAP
> + select PWRSEQ
>   select BOARD_LATE_INIT
>   imply CMD_DM
>  
> 

Reviewed-by: Neil Armstrong 
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Re: [U-Boot] [PATCH 2/4] configs: meson64: enable GIC support for G12A/G12B

2019-11-27 Thread Neil Armstrong
On 26/11/2019 22:12, Anand Moon wrote:
> Enable GIC support for G12A/G12B platform.
> 
> Signed-off-by: Anand Moon 
> ---
>  include/configs/meson64.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/configs/meson64.h b/include/configs/meson64.h
> index 736081277d..50707a3197 100644
> --- a/include/configs/meson64.h
> +++ b/include/configs/meson64.h
> @@ -8,7 +8,7 @@
>  #define __MESON64_CONFIG_H
>  
>  /* Generic Interrupt Controller Definitions */
> -#if defined(CONFIG_MESON_AXG)
> +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
>  #define GICD_BASE0xffc01000
>  #define GICC_BASE0xffc02000
>  #else /* MESON GXL and GXBB */
> 

Thanks for spotting this !

Reviewed-by: Neil Armstrong 
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[U-Boot] Using sspi for hardware detection?

2019-11-27 Thread Romain Naour
Hello,

I'm working on a modular socfpga based system with several optional boards.
Each optional board contain a board ID that can be read through a SPI bus.

Since we want just read the board ID, we used manually the sspi command,
something like:

=> sspi 1:1.0 8 0
42

But it seems that the sspi command can't be used in a uboot script. sspi seems
only used to manually test spi drivers.


If we compare with i2c command, we have a i2c read to memory:

i2c read chip address[.0, .1, .2] length memaddress - read to memory

Why there is no such feature for spi ?
Is there an interest to evolve the sspi command to add a read to memory?

sspi : .   


By looking at existing code, it seems that hardware detection in uboot is
handled by architecture/board specific code to set custom environment variable
like "fpgatype" [1] or "unit_ident" "unit_serial" [2] (misc_init_r).

What do you recommend?
Implement a custom misc_init_r() for hardware detection?

[1]
https://gitlab.denx.de/u-boot/u-boot/blob/master/arch/arm/mach-socfpga/misc_gen5.c#L139
[2]
https://gitlab.denx.de/u-boot/u-boot/blob/master/board/softing/vining_fpga/socfpga.c#L48

Best regards,
Romain
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Re: [U-Boot] [PATCH 1/4] mmc: meson-gx: Fix tx phase in the tuning process

2019-11-27 Thread Neil Armstrong
Hi,

On 26/11/2019 22:12, Anand Moon wrote:
> odroid n2 eMMC module would failed to boot up,
> because of TX phase clk failure, fix the typo in
> TX phase macro to help tune correct clk freqency.
> 
> Before these changes.
>   clock is enabled (380953Hz)
>   clock is enabled (2500Hz)
> after these changes
>   clock is enabled (380953Hz)
>   clock is enabled (2500Hz)
>   clock is enabled (5200Hz)
>   clock is enabled (5200Hz)
>   clock is enabled (5200Hz)
> 
> Signed-off-by: Anand Moon 
> ---
> Tested on
> new orange - eMMC AJNB4R 14.6 GiB MMC 5.1
> old back   - eMMC CGND3R 58.2 GiB MMC 5.0
> ---
>  drivers/mmc/meson_gx_mmc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> index 031cc79ccb..87bea2888b 100644
> --- a/drivers/mmc/meson_gx_mmc.c
> +++ b/drivers/mmc/meson_gx_mmc.c
> @@ -53,7 +53,7 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>   meson_mmc_clk |= CLK_CO_PHASE_180;
>  
>   /* 180 phase tx clock */
> - meson_mmc_clk |= CLK_TX_PHASE_000;
> + meson_mmc_clk |= CLK_TX_PHASE_180;
>  
>   /* clock settings */
>   meson_mmc_clk |= clk_src;
> 

I don't understand what this change helps, the linux driver sets the TX phase 
to 0,
why 180 would help here ?

Neil
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Re: [U-Boot] [PATCH v3 2/6] fat: write: fix broken write at non-zero file offset

2019-11-27 Thread Marek Szyprowski
Hi

On 27.11.2019 04:13, AKASHI Takahiro wrote:
> # I still need to understand the issues reported here.
>
> On Tue, Nov 26, 2019 at 11:57:34AM -0500, Tom Rini wrote:
>> On Tue, Nov 26, 2019 at 09:15:08AM +0100, Marek Szyprowski wrote:
>>
>>> Handling of the start file offset was broken in the current code. Although
>>> the code skipped the needed clusters, it then tried to continue write with
>>> current cluster set to EOF, what caused assertion. It also lacked adjusting
>>> filesize in case of writing at the end of file and adjusting in-cluster
>>> offset for partial overwrite.
>>>
>>> This patch fixes all those issues.
> If those issues are logically independent from each other,
> it would be nice to split this patch into small ones.
>
> I would like to expect you to add more test cases, especially
> against corner cases that you mentioned above, to test/py/tests/est_fs
> as I did in test_ext.py.
> Or at least please add more assertion checks.

Okay, I will try to prepare some tests which show bugs fixed by this 
patch. I'm not sure I will manage to split this patch into patches 
fixing each single issue I've observed, because at least some of them 
were related.

I'm not familiar with py_test&co, but I will try to prepare some simple 
scripts for sandbox to reproduce the observed issues.

>>> Signed-off-by: Marek Szyprowski 
>>> ---
>>>   fs/fat/fat_write.c | 13 ++---
>>>   1 file changed, 6 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
>>> index 6cfa5b4565..7fb373589d 100644
>>> --- a/fs/fat/fat_write.c
>>> +++ b/fs/fat/fat_write.c
>>> @@ -756,14 +756,12 @@ set_contents(fsdata *mydata, dir_entry *dentptr, 
>>> loff_t pos, __u8 *buffer,
>>> /* go to cluster at pos */
>>> cur_pos = bytesperclust;
>>> while (1) {
>>> +   newclust = get_fatent(mydata, curclust);
>>> if (pos <= cur_pos)
> I think that we should change this condition as
>  if (pos < cur_pos)
>  break;
> then modify the following code accordingly as well.
>
> In this way, 'curclust' points to [cur_pos - bytesperclust, cur_pos)
> and 'pos' is ensured to be in the middle after this 'while' unless
>  (pos == cur_pos) && IS_LAST_CLUST(curclust,...).
>
> Then the code will be expected to look better understandable.
>
> Thanks,
> -Takahiro Akashi
>
>
>>> break;
>>> -   if (IS_LAST_CLUST(curclust, mydata->fatsize))
>>> +   if (IS_LAST_CLUST(newclust, mydata->fatsize))
>>> break;
>>> -
>>> -   newclust = get_fatent(mydata, curclust);
>>> -   if (!IS_LAST_CLUST(newclust, mydata->fatsize) &&
>>> -   CHECK_CLUST(newclust, mydata->fatsize)) {
>>> +   if (CHECK_CLUST(newclust, mydata->fatsize)) {
>>> debug("curclust: 0x%x\n", curclust);
>>> debug("Invalid FAT entry\n");
>>> return -1;
>>> @@ -772,8 +770,8 @@ set_contents(fsdata *mydata, dir_entry *dentptr, loff_t 
>>> pos, __u8 *buffer,
>>> cur_pos += bytesperclust;
>>> curclust = newclust;
>>> }
>>> -   if (IS_LAST_CLUST(curclust, mydata->fatsize)) {
>>> -   assert(pos == cur_pos);
>>> +   if (pos == cur_pos && IS_LAST_CLUST(newclust, mydata->fatsize)) {
>>> +   filesize -= pos;
>>> goto set_clusters;
>>> }
>>>   
>>> @@ -814,6 +812,7 @@ set_contents(fsdata *mydata, dir_entry *dentptr, loff_t 
>>> pos, __u8 *buffer,
>>> else
>>> offset = pos - cur_pos;
>>> wsize = min_t(unsigned long long, actsize, filesize - cur_pos);
>>> +   wsize -= offset;
>>> if (get_set_cluster(mydata, curclust, offset,
>>> buffer, wsize, &actsize)) {
>>> printf("Error get-and-setting cluster\n");
>> Adding in Heinrich and Akashi-san for more review on this, thanks!

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

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Re: [U-Boot] [PATCH] bootm: vxworks: Support Linux compatible standard DTB for ARM and PPC

2019-11-27 Thread Soeren Moch
On 27.11.19 13:55, Tom Rini wrote:
> On Wed, Nov 27, 2019 at 02:03:03PM +0800, Bin Meng wrote:
>> Hi Tom,
>>
>> On Wed, Nov 20, 2019 at 10:22 PM Tom Rini  wrote:
>>> On Wed, Nov 20, 2019 at 10:11:00AM +0800, Bin Meng wrote:
 Hi Tom,

 On Fri, Nov 15, 2019 at 4:21 PM Bin Meng  wrote:
> From: Lihua Zhao 
>
> Enhance do_bootm_vxworks() to support Linux compatible standard DTB
> for ARM and PPC, when the least significant bit of flags in VxWorks
> bootargs is set. Otherwise it falls back to the existing bootm flow
> which is now legacy.
>
> Signed-off-by: Lihua Zhao 
> Signed-off-by: Bin Meng 
> Reviewed-by: Bin Meng 
> ---
>
>  common/bootm_os.c  | 39 +--
>  doc/README.vxworks | 13 +
>  include/vxworks.h  |  3 +++
>  3 files changed, 53 insertions(+), 2 deletions(-)
 It would be good if you pick this up for v2020.01. Thanks!
>>> OK, thanks.  I'll put this on my TODO list for soon.
>> A gentle ping?
> So the issue now is that this causes size growth and then link failure
> on tbs2910.  And I don't think "boot modern VxWorks kernels" is a new
> CONFIG option I want to see.  So I'm not quite sure what to do here yet.
> Soeren, do you care about VxWorks support on this platform?  Thanks!
>
I'm not aware of any user of VxWorks on tbs2910. So would be OK for me
to disable CONFIG_BOOTM_VXWORKS in tbs2910_defconfig.

Do you want me to send a patch for this? Has this to go through the imx
tree? I'm also happy to send an Acked-by instead, if this makes things
easier.

Regards,
Soeren



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Re: [U-Boot] [PATCH] configs: stih410-b2260: Enable DM_ETH flag

2019-11-27 Thread Patrick DELAUNAY
Hi

> From: Patrice CHOTARD 
> Sent: vendredi 15 novembre 2019 11:57
> 
> This patch allows to fix the following compilation warning:
> 
> = WARNING == This board
> does not use CONFIG_DM_ETH (Driver Model for Ethernet drivers). Please
> update the board to use CONFIG_DM_ETH before the v2020.07 release. Failure to
> update by the deadline may result in board removal.
> See doc/driver-model/migration.rst for more info.
> 
> 
> Signed-off-by: Patrice Chotard 

Applied to u-boot-stm32/master, thanks!

-- 
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Re: [U-Boot] [PATCH 1/3] ARM: dts: stm32: DT alignment with kernel v5.3

2019-11-27 Thread Patrick DELAUNAY
Hi,

> From: Patrick DELAUNAY 
> Sent: mercredi 6 novembre 2019 16:17
> 
> Device tree and binding alignment with kernel v5.3 and converted to SPDX.
> 
> Signed-off-by: Patrick Delaunay 
> ---

Applied to u-boot-stm32/master, thanks!

-- 
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Re: [U-Boot] [PATCH 2/3] ARM: dts: stm32: DT alignment with kernel v5.4-rc4

2019-11-27 Thread Patrick DELAUNAY
Hi,

> From: Patrick DELAUNAY 
> Sent: mercredi 6 novembre 2019 16:17
> 
> Device tree and binding alignment with kernel v5.4-rc4
> 
> Signed-off-by: Patrick Delaunay 
> ---

Applied to u-boot-stm32/master, thanks!

-- 
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Re: [U-Boot] [PATCH 3/3] ARM: dts: stm32: update eMMC configuration for stm32mp157c-ev1

2019-11-27 Thread Patrick DELAUNAY
Hi

> From: Patrick DELAUNAY 
> Sent: mercredi 6 novembre 2019 16:17
> 
> Update the sdmmc2 node for eMMC support on eval board stm32mp157c-ev1.
> - update slew-rate for pin configuration
> - update "vqmmc-supply"
> - remove "st,sig-dir"
> - add mandatory "pinctrl-names"
> - add "mmc-ddr-3_3v"
> 
> This patch solve the eMMC detection issue for command "mmc dev 1".
> 
> Signed-off-by: Patrick Delaunay 
> ---

Applied to u-boot-stm32/master, thanks!

-- 
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Re: [U-Boot] [PATCH v3 11/15] stm32mp1: activate DFU support and command MTD

2019-11-27 Thread Patrick DELAUNAY
Hi,

> From: Patrick DELAUNAY 
> Sent: lundi 14 octobre 2019 09:28
> 
> Add support of DFU for MMC, MTD, RAM and MTD command.
> 
> Signed-off-by: Patrick Delaunay 
> ---

Applied to u-boot-stm32/master, thanks!

-- 
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Re: [U-Boot] [PATCH v3 12/15] stm32mp1: activate SET_DFU_ALT_INFO

2019-11-27 Thread Patrick DELAUNAY
Hi,

> From: Patrick DELAUNAY 
> Sent: lundi 14 octobre 2019 09:28
> 
> Generate automatically dfu_alt_info for the supported device.
> The simple command "dfu 0" allows to start the dfu stack on usb 0 for the
> supported devices:
> - dfu mtd for nand0
> - dfu mtd for nor0
> - dfu mmc for SDCard
> - dfu mmc for eMMC
> - dfu ram for images in DDR
> 
> The DUF alternate use the "part", "partubi" and "mmcpart" options to select 
> the
> correct MTD or GPT partition or the eMMC hw boot partition.
> 
> Signed-off-by: Patrick Delaunay 
> ---

Applied to u-boot-stm32/master, thanks!

-- 
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Re: [U-Boot] [PATCH v3 13/15] stm32mp1: configs: activate CONFIG_MTD_SPI_NAND

2019-11-27 Thread Patrick DELAUNAY
Hi,

> From: Patrick DELAUNAY 
> Sent: lundi 14 octobre 2019 09:28
> 
> Activate the support of SPI NAND in stm32mp1 U-Boot.
> 
> Signed-off-by: Patrick Delaunay 
> ---

Applied to u-boot-stm32/master, thanks!

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Re: [U-Boot] [PATCH v3 14/15] stm32mp1: board: add spi nand support

2019-11-27 Thread Patrick DELAUNAY
Hi,

> From: Patrick DELAUNAY 
> Sent: lundi 14 octobre 2019 09:28
> 
> This patch adds the support of the spi nand device in mtdparts command and in
> dfu_alt_info.
> 
> Signed-off-by: Patrick Delaunay 
> ---

Applied to u-boot-stm32/master, thanks!

-- 
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Re: [U-Boot] [PATCH v3 15/15] stm32mp1: add support for virtual partition read

2019-11-27 Thread Patrick DELAUNAY
Hi,

> From: Patrick DELAUNAY 
> Sent: lundi 14 octobre 2019 09:28
> 
> Add read for OTP and PMIC NVM with alternates on virtual DFU device.
> 
> Serie-cc: Boris Brezillon 
> Signed-off-by: Patrick Delaunay 
> ---

Applied to u-boot-stm32/master, thanks!

-- 
Patrick
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[U-Boot] [PULL] Pull request: u-boot-stm32 u-boot-stm32-20191126

2019-11-27 Thread Patrick DELAUNAY
Hi Tom

Please pull the STM32 related patches for u-boot-stm32-20191126

With the following changes:
- Solve warning for stih410-b2260
- Device tree alignment on v5.4-rc4 for all stm32 boards
- Correct the eMMC pin configuration on stm32mp157c-ev1
- Add DFU and SPI-NAND support for stm32mp1 board

Travis CI status:
 https://travis-ci.org/patrickdelaunay/u-boot/builds/617166580

Thanks,
Patrick

The following changes since commit 4b19b89ca4a866b7baa642533e6dbd67cd832d27:

  Merge tag 'rpi-next-2020.01' of https://github.com/mbgg/u-boot (2019-11-25 
12:56:27 -0500)

are available in the Git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git 
tags/u-boot-stm32-20191126

for you to fetch changes up to b4fee1610864036c8363e552f8547e99b1100f0b:

  stm32mp1: add support for virtual partition read (2019-11-26 10:14:35 +0100)


- Solve warning for stih410-b2260
- Device tree alignment on v5.4-rc4 for all stm32 boards
- Correct the eMMC pin configuration on stm32mp157c-ev1
- Add DFU and SPI-NAND support for stm32mp1 board


Patrice Chotard (1):
  configs: stih410-b2260: Enable DM_ETH flag

Patrick Delaunay (8):
  ARM: dts: stm32: DT alignment with kernel v5.3
  ARM: dts: stm32: DT alignment with kernel v5.4-rc4
  ARM: dts: stm32: update eMMC configuration for stm32mp157c-ev1
  stm32mp1: activate DFU support and command MTD
  stm32mp1: activate SET_DFU_ALT_INFO
  stm32mp1: configs: activate CONFIG_MTD_SPI_NAND
  stm32mp1: board: add spi nand support
  stm32mp1: add support for virtual partition read

 arch/arm/dts/st-pincfg.h   |   1 +
 arch/arm/dts/stm32429i-eval.dts|  29 --
 arch/arm/dts/stm32746g-eval.dts| 105 
+
 arch/arm/dts/stm32f4-pinctrl.dtsi  |  38 
+---
 arch/arm/dts/stm32f429-disco.dts   |  40 
++
 arch/arm/dts/stm32f429-pinctrl.dtsi|  38 
+---
 arch/arm/dts/stm32f429.dtsi| 127 
+
 arch/arm/dts/stm32f469-disco.dts   |  39 
++---
 arch/arm/dts/stm32f469-pinctrl.dtsi|  39 
+
 arch/arm/dts/stm32f469.dtsi|   2 +-
 arch/arm/dts/stm32f746-disco.dts   |  39 
++---
 arch/arm/dts/stm32f746.dtsi|  54 

 arch/arm/dts/stm32f769-disco.dts   |  43 
+---
 arch/arm/dts/stm32h7-u-boot.dtsi   |  41 
+++
 arch/arm/dts/stm32h743-pinctrl.dtsi|  83 
+
 arch/arm/dts/stm32h743.dtsi|  69 
+++
 arch/arm/dts/stm32h743i-disco-u-boot.dtsi  |   8 --
 arch/arm/dts/stm32h743i-disco.dts  |  76 

 arch/arm/dts/stm32h743i-eval-u-boot.dtsi   |   9 ---
 arch/arm/dts/stm32h743i-eval.dts   |  42 
++-
 arch/arm/dts/stm32mp157-pinctrl.dtsi   |  59 

 arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi |   5 +++-
 arch/arm/dts/stm32mp157a-dk1.dts   | 129 
+++
 arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi   |   5 +++-
 arch/arm/dts/stm32mp157c-ed1.dts   |  51 
+++---
 arch/arm/dts/stm32mp157c-ev1.dts   |   3 ++-
 arch/arm/dts/stm32mp157c.dtsi  |  26 
 board/st/stm32mp1/README   | 111 
++
 board/st/stm32mp1/stm32mp1.c   | 164 
+++--
 configs/stih410-b2260_defconfig|   1 +
 configs/stm32mp15_basic_defconfig  |   6 +
 configs/stm32mp15_optee_defconfig  |   6 +
 configs/stm32mp15_trusted_defconfig|   6 +
 include/configs/stm32mp1.h |  42 
+--
 include/dt-bindings/clock/stm32fx-clock.h  |   9 ---
 include/dt-bindings/mfd/st,stpmic1.h   |   4 +++
 include/dt-bindings/mfd/stm32f7-rcc.h  |   1 +
 include/dt-bindings/mfd/stm32h7-rcc.h  |   2 +-
 38 files changed, 1014 inse

[U-Boot] [PATCH] ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT

2019-11-27 Thread Alex Marginean
Hardware comes out of reset with implicit values, but these are outside
the accepted range for Layerscape gen 3 chassis spec used on LS1028A.
Allocate different IDs and fix up Linux DT to use them.

Signed-off-by: Alex Marginean 
---
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c   |   9 ++
 .../asm/arch-fsl-layerscape/stream_id_lsch3.h |   8 ++
 board/freescale/ls1028a/ls1028a.c | 106 ++
 3 files changed, 123 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index e993209593..1e7e46e88a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -421,6 +421,12 @@ static void fdt_disable_multimedia(void *blob, unsigned 
int svr)
 }
 #endif
 
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+__weak void fdt_fixup_ecam(void *blob)
+{
+}
+#endif
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -485,4 +491,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_ARCH_LS1028A
fdt_disable_multimedia(blob, svr);
 #endif
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+   fdt_fixup_ecam(blob);
+#endif
 }
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index 94ea99a349..01d362d183 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -42,6 +42,10 @@
  * -the MC is responsible for allocating and setting up 'isolation context
  *  IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
  *
+ *  - ECAM (integrated PCI)
+ * - U-Boot applies the value here to HW and does DT fix-up for both
+ *   'iommu-map' and 'msi-map'
+ *
  * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for
  * each of the different bus masters.  The relationship between
  * the AMQ registers and stream IDs is defined in the table below:
@@ -98,6 +102,10 @@
 #define FSL_DPAA2_STREAM_ID_START  23
 #define FSL_DPAA2_STREAM_ID_END63
 
+/* PCI IEPs, this overlaps DPAA2 but these two are exclusive at least for now 
*/
+#define FSL_ECAM_STREAM_ID_START   32
+#define FSL_ECAM_STREAM_ID_END 63
+
 #define FSL_SEC_STREAM_ID  64
 #define FSL_SEC_JR1_STREAM_ID  65
 #define FSL_SEC_JR2_STREAM_ID  66
diff --git a/board/freescale/ls1028a/ls1028a.c 
b/board/freescale/ls1028a/ls1028a.c
index a9606b8865..1f5dc0d0b2 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -28,6 +28,52 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+
+#define ECAM_IERB_BASE 0x1f080ULL
+#define ECAM_IERB_OFFSET_NA-1
+#define ECAM_IERB_FUNC_CNT ARRAY_SIZE(ierb_offset)
+/* cache related transaction attributes for PCIe functions */
+#define ECAM_IERB_MSICAR   (ECAM_IERB_BASE + 0xa400)
+#define ECAM_IERB_MSICAR_VALUE 0x30
+
+/* offset of IERB config register per PCI function */
+static int ierb_offset[] = {
+   0x0800,
+   0x1800,
+   0x2800,
+   0x3800,
+   0x4800,
+   0x5800,
+   0x6800,
+   ECAM_IERB_OFFSET_NA,
+   0x0804,
+   0x0808,
+   0x1804,
+   0x1808,
+};
+
+/*
+ * Use a custom function for LS1028A, for now this is the only SoC with IERB
+ * and we're currently considering reorganizing IERB for future SoCs.
+ */
+static void set_ecam_icids(void)
+{
+   int i;
+
+   out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE);
+
+   for (i = 0; i < ECAM_IERB_FUNC_CNT; i++) {
+   if (ierb_offset[i] == ECAM_IERB_OFFSET_NA)
+   continue;
+
+   out_le32(ECAM_IERB_BASE + ierb_offset[i],
+FSL_ECAM_STREAM_ID_START + i);
+   }
+}
+
+#endif /* CONFIG_PCIE_ECAM_GENERIC */
+
 int config_board_mux(void)
 {
 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
@@ -88,6 +134,16 @@ int board_init(void)
 #endif
 
 #endif
+
+   /*
+* ICIDs for other hardware blocks are set really early on, before MMU
+* is set up.  For integrated PCI we need access to IERB which is not
+* part of CCSR, so we have to wait for MMU mappings to be applied
+*/
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+   set_ecam_icids();
+#endif
+
return 0;
 }
 
@@ -244,3 +300,53 @@ int checkboard(void)
return 0;
 }
 #endif
+
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+
+static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset,
+  const char *name, uint32_t idx, u32 val)
+{
+   val = cpu_to_be32(val);
+   return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name,
+  strlen(name),
+  idx * sizeof(val), &val,
+  s

Re: [U-Boot] [PATCH] ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT

2019-11-27 Thread Bin Meng
On Wed, Nov 27, 2019 at 9:58 PM Alex Marginean
 wrote:
>
> Hardware comes out of reset with implicit values, but these are outside
> the accepted range for Layerscape gen 3 chassis spec used on LS1028A.
> Allocate different IDs and fix up Linux DT to use them.
>
> Signed-off-by: Alex Marginean 
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/fdt.c   |   9 ++
>  .../asm/arch-fsl-layerscape/stream_id_lsch3.h |   8 ++
>  board/freescale/ls1028a/ls1028a.c | 106 ++
>  3 files changed, 123 insertions(+)
>

Reviewed-by: Bin Meng 
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Re: [U-Boot] [PATCH] bootm: vxworks: Support Linux compatible standard DTB for ARM and PPC

2019-11-27 Thread Tom Rini
On Wed, Nov 27, 2019 at 02:34:14PM +0100, Soeren Moch wrote:
> On 27.11.19 13:55, Tom Rini wrote:
> > On Wed, Nov 27, 2019 at 02:03:03PM +0800, Bin Meng wrote:
> >> Hi Tom,
> >>
> >> On Wed, Nov 20, 2019 at 10:22 PM Tom Rini  wrote:
> >>> On Wed, Nov 20, 2019 at 10:11:00AM +0800, Bin Meng wrote:
>  Hi Tom,
> 
>  On Fri, Nov 15, 2019 at 4:21 PM Bin Meng  wrote:
> > From: Lihua Zhao 
> >
> > Enhance do_bootm_vxworks() to support Linux compatible standard DTB
> > for ARM and PPC, when the least significant bit of flags in VxWorks
> > bootargs is set. Otherwise it falls back to the existing bootm flow
> > which is now legacy.
> >
> > Signed-off-by: Lihua Zhao 
> > Signed-off-by: Bin Meng 
> > Reviewed-by: Bin Meng 
> > ---
> >
> >  common/bootm_os.c  | 39 +--
> >  doc/README.vxworks | 13 +
> >  include/vxworks.h  |  3 +++
> >  3 files changed, 53 insertions(+), 2 deletions(-)
>  It would be good if you pick this up for v2020.01. Thanks!
> >>> OK, thanks.  I'll put this on my TODO list for soon.
> >> A gentle ping?
> > So the issue now is that this causes size growth and then link failure
> > on tbs2910.  And I don't think "boot modern VxWorks kernels" is a new
> > CONFIG option I want to see.  So I'm not quite sure what to do here yet.
> > Soeren, do you care about VxWorks support on this platform?  Thanks!
> >
> I'm not aware of any user of VxWorks on tbs2910. So would be OK for me
> to disable CONFIG_BOOTM_VXWORKS in tbs2910_defconfig.
> 
> Do you want me to send a patch for this? Has this to go through the imx
> tree? I'm also happy to send an Acked-by instead, if this makes things
> easier.

Thanks.  I'll post a patch shortly and you can ack it.

-- 
Tom


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[U-Boot] [RFC PATCH] ARM: reset: Move SYSRESET condition from Makefile into source file

2019-11-27 Thread Claudius Heine
In case CONFIG_SYSRESET is set, do_reset from reset.c will not be available
anywere, even if SYSRESET is disabled for SPL in the board specific header
file like this:

#if defined(CONFIG_SPL_BUILD)
#undef CONFIG_WDT
#undef CONFIG_WATCHDOG
#undef CONFIG_SYSRESET
#define CONFIG_HW_WATCHDOG
#endif

'do_reset' is called from SPL for instance from the panic handler in case
SPL_USB_SDP is enabled and PANIC_HANG is not set.

Setting PANIC_HANG would solve this issue, but it also changes the behavior
in case a panic occurs.

Signed-off-by: Claudius Heine 
---
 arch/arm/lib/Makefile | 2 --
 arch/arm/lib/reset.c  | 2 ++
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 9de9a9acee..763eb4498f 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -56,9 +56,7 @@ obj-y += interrupts_64.o
 else
 obj-y  += interrupts.o
 endif
-ifndef CONFIG_SYSRESET
 obj-y  += reset.o
-endif
 
 obj-y  += cache.o
 obj-$(CONFIG_SYS_ARM_CACHE_CP15)   += cache-cp15.o
diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c
index f3ea116e87..11e680be1d 100644
--- a/arch/arm/lib/reset.c
+++ b/arch/arm/lib/reset.c
@@ -22,6 +22,7 @@
 
 #include 
 
+#if !defined(CONFIG_SYSRESET)
 __weak void reset_misc(void)
 {
 }
@@ -40,3 +41,4 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
/*NOTREACHED*/
return 0;
 }
+#endif
-- 
2.21.0

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[U-Boot] [PATCH] tbs2910: Disable VxWorks image booting support

2019-11-27 Thread Tom Rini
There are currently no known users of this functionality on this
platform, disable it to prepare for additional VxWorks functionality
that would cause this platform to fail to link.

Cc: Soeren Moch 
Signed-off-by: Tom Rini 
---
 configs/tbs2910_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index ffe043678cdf..22fa0e138441 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -21,6 +21,7 @@ CONFIG_SYS_PROMPT="Matrix U-Boot> "
 CONFIG_CMD_BOOTZ=y
 # CONFIG_BOOTM_PLAN9 is not set
 # CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
 # CONFIG_CMD_FDT is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
-- 
2.17.1

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Re: [U-Boot] [PATCH] tbs2910: Disable VxWorks image booting support

2019-11-27 Thread Soeren Moch
On 27.11.19 15:23, Tom Rini wrote:
> There are currently no known users of this functionality on this
> platform, disable it to prepare for additional VxWorks functionality
> that would cause this platform to fail to link.
>
> Cc: Soeren Moch 
> Signed-off-by: Tom Rini 
Acked-by: Soeren Moch 

Thanks,
Soeren
> ---
>  configs/tbs2910_defconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
> index ffe043678cdf..22fa0e138441 100644
> --- a/configs/tbs2910_defconfig
> +++ b/configs/tbs2910_defconfig
> @@ -21,6 +21,7 @@ CONFIG_SYS_PROMPT="Matrix U-Boot> "
>  CONFIG_CMD_BOOTZ=y
>  # CONFIG_BOOTM_PLAN9 is not set
>  # CONFIG_BOOTM_RTEMS is not set
> +# CONFIG_BOOTM_VXWORKS is not set
>  # CONFIG_CMD_FDT is not set
>  CONFIG_CMD_MEMTEST=y
>  # CONFIG_CMD_FLASH is not set

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Re: [U-Boot] [PATCH] ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT

2019-11-27 Thread Michael Walle

Hi Alex,

Am 2019-11-27 14:57, schrieb Alex Marginean:

Hardware comes out of reset with implicit values, but these are outside
the accepted range for Layerscape gen 3 chassis spec used on LS1028A.
Allocate different IDs and fix up Linux DT to use them.

Signed-off-by: Alex Marginean 
---
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c   |   9 ++
 .../asm/arch-fsl-layerscape/stream_id_lsch3.h |   8 ++
 board/freescale/ls1028a/ls1028a.c | 106 ++


Doh :( is there no other place where to put this fixup? That would mean 
I

have to replicate this code for our custom board and so does every board
which uses the LS1028A. Shouldn't this be in the SoC LS1028A 
architecture

specific code?


 3 files changed, 123 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index e993209593..1e7e46e88a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -421,6 +421,12 @@ static void fdt_disable_multimedia(void *blob,
unsigned int svr)
 }
 #endif

+#ifdef CONFIG_PCIE_ECAM_GENERIC
+__weak void fdt_fixup_ecam(void *blob)
+{
+}
+#endif
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -485,4 +491,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_ARCH_LS1028A
fdt_disable_multimedia(blob, svr);
 #endif
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+   fdt_fixup_ecam(blob);
+#endif
 }
diff --git
a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index 94ea99a349..01d362d183 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -42,6 +42,10 @@
  * -the MC is responsible for allocating and setting up 'isolation 
context
  *  IDs (ICIDs) based on the allocated stream IDs for all DPAA2 
devices.

  *
+ *  - ECAM (integrated PCI)
+ * - U-Boot applies the value here to HW and does DT fix-up for 
both

+ *   'iommu-map' and 'msi-map'
+ *


mhh this is not entirely true, because it is the board code which does 
the fixup,

which may lead to some confusion.

  * On Chasis-3 SoCs stream IDs are programmed in AMQ registers 
(32-bits) for

  * each of the different bus masters.  The relationship between
  * the AMQ registers and stream IDs is defined in the table below:
@@ -98,6 +102,10 @@
 #define FSL_DPAA2_STREAM_ID_START  23
 #define FSL_DPAA2_STREAM_ID_END63

+/* PCI IEPs, this overlaps DPAA2 but these two are exclusive at least
for now */
+#define FSL_ECAM_STREAM_ID_START   32
+#define FSL_ECAM_STREAM_ID_END 63
+
 #define FSL_SEC_STREAM_ID  64
 #define FSL_SEC_JR1_STREAM_ID  65
 #define FSL_SEC_JR2_STREAM_ID  66
diff --git a/board/freescale/ls1028a/ls1028a.c
b/board/freescale/ls1028a/ls1028a.c
index a9606b8865..1f5dc0d0b2 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -28,6 +28,52 @@

 DECLARE_GLOBAL_DATA_PTR;

+#ifdef CONFIG_PCIE_ECAM_GENERIC
+
+#define ECAM_IERB_BASE 0x1f080ULL
+#define ECAM_IERB_OFFSET_NA-1
+#define ECAM_IERB_FUNC_CNT ARRAY_SIZE(ierb_offset)
+/* cache related transaction attributes for PCIe functions */
+#define ECAM_IERB_MSICAR   (ECAM_IERB_BASE + 0xa400)
+#define ECAM_IERB_MSICAR_VALUE 0x30
+
+/* offset of IERB config register per PCI function */
+static int ierb_offset[] = {
+   0x0800,
+   0x1800,
+   0x2800,
+   0x3800,
+   0x4800,
+   0x5800,
+   0x6800,
+   ECAM_IERB_OFFSET_NA,
+   0x0804,
+   0x0808,
+   0x1804,
+   0x1808,
+};
+
+/*
+ * Use a custom function for LS1028A, for now this is the only SoC 
with IERB

+ * and we're currently considering reorganizing IERB for future SoCs.
+ */
+static void set_ecam_icids(void)
+{
+   int i;
+
+   out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE);
+
+   for (i = 0; i < ECAM_IERB_FUNC_CNT; i++) {
+   if (ierb_offset[i] == ECAM_IERB_OFFSET_NA)
+   continue;
+
+   out_le32(ECAM_IERB_BASE + ierb_offset[i],
+FSL_ECAM_STREAM_ID_START + i);
+   }
+}
+
+#endif /* CONFIG_PCIE_ECAM_GENERIC */
+
 int config_board_mux(void)
 {
 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
@@ -88,6 +134,16 @@ int board_init(void)
 #endif

 #endif
+
+   /*
+	 * ICIDs for other hardware blocks are set really early on, before 
MMU

+* is set up.  For integrated PCI we need access to IERB which is not
+* part of CCSR, so we have to wait for MMU mappings to be applied
+*/
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+   set_ecam_icids();
+#endif
+
return 0;
 }

@@ -244,3 +300,53 @@ int checkboard(void)
return 0;
 }
 #endif
+
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+
+static int fdt_setprop_inplace_i

Re: [U-Boot] [PATCH v1 3/4] dfu: Add optional timeout parameter

2019-11-27 Thread Andy Shevchenko
On Wed, Nov 27, 2019 at 11:56:15AM +0100, Lukasz Majewski wrote:

> Thank you for your work on enhancing DFU. The patch series is generally
> Ok.
> 
> Please find some minor comments/requests below.

Thank you for review, my answers below.

> > +#ifdef CONFIG_DFU_TIMEOUT
> > +   dfu_set_timeout(value * 1000);
> > +#endif

(1)

> > +#ifdef CONFIG_DFU_TIMEOUT
> > +void dfu_set_timeout(unsigned long timeout)
> > +{
> > +   dfu_timeout = timeout;
> > +}
> 
> I do guess that dfu_set_timeout() is not yet used in this patch series?

I think you missed (1) by some reason.

> Please add some description and example of this new option / feature to
> ./doc/README.dfu file.

Will do for v2.

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Andy Shevchenko


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Re: [U-Boot] [PATCH 1/4] mmc: meson-gx: Fix tx phase in the tuning process

2019-11-27 Thread Anand Moon
Hi Neil,

On Wed, 27 Nov 2019 at 18:30, Neil Armstrong  wrote:
>
> Hi,
>
> On 26/11/2019 22:12, Anand Moon wrote:
> > odroid n2 eMMC module would failed to boot up,
> > because of TX phase clk failure, fix the typo in
> > TX phase macro to help tune correct clk freqency.
> >
> > Before these changes.
> >   clock is enabled (380953Hz)
> >   clock is enabled (2500Hz)
> > after these changes
> >   clock is enabled (380953Hz)
> >   clock is enabled (2500Hz)
> >   clock is enabled (5200Hz)
> >   clock is enabled (5200Hz)
> >   clock is enabled (5200Hz)
> >
> > Signed-off-by: Anand Moon 
> > ---
> > Tested on
> > new orange - eMMC AJNB4R 14.6 GiB MMC 5.1
> > old back   - eMMC CGND3R 58.2 GiB MMC 5.0
> > ---
> >  drivers/mmc/meson_gx_mmc.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> > index 031cc79ccb..87bea2888b 100644
> > --- a/drivers/mmc/meson_gx_mmc.c
> > +++ b/drivers/mmc/meson_gx_mmc.c
> > @@ -53,7 +53,7 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> >   meson_mmc_clk |= CLK_CO_PHASE_180;
> >
> >   /* 180 phase tx clock */
> > - meson_mmc_clk |= CLK_TX_PHASE_000;
> > + meson_mmc_clk |= CLK_TX_PHASE_180;
> >
> >   /* clock settings */
> >   meson_mmc_clk |= clk_src;
> >
>
> I don't understand what this change helps, the linux driver sets the TX phase 
> to 0,
> why 180 would help here ?
>
> Neil

I narrow down to this small changes, without this small change
it fails to detect the eMMC module. See the below log.

U-Boot 2020.01-rc3-00082-g4b19b89ca4-dirty (Nov 27 2019 - 18:56:37
+0530) odroid-n2

Model: Hardkernel ODROID-N2
SoC:   Amlogic Meson G12B (S922X) Revision 29:a (40:2)
DRAM:  3.8 GiB
mmc_bind: alias ret=-2, devnum=-1
mmc_bind: alias ret=-2, devnum=-1
MMC:   clock is enabled (380953Hz)
clock is enabled (380953Hz)
sd@ffe05000: 0, mmc@ffe07000: 1
In:serial@3000
Out:   serial@3000
Err:   serial@3000
Net:   gpio_request_tail: Node 'ethernet@ff3f', property
'snps,reset-gpio', failed to request GPIO index 0: -2

Warning: ethernet@ff3f (eth0) using random MAC address - 26:1e:2a:2a:67:d6
eth0: ethernet@ff3f
Hit any key to stop autoboot:  0
clock is disabled (0Hz)
regulator_common_set_enable: dev='regulator-tflash_vdd', enable=1,
delay=0, has_gpio=1
regulator_common_set_enable: done
clock is enabled (380953Hz)
Card did not respond to voltage select!
gpio_request_tail: Node 'regulator-vcc_3v3', property 'gpio', failed
to request GPIO index 0: -2
Regulator 'regulator-vcc_3v3' optional enable GPIO - not found! Error: -2
gpio_request_tail: Node 'regulator-flash_1v8', property 'gpio', failed
to request GPIO index 0: -2
Regulator 'regulator-flash_1v8' optional enable GPIO - not found! Error: -2
clock is disabled (0Hz)
regulator_common_set_enable: dev='regulator-vcc_3v3', enable=1,
delay=0, has_gpio=0
clock is enabled (380953Hz)
clock is enabled (2500Hz)
unable to select a mode
switch to partitions #0, OK
mmc1(part 0) is current device
** No partition table - mmc 1 **
MMC Device 2 not found
no mmc device at slot 2
starting USB...
Bus usb@ff50: gpio_request_tail: Node 'regulator-vcc_5v', property
'gpio', failed to request GPIO index 0: -2
Regulator 'regulator-vcc_5v' optional enable GPIO - not found! Error: -2
regulator_common_set_enable: dev='regulator-usb_pwr_en', enable=1,
delay=0, has_gpio=1
regulator_common_set_enable: done
Register 3000140 NbrPorts 3
Starting the controller
USB XHCI 1.10
scanning bus usb@ff50 for devices... 1 USB Device(s) found
   scanning usb for storage devices... 0 Storage Device(s) found

-Anand
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Re: [U-Boot] SPDX header might be wrong in 4 files from Android Open Source Project

2019-11-27 Thread Alex Deymo
Le lun. 25 nov. 2019 à 17:20, Igor Opaniuk  a
écrit :

> + Alex Deymo
>
> Hi Zdenek
>
> On Mon, Nov 25, 2019 at 6:05 PM zdenek.bou...@siemens.com
>  wrote:
> >
> > Hello,
> >
> > SPDX-License-Identifier: BSD-3-Clause might be wrong in the following 4
> files from Android Open Source Project (AOSP):
> >
> > include/android_bootloader_message.h
> > include/sparse_format.h
> > include/dt_table.h
> > include/android_image.h
>
> they were re-licensed by one of the Google employees specifically for
> U-boot [1].
>

That's correct, I tried to make this re-licensing step explicit in the
commit message. I sent the patches to add these headers re-licensed to
BSD-3 after checking with our Opensource Releasing Team and they were OK
with it in these particular cases. The original headers were Copyright "The
Android Open Source Project".

If you need help importing other AOSP headers with BSD-3 license instead of
the one we normally use in AOSP (Apache 2) I might be able to help with
that, but I do need to check with the team first.

Best regards,
deymo@
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Re: [U-Boot] [PATCH 4/4] board: amlogic: Add missing config option

2019-11-27 Thread Anand Moon
Hi Neil,

On Wed, 27 Nov 2019 at 18:25, Neil Armstrong  wrote:
>
> Hi,
>
> On 26/11/2019 22:12, Anand Moon wrote:
> > Add missing config option CONFIG_MESON_GXBB and CONFIG_SYS_BOARD,
> > for odroid-c2 and nanopi k2 board
> >
> > Signed-off-by: Anand Moon 
> > ---
> >  configs/nanopi-k2_defconfig | 2 ++
> >  configs/odroid-c2_defconfig | 2 ++
> >  2 files changed, 4 insertions(+)
> >
> > diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig
> > index 7bdeb7906a..3d6265c587 100644
> > --- a/configs/nanopi-k2_defconfig
> > +++ b/configs/nanopi-k2_defconfig
> > @@ -1,6 +1,8 @@
> >  CONFIG_ARM=y
> > +CONFIG_SYS_BOARD="p200"
> >  CONFIG_ARCH_MESON=y
> >  CONFIG_SYS_TEXT_BASE=0x0100
> > +CONFIG_MESON_GXBB=y
> >  CONFIG_ENV_SIZE=0x2000
> >  CONFIG_NR_DRAM_BANKS=1
> >  CONFIG_DEBUG_UART_BASE=0xc81004c0
> > diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
> > index 1f5a52c57c..700c871918 100644
> > --- a/configs/odroid-c2_defconfig
> > +++ b/configs/odroid-c2_defconfig
> > @@ -1,6 +1,8 @@
> >  CONFIG_ARM=y
> > +CONFIG_SYS_BOARD="p200"
> >  CONFIG_ARCH_MESON=y
> >  CONFIG_SYS_TEXT_BASE=0x0100
> > +CONFIG_MESON_GXBB=y
> >  CONFIG_ENV_SIZE=0x2000
> >  CONFIG_NR_DRAM_BANKS=1
> >  CONFIG_DEBUG_UART_BASE=0xc81004c0
> >
>
> These are not present since they are the default values, thus not exported in 
> savedefconfig.
>
> Neil

You can ignore and drop this changes.

-Anand
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Re: [U-Boot] [PATCH] ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT

2019-11-27 Thread Alexandru Marginean

Hi Michael,

On 11/27/2019 3:33 PM, Michael Walle wrote:

Hi Alex,

Am 2019-11-27 14:57, schrieb Alex Marginean:

Hardware comes out of reset with implicit values, but these are outside
the accepted range for Layerscape gen 3 chassis spec used on LS1028A.
Allocate different IDs and fix up Linux DT to use them.

Signed-off-by: Alex Marginean 
---
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c   |   9 ++
 .../asm/arch-fsl-layerscape/stream_id_lsch3.h |   8 ++
 board/freescale/ls1028a/ls1028a.c | 106 ++


Doh :( is there no other place where to put this fixup? That would mean I
have to replicate this code for our custom board and so does every board
which uses the LS1028A. Shouldn't this be in the SoC LS1028A architecture
specific code?


Yeah, you're right about that.
It should probably go into armv8/fsl-layerscape/icid.c or somewhere 
around there.

I'll send a v2.

Thanks!
Alex




 3 files changed, 123 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index e993209593..1e7e46e88a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -421,6 +421,12 @@ static void fdt_disable_multimedia(void *blob,
unsigned int svr)
 }
 #endif

+#ifdef CONFIG_PCIE_ECAM_GENERIC
+__weak void fdt_fixup_ecam(void *blob)
+{
+}
+#endif
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -485,4 +491,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_ARCH_LS1028A
 fdt_disable_multimedia(blob, svr);
 #endif
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+    fdt_fixup_ecam(blob);
+#endif
 }
diff --git
a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index 94ea99a349..01d362d183 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -42,6 +42,10 @@
  * -the MC is responsible for allocating and setting up 
'isolation context
  *  IDs (ICIDs) based on the allocated stream IDs for all DPAA2 
devices.

  *
+ *  - ECAM (integrated PCI)
+ * - U-Boot applies the value here to HW and does DT fix-up for both
+ *   'iommu-map' and 'msi-map'
+ *


mhh this is not entirely true, because it is the board code which
does the fixup, which may lead to some confusion. >
  * On Chasis-3 SoCs stream IDs are programmed in AMQ registers 
(32-bits) for

  * each of the different bus masters.  The relationship between
  * the AMQ registers and stream IDs is defined in the table below:
@@ -98,6 +102,10 @@
 #define FSL_DPAA2_STREAM_ID_START    23
 #define FSL_DPAA2_STREAM_ID_END    63

+/* PCI IEPs, this overlaps DPAA2 but these two are exclusive at least
for now */
+#define FSL_ECAM_STREAM_ID_START    32
+#define FSL_ECAM_STREAM_ID_END    63
+
 #define FSL_SEC_STREAM_ID    64
 #define FSL_SEC_JR1_STREAM_ID    65
 #define FSL_SEC_JR2_STREAM_ID    66
diff --git a/board/freescale/ls1028a/ls1028a.c
b/board/freescale/ls1028a/ls1028a.c
index a9606b8865..1f5dc0d0b2 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -28,6 +28,52 @@

 DECLARE_GLOBAL_DATA_PTR;

+#ifdef CONFIG_PCIE_ECAM_GENERIC
+
+#define ECAM_IERB_BASE    0x1f080ULL
+#define ECAM_IERB_OFFSET_NA    -1
+#define ECAM_IERB_FUNC_CNT    ARRAY_SIZE(ierb_offset)
+/* cache related transaction attributes for PCIe functions */
+#define ECAM_IERB_MSICAR    (ECAM_IERB_BASE + 0xa400)
+#define ECAM_IERB_MSICAR_VALUE    0x30
+
+/* offset of IERB config register per PCI function */
+static int ierb_offset[] = {
+    0x0800,
+    0x1800,
+    0x2800,
+    0x3800,
+    0x4800,
+    0x5800,
+    0x6800,
+    ECAM_IERB_OFFSET_NA,
+    0x0804,
+    0x0808,
+    0x1804,
+    0x1808,
+};
+
+/*
+ * Use a custom function for LS1028A, for now this is the only SoC 
with IERB

+ * and we're currently considering reorganizing IERB for future SoCs.
+ */
+static void set_ecam_icids(void)
+{
+    int i;
+
+    out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE);
+
+    for (i = 0; i < ECAM_IERB_FUNC_CNT; i++) {
+    if (ierb_offset[i] == ECAM_IERB_OFFSET_NA)
+    continue;
+
+    out_le32(ECAM_IERB_BASE + ierb_offset[i],
+ FSL_ECAM_STREAM_ID_START + i);
+    }
+}
+
+#endif /* CONFIG_PCIE_ECAM_GENERIC */
+
 int config_board_mux(void)
 {
 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
@@ -88,6 +134,16 @@ int board_init(void)
 #endif

 #endif
+
+    /*
+ * ICIDs for other hardware blocks are set really early on, 
before MMU
+ * is set up.  For integrated PCI we need access to IERB which is 
not

+ * part of CCSR, so we have to wait for MMU mappings to be applied
+ */
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+    set_ecam_icids();
+#endif
+
 return 0;
 }

@@ -244,3 +300,53 @@ int checkboard(void)
 return 0;
 }
 #endif
+
+#ifdef CONF

Re: [U-Boot] [RFC PATCH] ARM: reset: Move SYSRESET condition from Makefile into source file

2019-11-27 Thread Marek Vasut
On 11/27/19 3:20 PM, Claudius Heine wrote:
> In case CONFIG_SYSRESET is set, do_reset from reset.c will not be available
> anywere, even if SYSRESET is disabled for SPL in the board specific header
> file like this:
> 
> #if defined(CONFIG_SPL_BUILD)
> #undef CONFIG_WDT
> #undef CONFIG_WATCHDOG
> #undef CONFIG_SYSRESET
> #define CONFIG_HW_WATCHDOG
> #endif
> 
> 'do_reset' is called from SPL for instance from the panic handler in case
> SPL_USB_SDP is enabled and PANIC_HANG is not set.
> 
> Setting PANIC_HANG would solve this issue, but it also changes the behavior
> in case a panic occurs.
> 
> Signed-off-by: Claudius Heine 
> ---
>  arch/arm/lib/Makefile | 2 --
>  arch/arm/lib/reset.c  | 2 ++
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
> index 9de9a9acee..763eb4498f 100644
> --- a/arch/arm/lib/Makefile
> +++ b/arch/arm/lib/Makefile
> @@ -56,9 +56,7 @@ obj-y   += interrupts_64.o
>  else
>  obj-y+= interrupts.o
>  endif
> -ifndef CONFIG_SYSRESET
>  obj-y+= reset.o
> -endif
>  
>  obj-y+= cache.o
>  obj-$(CONFIG_SYS_ARM_CACHE_CP15) += cache-cp15.o
> diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c
> index f3ea116e87..11e680be1d 100644
> --- a/arch/arm/lib/reset.c
> +++ b/arch/arm/lib/reset.c
> @@ -22,6 +22,7 @@
>  
>  #include 
>  
> +#if !defined(CONFIG_SYSRESET)
>  __weak void reset_misc(void)
>  {
>  }
> @@ -40,3 +41,4 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * 
> const argv[])
>   /*NOTREACHED*/
>   return 0;
>  }
> +#endif

Does this mean there's now one huge ifdef around the entire source file?
That's odd.
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Re: [U-Boot] [PATCH v1 3/4] dfu: Add optional timeout parameter

2019-11-27 Thread Lukasz Majewski
Hi Andy,

> On Wed, Nov 27, 2019 at 11:56:15AM +0100, Lukasz Majewski wrote:
> 
> > Thank you for your work on enhancing DFU. The patch series is
> > generally Ok.
> > 
> > Please find some minor comments/requests below.  
> 
> Thank you for review, my answers below.
> 
> > > +#ifdef CONFIG_DFU_TIMEOUT
> > > + dfu_set_timeout(value * 1000);
> > > +#endif  
> 
> (1)
> 
> > > +#ifdef CONFIG_DFU_TIMEOUT
> > > +void dfu_set_timeout(unsigned long timeout)
> > > +{
> > > + dfu_timeout = timeout;
> > > +}  
> > 
> > I do guess that dfu_set_timeout() is not yet used in this patch
> > series?  
> 
> I think you missed (1) by some reason.

Right. Thanks for pointing this out.

> 
> > Please add some description and example of this new option /
> > feature to ./doc/README.dfu file.  
> 
> Will do for v2.
> 

Thanks, appreciated.


Best regards,

Lukasz Majewski

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Re: [U-Boot] [RFC PATCH] ARM: reset: Move SYSRESET condition from Makefile into source file

2019-11-27 Thread Claudius Heine
Hi Marek,

On 27/11/2019 15.47, Marek Vasut wrote:
> On 11/27/19 3:20 PM, Claudius Heine wrote:
>> In case CONFIG_SYSRESET is set, do_reset from reset.c will not be available
>> anywere, even if SYSRESET is disabled for SPL in the board specific header
>> file like this:
>>
>> #if defined(CONFIG_SPL_BUILD)
>> #undef CONFIG_WDT
>> #undef CONFIG_WATCHDOG
>> #undef CONFIG_SYSRESET
>> #define CONFIG_HW_WATCHDOG
>> #endif
>>
>> 'do_reset' is called from SPL for instance from the panic handler in case
>> SPL_USB_SDP is enabled and PANIC_HANG is not set.
>>
>> Setting PANIC_HANG would solve this issue, but it also changes the behavior
>> in case a panic occurs.
>>
>> Signed-off-by: Claudius Heine 
>> ---
>>  arch/arm/lib/Makefile | 2 --
>>  arch/arm/lib/reset.c  | 2 ++
>>  2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
>> index 9de9a9acee..763eb4498f 100644
>> --- a/arch/arm/lib/Makefile
>> +++ b/arch/arm/lib/Makefile
>> @@ -56,9 +56,7 @@ obj-y  += interrupts_64.o
>>  else
>>  obj-y   += interrupts.o
>>  endif
>> -ifndef CONFIG_SYSRESET
>>  obj-y   += reset.o
>> -endif
>>  
>>  obj-y   += cache.o
>>  obj-$(CONFIG_SYS_ARM_CACHE_CP15)+= cache-cp15.o
>> diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c
>> index f3ea116e87..11e680be1d 100644
>> --- a/arch/arm/lib/reset.c
>> +++ b/arch/arm/lib/reset.c
>> @@ -22,6 +22,7 @@
>>  
>>  #include 
>>  
>> +#if !defined(CONFIG_SYSRESET)
>>  __weak void reset_misc(void)
>>  {
>>  }
>> @@ -40,3 +41,4 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * 
>> const argv[])
>>  /*NOTREACHED*/
>>  return 0;
>>  }
>> +#endif
> 
> Does this mean there's now one huge ifdef around the entire source file?
> That's odd.

Right. Other suggestions?

Maybe having 'do_reset' here as a weak instead, so that sysreset can
overwrite it? But then the other definitions in arch/*/lib/reset.c
should probably be the same for consistency sake?

I tried with this patch not to change anything in case SYSRESET is
enabled too much and since the file isn't too large I thought that would
be ok for now.

regards

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Re: [U-Boot] [RFC PATCH] ARM: reset: Move SYSRESET condition from Makefile into source file

2019-11-27 Thread Marek Vasut
On 11/27/19 4:09 PM, Claudius Heine wrote:
> Hi Marek,
> 
> On 27/11/2019 15.47, Marek Vasut wrote:
>> On 11/27/19 3:20 PM, Claudius Heine wrote:
>>> In case CONFIG_SYSRESET is set, do_reset from reset.c will not be available
>>> anywere, even if SYSRESET is disabled for SPL in the board specific header
>>> file like this:
>>>
>>> #if defined(CONFIG_SPL_BUILD)
>>> #undef CONFIG_WDT
>>> #undef CONFIG_WATCHDOG
>>> #undef CONFIG_SYSRESET
>>> #define CONFIG_HW_WATCHDOG
>>> #endif
>>>
>>> 'do_reset' is called from SPL for instance from the panic handler in case
>>> SPL_USB_SDP is enabled and PANIC_HANG is not set.
>>>
>>> Setting PANIC_HANG would solve this issue, but it also changes the behavior
>>> in case a panic occurs.
>>>
>>> Signed-off-by: Claudius Heine 
>>> ---
>>>  arch/arm/lib/Makefile | 2 --
>>>  arch/arm/lib/reset.c  | 2 ++
>>>  2 files changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
>>> index 9de9a9acee..763eb4498f 100644
>>> --- a/arch/arm/lib/Makefile
>>> +++ b/arch/arm/lib/Makefile
>>> @@ -56,9 +56,7 @@ obj-y += interrupts_64.o
>>>  else
>>>  obj-y  += interrupts.o
>>>  endif
>>> -ifndef CONFIG_SYSRESET
>>>  obj-y  += reset.o
>>> -endif
>>>  
>>>  obj-y  += cache.o
>>>  obj-$(CONFIG_SYS_ARM_CACHE_CP15)   += cache-cp15.o
>>> diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c
>>> index f3ea116e87..11e680be1d 100644
>>> --- a/arch/arm/lib/reset.c
>>> +++ b/arch/arm/lib/reset.c
>>> @@ -22,6 +22,7 @@
>>>  
>>>  #include 
>>>  
>>> +#if !defined(CONFIG_SYSRESET)
>>>  __weak void reset_misc(void)
>>>  {
>>>  }
>>> @@ -40,3 +41,4 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * 
>>> const argv[])
>>> /*NOTREACHED*/
>>> return 0;
>>>  }
>>> +#endif
>>
>> Does this mean there's now one huge ifdef around the entire source file?
>> That's odd.
> 
> Right. Other suggestions?
> 
> Maybe having 'do_reset' here as a weak instead, so that sysreset can
> overwrite it? But then the other definitions in arch/*/lib/reset.c
> should probably be the same for consistency sake?
> 
> I tried with this patch not to change anything in case SYSRESET is
> enabled too much and since the file isn't too large I thought that would
> be ok for now.

What if sysreset implemented do_reset ? Wouldn't that solve the issue ?
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Re: [U-Boot] [RFC PATCH] ARM: reset: Move SYSRESET condition from Makefile into source file

2019-11-27 Thread Claudius Heine
On 27/11/2019 16.12, Marek Vasut wrote:
> On 11/27/19 4:09 PM, Claudius Heine wrote:
>> Hi Marek,
>>
>> On 27/11/2019 15.47, Marek Vasut wrote:
>>> On 11/27/19 3:20 PM, Claudius Heine wrote:
 In case CONFIG_SYSRESET is set, do_reset from reset.c will not be available
 anywere, even if SYSRESET is disabled for SPL in the board specific header
 file like this:

 #if defined(CONFIG_SPL_BUILD)
 #undef CONFIG_WDT
 #undef CONFIG_WATCHDOG
 #undef CONFIG_SYSRESET
 #define CONFIG_HW_WATCHDOG
 #endif

 'do_reset' is called from SPL for instance from the panic handler in case
 SPL_USB_SDP is enabled and PANIC_HANG is not set.

 Setting PANIC_HANG would solve this issue, but it also changes the behavior
 in case a panic occurs.

 Signed-off-by: Claudius Heine 
 ---
  arch/arm/lib/Makefile | 2 --
  arch/arm/lib/reset.c  | 2 ++
  2 files changed, 2 insertions(+), 2 deletions(-)

 diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
 index 9de9a9acee..763eb4498f 100644
 --- a/arch/arm/lib/Makefile
 +++ b/arch/arm/lib/Makefile
 @@ -56,9 +56,7 @@ obj-y+= interrupts_64.o
  else
  obj-y += interrupts.o
  endif
 -ifndef CONFIG_SYSRESET
  obj-y += reset.o
 -endif
  
  obj-y += cache.o
  obj-$(CONFIG_SYS_ARM_CACHE_CP15)  += cache-cp15.o
 diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c
 index f3ea116e87..11e680be1d 100644
 --- a/arch/arm/lib/reset.c
 +++ b/arch/arm/lib/reset.c
 @@ -22,6 +22,7 @@
  
  #include 
  
 +#if !defined(CONFIG_SYSRESET)
  __weak void reset_misc(void)
  {
  }
 @@ -40,3 +41,4 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char 
 * const argv[])
/*NOTREACHED*/
return 0;
  }
 +#endif
>>>
>>> Does this mean there's now one huge ifdef around the entire source file?
>>> That's odd.
>>
>> Right. Other suggestions?
>>
>> Maybe having 'do_reset' here as a weak instead, so that sysreset can
>> overwrite it? But then the other definitions in arch/*/lib/reset.c
>> should probably be the same for consistency sake?
>>
>> I tried with this patch not to change anything in case SYSRESET is
>> enabled too much and since the file isn't too large I thought that would
>> be ok for now.
> 
> What if sysreset implemented do_reset ? Wouldn't that solve the issue ?

Not sure what you mean... sysreset implements do_reset:

https://gitlab.denx.de/u-boot/u-boot/blob/master/drivers/sysreset/sysreset-uclass.c#L112

But the SPL does not have sysreset in this case, so it needs something
different.

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[U-Boot] [PATCH v2] ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT

2019-11-27 Thread Alex Marginean
Hardware comes out of reset with implicit values, but these are outside
the accepted range for Layerscape gen 3 chassis spec used on LS1028A.
Allocate different IDs and fix up Linux DT to use them.

Signed-off-by: Alex Marginean 
Reviewed-by: Bin Meng 
---

Changes in v2:
 - moved code under arm/cpu from board as it's in fact SoC related
 
Replaces v1 and this earlier patch:
https://patchwork.ozlabs.org/patch/1144486/

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c   |  9 ++
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c   |  9 ++
 .../arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 93 +++
 .../asm/arch-fsl-layerscape/stream_id_lsch3.h |  8 ++
 4 files changed, 119 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 83a3319321..c6490556e6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1098,6 +1098,12 @@ static void config_core_prefetch(void)
}
 }
 
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+__weak void set_ecam_icids(void)
+{
+}
+#endif
+
 int arch_early_init_r(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
@@ -1149,6 +1155,9 @@ int arch_early_init_r(void)
 #endif
 #ifdef CONFIG_SYS_DPAA_QBMAN
setup_qbman_portals();
+#endif
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+   set_ecam_icids();
 #endif
return 0;
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index e993209593..1e7e46e88a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -421,6 +421,12 @@ static void fdt_disable_multimedia(void *blob, unsigned 
int svr)
 }
 #endif
 
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+__weak void fdt_fixup_ecam(void *blob)
+{
+}
+#endif
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -485,4 +491,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_ARCH_LS1028A
fdt_disable_multimedia(blob, svr);
 #endif
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+   fdt_fixup_ecam(blob);
+#endif
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c 
b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
index 9462298fbf..8110412da6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
@@ -33,3 +33,96 @@ struct icid_id_table icid_tbl[] = {
 };
 
 int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
+
+/* integrated PCI is handled separately as it's not part of CCSR/SCFG */
+#ifdef CONFIG_PCIE_ECAM_GENERIC
+
+#define ECAM_IERB_BASE 0x1f080ULL
+#define ECAM_IERB_OFFSET_NA-1
+#define ECAM_IERB_FUNC_CNT ARRAY_SIZE(ierb_offset)
+/* cache related transaction attributes for PCIe functions */
+#define ECAM_IERB_MSICAR   (ECAM_IERB_BASE + 0xa400)
+#define ECAM_IERB_MSICAR_VALUE 0x30
+
+/* offset of IERB config register per PCI function */
+static int ierb_offset[] = {
+   0x0800,
+   0x1800,
+   0x2800,
+   0x3800,
+   0x4800,
+   0x5800,
+   0x6800,
+   ECAM_IERB_OFFSET_NA,
+   0x0804,
+   0x0808,
+   0x1804,
+   0x1808,
+};
+
+/*
+ * Use a custom function for LS1028A, for now this is the only SoC with IERB
+ * and we're currently considering reorganizing IERB for future SoCs.
+ */
+void set_ecam_icids(void)
+{
+   int i;
+
+   out_le32(ECAM_IERB_MSICAR, ECAM_IERB_MSICAR_VALUE);
+
+   for (i = 0; i < ECAM_IERB_FUNC_CNT; i++) {
+   if (ierb_offset[i] == ECAM_IERB_OFFSET_NA)
+   continue;
+
+   out_le32(ECAM_IERB_BASE + ierb_offset[i],
+FSL_ECAM_STREAM_ID_START + i);
+   }
+}
+
+static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset,
+  const char *name, uint32_t idx, u32 val)
+{
+   val = cpu_to_be32(val);
+   return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name,
+  strlen(name),
+  idx * sizeof(val), &val,
+  sizeof(val));
+}
+
+static int fdt_getprop_len(void *fdt, int nodeoffset, const char *name)
+{
+   int len;
+
+   if (fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), &len))
+   return len;
+
+   return 0;
+}
+
+void fdt_fixup_ecam(void *blob)
+{
+   int off;
+
+   off = fdt_node_offset_by_compatible(blob, 0, "pci-host-ecam-generic");
+   if (off < 0) {
+   debug("ECAM node not found\n");
+   return;
+   }
+
+   if (fdt_getprop_len(blob, off, "msi-map") != 16 ||
+   fdt_getprop_len(blob, off, "iommu-map") != 16) {
+   log_err("invalid msi/iommu-map propertly size in ECAM node\n");
+   return;
+   }
+
+   fdt_setprop_inplace_idx_u32(blob, off, "msi-map", 2,
+   FSL_E

Re: [U-Boot] [PATCH v1 4/4] x86: edison: Enable DFU timeout

2019-11-27 Thread Andy Shevchenko
On Wed, Nov 27, 2019 at 11:57:53AM +0100, Lukasz Majewski wrote:
> Hi Andy,
> 
> > The stock U-Boot on Intel Edison has timeout parameter for DFU
> > command. Enable it here to be compatible with the original U-Boot
> > configuration.
> > 
> > Signed-off-by: Andy Shevchenko 
> > ---
> >  configs/edison_defconfig | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/configs/edison_defconfig b/configs/edison_defconfig
> > index 1c74ee9709..227e2f750c 100644
> > --- a/configs/edison_defconfig
> > +++ b/configs/edison_defconfig
> > @@ -29,6 +29,7 @@ CONFIG_CMD_FS_GENERIC=y
> >  CONFIG_DEFAULT_DEVICE_TREE="edison"
> >  CONFIG_ENV_IS_IN_MMC=y
> >  CONFIG_CPU=y
> > +CONFIG_DFU_TIMEOUT=y
> >  CONFIG_DFU_MMC=y
> >  CONFIG_DFU_RAM=y
> >  CONFIG_SUPPORT_EMMC_BOOT=y
> 
> This patch doesn't apply now.

I base my patches on official releases / release candidates. It applies very
well on top of 2020.01-rc3 as of today. Does DFU has a separate repository /
branch to track?

-- 
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Andy Shevchenko


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Re: [U-Boot] [RFC PATCH] ARM: reset: Move SYSRESET condition from Makefile into source file

2019-11-27 Thread Marek Vasut
On 11/27/19 4:17 PM, Claudius Heine wrote:
> On 27/11/2019 16.12, Marek Vasut wrote:
>> On 11/27/19 4:09 PM, Claudius Heine wrote:
>>> Hi Marek,
>>>
>>> On 27/11/2019 15.47, Marek Vasut wrote:
 On 11/27/19 3:20 PM, Claudius Heine wrote:
> In case CONFIG_SYSRESET is set, do_reset from reset.c will not be 
> available
> anywere, even if SYSRESET is disabled for SPL in the board specific header
> file like this:
>
> #if defined(CONFIG_SPL_BUILD)
> #undef CONFIG_WDT
> #undef CONFIG_WATCHDOG
> #undef CONFIG_SYSRESET
> #define CONFIG_HW_WATCHDOG
> #endif
>
> 'do_reset' is called from SPL for instance from the panic handler in case
> SPL_USB_SDP is enabled and PANIC_HANG is not set.
>
> Setting PANIC_HANG would solve this issue, but it also changes the 
> behavior
> in case a panic occurs.
>
> Signed-off-by: Claudius Heine 
> ---
>  arch/arm/lib/Makefile | 2 --
>  arch/arm/lib/reset.c  | 2 ++
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
> index 9de9a9acee..763eb4498f 100644
> --- a/arch/arm/lib/Makefile
> +++ b/arch/arm/lib/Makefile
> @@ -56,9 +56,7 @@ obj-y   += interrupts_64.o
>  else
>  obj-y+= interrupts.o
>  endif
> -ifndef CONFIG_SYSRESET
>  obj-y+= reset.o
> -endif
>  
>  obj-y+= cache.o
>  obj-$(CONFIG_SYS_ARM_CACHE_CP15) += cache-cp15.o
> diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c
> index f3ea116e87..11e680be1d 100644
> --- a/arch/arm/lib/reset.c
> +++ b/arch/arm/lib/reset.c
> @@ -22,6 +22,7 @@
>  
>  #include 
>  
> +#if !defined(CONFIG_SYSRESET)
>  __weak void reset_misc(void)
>  {
>  }
> @@ -40,3 +41,4 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char 
> * const argv[])
>   /*NOTREACHED*/
>   return 0;
>  }
> +#endif

 Does this mean there's now one huge ifdef around the entire source file?
 That's odd.
>>>
>>> Right. Other suggestions?
>>>
>>> Maybe having 'do_reset' here as a weak instead, so that sysreset can
>>> overwrite it? But then the other definitions in arch/*/lib/reset.c
>>> should probably be the same for consistency sake?
>>>
>>> I tried with this patch not to change anything in case SYSRESET is
>>> enabled too much and since the file isn't too large I thought that would
>>> be ok for now.
>>
>> What if sysreset implemented do_reset ? Wouldn't that solve the issue ?
> 
> Not sure what you mean... sysreset implements do_reset:
> 
> https://gitlab.denx.de/u-boot/u-boot/blob/master/drivers/sysreset/sysreset-uclass.c#L112
> 
> But the SPL does not have sysreset in this case, so it needs something
> different.

Oh, so you need CONFIG_$(SPL_TPL_)SYSRESET then ?
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Re: [U-Boot] [PATCH v1 4/4] x86: edison: Enable DFU timeout

2019-11-27 Thread Andy Shevchenko
On Wed, Nov 27, 2019 at 05:21:32PM +0200, Andy Shevchenko wrote:
> On Wed, Nov 27, 2019 at 11:57:53AM +0100, Lukasz Majewski wrote:
> > Hi Andy,
> > 
> > > The stock U-Boot on Intel Edison has timeout parameter for DFU
> > > command. Enable it here to be compatible with the original U-Boot
> > > configuration.
> > > 
> > > Signed-off-by: Andy Shevchenko 
> > > ---
> > >  configs/edison_defconfig | 1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/configs/edison_defconfig b/configs/edison_defconfig
> > > index 1c74ee9709..227e2f750c 100644
> > > --- a/configs/edison_defconfig
> > > +++ b/configs/edison_defconfig
> > > @@ -29,6 +29,7 @@ CONFIG_CMD_FS_GENERIC=y
> > >  CONFIG_DEFAULT_DEVICE_TREE="edison"
> > >  CONFIG_ENV_IS_IN_MMC=y
> > >  CONFIG_CPU=y
> > > +CONFIG_DFU_TIMEOUT=y
> > >  CONFIG_DFU_MMC=y
> > >  CONFIG_DFU_RAM=y
> > >  CONFIG_SUPPORT_EMMC_BOOT=y
> > 
> > This patch doesn't apply now.
> 
> I base my patches on official releases / release candidates. It applies very
> well on top of 2020.01-rc3 as of today. Does DFU has a separate repository /
> branch to track?

I see few patches in mainstream touching areas nearby. Though, this one can be
still applied with a reduced context.

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Re: [U-Boot] [RFC PATCH] ARM: reset: Move SYSRESET condition from Makefile into source file

2019-11-27 Thread Claudius Heine
On 27/11/2019 16.21, Marek Vasut wrote:
> On 11/27/19 4:17 PM, Claudius Heine wrote:
>> On 27/11/2019 16.12, Marek Vasut wrote:
>>> On 11/27/19 4:09 PM, Claudius Heine wrote:
 Hi Marek,

 On 27/11/2019 15.47, Marek Vasut wrote:
> On 11/27/19 3:20 PM, Claudius Heine wrote:
>> In case CONFIG_SYSRESET is set, do_reset from reset.c will not be 
>> available
>> anywere, even if SYSRESET is disabled for SPL in the board specific 
>> header
>> file like this:
>>
>> #if defined(CONFIG_SPL_BUILD)
>> #undef CONFIG_WDT
>> #undef CONFIG_WATCHDOG
>> #undef CONFIG_SYSRESET
>> #define CONFIG_HW_WATCHDOG
>> #endif
>>
>> 'do_reset' is called from SPL for instance from the panic handler in case
>> SPL_USB_SDP is enabled and PANIC_HANG is not set.
>>
>> Setting PANIC_HANG would solve this issue, but it also changes the 
>> behavior
>> in case a panic occurs.
>>
>> Signed-off-by: Claudius Heine 
>> ---
>>  arch/arm/lib/Makefile | 2 --
>>  arch/arm/lib/reset.c  | 2 ++
>>  2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
>> index 9de9a9acee..763eb4498f 100644
>> --- a/arch/arm/lib/Makefile
>> +++ b/arch/arm/lib/Makefile
>> @@ -56,9 +56,7 @@ obj-y  += interrupts_64.o
>>  else
>>  obj-y   += interrupts.o
>>  endif
>> -ifndef CONFIG_SYSRESET
>>  obj-y   += reset.o
>> -endif
>>  
>>  obj-y   += cache.o
>>  obj-$(CONFIG_SYS_ARM_CACHE_CP15)+= cache-cp15.o
>> diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c
>> index f3ea116e87..11e680be1d 100644
>> --- a/arch/arm/lib/reset.c
>> +++ b/arch/arm/lib/reset.c
>> @@ -22,6 +22,7 @@
>>  
>>  #include 
>>  
>> +#if !defined(CONFIG_SYSRESET)
>>  __weak void reset_misc(void)
>>  {
>>  }
>> @@ -40,3 +41,4 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, 
>> char * const argv[])
>>  /*NOTREACHED*/
>>  return 0;
>>  }
>> +#endif
>
> Does this mean there's now one huge ifdef around the entire source file?
> That's odd.

 Right. Other suggestions?

 Maybe having 'do_reset' here as a weak instead, so that sysreset can
 overwrite it? But then the other definitions in arch/*/lib/reset.c
 should probably be the same for consistency sake?

 I tried with this patch not to change anything in case SYSRESET is
 enabled too much and since the file isn't too large I thought that would
 be ok for now.
>>>
>>> What if sysreset implemented do_reset ? Wouldn't that solve the issue ?
>>
>> Not sure what you mean... sysreset implements do_reset:
>>
>> https://gitlab.denx.de/u-boot/u-boot/blob/master/drivers/sysreset/sysreset-uclass.c#L112
>>
>> But the SPL does not have sysreset in this case, so it needs something
>> different.
> 
> Oh, so you need CONFIG_$(SPL_TPL_)SYSRESET then ?

Well that would probably not enough. I would also need settings for the
watchdog, because the SPL does not have DM support, so while u-boot uses
CONFIG_WATCHDOG the SPL uses CONFIG_HW_WATCHDOG.

Easier that changing all this is something like this in the board header
file (as I described in the commit description):

#if defined(CONFIG_SPL_BUILD)
#undef CONFIG_WDT
#undef CONFIG_WATCHDOG
#undef CONFIG_SYSRESET
#define CONFIG_HW_WATCHDOG
#endif

In case of imx6, that way the SPL uses the hw_watchdog_reset from the
imx watchdog driver instead of the 'watchdog_reset'.

'watchdog_reset' is not available since that is implemented in
wdt-uclass.c and CONFIG_SPL_WDT depends on SPL_DM.
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Re: [U-Boot] GPT overlap on i.MX6

2019-11-27 Thread Jagan Teki
Hi Lukasz,

On Wed, Nov 27, 2019 at 4:15 PM Lukasz Majewski  wrote:
>
> Hi Jagan,
>
> > Hi,
> >
> > I have created GPT table start from 8MB for kernel, roots etc.
> > something like
> >
> > PartStart LBA   End LBA Name
> > Attributes
> > Type GUID
> > Partition GUID
> >   1 0x4000  0x00023fff  "boota"
> > attrs:  0x0004
> > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > guid:   c12a7328-f81f-11d2-ba4b-00a0c93ec93b
> >   2 0x00024000  0x00043fff  "bootb"
> > attrs:  0x0004
> > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > guid:   21686148-6449-6e6f-744e-656564454649
> >   3 0x00044000  0x00243fff  "rootfsa"
> > attrs:  0x
> > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > guid:   b921b045-1df0-41c3-af44-4c6f280d3fae
> >   4 0x00244000  0x00443fff  "rootfsb"
> > attrs:  0x
> > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > guid:   8da63339-0007-60c0-c436-083ac8230908
> >   5 0x00444000  0x0070bfde  "data"
> > attrs:  0x
> > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > guid:   4f72ab70-69be-5948-81ff-4fc3daf24faa
> >
> > I have not included SPL, U-Boot to the partition list since it start
> > from 0x400 in i.MX6. So
> > I'm writing SPL separately using fastboot(with offset) or ums.
> >
> > But by doing this, the partition header seems overlapped so the
> > output looks
> >
> > GUID Partition Table Entry Array CRC is wrong: 0x6a1aba0a !=
> > 0x8e4fd548 find_valid_gpt: *** ERROR: Invalid GPT ***
> > find_valid_gpt: ***Using Backup GPT ***
> > PartStart LBA   End LBA Name
> > Attributes
> > Type GUID
> > Partition GUID
> >   1 0x4000  0x00023fff  "boota"
> > attrs:  0x0004
> > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > guid:   c12a7328-f81f-11d2-ba4b-00a0c93ec93b
> >   2 0x00024000  0x00043fff  "bootb"
> > attrs:  0x0004
> > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > guid:   21686148-6449-6e6f-744e-656564454649
> >   3 0x00044000  0x00243fff  "rootfsa"
> > attrs:  0x
> > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > guid:   b921b045-1df0-41c3-af44-4c6f280d3fae
> >   4 0x00244000  0x00443fff  "rootfsb"
> > attrs:  0x
> > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > guid:   8da63339-0007-60c0-c436-083ac8230908
> >   5 0x00444000  0x0070bfde  "data"
> > attrs:  0x
> > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > guid:   4f72ab70-69be-5948-81ff-4fc3daf24faa
> >
> > So, what I understand is If I create the GPT first and then write the
> > SPL, the SPL writing process will destroy the GPT Table and if I write
> > SPL first and then create GPT, the GPT creation process will destroy
> > the SPL.
> >
> > Is there any way to fix this? I remember we can prevent this overlap
> > by preserving GPT Table som other or boot partition instead of having
> > them at the beginning by default.
> >
> > Any inputs?
>
> On the diagram of GPT description [1] there is the info that partitions
> can start from LBA 34 (0x200 * 34) = 0x4400
>
> From the above it seems like you starts from 0x4000 your boota
> partition, which then overwrites the "Entries 5-128" which shall be 0
> and are protected by CRC written in the Primary GPT Header.
>
> Please try to adjust your partition scheme to start from 0x4400.

I still see the overlap. I have created boota at 0x4400 and the write
the SPL at 0x400

icorem6qdl-rqs> mmc part

Partition Map for MMC device 2  --   Partition Type: EFI

GUID Partition Table Entry Array CRC is wrong: 0xfca8e0bf != 0xc10fdc7b
find_valid_gpt: *** ERROR: Invalid GPT ***
find_valid_gpt: ***Using Backup GPT ***
PartStart LBA   End LBA Name
Attributes
Type GUID
Partition GUID
  1 0x4400  0x000243ff  "bootA"
attrs:  0x0004
type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
guid:   c12a7328-f81f-11d2-ba4b-00a0c93ec93b
  2 0x00024400  0x000443ff  "bootB"
attrs:  0x0004
type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
guid:   21686148-6449-6e6f-744e-656564454649
  3 0x00044400  0x002443ff  "rootfsA"
attrs:  0x
type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
guid:   b921b045-1df0-41c3-af44-4c6f280d3fae
  4 0x00244400  0x004443ff  "rootfsB"
attrs:  0x
type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
guid:   8da63339-0007-60c0-c436-083ac8230908
  5 0x0000  0x0070bfde

Re: [U-Boot] [RFC PATCH] ARM: reset: Move SYSRESET condition from Makefile into source file

2019-11-27 Thread Marek Vasut
On 11/27/19 4:40 PM, Claudius Heine wrote:
> On 27/11/2019 16.21, Marek Vasut wrote:
>> On 11/27/19 4:17 PM, Claudius Heine wrote:
>>> On 27/11/2019 16.12, Marek Vasut wrote:
 On 11/27/19 4:09 PM, Claudius Heine wrote:
> Hi Marek,
>
> On 27/11/2019 15.47, Marek Vasut wrote:
>> On 11/27/19 3:20 PM, Claudius Heine wrote:
>>> In case CONFIG_SYSRESET is set, do_reset from reset.c will not be 
>>> available
>>> anywere, even if SYSRESET is disabled for SPL in the board specific 
>>> header
>>> file like this:
>>>
>>> #if defined(CONFIG_SPL_BUILD)
>>> #undef CONFIG_WDT
>>> #undef CONFIG_WATCHDOG
>>> #undef CONFIG_SYSRESET
>>> #define CONFIG_HW_WATCHDOG
>>> #endif
>>>
>>> 'do_reset' is called from SPL for instance from the panic handler in 
>>> case
>>> SPL_USB_SDP is enabled and PANIC_HANG is not set.
>>>
>>> Setting PANIC_HANG would solve this issue, but it also changes the 
>>> behavior
>>> in case a panic occurs.
>>>
>>> Signed-off-by: Claudius Heine 
>>> ---
>>>  arch/arm/lib/Makefile | 2 --
>>>  arch/arm/lib/reset.c  | 2 ++
>>>  2 files changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
>>> index 9de9a9acee..763eb4498f 100644
>>> --- a/arch/arm/lib/Makefile
>>> +++ b/arch/arm/lib/Makefile
>>> @@ -56,9 +56,7 @@ obj-y += interrupts_64.o
>>>  else
>>>  obj-y  += interrupts.o
>>>  endif
>>> -ifndef CONFIG_SYSRESET
>>>  obj-y  += reset.o
>>> -endif
>>>  
>>>  obj-y  += cache.o
>>>  obj-$(CONFIG_SYS_ARM_CACHE_CP15)   += cache-cp15.o
>>> diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c
>>> index f3ea116e87..11e680be1d 100644
>>> --- a/arch/arm/lib/reset.c
>>> +++ b/arch/arm/lib/reset.c
>>> @@ -22,6 +22,7 @@
>>>  
>>>  #include 
>>>  
>>> +#if !defined(CONFIG_SYSRESET)
>>>  __weak void reset_misc(void)
>>>  {
>>>  }
>>> @@ -40,3 +41,4 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, 
>>> char * const argv[])
>>> /*NOTREACHED*/
>>> return 0;
>>>  }
>>> +#endif
>>
>> Does this mean there's now one huge ifdef around the entire source file?
>> That's odd.
>
> Right. Other suggestions?
>
> Maybe having 'do_reset' here as a weak instead, so that sysreset can
> overwrite it? But then the other definitions in arch/*/lib/reset.c
> should probably be the same for consistency sake?
>
> I tried with this patch not to change anything in case SYSRESET is
> enabled too much and since the file isn't too large I thought that would
> be ok for now.

 What if sysreset implemented do_reset ? Wouldn't that solve the issue ?
>>>
>>> Not sure what you mean... sysreset implements do_reset:
>>>
>>> https://gitlab.denx.de/u-boot/u-boot/blob/master/drivers/sysreset/sysreset-uclass.c#L112
>>>
>>> But the SPL does not have sysreset in this case, so it needs something
>>> different.
>>
>> Oh, so you need CONFIG_$(SPL_TPL_)SYSRESET then ?
> 
> Well that would probably not enough. I would also need settings for the
> watchdog, because the SPL does not have DM support, so while u-boot uses
> CONFIG_WATCHDOG the SPL uses CONFIG_HW_WATCHDOG.
> 
> Easier that changing all this is something like this in the board header
> file (as I described in the commit description):
> 
> #if defined(CONFIG_SPL_BUILD)
> #undef CONFIG_WDT
> #undef CONFIG_WATCHDOG
> #undef CONFIG_SYSRESET
> #define CONFIG_HW_WATCHDOG
> #endif

Can't we add DM watchdog to SPL instead ?

> In case of imx6, that way the SPL uses the hw_watchdog_reset from the
> imx watchdog driver instead of the 'watchdog_reset'.
> 
> 'watchdog_reset' is not available since that is implemented in
> wdt-uclass.c and CONFIG_SPL_WDT depends on SPL_DM.
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Re: [U-Boot] [PATCH 1/5] Revert "powerpc: mpc85xx: delete FSL_SATA for T2080QDS board."

2019-11-27 Thread Wolfgang Denk
Dear Peng Ma,

In message <20191127100145.44346-1-peng...@nxp.com> you wrote:
> This reverts commit 856b9cdb53f0e6c8d98f81cf71ef363c16b0aa0e.
>
> Signed-off-by: Peng Ma 

Why?

A commit message should always explain why such an action is taking
place.

Best regards,

Wolfgang Denk

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Re: [U-Boot] [PATCH v1 4/4] x86: edison: Enable DFU timeout

2019-11-27 Thread Lukasz Majewski
Hi Andy,

> On Wed, Nov 27, 2019 at 11:57:53AM +0100, Lukasz Majewski wrote:
> > Hi Andy,
> >   
> > > The stock U-Boot on Intel Edison has timeout parameter for DFU
> > > command. Enable it here to be compatible with the original U-Boot
> > > configuration.
> > > 
> > > Signed-off-by: Andy Shevchenko 
> > > ---
> > >  configs/edison_defconfig | 1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/configs/edison_defconfig b/configs/edison_defconfig
> > > index 1c74ee9709..227e2f750c 100644
> > > --- a/configs/edison_defconfig
> > > +++ b/configs/edison_defconfig
> > > @@ -29,6 +29,7 @@ CONFIG_CMD_FS_GENERIC=y
> > >  CONFIG_DEFAULT_DEVICE_TREE="edison"
> > >  CONFIG_ENV_IS_IN_MMC=y
> > >  CONFIG_CPU=y
> > > +CONFIG_DFU_TIMEOUT=y
> > >  CONFIG_DFU_MMC=y
> > >  CONFIG_DFU_RAM=y
> > >  CONFIG_SUPPORT_EMMC_BOOT=y  
> > 
> > This patch doesn't apply now.  
> 
> I base my patches on official releases / release candidates. It
> applies very well on top of 2020.01-rc3 as of today. Does DFU has a
> separate repository / branch to track?
> 

I'm using u-boot-usb as a base:

https://gitlab.denx.de/u-boot/custodians/u-boot-usb/commits/next

as I'm sending PRs to Marek.


Best regards,

Lukasz Majewski

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[U-Boot] [PATCH v2 2/4] dfu: Refactor do_dfu() to handle optional argument

2019-11-27 Thread Andy Shevchenko
In the future we may utilize optional argument in 'dfu' command line.
As a preparation for this, refactor do_dfu().

Signed-off-by: Andy Shevchenko 
Acked-by: Lukasz Majewski 
---
 cmd/dfu.c | 17 ++---
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/cmd/dfu.c b/cmd/dfu.c
index 33491d0bc9..14a8ec879e 100644
--- a/cmd/dfu.c
+++ b/cmd/dfu.c
@@ -30,22 +30,25 @@ static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 #if defined(CONFIG_DFU_OVER_USB) || defined(CONFIG_DFU_OVER_TFTP)
char *interface = NULL;
char *devstring = NULL;
+#if defined(CONFIG_DFU_OVER_TFTP)
+   unsigned long value = 0;
+#endif
 
if (argc >= 4) {
interface = argv[2];
devstring = argv[3];
}
+
+#if defined(CONFIG_DFU_OVER_TFTP)
+   if (argc == 5 || argc == 3)
+   value = simple_strtoul(argv[argc - 1], NULL, 0);
+#endif
 #endif
 
int ret = 0;
 #ifdef CONFIG_DFU_OVER_TFTP
-   unsigned long addr = 0;
-   if (!strcmp(argv[1], "tftp")) {
-   if (argc == 5 || argc == 3)
-   addr = simple_strtoul(argv[argc - 1], NULL, 0);
-
-   return update_tftp(addr, interface, devstring);
-   }
+   if (!strcmp(argv[1], "tftp"))
+   return update_tftp(value, interface, devstring);
 #endif
 #ifdef CONFIG_DFU_OVER_USB
ret = dfu_init_env_entities(interface, devstring);
-- 
2.24.0

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[U-Boot] [PATCH v2 3/4] dfu: Add optional timeout parameter

2019-11-27 Thread Andy Shevchenko
When the `dfu` command is called from the U-Boot environment,
it now accepts an optional parameter that specifies a timeout (in seconds).
If a DFU connection is not made within that time the `dfu` command exits
(as it would if Ctrl+C was pressed). If the timeout is left empty or being
zero the `dfu` command behaves as it does now.

This is useful for allowing U-Boot to check to see if anything wants to
upload new firmware before continuing to boot.

The patch is based on the commit
https://github.com/01org/edison-u-boot/commit/5e966ccc3c65c18c9783741fa04e0c45e021780c
by Sebastien Colleur, which has been heavily reworked due to U-Boot changes
in the past.

Signed-off-by: Brad Campbell 
Signed-off-by: Andy Shevchenko 
---
v2:
- add documentation part (Lukasz)
- drop original author's SoB due to bouncing email, give credit
  in the commit message anyway

 cmd/dfu.c   | 15 +--
 common/dfu.c| 17 +
 doc/README.dfu  |  8 ++--
 drivers/dfu/Kconfig |  6 ++
 drivers/dfu/dfu.c   | 15 +++
 include/dfu.h   |  5 +
 6 files changed, 62 insertions(+), 4 deletions(-)

diff --git a/cmd/dfu.c b/cmd/dfu.c
index 14a8ec879e..b30f8a5667 100644
--- a/cmd/dfu.c
+++ b/cmd/dfu.c
@@ -30,7 +30,7 @@ static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char 
* const argv[])
 #if defined(CONFIG_DFU_OVER_USB) || defined(CONFIG_DFU_OVER_TFTP)
char *interface = NULL;
char *devstring = NULL;
-#if defined(CONFIG_DFU_OVER_TFTP)
+#if defined(CONFIG_DFU_TIMEOUT) || defined(CONFIG_DFU_OVER_TFTP)
unsigned long value = 0;
 #endif
 
@@ -39,7 +39,7 @@ static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char 
* const argv[])
devstring = argv[3];
}
 
-#if defined(CONFIG_DFU_OVER_TFTP)
+#if defined(CONFIG_DFU_TIMEOUT) || defined(CONFIG_DFU_OVER_TFTP)
if (argc == 5 || argc == 3)
value = simple_strtoul(argv[argc - 1], NULL, 0);
 #endif
@@ -55,6 +55,10 @@ static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char 
* const argv[])
if (ret)
goto done;
 
+#ifdef CONFIG_DFU_TIMEOUT
+   dfu_set_timeout(value * 1000);
+#endif
+
ret = CMD_RET_SUCCESS;
if (strcmp(argv[argc - 1], "list") == 0) {
dfu_show_entities();
@@ -75,10 +79,17 @@ U_BOOT_CMD(dfu, CONFIG_SYS_MAXARGS, 1, do_dfu,
"Device Firmware Upgrade",
""
 #ifdef CONFIG_DFU_OVER_USB
+#ifdef CONFIG_DFU_TIMEOUT
+   " [ ] [] [list]\n"
+#else
" [ ] [list]\n"
+#endif
"  - device firmware upgrade via \n"
"on device , attached to interface\n"
"\n"
+#ifdef CONFIG_DFU_TIMEOUT
+   "[] - specify inactivity timeout in seconds\n"
+#endif
"[list] - list available alt settings\n"
 #endif
 #ifdef CONFIG_DFU_OVER_TFTP
diff --git a/common/dfu.c b/common/dfu.c
index 44d1484d3d..da6289b218 100644
--- a/common/dfu.c
+++ b/common/dfu.c
@@ -35,6 +35,10 @@ int run_usb_dnl_gadget(int usbctrl_index, char 
*usb_dnl_gadget)
return CMD_RET_FAILURE;
}
 
+#ifdef CONFIG_DFU_TIMEOUT
+   unsigned long start_time = get_timer(0);
+#endif
+
while (1) {
if (g_dnl_detach()) {
/*
@@ -79,6 +83,19 @@ int run_usb_dnl_gadget(int usbctrl_index, char 
*usb_dnl_gadget)
}
}
 
+#ifdef CONFIG_DFU_TIMEOUT
+   unsigned long wait_time = dfu_get_timeout();
+
+   if (wait_time) {
+   unsigned long current_time = get_timer(start_time);
+
+   if (current_time > wait_time) {
+   debug("Inactivity timeout, abort DFU\n");
+   goto exit;
+   }
+   }
+#endif
+
WATCHDOG_RESET();
usb_gadget_handle_interrupts(usbctrl_index);
}
diff --git a/doc/README.dfu b/doc/README.dfu
index 558d347c26..caf1c9998c 100644
--- a/doc/README.dfu
+++ b/doc/README.dfu
@@ -43,6 +43,7 @@ Configuration Options:
   CONFIG_DFU_RAM
   CONFIG_DFU_SF
   CONFIG_DFU_SF_PART
+  CONFIG_DFU_TIMEOUT
   CONFIG_DFU_VIRTUAL
   CONFIG_CMD_DFU
 
@@ -70,12 +71,15 @@ Commands:
   dfu  [ ] list
 list the alternate device defined in "dfu_alt_info"
 
-  dfu  [ ]
+  dfu  [ ] []
 start the dfu stack on the USB instance with the selected medium
 backend and use the "dfu_alt_info" variable to configure the
 alternate setting and link each one with the medium
 The dfu command continue until receive a ^C in console or
-a DFU detach transaction from HOST.
+a DFU detach transaction from HOST. If CONFIG_DFU_TIMEOUT option
+is enabled and  parameter is present in the command line,
+the DFU operation will be aborted automatically after 
+seconds of waiting remote to initiate DFU session.
 
   The possible values of  are :
   (with  = 0 in the dfu command example)
diff --git a/drivers/dfu/Kconfig

[U-Boot] [PATCH v2 1/4] dfu: Drop unused prototype of dfu_trigger_reset()

2019-11-27 Thread Andy Shevchenko
After the commit 1cc03c5c53c0 ("dfu: Provide means to find difference between
dfu-util -e and -R") the dangling ptototype appeared. Remove it here.

Fixes: 1cc03c5c53c0 ("dfu: Provide means to find difference between dfu-util -e 
and -R")
Cc: Lukasz Majewski 
Cc: Stephen Warren 
Signed-off-by: Andy Shevchenko 
Acked-by: Lukasz Majewski 
---
 include/dfu.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/dfu.h b/include/dfu.h
index 564966333f..2e3e91c8d2 100644
--- a/include/dfu.h
+++ b/include/dfu.h
@@ -171,7 +171,6 @@ const char *dfu_get_dev_type(enum dfu_device_type t);
 const char *dfu_get_layout(enum dfu_layout l);
 struct dfu_entity *dfu_get_entity(int alt);
 char *dfu_extract_token(char** e, int *n);
-void dfu_trigger_reset(void);
 int dfu_get_alt(char *name);
 int dfu_init_env_entities(char *interface, char *devstr);
 unsigned char *dfu_get_buf(struct dfu_entity *dfu);
-- 
2.24.0

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[U-Boot] [PATCH v2 4/4] x86: edison: Enable DFU timeout

2019-11-27 Thread Andy Shevchenko
The stock U-Boot on Intel Edison has timeout parameter for DFU command.
Enable it here to be compatible with the original U-Boot configuration.

Signed-off-by: Andy Shevchenko 
---
v2:
- rebase on top of origin/master as of today (Lukasz)
 configs/edison_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/edison_defconfig b/configs/edison_defconfig
index 29bc96aa60..056521a571 100644
--- a/configs/edison_defconfig
+++ b/configs/edison_defconfig
@@ -34,6 +34,7 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_ENV_OFFSET_REDUND=0x60
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_CPU=y
+CONFIG_DFU_TIMEOUT=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-- 
2.24.0

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Re: [U-Boot] GPT overlap on i.MX6

2019-11-27 Thread Lukasz Majewski
Hi Jagan,

> Hi Lukasz,
> 
> On Wed, Nov 27, 2019 at 4:15 PM Lukasz Majewski  wrote:
> >
> > Hi Jagan,
> >  
> > > Hi,
> > >
> > > I have created GPT table start from 8MB for kernel, roots etc.
> > > something like
> > >
> > > PartStart LBA   End LBA Name
> > > Attributes
> > > Type GUID
> > > Partition GUID
> > >   1 0x4000  0x00023fff  "boota"
> > > attrs:  0x0004
> > > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > > guid:   c12a7328-f81f-11d2-ba4b-00a0c93ec93b
> > >   2 0x00024000  0x00043fff  "bootb"
> > > attrs:  0x0004
> > > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > > guid:   21686148-6449-6e6f-744e-656564454649
> > >   3 0x00044000  0x00243fff  "rootfsa"
> > > attrs:  0x
> > > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > > guid:   b921b045-1df0-41c3-af44-4c6f280d3fae
> > >   4 0x00244000  0x00443fff  "rootfsb"
> > > attrs:  0x
> > > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > > guid:   8da63339-0007-60c0-c436-083ac8230908
> > >   5 0x00444000  0x0070bfde  "data"
> > > attrs:  0x
> > > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > > guid:   4f72ab70-69be-5948-81ff-4fc3daf24faa
> > >
> > > I have not included SPL, U-Boot to the partition list since it
> > > start from 0x400 in i.MX6. So
> > > I'm writing SPL separately using fastboot(with offset) or ums.
> > >
> > > But by doing this, the partition header seems overlapped so the
> > > output looks
> > >
> > > GUID Partition Table Entry Array CRC is wrong: 0x6a1aba0a !=
> > > 0x8e4fd548 find_valid_gpt: *** ERROR: Invalid GPT ***
> > > find_valid_gpt: ***Using Backup GPT ***
> > > PartStart LBA   End LBA Name
> > > Attributes
> > > Type GUID
> > > Partition GUID
> > >   1 0x4000  0x00023fff  "boota"
> > > attrs:  0x0004
> > > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > > guid:   c12a7328-f81f-11d2-ba4b-00a0c93ec93b
> > >   2 0x00024000  0x00043fff  "bootb"
> > > attrs:  0x0004
> > > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > > guid:   21686148-6449-6e6f-744e-656564454649
> > >   3 0x00044000  0x00243fff  "rootfsa"
> > > attrs:  0x
> > > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > > guid:   b921b045-1df0-41c3-af44-4c6f280d3fae
> > >   4 0x00244000  0x00443fff  "rootfsb"
> > > attrs:  0x
> > > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > > guid:   8da63339-0007-60c0-c436-083ac8230908
> > >   5 0x00444000  0x0070bfde  "data"
> > > attrs:  0x
> > > type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > > guid:   4f72ab70-69be-5948-81ff-4fc3daf24faa
> > >
> > > So, what I understand is If I create the GPT first and then write
> > > the SPL, the SPL writing process will destroy the GPT Table and
> > > if I write SPL first and then create GPT, the GPT creation
> > > process will destroy the SPL.
> > >
> > > Is there any way to fix this? I remember we can prevent this
> > > overlap by preserving GPT Table som other or boot partition
> > > instead of having them at the beginning by default.
> > >
> > > Any inputs?  
> >
> > On the diagram of GPT description [1] there is the info that
> > partitions can start from LBA 34 (0x200 * 34) = 0x4400
> >
> > From the above it seems like you starts from 0x4000 your boota
> > partition, which then overwrites the "Entries 5-128" which shall be
> > 0 and are protected by CRC written in the Primary GPT Header.
> >
> > Please try to adjust your partition scheme to start from 0x4400.  
> 
> I still see the overlap. I have created boota at 0x4400 and the write
> the SPL at 0x400
 ^^ - this overwrites the GPT header IMHO.

You may dump the eMMC and check if this is the case (even with u-boot's
md.l utility)


I had similar problem on some Beagle Bone Black (AM33x) board.

The ROM wanted to boot from the fixed eMMC LBA offset which was clashing
with GPT.

Fortunately, it was also possible to boot from FAT (it was checked
before the raw offset from eMMC case) partition, so I used this option
instead.


But hey, isn't it possible to store SPL/u-boot to the eMMC's boot (the
separate HW partition) partition and store GPT to the user accessible
one (the large one - e.g. 4 GiB)?


> 
> icorem6qdl-rqs> mmc part
> 
> Partition Map for MMC device 2  --   Partition Type: EFI
> 
> GUID Partition Table Entry Array CRC is wrong: 0xfca8e0bf !=
> 0xc10fdc7b find_valid_gpt: *** ERROR: Invalid GPT ***
> find_valid_gpt: ***Using Backup GPT ***
> PartStart LBA   End LBA Name
> A

[U-Boot] [PATCH v1] MAINTAINERS: Add info for bcm283x

2019-11-27 Thread matthias . bgg
From: Matthias Brugger 

The bcm283x has grown in files, which was not reflected in the
MAINTAINERS file. Fix this by adding the missing entries.

Signed-off-by: Matthias Brugger 

---

 MAINTAINERS | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 332fd9d74c..8d588b7d64 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -150,7 +150,9 @@ N:  meson
 ARM BROADCOM BCM283X
 M: Matthias Brugger 
 S: Maintained
+F: arch/arm/dts/bcm283*
 F: arch/arm/mach-bcm283x/
+F: board/raspberrypi/
 F: drivers/gpio/bcm2835_gpio.c
 F: drivers/mmc/bcm2835_sdhci.c
 F: drivers/mmc/bcm2835_sdhost.c
@@ -158,6 +160,7 @@ F:  drivers/serial/serial_bcm283x_mu.c
 F: drivers/serial/serial_bcm283x_pl011.c
 F: drivers/video/bcm2835.c
 F: include/dm/platform_data/serial_bcm283x_mu.h
+F: include/dt-bindings/pinctrl/bcm2835.h
 F: drivers/pinctrl/broadcom/
 
 ARM BROADCOM BCMSTB
-- 
2.24.0

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Re: [U-Boot] [PATCH v1 4/4] x86: edison: Enable DFU timeout

2019-11-27 Thread Andy Shevchenko
On Wed, Nov 27, 2019 at 05:10:22PM +0100, Lukasz Majewski wrote:
> > On Wed, Nov 27, 2019 at 11:57:53AM +0100, Lukasz Majewski wrote:

> > I base my patches on official releases / release candidates. It
> > applies very well on top of 2020.01-rc3 as of today. Does DFU has a
> > separate repository / branch to track?
> > 
> 
> I'm using u-boot-usb as a base:
> 
> https://gitlab.denx.de/u-boot/custodians/u-boot-usb/commits/next
> 
> as I'm sending PRs to Marek.

I see, thanks. I have added it to my remote list.

Note, I sent v2 based on origin/master, but later I have tested against
usb/next and everything can be applied well.

-- 
With Best Regards,
Andy Shevchenko


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Re: [U-Boot] [PATCH v1 4/4] x86: edison: Enable DFU timeout

2019-11-27 Thread Lukasz Majewski
On Wed, 27 Nov 2019 18:45:43 +0200
Andy Shevchenko  wrote:

> On Wed, Nov 27, 2019 at 05:10:22PM +0100, Lukasz Majewski wrote:
> > > On Wed, Nov 27, 2019 at 11:57:53AM +0100, Lukasz Majewski wrote:  
> 
> > > I base my patches on official releases / release candidates. It
> > > applies very well on top of 2020.01-rc3 as of today. Does DFU has
> > > a separate repository / branch to track?
> > >   
> > 
> > I'm using u-boot-usb as a base:
> > 
> > https://gitlab.denx.de/u-boot/custodians/u-boot-usb/commits/next
> > 
> > as I'm sending PRs to Marek.  
> 
> I see, thanks. I have added it to my remote list.
> 
> Note, I sent v2 based on origin/master, but later I have tested
> against usb/next and everything can be applied well.
> 

Ok. Great :-)


Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de


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Re: [U-Boot] Reboot is broken on RockPro64 with mainline u-boot and ATF

2019-11-27 Thread Vasily Khoruzhick
On Mon, Nov 25, 2019 at 9:25 AM Vasily Khoruzhick  wrote:
>
> Hey guys,
>
> Looks like reboot is broken on RockPro64 (RK3399-based) with mainline
> u-boot and ATF (ATF already has a fix [1]).

Added Philipp and Simon to CC.

Can anyone please help me with this issue?

> When I type 'reboot' in linux I get back to u-boot, but subsequent
> linux boot hangs in most cases. Sometimes I get this warning:
>
> [   62.400363] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
> [   62.418095] rcu: 4-...!: (3 ticks this GP)
> idle=332/1/0x4000 softirq=23/24 fqs=13
> [   62.444137] Task dump for CPU 4:
> [   62.453791] kworker/4:1 R  running task042  2 
> 0x002a
> [   62.474907] Workqueue: pm genpd_power_off_work_fn
> [   62.489013] rcu: rcu_sched kthread starved for 5976 jiffies! g-1147
> f0x0 RCU_GP_WAIT_FQS(5) ->state=0x0 ->cpu=1
> [   62.519205] rcu: RCU grace-period kthread stack dump:
> [   62.534316] rcu_sched   R  running task010  2 
> 0x0028
>
> I already checked that regulators are configured correctly, also I
> tried to disable big CPU cluster in linux and re-initializing CPU
> voltages in u-boot but unfortunately nothing helps.
>
> There were other reports on #linux-rockchip at freenode that reboot is broken.
>
> Any ideas how to debug it or what could be wrong?
>
> Regards,
> Vasily
>
> [1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2512
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Re: [U-Boot] Reboot is broken on RockPro64 with mainline u-boot and ATF

2019-11-27 Thread Jagan Teki
Hi,

On Mon, Nov 25, 2019 at 10:56 PM Vasily Khoruzhick  wrote:
>
> Hey guys,
>
> Looks like reboot is broken on RockPro64 (RK3399-based) with mainline
> u-boot and ATF (ATF already has a fix [1]).
>
> When I type 'reboot' in linux I get back to u-boot, but subsequent
> linux boot hangs in most cases. Sometimes I get this warning:
>
> [   62.400363] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
> [   62.418095] rcu: 4-...!: (3 ticks this GP)
> idle=332/1/0x4000 softirq=23/24 fqs=13
> [   62.444137] Task dump for CPU 4:
> [   62.453791] kworker/4:1 R  running task042  2 
> 0x002a
> [   62.474907] Workqueue: pm genpd_power_off_work_fn
> [   62.489013] rcu: rcu_sched kthread starved for 5976 jiffies! g-1147
> f0x0 RCU_GP_WAIT_FQS(5) ->state=0x0 ->cpu=1
> [   62.519205] rcu: RCU grace-period kthread stack dump:
> [   62.534316] rcu_sched   R  running task010  2 
> 0x0028
>
> I already checked that regulators are configured correctly, also I
> tried to disable big CPU cluster in linux and re-initializing CPU
> voltages in u-boot but unfortunately nothing helps.
>
> There were other reports on #linux-rockchip at freenode that reboot is broken.
>
> Any ideas how to debug it or what could be wrong?

I did see it was hang in SPL when I reboot from Linux. But nothing
seen with rkbin. Can you have a quick check with rkbin flow if you
haven't tried yet? (I mean idbloader.img, trust.img and uboot.img)
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