Re: [U-Boot] [PATCH 2/3] sunxi: add DM I2C support for H3/H5

[Maxime Ripard]

On Wed, Jan 24, 2018 at 12:00:58PM +0100, Nuno Gonçalves wrote:
> On Wed, Jan 24, 2018 at 11:57 AM, Maxime Ripard
>  wrote:
> > Why don't you just synchronize the DT with Linux?
> 
> Didn't know that was the usual approach. But in Linux the files have a
> different structure, for example there is sunxi-h3-h5.dtsi.

Yes, but nothing prevents us to have the same one here.

Maxime

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Re: [U-Boot] [PATCH 3/3] sunxi: add I2C nodes present on Orange Pi >ero

[Maxime Ripard]

On Wed, Jan 24, 2018 at 12:03:26PM +0100, Nuno Gonçalves wrote:
> On Wed, Jan 24, 2018 at 11:58 AM, Maxime Ripard
>  wrote:
> > In particular, you should describe what these i2c buses are used for.
> 
> They are available on the pins exclusively. I could add the pinout for
> this board for sure. But maybe it doesn't make sense in this case to
> activate them, as without external hardware they have no use.

Indeed. It's still good to have that patch for reference though, even
if we won't merge it.

Thanks!
Maxime

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Re: [U-Boot] [PATCH 2/7] sun50i: a64: Fix USB clock/reset properties

[Maxime Ripard]

On Wed, Jan 24, 2018 at 07:06:37AM -0600, Samuel Holland wrote:
> On 01/24/18 02:42, Maxime Ripard wrote:
> > On Tue, Jan 23, 2018 at 04:18:14PM -0600, Samuel Holland wrote:
> >> Move the CLK_USB_OHCI0/1 clocks to the OHCI nodes where they belong, and
> >> make the format consistent with the H3/H5 nodes. While here, also remove
> >> leading zeros from the USB nodes' unit addresses.
> >>
> >> Signed-off-by: Samuel Holland 
> > 
> > I guess you just took the linux DTS?
> 
> No, actually the Linux DTS has the same issue with the clocks (the
> unit addresses there have been fixed). Should I send a patch there
> first?

A patch fixing that has been merged in 4.15.

> > You can just mention that, along with which version of the kernel you
> > used for that synchronization.
> 
> And then once that's merged, send a patch for synchronization?

So you're only left with that :)

Maxime

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Re: [U-Boot] [PATCH 0/2] Fix CAAM for TrustZone enable for warp7

[Auer, Lukas]

On Wed, 2018-01-24 at 19:41 +, Bryan O'Donoghue wrote:
> 
> On 24/01/18 17:41, Auer, Lukas wrote:
> > Thanks for adding me to the CC list.
> > I have experienced the same thing regarding the dec0 registers.
> > However, I don't understand why you want to detect secure mode in
> > the
> > kernel driver to skip RNG instantiation instead of instantiating
> > all
> > RNG state handles in the u-boot driver. 
> 
> That's what we are doing though.
> 
> This set instantiates everything in u-boot and then detects and skips
> in 
> the kernel if-and-only if
> 
> 1. Trust zone is detected
> 2. It looks to the Linux CAAM driver as if u-boot has initialised the
> h/w
> 
> For #2 I actually have to variants
> 
> 1. Which passes a DT parameter which indicates the kernel should
> skip 
> RNG init
> 
> 2. A module parameter which indicates the kernel should skip rng init
> 
> Could we discuss the kernel changes in the kernel thread ?
> 
> I believe we agree the u-boot side is right ?

Sorry, I haven't explained what I mean very well.

You are right in that sec_init() must be called to instantiate the RNG,
however the CAAM u-boot driver only partially does so. If you look at
function instantiate_rng() in both u-boot (drivers/crypto/fsl/jr.c) and
the kernel (drivers/crypto/caam/ctrl.c), you'll see that the kernel
loops over all available state handles whereas u-boot does not.

Fixing this in u-boot should mean that you can drop patch 5 and 6 from
your kernel series since the kernel should then skip over all state
handles.

I can send out a patch later today to fix this on the u-boot side.

Thanks,
Lukas
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Re: [U-Boot] [PATCH 1/3] configs: trats2: enable the max77686 regulator config

[Lukasz Majewski]

On Thu, 25 Jan 2018 16:06:35 +0900
Jaehoon Chung  wrote:

> Enable the CONFIG_DM_REGULATOR_MAX77686 for using regulator driver.
> 
> Signed-off-by: Jaehoon Chung 
> ---
>  configs/trats2_defconfig | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
> index aaa25a9bc7..dab62530e7 100644
> --- a/configs/trats2_defconfig
> +++ b/configs/trats2_defconfig
> @@ -46,6 +46,8 @@ CONFIG_MMC_SDHCI_SDMA=y
>  CONFIG_MMC_SDHCI_S5P=y
>  CONFIG_DM_PMIC=y
>  CONFIG_DM_PMIC_MAX77686=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_MAX77686=y
>  CONFIG_USB=y
>  CONFIG_DM_USB=y
>  CONFIG_USB_GADGET=y

Reviewed-by: Lukasz Majewski 

Best regards,

Lukasz Majewski

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Re: [U-Boot] [PATCH 2/3] power: pmic_max77686: remove the old pmic_max77686 file

[Lukasz Majewski]

On Thu, 25 Jan 2018 16:06:36 +0900
Jaehoon Chung  wrote:

> max77686 pmic is supporting with max77686.c under pmic/ and regulator/
> direnctroy. Remove pmic_max77686.c what didn't use anywhere.
> Instead, enable CONFIG_DM_REGULATOR_MAX77686 and
> CONFIG_DM_PMIC_MAX77686.
> 
> Signed-off-by: Jaehoon Chung 
> ---
>  drivers/power/pmic/Makefile|   1 -
>  drivers/power/pmic/pmic_max77686.c | 304
> - 2 files changed, 305
> deletions(-) delete mode 100644 drivers/power/pmic/pmic_max77686.c
> 
> diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
> index 7d6c583d34..265b7cb2f6 100644
> --- a/drivers/power/pmic/Makefile
> +++ b/drivers/power/pmic/Makefile
> @@ -29,7 +29,6 @@ obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
>  obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
>  obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
>  obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
> -obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
>  obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
>  obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o
>  obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
> diff --git a/drivers/power/pmic/pmic_max77686.c
> b/drivers/power/pmic/pmic_max77686.c deleted file mode 100644
> index 8e653316d1..00
> --- a/drivers/power/pmic/pmic_max77686.c
> +++ /dev/null
> @@ -1,304 +0,0 @@
> -/*
> - *  Copyright (C) 2012 Samsung Electronics
> - *  Rajeshwari Shinde 
> - *
> - * SPDX-License-Identifier:  GPL-2.0+
> - */
> -
> -#include 
> -#include 
> -#include 
> -#include 
> -#include 
> -#include 
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -static const char max77686_buck_addr[] = {
> - 0xff, 0x10, 0x12, 0x1c, 0x26, 0x30, 0x32, 0x34, 0x36, 0x38
> -};
> -
> -static unsigned int max77686_ldo_volt2hex(int ldo, ulong uV)
> -{
> - unsigned int hex = 0;
> -
> - switch (ldo) {
> - case 1:
> - case 2:
> - case 6:
> - case 7:
> - case 8:
> - case 15:
> - hex = (uV - 80) / 25000;
> - break;
> - default:
> - hex = (uV - 80) / 5;
> - }
> -
> - if (hex >= 0 && hex <= MAX77686_LDO_VOLT_MAX_HEX)
> - return hex;
> -
> - debug("%s: %ld is wrong voltage value for LDO%d\n",
> __func__, uV, ldo);
> - return 0;
> -}
> -
> -static int max77686_buck_volt2hex(int buck, ulong uV)
> -{
> - int hex = 0;
> -
> - if (buck < 5 || buck > 9) {
> - debug("%s: buck %d is not supported\n", __func__,
> buck);
> - return -EINVAL;
> - }
> -
> - hex = (uV - 75) / 5;
> -
> - if (hex >= 0 && hex <= MAX77686_BUCK_VOLT_MAX_HEX)
> - return hex;
> -
> - debug("%s: %ld is wrong voltage value for BUCK%d\n",
> -   __func__, uV, buck);
> - return -EINVAL;
> -}
> -
> -int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
> -{
> - unsigned int val, ret, hex, adr;
> -
> - if (ldo < 1 || ldo > 26) {
> - printf("%s: %d is wrong ldo number\n", __func__,
> ldo);
> - return -EINVAL;
> - }
> -
> - adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1;
> - hex = max77686_ldo_volt2hex(ldo, uV);
> -
> - if (!hex)
> - return -EINVAL;
> -
> - ret = pmic_reg_read(p, adr, &val);
> - if (ret)
> - return ret;
> -
> - val &= ~MAX77686_LDO_VOLT_MASK;
> - val |= hex;
> - ret |= pmic_reg_write(p, adr, val);
> -
> - return ret;
> -}
> -
> -int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV)
> -{
> - unsigned int val, adr;
> - int hex, ret;
> -
> - if (buck < 5 || buck > 9) {
> - printf("%s: %d is an unsupported bucket number\n",
> -__func__, buck);
> - return -EINVAL;
> - }
> -
> - adr = max77686_buck_addr[buck] + 1;
> - hex = max77686_buck_volt2hex(buck, uV);
> -
> - if (hex < 0)
> - return hex;
> -
> - ret = pmic_reg_read(p, adr, &val);
> - if (ret)
> - return ret;
> -
> - val &= ~MAX77686_BUCK_VOLT_MASK;
> - ret |= pmic_reg_write(p, adr, val | hex);
> -
> - return ret;
> -}
> -
> -int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode)
> -{
> - unsigned int val, ret, adr, mode;
> -
> - if (ldo < 1 || 26 < ldo) {
> - printf("%s: %d is wrong ldo number\n", __func__,
> ldo);
> - return -EINVAL;
> - }
> -
> - adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1;
> -
> - /* mode */
> - switch (opmode) {
> - case OPMODE_OFF:
> - mode = MAX77686_LDO_MODE_OFF;
> - break;
> - case OPMODE_STANDBY:
> - switch (ldo) {
> - case 2:
> - case 6:
> - case 7:
> - case 8:
> - case 10:
> - case 11:
> - case 12:
> - case 14:
> - case 15:
> - case 16:
> - mode = MAX77686_LDO_MODE_STANDBY;
> - 

Re: [U-Boot] [PATCH v2 3/3] lib: fdtdec: drop the old compatible about max77686

[Lukasz Majewski]

On Thu, 25 Jan 2018 16:11:03 +0900
Jaehoon Chung  wrote:

> Drop the old compatible about max77686.
> 
> Signed-off-by: Jaehoon Chung 
> ---
>  include/fdtdec.h | 1 -
>  lib/fdtdec.c | 1 -
>  2 files changed, 2 deletions(-)
> 
> diff --git a/include/fdtdec.h b/include/fdtdec.h
> index 4afb9ac501..59f589bc01 100644
> --- a/include/fdtdec.h
> +++ b/include/fdtdec.h
> @@ -136,7 +136,6 @@ enum fdt_compat_id {
>   COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */
>   COMPAT_SAMSUNG_EXYNOS_DWMMC,/* Exynos DWMMC
> controller */ COMPAT_SAMSUNG_EXYNOS_MMC,  /* Exynos MMC
> controller */
> - COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */
>   COMPAT_GENERIC_SPI_FLASH,   /* Generic SPI Flash chip */
>   COMPAT_MAXIM_98095_CODEC,   /* MAX98095 Codec */
>   COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C
> Controller */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> index df9d9ae433..58830aa370 100644
> --- a/lib/fdtdec.c
> +++ b/lib/fdtdec.c
> @@ -48,7 +48,6 @@ static const char * const
> compat_names[COMPAT_COUNT] = { COMPAT(SAMSUNG_EXYNOS_MIPI_DSI,
> "samsung,exynos-mipi-dsi"), COMPAT(SAMSUNG_EXYNOS_DWMMC,
> "samsung,exynos-dwmmc"), COMPAT(SAMSUNG_EXYNOS_MMC,
> "samsung,exynos-mmc"),
> - COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686"),
>   COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
>   COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"),
>   COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"),

Acked-by: Lukasz Majewski 

Best regards,

Lukasz Majewski

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Re: [U-Boot] [PATCH 0/2] Fix CAAM for TrustZone enable for warp7

[Bryan O'Donoghue]

On 25/01/18 09:14, Auer, Lukas wrote:

On Wed, 2018-01-24 at 19:41 +, Bryan O'Donoghue wrote:


On 24/01/18 17:41, Auer, Lukas wrote:

Thanks for adding me to the CC list.
I have experienced the same thing regarding the dec0 registers.
However, I don't understand why you want to detect secure mode in
the
kernel driver to skip RNG instantiation instead of instantiating
all
RNG state handles in the u-boot driver.


That's what we are doing though.

This set instantiates everything in u-boot and then detects and skips
in
the kernel if-and-only if

1. Trust zone is detected
2. It looks to the Linux CAAM driver as if u-boot has initialised the
h/w

For #2 I actually have to variants

1. Which passes a DT parameter which indicates the kernel should
skip
RNG init

2. A module parameter which indicates the kernel should skip rng init

Could we discuss the kernel changes in the kernel thread ?

I believe we agree the u-boot side is right ?


Sorry, I haven't explained what I mean very well.

You are right in that sec_init() must be called to instantiate the RNG,
however the CAAM u-boot driver only partially does so. If you look at
function instantiate_rng() in both u-boot (drivers/crypto/fsl/jr.c) and
the kernel (drivers/crypto/caam/ctrl.c), you'll see that the kernel
loops over all available state handles whereas u-boot does not.

Fixing this in u-boot should mean that you can drop patch 5 and 6 from
your kernel series since the kernel should then skip over all state
handles.


Are you sure about that ?

It looks to me as if we will hit this block of code fairly decisively 
without #5 and #6


clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);

while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
 --timeout)
cpu_relax();

if (!timeout) {
dev_err(ctrldev, "failed to acquire DECO 0\n");
clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
return -ENODEV;
}

... but again let's discuss that in the kernel thread.


I can send out a patch later today to fix this on the u-boot side.


I'll certainly try out your patch on top of these patches.



Thanks,
Lukas


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Re: [U-Boot] [RFC PATCH] Allow providing default environment from file

[Lukasz Majewski]

Hi Rasmus,

> It is sometimes useful to be able to define the entire default
> environment in an external file.

There is already available script for extracting the environment.

Please look into:
./scripts/get_default_envs.sh

Maybe you can reuse it in this patch?

> This implements a Kconfig option for
> allowing that.
> 
> It is somewhat annoying to have two visible Kconfig options; it would
> probably be more user-friendly to just have the string option (with
> empty string obviously meaning not to use this feature). But then we'd
> also need a hidden CONFIG that we can use in the #ifdef in
> env_default.h, and I don't think one can set a def_bool based on
> whether a string-valued config is empty or not.
> 
> I've tried to make the accepted format the same as the one the
> mkenvimage tool accepts. I have no idea how portable the sed script
> implementing the "allow embedded newlines in values" is. Nor do I know
> if one can expect xxd to be available.
> 
> Signed-off-by: Rasmus Villemoes 
> ---
>  Makefile  | 16 
>  env/Kconfig   | 18 ++
>  include/env_default.h |  4 
>  3 files changed, 38 insertions(+)
> 
> diff --git a/Makefile b/Makefile
> index 4981a2ed6f..e5ba5213fd 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -423,6 +423,7 @@ endif
>  
>  version_h := include/generated/version_autogenerated.h
>  timestamp_h := include/generated/timestamp_autogenerated.h
> +defaultenv_h := include/generated/defaultenv_autogenerated.h
>  
>  no-dot-config-targets := clean clobber mrproper distclean \
>help %docs check% coccicheck \
> @@ -1366,6 +1367,10 @@ ifeq ($(wildcard $(LDSCRIPT)),)
>   @/bin/false
>  endif
>  
> +ifeq ($(CONFIG_DEFAULT_ENV_FROM_FILE),y)
> +prepare1: $(defaultenv_h)
> +endif
> +
>  archprepare: prepare1 scripts_basic
>  
>  prepare0: archprepare FORCE
> @@ -1413,12 +1418,23 @@ define filechk_timestamp.h
>   fi)
>  endef
>  
> +define filechk_defaultenv.h
> + (grep -v '^#' | \
> +  grep -v '^$$' | \
> +  tr '\n' '\0' | \
> +  sed -e 's/\\\x0/\n/' | \
> +  xxd -i ; echo ", 0x00" ; )
> +endef
> +
>  $(version_h): include/config/uboot.release FORCE
>   $(call filechk,version.h)
>  
>  $(timestamp_h): $(srctree)/Makefile FORCE
>   $(call filechk,timestamp.h)
>  
> +$(defaultenv_h): $(CONFIG_DEFAULT_ENV_FILE:"%"=%) FORCE
> + $(call filechk,defaultenv.h)
> +
>  #
> ---
> quiet_cmd_cpp_lds = LDS $@ cmd_cpp_lds = $(CPP)
> -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) \ diff --git
> a/env/Kconfig b/env/Kconfig index a24370786b..1baebd743b 100644
> --- a/env/Kconfig
> +++ b/env/Kconfig
> @@ -482,4 +482,22 @@ config ENV_SIZE
>  
>  endif
>  
> +config DEFAULT_ENV_FROM_FILE
> + bool "Create default environment from file"
> + help
> +   Normally, the default environment is automatically
> generated
> +   based on the settings of various CONFIG_* options, as well
> +   as the CONFIG_EXTRA_ENV_SETTINGS. By selecting this option,
> +   you can instead define the entire default environment in an
> +   external file.
> +
> +config DEFAULT_ENV_FILE
> + string "Path to default environment file"
> + depends on DEFAULT_ENV_FROM_FILE
> + help
> +   The path containing the default environment. The format is
> +   the same as accepted by the mkenvimage tool: lines
> +   containing key=value pairs, blank lines and lines beginning
> +   with # are ignored.
> +
>  endmenu
> diff --git a/include/env_default.h b/include/env_default.h
> index b574345af2..656d202cc7 100644
> --- a/include/env_default.h
> +++ b/include/env_default.h
> @@ -22,6 +22,7 @@ static char default_environment[] = {
>  #else
>  const uchar default_environment[] = {
>  #endif
> +#ifndef CONFIG_DEFAULT_ENV_FROM_FILE
>  #ifdef   CONFIG_ENV_CALLBACK_LIST_DEFAULT
>   ENV_CALLBACK_VAR "=" CONFIG_ENV_CALLBACK_LIST_DEFAULT "\0"
>  #endif
> @@ -108,6 +109,9 @@ const uchar default_environment[] = {
>   CONFIG_EXTRA_ENV_SETTINGS
>  #endif
>   "\0"
> +#else /* CONFIG_DEFAULT_ENV_FROM_FILE */
> +#include "generated/defaultenv_autogenerated.h"
> +#endif
>  #ifdef DEFAULT_ENV_INSTANCE_EMBEDDED
>   }
>  #endif



Best regards,

Lukasz Majewski

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Re: [U-Boot] FW: u-boot v2016 vs v2013

[Lukasz Majewski]

Hi,

> On Wed, Jan 24, 2018 at 10:26 AM, Mehmet Ali İPİN
>  wrote:
> > Dear Estevam,
> >
> > I am (in fact hardware engineer developed the PCB)  not an
> > experienced u-boot/linux developer, therefore sorry for my complex
> > questions. I will check the forum, and google for this message, but
> > you may help me to start the right path.
> >
> > May be, according to your experience you can advise me to check
> > some (phy/mac) register, pin status, clock values, Or give the name
> > of threads in u-boot or nxp imx6 forum which is about similar dhcp
> > events, if you remember.
> >
> > Since its a new PCB board, so we did not load/run the linux yet.  
> 
> Try looking at existing supported boards that use KSZ9021, such as
> board/boundary/nitrogen6x/nitrogen6x.c for example.

If I may add a remark here. If this is a new board - then look for
RGMII's internal delays, which are set in the ETH PHY chip. You may get
default values, which may not be correct in your new PCB design.

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Best regards,

Lukasz Majewski

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Re: [U-Boot] [RESEND PATCH] ddr: altera: silence PHY calibration unless in debug mode

[Marek Vasut]

On 01/25/2018 07:04 AM, Goldschmidt Simon wrote:
> This driver has been using printf() including filename since it was
> added. Convert to using debug() instead.
> 
> Signed-off-by: Simon Goldschmidt 

Applied, thanks

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Re: [U-Boot] [PATCH v2] arm: socfpga: allow configs without network support

[Marek Vasut]

On 01/25/2018 07:18 AM, Simon Goldschmidt wrote:
> Currently, socfpga_common.h does not allow configurations without
> network support. This is because CONFIG_CMD_PXE is defined in this
> file and distro mode has DHCP hard-coded as available.
> 
> Fix this by moving CONFIG_CMD_PXE and CONFIG_MENU to the defconfigs
> and by making DHCP optional in BOOT_TARGET_DEVICES(func).
> 
> Signed-off-by: Simon Goldschmidt 

Applied, thanks

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Re: [U-Boot] rockchip: dts: rk3128: update pwm-cell for pwm0

[Philipp Tomsich]

> The backlight pwm-cell is 3.
> 
> This remove the warning in buildman:
> arch/arm/dts/rk3126-evb.dtb: Warning (pwms_property): Property 'pwms', cell 3 
> is not a phandle reference in /backlight
> arch/arm/dts/rk3126-evb.dtb: Warning (pwms_property): Missing property 
> '#pwm-cells' in node /sram@10080400 or bad phandle (referred from 
> /backlight:pwms[3])
> 
> Signed-off-by: Kever Yang 
> ---
> 
>  arch/arm/dts/rk3128.dtsi | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 19/20] clk: rockchip: clk_rk3288: Implement "assign-clock-parent" and "assign-clock-rate"

[Philipp Tomsich]

> The RK3288 CRU-node assigns rates to a number of clocks that are not
> implemented in the RK3288 clock-driver (but which have been
> sufficiently initialised from rkclk_init()): for these clocks, we
> implement the gmac clock set parent, but simply ignore the
> others' set_rate() operation and return 0 to signal success.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - New patch
> 
> Changes in v2: None
> 
>  drivers/clk/rockchip/clk_rk3288.c  | 106 
> ++---
>  include/dt-bindings/clock/rk3288-cru.h |   1 +
>  2 files changed, 99 insertions(+), 8 deletions(-)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] rockchip: rk3036: enable rockusb support on rk3036 based device

[Philipp Tomsich]

> Rockchip Rockusb driver already merged. So we enable rockusb
> support on rk3036 based device.
> 
> Signed-off-by: Eddie Cai 
> ---
>  arch/arm/mach-rockchip/Kconfig | 2 ++
>  1 file changed, 2 insertions(+)
> 

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Re: [U-Boot] [U-Boot, v3, 18/20] ARM: dts: rk3288: Remove unused LCDC clock assigned

[Philipp Tomsich]

> The LCDC assigned rate is 0, it will make boot error,
> error log:"pll_para_config: the frequency can not be
>  0 Hz". Remove them, and the lcdc driver will do the
> correct clock rate setting.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - New patch
> 
> Changes in v2: None
> 
>  arch/arm/dts/rk3288.dtsi | 7 ++-
>  1 file changed, 2 insertions(+), 5 deletions(-)
> 

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Re: [U-Boot] [U-Boot, v3, 17/20] config: evb-rk3229: Enable rk gmac configs

[Philipp Tomsich]

> Add gmac config support for rk3229 evb.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - New patch
> 
>  configs/evb-rk3229_defconfig | 5 +
>  1 file changed, 5 insertions(+)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 16/20] net: gmac_rockchip: Add support for the RK3228 GMAC

[Philipp Tomsich]

> The GMAC in the RK3228 once again is identical to the incarnation in
> the RK3288 and the RK3399, except for where some of the configuration
> and control registers are located in the GRF.
> 
> This adds the RK3368-specific logic necessary to reuse this driver.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - New patch
> 
>  drivers/net/gmac_rockchip.c | 85 
> +
>  1 file changed, 85 insertions(+)
> 

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Re: [U-Boot] spl: atf: pass NULL for bl32_ep pc

[Philipp Tomsich]

> ATF use bl32_ep_info->pc to decide if thre is an available bl32,
> let's mark it as NULL first.
> 
> Signed-off-by: Kever Yang 
> ---
> 
>  common/spl/spl_atf.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 

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Re: [U-Boot] [U-Boot, v3, 15/20] clk: rockchip: Add rk322x gamc clock support

[Philipp Tomsich]

> Assuming mac_clk is fed by an external clock, set clk_rmii_src
> clock select control register from IO for rgmii interface.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - Add "set parent" for gmac
> - Add internal mac clk div_sel for gmac
> 
> Changes in v2:
> - New patch
> 
>  drivers/clk/rockchip/clk_rk322x.c | 107 
> ++
>  1 file changed, 107 insertions(+)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 14/20] rockchip: pinctrl: Add rk322x gmac pinctrl support

[Philipp Tomsich]

> Set gmac pins iomux and rgmii tx pins to 12ma drive-strength,
> clean others to 2ma.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - adhere to the established way of writing this to avoid future confusion
> - use defined symbolic constants for drive-strength
> 
> Changes in v2:
> - New patch
> 
>  drivers/pinctrl/rockchip/pinctrl_rk322x.c | 148 
> ++
>  1 file changed, 148 insertions(+)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 20/20] clk: rockchip: clk_rk3368: Implement "assign-clock-parent"

[Philipp Tomsich]

> Implement the setting parent for gmac clock, and add internal
> pll div set for mac clk.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - New patch
> 
> Changes in v2: None
> 
>  arch/arm/include/asm/arch-rockchip/cru_rk3368.h |  7 ++
>  drivers/clk/rockchip/clk_rk3368.c   | 91 
> +++--
>  2 files changed, 91 insertions(+), 7 deletions(-)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] [linux-sunxi] [PATCH 3/7] sun50i: a64: Move ethernet nodes to SoC DTS

[Andre Przywara]

Hi,

On 25/01/18 07:46, Maxime Ripard wrote:
> On Thu, Jan 25, 2018 at 12:21:07AM +, André Przywara wrote:
>> On 23/01/18 22:46, Kyle Evans wrote:
>>> On Tue, Jan 23, 2018 at 4:18 PM, Samuel Holland  wrote:
 These nodes were previously in an unused file specific to the Pine64.
 Move them to the base SoC device tree for use by other boards. Require
 individual boards to enable the emac and provide a pin configuration.

 Signed-off-by: Samuel Holland 
 ---
  arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi | 50 
 -
  arch/arm/dts/sun50i-a64.dtsi| 28 ++
  2 files changed, 28 insertions(+), 50 deletions(-)
  delete mode 100644 arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi
>>>
>>> On that note, it seems like it would be a good idea to re-sync this
>>> with mainline Linux now that emac bindings exist in-tree [1] and these
>>> are generally becoming standard. Thoughts?
>>
>> Sure. The problem with that is that the Ethernet nodes are no longer
>> compatible with what the U-Boot driver understands. Solutions are:
>> - Keep the EMAC nodes - in "old" U-Boot style - in a *-u-boot.dtsi
>> override. Easy enough, but bad idea.
>> - Teach the U-Boot EMAC driver to cope with the new bindings. I sent
>> patches for that a while ago [2]. Problem is that people didn't like the
>> "handish" way of parsing the pinctrl properties - instead opting for a
>> proper DM pinctrl driver for sunxi. Sounds reasonable - but is a quite a
>> chunk of work. This was on the list before - but IMHO a bit over the top
>> by copying the Linux driver.
>>
>> I was wondering if we could just go with the easy pinctrl solution (as
>> in [2], based on what we currently have in the EMAC driver). We could
>> switch anytime to a proper DM pinctrl driver - which is on my list, but
>> not very high on it. I have some ideas on how to make this small and
>> simple, as we don't need the fully glory and bloat of the Linux driver.
>>
>> If people are OK with this, I can post a rebased version of [2]. We can
>> then just copy the mainline DTs for A64 into U-Boot.
>> And leave the DM pinctrl driver for another time.
> 
> That's what I was about to suggest. The pinctrl discussion is pretty
> much orthogonal, and we'll have to convert a whole bunch of drivers
> anyway when that happens, so it's not a big deal to add a new driver
> that doesn't rely on pinctrl at the moment.

Thanks, I totally agree.

I will post something after I have tested it later tonight.
If you don't mind, I will include the mainline H3/H5 DTs as well (in a
separate patch), as they suffer from the same EMAC problem and are stuck
at a copy from an ancient kernel (if at all) at the moment.

Cheers,
Andre.
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Re: [U-Boot] [U-Boot, v4, 04/11] rockchip: rk322x: enable tpl support

[Philipp Tomsich]

> Move original spl to tpl, and add spl to load next stage firmware,
> adapt all the address and option for them.
> 
> Serial-changes: 2
> - update upon latest source
> 
> Signed-off-by: Kever Yang 
> Acked-by: Philipp Tomsich 
> ---
> 
> Changes in v4:
> - remove non-used MACRO define
> 
> Changes in v3:
> - do not init ddr region in spl
> 
> Changes in v2: None
> 
>  arch/arm/mach-rockchip/Kconfig   |  9 +++
>  arch/arm/mach-rockchip/Makefile  |  3 +-
>  arch/arm/mach-rockchip/rk322x-board-spl.c| 63 +---
>  arch/arm/mach-rockchip/rk322x-board-tpl.c| 88 
> 
>  arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds | 13 
>  include/configs/rk322x_common.h  |  9 ++-
>  6 files changed, 132 insertions(+), 53 deletions(-)
>  create mode 100644 arch/arm/mach-rockchip/rk322x-board-tpl.c
>  create mode 100644 arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 18/20] ARM: dts: rk3288: Remove unused LCDC clock assigned

[Philipp Tomsich]

> The LCDC assigned rate is 0, it will make boot error,
> error log:"pll_para_config: the frequency can not be
>  0 Hz". Remove them, and the lcdc driver will do the
> correct clock rate setting.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - New patch
> 
> Changes in v2: None
> 
>  arch/arm/dts/rk3288.dtsi | 7 ++-
>  1 file changed, 2 insertions(+), 5 deletions(-)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] rockchip: dts: rk3128: update pwm-cell for pwm0

[Philipp Tomsich]

> The backlight pwm-cell is 3.
> 
> This remove the warning in buildman:
> arch/arm/dts/rk3126-evb.dtb: Warning (pwms_property): Property 'pwms', cell 3 
> is not a phandle reference in /backlight
> arch/arm/dts/rk3126-evb.dtb: Warning (pwms_property): Missing property 
> '#pwm-cells' in node /sram@10080400 or bad phandle (referred from 
> /backlight:pwms[3])
> 
> Signed-off-by: Kever Yang 
> ---
> 
>  arch/arm/dts/rk3128.dtsi | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] rockchip: rk3036: enable rockusb support on rk3036 based device

[Philipp Tomsich]

> Rockchip Rockusb driver already merged. So we enable rockusb
> support on rk3036 based device.
> 
> Signed-off-by: Eddie Cai 
> ---
>  arch/arm/mach-rockchip/Kconfig | 2 ++
>  1 file changed, 2 insertions(+)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 16/20] net: gmac_rockchip: Add support for the RK3228 GMAC

[Philipp Tomsich]

> The GMAC in the RK3228 once again is identical to the incarnation in
> the RK3288 and the RK3399, except for where some of the configuration
> and control registers are located in the GRF.
> 
> This adds the RK3368-specific logic necessary to reuse this driver.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - New patch
> 
>  drivers/net/gmac_rockchip.c | 85 
> +
>  1 file changed, 85 insertions(+)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 17/20] config: evb-rk3229: Enable rk gmac configs

[Philipp Tomsich]

> Add gmac config support for rk3229 evb.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - New patch
> 
>  configs/evb-rk3229_defconfig | 5 +
>  1 file changed, 5 insertions(+)
> 

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Re: [U-Boot] [U-Boot, v3, 20/20] clk: rockchip: clk_rk3368: Implement "assign-clock-parent"

[Philipp Tomsich]

> Implement the setting parent for gmac clock, and add internal
> pll div set for mac clk.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - New patch
> 
> Changes in v2: None
> 
>  arch/arm/include/asm/arch-rockchip/cru_rk3368.h |  7 ++
>  drivers/clk/rockchip/clk_rk3368.c   | 91 
> +++--
>  2 files changed, 91 insertions(+), 7 deletions(-)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v4, 07/11] spl: add support to booting with OP-TEE

[Philipp Tomsich]

> OP-TEE is an open source trusted OS, in armv7, its loading and
> running are like this:
> loading:
> - SPL load both OP-TEE and U-Boot
> running:
> - SPL run into OP-TEE in secure mode;
> - OP-TEE run into U-Boot in non-secure mode;
> 
> More detail:
> https://github.com/OP-TEE/optee_os
> and search for 'boot arguments' for detail entry parameter in:
> core/arch/arm/kernel/generic_entry_a32.S
> 
> Signed-off-by: Kever Yang 
> Acked-by: Philipp Tomsich 
> ---
> 
> Changes in v4:
> - use NULL instead of '0'
> - add fdt_addr as arg2 of entry
> 
> Changes in v3: None
> Changes in v2:
> - Using new image type for op-tee
> 
>  common/spl/Kconfig |  7 +++
>  common/spl/Makefile|  1 +
>  common/spl/spl.c   |  9 +
>  common/spl/spl_optee.S | 13 +
>  include/spl.h  | 13 +
>  5 files changed, 43 insertions(+)
>  create mode 100644 common/spl/spl_optee.S
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] spl: atf: pass NULL for bl32_ep pc

[Philipp Tomsich]

> ATF use bl32_ep_info->pc to decide if thre is an available bl32,
> let's mark it as NULL first.
> 
> Signed-off-by: Kever Yang 
> ---
> 
>  common/spl/spl_atf.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 19/20] clk: rockchip: clk_rk3288: Implement "assign-clock-parent" and "assign-clock-rate"

[Philipp Tomsich]

> The RK3288 CRU-node assigns rates to a number of clocks that are not
> implemented in the RK3288 clock-driver (but which have been
> sufficiently initialised from rkclk_init()): for these clocks, we
> implement the gmac clock set parent, but simply ignore the
> others' set_rate() operation and return 0 to signal success.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - New patch
> 
> Changes in v2: None
> 
>  drivers/clk/rockchip/clk_rk3288.c  | 106 
> ++---
>  include/dt-bindings/clock/rk3288-cru.h |   1 +
>  2 files changed, 99 insertions(+), 8 deletions(-)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 03/20] rockchip: grf_rv1108.h: Fix the grf offsets

[Philipp Tomsich]

> The last 4 grf registers offset of rv1108 are wrong, fix them
> for correct usage.
> 
> Signed-off-by: David Wu 
> Reviewed-by: Simon Glass 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - New patch
> 
>  arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 06/20] rockchip: pinctrl: rk3328: Move the iomux definitions into pinctrl-driver

[Philipp Tomsich]

> Clean the iomux definitions at grf_rk3328.h, and move them into
> pinctrl-driver for resolving the compiling error of redefinition.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - New patch
> 
>  arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 113 
> 
>  drivers/pinctrl/rockchip/pinctrl_rk3328.c   | 113 
> 
>  2 files changed, 113 insertions(+), 113 deletions(-)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 15/20] clk: rockchip: Add rk322x gamc clock support

[Philipp Tomsich]

> Assuming mac_clk is fed by an external clock, set clk_rmii_src
> clock select control register from IO for rgmii interface.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - Add "set parent" for gmac
> - Add internal mac clk div_sel for gmac
> 
> Changes in v2:
> - New patch
> 
>  drivers/clk/rockchip/clk_rk322x.c | 107 
> ++
>  1 file changed, 107 insertions(+)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 09/20] net: gmac_rockchip: Add rk3328 gmac support

[Philipp Tomsich]

> The GMAC2IO in the RK3328 once again is identical to the incarnation in
> the RK3288 and the RK3399, except for where some of the configuration
> and control registers are located in the GRF.
> 
> This adds the RK3328-specific logic necessary to reuse this driver.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - New patch
> 
>  drivers/net/gmac_rockchip.c | 85 
> +
>  1 file changed, 85 insertions(+)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 12/20] rockchip: dts: rk3328-evb: Enable gmac2io for rk3328-evb

[Philipp Tomsich]

> Add rk3328-evb gmac support.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - New patch
> 
>  arch/arm/dts/rk3328-evb.dts | 30 ++
>  1 file changed, 30 insertions(+)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 03/20] rockchip: grf_rv1108.h: Fix the grf offsets

[Philipp Tomsich]

> The last 4 grf registers offset of rv1108 are wrong, fix them
> for correct usage.
> 
> Signed-off-by: David Wu 
> Reviewed-by: Simon Glass 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - New patch
> 
>  arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] [PATCH] imx: mx25: Remove SION bit in all pin-mux

[Benoît Thébaudeau]

Hi Michael,

On 25/01/2018 at 06:47, Michael Nazzareno Trimarchi wrote:
> On 25 Jan. 2018 12:07 am, "Fabio Estevam"  > wrote:
> 
> Hi Michael,
> 
> On Wed, Jan 24, 2018 at 3:46 PM, Michael Nazzareno Trimarchi
> mailto:mich...@amarulasolutions.com>> 
> wrote:
> 
> > This is exactly my initial propose. Can we give a try and manage on 
> board level?
> 
> The kernel should not rely on the IOMUX setting done by the bootloader.
> 
> Do you use 0x8000 in your dts IOMUX configuration by any chance?
> 
> 0x8000 means that the kernel will not do IOMUX configuration and
> will use the IOMUX value that comes from the bootloader.
> 
> 
> Yes but those should not be even wrong. We can not be sure if the state 
> machine of any logic as already corrupted. Remember that we have already this 
> problem with the clock in general that most of the time are already enabled 
> and so logic can be up.
> 
> 
> It seems you can fix your USB problem by not using the IOMUX value
> from the bootloader and just use the good IOMUX (without SION)
> explicitly in your dts.
> 
> Does it fix the problem?
> 
> 
> I think that the way to fix in a specific case could be more then one. I will 
> do the best on my side but I will include to not touch iomux without any 
> reason. I already point out that just with few pins configured like console I 
> get the problem . I can check two extra gpio too. 
> 
> To be clear, my board was "working". We are talking about a product in the 
> field since years with one minimal USB mulfuction . Other boards can have the 
> same problem but just not rise in the field. If the host port is direct 
> connected to the pen drive without an hub the USB reset can most of the time 
> recover the connection.

I agree with Fabio: Linux should not rely on the pad configurations performed by
U-Boot. But as you say, U-Boot should work fine itself too. Have you tested the
problematic USB pen drive with U-Boot?

Besides your USB issue, in order to optimize power consumption, iomux-mx25.h
should not set SION by default, except for the pad functions that can in no way
work without it (still to be identified/tested). For the other use cases, the
board files can set SION themselves, thanks to a NEW_PAD_CTRL()-like mechanism
(apparently yet to be introduced into U-Boot). The changes introduced here
should not break anything for the current in-tree boards.

You said that setting SION only for a UART is enough to trigger your USB issue.
Of course, there is no reason to set SION by default for a UART, but I was
thinking about a possible link between UART and USB, as this behavior is very
strange. Which USB host port are use using with the problematic pen drive, and
with which PHY (SoC-internal/external, bus)? Have you checked that this port is
properly configured for this PHY and PWR/OC (on/off + polarity) in both U-Boot
and Linux? For instance, if this port is configured to use OC but no OC signal
is actually wired, this can probably do weird things.

Best regards,
Benoît
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Re: [U-Boot] [RFC PATCH] Allow providing default environment from file

[Rasmus Villemoes]

On 2018-01-25 10:30, Lukasz Majewski wrote:
> Hi Rasmus,
> 
>> It is sometimes useful to be able to define the entire default
>> environment in an external file.
> 
> There is already available script for extracting the environment.
> 
> Please look into:
> ./scripts/get_default_envs.sh
> 
> Maybe you can reuse it in this patch?

I'm sorry, but I don't see what I could use that for. It seems to do the
opposite of what I want, namely extract the default environment and
store it in a plain-text file. I want to provide a plain-text file to
define the default environment.

It's quite likely that that script can be useful for generating a sketch
for the external file (i.e., build a U-boot as "usual" with default
environment built from various config options etc. etc., then hand-edit
that file to remove redundant stuff and add the things one needs). The
thing is, having the default environment in an external file makes it
much easier to put it under version control than having to maintain a
branch inside the U-boot repo just to tweak CONFIG_EXTRA_ENV_SETTINGS.

Rasmus
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Re: [U-Boot] [U-Boot, v3, 08/20] clk: rockchip: Add rk3328 gamc clock support

[Philipp Tomsich]

> The rk3328 soc has two gmac controllers, one is gmac2io,
> the other is gmac2phy. We use the gmac2io rgmii interface
> for 1000M phy here.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - Add "set parent" for gmac2io
> - Add internal mac clk div_sel for gmac2io
> 
> Changes in v2:
> - New patch
> 
>  drivers/clk/rockchip/clk_rk3328.c  | 178 
> +
>  include/dt-bindings/clock/rk3328-cru.h |   6 +-
>  2 files changed, 181 insertions(+), 3 deletions(-)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 07/20] rockchip: pinctrl: Add rk3328 gmac pinctrl support

[Philipp Tomsich]

> Need to set gmac m1 pins iomux, gmac m0 tx pins, select bit2
> and bit10 at com iomux register. After that, set rgmii m1 tx
> pins to 12ma drive-strength, and clean others to 2ma.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - adhere to the established way of writing this to avoid future confusion
> - use defined symbolic constants for drive-strength
> 
> Changes in v2:
> - New patch
> 
>  arch/arm/include/asm/arch-rockchip/grf_rk3328.h |   1 -
>  drivers/pinctrl/rockchip/pinctrl_rk3328.c   | 275 
> 
>  2 files changed, 275 insertions(+), 1 deletion(-)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 10/20] rockchip: configs: Enable GMAC configs for evb-rk3328

[Philipp Tomsich]

> Enable GMAC configs for evb-rk3328
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - New patch
> 
>  configs/evb-rk3328_defconfig | 5 +
>  1 file changed, 5 insertions(+)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 06/20] rockchip: pinctrl: rk3328: Move the iomux definitions into pinctrl-driver

[Philipp Tomsich]

> Clean the iomux definitions at grf_rk3328.h, and move them into
> pinctrl-driver for resolving the compiling error of redefinition.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - New patch
> 
>  arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 113 
> 
>  drivers/pinctrl/rockchip/pinctrl_rk3328.c   | 113 
> 
>  2 files changed, 113 insertions(+), 113 deletions(-)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 10/20] rockchip: configs: Enable GMAC configs for evb-rk3328

[Philipp Tomsich]

> Enable GMAC configs for evb-rk3328
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - New patch
> 
>  configs/evb-rk3328_defconfig | 5 +
>  1 file changed, 5 insertions(+)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 12/20] rockchip: dts: rk3328-evb: Enable gmac2io for rk3328-evb

[Philipp Tomsich]

> Add rk3328-evb gmac support.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - New patch
> 
>  arch/arm/dts/rk3328-evb.dts | 30 ++
>  1 file changed, 30 insertions(+)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 11/20] rockchip: dts: rk3328: Add gmac2io support

[Philipp Tomsich]

> Add basic dts configuration for rk3328 gmac2io.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - New patch
> 
>  arch/arm/dts/rk3328.dtsi | 19 +++
>  1 file changed, 19 insertions(+)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v4, 07/11] spl: add support to booting with OP-TEE

[Bryan O'Donoghue]

On 18/01/18 11:21, Bryan O'Donoghue wrote:



On 18/01/18 01:31, Kever Yang wrote:
I don't think we can reuse IH_TYPE_TEE， it use a optee.img type 
create by mkimage and it seem use more then one cpu.


Don't really understand what you mean by using more than one CPU - can 
you give an example in the code ?


---
bod


So - what's the proposed resolution here ?
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Re: [U-Boot] [U-Boot, v3, 11/20] rockchip: dts: rk3328: Add gmac2io support

[Philipp Tomsich]

> Add basic dts configuration for rk3328 gmac2io.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - New patch
> 
>  arch/arm/dts/rk3328.dtsi | 19 +++
>  1 file changed, 19 insertions(+)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 04/20] rockchip: pinctrl: rv1108: Move the iomux definitions into pinctrl-driver

[Philipp Tomsich]

> If we include both the rk3288_grf.h and rv1108_grf.h, it will cause the
> conflicts of redefinition. Clean the iomux definitions at grf_rv1108.h,
> and move them into pinctrl-driver.
> 
> Signed-off-by: David Wu 
> Reviewed-by: Philipp Tomsich 
> ---
> 
> Changes in v3:
> - Fix the wrong define for uart2M0
> 
> Changes in v2:
> - New patch
> 
>  arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 399 
> 
>  board/rockchip/evb_rv1108/evb_rv1108.c  |  17 +
>  drivers/pinctrl/rockchip/pinctrl_rv1108.c   | 399 
> 
>  3 files changed, 416 insertions(+), 399 deletions(-)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 07/20] rockchip: pinctrl: Add rk3328 gmac pinctrl support

[Philipp Tomsich]

> Need to set gmac m1 pins iomux, gmac m0 tx pins, select bit2
> and bit10 at com iomux register. After that, set rgmii m1 tx
> pins to 12ma drive-strength, and clean others to 2ma.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - adhere to the established way of writing this to avoid future confusion
> - use defined symbolic constants for drive-strength
> 
> Changes in v2:
> - New patch
> 
>  arch/arm/include/asm/arch-rockchip/grf_rk3328.h |   1 -
>  drivers/pinctrl/rockchip/pinctrl_rk3328.c   | 275 
> 
>  2 files changed, 275 insertions(+), 1 deletion(-)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 04/20] rockchip: pinctrl: rv1108: Move the iomux definitions into pinctrl-driver

[Philipp Tomsich]

> If we include both the rk3288_grf.h and rv1108_grf.h, it will cause the
> conflicts of redefinition. Clean the iomux definitions at grf_rv1108.h,
> and move them into pinctrl-driver.
> 
> Signed-off-by: David Wu 
> Reviewed-by: Philipp Tomsich 
> ---
> 
> Changes in v3:
> - Fix the wrong define for uart2M0
> 
> Changes in v2:
> - New patch
> 
>  arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 399 
> 
>  board/rockchip/evb_rv1108/evb_rv1108.c  |  17 +
>  drivers/pinctrl/rockchip/pinctrl_rv1108.c   | 399 
> 
>  3 files changed, 416 insertions(+), 399 deletions(-)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 13/20] rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driver

[Philipp Tomsich]

> Clean the iomux definitions at grf_rk322x.h, and move them into
> pinctrl-driver for resolving the compiling error of redefinition.
> After that, define the uart2 iomux at rk322x-board file.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - Fix the wrong define for uart2 iomux
> 
> Changes in v2:
> - New patch
> 
>  arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 455 
> 
>  arch/arm/mach-rockchip/rk322x-board-spl.c   |  22 +-
>  arch/arm/mach-rockchip/rk322x-board.c   |  18 +
>  drivers/pinctrl/rockchip/pinctrl_rk322x.c   | 453 +++
>  4 files changed, 492 insertions(+), 456 deletions(-)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 14/20] rockchip: pinctrl: Add rk322x gmac pinctrl support

[Philipp Tomsich]

> Set gmac pins iomux and rgmii tx pins to 12ma drive-strength,
> clean others to 2ma.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - adhere to the established way of writing this to avoid future confusion
> - use defined symbolic constants for drive-strength
> 
> Changes in v2:
> - New patch
> 
>  drivers/pinctrl/rockchip/pinctrl_rk322x.c | 148 
> ++
>  1 file changed, 148 insertions(+)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 05/20] net: gmac_rockchip: Add support for the RV1108 GMAC

[Philipp Tomsich]

> The rv1108 GMAC only support rmii interface, so need to add the
> set_rmii() ops. Use the phy current interface to set rmii or
> rgmii ops. At the same time, need to set the mac clock rate of
> rmii with 50M, the clock rate of rgmii with 125M.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - return error if there was no set_to_rgmii ops at rgmii case
> - return error if there was no set_to_rmii ops at rmii case
> - set and check clock rate when gmac clock is internal pll.
> 
> Changes in v2:
> - Add check whether the set rgmii/rmii function is a valid function pointer
> - Clean the grf offset at gmac_rockchip.c
> - Use current phy interface to set mac clock rate
> 
>  drivers/net/gmac_rockchip.c | 115 
> +---
>  1 file changed, 109 insertions(+), 6 deletions(-)
> 

Reviewed-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 13/20] rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driver

[Philipp Tomsich]

> Clean the iomux definitions at grf_rk322x.h, and move them into
> pinctrl-driver for resolving the compiling error of redefinition.
> After that, define the uart2 iomux at rk322x-board file.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - Fix the wrong define for uart2 iomux
> 
> Changes in v2:
> - New patch
> 
>  arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 455 
> 
>  arch/arm/mach-rockchip/rk322x-board-spl.c   |  22 +-
>  arch/arm/mach-rockchip/rk322x-board.c   |  18 +
>  drivers/pinctrl/rockchip/pinctrl_rk322x.c   | 453 +++
>  4 files changed, 492 insertions(+), 456 deletions(-)
> 

Acked-by: Philipp Tomsich 
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Re: [U-Boot] [U-Boot, v3, 08/20] clk: rockchip: Add rk3328 gamc clock support

[Philipp Tomsich]

> The rk3328 soc has two gmac controllers, one is gmac2io,
> the other is gmac2phy. We use the gmac2io rgmii interface
> for 1000M phy here.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - Add "set parent" for gmac2io
> - Add internal mac clk div_sel for gmac2io
> 
> Changes in v2:
> - New patch
> 
>  drivers/clk/rockchip/clk_rk3328.c  | 178 
> +
>  include/dt-bindings/clock/rk3328-cru.h |   6 +-
>  2 files changed, 181 insertions(+), 3 deletions(-)
> 

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Re: [U-Boot] [U-Boot, v3, 09/20] net: gmac_rockchip: Add rk3328 gmac support

[Philipp Tomsich]

> The GMAC2IO in the RK3328 once again is identical to the incarnation in
> the RK3288 and the RK3399, except for where some of the configuration
> and control registers are located in the GRF.
> 
> This adds the RK3328-specific logic necessary to reuse this driver.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - New patch
> 
>  drivers/net/gmac_rockchip.c | 85 
> +
>  1 file changed, 85 insertions(+)
> 

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Re: [U-Boot] [U-Boot, v3, 05/20] net: gmac_rockchip: Add support for the RV1108 GMAC

[Philipp Tomsich]

> The rv1108 GMAC only support rmii interface, so need to add the
> set_rmii() ops. Use the phy current interface to set rmii or
> rgmii ops. At the same time, need to set the mac clock rate of
> rmii with 50M, the clock rate of rgmii with 125M.
> 
> Signed-off-by: David Wu 
> ---
> 
> Changes in v3:
> - return error if there was no set_to_rgmii ops at rgmii case
> - return error if there was no set_to_rmii ops at rmii case
> - set and check clock rate when gmac clock is internal pll.
> 
> Changes in v2:
> - Add check whether the set rgmii/rmii function is a valid function pointer
> - Clean the grf offset at gmac_rockchip.c
> - Use current phy interface to set mac clock rate
> 
>  drivers/net/gmac_rockchip.c | 115 
> +---
>  1 file changed, 109 insertions(+), 6 deletions(-)
> 

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Re: [U-Boot] [PATCH] imx: mx25: Remove SION bit in all pin-mux

[Michael Nazzareno Trimarchi]

Hi

On Thu, Jan 25, 2018 at 11:02 AM, Benoît Thébaudeau  wrote:
> Hi Michael,
>
> On 25/01/2018 at 06:47, Michael Nazzareno Trimarchi wrote:
>> On 25 Jan. 2018 12:07 am, "Fabio Estevam" > > wrote:
>>
>> Hi Michael,
>>
>> On Wed, Jan 24, 2018 at 3:46 PM, Michael Nazzareno Trimarchi
>> mailto:mich...@amarulasolutions.com>> 
>> wrote:
>>
>> > This is exactly my initial propose. Can we give a try and manage on 
>> board level?
>>
>> The kernel should not rely on the IOMUX setting done by the bootloader.
>>
>> Do you use 0x8000 in your dts IOMUX configuration by any chance?
>>
>> 0x8000 means that the kernel will not do IOMUX configuration and
>> will use the IOMUX value that comes from the bootloader.
>>
>>
>> Yes but those should not be even wrong. We can not be sure if the state 
>> machine of any logic as already corrupted. Remember that we have already 
>> this problem with the clock in general that most of the time are already 
>> enabled and so logic can be up.
>>
>>
>> It seems you can fix your USB problem by not using the IOMUX value
>> from the bootloader and just use the good IOMUX (without SION)
>> explicitly in your dts.
>>
>> Does it fix the problem?
>>
>>
>> I think that the way to fix in a specific case could be more then one. I 
>> will do the best on my side but I will include to not touch iomux without 
>> any reason. I already point out that just with few pins configured like 
>> console I get the problem . I can check two extra gpio too.
>>
>> To be clear, my board was "working". We are talking about a product in the 
>> field since years with one minimal USB mulfuction . Other boards can have 
>> the same problem but just not rise in the field. If the host port is direct 
>> connected to the pen drive without an hub the USB reset can most of the time 
>> recover the connection.
>
> I agree with Fabio: Linux should not rely on the pad configurations performed 
> by

This is not the linux mailing list

> U-Boot. But as you say, U-Boot should work fine itself too. Have you tested 
> the
> problematic USB pen drive with U-Boot?
>

ehci phy of imx25 is not supported in uboot I think and it's not in
the scope of this change


> Besides your USB issue, in order to optimize power consumption, iomux-mx25.h
> should not set SION by default, except for the pad functions that can in no 
> way
> work without it (still to be identified/tested). For the other use cases, the
> board files can set SION themselves, thanks to a NEW_PAD_CTRL()-like mechanism
> (apparently yet to be introduced into U-Boot). The changes introduced here
> should not break anything for the current in-tree boards.

yes I know.

>
> You said that setting SION only for a UART is enough to trigger your USB 
> issue.
> Of course, there is no reason to set SION by default for a UART, but I was
> thinking about a possible link between UART and USB, as this behavior is very
> strange. Which USB host port are use using with the problematic pen drive, and
> with which PHY (SoC-internal/external, bus)? Have you checked that this port 
> is
> properly configured for this PHY and PWR/OC (on/off + polarity) in both U-Boot
> and Linux? For instance, if this port is configured to use OC but no OC signal

Nothing of above is connected. Pen drive is in the linux thread
described in the commit
message. All the usb stack is fully functional with a lot of pen
drive. OC, PWR are not
managed on USB/serial ehci port so they are not involved and I can
check. I have posted
some patches on linux mailing list to fix minor stuff. Let's say any
permutation bit on phy
configuration does not solve the problem. It's not a problem of usb
suspend etc. I think that
approch should be:

- align the pin mux mx25 file to the other architecture. So drop all
the sion bit expect for the one
where we know that silicon is buggy
- apply SION when is needed in the board that are already in uboot
- send patches on pin mux for board that are in mainline and we can test

On my side. I will restrict the change on my board to full isolate the
configuration. Force the reset of SION
bit anyway in linux if this solve.

Agree?

Michael

> is actually wired, this can probably do weird things.
>
> Best regards,
> Benoît



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Re: [U-Boot] [PATCH 1/7] mmc: uniphier-sd: Use mmc_of_parse()

[Masahiro Yamada]

2018-01-25 10:01 GMT+09:00 Jaehoon Chung :
> Hi,
>
> On 01/17/2018 02:16 AM, Marek Vasut wrote:
>> Drop the ad-hoc DT caps parsing in favor of common framework function.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Jaehoon Chung 
>> Cc: Masahiro Yamada 
>
> If Masahiro is ok, i will pick this patch and others to u-boot-mmc.
>
> Best Regards,
> Jaehoon Chung


Acked-by: Masahiro Yamada 



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Re: [U-Boot] [PATCH] mmc: uniphier-sd: Add compatible strings for RCar Gen2

[Masahiro Yamada]

2018-01-25 9:58 GMT+09:00 Jaehoon Chung :
> On 01/25/2018 07:19 AM, Marek Vasut wrote:
>> Add DT compatible strings for RCar Gen2 SoCs, so that this driver
>> can bind with them. Unlike Gen3, which uses 64bit FIFO, the Gen2
>> uses 16bit FIFO.
>>
>> Signed-off-by: Marek Vasut 
>> Cc: Jaehoon Chung 
>> Cc: Masahiro Yamada 
>
> Reviewed-by: Jaehoon Chung 
>
>> ---
>>  drivers/mmc/uniphier-sd.c | 5 +
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
>> index 741f9dfd9c..a080674c8a 100644
>> --- a/drivers/mmc/uniphier-sd.c
>> +++ b/drivers/mmc/uniphier-sd.c
>> @@ -847,6 +847,11 @@ static int uniphier_sd_probe(struct udevice *dev)
>>  }
>>
>>  static const struct udevice_id uniphier_sd_match[] = {
>> + { .compatible = "renesas,sdhi-r8a7790", .data = 0 },
>> + { .compatible = "renesas,sdhi-r8a7791", .data = 0 },
>> + { .compatible = "renesas,sdhi-r8a7792", .data = 0 },
>> + { .compatible = "renesas,sdhi-r8a7793", .data = 0 },
>> + { .compatible = "renesas,sdhi-r8a7794", .data = 0 },
>>   { .compatible = "renesas,sdhi-r8a7795", .data = UNIPHIER_SD_CAP_64BIT 
>> },
>>   { .compatible = "renesas,sdhi-r8a7796", .data = UNIPHIER_SD_CAP_64BIT 
>> },
>>   { .compatible = "renesas,sdhi-r8a77970", .data = UNIPHIER_SD_CAP_64BIT 
>> },
>>
>


Nit:
You can omit ".data = 0 " if you want.

Otherwise,

Acked-by: Masahiro Yamada 





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Re: [U-Boot] [PATCH V2 2/7] mmc: uniphier-sd: Properly handle pin voltage configuration

[Masahiro Yamada]

2018-01-17 2:16 GMT+09:00 Marek Vasut :
> Factor out the regulator handling into set_ios and add support for
> selecting pin configuration based on the voltage to support UHS modes.
>
> Signed-off-by: Marek Vasut 
> Cc: Jaehoon Chung 
> Cc: Masahiro Yamada 
> ---
> V2: Protect vqmmc_dev access in uniphier_sd_set_pins() with an ifdef
> just like everywhere else
> ---
>  drivers/mmc/uniphier-sd.c | 35 ++-
>  1 file changed, 26 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
> index 552e37d852..e6c610a22a 100644
> --- a/drivers/mmc/uniphier-sd.c
> +++ b/drivers/mmc/uniphier-sd.c
> @@ -10,6 +10,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -134,6 +135,9 @@ struct uniphier_sd_priv {
>  #define UNIPHIER_SD_CAP_DMA_INTERNAL   BIT(1)  /* have internal DMA engine */
>  #define UNIPHIER_SD_CAP_DIV1024BIT(2)  /* divisor 1024 is 
> available */
>  #define UNIPHIER_SD_CAP_64BIT  BIT(3)  /* Controller is 64bit */
> +#ifdef CONFIG_DM_REGULATOR
> +   struct udevice *vqmmc_dev;
> +#endif
>  };
>
>  static u64 uniphier_sd_readq(struct uniphier_sd_priv *priv, unsigned int reg)
> @@ -676,6 +680,26 @@ static void uniphier_sd_set_clk_rate(struct 
> uniphier_sd_priv *priv,
> udelay(1000);
>  }
>
> +static void uniphier_sd_set_pins(struct udevice *dev)
> +{
> +   struct uniphier_sd_priv *priv = dev_get_priv(dev);
> +   struct mmc *mmc = mmc_get_mmc_dev(dev);


This gives me a new warning for my board, where CONFIG_DM_REGULATOR is disabled.

drivers/mmc/uniphier-sd.c:685:27: warning: unused variable ‘priv’
[-Wunused-variable]
  struct uniphier_sd_priv *priv = dev_get_priv(dev);
   ^~~~

Is it reasonable to surround the whole this function by
#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE) ?


> +#ifdef CONFIG_DM_REGULATOR
> +   if (priv->vqmmc_dev) {
> +   if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
> +   regulator_set_value(priv->vqmmc_dev, 180);
> +   else
> +   regulator_set_value(priv->vqmmc_dev, 330);
> +   }
> +#endif
> +
> +   if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
> +   pinctrl_select_state(dev, "state_uhs");
> +   else
> +   pinctrl_select_state(dev, "default");
> +}

I am not sure about this code.
If MMC_SIGNAL_VOLTAGE_180 is set, is it always UHS?
eMMC also can do 1.8V signaling.





>  static int uniphier_sd_set_ios(struct udevice *dev)
>  {
> struct uniphier_sd_priv *priv = dev_get_priv(dev);
> @@ -690,6 +714,7 @@ static int uniphier_sd_set_ios(struct udevice *dev)
> return ret;
> uniphier_sd_set_ddr_mode(priv, mmc);
> uniphier_sd_set_clk_rate(priv, mmc);
> +   uniphier_sd_set_pins(dev);
>
> return 0;
>  }
> @@ -757,9 +782,6 @@ static int uniphier_sd_probe(struct udevice *dev)
> fdt_addr_t base;
> struct clk clk;
> int ret;
> -#ifdef CONFIG_DM_REGULATOR
> -   struct udevice *vqmmc_dev;
> -#endif
>
> base = devfdt_get_addr(dev);
> if (base == FDT_ADDR_T_NONE)
> @@ -770,12 +792,7 @@ static int uniphier_sd_probe(struct udevice *dev)
> return -ENOMEM;
>
>  #ifdef CONFIG_DM_REGULATOR
> -   ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
> -   if (!ret) {
> -   /* Set the regulator to 3.3V until we support 1.8V modes */
> -   regulator_set_value(vqmmc_dev, 330);
> -   regulator_set_enable(vqmmc_dev, true);
> -   }
> +   ret = device_get_supply_regulator(dev, "vqmmc-supply", 
> &priv->vqmmc_dev);
>  #endif
>
> ret = clk_get_by_index(dev, 0, &clk);


The return value from device_get_supply_regulator()
is overwritten by the following clk_get_by_index().

Shouldn't it be checked?


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Re: [U-Boot] [PATCH 3/7] mmc: uniphier-sd: Add Renesas RCar quirks

[Masahiro Yamada]

2018-01-17 2:16 GMT+09:00 Marek Vasut :
> Add a quirk to identify that the controller is Renesas RCar variant
> of the Matsushita SD IP and another quirk indicating it can support
> Renesas RCar HS200/HS400/SDR104 modes.
>
> Signed-off-by: Marek Vasut 
> Cc: Jaehoon Chung 
> Cc: Masahiro Yamada 
> ---
>  drivers/mmc/uniphier-sd.c | 13 +
>  1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
> index e6c610a22a..2f7ec680a3 100644
> --- a/drivers/mmc/uniphier-sd.c
> +++ b/drivers/mmc/uniphier-sd.c
> @@ -135,6 +135,8 @@ struct uniphier_sd_priv {
>  #define UNIPHIER_SD_CAP_DMA_INTERNAL   BIT(1)  /* have internal DMA engine */
>  #define UNIPHIER_SD_CAP_DIV1024BIT(2)  /* divisor 1024 is 
> available */
>  #define UNIPHIER_SD_CAP_64BIT  BIT(3)  /* Controller is 64bit */
> +#define UNIPHIER_SD_CAP_RCAR   BIT(4)  /* Renesas RCar version of IP 
> */
> +#define UNIPHIER_SD_CAP_RCAR_UHS   BIT(5)  /* Renesas RCar UHS/SDR modes 
> */
>  #ifdef CONFIG_DM_REGULATOR
> struct udevice *vqmmc_dev;
>  #endif
> @@ -854,11 +856,14 @@ static int uniphier_sd_probe(struct udevice *dev)
> return 0;
>  }
>
> +#define RENESAS_SD_QUIRKS  \
> +   UNIPHIER_SD_CAP_64BIT | UNIPHIER_SD_CAP_RCAR | 
> UNIPHIER_SD_CAP_RCAR_UHS
> +
>  static const struct udevice_id uniphier_sd_match[] = {
> -   { .compatible = "renesas,sdhi-r8a7795", .data = UNIPHIER_SD_CAP_64BIT 
> },
> -   { .compatible = "renesas,sdhi-r8a7796", .data = UNIPHIER_SD_CAP_64BIT 
> },
> -   { .compatible = "renesas,sdhi-r8a77970", .data = 
> UNIPHIER_SD_CAP_64BIT },
> -   { .compatible = "renesas,sdhi-r8a77995", .data = 
> UNIPHIER_SD_CAP_64BIT },
> +   { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_SD_QUIRKS },
> +   { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_SD_QUIRKS },
> +   { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_SD_QUIRKS },
> +   { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_SD_QUIRKS },
> { .compatible = "socionext,uniphier-sdhc", .data = 0 },
> { /* sentinel */ }
>  };
> --

Acked-by: Masahiro Yamada 

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Re: [U-Boot] [RFC PATCH] Allow providing default environment from file

[Lukasz Majewski]

Hi Rasmus,

> On 2018-01-25 10:30, Lukasz Majewski wrote:
> > Hi Rasmus,
> >   
> >> It is sometimes useful to be able to define the entire default
> >> environment in an external file.  
> > 
> > There is already available script for extracting the environment.
> > 
> > Please look into:
> > ./scripts/get_default_envs.sh
> > 
> > Maybe you can reuse it in this patch?  
> 
> I'm sorry, but I don't see what I could use that for. It seems to do
> the opposite of what I want, 

Sorry. I have had misunderstood the patch description.

> namely extract the default environment
> and store it in a plain-text file. I want to provide a plain-text
> file to define the default environment.

Ok. Then your patch seems perfectly valid.

> 
> It's quite likely that that script can be useful for generating a
> sketch for the external file (i.e., build a U-boot as "usual" with
> default environment built from various config options etc. etc., then
> hand-edit that file to remove redundant stuff and add the things one
> needs). The thing is, having the default environment in an external
> file makes it much easier to put it under version control than having
> to maintain a branch inside the U-boot repo just to tweak
> CONFIG_EXTRA_ENV_SETTINGS.
> 
> Rasmus



Best regards,

Lukasz Majewski

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Re: [U-Boot] [PATCH 4/7] mmc: uniphier-sd: Handle Renesas div-by-1

[Masahiro Yamada]

2018-01-17 2:17 GMT+09:00 Marek Vasut :
> On the Renesas version of the IP, the /1 divider is realized by
> setting the clock register [7:0] to 0xff instead of setting bit
> 10 of the register. Check the quirk and handle accordingly.
>
> Signed-off-by: Marek Vasut 
> Cc: Jaehoon Chung 
> Cc: Masahiro Yamada 
> ---
>  drivers/mmc/uniphier-sd.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
> index 2f7ec680a3..d828535b11 100644
> --- a/drivers/mmc/uniphier-sd.c
> +++ b/drivers/mmc/uniphier-sd.c
> @@ -75,6 +75,7 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define   UNIPHIER_SD_CLKCTL_DIV4  BIT(0)  /* SDCLK = CLK / 4 */
>  #define   UNIPHIER_SD_CLKCTL_DIV2  0   /* SDCLK = CLK / 2 */
>  #define   UNIPHIER_SD_CLKCTL_DIV1  BIT(10) /* SDCLK = CLK */
> +#define   UNIPHIER_SD_CLKCTL_RCAR_DIV1 0xff/* SDCLK = CLK (RCar ver.) */
>  #define   UNIPHIER_SD_CLKCTL_OFFEN BIT(9)  /* stop SDCLK when unused */
>  #define   UNIPHIER_SD_CLKCTL_SCLKENBIT(8)  /* SDCLK output enable */
>  #define UNIPHIER_SD_SIZE   0x04c   /* block size */
> @@ -641,7 +642,8 @@ static void uniphier_sd_set_clk_rate(struct 
> uniphier_sd_priv *priv,
> divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
>
> if (divisor <= 1)
> -   val = UNIPHIER_SD_CLKCTL_DIV1;
> +   val = (priv->caps & UNIPHIER_SD_CAP_RCAR) ?
> + UNIPHIER_SD_CLKCTL_RCAR_DIV1 : UNIPHIER_SD_CLKCTL_DIV1;
> else if (divisor <= 2)
> val = UNIPHIER_SD_CLKCTL_DIV2;
> else if (divisor <= 4)
> --
> 2.15.1


Acked-by: Masahiro Yamada 

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Re: [U-Boot] [PATCH] imx: mx25: Remove SION bit in all pin-mux

[Benoît Thébaudeau]

On 25/01/2018 at 11:17, Michael Nazzareno Trimarchi wrote:
> On Thu, Jan 25, 2018 at 11:02 AM, Benoît Thébaudeau  
> wrote:
>> You said that setting SION only for a UART is enough to trigger your USB 
>> issue.
>> Of course, there is no reason to set SION by default for a UART, but I was
>> thinking about a possible link between UART and USB, as this behavior is very
>> strange. Which USB host port are use using with the problematic pen drive, 
>> and
>> with which PHY (SoC-internal/external, bus)? Have you checked that this port 
>> is
>> properly configured for this PHY and PWR/OC (on/off + polarity) in both 
>> U-Boot
>> and Linux? For instance, if this port is configured to use OC but no OC 
>> signal
> 
> Nothing of above is connected. Pen drive is in the linux thread
> described in the commit
> message. All the usb stack is fully functional with a lot of pen
> drive. OC, PWR are not
> managed on USB/serial ehci port so they are not involved and I can
> check. I have posted
> some patches on linux mailing list to fix minor stuff. Let's say any
> permutation bit on phy
> configuration does not solve the problem. It's not a problem of usb
> suspend etc. I think that
> approch should be:
> 
> - align the pin mux mx25 file to the other architecture. So drop all
> the sion bit expect for the one
> where we know that silicon is buggy
> - apply SION when is needed in the board that are already in uboot
> - send patches on pin mux for board that are in mainline and we can test
> 
> On my side. I will restrict the change on my board to full isolate the
> configuration. Force the reset of SION
> bit anyway in linux if this solve.
> 
> Agree?

Looks good to me.

Benoît
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Re: [U-Boot] [PATCH 5/7] mmc: uniphier-sd: Add Renesas SDR104/HS200 tuning support

[Masahiro Yamada]

2018-01-17 2:17 GMT+09:00 Marek Vasut :
> Add code for PHY tuning required for SDR104/HS200 support on Renesas RCar.
>
> Signed-off-by: Marek Vasut 
> Cc: Jaehoon Chung 
> Cc: Masahiro Yamada 
> ---
>  drivers/mmc/uniphier-sd.c | 290 
> ++
>  1 file changed, 290 insertions(+)
>
> diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
> index d828535b11..2af8244515 100644
> --- a/drivers/mmc/uniphier-sd.c
> +++ b/drivers/mmc/uniphier-sd.c
> @@ -143,6 +143,10 @@ struct uniphier_sd_priv {
>  #endif
>  };
>
> +#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
> +static void uniphier_sd_reset_tuning(struct uniphier_sd_priv *priv);
> +#endif
> +
>  static u64 uniphier_sd_readq(struct uniphier_sd_priv *priv, unsigned int reg)
>  {
> if (priv->caps & UNIPHIER_SD_CAP_64BIT)
> @@ -596,6 +600,7 @@ static int uniphier_sd_set_bus_width(struct 
> uniphier_sd_priv *priv,
> u32 val, tmp;
>
> switch (mmc->bus_width) {
> +   case 0:
> case 1:
> val = UNIPHIER_SD_OPTION_WIDTH_1;
> break;
> @@ -695,6 +700,7 @@ static void uniphier_sd_set_pins(struct udevice *dev)
> regulator_set_value(priv->vqmmc_dev, 180);
> else
> regulator_set_value(priv->vqmmc_dev, 330);
> +   regulator_set_enable(priv->vqmmc_dev, true);
> }
>  #endif
>
> @@ -720,6 +726,11 @@ static int uniphier_sd_set_ios(struct udevice *dev)
> uniphier_sd_set_clk_rate(priv, mmc);
> uniphier_sd_set_pins(dev);
>
> +#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
> +   if (priv->caps & UNIPHIER_SD_CAP_RCAR_UHS)
> +   uniphier_sd_reset_tuning(priv);
> +#endif
> +
> return 0;
>  }
>
> @@ -734,10 +745,284 @@ static int uniphier_sd_get_cd(struct udevice *dev)
>   UNIPHIER_SD_INFO1_CD);
>  }
>
> +/*
> + * Renesas RCar SDR104 / HS200
> + */
> +#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
> +
> +/* SCC registers */
> +#define SH_MOBILE_SDHI_SCC_DTCNTL  0x800
> +#define   SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN  BIT(0)
> +#define   SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT   16
> +#define   SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK0xff
> +#define SH_MOBILE_SDHI_SCC_TAPSET  0x804
> +#define SH_MOBILE_SDHI_SCC_DT2FF   0x808
> +#define SH_MOBILE_SDHI_SCC_CKSEL   0x80c
> +#define   SH_MOBILE_SDHI_SCC_CKSEL_DTSEL   BIT(0)
> +#define SH_MOBILE_SDHI_SCC_RVSCNTL 0x810
> +#define   SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
> +#define SH_MOBILE_SDHI_SCC_RVSREQ  0x814
> +#define   SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
> +#define SH_MOBILE_SDHI_SCC_SMPCMP  0x818
> +#define SH_MOBILE_SDHI_SCC_TMPPORT20x81c
> +
> +#define SH_MOBILE_SDHI_MAX_TAP 3
> +
> +static unsigned int uniphier_sd_init_tuning(struct uniphier_sd_priv *priv)
> +{
> +   u32 reg;
> +
> +   /* Initialize SCC */
> +   uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO1);
> +
> +   reg = uniphier_sd_readl(priv, UNIPHIER_SD_CLKCTL);
> +   reg &= ~UNIPHIER_SD_CLKCTL_SCLKEN;
> +   uniphier_sd_writel(priv, reg, UNIPHIER_SD_CLKCTL);
> +
> +   /* Set sampling clock selection range */
> +   uniphier_sd_writel(priv, 0x8 << 
> SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT,
> +  SH_MOBILE_SDHI_SCC_DTCNTL);
> +
> +   reg = uniphier_sd_readl(priv, SH_MOBILE_SDHI_SCC_DTCNTL);
> +   reg |= SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN;
> +   uniphier_sd_writel(priv, reg, SH_MOBILE_SDHI_SCC_DTCNTL);
> +
> +   reg = uniphier_sd_readl(priv, SH_MOBILE_SDHI_SCC_CKSEL);
> +   reg |= SH_MOBILE_SDHI_SCC_CKSEL_DTSEL;
> +   uniphier_sd_writel(priv, reg, SH_MOBILE_SDHI_SCC_CKSEL);
> +
> +   reg = uniphier_sd_readl(priv, SH_MOBILE_SDHI_SCC_RVSCNTL);
> +   reg &= ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN;
> +   uniphier_sd_writel(priv, reg, SH_MOBILE_SDHI_SCC_RVSCNTL);
> +
> +   uniphier_sd_writel(priv, 0x300 /* scc_tappos */,
> +  SH_MOBILE_SDHI_SCC_DT2FF);
> +
> +   reg = uniphier_sd_readl(priv, UNIPHIER_SD_CLKCTL);
> +   reg |= UNIPHIER_SD_CLKCTL_SCLKEN;
> +   uniphier_sd_writel(priv, reg, UNIPHIER_SD_CLKCTL);
> +
> +   /* Read TAPNUM */
> +   return (uniphier_sd_readl(priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
> +   SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
> +   SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
> +}
> +
> +static void uniphier_sd_reset_tuning(struct uniphier_sd_priv *priv)
> +{
> +   u32 reg;
> +
> +   /* Reset SCC */
> +   reg = uniphier_sd_readl(priv, UNIPHIER_SD_CLKCTL);
> +   reg &= ~UNIPHIER_SD_CLKCTL_SCLKEN;
> +   uniphier_sd_writel(priv, reg, UNIPHIER_SD_CLKCTL);
> +
> +   reg = uniphier_sd_readl(priv, SH_MOBILE_SDHI_SCC_CKSEL);
> +   r

Re: [U-Boot] [PATCH 6/7] mmc: uniphier-sd: Handle DMA completion flag differences

[Masahiro Yamada]

2018-01-17 2:17 GMT+09:00 Marek Vasut :
> The DMA READ completion flag position differs on Socionext and Renesas
> SoCs. It is bit 20 on Socionext SoCs and using bit 17 is a hardware bug
> and forbidden. It is bit 17 on Renesas SoCs and bit 20 does not work on
> them.
>
> Signed-off-by: Marek Vasut 
> Cc: Jaehoon Chung 
> Cc: Masahiro Yamada 
> ---

Acked-by: Masahiro Yamada 

-- 
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Masahiro Yamada
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Re: [U-Boot] [PATCH 7/7] mmc: uniphier-sd: Always check controller version

[Masahiro Yamada]

2018-01-17 2:17 GMT+09:00 Marek Vasut :
> Handle the controller version even if quirks are set. The controller in
> Renesas Gen3 SoCs does provide the version register, which indicates a
> controller v10 and the controller does support internal DMA and /1024
> divider.
>
> Signed-off-by: Marek Vasut 
> Cc: Jaehoon Chung 
> Cc: Masahiro Yamada 
> ---

Acked-by: Masahiro Yamada 
-- 
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[U-Boot] [PATCH v2 02/24] mmc: omap_hsmmc: cleanup omap_hsmmc_set_ios

[Jean-Jacques Hiblot]

From: Kishon Vijay Abraham I 

No functional change. Move bus width configuration setting to a
separate function and invoke it only if there is a change in the
bus width.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Jean-Jacques Hiblot 
---

 drivers/mmc/omap_hsmmc.c | 29 -
 1 file changed, 20 insertions(+), 9 deletions(-)

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index f5917b0..f02a7a5e 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -62,6 +62,7 @@ struct omap_hsmmc_data {
 #if !CONFIG_IS_ENABLED(DM_MMC)
struct mmc_config cfg;
 #endif
+   uint bus_width;
uint clock;
 #ifdef OMAP_HSMMC_USE_GPIO
 #if CONFIG_IS_ENABLED(DM_MMC)
@@ -812,17 +813,9 @@ static void omap_hsmmc_set_clock(struct mmc *mmc)
omap_hsmmc_start_clock(mmc_base);
 }
 
-#if !CONFIG_IS_ENABLED(DM_MMC)
-static int omap_hsmmc_set_ios(struct mmc *mmc)
+static void omap_hsmmc_set_bus_width(struct mmc *mmc)
 {
struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
-#else
-static int omap_hsmmc_set_ios(struct udevice *dev)
-{
-   struct omap_hsmmc_data *priv = dev_get_priv(dev);
-   struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
-   struct mmc *mmc = upriv->mmc;
-#endif
struct hsmmc *mmc_base;
 
mmc_base = priv->base_addr;
@@ -849,6 +842,24 @@ static int omap_hsmmc_set_ios(struct udevice *dev)
break;
}
 
+   priv->bus_width = mmc->bus_width;
+}
+
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static int omap_hsmmc_set_ios(struct mmc *mmc)
+{
+   struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+#else
+static int omap_hsmmc_set_ios(struct udevice *dev)
+{
+   struct omap_hsmmc_data *priv = dev_get_priv(dev);
+   struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+   struct mmc *mmc = upriv->mmc;
+#endif
+
+   if (priv->bus_width != mmc->bus_width)
+   omap_hsmmc_set_bus_width(mmc);
+
if (priv->clock != mmc->clock)
omap_hsmmc_set_clock(mmc);
 
-- 
1.9.1

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[U-Boot] [PATCH v2 00/24] omap_hsmmc: Add support for HS200 and UHS modes

[Jean-Jacques Hiblot]

This series adds the missing bits to enable the UHS and HS200 modes
for the TI platforms.

Enabling support for high speed modes on omap5 requires implementing:
 * io signal voltage selection
 * tuning support
 * pin configuration (IO delays)

The few last patches enable the high speed modes for the DRA7 platforms and
also take care of disabling those modes in the dts for the platforms that
cannot support either the UHS or the HS200 because the voltage regulators
on board would not allow using those modes (not a SOC limitation).

With this in place we observe significant improvements in the performances:
on a DRA72 evm:
eMMC HS200: 124 MB/s
eMMC DDR52: 78 MB/s
sd   SDR104: 71 MB/s
sd   SDR50: 44 MB/s
For the record, the original performances were:
SD High speed: 18 MB/s
MMC High speed: 18 MB/s

This series has been tested on:
* DRA71-evm
* DRA72-evm
* DRA7x-evm
* DRA76-evm
* AM57x-evm
* Beaglebone Black (dt and non-dt)

changes since v1:
 - rebased on top of u-boot/master
 - enable the H200 and UHS support in the defconfigs of the DRA7 platforms



Jean-Jacques Hiblot (9):
  mmc: omap_hsmmc: Reduce the max timeout for reset controller fsm
  mmc: omap_hsmmc: allow the simple HS modes to use the default pinctrl
  mmc: omap_hsmmc: update mmc->clock with the actual bus speed
  mmc: omap_hsmmc: implement send_init_stream callback
  mmc: omap_hsmmc: add signal voltage selection support
  ARM: dts: dra7: Add supported MMC/SD modes in MMC dt nodes
  dts: am57xx-beagle-x15: disable UHS and HS200 support
  dts: am57xx-idk: disable HS200 support
  configs: dra7xx_evm/dra7xx_hs_evm: Enable MMC HS200 and SD UHS support

Kishon Vijay Abraham I (15):
  mmc: omap_hsmmc: cleanup clock configuration
  mmc: omap_hsmmc: cleanup omap_hsmmc_set_ios
  mmc: omap_hsmmc: add support to set default io voltage
  mmc: omap_hsmmc: set MMC mode in the UHSMS bit field
  mmc: omap_hsmmc: Enable DDR mode support
  mmc: omap_hsmmc: Add tuning support
  mmc: omap_hsmmc: Workaround for errata id i802
  mmc: omap_hsmmc: use mmc_of_parse to populate mmc_config
  ARM: OMAP5/DRA7: Enable iodelay recalibration to be done from uboot
  mmc: omap_hsmmc: Add support to set IODELAY values
  mmc: omap_hsmmc: Add support to get pinctrl values and max frequency
for different hw revisions
  mmc: omap_hsmmc: allow mmc clock to be gated
  ARM: OMAP5: set mmc clock frequency to 192MHz
  ARM: dts: DRA7: use new dra7-specific compatible string
  ARM: DRA7x/AM57x: Add MMC/SD fixups for rev1.0 and rev 1.1

 arch/arm/dts/am57xx-beagle-x15.dts   |   6 +
 arch/arm/dts/am57xx-idk-common.dtsi  |   2 +
 arch/arm/dts/dra7.dtsi   |  22 +-
 arch/arm/include/asm/arch-omap5/clock.h  |   2 +-
 arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h |   3 +
 arch/arm/include/asm/arch-omap5/sys_proto.h  |   7 +
 arch/arm/include/asm/omap_mmc.h  |  59 +-
 arch/arm/mach-omap2/omap5/dra7xx_iodelay.c   |  30 +
 arch/arm/mach-omap2/omap5/hw_data.c  |  10 +-
 board/ti/am57xx/board.c  |  30 +
 board/ti/dra7xx/evm.c|  29 +
 configs/dra7xx_evm_defconfig |   3 +
 configs/dra7xx_hs_evm_defconfig  |   3 +
 drivers/mmc/omap_hsmmc.c | 948 +--
 include/configs/am57xx_evm.h |   2 -
 include/configs/dra7xx_evm.h |   2 -
 16 files changed, 1085 insertions(+), 73 deletions(-)

-- 
1.9.1

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[U-Boot] [PATCH v2 01/24] mmc: omap_hsmmc: cleanup clock configuration

[Jean-Jacques Hiblot]

From: Kishon Vijay Abraham I 

Add a separate function for starting the clock, stopping the clock and
setting the clock. Starting the clock and stopping the clock can
be used irrespective of setting the clock (For example during iodelay
recalibration).
Also set the clock only if there is a change in frequency.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Jean-Jacques Hiblot 
---

 arch/arm/include/asm/omap_mmc.h |  2 ++
 drivers/mmc/omap_hsmmc.c| 74 -
 2 files changed, 52 insertions(+), 24 deletions(-)

diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index bf9de9b..102aec2 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -172,6 +172,8 @@ struct omap_hsmmc_plat {
 #define CLK_400KHZ 1
 #define CLK_MISC   2
 
+#define CLKD_MAX   0x3FF   /* max clock divisor: 1023 */
+
 #define RSP_TYPE_NONE  (RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
 #define MMC_CMD0   (INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
 
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index b12d6d9..f5917b0 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -62,6 +62,7 @@ struct omap_hsmmc_data {
 #if !CONFIG_IS_ENABLED(DM_MMC)
struct mmc_config cfg;
 #endif
+   uint clock;
 #ifdef OMAP_HSMMC_USE_GPIO
 #if CONFIG_IS_ENABLED(DM_MMC)
struct gpio_desc cd_gpio;   /* Change Detect GPIO */
@@ -114,6 +115,8 @@ struct omap_hsmmc_adma_desc {
 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
unsigned int siz);
+static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
+static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 
 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 {
@@ -764,6 +767,51 @@ static int mmc_write_data(struct hsmmc *mmc_base, const 
char *buf,
return 0;
 }
 
+static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
+{
+   writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
+}
+
+static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
+{
+   writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
+}
+
+static void omap_hsmmc_set_clock(struct mmc *mmc)
+{
+   struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+   struct hsmmc *mmc_base;
+   unsigned int dsor = 0;
+   ulong start;
+
+   mmc_base = priv->base_addr;
+   omap_hsmmc_stop_clock(mmc_base);
+
+   /* TODO: Is setting DTO required here? */
+   mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
+   (ICE_STOP | DTO_15THDTO));
+
+   if (mmc->clock != 0) {
+   dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 100, mmc->clock);
+   if (dsor > CLKD_MAX)
+   dsor = CLKD_MAX;
+   }
+
+   mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
+   (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
+
+   start = get_timer(0);
+   while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
+   if (get_timer(0) - start > MAX_RETRY_MS) {
+   printf("%s: timedout waiting for ics!\n", __func__);
+   return;
+   }
+   }
+
+   priv->clock = mmc->clock;
+   omap_hsmmc_start_clock(mmc_base);
+}
+
 #if !CONFIG_IS_ENABLED(DM_MMC)
 static int omap_hsmmc_set_ios(struct mmc *mmc)
 {
@@ -776,8 +824,6 @@ static int omap_hsmmc_set_ios(struct udevice *dev)
struct mmc *mmc = upriv->mmc;
 #endif
struct hsmmc *mmc_base;
-   unsigned int dsor = 0;
-   ulong start;
 
mmc_base = priv->base_addr;
/* configue bus width */
@@ -803,28 +849,8 @@ static int omap_hsmmc_set_ios(struct udevice *dev)
break;
}
 
-   /* configure clock with 96Mhz system clock.
-*/
-   if (mmc->clock != 0) {
-   dsor = (MMC_CLOCK_REFERENCE * 100 / mmc->clock);
-   if ((MMC_CLOCK_REFERENCE * 100) / dsor > mmc->clock)
-   dsor++;
-   }
-
-   mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
-   (ICE_STOP | DTO_15THDTO));
-
-   mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
-   (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
-
-   start = get_timer(0);
-   while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
-   if (get_timer(0) - start > MAX_RETRY_MS) {
-   printf("%s: timedout waiting for ics!\n", __func__);
-   return -ETIMEDOUT;
-   }
-   }
-   writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
+   if (priv->clock != mmc->clock)
+   omap_hsmmc_set_clock(mmc);
 

[U-Boot] [PATCH v2 05/24] mmc: omap_hsmmc: Enable DDR mode support

[Jean-Jacques Hiblot]

From: Kishon Vijay Abraham I 

In order to enable DDR mode, Dual Data Rate mode bit has to be set in
MMCHS_CON register. Set it here.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Jean-Jacques Hiblot 
---

 arch/arm/include/asm/omap_mmc.h | 1 +
 drivers/mmc/omap_hsmmc.c| 5 +
 2 files changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 3f94f2e..341a2e2 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -89,6 +89,7 @@ struct omap_hsmmc_plat {
 #define WPP_ACTIVEHIGH (0x0 << 8)
 #define RESERVED_MASK  (0x3 << 9)
 #define CTPL_MMC_SD(0x0 << 11)
+#define DDR(0x1 << 19)
 #define DMA_MASTER (0x1 << 20)
 #define BLEN_512BYTESLEN   (0x200 << 0)
 #define NBLK_STPCNT(0x0 << 16)
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index a65005f..5f5fd90 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -271,6 +271,11 @@ static void omap_hsmmc_set_timing(struct mmc *mmc)
val &= ~AC12_UHSMC_MASK;
priv->mode = mmc->selected_mode;
 
+   if (mmc_is_mode_ddr(priv->mode))
+   writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
+   else
+   writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
+
switch (priv->mode) {
case MMC_HS_200:
case UHS_SDR104:
-- 
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[U-Boot] [PATCH v2 03/24] mmc: omap_hsmmc: add support to set default io voltage

[Jean-Jacques Hiblot]

From: Kishon Vijay Abraham I 

"ti,dual-volt" is used in linux kernel to set the voltage capabilities.
For host controller dt nodes that doesn't have "ti,dual-volt",
it's assumed 1.8v is the io voltage. This is not always true (like in
the case of beagle-x15 where the io lines are connected to 3.3v).
Hence if "no-1-8-v" property is set, io voltage will be set to 3v.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Jean-Jacques Hiblot 
---

 arch/arm/include/asm/omap_mmc.h | 12 ++--
 drivers/mmc/omap_hsmmc.c| 67 +
 2 files changed, 77 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 102aec2..c4d326d 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -65,6 +65,7 @@ struct omap_hsmmc_plat {
struct hsmmc *base_addr;
struct mmc mmc;
bool cd_inverted;
+   u32 controller_flags;
 };
 
 /*
@@ -124,8 +125,10 @@ struct omap_hsmmc_plat {
 #define DTW_8_BITMODE   (0x1 << 5) /* CON[DW8]*/
 #define SDBP_PWROFF(0x0 << 8)
 #define SDBP_PWRON (0x1 << 8)
+#define SDVS_MASK  (0x7 << 9)
 #define SDVS_1V8   (0x5 << 9)
 #define SDVS_3V0   (0x6 << 9)
+#define SDVS_3V3   (0x7 << 9)
 #define DMA_SELECT (0x2 << 3)
 #define ICE_MASK   (0x1 << 0)
 #define ICE_STOP   (0x0 << 0)
@@ -159,8 +162,13 @@ struct omap_hsmmc_plat {
 #define IE_CERR(0x01 << 28)
 #define IE_BADA(0x01 << 29)
 
-#define VS30_3V0SUP(1 << 25)
-#define VS18_1V8SUP(1 << 26)
+#define VS33_3V3SUPBIT(24)
+#define VS30_3V0SUPBIT(25)
+#define VS18_1V8SUPBIT(26)
+
+#define IOV_3V3330
+#define IOV_3V0300
+#define IOV_1V8180
 
 /* Driver definitions */
 #define MMCSD_SECTOR_SIZE  512
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index f02a7a5e..a6a0df6 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -74,6 +74,9 @@ struct omap_hsmmc_data {
int wp_gpio;
 #endif
 #endif
+#if CONFIG_IS_ENABLED(DM_MMC)
+   uint iov;
+#endif
u8 controller_flags;
 #ifndef CONFIG_OMAP34XX
struct omap_hsmmc_adma_desc *adma_desc_table;
@@ -111,6 +114,8 @@ struct omap_hsmmc_adma_desc {
  * that the bandwidth is always above 3MB/s).
  */
 #define DMA_TIMEOUT_PER_MB 333
+#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT  BIT(0)
+#define OMAP_HSMMC_NO_1_8_VBIT(1)
 #define OMAP_HSMMC_USE_ADMABIT(2)
 
 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
@@ -252,6 +257,58 @@ void mmc_init_stream(struct hsmmc *mmc_base)
writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 }
 
+#if CONFIG_IS_ENABLED(DM_MMC)
+static void omap_hsmmc_conf_bus_power(struct mmc *mmc)
+{
+   struct hsmmc *mmc_base;
+   struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+   u32 val;
+
+   mmc_base = priv->base_addr;
+
+   val = readl(&mmc_base->hctl) & ~SDVS_MASK;
+
+   switch (priv->iov) {
+   case IOV_3V3:
+   val |= SDVS_3V3;
+   break;
+   case IOV_3V0:
+   val |= SDVS_3V0;
+   break;
+   case IOV_1V8:
+   val |= SDVS_1V8;
+   break;
+   }
+
+   writel(val, &mmc_base->hctl);
+}
+
+static void omap_hsmmc_set_capabilities(struct mmc *mmc)
+{
+   struct hsmmc *mmc_base;
+   struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+   u32 val;
+
+   mmc_base = priv->base_addr;
+   val = readl(&mmc_base->capa);
+
+   if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
+   val |= (VS30_3V0SUP | VS18_1V8SUP);
+   priv->iov = IOV_3V0;
+   } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
+   val |= VS30_3V0SUP;
+   val &= ~VS18_1V8SUP;
+   priv->iov = IOV_3V0;
+   } else {
+   val |= VS18_1V8SUP;
+   val &= ~VS30_3V0SUP;
+   priv->iov = IOV_1V8;
+   }
+
+   writel(val, &mmc_base->capa);
+}
+#endif
+
 static int omap_hsmmc_init_setup(struct mmc *mmc)
 {
struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
@@ -286,9 +343,15 @@ static int omap_hsmmc_init_setup(struct mmc *mmc)
if (reg_val & MADMA_EN)
priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 #endif
+
+#if CONFIG_IS_ENABLED(DM_MMC)
+   omap_hsmmc_set_capabilities(mmc);
+   omap_hsmmc_conf_bus_power(mmc);
+#else
writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS

[U-Boot] [PATCH v2 08/24] mmc: omap_hsmmc: Reduce the max timeout for reset controller fsm

[Jean-Jacques Hiblot]

From OMAP3 SoCs (OMAP3, OMAP4, OMAP5, AM572x, AM571x), the DAT/CMD lines
reset procedure section in TRM suggests to first poll the SRD/SRC bit
until it is set to 0x1. But looks like that bit is never set to 1 and there
is an observable delay of 1sec everytime the driver tries to reset DAT/CMD.
(The same is observed in linux kernel).

Reduce the time the driver waits for the controller to set the SRC/SRD bits
to 1 so that there is no observable delay.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Jean-Jacques Hiblot 
---

 drivers/mmc/omap_hsmmc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 3cfd062..df3f14c 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -108,6 +108,7 @@ struct omap_hsmmc_adma_desc {
 
 /* If we fail after 1 second wait, something is really bad */
 #define MAX_RETRY_MS   1000
+#define MMC_TIMEOUT_MS 20
 
 /* DMA transfers can take a long time if a lot a data is transferred.
  * The timeout must take in account the amount of data. Let's assume
@@ -598,7 +599,7 @@ static void mmc_reset_controller_fsm(struct hsmmc 
*mmc_base, u32 bit)
if (!(readl(&mmc_base->sysctl) & bit)) {
start = get_timer(0);
while (!(readl(&mmc_base->sysctl) & bit)) {
-   if (get_timer(0) - start > MAX_RETRY_MS)
+   if (get_timer(0) - start > MMC_TIMEOUT_MS)
return;
}
}
-- 
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[U-Boot] [PATCH v2 11/24] mmc: omap_hsmmc: Add support to set IODELAY values

[Jean-Jacques Hiblot]

From: Kishon Vijay Abraham I 

The data manual of J6/J6 Eco recommends to set different IODELAY values
depending on the mode in which the MMC/SD is enumerated in order to
ensure IO timings are met.

Add support to parse mux values and iodelay values from device tree
and set these depending on the enumerated MMC mode.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Jean-Jacques Hiblot 
---

 drivers/mmc/omap_hsmmc.c | 372 +++
 1 file changed, 372 insertions(+)

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 46c3a04..3cb3fcd 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -34,6 +34,10 @@
 #endif
 #include 
 #include 
+#ifdef CONFIG_OMAP54XX
+#include 
+#include 
+#endif
 #if !defined(CONFIG_SOC_KEYSTONE)
 #include 
 #include 
@@ -57,6 +61,15 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SYSCTL_SRC (1 << 25)
 #define SYSCTL_SRD (1 << 26)
 
+#ifdef CONFIG_IODELAY_RECALIBRATION
+struct omap_hsmmc_pinctrl_state {
+   struct pad_conf_entry *padconf;
+   int npads;
+   struct iodelay_cfg_entry *iodelay;
+   int niodelays;
+};
+#endif
+
 struct omap_hsmmc_data {
struct hsmmc *base_addr;
 #if !CONFIG_IS_ENABLED(DM_MMC)
@@ -83,6 +96,21 @@ struct omap_hsmmc_data {
struct omap_hsmmc_adma_desc *adma_desc_table;
uint desc_slot;
 #endif
+#ifdef CONFIG_IODELAY_RECALIBRATION
+   struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
+   struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
+   struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
+   struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
+   struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
+   struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
+   struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
+   struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
+   struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
+#endif
+};
+
+struct omap_mmc_of_data {
+   u8 controller_flags;
 };
 
 #ifndef CONFIG_OMAP34XX
@@ -119,6 +147,7 @@ struct omap_hsmmc_adma_desc {
 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT  BIT(0)
 #define OMAP_HSMMC_NO_1_8_VBIT(1)
 #define OMAP_HSMMC_USE_ADMABIT(2)
+#define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)
 
 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
@@ -261,6 +290,56 @@ void mmc_init_stream(struct hsmmc *mmc_base)
 }
 
 #if CONFIG_IS_ENABLED(DM_MMC)
+#ifdef CONFIG_IODELAY_RECALIBRATION
+static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
+{
+   struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+   struct omap_hsmmc_pinctrl_state *pinctrl_state;
+
+   switch (priv->mode) {
+   case MMC_HS_200:
+   pinctrl_state = priv->hs200_1_8v_pinctrl_state;
+   break;
+   case UHS_SDR104:
+   pinctrl_state = priv->sdr104_pinctrl_state;
+   break;
+   case UHS_SDR50:
+   pinctrl_state = priv->sdr50_pinctrl_state;
+   break;
+   case UHS_DDR50:
+   pinctrl_state = priv->ddr50_pinctrl_state;
+   break;
+   case UHS_SDR25:
+   pinctrl_state = priv->sdr25_pinctrl_state;
+   break;
+   case UHS_SDR12:
+   pinctrl_state = priv->sdr12_pinctrl_state;
+   break;
+   case SD_HS:
+   case MMC_HS:
+   case MMC_HS_52:
+   pinctrl_state = priv->hs_pinctrl_state;
+   break;
+   case MMC_DDR_52:
+   pinctrl_state = priv->ddr_1_8v_pinctrl_state;
+   default:
+   pinctrl_state = priv->default_pinctrl_state;
+   break;
+   }
+
+   if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
+   if (pinctrl_state->iodelay)
+   late_recalibrate_iodelay(pinctrl_state->padconf,
+pinctrl_state->npads,
+pinctrl_state->iodelay,
+pinctrl_state->niodelays);
+   else
+   do_set_mux32((*ctrl)->control_padconf_core_base,
+pinctrl_state->padconf,
+pinctrl_state->npads);
+   }
+}
+#endif
 static void omap_hsmmc_set_timing(struct mmc *mmc)
 {
u32 val;
@@ -269,6 +348,7 @@ static void omap_hsmmc_set_timing(struct mmc *mmc)
 
mmc_base = priv->base_addr;
 
+   omap_hsmmc_stop_clock(mmc_base);
val = readl(&mmc_base->ac12);
val &= ~AC12_UHSMC_MASK;
priv->mode = mmc->selected_mode;
@@ -306,6 +386,11 @@ static void omap_hsmmc_set_timing(struct mmc *mmc)
break;
}
writel(val, &mmc_base->ac12);
+
+#ifdef CONFIG_IODELAY_RECALIBRATIO

[U-Boot] [PATCH v2 06/24] mmc: omap_hsmmc: Add tuning support

[Jean-Jacques Hiblot]

From: Kishon Vijay Abraham I 

HS200/SDR104 requires tuning command to be sent to the card. Use
the mmc_send_tuning library function to send the tuning
command and configure the internal DLL.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Jean-Jacques Hiblot 
---

 arch/arm/include/asm/omap_mmc.h |  21 ++-
 drivers/mmc/omap_hsmmc.c| 122 
 2 files changed, 141 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 341a2e2..0293281 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -39,7 +39,9 @@ struct hsmmc {
unsigned int sysstatus; /* 0x14 */
unsigned char res2[0x14];
unsigned int con;   /* 0x2C */
-   unsigned char res3[0xD4];
+   unsigned int pwcnt; /* 0x30 */
+   unsigned int dll;   /* 0x34 */
+   unsigned char res3[0xcc];
unsigned int blk;   /* 0x104 */
unsigned int arg;   /* 0x108 */
unsigned int cmd;   /* 0x10C */
@@ -56,7 +58,8 @@ struct hsmmc {
unsigned char res4[0x4];
unsigned int ac12;  /* 0x13C */
unsigned int capa;  /* 0x140 */
-   unsigned char res5[0x10];
+   unsigned int capa2; /* 0x144 */
+   unsigned char res5[0xc];
unsigned int admaes;/* 0x154 */
unsigned int admasal;   /* 0x158 */
 };
@@ -173,6 +176,8 @@ struct omap_hsmmc_plat {
 #define IOV_1V8180
 
 #define AC12_ET(1 << 22)
+#define AC12_V1V8_SIGEN(1 << 19)
+#define AC12_SCLK_SEL  (1 << 23)
 #define AC12_UHSMC_MASK(7 << 16)
 #define AC12_UHSMC_DDR50   (4 << 16)
 #define AC12_UHSMC_SDR104  (3 << 16)
@@ -199,6 +204,18 @@ struct omap_hsmmc_plat {
 /* Clock Configurations and Macros */
 #define MMC_CLOCK_REFERENCE96 /* MHz */
 
+/* DLL */
+#define DLL_SWT(1 << 20)
+#define DLL_FORCE_SR_C_SHIFT   13
+#define DLL_FORCE_SR_C_MASK0x7f
+#define DLL_FORCE_VALUE(1 << 12)
+#define DLL_CALIB  (1 << 1)
+
+#define MAX_PHASE_DELAY0x7c
+
+/* CAPA2 */
+#define CAPA2_TSDR50   (1 << 13)
+
 #define mmc_reg_out(addr, mask, val)\
writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 5f5fd90..fb29a08 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -124,6 +124,7 @@ static int mmc_write_data(struct hsmmc *mmc_base, const 
char *buf,
unsigned int siz);
 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
+static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
 
 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 {
@@ -355,6 +356,124 @@ static void omap_hsmmc_set_capabilities(struct mmc *mmc)
 
writel(val, &mmc_base->capa);
 }
+
+#ifdef MMC_SUPPORTS_TUNING
+static void omap_hsmmc_disable_tuning(struct mmc *mmc)
+{
+   struct hsmmc *mmc_base;
+   struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+   u32 val;
+
+   mmc_base = priv->base_addr;
+   val = readl(&mmc_base->ac12);
+   val &= ~(AC12_SCLK_SEL);
+   writel(val, &mmc_base->ac12);
+
+   val = readl(&mmc_base->dll);
+   val &= ~(DLL_FORCE_VALUE | DLL_SWT);
+   writel(val, &mmc_base->dll);
+}
+
+static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
+{
+   int i;
+   struct hsmmc *mmc_base;
+   struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+   u32 val;
+
+   mmc_base = priv->base_addr;
+   val = readl(&mmc_base->dll);
+   val |= DLL_FORCE_VALUE;
+   val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
+   val |= (count << DLL_FORCE_SR_C_SHIFT);
+   writel(val, &mmc_base->dll);
+
+   val |= DLL_CALIB;
+   writel(val, &mmc_base->dll);
+   for (i = 0; i < 1000; i++) {
+   if (readl(&mmc_base->dll) & DLL_CALIB)
+   break;
+   }
+   val &= ~DLL_CALIB;
+   writel(val, &mmc_base->dll);
+}
+
+static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
+{
+   struct omap_hsmmc_data *priv = dev_get_priv(dev);
+   struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+   struct mmc *mmc = upriv->mmc;
+   struct hsmmc *mmc_base;
+   u32 val;
+   u8 cur_match, prev_match = 0;
+   int ret;
+   u32 phase_delay = 0;
+   u32 start_window = 0, max_window = 0;
+   u32 length = 0, max_len = 0;
+
+   mmc_base = priv->base_addr;
+   val = readl(&mmc_base->capa2);
+
+   /* clock tuning is not needed for upto 52MHz */
+   if (!((mmc->sele

[U-Boot] [PATCH v2 10/24] ARM: OMAP5/DRA7: Enable iodelay recalibration to be done from uboot

[Jean-Jacques Hiblot]

From: Kishon Vijay Abraham I 

Add a new API to perform iodelay recalibration without isolate
io to be used in uboot.

The data manual of J6/J6 Eco recommends to set different IODELAY values
depending on the mode in which the MMC/SD is enumerated in order to
ensure IO timings are met. The MMC driver can use the new API to
set the IO delay values depending on the MMC mode.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Jean-Jacques Hiblot 
---

 arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h |  3 +++
 arch/arm/mach-omap2/omap5/dra7xx_iodelay.c   | 30 
 include/configs/am57xx_evm.h |  2 --
 include/configs/dra7xx_evm.h |  2 --
 4 files changed, 33 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h 
b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
index c997004..a8780ee 100644
--- a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
+++ b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
@@ -83,6 +83,9 @@
 void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
   struct iodelay_cfg_entry const *iodelay,
   int niodelays);
+void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
+ struct iodelay_cfg_entry const *iodelay,
+ int niodelays);
 int __recalibrate_iodelay_start(void);
 void __recalibrate_iodelay_end(int ret);
 
diff --git a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c 
b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c
index 8798730..a9a9f75 100644
--- a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c
+++ b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c
@@ -272,3 +272,33 @@ err:
__recalibrate_iodelay_end(ret);
 
 }
+
+void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
+ struct iodelay_cfg_entry const *iodelay,
+ int niodelays)
+{
+   int ret = 0;
+
+   /* unlock IODELAY CONFIG registers */
+   writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base +
+  CFG_REG_8_OFFSET);
+
+   ret = calibrate_iodelay((*ctrl)->iodelay_config_base);
+   if (ret)
+   goto err;
+
+   ret = update_delay_mechanism((*ctrl)->iodelay_config_base);
+
+   /* Configure Mux settings */
+   do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
+
+   /* Configure Manual IO timing modes */
+   ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
+   if (ret)
+   goto err;
+
+err:
+   /* lock IODELAY CONFIG registers */
+   writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base +
+  CFG_REG_8_OFFSET);
+}
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index 7546b3f..65465d1 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -15,9 +15,7 @@
 #include 
 #include 
 
-#ifdef CONFIG_SPL_BUILD
 #define CONFIG_IODELAY_RECALIBRATION
-#endif
 
 #define CONFIG_NR_DRAM_BANKS   2
 
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index ff90b6d..975e6fd 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -14,9 +14,7 @@
 
 #include 
 
-#ifdef CONFIG_SPL_BUILD
 #define CONFIG_IODELAY_RECALIBRATION
-#endif
 
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_NR_DRAM_BANKS   2
-- 
1.9.1

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[U-Boot] [PATCH v2 22/24] dts: am57xx-idk: disable HS200 support

[Jean-Jacques Hiblot]

HS200 cannot be supported on mmc2, because the IO lines of mmc2 are
connected to 3.3v.

Signed-off-by: Jean-Jacques Hiblot 
---

 arch/arm/dts/am57xx-idk-common.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/am57xx-idk-common.dtsi 
b/arch/arm/dts/am57xx-idk-common.dtsi
index 97aa8e6..fa5a078 100644
--- a/arch/arm/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/dts/am57xx-idk-common.dtsi
@@ -413,6 +413,8 @@
bus-width = <8>;
ti,non-removable;
max-frequency = <9600>;
+   no-1-8-v;
+   /delete-property/ mmc-hs200-1_8v;
 };
 
 &dcan1 {
-- 
1.9.1

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[U-Boot] [PATCH v2 18/24] ARM: OMAP5: set mmc clock frequency to 192MHz

[Jean-Jacques Hiblot]

From: Kishon Vijay Abraham I 

Now that omap_hsmmc has support for hs200 mode, change the clock
frequency to 192MHz. Also change the REFERENCE CLOCK frequency to
192MHz based on which the internal mmc clock divider is calculated.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Jean-Jacques Hiblot 
---

 arch/arm/include/asm/arch-omap5/clock.h |  2 +-
 arch/arm/include/asm/omap_mmc.h |  4 
 arch/arm/mach-omap2/omap5/hw_data.c | 10 +-
 3 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/arch-omap5/clock.h 
b/arch/arm/include/asm/arch-omap5/clock.h
index ee2e78b..3d718c0 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -135,7 +135,7 @@
 
 /* CM_L3INIT_HSMMCn_CLKCTRL */
 #define HSMMC_CLKCTRL_CLKSEL_MASK  (1 << 24)
-#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK  (1 << 25)
+#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK  (3 << 25)
 
 /* CM_L3INIT_SATA_CLKCTRL */
 #define SATA_CLKCTRL_OPTFCLKEN_MASK(1 << 8)
diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 6871f54..d604b79 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -199,7 +199,11 @@ struct omap_hsmmc_plat {
 #define MMC_CMD0   (INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
 
 /* Clock Configurations and Macros */
+#ifdef CONFIG_OMAP54XX
+#define MMC_CLOCK_REFERENCE192 /* MHz */
+#else
 #define MMC_CLOCK_REFERENCE96 /* MHz */
+#endif
 
 /* DLL */
 #define DLL_SWT(1 << 20)
diff --git a/arch/arm/mach-omap2/omap5/hw_data.c 
b/arch/arm/mach-omap2/omap5/hw_data.c
index bb05e19..7fc3836 100644
--- a/arch/arm/mach-omap2/omap5/hw_data.c
+++ b/arch/arm/mach-omap2/omap5/hw_data.c
@@ -438,17 +438,17 @@ void enable_basic_clocks(void)
setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
GPIO4_CLKCTRL_OPTFCLKEN_MASK);
 
-   /* Enable 96 MHz clock for MMC1 & MMC2 */
+   /* Enable 192 MHz clock for MMC1 & MMC2 */
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
HSMMC_CLKCTRL_CLKSEL_MASK);
 
/* Set the correct clock dividers for mmc */
-   setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
-   HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
-   setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
-   HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+   clrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
+HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+   clrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
+HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
 
/* Select 32KHz clock as the source of GPTIMER1 */
setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
-- 
1.9.1

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[U-Boot] [PATCH v2 07/24] mmc: omap_hsmmc: Workaround for errata id i802

[Jean-Jacques Hiblot]

From: Kishon Vijay Abraham I 

According to errata i802, DCRC error interrupts
(MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure.

The DCRC interrupt, occurs when the last tuning block fails
(the last ratio tested). The delay from CRC check until the
interrupt is asserted is bigger than the delay until assertion
of the tuning end flag. Assertion of tuning end flag is what
masks the interrupts. Because of this race, an erroneous DCRC
interrupt occurs.

The suggested  workaround is to disable DCRC interrupts during
the tuning procedure which is implemented here.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Jean-Jacques Hiblot 
---

 arch/arm/include/asm/omap_mmc.h |  4 
 drivers/mmc/omap_hsmmc.c| 26 ++
 2 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 0293281..0893844 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -219,6 +219,10 @@ struct omap_hsmmc_plat {
 #define mmc_reg_out(addr, mask, val)\
writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 
+#define INT_EN_MASK (IE_BADA | IE_CERR | IE_DEB | IE_DCRC |\
+   IE_DTO | IE_CIE | IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO |\
+   IE_BRR | IE_BWR | IE_TC | IE_CC)
+
 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
int wp_gpio);
 
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index fb29a08..3cfd062 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -476,6 +476,25 @@ tuning_error:
 #endif
 #endif
 
+static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
+{
+   struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+   struct hsmmc *mmc_base = priv->base_addr;
+   u32 irq_mask = INT_EN_MASK;
+
+   /*
+* TODO: Errata i802 indicates only DCRC interrupts can occur during
+* tuning procedure and DCRC should be disabled. But see occurences
+* of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
+* interrupts occur along with BRR, so the data is actually in the
+* buffer. It has to be debugged why these interrutps occur
+*/
+   if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
+   irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
+
+   writel(irq_mask, &mmc_base->ie);
+}
+
 static int omap_hsmmc_init_setup(struct mmc *mmc)
 {
struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
@@ -542,10 +561,7 @@ static int omap_hsmmc_init_setup(struct mmc *mmc)
 
writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 
-   writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
-   IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC |
-   IE_CC, &mmc_base->ie);
-
+   mmc_enable_irq(mmc, NULL);
mmc_init_stream(mmc_base);
 
return 0;
@@ -810,6 +826,8 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct 
mmc_cmd *cmd,
 #endif
}
 
+   mmc_enable_irq(mmc, cmd);
+
writel(cmd->cmdarg, &mmc_base->arg);
udelay(20); /* To fix "No status update" error on eMMC */
writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
-- 
1.9.1

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[U-Boot] [PATCH v2 16/24] mmc: omap_hsmmc: allow mmc clock to be gated

[Jean-Jacques Hiblot]

From: Kishon Vijay Abraham I 

mmc core has defined a new parameter *clk_disable* to gate the clock.
Disable the clock here if *clk_disable* is set.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Jean-Jacques Hiblot 
---

 drivers/mmc/omap_hsmmc.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 5eeccfc..6ef3426 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -1207,6 +1207,7 @@ static int omap_hsmmc_set_ios(struct udevice *dev)
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct mmc *mmc = upriv->mmc;
 #endif
+   struct hsmmc *mmc_base = priv->base_addr;
 
if (priv->bus_width != mmc->bus_width)
omap_hsmmc_set_bus_width(mmc);
@@ -1214,6 +1215,11 @@ static int omap_hsmmc_set_ios(struct udevice *dev)
if (priv->clock != mmc->clock)
omap_hsmmc_set_clock(mmc);
 
+   if (mmc->clk_disable)
+   omap_hsmmc_stop_clock(mmc_base);
+   else
+   omap_hsmmc_start_clock(mmc_base);
+
 #if CONFIG_IS_ENABLED(DM_MMC)
if (priv->mode != mmc->selected_mode)
omap_hsmmc_set_timing(mmc);
-- 
1.9.1

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[U-Boot] [PATCH v2 15/24] mmc: omap_hsmmc: implement send_init_stream callback

[Jean-Jacques Hiblot]

This callback is used to send the 74 clock cycles after power up.

Signed-off-by: Jean-Jacques Hiblot 
---

 drivers/mmc/omap_hsmmc.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 28fac9b..5eeccfc 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -46,6 +46,7 @@
 #include 
 #endif
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -564,6 +565,14 @@ tuning_error:
return ret;
 }
 #endif
+
+static void omap_hsmmc_send_init_stream(struct udevice *dev)
+{
+   struct omap_hsmmc_data *priv = dev_get_priv(dev);
+   struct hsmmc *mmc_base = priv->base_addr;
+
+   mmc_init_stream(mmc_base);
+}
 #endif
 
 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
@@ -652,7 +661,10 @@ static int omap_hsmmc_init_setup(struct mmc *mmc)
writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 
mmc_enable_irq(mmc, NULL);
+
+#if !CONFIG_IS_ENABLED(DM_MMC)
mmc_init_stream(mmc_base);
+#endif
 
return 0;
 }
@@ -1279,6 +1291,7 @@ static const struct dm_mmc_ops omap_hsmmc_ops = {
 #ifdef MMC_SUPPORTS_TUNING
.execute_tuning = omap_hsmmc_execute_tuning,
 #endif
+   .send_init_stream   = omap_hsmmc_send_init_stream,
 };
 #else
 static const struct mmc_ops omap_hsmmc_ops = {
-- 
1.9.1

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[U-Boot] [PATCH v2 20/24] ARM: dts: dra7: Add supported MMC/SD modes in MMC dt nodes

[Jean-Jacques Hiblot]

On DRA7 family SoCs, MMC1 controller supports SDR104,
SDR50, DDR50, SDR25 and SDR12 UHS modes.

MMC2 controller supports HS200 and DDR modes.

MMC3 controller supports SDR12, SDR25 and SDR50 modes.

MMC4 controller supports SDR12 and SDR25 modes.

Add these supported modes in device-tree file.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Jean-Jacques Hiblot 
---

 arch/arm/dts/dra7.dtsi | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index 9061843..0f982d8 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -1067,6 +1067,11 @@
status = "disabled";
pbias-supply = <&pbias_mmc_reg>;
max-frequency = <19200>;
+   sd-uhs-sdr104;
+   sd-uhs-sdr50;
+   sd-uhs-ddr50;
+   sd-uhs-sdr25;
+   sd-uhs-sdr12;
};
 
mmc2: mmc@480b4000 {
@@ -1079,6 +1084,10 @@
dma-names = "tx", "rx";
status = "disabled";
max-frequency = <19200>;
+   sd-uhs-sdr25;
+   sd-uhs-sdr12;
+   mmc-hs200-1_8v;
+   mmc-ddr-1_8v;
};
 
mmc3: mmc@480ad000 {
@@ -1092,6 +1101,9 @@
status = "disabled";
/* Errata i887 limits max-frequency of MMC3 to 64 MHz */
max-frequency = <6400>;
+   sd-uhs-sdr12;
+   sd-uhs-sdr25;
+   sd-uhs-sdr50;
};
 
mmc4: mmc@480d1000 {
@@ -1104,6 +1116,8 @@
dma-names = "tx", "rx";
status = "disabled";
max-frequency = <19200>;
+   sd-uhs-sdr12;
+   sd-uhs-sdr25;
};
 
mmu0_dsp1: mmu@40d01000 {
-- 
1.9.1

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[U-Boot] [PATCH v2 19/24] ARM: dts: DRA7: use new dra7-specific compatible string

[Jean-Jacques Hiblot]

From: Kishon Vijay Abraham I 

Use the new compatible string "ti,dra7-hsmmc" that was specifically
added for dra7 and dra72. This is required since for dra7 and dra72
processors iodelay values has to be set unlike other processors.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Sekhar Nori 
Signed-off-by: Jean-Jacques Hiblot 
---

 arch/arm/dts/dra7.dtsi | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index 02a136a..9061843 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -1056,7 +1056,7 @@
};
 
mmc1: mmc@4809c000 {
-   compatible = "ti,omap4-hsmmc";
+   compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
reg = <0x4809c000 0x400>;
interrupts = ;
ti,hwmods = "mmc1";
@@ -1070,7 +1070,7 @@
};
 
mmc2: mmc@480b4000 {
-   compatible = "ti,omap4-hsmmc";
+   compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
reg = <0x480b4000 0x400>;
interrupts = ;
ti,hwmods = "mmc2";
@@ -1082,7 +1082,7 @@
};
 
mmc3: mmc@480ad000 {
-   compatible = "ti,omap4-hsmmc";
+   compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
reg = <0x480ad000 0x400>;
interrupts = ;
ti,hwmods = "mmc3";
@@ -1095,7 +1095,7 @@
};
 
mmc4: mmc@480d1000 {
-   compatible = "ti,omap4-hsmmc";
+   compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
reg = <0x480d1000 0x400>;
interrupts = ;
ti,hwmods = "mmc4";
-- 
1.9.1

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[U-Boot] [PATCH v2 17/24] mmc: omap_hsmmc: add signal voltage selection support

[Jean-Jacques Hiblot]

I/O data lines of UHS SD card operates at 1.8V when in UHS speed
mode (same is true for eMMC in DDR and HS200 modes). Add support
to switch signal voltage to 1.8V in order to support
UHS cards and eMMC HS200 and DDR modes.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Jean-Jacques Hiblot 
---

 arch/arm/include/asm/omap_mmc.h |  10 ++-
 drivers/mmc/omap_hsmmc.c| 176 +++-
 2 files changed, 160 insertions(+), 26 deletions(-)

diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 3073805..6871f54 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -172,10 +172,6 @@ struct omap_hsmmc_plat {
 #define VS30_3V0SUPBIT(25)
 #define VS18_1V8SUPBIT(26)
 
-#define IOV_3V3330
-#define IOV_3V0300
-#define IOV_1V8180
-
 #define AC12_ET(1 << 22)
 #define AC12_V1V8_SIGEN(1 << 19)
 #define AC12_SCLK_SEL  (1 << 23)
@@ -224,6 +220,12 @@ struct omap_hsmmc_plat {
IE_DTO | IE_CIE | IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO |\
IE_BRR | IE_BWR | IE_TC | IE_CC)
 
+#define CON_CLKEXTFREE BIT(16)
+#define CON_PADEN  BIT(15)
+#define PSTATE_CLEVBIT(24)
+#define PSTATE_DLEV(0xF << 20)
+#define PSTATE_DLEV_DAT0   (0x1 << 20)
+
 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
int wp_gpio);
 
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 6ef3426..6098d02 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -78,6 +78,7 @@ struct omap_hsmmc_data {
 #endif
uint bus_width;
uint clock;
+   ushort last_cmd;
 #ifdef OMAP_HSMMC_USE_GPIO
 #if CONFIG_IS_ENABLED(DM_MMC)
struct gpio_desc cd_gpio;   /* Change Detect GPIO */
@@ -89,7 +90,6 @@ struct omap_hsmmc_data {
 #endif
 #endif
 #if CONFIG_IS_ENABLED(DM_MMC)
-   uint iov;
enum bus_mode mode;
 #endif
u8 controller_flags;
@@ -98,6 +98,8 @@ struct omap_hsmmc_data {
uint desc_slot;
 #endif
const char *hw_rev;
+   struct udevice *pbias_supply;
+   uint signal_voltage;
 #ifdef CONFIG_IODELAY_RECALIBRATION
struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
@@ -254,7 +256,8 @@ static unsigned char mmc_board_init(struct mmc *mmc)
&prcm_base->iclken1_core);
 #endif
 
-#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
+#if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
+   !CONFIG_IS_ENABLED(DM_REGULATOR)
/* PBIAS config needed for MMC1 only */
if (mmc_get_blk_desc(mmc)->devnum == 0)
vmmc_pbias_config(LDO_VOLT_3V0);
@@ -398,32 +401,148 @@ static void omap_hsmmc_set_timing(struct mmc *mmc)
omap_hsmmc_start_clock(mmc_base);
 }
 
-static void omap_hsmmc_conf_bus_power(struct mmc *mmc)
+static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
 {
struct hsmmc *mmc_base;
struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
-   u32 val;
+   u32 hctl, ac12;
 
mmc_base = priv->base_addr;
 
-   val = readl(&mmc_base->hctl) & ~SDVS_MASK;
+   hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
+   ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
 
-   switch (priv->iov) {
-   case IOV_3V3:
-   val |= SDVS_3V3;
-   break;
-   case IOV_3V0:
-   val |= SDVS_3V0;
+   switch (signal_voltage) {
+   case MMC_SIGNAL_VOLTAGE_330:
+   hctl |= SDVS_3V0;
break;
-   case IOV_1V8:
-   val |= SDVS_1V8;
+   case MMC_SIGNAL_VOLTAGE_180:
+   hctl |= SDVS_1V8;
+   ac12 |= AC12_V1V8_SIGEN;
break;
}
 
-   writel(val, &mmc_base->hctl);
+   writel(hctl, &mmc_base->hctl);
+   writel(ac12, &mmc_base->ac12);
 }
 
-static void omap_hsmmc_set_capabilities(struct mmc *mmc)
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout)
+{
+   int ret = -ETIMEDOUT;
+   u32 con;
+   bool dat0_high;
+   bool target_dat0_high = !!state;
+   struct omap_hsmmc_data *priv = dev_get_priv(dev);
+   struct hsmmc *mmc_base = priv->base_addr;
+
+   con = readl(&mmc_base->con);
+   writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
+
+   timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
+   while (timeout--)   {
+   dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
+   if (dat0_high == target_dat0_high) {
+   ret = 0;
+   break;
+   }
+

[U-Boot] [PATCH v2 23/24] ARM: DRA7x/AM57x: Add MMC/SD fixups for rev1.0 and rev 1.1

[Jean-Jacques Hiblot]

From: Kishon Vijay Abraham I 

Since DRA7xx/AM57xx SR1.1 and SR1.0 has errata to limit the frequency of
MMC1 to 96MHz and frequency of MMC2 to 48MHz for AM572x SR1.1, limit the
frequency and disable higher speed modes for those revision.
Also use the recommended IO delays (those tagged with "rev11")

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Jean-Jacques Hiblot 
---

 board/ti/am57xx/board.c | 30 ++
 board/ti/dra7xx/evm.c   | 29 +
 2 files changed, 59 insertions(+)

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 1128784..9c1e2ef 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -30,6 +30,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "../common/board_detect.h"
 #include "mux_data.h"
@@ -815,6 +816,35 @@ int board_mmc_init(bd_t *bis)
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
 }
+
+static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
+   .hw_rev = "rev11",
+   .unsupported_caps = MMC_CAP(MMC_HS_200) |
+   MMC_CAP(UHS_SDR104),
+   .max_freq = 9600,
+};
+
+static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
+   .hw_rev = "rev11",
+   .unsupported_caps = MMC_CAP(MMC_HS_200) |
+   MMC_CAP(UHS_SDR104) |
+   MMC_CAP(UHS_SDR50),
+   .max_freq = 4800,
+};
+
+const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
+{
+   switch (omap_revision()) {
+   case DRA752_ES1_0:
+   case DRA752_ES1_1:
+   if (addr == OMAP_HSMMC1_BASE)
+   return &am57x_es1_1_mmc1_fixups;
+   else
+   return &am57x_es1_1_mmc23_fixups;
+   default:
+   return NULL;
+   }
+}
 #endif
 
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 6ecf971..c62724e 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -866,6 +866,35 @@ void board_mmc_poweron_ldo(uint voltage)
palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
}
 }
+
+static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = {
+   .hw_rev = "rev11",
+   .unsupported_caps = MMC_CAP(MMC_HS_200) |
+   MMC_CAP(UHS_SDR104),
+   .max_freq = 9600,
+};
+
+static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = {
+   .hw_rev = "rev11",
+   .unsupported_caps = MMC_CAP(MMC_HS_200) |
+   MMC_CAP(UHS_SDR104) |
+   MMC_CAP(UHS_SDR50),
+   .max_freq = 4800,
+};
+
+const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
+{
+   switch (omap_revision()) {
+   case DRA752_ES1_0:
+   case DRA752_ES1_1:
+   if (addr == OMAP_HSMMC1_BASE)
+   return &dra7x_es1_1_mmc1_fixups;
+   else
+   return &dra7x_es1_1_mmc23_fixups;
+   default:
+   return NULL;
+   }
+}
 #endif
 
 #ifdef CONFIG_USB_DWC3
-- 
1.9.1

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[U-Boot] [PATCH v2 24/24] configs: dra7xx_evm/dra7xx_hs_evm: Enable MMC HS200 and SD UHS support

[Jean-Jacques Hiblot]

By default UHS and HS200 are not enabled.

Signed-off-by: Jean-Jacques Hiblot 

---

 configs/dra7xx_evm_defconfig| 3 +++
 configs/dra7xx_hs_evm_defconfig | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index b13a27e..e79e6d6 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -49,6 +49,9 @@ CONFIG_DM_GPIO=y
 CONFIG_PCF8575_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 7ccb4f0..bc15fd8 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -51,6 +51,9 @@ CONFIG_DM_GPIO=y
 CONFIG_PCF8575_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
-- 
1.9.1

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[U-Boot] [PATCH v2 04/24] mmc: omap_hsmmc: set MMC mode in the UHSMS bit field

[Jean-Jacques Hiblot]

From: Kishon Vijay Abraham I 

Use the timing parameter set in the MMC core to set the
mode in UHSMS  bit field. This is in preparation for
adding HS200 support in omap hsmmc driver.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Jean-Jacques Hiblot 
---

 arch/arm/include/asm/omap_mmc.h | 12 ++-
 drivers/mmc/omap_hsmmc.c| 47 +
 2 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index c4d326d..3f94f2e 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -53,7 +53,8 @@ struct hsmmc {
unsigned int sysctl;/* 0x12C */
unsigned int stat;  /* 0x130 */
unsigned int ie;/* 0x134 */
-   unsigned char res4[0x8];
+   unsigned char res4[0x4];
+   unsigned int ac12;  /* 0x13C */
unsigned int capa;  /* 0x140 */
unsigned char res5[0x10];
unsigned int admaes;/* 0x154 */
@@ -170,6 +171,15 @@ struct omap_hsmmc_plat {
 #define IOV_3V0300
 #define IOV_1V8180
 
+#define AC12_ET(1 << 22)
+#define AC12_UHSMC_MASK(7 << 16)
+#define AC12_UHSMC_DDR50   (4 << 16)
+#define AC12_UHSMC_SDR104  (3 << 16)
+#define AC12_UHSMC_SDR50   (2 << 16)
+#define AC12_UHSMC_SDR25   (1 << 16)
+#define AC12_UHSMC_SDR12   (0 << 16)
+#define AC12_UHSMC_RES (0x7 << 16)
+
 /* Driver definitions */
 #define MMCSD_SECTOR_SIZE  512
 #define MMC_CARD   0
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index a6a0df6..a65005f 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -76,6 +76,7 @@ struct omap_hsmmc_data {
 #endif
 #if CONFIG_IS_ENABLED(DM_MMC)
uint iov;
+   enum bus_mode mode;
 #endif
u8 controller_flags;
 #ifndef CONFIG_OMAP34XX
@@ -258,6 +259,48 @@ void mmc_init_stream(struct hsmmc *mmc_base)
 }
 
 #if CONFIG_IS_ENABLED(DM_MMC)
+static void omap_hsmmc_set_timing(struct mmc *mmc)
+{
+   u32 val;
+   struct hsmmc *mmc_base;
+   struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
+
+   mmc_base = priv->base_addr;
+
+   val = readl(&mmc_base->ac12);
+   val &= ~AC12_UHSMC_MASK;
+   priv->mode = mmc->selected_mode;
+
+   switch (priv->mode) {
+   case MMC_HS_200:
+   case UHS_SDR104:
+   val |= AC12_UHSMC_SDR104;
+   break;
+   case UHS_SDR50:
+   val |= AC12_UHSMC_SDR50;
+   break;
+   case MMC_DDR_52:
+   case UHS_DDR50:
+   val |= AC12_UHSMC_DDR50;
+   break;
+   case SD_HS:
+   case MMC_HS_52:
+   case UHS_SDR25:
+   val |= AC12_UHSMC_SDR25;
+   break;
+   case MMC_LEGACY:
+   case MMC_HS:
+   case SD_LEGACY:
+   case UHS_SDR12:
+   val |= AC12_UHSMC_SDR12;
+   break;
+   default:
+   val |= AC12_UHSMC_RES;
+   break;
+   }
+   writel(val, &mmc_base->ac12);
+}
+
 static void omap_hsmmc_conf_bus_power(struct mmc *mmc)
 {
struct hsmmc *mmc_base;
@@ -926,6 +969,10 @@ static int omap_hsmmc_set_ios(struct udevice *dev)
if (priv->clock != mmc->clock)
omap_hsmmc_set_clock(mmc);
 
+#if CONFIG_IS_ENABLED(DM_MMC)
+   if (priv->mode != mmc->selected_mode)
+   omap_hsmmc_set_timing(mmc);
+#endif
return 0;
 }
 
-- 
1.9.1

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[U-Boot] [PATCH v2 13/24] mmc: omap_hsmmc: allow the simple HS modes to use the default pinctrl

[Jean-Jacques Hiblot]

The default configuration is usually working fine for the the HS modes.
Don't enforce the presence of a dedicated pinmux for the HS modes.

Signed-off-by: Jean-Jacques Hiblot 
---

 drivers/mmc/omap_hsmmc.c | 23 +--
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index a2d68f7..052162b 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -328,6 +328,9 @@ static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
break;
}
 
+   if (!pinctrl_state)
+   pinctrl_state = priv->default_pinctrl_state;
+
if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
if (pinctrl_state->iodelay)
late_recalibrate_iodelay(pinctrl_state->padconf,
@@ -1589,7 +1592,7 @@ err_pinctrl_state:
return 0;
 }
 
-#define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode)
\
+#define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional)  \
do {\
struct omap_hsmmc_pinctrl_state *s = NULL;  \
char str[20];   \
@@ -1604,7 +1607,7 @@ err_pinctrl_state:
if (!s) \
s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
\
-   if (!s) {   \
+   if (!s && !optional) {  \
debug("%s: no pinctrl for %s\n",\
  mmc->dev->name, #mode);   \
cfg->host_caps &= ~(capmask);   \
@@ -1630,15 +1633,15 @@ static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
 
priv->default_pinctrl_state = default_pinctrl;
 
-   OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104);
-   OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50);
-   OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50);
-   OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25);
-   OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12);
+   OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
+   OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
+   OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
+   OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
+   OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
 
-   OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v);
-   OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v);
-   OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs);
+   OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
+   OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
+   OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
 
return 0;
 }
-- 
1.9.1

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[U-Boot] [PATCH v2 12/24] mmc: omap_hsmmc: Add support to get pinctrl values and max frequency for different hw revisions

[Jean-Jacques Hiblot]

From: Kishon Vijay Abraham I 

AM572x SR1.1 requires different IODelay values to be used than that used
in AM572x SR2.0. These values are populated in device tree. Add
capability in omap_hsmmc driver to extract IOdelay values for different
silicon revision. The maximum frequency is also reduced when using a ES1.1.
To keep the ability to boot both revsions with the same dtb, those values
can be provided by the platform code.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Jean-Jacques Hiblot 
---

 arch/arm/include/asm/arch-omap5/sys_proto.h |  7 
 arch/arm/include/asm/omap_mmc.h |  1 +
 drivers/mmc/omap_hsmmc.c| 58 ++---
 3 files changed, 52 insertions(+), 14 deletions(-)

diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h 
b/arch/arm/include/asm/arch-omap5/sys_proto.h
index a6b3557..d43cd7f 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -35,6 +35,12 @@ struct pad_conf_entry {
u32 val;
 };
 
+struct mmc_platform_fixups {
+   const char *hw_rev;
+   u32 unsupported_caps;
+   u32 max_freq;
+};
+
 struct omap_sysinfo {
char *board_string;
 };
@@ -71,6 +77,7 @@ void force_emif_self_refresh(void);
 void get_ioregs(const struct ctrl_ioregs **regs);
 void srcomp_enable(void);
 void setup_warmreset_time(void);
+const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr);
 
 static inline u32 div_round_up(u32 num, u32 den)
 {
diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 0893844..3073805 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -70,6 +70,7 @@ struct omap_hsmmc_plat {
struct mmc mmc;
bool cd_inverted;
u32 controller_flags;
+   const char *hw_rev;
 };
 
 /*
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 3cb3fcd..a2d68f7 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -96,6 +96,7 @@ struct omap_hsmmc_data {
struct omap_hsmmc_adma_desc *adma_desc_table;
uint desc_slot;
 #endif
+   const char *hw_rev;
 #ifdef CONFIG_IODELAY_RECALIBRATION
struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
@@ -1368,6 +1369,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, 
uint f_max, int cd_gpio,
if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= 
CPU_3XX_ES21))
cfg->b_max = 1;
 #endif
+
mmc = mmc_create(cfg, priv);
if (mmc == NULL)
return -1;
@@ -1587,20 +1589,28 @@ err_pinctrl_state:
return 0;
 }
 
-#define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode)\
-   do {\
-   struct omap_hsmmc_pinctrl_state *s; \
-   if (!(cfg->host_caps & capmask))\
-   break;  \
-   \
-   s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
-   if (!s) {   \
-   debug("%s: no pinctrl for %s\n",\
- mmc->dev->name, #mode);   \
-   cfg->host_caps &= ~(capmask);   \
-   } else {\
-   priv->mode##_pinctrl_state = s; \
-   }   \
+#define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode)
\
+   do {\
+   struct omap_hsmmc_pinctrl_state *s = NULL;  \
+   char str[20];   \
+   if (!(cfg->host_caps & capmask))\
+   break;  \
+   \
+   if (priv->hw_rev) { \
+   sprintf(str, "%s-%s", #mode, priv->hw_rev); \
+   s = omap_hsmmc_get_pinctrl_by_mode(mmc, str);   \
+   }   \
+   \
+   if (!s) \
+   s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
+   \
+   if (!s) {   \
+   debug("%s: no pinctrl for %s\n",\
+ mmc->dev->name, #mode);   \
+  

[U-Boot] [PATCH v2 09/24] mmc: omap_hsmmc: use mmc_of_parse to populate mmc_config

[Jean-Jacques Hiblot]

From: Kishon Vijay Abraham I 

Use the mmc_of_parse library function to populate mmc_config instead of
repeating the same code in host controller driver.

Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Jean-Jacques Hiblot 
---

 drivers/mmc/omap_hsmmc.c | 24 +---
 1 file changed, 5 insertions(+), 19 deletions(-)

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index df3f14c..46c3a04 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -1297,32 +1297,18 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice 
*dev)
struct mmc_config *cfg = &plat->cfg;
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
-   int val;
+   int ret;
 
plat->base_addr = map_physmem(devfdt_get_addr(dev),
  sizeof(struct hsmmc *),
  MAP_NOCACHE);
 
-   cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
-   val = fdtdec_get_int(fdt, node, "bus-width", -1);
-   if (val < 0) {
-   printf("error: bus-width property missing\n");
-   return -ENOENT;
-   }
-
-   switch (val) {
-   case 0x8:
-   cfg->host_caps |= MMC_MODE_8BIT;
-   case 0x4:
-   cfg->host_caps |= MMC_MODE_4BIT;
-   break;
-   default:
-   printf("error: invalid bus-width property\n");
-   return -ENOENT;
-   }
+   ret = mmc_of_parse(dev, cfg);
+   if (ret < 0)
+   return ret;
 
+   cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
cfg->f_min = 40;
-   cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 5200);
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
-- 
1.9.1

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[U-Boot] [PATCH v2 14/24] mmc: omap_hsmmc: update mmc->clock with the actual bus speed

[Jean-Jacques Hiblot]

When the clock is applied, compute the actual value of the clock. It may be
slightly different from the requested value (max freq, divisor threshold)

Signed-off-by: Jean-Jacques Hiblot 
---

 drivers/mmc/omap_hsmmc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 052162b..28fac9b 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -1147,7 +1147,8 @@ static void omap_hsmmc_set_clock(struct mmc *mmc)
}
}
 
-   priv->clock = mmc->clock;
+   priv->clock = MMC_CLOCK_REFERENCE * 100 / dsor;
+   mmc->clock = priv->clock;
omap_hsmmc_start_clock(mmc_base);
 }
 
-- 
1.9.1

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[U-Boot] [PATCH v2 21/24] dts: am57xx-beagle-x15: disable UHS and HS200 support

[Jean-Jacques Hiblot]

The UHS modes are not supported in beagle-x15 because it's not possible to
switch the IO lines supply voltage to 1.8v.
Also HS200 cannot be supported on mmc2, because the IO lines of mmc2 are
connected to 3.3v.

Signed-off-by: Jean-Jacques Hiblot 
---

 arch/arm/dts/am57xx-beagle-x15.dts | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/dts/am57xx-beagle-x15.dts 
b/arch/arm/dts/am57xx-beagle-x15.dts
index d668910..8d9bdf1 100644
--- a/arch/arm/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/dts/am57xx-beagle-x15.dts
@@ -25,6 +25,11 @@
pinctrl-1 = <&mmc1_pins_hs>;
 
vmmc-supply = <&ldo1_reg>;
+   /delete-property/ sd-uhs-sdr104;
+   /delete-property/ sd-uhs-sdr50;
+   /delete-property/ sd-uhs-ddr50;
+   /delete-property/ sd-uhs-sdr25;
+   /delete-property/ sd-uhs-sdr12;
 };
 
 &mmc2 {
@@ -32,6 +37,7 @@
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 
&mmc2_iodelay_ddr_3_3v_rev11_conf>;
+   /delete-property/ mmc-hs200-1_8v;
 };
 
 /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
-- 
1.9.1

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[U-Boot] [PATCH v3 13/15] MAINTAINERS: Take over BCM2835 maintainership

[Alexander Graf]

It seems as if I have more interest in BCM2835 support than most others,
so I'll bite the bullet and declare myself maintainer. It'd be a shame
to leave that platform orphaned.

Signed-off-by: Alexander Graf 
---
 MAINTAINERS | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 728d38aebf..19f645d825 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -92,8 +92,8 @@ T:git git://git.denx.de/u-boot-atmel.git
 F: arch/arm/mach-at91/
 
 ARM BROADCOM BCM283X
-#M:Stephen Warren 
-S: Orphaned (Since 2017-07)
+M: Alexander Graf 
+S: Maintained
 F: arch/arm/mach-bcm283x/
 F: drivers/gpio/bcm2835_gpio.c
 F: drivers/mmc/bcm2835_sdhci.c
-- 
2.12.3

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[U-Boot] [PATCH v3 10/15] pl011: Convert CONFIG_PL011_SERIAL to Kconfig

[Alexander Graf]

We want to use Kconfig logic to depend on whether pl01x devices
are built in, so let's convert their inclusion selection to Kconfig.

This round goes to pl011.

Signed-off-by: Alexander Graf 
---
 arch/arm/Kconfig  | 19 +++
 drivers/serial/Kconfig|  6 ++
 include/configs/highbank.h|  1 -
 include/configs/mxs.h |  1 -
 include/configs/spear-common.h|  1 -
 include/configs/vexpress_aemv8a.h |  1 -
 include/configs/vexpress_common.h |  1 -
 include/configs/x600.h|  1 -
 scripts/config_whitelist.txt  |  1 -
 9 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 97b8249432..1557e7cfdf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -400,49 +400,58 @@ config TARGET_APX4DEVKIT
bool "Support apx4devkit"
select CPU_ARM926EJS
select SUPPORT_SPL
+   select PL011_SERIAL
 
 config TARGET_XFI3
bool "Support xfi3"
select CPU_ARM926EJS
select SUPPORT_SPL
+   select PL011_SERIAL
 
 config TARGET_M28EVK
bool "Support m28evk"
select CPU_ARM926EJS
select SUPPORT_SPL
+   select PL011_SERIAL
 
 config TARGET_MX23EVK
bool "Support mx23evk"
select CPU_ARM926EJS
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
+   select PL011_SERIAL
 
 config TARGET_MX28EVK
bool "Support mx28evk"
select CPU_ARM926EJS
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
+   select PL011_SERIAL
 
 config TARGET_MX23_OLINUXINO
bool "Support mx23_olinuxino"
select CPU_ARM926EJS
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
+   select PL011_SERIAL
 
 config TARGET_BG0900
bool "Support bg0900"
select CPU_ARM926EJS
select SUPPORT_SPL
+   select PL011_SERIAL
 
 config TARGET_SANSA_FUZE_PLUS
bool "Support sansa_fuze_plus"
select CPU_ARM926EJS
select SUPPORT_SPL
+   select PL011_SERIAL
 
 config TARGET_SC_SPS_1
bool "Support sc_sps_1"
select CPU_ARM926EJS
select SUPPORT_SPL
+   select PL011_SERIAL
 
 config ORION5X
bool "Marvell Orion"
@@ -453,24 +462,28 @@ config TARGET_SPEAR300
select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
imply CMD_SAVES
+   select PL011_SERIAL
 
 config TARGET_SPEAR310
bool "Support spear310"
select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
imply CMD_SAVES
+   select PL011_SERIAL
 
 config TARGET_SPEAR320
bool "Support spear320"
select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
imply CMD_SAVES
+   select PL011_SERIAL
 
 config TARGET_SPEAR600
bool "Support spear600"
select CPU_ARM926EJS
select BOARD_EARLY_INIT_F
imply CMD_SAVES
+   select PL011_SERIAL
 
 config TARGET_STV0991
bool "Support stv0991"
@@ -486,6 +499,7 @@ config TARGET_X600
select BOARD_LATE_INIT
select CPU_ARM926EJS
select SUPPORT_SPL
+   select PL011_SERIAL
 
 config TARGET_IMX31_PHYCORE
bool "Support imx31_phycore_eet"
@@ -541,14 +555,17 @@ config TARGET_VEXPRESS_CA15_TC2
select CPU_V7
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
+   select PL011_SERIAL
 
 config TARGET_VEXPRESS_CA5X2
bool "Support vexpress_ca5x2"
select CPU_V7
+   select PL011_SERIAL
 
 config TARGET_VEXPRESS_CA9X4
bool "Support vexpress_ca9x4"
select CPU_V7
+   select PL011_SERIAL
 
 config TARGET_BCM23550_W1D
bool "Support bcm23550_w1d"
@@ -607,6 +624,7 @@ config ARCH_S5PC1XX
 config ARCH_HIGHBANK
bool "Calxeda Highbank"
select CPU_V7
+   select PL011_SERIAL
 
 config ARCH_INTEGRATOR
bool "ARM Ltd. Integrator family"
@@ -761,6 +779,7 @@ config TARGET_TS4600
bool "Support TS4600"
select CPU_ARM926EJS
select SUPPORT_SPL
+   select PL011_SERIAL
 
 config ARCH_VF610
bool "Freescale Vybrid"
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 2816121dec..99aa817e63 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -453,6 +453,12 @@ config PL010_SERIAL
help
  Select this to enable a UART for platforms using PL010.
 
+config PL011_SERIAL
+   bool "ARM PL011 driver"
+   depends on !DM_SERIAL
+   help
+ Select this to enable a UART for platforms using PL011.
+
 config ROCKCHIP_SERIAL
bool "Rockchip on-chip UART support"
depends on DM_SERIAL && SPL_OF_PLATDATA
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index a5a524008b..726ae8a214 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h
@@ -22,7 +22,6 @@
  */
 #define CONFIG_SYS_MALLOC_LEN  (512 * 1024)
 
-#define CONFIG_PL011_SERIAL
 #define CONFIG_PL011_CLOCK 15000
 #define CONFIG_PL01x_

[U-Boot] [PATCH v3 01/15] serial: Use next serial device if probing fails

[Alexander Graf]

Currently our serial device search chokes on the fact that the serial
probe function could fail. If it does, instead of searching for the next
usable serial device, it just quits.

This patch changes the fallback logic so that even when a serial device
was not probed correctly, we just try the next ones until we find one that
works.

Signed-off-by: Alexander Graf 
Reviewed-by: Simon Glass 

---

v1 -> v2:

  - Make search logic easier to follow
---
 drivers/serial/serial-uclass.c | 25 +++--
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 2e5116f7ce..68ca2d09d1 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -74,6 +74,7 @@ static void serial_find_console_or_panic(void)
 {
const void *blob = gd->fdt_blob;
struct udevice *dev;
+   int ret;
 
if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
uclass_first_device(UCLASS_SERIAL, &dev);
@@ -104,8 +105,8 @@ static void serial_find_console_or_panic(void)
 * from 1!).
 *
 * Failing that, get the device with sequence number 0, or in
-* extremis just the first serial device we can find. But we
-* insist on having a console (even if it is silent).
+* extremis just the first working serial device we can find.
+* But we insist on having a console (even if it is silent).
 */
 #ifdef CONFIG_CONS_INDEX
 #define INDEX (CONFIG_CONS_INDEX - 1)
@@ -113,10 +114,22 @@ static void serial_find_console_or_panic(void)
 #define INDEX 0
 #endif
if (!uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &dev) ||
-   !uclass_get_device(UCLASS_SERIAL, INDEX, &dev) ||
-   (!uclass_first_device(UCLASS_SERIAL, &dev) && dev)) {
-   gd->cur_serial_dev = dev;
-   return;
+   !uclass_get_device(UCLASS_SERIAL, INDEX, &dev)) {
+   if (dev->flags & DM_FLAG_ACTIVATED) {
+   gd->cur_serial_dev = dev;
+   return;
+   }
+   }
+
+   /* Search for any working device */
+   for (ret = uclass_first_device_check(UCLASS_SERIAL, &dev);
+dev;
+ret = uclass_next_device_check(&dev)) {
+   if (!ret) {
+   /* Device did succeed probing */
+   gd->cur_serial_dev = dev;
+   return;
+   }
}
 #undef INDEX
}
-- 
2.12.3

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[U-Boot] [PATCH v3 06/15] serial_bcm283x_mu: Always skip init

[Alexander Graf]

The serial initialization doesn't always quite work for me, so let's
always skip it for now. We know that firmware on the RPi initializes
us properly already.

Signed-off-by: Alexander Graf 
---
 drivers/serial/serial_bcm283x_mu.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/serial/serial_bcm283x_mu.c 
b/drivers/serial/serial_bcm283x_mu.c
index 20dc3defcc..c6132b4463 100644
--- a/drivers/serial/serial_bcm283x_mu.c
+++ b/drivers/serial/serial_bcm283x_mu.c
@@ -147,7 +147,12 @@ static int bcm283x_mu_serial_ofdata_to_platdata(struct 
udevice *dev)
 
plat->base = addr;
plat->clock = dev_read_u32_default(dev, "clock", 1);
-   plat->skip_init = dev_read_bool(dev, "skip-init");
+
+   /*
+* TODO: Reinitialization doesn't always work for now, just skip
+*   init always - we know we're already initialized
+*/
+   plat->skip_init = true;
 
return 0;
 }
-- 
2.12.3

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