Re: [U-Boot] [PATCH] Disaligned buffer in print_buffer

[Albert ARIBAUD]

Le 19/08/2010 18:33, Stefano Babic a écrit :
> As I see in the
> discussion, the patch proposed is accepted because
> _attribute__((__aligned__())) is everywhere used in u-boot.
>
> Stefano

'Acceptable' is my bet... Not yet 'accepted' though. :)

Amicalement,
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[U-Boot] u-boot-x86

[sk ong]

Hi,

I notice there is u-boot for x86 architecture in the denx site. I wonder
whether the u-boot-x86 has the legacy BIOS services, such as dispatching
PCI/PCIE device option rom such as video, SATA, etc. Does it have int13,
int15 etc. services for x86 Linux to call during booting phase.

Thanks,
SK
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Re: [U-Boot] [PATCH 1/4] MX51: iomux: Added support for mxc_iomux_set_input()

[Stefano Babic]

David Jander wrote:
> Signed-off-by: David Jander 
> ---

Hi Dave,

>  arch/arm/cpu/armv7/mx51/iomux.c |8 +++-
>  1 files changed, 7 insertions(+), 1 deletions(-)
> 

Probably iut is better you set a more useful comment in your commit.
Instead of "Added support for   mxc_iomux_set_input()", you can explain
which is the new feature you provide. Something to explain you add a
utility for the "daisy chain" pins, to control the input path to a
module when the module can be connected to more as one pin.

The patch is part of a series. However, I can see only the first two
patches. Is there something missing ? I do not see any relation between
these two patches, too.

> +void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
> +{
> + u32 pad_reg = IOMUXSW_INPUT_CTL+(input*4);

Code styling, you should add spaces:

u32 pad_reg = IOMUXSW_INPUT_CTL + (input * 4);

> + writel(config, pad_reg);
> +}

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH 2/4] MX51: Added missing pin definition

[Stefano Babic]

David Jander wrote:
> Signed-off-by: David Jander 
> ---
>  arch/arm/include/asm/arch-mx51/mx51_pins.h |1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-mx51/mx51_pins.h 
> b/arch/arm/include/asm/arch-mx51/mx51_pins.h
> index ca26f41..c443f13 100644
> --- a/arch/arm/include/asm/arch-mx51/mx51_pins.h
> +++ b/arch/arm/include/asm/arch-mx51/mx51_pins.h
> @@ -320,6 +320,7 @@ enum iomux_pins {
>   MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
>   MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
>   MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
> + MX51_PIN_DI1_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x730), /* No MUX 
> register!! */

Line too long.

Best regards,
Stefano Babic

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[U-Boot] [PATCH] Use common function to set GPIOs for MX3 and MX5

[Stefano Babic]

The patch adds support for setting gpios to the
MX51 processor and change name to the corresponding
functions for MX31. In this way, it is possible to get rid
of nasty #ifdef switches related to the processor type.

Signed-off-by: Stefano Babic 
---
 arch/arm/include/asm/arch-mx31/mx31-regs.h |   14 +++-
 arch/arm/include/asm/arch-mx31/mx31.h  |   25 ---
 arch/arm/include/asm/arch-mx51/imx-regs.h  |6 ++
 board/davedenx/qong/qong.c |   29 
 drivers/gpio/Makefile  |2 +-
 drivers/gpio/mx31_gpio.c   |   88 ---
 drivers/gpio/mxc_gpio.c|  107 
 drivers/spi/mxc_spi.c  |9 +--
 include/configs/imx31_phycore.h|2 +-
 include/configs/qong.h |2 +-
 include/mxc_gpio.h |   52 +
 11 files changed, 197 insertions(+), 139 deletions(-)
 delete mode 100644 drivers/gpio/mx31_gpio.c
 create mode 100644 drivers/gpio/mxc_gpio.c
 create mode 100644 include/mxc_gpio.h

diff --git a/arch/arm/include/asm/arch-mx31/mx31-regs.h 
b/arch/arm/include/asm/arch-mx31/mx31-regs.h
index d72585c..f05e743 100644
--- a/arch/arm/include/asm/arch-mx31/mx31-regs.h
+++ b/arch/arm/include/asm/arch-mx31/mx31-regs.h
@@ -57,6 +57,14 @@ struct clock_control_regs {
u32 pdr2;
 };
 
+/* GPIO Registers */
+struct gpio_regs {
+   u32 gpio_dr;
+   u32 gpio_dir;
+   u32 gpio_psr;
+};
+
+
 /* Bit definitions for RCSR register in CCM */
 #define CCM_RCSR_NF16B (1 << 31)
 #define CCM_RCSR_NFMS  (1 << 30)
@@ -153,9 +161,9 @@ struct clock_control_regs {
 /*
  * GPIO
  */
-#define GPIO1_BASE 0x53FCC000
-#define GPIO2_BASE 0x53FD
-#define GPIO3_BASE 0x53FA4000
+#define GPIO1_BASE_ADDR0x53FCC000
+#define GPIO2_BASE_ADDR0x53FD
+#define GPIO3_BASE_ADDR0x53FA4000
 #define GPIO_DR0x  /* data register */
 #define GPIO_GDIR  0x0004  /* direction register */
 #define GPIO_PSR   0x0008  /* pad status register */
diff --git a/arch/arm/include/asm/arch-mx31/mx31.h 
b/arch/arm/include/asm/arch-mx31/mx31.h
index f702d26..5a5aa11 100644
--- a/arch/arm/include/asm/arch-mx31/mx31.h
+++ b/arch/arm/include/asm/arch-mx31/mx31.h
@@ -28,31 +28,6 @@ extern u32 mx31_get_ipg_clk(void);
 #define imx_get_uartclk mx31_get_ipg_clk
 extern void mx31_gpio_mux(unsigned long mode);
 
-enum mx31_gpio_direction {
-   MX31_GPIO_DIRECTION_IN,
-   MX31_GPIO_DIRECTION_OUT,
-};
-
-#ifdef CONFIG_MX31_GPIO
-extern int mx31_gpio_direction(unsigned int gpio,
-  enum mx31_gpio_direction direction);
-extern void mx31_gpio_set(unsigned int gpio, unsigned int value);
-extern int mx31_gpio_get(unsigned int gpio);
-#else
-static inline int mx31_gpio_direction(unsigned int gpio,
- enum mx31_gpio_direction direction)
-{
-   return 1;
-}
-static inline int mx31_gpio_get(unsigned int gpio)
-{
-   return 1;
-}
-static inline void mx31_gpio_set(unsigned int gpio, unsigned int value)
-{
-}
-#endif
-
 void mx31_uart1_hw_init(void);
 void mx31_spi2_hw_init(void);
 
diff --git a/arch/arm/include/asm/arch-mx51/imx-regs.h 
b/arch/arm/include/asm/arch-mx51/imx-regs.h
index 3887d3c..0e3bc2a 100644
--- a/arch/arm/include/asm/arch-mx51/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx51/imx-regs.h
@@ -256,6 +256,12 @@ struct weim {
u32 cswcr2;
 };
 
+/* GPIO Registers */
+struct gpio_regs {
+   u32 gpio_dr;
+   u32 gpio_dir;
+   u32 gpio_psr;
+};
 #endif /* __ASSEMBLER__*/
 
 #endif /*  __ASM_ARCH_MXC_MX51_H__ */
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
index 781333b..59589c2 100644
--- a/board/davedenx/qong/qong.c
+++ b/board/davedenx/qong/qong.c
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "qong_fpga.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -42,9 +43,9 @@ int dram_init (void)
 
 static void qong_fpga_reset(void)
 {
-   mx31_gpio_set(QONG_FPGA_RST_PIN, 0);
+   mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
udelay(30);
-   mx31_gpio_set(QONG_FPGA_RST_PIN, 1);
+   mxc_gpio_set(QONG_FPGA_RST_PIN, 1);
 
udelay(300);
 }
@@ -115,11 +116,11 @@ int board_init (void)
 
/* FPGA reset  Pin */
/* rstn = 0 */
-   mx31_gpio_set(QONG_FPGA_RST_PIN, 0);
-   mx31_gpio_direction(QONG_FPGA_RST_PIN, MX31_GPIO_DIRECTION_OUT);
+   mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
+   mxc_gpio_direction(QONG_FPGA_RST_PIN, MXC_GPIO_DIRECTION_OUT);
 
/* set interrupt pin as input */
-   mx31_gpio_direction(QONG_FPGA_IRQ_PIN, MX31_GPIO_DIRECTION_IN);
+   mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN);
 
 #endif
 
@@ -201,27 +202,27 @@ static void board_nand_setup(void)
qong_fpga_reset();
 
/* Enable NAND flash */
-   mx31_gpi

Re: [U-Boot] [PATCH] mx51evk: Provide a proper reset for the Ethernet PHY

[Stefano Babic]

Fabio Estevam wrote:
> Provide a proper reset for the Ethernet PHY (LAN8700) on the MX51EVK.
> 

Hi Fabio,

> Signed-off-by: Fabio Estevam 
> ---
>  board/freescale/mx51evk/mx51evk.c |4 
>  1 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/board/freescale/mx51evk/mx51evk.c 
> b/board/freescale/mx51evk/mx51evk.c
> index 75d642b..70cce55 100644
> --- a/board/freescale/mx51evk/mx51evk.c
> +++ b/board/freescale/mx51evk/mx51evk.c
> @@ -261,6 +261,10 @@ static void power_init(void)
>  
>   /* Reset the ethernet controller over GPIO */
>   writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
> + udelay(200);
> + reg = readl(GPIO2_BASE_ADDR + 0x0);
> + reg |= 0x4000;  /* Set reset line to high*/
> + writel(reg, GPIO2_BASE_ADDR + 0x0);

I know I am responsible for this usage, because I forget to add some
accessors for the gpio pins - as I see your patch, I have sent a patch
to support it. However, a direct access to registers using offsets is
not allowed in u-boot. If we use some kind of accessors, your code will
be easier to read it. Everything could be changed as (0X4000 --> gpio
46, if I am not wrong):

udelay(200);
mxc_gpio_set(46);

What do you think ?

Best regards,
Stefano

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Re: [U-Boot] [PATCH 1/4] MX51: iomux: Added su pport for mxc_iomux_set_input ()

[David Jander]

Hi Stefano,

On Friday 20 August 2010 10:10:49 am Stefano Babic wrote: 
> Hi Dave,
> 
> >  arch/arm/cpu/armv7/mx51/iomux.c |8 +++-
> >  1 files changed, 7 insertions(+), 1 deletions(-)
> 
> Probably iut is better you set a more useful comment in your commit.
> Instead of "Added support for mxc_iomux_set_input()", you can explain
> which is the new feature you provide. Something to explain you add a
> utility for the "daisy chain" pins, to control the input path to a
> module when the module can be connected to more as one pin.

Hmmm. I thought it was a trivial and obviously missing function to make 
iomux.c complete. Someone just needed to write it. I didn't think it needed 
any more explaining than that, but I'll do it in the next version of the patch 
set (will take a while).

> The patch is part of a series. However, I can see only the first two
> patches. Is there something missing ? I do not see any relation between
> these two patches, too.

I sent 4 patches and received them all on the mailing-list. Are you sure you 
miss two of them?
The first three patches introduce some minimal fixes/additions in order to 
implement the BSP for PRTLVT2 boards (patch 4/4).

> > +void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
> > +{
> > +   u32 pad_reg = IOMUXSW_INPUT_CTL+(input*4);
> 
> Code styling, you should add spaces:
> 
>   u32 pad_reg = IOMUXSW_INPUT_CTL + (input * 4);

Ok.

Best regards,

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Re: [U-Boot] [PATCH 2/4] MX51: Added missing pin definition

[David Jander]

On Friday 20 August 2010 10:12:16 am Stefano Babic wrote:
> David Jander wrote:
> > Signed-off-by: David Jander 
> > ---
> >  arch/arm/include/asm/arch-mx51/mx51_pins.h |1 +
> >  1 files changed, 1 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch-mx51/mx51_pins.h
> > b/arch/arm/include/asm/arch-mx51/mx51_pins.h index ca26f41..c443f13
> > 100644
> > --- a/arch/arm/include/asm/arch-mx51/mx51_pins.h
> > +++ b/arch/arm/include/asm/arch-mx51/mx51_pins.h
> > @@ -320,6 +320,7 @@ enum iomux_pins {
> > MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
> > MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
> > MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
> > +   MX51_PIN_DI1_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x730), /* No MUX
> > register!! */
> 
> Line too long.

Ok, will fix.

Best regards,

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Re: [U-Boot] [PATCH] Use common function to set GPIOs for MX3 and MX5

[David Jander]

On Friday 20 August 2010 10:20:11 am Stefano Babic wrote:
> The patch adds support for setting gpios to the
> MX51 processor and change name to the corresponding
> functions for MX31. In this way, it is possible to get rid
> of nasty #ifdef switches related to the processor type.

Argh! I was just writing the exact same code as in this patch :-(
Thanks a lot anyway.

Best regards,

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Re: [U-Boot] [PATCH 1/4] MX51: iomux: Added support for mxc_iomux_set_input()

[Stefano Babic]

David Jander wrote:
> Hi Stefano,
> 

Hi David,

> Hmmm. I thought it was a trivial and obviously missing function to make 
> iomux.c complete.
> Someone just needed to write it. I didn't think it needed 
> any more explaining than that, but I'll do it in the next version of the 
> patch 
> set (will take a while).

Not everybody works with the MX51, and if we do not write some
additional info it is difficult to find a relation in the reference
manual ;-).

> I sent 4 patches and received them all on the mailing-list. Are you sure you 
> miss two of them?

I have found them on gmane now, thanks.

Best regards,
Stefano

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[U-Boot] [PATCH] S5P: mmc: fix the mmc offset

[Minkyu Kang]

This patch fixed the size of mmc structure.

Signed-off-by: Minkyu Kang 
---
 arch/arm/include/asm/arch-s5pc1xx/mmc.h |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h 
b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
index ac560c2..68c59d1 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
@@ -56,7 +56,7 @@ struct s5p_mmc {
unsigned intcontrol4;
unsigned char   res4[0x6e];
unsigned short  hcver;
-   unsigned char   res5[0xFFF00];
+   unsigned char   res5[0xFFF02];
 };
 
 struct mmc_host {
-- 
1.7.0.4
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Re: [U-Boot] [PATCH] Use common function to set GPIOs for MX3 and MX5

[David Jander]

Hi Stefano,

On Friday 20 August 2010 10:20:11 am Stefano Babic wrote:
> diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
> index e15a63c..54af2e3 100644
> --- a/drivers/spi/mxc_spi.c
> +++ b/drivers/spi/mxc_spi.c
> @@ -23,6 +23,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
> 
>  #ifdef CONFIG_MX27
>  /* i.MX27 has a completely wrong register layout and register definitions
>  in the @@ -68,9 +69,6 @@ static unsigned long spi_bases[] = {
>   0x53f84000,
>  };
> 
> -#define OUT  MX31_GPIO_DIRECTION_OUT
> -#define mxc_gpio_direction   mx31_gpio_direction
> -#define mxc_gpio_set mx31_gpio_set
>  #elif defined(CONFIG_MX51)
>  #include 
>  #include 
> @@ -111,13 +109,12 @@ static unsigned long spi_bases[] = {
>   CSPI2_BASE_ADDR,
>   CSPI3_BASE_ADDR,
>  };
> -#define mxc_gpio_direction(gpio, dir)(0)
> -#define mxc_gpio_set(gpio, value){}
> -#define OUT  1

After this change, it seems something else is missing:
GCC somehow removed the following code for i.MX51 without actually compiling 
the arguments to the functions (???), but now it becomes evident this only 
compiles for i.MX31:

void spi_cs_activate(struct spi_slave *slave)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
if (mxcs->gpio > 0)
mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
}

void spi_cs_deactivate(struct spi_slave *slave)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
if (mxcs->gpio > 0)
mxc_gpio_set(mxcs->gpio,
  !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
}

On i.MX51 SSPOL is set in the config register, and per SS individually. 
Therefore, MXC_CSPICTRL_SSPOL isn't defined for i.MX51.

Best regards,

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Re: [U-Boot] [PATCH 4/4] Added initial support for PRTLVT2-based boards.

[Stefano Babic]

Wolfgang Denk wrote:

Hi Wolfgang,
>> +pmic_reg_write(REG_POWER_MISC, GPO4ADIN);
> 
> It would really be great if someone cold clean up this mess in
> "include/fsl_pmic.h"
> 
> Using an "enum" for register definitions is just horrible.
> 
> I am well aware that you did not introduce this code, but reading this
> feels is if my nails are rolling up.

Well, that's me ! I am aware it sounds crazy. However, the registers on
the pmic are not memory mapped and the access is done via SPI.
The pmic manuals (MC13783, MC13892,) describe the SPI frame (ok, frame
is probably a big word..it is only a 32 bit) and one of the field is the
internal register number.

Using a structure looks like to me even stranger. We have to use some
kind of offsetof() to get the index number back and put it inside the
SPI data.

Best regards,
Stefano Babic

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[U-Boot] [PATCH 1/8] PXA: pxafb: Add ACX517AKN support

[Marek Vasut]

ACX517AKN LCD panel is found in Palm Tungsten|C

Signed-off-by: Marek Vasut 
---
No changes

 arch/arm/cpu/pxa/pxafb.c |   34 ++
 1 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/pxa/pxafb.c b/arch/arm/cpu/pxa/pxafb.c
index 524a03b..328fa7a 100644
--- a/arch/arm/cpu/pxa/pxafb.c
+++ b/arch/arm/cpu/pxa/pxafb.c
@@ -215,6 +215,40 @@ vidinfo_t panel_info = {
 
 /*--*/
 
+#ifdef CONFIG_ACX517AKN
+
+# define LCD_BPP   LCD_COLOR8
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0 0x003008f9
+# define REG_LCCR3 0x0376
+
+vidinfo_t panel_info = {
+   vl_col: 320,
+   vl_row: 320,
+   vl_width:   320,
+   vl_height:  320,
+   vl_clkp:CONFIG_SYS_HIGH,
+   vl_oep: CONFIG_SYS_LOW,
+   vl_hsp: CONFIG_SYS_LOW,
+   vl_vsp: CONFIG_SYS_LOW,
+   vl_dp:  CONFIG_SYS_HIGH,
+   vl_bpix:LCD_BPP,
+   vl_lbw: 0,
+   vl_splt:1,
+   vl_clor:1,
+   vl_tft: 1,
+   vl_hpw: 0x04,
+   vl_blw: 0x1c,
+   vl_elw: 0x08,
+   vl_vpw: 0x01,
+   vl_bfw: 0x07,
+   vl_efw: 0x08,
+};
+#endif /* CONFIG_ACX517AKN */
+
+/*--*/
+
 #if LCD_BPP == LCD_COLOR8
 void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
 #endif
-- 
1.7.1

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[U-Boot] [PATCH 3/8 v2] PXA: Palm Tungsten|C Support

[Marek Vasut]

This patch adds support for the Palm Tungsten|C PXA255 board. The support
includes:
- LCD
- MMC
- UART
- NOR

Signed-off-by: Marek Vasut 
---
Fix line-over-80s
Fix off-tree build
Fix buggy comments
Add missing MAINTAINERS and MAKEALL entries
(the above is true for the rest of patches adding new platforms)

 MAINTAINERS  |4 +
 MAKEALL  |1 +
 board/palmtc/Makefile|   49 +
 board/palmtc/config.mk   |1 +
 board/palmtc/lowlevel_init.S |   39 +++
 board/palmtc/palmtc.c|   58 ++
 board/palmtc/u-boot.lds  |   56 ++
 boards.cfg   |1 +
 include/configs/palmtc.h |  247 ++
 9 files changed, 456 insertions(+), 0 deletions(-)
 create mode 100644 board/palmtc/Makefile
 create mode 100644 board/palmtc/config.mk
 create mode 100644 board/palmtc/lowlevel_init.S
 create mode 100644 board/palmtc/palmtc.c
 create mode 100644 board/palmtc/u-boot.lds
 create mode 100644 include/configs/palmtc.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 4b91b0f..70f03fb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -796,6 +796,10 @@ Greg Ungerer 
cm4116  ks8695p
cm4148  ks8695p
 
+Marek Vasut 
+
+   palmtc  xscale
+
 Hugo Villeneuve 
 
SFFSDR  ARM926EJS
diff --git a/MAKEALL b/MAKEALL
index b34ae33..b871976 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -713,6 +713,7 @@ LIST_pxa="  \
delta   \
innokom \
lubbock \
+   palmtc  \
pleb2   \
polaris \
pxa255_idp  \
diff --git a/board/palmtc/Makefile b/board/palmtc/Makefile
new file mode 100644
index 000..20ac4e1
--- /dev/null
+++ b/board/palmtc/Makefile
@@ -0,0 +1,49 @@
+#
+# Palm Tungsten|C Support
+#
+# Copyright (C) 2009-2010 Marek Vasut 
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS  := palmtc.o
+SOBJS  := lowlevel_init.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+   $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+   rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+   rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/palmtc/config.mk b/board/palmtc/config.mk
new file mode 100644
index 000..1d650ac
--- /dev/null
+++ b/board/palmtc/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xa100
diff --git a/board/palmtc/lowlevel_init.S b/board/palmtc/lowlevel_init.S
new file mode 100644
index 000..74050dc
--- /dev/null
+++ b/board/palmtc/lowlevel_init.S
@@ -0,0 +1,39 @@
+/*
+ * Palm Tungsten|C Lowlevel Hardware Initialization
+ *
+ * Copyright (C) 2010 Marek Vasut 
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+.globl lowlevel_init
+lowlevel_init:
+   pxa_gpio_setup
+   pxa_wait_ticks  0x8000
+   pxa_mem_setup
+   pxa_wakeup
+   pxa_intr_setup
+   pxa_clock_setup
+
+   mov pc, lr
diff --git a/board/palmtc/palmtc.c b/board/palmtc/palmtc.c
new file mode 100644
index 000..0c98eb6
--- /dev/null
+++ b/board/palmtc/palmtc.c
@@ -0,0

[U-Boot] [PATCH 2/8] common: Enable serial for PXA250

[Marek Vasut]

Signed-off-by: Marek Vasut 
---
No changes

 common/serial.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/common/serial.c b/common/serial.c
index fceabfa..7148cb9 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static struct serial_device *serial_devices = NULL;
 static struct serial_device *serial_current = NULL;
 
-#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA27X)
+#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA27X) && 
!defined(CONFIG_PXA250)
 struct serial_device *__default_serial_console (void)
 {
 #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
-- 
1.7.1

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[U-Boot] [PATCH 4/8] PXA: pxafb: Add support for Sharp LQ038J7DH53

[Marek Vasut]

This LCD panel is found in Palm LifeDrive handheld

Signed-off-by: Marek Vasut 
---
No changes

 arch/arm/cpu/pxa/pxafb.c |   34 ++
 1 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/pxa/pxafb.c b/arch/arm/cpu/pxa/pxafb.c
index 328fa7a..066f49e 100644
--- a/arch/arm/cpu/pxa/pxafb.c
+++ b/arch/arm/cpu/pxa/pxafb.c
@@ -249,6 +249,40 @@ vidinfo_t panel_info = {
 
 /*--*/
 
+#ifdef CONFIG_LQ038J7DH53
+
+# define LCD_BPP   LCD_COLOR8
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0 0x003008f9
+# define REG_LCCR3 0x0374
+
+vidinfo_t panel_info = {
+   vl_col: 320,
+   vl_row: 480,
+   vl_width:   320,
+   vl_height:  480,
+   vl_clkp:CONFIG_SYS_HIGH,
+   vl_oep: CONFIG_SYS_LOW,
+   vl_hsp: CONFIG_SYS_LOW,
+   vl_vsp: CONFIG_SYS_LOW,
+   vl_dp:  CONFIG_SYS_HIGH,
+   vl_bpix:LCD_BPP,
+   vl_lbw: 0,
+   vl_splt:1,
+   vl_clor:1,
+   vl_tft: 1,
+   vl_hpw: 0x04,
+   vl_blw: 0x20,
+   vl_elw: 0x01,
+   vl_vpw: 0x01,
+   vl_bfw: 0x04,
+   vl_efw: 0x01,
+};
+#endif /* CONFIG_ACX517AKN */
+
+/*--*/
+
 #if LCD_BPP == LCD_COLOR8
 void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
 #endif
-- 
1.7.1

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[U-Boot] [PATCH 5/8] PXA: Add initial Palm LifeDrive support

[Marek Vasut]

Signed-off-by: Marek Vasut 
---
Changes same as in PalmTC

 MAINTAINERS  |1 +
 MAKEALL  |1 +
 board/palmld/Makefile|   49 
 board/palmld/config.mk   |1 +
 board/palmld/lowlevel_init.S |   45 +++
 board/palmld/palmld.c|   68 +++
 board/palmld/u-boot.lds  |   56 +
 boards.cfg   |1 +
 include/configs/palmld.h |  273 ++
 9 files changed, 495 insertions(+), 0 deletions(-)
 create mode 100644 board/palmld/Makefile
 create mode 100644 board/palmld/config.mk
 create mode 100644 board/palmld/lowlevel_init.S
 create mode 100644 board/palmld/palmld.c
 create mode 100644 board/palmld/u-boot.lds
 create mode 100644 include/configs/palmld.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 70f03fb..5d20dca 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -798,6 +798,7 @@ Greg Ungerer 
 
 Marek Vasut 
 
+   palmld  xscale
palmtc  xscale
 
 Hugo Villeneuve 
diff --git a/MAKEALL b/MAKEALL
index b871976..1642abe 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -713,6 +713,7 @@ LIST_pxa="  \
delta   \
innokom \
lubbock \
+   palmld  \
palmtc  \
pleb2   \
polaris \
diff --git a/board/palmld/Makefile b/board/palmld/Makefile
new file mode 100644
index 000..bcb014d
--- /dev/null
+++ b/board/palmld/Makefile
@@ -0,0 +1,49 @@
+#
+# Palm LifeDrive Support
+#
+# Copyright (C) 2010 Marek Vasut 
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS  := palmld.o
+SOBJS  := lowlevel_init.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+   $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+   rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+   rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/palmld/config.mk b/board/palmld/config.mk
new file mode 100644
index 000..1d650ac
--- /dev/null
+++ b/board/palmld/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xa100
diff --git a/board/palmld/lowlevel_init.S b/board/palmld/lowlevel_init.S
new file mode 100644
index 000..e3382ee
--- /dev/null
+++ b/board/palmld/lowlevel_init.S
@@ -0,0 +1,45 @@
+/*
+ * Palm LifeDrive Lowlevel Hardware Initialization
+ *
+ * Copyright (C) 2010 Marek Vasut 
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+.globl lowlevel_init
+lowlevel_init:
+   pxa_gpio_setup
+
+   /* Enable GPIO reset */
+   ldr r0, =PCFR
+   mov r1, #0x30
+   str r1, [r0]
+
+   pxa_wait_ticks  0x8000
+   pxa_mem_setup
+   pxa_wakeup
+   pxa_intr_setup
+   pxa_clock_setup
+
+   mov pc, lr
diff --git a/board/palmld/palmld.c b/board/palmld/palmld.c
new file mode 100644
index 000..209f0b4
--- /dev/null
+++ b/board/palmld/palmld.c
@@ -0,0 +1,68 @@
+/*
+ * Palm LifeDrive Support
+ *
+ * Copyright (C) 2010 Marek Vasut 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License

[U-Boot] [PATCH 6/8] PXA: Voipac270 improvements

[Marek Vasut]

128MB NOR module support.
Define __io to get harddrive working.
Fix saving of environment into OneNAND.
Boot from harddrive when possible.
Add missing MAINTAINERS entry.

Signed-off-by: Marek Vasut 
---
Changes same as in PalmTC

 MAINTAINERS   |1 +
 MAKEALL   |3 +-
 Makefile  |7 ++-
 board/vpac270/Makefile|7 +--
 board/vpac270/lowlevel_init.S |1 -
 board/vpac270/vpac270.c   |   41 ++--
 include/configs/vpac270.h |  106 +++-
 7 files changed, 87 insertions(+), 79 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 5d20dca..c35a277 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -800,6 +800,7 @@ Marek Vasut 
 
palmld  xscale
palmtc  xscale
+   vpac270 xscale
 
 Hugo Villeneuve 
 
diff --git a/MAKEALL b/MAKEALL
index 1642abe..52472de 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -719,7 +719,8 @@ LIST_pxa="  \
polaris \
pxa255_idp  \
trizepsiv   \
-   vpac270_nor \
+   vpac270_128M_nor\
+   vpac270_256M_nor\
vpac270_onenand \
wepep250\
xaeniax \
diff --git a/Makefile b/Makefile
index 4f1cb1b..3f2b304 100644
--- a/Makefile
+++ b/Makefile
@@ -2180,13 +2180,18 @@ trizepsiv_config:   unconfig
fi;
@$(MKCONFIG) -n $@ -a trizepsiv arm pxa trizepsiv
 
-vpac270_nor_config \
+vpac270_nor_256M_config \
+vpac270_nor_128M_config \
 vpac270_onenand_config : unconfig
@mkdir -p $(obj)include
@if [ "$(findstring onenand,$@)" ] ; then \
echo "#define CONFIG_ONENAND_U_BOOT" \
>>$(obj)include/config.h ; \
fi;
+   @if [ "$(findstring 256M,$@)" ] ; then \
+   echo "#define CONFIG_256M_U_BOOT" \
+   >>$(obj)include/config.h ; \
+   fi;
@$(MKCONFIG) -n $@ -a vpac270 arm pxa vpac270
 
 #
diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile
index c6f4c7c..f5014fc 100644
--- a/board/vpac270/Makefile
+++ b/board/vpac270/Makefile
@@ -1,10 +1,7 @@
-
 #
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+# Voipac PXA270 Support
 #
-# See file CREDITS for list of people who contributed to this
-# project.
+# Copyright (C) 2010 Marek Vasut 
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License as
diff --git a/board/vpac270/lowlevel_init.S b/board/vpac270/lowlevel_init.S
index ec0d12c..c40d12f 100644
--- a/board/vpac270/lowlevel_init.S
+++ b/board/vpac270/lowlevel_init.S
@@ -3,7 +3,6 @@
  *
  * Copyright (C) 2010 Marek Vasut 
  *
- *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c
index 18e47e2..2d01e22 100644
--- a/board/vpac270/vpac270.c
+++ b/board/vpac270/vpac270.c
@@ -1,16 +1,7 @@
 /*
- * (C) Copyright 2004
- * Robert Whaley, Applied Data Systems, Inc. rwha...@applieddata.net
+ * Voipac PXA270 Support
  *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. khar...@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH 
- * Marius Groeger 
- *
- * See file CREDITS for list of people who contributed to this
- * project.
+ * Copyright (C) 2010 Marek Vasut 
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -31,29 +22,19 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* - */
-
 /*
  * Miscelaneous platform dependent initialisations
  */
-extern struct serial_device serial_ffuart_device;
-extern struct serial_device serial_btuart_device;
-extern struct serial_device serial_stuart_device;
-
-struct serial_device *default_serial_console (void)
-{
-   return &serial_ffuart_device;
-}
-
 int board_init (void)
 {
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
 
-   /* arch number of vpac270 */
+   /* Arch number of vpac270 */
gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
 
/* adress of boot parameters */
@@ -62,17 +43,24 @@ int board_init (void)
return 0;
 }
 
+struct serial_device *default_serial_console (void)
+{
+   return &serial_ffuart_device;
+}
+
 int dram_init (void)
 {
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-   gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-   gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 
+#ifdef CONFIG_256M_U_BOOT
+   gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+   gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
return 0;
 }
 

[U-Boot] [PATCH 7/8] PXA: Balloon3 board support

[Marek Vasut]

The following hardware is currently supported:
- UART
- USB Host
- FPGA

Signed-off-by: Marek Vasut 
---
Changes same as in PalmTC

 MAINTAINERS|1 +
 MAKEALL|1 +
 board/balloon3/Makefile|   49 +++
 board/balloon3/balloon3.c  |  224 +
 board/balloon3/config.mk   |1 +
 board/balloon3/lowlevel_init.S |   36 ++
 board/balloon3/u-boot.lds  |   55 
 boards.cfg |1 +
 include/configs/balloon3.h |  269 
 9 files changed, 637 insertions(+), 0 deletions(-)
 create mode 100644 board/balloon3/Makefile
 create mode 100644 board/balloon3/balloon3.c
 create mode 100644 board/balloon3/config.mk
 create mode 100644 board/balloon3/lowlevel_init.S
 create mode 100644 board/balloon3/u-boot.lds
 create mode 100644 include/configs/balloon3.h

diff --git a/MAINTAINERS b/MAINTAINERS
index c35a277..433eae4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -798,6 +798,7 @@ Greg Ungerer 
 
 Marek Vasut 
 
+   balloon3xscale
palmld  xscale
palmtc  xscale
vpac270 xscale
diff --git a/MAKEALL b/MAKEALL
index 52472de..9d149e2 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -706,6 +706,7 @@ LIST_at91=" \
 #
 
 LIST_pxa=" \
+   balloon3\
cerf250 \
colibri_pxa270  \
cradle  \
diff --git a/board/balloon3/Makefile b/board/balloon3/Makefile
new file mode 100644
index 000..3928e1f
--- /dev/null
+++ b/board/balloon3/Makefile
@@ -0,0 +1,49 @@
+#
+# Balloon3 Support
+#
+# Copyright (C) 2010 Marek Vasut 
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS  := balloon3.o
+SOBJS  := lowlevel_init.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+   $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+   rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+   rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c
new file mode 100644
index 000..6d682d9
--- /dev/null
+++ b/board/balloon3/balloon3.c
@@ -0,0 +1,224 @@
+/*
+ * Balloon3 Support
+ *
+ * Copyright (C) 2010 Marek Vasut 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void balloon3_init_fpga(void);
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+   /* arch number of vpac270 */
+   gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
+
+   /* adress of boot parameters */
+   gd->bd->bi_boot_params = 0xa100;
+
+   /* Init the FPGA */
+   balloon3_init_fpga();
+
+   return 0;
+}
+
+struct serial_device *default_serial_console (void)
+{
+   return &serial_stuart_device;
+}
+
+int dram_init (void)
+{
+   gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+   gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+   gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+
+   gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+   gd->bd->bi_dram[1].siz

[U-Boot] [PATCH 8/8] PXA: Add missing MAINTAINERS entries

[Marek Vasut]

Signed-off-by: Marek Vasut 
---
No changes

 MAINTAINERS |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 433eae4..7d66f7d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -799,9 +799,11 @@ Greg Ungerer 
 Marek Vasut 
 
balloon3xscale
+   colibri_pxa270  xscale
palmld  xscale
palmtc  xscale
vpac270 xscale
+   zipitz2 xscale
 
 Hugo Villeneuve 
 
-- 
1.7.1

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Re: [U-Boot] [PATCH 4/4] Added initial support for PRTLVT2-based boards.

[Stefano Babic]

David Jander wrote:
> Signed-off-by: David Jander 
> ---

Hi David,

in addition to Wolfgang's comments:

> +static u32 system_rev;
> +struct io_board_ctrl *mx51_io_board;

Structure is not used, and probably does not match your board. You
should drop it.

> +#define POUT_HS (PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST)
> +#define POUT_MS (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)
> +#define POUT_LS (PAD_CTL_DRV_MEDIUM)
> +#define PIN_HYS (PAD_CTL_HYS_ENABLE)
> +#define PIN_HYS_PULL (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | 
> PAD_CTL_PUE_PULL)
> +#define PIN_HYS_KEEP (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE)
> +#define PIO_OD  (PIN_HYS_PULL | PAD_CTL_22K_PU | 
> PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_DRV_MEDIUM)

Consider to put these defines in include/asm/arch-mx51/iomux.h. They
could be usefult for other boards, too.

> + /* Raise the core frequency to 800MHz */
> + /* printf("Core at 400 MHz!\n"); */
> + /* writel(0x1, &mxc_ccm->cacrr); */
> + writel(0x0, &mxc_ccm->cacrr);

Comment is misleading. Remove what is not needed.

> + /* Setup other io's */
> + for(t=0; other_io_conf[t].pin>=0; t++) {

Add spaces when needed.

> +#ifdef BOARD_LATE_INIT

Probably it is better (and in mx51evk, too) to remove the #ifdef,
because we need to initialize the pmic, else some functionalities cannot
work. It is mandatory that power_init is called.

> diff --git a/board/Protonic/prtlvt2/prtlvt2.h 
> b/board/Protonic/prtlvt2/prtlvt2.h
> +#ifndef __BOARD_FREESCALE_MX51_EVK_H__
> +#define __BOARD_FREESCALE_MX51_EVK_H__
> +
> +#ifndef __ASSEMBLY__
> +struct io_board_ctrl {
> + u16 led_ctrl;   /* 0x00 */
> + u16 resv1[0x03];
> + u16 sb_stat;/* 0x08 */
> + u16 resv2[0x03];
> + u16 int_stat;   /* 0x10 */
> + u16 resv3[0x07];
> + u16 int_rest;   /* 0x20 */
> + u16 resv4[0x0B];
> + u16 int_mask;   /* 0x38 */
> + u16 resv5[0x03];
> + u16 id1;/* 0x40 */
> + u16 resv6[0x03];
> + u16 id2;/* 0x48 */
> + u16 resv7[0x03];
> + u16 version;/* 0x50 */
> + u16 resv8[0x03];
> + u16 id3;/* 0x58 */
> + u16 resv9[0x03];
> + u16 sw_reset;   /* 0x60 */
> +};
> +#endif

Is this structure really used ? I have not seen in code. Or does it come
only from mx51evk ? You can remove the whole file, if it is not needed.

Best regards,
Stefano Babic

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[U-Boot] [PULL] U-Boot-pxa pull request

[Marek Vasut]

Hi, please pull my git://git.denx.de/u-boot-pxa for-wd-master branch into your -
master branch. Thanks

The following changes since commit bd2313078114c4b44c4a5ce149af43bcb7fc8854:

  Merge branch 'master' of ssh://gemini/home/wd/git/u-boot/master (2010-08-18 
21:16:35 +0200)

are available in the git repository at:

  git://git.denx.de/u-boot-pxa.git for-wd-master

Marek Vasut (8):
  PXA: pxafb: Add ACX517AKN support
  common: Enable serial for PXA250
  PXA: Palm Tungsten|C Support
  PXA: pxafb: Add support for Sharp LQ038J7DH53
  PXA: Add initial Palm LifeDrive support
  PXA: Voipac270 improvements
  PXA: Balloon3 board support
  PXA: Add missing MAINTAINERS entries

 MAINTAINERS|9 ++
 MAKEALL|6 +-
 Makefile   |7 +-
 arch/arm/cpu/pxa/pxafb.c   |   68 ++
 board/balloon3/Makefile|   49 +++
 board/balloon3/balloon3.c  |  224 
 board/balloon3/config.mk   |1 +
 board/balloon3/lowlevel_init.S |   36 ++
 board/balloon3/u-boot.lds  |   55 
 board/palmld/Makefile  |   49 +++
 board/palmld/config.mk |1 +
 board/palmld/lowlevel_init.S   |   45 +++
 board/palmld/palmld.c  |   68 ++
 board/palmld/u-boot.lds|   56 
 board/palmtc/Makefile  |   49 +++
 board/palmtc/config.mk |1 +
 board/palmtc/lowlevel_init.S   |   39 ++
 board/palmtc/palmtc.c  |   58 +
 board/palmtc/u-boot.lds|   56 
 board/vpac270/Makefile |7 +-
 board/vpac270/lowlevel_init.S  |1 -



 board/vpac270/vpac270.c|   41 +++  



 boards.cfg |3 +



 common/serial.c|2 +-   



 include/configs/balloon3.h |  269 +++  



 include/configs/palmld.h   |  273  



 include/configs/palmtc.h   |  247  



 include/configs/vpac270.h  |  106 +--- 



 28 files changed, 1746 insertions(+), 80 deletions(-)  



 create mode 100644 board/balloon3/Makefile 



 create mode 100644 board/balloon3/balloon3.c   



 create mode 100644 board/balloon3/config.mk



 create mode 100644 board/balloon3/lowlevel_init.S  



 create mode 100644 board/balloon3/u-boot.lds   

Re: [U-Boot] [PATCH] Use common function to set GPIOs for MX3 and MX5

[Stefano Babic]

David Jander wrote:
> Hi Stefano,
> 
Hi David,

> After this change, it seems something else is missing:
> GCC somehow removed the following code for i.MX51 without actually compiling 
> the arguments to the functions (???), but now it becomes evident this only 
> compiles for i.MX31:

Understood, in SPI driver. Really I had another patch in my private
tree, but I have not yet sent. However, as you note, it makes no sense
to split changes in two patches.

I will rebase my tree and send V2 version of the pacth, inclusive the
changes for mxc_spi.c

> void spi_cs_activate(struct spi_slave *slave)
> {
>   struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
>   if (mxcs->gpio > 0)
>   mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);

I know, I had already change this code...I store ss_pol in the priivate
structure to be independent from the processor register.

I will send the compound patch soon.

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH] Use common function to set GPIOs for MX3 and MX5

[David Jander]

Stefano,

On Friday 20 August 2010 12:01:00 pm Stefano Babic wrote:
> > After this change, it seems something else is missing:
> > GCC somehow removed the following code for i.MX51 without actually
> > compiling the arguments to the functions (???), but now it becomes
> > evident this only compiles for i.MX31:
> 
> Understood, in SPI driver. Really I had another patch in my private
> tree, but I have not yet sent. However, as you note, it makes no sense
> to split changes in two patches.
> 
> I will rebase my tree and send V2 version of the pacth, inclusive the
> changes for mxc_spi.c

Ok, thanks!

> > void spi_cs_activate(struct spi_slave *slave)
> > {
> > struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
> > if (mxcs->gpio > 0)
> > mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
> 
> I know, I had already change this code...I store ss_pol in the priivate
> structure to be independent from the processor register.
> 
> I will send the compound patch soon.

Great. I'll wait.
In the meantime I have just done this to get it working:

#ifdef CONFIG_MX31
void spi_cs_activate(struct spi_slave *slave)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
if (mxcs->gpio > 0)
mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
}

void spi_cs_deactivate(struct spi_slave *slave)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
if (mxcs->gpio > 0)
mxc_gpio_set(mxcs->gpio,
  !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
}
#elif defined (CONFIG_MX51)
void spi_cs_activate(struct spi_slave *slave)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
unsigned int val = mxcs->cfg_reg & 
(1 << (slave->cs + MXC_CSPICON_SSPOL));
if (mxcs->gpio > 0)
mxc_gpio_set(mxcs->gpio, val);
}

void spi_cs_deactivate(struct spi_slave *slave)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
unsigned int val = !(mxcs->cfg_reg & 
(1 << (slave->cs + MXC_CSPICON_SSPOL)));
if (mxcs->gpio > 0)
mxc_gpio_set(mxcs->gpio, val);
}
#endif

Seems to work, but never mind...

Best regards,

-- 
David Jander
Protonic Holland.
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Re: [U-Boot] [PATCH] Use common function to set GPIOs for MX3 and MX5

[Stefano Babic]

David Jander wrote:

> Great. I'll wait.
> In the meantime I have just done this to get it working:
> 
> #ifdef CONFIG_MX31
> void spi_cs_activate(struct spi_slave *slave)
> {
>   struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
>   if (mxcs->gpio > 0)
>   mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
> }
> 

Ok, but one goal I have is to get rid of nasty #ifdef CONFIG_MX*. I
introduce general gpio functions to make code more common, and I do not
want to fall back adding processor switches.

> Seems to work, but never mind...

Ok, I will resend my patch, I hope you can give a chance a test it on
your target.

Best regards,
Stefano

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Re: [U-Boot] [PATCH 4/4] Added initial support for PRTLVT2-based boards.

[David Jander]

On Friday 20 August 2010 11:51:18 am Stefano Babic wrote:
> Hi David,
> 
> in addition to Wolfgang's comments:
> > +static u32 system_rev;
> > +struct io_board_ctrl *mx51_io_board;
> 
> Structure is not used, and probably does not match your board. You
> should drop it.

Ok, I was already wondering what this did here I'll just remove it.

> > +#define POUT_HS (PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST)
> > +#define POUT_MS (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)
> > +#define POUT_LS (PAD_CTL_DRV_MEDIUM)
> > +#define PIN_HYS (PAD_CTL_HYS_ENABLE)
> > +#define PIN_HYS_PULL (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> > PAD_CTL_PUE_PULL) +#define PIN_HYS_KEEP (PAD_CTL_HYS_ENABLE |
> > PAD_CTL_PKE_ENABLE)
> > +#define PIO_OD  (PIN_HYS_PULL | PAD_CTL_22K_PU |
> > PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_DRV_MEDIUM)
> 
> Consider to put these defines in include/asm/arch-mx51/iomux.h. They
> could be usefult for other boards, too.

Hmmm. In that case they should have other names, and one should probably make 
the set complete with all combinations, and I doubt it'll make sense anymore 
then
This subset of possibilities is too specific to our board I fear.
I had already been complaining about some seemingly arbitrary combinations of 
IO-pad settings being used in SoC-driver code in the linux kernel. IMHO, one 
should never choose a specific combination of settings without excactly 
knowing it is electrically correct for that specific pin on that specific 
board... not only because it works, but also from EMC considerations.
I also think, that in theory this would make the kernel board-specific in that 
case... not something one would want I believe. For that reason, I keep 
thinking that correct and thorough IO-pad setup specific for each board should 
be done in the boot-loader never in the kernel.

OTOH, maybe one could come up with some commonly-used combinations... but 
which ones?

> > +   /* Raise the core frequency to 800MHz */
> > +   /* printf("Core at 400 MHz!\n"); */
> > +   /* writel(0x1, &mxc_ccm->cacrr); */
> > +   writel(0x0, &mxc_ccm->cacrr);
> 
> Comment is misleading. Remove what is not needed.

Sorry, I was too lazy to make a configuration option out of this... will fix 
it.

> > +   /* Setup other io's */
> > +   for(t=0; other_io_conf[t].pin>=0; t++) {
> 
> Add spaces when needed.

Ok.

> > +#ifdef BOARD_LATE_INIT
> 
> Probably it is better (and in mx51evk, too) to remove the #ifdef,
> because we need to initialize the pmic, else some functionalities cannot
> work. It is mandatory that power_init is called.

I agree. I had always been "about to remove it" ;-)

> > diff --git a/board/Protonic/prtlvt2/prtlvt2.h
> > b/board/Protonic/prtlvt2/prtlvt2.h +#ifndef
> > __BOARD_FREESCALE_MX51_EVK_H__
> > +#define __BOARD_FREESCALE_MX51_EVK_H__
> > +
> > +#ifndef __ASSEMBLY__
> > +struct io_board_ctrl {
> > +   u16 led_ctrl;   /* 0x00 */
> > +   u16 resv1[0x03];
> > +   u16 sb_stat;/* 0x08 */
> > +   u16 resv2[0x03];
> > +   u16 int_stat;   /* 0x10 */
> > +   u16 resv3[0x07];
> > +   u16 int_rest;   /* 0x20 */
> > +   u16 resv4[0x0B];
> > +   u16 int_mask;   /* 0x38 */
> > +   u16 resv5[0x03];
> > +   u16 id1;/* 0x40 */
> > +   u16 resv6[0x03];
> > +   u16 id2;/* 0x48 */
> > +   u16 resv7[0x03];
> > +   u16 version;/* 0x50 */
> > +   u16 resv8[0x03];
> > +   u16 id3;/* 0x58 */
> > +   u16 resv9[0x03];
> > +   u16 sw_reset;   /* 0x60 */
> > +};
> > +#endif
> 
> Is this structure really used ? I have not seen in code. Or does it come
> only from mx51evk ? You can remove the whole file, if it is not needed.

No idea what it does. It's copied from MX51EVK. I will try removing it.

Best regards,

-- 
David Jander
Protonic Holland.
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Re: [U-Boot] [PATCH] Use common function to set GPIOs for MX3 and MX5

[David Jander]

On Friday 20 August 2010 12:20:25 pm Stefano Babic wrote:
> David Jander wrote:
> > Great. I'll wait.
> > In the meantime I have just done this to get it working:
> >
> > #ifdef CONFIG_MX31
> > void spi_cs_activate(struct spi_slave *slave)
> > {
> > struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
> > if (mxcs->gpio > 0)
> > mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
> > }
> 
> Ok, but one goal I have is to get rid of nasty #ifdef CONFIG_MX*. I
> introduce general gpio functions to make code more common, and I do not
> want to fall back adding processor switches.

Absolutely right. I just posted it as reference for your patch eventually, not 
because I thought it was good that way.

> > Seems to work, but never mind...
> 
> Ok, I will resend my patch, I hope you can give a chance a test it on
> your target.

Will do.
Btw, do you have any idea why spi_xchg_single() hangs while transmitting the 
second word without claiming the bus again?

Also, I don't know if you already fixed mxc_spi.c, to use the correct byte-
ordering when sending u8 buffers. I have a fix, but it is not yet ready.
I essentially renamed spi_xfer() to spi_xfer_fsl(), to be used in the (broken) 
pmic driver, and wrote a new spi_xfer() function which works correcly for u8 
buffers.

Best regards,

-- 
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Re: [U-Boot] [PATCH 4/4] Added initial support for PRTLVT2-based boards.

[Stefano Babic]

David Jander wrote:
> 
> Hmmm. In that case they should have other names, and one should probably make 
> the set complete with all combinations, and I doubt it'll make sense anymore 
> then
> This subset of possibilities is too specific to our board I fear.

Ok, I understand. I have thought it coul be easier to other one to use
the same set of combinations.

>> Is this structure really used ? I have not seen in code. Or does it come
>> only from mx51evk ? You can remove the whole file, if it is not needed.
> 
> No idea what it does. It's copied from MX51EVK. I will try removing it.
> 

This structure comes from older Freescale's source and makes sense only
on another board. I have already merged a patch to drop the usage of the
structure inside the board functions, but rather the mx51evk.h is still
in mainline. I will cleanup in mx51evk, too.

Best regards,
Stefano

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[U-Boot] [PATCH V2] Use common function to set GPIOs for MX3 and MX5

[Stefano Babic]

The patch adds support for setting gpios to the
MX51 processor and change name to the corresponding
functions for MX31. In this way, it is possible to get rid
of nasty #ifdef switches related to the processor type.

Signed-off-by: Stefano Babic 
---
 arch/arm/include/asm/arch-mx31/mx31-regs.h |   14 +++-
 arch/arm/include/asm/arch-mx31/mx31.h  |   25 ---
 arch/arm/include/asm/arch-mx51/imx-regs.h  |6 ++
 board/davedenx/qong/qong.c |   29 
 drivers/gpio/Makefile  |2 +-
 drivers/gpio/mx31_gpio.c   |   88 ---
 drivers/gpio/mxc_gpio.c|  107 
 drivers/spi/mxc_spi.c  |   15 ++--
 include/configs/imx31_phycore.h|2 +-
 include/configs/qong.h |2 +-
 include/mxc_gpio.h |   52 +
 11 files changed, 201 insertions(+), 141 deletions(-)
 delete mode 100644 drivers/gpio/mx31_gpio.c
 create mode 100644 drivers/gpio/mxc_gpio.c
 create mode 100644 include/mxc_gpio.h

diff --git a/arch/arm/include/asm/arch-mx31/mx31-regs.h 
b/arch/arm/include/asm/arch-mx31/mx31-regs.h
index d72585c..f05e743 100644
--- a/arch/arm/include/asm/arch-mx31/mx31-regs.h
+++ b/arch/arm/include/asm/arch-mx31/mx31-regs.h
@@ -57,6 +57,14 @@ struct clock_control_regs {
u32 pdr2;
 };
 
+/* GPIO Registers */
+struct gpio_regs {
+   u32 gpio_dr;
+   u32 gpio_dir;
+   u32 gpio_psr;
+};
+
+
 /* Bit definitions for RCSR register in CCM */
 #define CCM_RCSR_NF16B (1 << 31)
 #define CCM_RCSR_NFMS  (1 << 30)
@@ -153,9 +161,9 @@ struct clock_control_regs {
 /*
  * GPIO
  */
-#define GPIO1_BASE 0x53FCC000
-#define GPIO2_BASE 0x53FD
-#define GPIO3_BASE 0x53FA4000
+#define GPIO1_BASE_ADDR0x53FCC000
+#define GPIO2_BASE_ADDR0x53FD
+#define GPIO3_BASE_ADDR0x53FA4000
 #define GPIO_DR0x  /* data register */
 #define GPIO_GDIR  0x0004  /* direction register */
 #define GPIO_PSR   0x0008  /* pad status register */
diff --git a/arch/arm/include/asm/arch-mx31/mx31.h 
b/arch/arm/include/asm/arch-mx31/mx31.h
index f702d26..5a5aa11 100644
--- a/arch/arm/include/asm/arch-mx31/mx31.h
+++ b/arch/arm/include/asm/arch-mx31/mx31.h
@@ -28,31 +28,6 @@ extern u32 mx31_get_ipg_clk(void);
 #define imx_get_uartclk mx31_get_ipg_clk
 extern void mx31_gpio_mux(unsigned long mode);
 
-enum mx31_gpio_direction {
-   MX31_GPIO_DIRECTION_IN,
-   MX31_GPIO_DIRECTION_OUT,
-};
-
-#ifdef CONFIG_MX31_GPIO
-extern int mx31_gpio_direction(unsigned int gpio,
-  enum mx31_gpio_direction direction);
-extern void mx31_gpio_set(unsigned int gpio, unsigned int value);
-extern int mx31_gpio_get(unsigned int gpio);
-#else
-static inline int mx31_gpio_direction(unsigned int gpio,
- enum mx31_gpio_direction direction)
-{
-   return 1;
-}
-static inline int mx31_gpio_get(unsigned int gpio)
-{
-   return 1;
-}
-static inline void mx31_gpio_set(unsigned int gpio, unsigned int value)
-{
-}
-#endif
-
 void mx31_uart1_hw_init(void);
 void mx31_spi2_hw_init(void);
 
diff --git a/arch/arm/include/asm/arch-mx51/imx-regs.h 
b/arch/arm/include/asm/arch-mx51/imx-regs.h
index 3887d3c..0e3bc2a 100644
--- a/arch/arm/include/asm/arch-mx51/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx51/imx-regs.h
@@ -256,6 +256,12 @@ struct weim {
u32 cswcr2;
 };
 
+/* GPIO Registers */
+struct gpio_regs {
+   u32 gpio_dr;
+   u32 gpio_dir;
+   u32 gpio_psr;
+};
 #endif /* __ASSEMBLER__*/
 
 #endif /*  __ASM_ARCH_MXC_MX51_H__ */
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
index 781333b..59589c2 100644
--- a/board/davedenx/qong/qong.c
+++ b/board/davedenx/qong/qong.c
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "qong_fpga.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -42,9 +43,9 @@ int dram_init (void)
 
 static void qong_fpga_reset(void)
 {
-   mx31_gpio_set(QONG_FPGA_RST_PIN, 0);
+   mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
udelay(30);
-   mx31_gpio_set(QONG_FPGA_RST_PIN, 1);
+   mxc_gpio_set(QONG_FPGA_RST_PIN, 1);
 
udelay(300);
 }
@@ -115,11 +116,11 @@ int board_init (void)
 
/* FPGA reset  Pin */
/* rstn = 0 */
-   mx31_gpio_set(QONG_FPGA_RST_PIN, 0);
-   mx31_gpio_direction(QONG_FPGA_RST_PIN, MX31_GPIO_DIRECTION_OUT);
+   mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
+   mxc_gpio_direction(QONG_FPGA_RST_PIN, MXC_GPIO_DIRECTION_OUT);
 
/* set interrupt pin as input */
-   mx31_gpio_direction(QONG_FPGA_IRQ_PIN, MX31_GPIO_DIRECTION_IN);
+   mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN);
 
 #endif
 
@@ -201,27 +202,27 @@ static void board_nand_setup(void)
qong_fpga_reset();
 
/* Enable NAND flash */
-   mx31_gp

[U-Boot] [PATCH] ARM: Use syslib functions for all CORTEXA8

[Stefano Babic]

The OMAP3 cpu directory contains a syslib file with some utilities
that can be shared by all targets using arm cortexa8 processors,
not only OMAP.

Signed-off-by: Stefano Babic 
---
 arch/arm/cpu/armv7/Makefile|3 +-
 arch/arm/cpu/armv7/omap3/Makefile  |1 -
 arch/arm/cpu/armv7/omap3/syslib.c  |   72 
 arch/arm/cpu/armv7/syslib.c|   69 ++
 arch/arm/include/asm/arch-mx51/sys_proto.h |1 +
 5 files changed, 72 insertions(+), 74 deletions(-)
 delete mode 100644 arch/arm/cpu/armv7/omap3/syslib.c
 create mode 100644 arch/arm/cpu/armv7/syslib.c

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index ae20299..de4b065 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -27,6 +27,7 @@ LIB   = $(obj)lib$(CPU).a
 
 START  := start.o
 COBJS  := cpu.o
+COBJS  += syslib.o
 
 SRCS   := $(START:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS))
@@ -44,4 +45,4 @@ include $(SRCTREE)/rules.mk
 
 sinclude $(obj).depend
 
-#
\ No newline at end of file
+#
diff --git a/arch/arm/cpu/armv7/omap3/Makefile 
b/arch/arm/cpu/armv7/omap3/Makefile
index 79ae267..95526d6 100644
--- a/arch/arm/cpu/armv7/omap3/Makefile
+++ b/arch/arm/cpu/armv7/omap3/Makefile
@@ -32,7 +32,6 @@ COBJS += board.o
 COBJS  += clock.o
 COBJS  += gpio.o
 COBJS  += mem.o
-COBJS  += syslib.o
 COBJS  += sys_info.o
 
 COBJS-$(CONFIG_EMIF4)  += emif4.o
diff --git a/arch/arm/cpu/armv7/omap3/syslib.c 
b/arch/arm/cpu/armv7/omap3/syslib.c
deleted file mode 100644
index 9ced495..000
--- a/arch/arm/cpu/armv7/omap3/syslib.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, 
- *
- * Richard Woodruff 
- * Syed Mohammed Khasim 
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-/
- * sdelay() - simple spin loop.  Will be constant time as
- *  its generally used in bypass conditions only.  This
- *  is necessary until timers are accessible.
- *
- *  not inline to increase chances its in cache when called
- */
-void sdelay(unsigned long loops)
-{
-   __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0"(loops));
-}
-
-/*
- * sr32 - clear & set a value in a bit range for a 32 bit address
- */
-void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
-{
-   u32 tmp, msk = 0;
-   msk = 1 << num_bits;
-   --msk;
-   tmp = readl((u32)addr) & ~(msk << start_bit);
-   tmp |= value << start_bit;
-   writel(tmp, (u32)addr);
-}
-
-/*
- * wait_on_value() - common routine to allow waiting for changes in
- *   volatile regs.
- */
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
- u32 bound)
-{
-   u32 i = 0, val;
-   do {
-   ++i;
-   val = readl((u32)read_addr) & read_bit_mask;
-   if (val == match_value)
-   return 1;
-   if (i == bound)
-   return 0;
-   } while (1);
-}
diff --git a/arch/arm/cpu/armv7/syslib.c b/arch/arm/cpu/armv7/syslib.c
new file mode 100644
index 000..84d17f0
--- /dev/null
+++ b/arch/arm/cpu/armv7/syslib.c
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, 
+ *
+ * Richard Woodruff 
+ * Syed Mohammed Khasim 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warr

[U-Boot] [PATCH] MX51: Added pins definition to set up pads

[Stefano Babic]

Add pins definitions to set up RAM pads. Pins have only
a pad, there is no entry in the multiplexer.

Signed-off-by: Stefano Babic 
---
 arch/arm/include/asm/arch-mx51/mx51_pins.h |   44 
 1 files changed, 44 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx51/mx51_pins.h 
b/arch/arm/include/asm/arch-mx51/mx51_pins.h
index ca26f41..b44ff25 100644
--- a/arch/arm/include/asm/arch-mx51/mx51_pins.h
+++ b/arch/arm/include/asm/arch-mx51/mx51_pins.h
@@ -368,6 +368,50 @@ enum iomux_pins {
MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
+
+   /* The following are PADS used for drive strength */
+
+   MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820),
+   MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838),
+   MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890),
+   MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C),
+   MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C),
+   MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884),
+   MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C),
+   MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864),
+   MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C),
+   MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874),
+   MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878),
+   MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880),
+   MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C),
+   MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C),
+   MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4),
+   MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC),
+   MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8),
+   MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C),
+   MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0),
+   MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0),
+   MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4),
+   MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC),
+   MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C),
+   MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848),
+   MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868),
+   MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4),
+   MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8),
+   MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac),
+   MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0),
+   MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4),
+   MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8),
+   MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC),
+   MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0),
+   MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4),
+   MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8),
+   MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC),
+   MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0),
+   MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4),
+   MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8),
+   MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC),
+   MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0),
 };
 
 #endif /* __ASSEMBLY__ */
-- 
1.6.3.3

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[U-Boot] [PATCH] MX51: add structure to access System Reset Controller

[Stefano Babic]

Signed-off-by: Stefano Babic 
---
 arch/arm/include/asm/arch-mx51/imx-regs.h |   10 ++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx51/imx-regs.h 
b/arch/arm/include/asm/arch-mx51/imx-regs.h
index 0e3bc2a..06f2720 100644
--- a/arch/arm/include/asm/arch-mx51/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx51/imx-regs.h
@@ -262,6 +262,16 @@ struct gpio_regs {
u32 gpio_dir;
u32 gpio_psr;
 };
+
+/* System Reset Controller (SRS) */
+struct src {
+   u32 scr;
+   u32 sbmr;
+   u32 srsr;
+   u32 reserved1[2];
+   u32 sisr;
+   u32 simr;
+};
 #endif /* __ASSEMBLER__*/
 
 #endif /*  __ASM_ARCH_MXC_MX51_H__ */
-- 
1.6.3.3

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[U-Boot] [PATCH] MXC: Add watchdog support to serial driver

[Stefano Babic]

Calls WATCHDOG_RESET() inside serial driver
for boards enabling watchdog.

Signed-off-by: Stefano Babic 
---
 drivers/serial/serial_mxc.c |7 +--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 4b93e7b..110bd15 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -18,6 +18,7 @@
  */
 
 #include 
+#include 
 #ifdef CONFIG_MX31
 #include 
 #else
@@ -189,7 +190,8 @@ void serial_setbrg (void)
 
 int serial_getc (void)
 {
-   while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
+   while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
+   WATCHDOG_RESET();
return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status 
from upper word */
 }
 
@@ -198,7 +200,8 @@ void serial_putc (const char c)
__REG(UART_PHYS + UTXD) = c;
 
/* wait for transmitter to be ready */
-   while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY));
+   while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
+   WATCHDOG_RESET();
 
/* If \n, also do \r */
if (c == '\n')
-- 
1.6.3.3

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[U-Boot] [PATCH] MX51: Drop unused header file for mx51evk

[Stefano Babic]

As stated in 272017853339f5b9685f9488bdaf5405812d12a4,
the mx51evk has not CPLD and all references must be removed.
This patch drop a .h file that still remains in board
directory.

Signed-off-by: Stefano Babic 
---
 board/freescale/mx51evk/mx51evk.c |2 -
 board/freescale/mx51evk/mx51evk.h |   50 -
 2 files changed, 0 insertions(+), 52 deletions(-)
 delete mode 100644 board/freescale/mx51evk/mx51evk.h

diff --git a/board/freescale/mx51evk/mx51evk.c 
b/board/freescale/mx51evk/mx51evk.c
index 75d642b..84386e6 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -33,12 +33,10 @@
 #include 
 #include 
 #include 
-#include "mx51evk.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
 static u32 system_rev;
-struct io_board_ctrl *mx51_io_board;
 
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg esdhc_cfg[2] = {
diff --git a/board/freescale/mx51evk/mx51evk.h 
b/board/freescale/mx51evk/mx51evk.h
deleted file mode 100644
index 2854e71..000
--- a/board/freescale/mx51evk/mx51evk.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __BOARD_FREESCALE_MX51_EVK_H__
-#define __BOARD_FREESCALE_MX51_EVK_H__
-
-#ifndef __ASSEMBLY__
-struct io_board_ctrl {
-   u16 led_ctrl;   /* 0x00 */
-   u16 resv1[0x03];
-   u16 sb_stat;/* 0x08 */
-   u16 resv2[0x03];
-   u16 int_stat;   /* 0x10 */
-   u16 resv3[0x07];
-   u16 int_rest;   /* 0x20 */
-   u16 resv4[0x0B];
-   u16 int_mask;   /* 0x38 */
-   u16 resv5[0x03];
-   u16 id1;/* 0x40 */
-   u16 resv6[0x03];
-   u16 id2;/* 0x48 */
-   u16 resv7[0x03];
-   u16 version;/* 0x50 */
-   u16 resv8[0x03];
-   u16 id3;/* 0x58 */
-   u16 resv9[0x03];
-   u16 sw_reset;   /* 0x60 */
-};
-#endif
-
-#endif
-- 
1.6.3.3

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Re: [U-Boot] [PATCH] MX51: add structure to access System Reset Controller

[Sergei Shtylyov]

Hello.

Stefano Babic wrote:

> Signed-off-by: Stefano Babic 
[...]
> diff --git a/arch/arm/include/asm/arch-mx51/imx-regs.h 
> b/arch/arm/include/asm/arch-mx51/imx-regs.h
> index 0e3bc2a..06f2720 100644
> --- a/arch/arm/include/asm/arch-mx51/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx51/imx-regs.h
> @@ -262,6 +262,16 @@ struct gpio_regs {
>   u32 gpio_dir;
>   u32 gpio_psr;
>  };
> +
> +/* System Reset Controller (SRS) */

So, it's SRS or SRC?

> +struct src {
> + u32 scr;
> + u32 sbmr;
> + u32 srsr;
> + u32 reserved1[2];
> + u32 sisr;
> + u32 simr;
> +};
>  #endif /* __ASSEMBLER__*/

WBR, Sergei
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Re: [U-Boot] [PATCH] Use common function to set GPIOs for MX3 and MX5

[Stefano Babic]

David Jander wrote:
> Absolutely right. I just posted it as reference for your patch eventually, 
> not 
> because I thought it was good that way.

Yes, I know. I want only to point out what we have to reach ;-)

>>> Seems to work, but never mind...
>> Ok, I will resend my patch, I hope you can give a chance a test it on
>> your target.
> 
> Will do.
> Btw, do you have any idea why spi_xchg_single() hangs while transmitting the 
> second word without claiming the bus again?

Can you see where does it hang ? Which device is connected to your SPI
bus ? Does it work with the pmic (I think so, see later...).

> 
> Also, I don't know if you already fixed mxc_spi.c, to use the correct byte-
> ordering when sending u8 buffers.

Well, it seems we are working at the same issues, and probably it is
better if we try some coordination ;-)

I have already fix the byte ordering, but I am fixing now the misaligned
access (this is the reason I have not sent the changes for gpios in the
mxc_spi.c: I am reworking this driver...). In the mainline driver, only
32-bit aligned buffers are allowed, and this is a strong limitation. I
cannot use some other components in u-boot, such as SPI flash, because
the code allocates u8 buffers that can be disaligned. And with other
devices (sensors, eeprom, ...) does not work, because most of them
require to transfer only one or two bytes as command.

Now that I think...is it maybe your case now ? The FIFO can be accessed
only as word, other accesses are not allowed according to the manual.

However, I am currently working on several issues for MX51. It should be
nice to know which are your plans to save both some time ;-)

> I have a fix, but it is not yet ready.
> I essentially renamed spi_xfer() to spi_xfer_fsl(), to be used in the 
> (broken) 
> pmic driver,

As I said, I changed the pmic driver, too. I do not agree we must have
"special" functions, only because something is broken. The pmic works
because it is connected to the FSL SPI controller, and the endianess is
consistent. However, it is common for a SPI driver to allocate a "char"
buffer, and the first byte in the buffer is the first byte sent to the
SPI bus. This is not the case with mxc_spi.c

Regards,
Stefano

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Re: [U-Boot] [PATCH] MX51: add structure to access System Reset Controller

[Stefano Babic]

Sergei Shtylyov wrote:
> Hello.
> 

Hi Sergej,

>> +/* System Reset Controller (SRS) */
> 
>So, it's SRS or SRC?

Thanks to point out. With srs (reset status) and src (reset controller)
I have confused the names..

Best regards,
Stefano

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Re: [U-Boot] [PATCH] Support for Calao USB A9263 board based on AT91SAM9263 CPU

[Reinhard Meyer]

Dear Thomas Petazzoni,

I can find no comments or anything for this patch.

> The Calao USB A9263 board is a board manufactured and sold by Calao
> Systems . Its components are very
> similar to the AT91SAM9263EK board, so its configuration is based
> on the configuration of this board. There are however some
> differences: different clocks, no LCD, etc.
>  MAINTAINERS   |4 +
>  MAKEALL   |1 +

>  Makefile  |3 +

Please change this to use boards.cfg instead.

> +# (C) Copyright 2003-2008
> +# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
> +#
> +# (C) Copyright 2008
> +# Stelian Pop 
> +# Lead Tech Design 
> +#
> +# (C) Copyright 2009
> +# Thomas Petazzoni, Free Electrons, 

Not sure, but I think Copyright should be in newest date at the top...

> +#define CONFIG_ATMEL_USART   1
> +#undef CONFIG_USART0
> +#undef CONFIG_USART1
> +#undef CONFIG_USART2
> +#define CONFIG_USART31   /* USART 3 is DBGU */

Someone complained earlier in a similiar case that #undefs are not allowed
here, convert this into a comment _IF_ your board can use other USARTs for
console at all. If not drop the #undef lines.

If you would like this patch to go mainstream, please resubmit it and
make sure it will apply to current top-of-tree
.

Best Regards
Reinhard

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Re: [U-Boot] [PATCH v3] [ARM] at91: Add support for taskit AT91SAM9G20 boards

[Reinhard Meyer]

Dear Achim Ehrlich,

> are there still objections to our patch or has it just got forgotten?

Just not dealt with (#error: no custodian) :)

Can you please rebase,
and use boards.cfg instead of global Makefile?

Best Regards,
Reinhard

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Re: [U-Boot] [PATCH] Use common function to set GPIOs for MX3 and MX5

[David Jander]

Hi Stefano,

On Friday 20 August 2010 01:19:28 pm Stefano Babic wrote:
> > Will do.
> > Btw, do you have any idea why spi_xchg_single() hangs while transmitting
> > the second word without claiming the bus again?
> 
> Can you see where does it hang ? Which device is connected to your SPI
> bus ? Does it work with the pmic (I think so, see later...).

Just figured out one big mistake. I was debugging spi_flash.c, and had 
CONFIG_ENV_IS_IN_SPI_FLASH set. That means, first SPI access is done before 
malloc is available, and guess what? spi_setup_slave() uses malloc ;-)
So I did something in the way of this:

static struct mxc_spi_slave mxc_spi_slave_pool[4];

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
unsigned int ctrl_reg;
struct mxc_spi_slave *mxcs;
int ret;

if (bus >= ARRAY_SIZE(spi_bases))
return NULL;

//mxcs = malloc(sizeof(struct mxc_spi_slave));
//if (!mxcs)
//  return NULL;
mxcs = &mxc_spi_slave_pool[cs];

The C++ comments show original code, the line below is new.

It still hangs though, waiting for MXC_CSPICTRL_TC to become active. Busy 
finding out why...

I see a one byte access followed by a 5 byte access, of which only 8.5 clock 
pulses come out of SCLK, and then nothing more. MXC_CSPICTRL_TC stays low.

> > Also, I don't know if you already fixed mxc_spi.c, to use the correct
> > byte- ordering when sending u8 buffers.
> 
> Well, it seems we are working at the same issues, and probably it is
> better if we try some coordination ;-)

Good idea.

> I have already fix the byte ordering, but I am fixing now the misaligned
> access (this is the reason I have not sent the changes for gpios in the
> mxc_spi.c: I am reworking this driver...). In the mainline driver, only
> 32-bit aligned buffers are allowed, and this is a strong limitation. I
> cannot use some other components in u-boot, such as SPI flash, because
> the code allocates u8 buffers that can be disaligned. And with other
> devices (sensors, eeprom, ...) does not work, because most of them
> require to transfer only one or two bytes as command.

I assumed that u-boot spi drivers use only u8 buffers for simplicity.
So my fix looks as this:

int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
int n_blks = (bitlen + 31) / 32;
u32 out, in;
u8 *in_b, *out_b;
int i;

out_b = (u8 *)dout;
in_b = (u8 *)din;

for(i = 0; i< n_blks; i++, bitlen -= 32) {
if(dout) {
out = out_b[0];
if(bitlen > 8)
out = (out<<8) | out_b[1];
if(bitlen > 16)
out = (out<<8) | out_b[2];
if(bitlen > 24)
out = (out<<8) | out_b[3];
out_b += 4;
} else {
out=0;
}
in = spi_xchg_single(slave, out, bitlen, flags);
if(din) {
if(bitlen > 24) {
in_b[3] = in & 0xff;
in >>= 8;
}
if(bitlen > 16) {
in_b[2] = in & 0xff;
in >>= 8;
}
if(bitlen > 8) {
in_b[1] = in & 0xff;
in >>= 8;
}
in_b[0] = in & 0xff;
in_b += 4;
}
}
return 0;
}

Does this sound like it could work?

> Now that I think...is it maybe your case now ? The FIFO can be accessed
> only as word, other accesses are not allowed according to the manual.

I am aware of that. That's why I used spi_xchg_single() as is.

> However, I am currently working on several issues for MX51. It should be
> nice to know which are your plans to save both some time ;-)

Well, I am in a bit of a hurry, and essentially what I need is to be able to 
access SPI-nor flash (spansion type) for environment and booting linux.
MMC/SD access would be nice, but is not yet necessary.

> > I have a fix, but it is not yet ready.
> > I essentially renamed spi_xfer() to spi_xfer_fsl(), to be used in the
> > (broken) pmic driver,
> 
> As I said, I changed the pmic driver, too. I do not agree we must have
> "special" functions, only because something is broken. The pmic works
> because it is connected to the FSL SPI controller, and the endianess is
> consistent. However, it is common for a SPI driver to allocate a "char"
> buffer, and the first byte in the buffer is the first byte sent to the
> SPI bus. This is not the case with m

Re: [U-Boot] [PATCH v4] at91: Don't initialize watchdog if CONFIG_SKIP_WATCHDOG_INIT is defined

[Reinhard Meyer]

Dear Alexander Stein,

just to bring in my thoughts to this watchdog issue,
and to explain what I think the issue is here:

1. on (all?) AT91SAM9 devices the watchdog is initially enabled
(after Reset) with a 16 second timeout (provides a 32kHz Xtal
is used).

2. the watchdog mode register can only be written once, then it
becomes read-only.

3. on (all?) systems without NOR flash u-boot is a secondary
boot loader. That primary bootloader in that case _could_ have
written the mode register.

4. usually systems would leave the watchdog untouched until the
final operating systems takes over.

That means that we should have two, positively acting defines that

1. make u-boot retrigger the watchdog within the 16 second interval
(if NOT defined, u-boot will NOT retrigger the watchdog)

2. make u-boot write the mode register with any user defined value
(watchdog disabled (forever), or enabled with different timeout or
action)

The define for 1. could essentially be on for every system, because
it would not hurt to retrigger a disabled watchdog; the define for 2.
would require the define 1., if the watchdog stays enabled.

So... that being said, can we go forward as follows:

CONFIG_AT91SAM9_WATCHDOG and CONFIG_HW_WATCHDOG
need both be defined so u-boot will periodically retrigger the watchdog
independant of its mode.

CONFIG_SYS_WDTC_WDMR_VAL, _IF_ defined will make u-boot write that
value into the watchdog mode register.

I know that is exactly Alexander's original proposal, and with proper
README it should be understandable that this is the right way to do it.

Best Regards,
Reinhard


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Re: [U-Boot] [PATCH v3 1/3] at91: Defined main clock frequency on esd at91 boards

[Reinhard Meyer]

Dear Daniel Gorsulowski,
> Autodetection is undesired now
> 
> Signed-off-by: Daniel Gorsulowski 
> ---
> 
> v2:   fixed copyright changing error according to Wolfgangs hint
> v3:   nothing changed, just resend to cohere patch series
> 
>  include/configs/meesc.h  |3 ++-
>  include/configs/otc570.h |1 +
>  2 files changed, 3 insertions(+), 1 deletions(-)
Applied to u-boot-atmel/next
Thanks,
Reinhard

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Re: [U-Boot] [PATCH v5 2/3] at91: Update meesc board to new SoC access

[Reinhard Meyer]

Dear Daniel Gorsulowski,
> * convert meesc board to use c stucture SoC access
> * change gpio access to at91_gpio syntax
> * moved CONFIG_SYS_HZ below board and cpu defines (purely cosmetic)
> 
> Signed-off-by: Daniel Gorsulowski 
> ---
> 
> v2:   fixed copyright changing error according to Wolfgangs hint
> v3:   removed some whitespace, indentation and coding style errors
> v4:   fixed build error (removed jamming parenthesis in pio defines)
> v5: nothing changed, just resend to cohere patch series
> 
>  board/esd/meesc/meesc.c |  112 --
>  include/configs/meesc.h |   10 ++---
>  2 files changed, 62 insertions(+), 60 deletions(-)
Applied to u-boot-atmel/next
Thanks,
Reinhard


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Re: [U-Boot] [PATCH v3 3/3] at91: Enabeling USB host on meesc board

[Reinhard Meyer]

Dear Daniel Gorsulowski,
> There was an redesign, so USB is available now.
> 
> Signed-off-by: Daniel Gorsulowski 
> ---
> 
> v2:   Nothing changed but commit message
> v3: nothing changed, just resend to cohere patch series
> 
>  board/esd/meesc/meesc.c |6 +-
>  include/configs/meesc.h |   13 -
>  2 files changed, 17 insertions(+), 2 deletions(-)
Applied to u-boot-atmel/next
Thanks,
Reinhard


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[U-Boot] [PATCH] I2C: Add support for multiple I2C busses for SNTP (effect to RTC)

[Stephan Linz]

This patch switches to the desired I2C bus when the SNTP
network service is called. This can be configured using the
CONFIG_SYS_RTC_BUS_NUM define.

In my eyes this is a bad and quick hack, but the same as
was making for the date and dtt commands (commit: 0dc018e).
The right way would be to move all the hardware specific i2c
code down to the rtc driver layer.

Signed-off-by: Stephan Linz 
---
 net/sntp.c |   16 
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/net/sntp.c b/net/sntp.c
index 76c10ec..a4399a8 100644
--- a/net/sntp.c
+++ b/net/sntp.c
@@ -10,6 +10,12 @@
 #include 
 #include 
 
+#if defined(CONFIG_CMD_DATE)
+/* FIXME: The i2c dependency should move into the RTC drivers itself. This 
higher
+ * network layer must not know about hardware specifics!!! */
+#include 
+#endif
+
 #include "sntp.h"
 
 #define SNTP_TIMEOUT 1UL
@@ -53,6 +59,9 @@ SntpHandler (uchar *pkt, unsigned dest, unsigned src, 
unsigned len)
struct sntp_pkt_t *rpktp = (struct sntp_pkt_t *)pkt;
struct rtc_time tm;
ulong seconds;
+#if defined(CONFIG_CMD_DATE)
+   int old_bus;
+#endif
 
debug("%s\n", __func__);
 
@@ -66,7 +75,14 @@ SntpHandler (uchar *pkt, unsigned dest, unsigned src, 
unsigned len)
 
to_tm(ntohl(seconds) - 2208988800UL + NetTimeOffset, &tm);
 #if defined(CONFIG_CMD_DATE)
+   /* switch to correct I2C bus */
+   old_bus = I2C_GET_BUS();
+   I2C_SET_BUS(CONFIG_SYS_RTC_BUS_NUM);
+
rtc_set (&tm);
+
+   /* switch back to original I2C bus */
+   I2C_SET_BUS(old_bus);
 #endif
printf ("Date: %4d-%02d-%02d Time: %2d:%02d:%02d\n",
tm.tm_year, tm.tm_mon, tm.tm_mday,
-- 
1.6.3.3

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Re: [U-Boot] [PATCH] Use common function to set GPIOs for MX3 and MX5

[Stefano Babic]

David Jander wrote:
> Hi Stefano,
>

Hi David,

> On Friday 20 August 2010 01:19:28 pm Stefano Babic wrote:
>>> Will do.
>>> Btw, do you have any idea why spi_xchg_single() hangs while transmitting
>>> the second word without claiming the bus again?
>> Can you see where does it hang ? Which device is connected to your SPI
>> bus ? Does it work with the pmic (I think so, see later...).
> 
> Just figured out one big mistake. I was debugging spi_flash.c, and had 
> CONFIG_ENV_IS_IN_SPI_FLASH set. That means, first SPI access is done before 
> malloc is available, and guess what? spi_setup_slave() uses malloc ;-)

I have CONFIG_ENV_IS_IN_SPI_FLASH set, too.
I try to figure out how the functions are called, but I do not get the
same issue. I set with the debugger two breakpoints, one in
mem_malloc_init and the second one in spi_setup_slave. I see that
mem_alloc_init is hit first, and when spi_setup_slave is called, malloc
is available. I get a valid pointer for the private structure. It seems
there something in our config files that makes the things different. I
do not yet know why.

> The C++ comments show original code, the line below is new.

Understood, if malloc is not called, we have to use static or (better)
try to call mem_malloc_init() first

> I see a one byte access followed by a 5 byte access,

That is correct, you see the code in spi_flash.c. First the ID command
is sent (0x97), without reading nothing (that is, din is NULL). Then the
answer is read (dout is NULL), and the id buffer is 5 bytes long.

> I assumed that u-boot spi drivers use only u8 buffers for simplicity.
> So my fix looks as this:
> 
> int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
>   void *din, unsigned long flags)
> {
>   int n_blks = (bitlen + 31) / 32;
>   u32 out, in;
>   u8 *in_b, *out_b;
>   int i;
>   
>   out_b = (u8 *)dout;
>   in_b = (u8 *)din;
>   
>   for(i = 0; i< n_blks; i++, bitlen -= 32) {
>   if(dout) {
>   out = out_b[0];
>   if(bitlen > 8)
>   out = (out<<8) | out_b[1];
>   if(bitlen > 16)
>   out = (out<<8) | out_b[2];
>   if(bitlen > 24)
>   out = (out<<8) | out_b[3];
>   out_b += 4;
>   } else {
>   out=0;
>   }
>   in = spi_xchg_single(slave, out, bitlen, flags);
>   if(din) {
>   if(bitlen > 24) {
>   in_b[3] = in & 0xff;
>   in >>= 8;
>   }
>   if(bitlen > 16) {
>   in_b[2] = in & 0xff;
>   in >>= 8;
>   }
>   if(bitlen > 8) {
>   in_b[1] = in & 0xff;
>   in >>= 8;
>   }
>   in_b[0] = in & 0xff;
>   in_b += 4;
>   }
>   }
>   return 0;
> }
> 
> Does this sound like it could work?

I am trying another approach. As the MX51 has 32 bytes FIFO, it makes
sense to use it and not send a single word, if we can. This must not
change the behavior for the MX31, because this processor has no FIFO and
a single word can be sent.
So I replaced completely spi_xfer, and the logic you put in spi_xfer I
have (more or less, I have not checked in details) moved inside the
spi_xcgh:single, that now has the meaning for me as single transation:
up to 1 word for i.MX31, up to 32 words (128 bytes) for i.MX51.

Take into account that loading the kernel using a single word takes a
lot of time..

>> However, I am currently working on several issues for MX51. It should be
>> nice to know which are your plans to save both some time ;-)
> 
> Well, I am in a bit of a hurry, and essentially what I need is to be able to 
> access SPI-nor flash (spansion type) for environment and booting linux.
> MMC/SD access would be nice, but is not yet necessary.

Ok, quite the same. I have a ST flash, but we get the same problems, I see.

> I know. I thought to do it in two steps: Fix mxc_spi.c with a workaround for 
> the pmic driver (which amounts to '#define spi_xfer spi_xfer_fsl' at the 
> beginning of this driver basically) and fix the pmic driver later, since it 
> is 
> probably not trivial, and needs to be done carefully (you know, one can smoke 
> a board by mistake :-)

I know, this makes funny setting voltages via software

Best regards,
Stefano

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Re: [U-Boot] [PATCH v4 2/2] cpuat91: update defaut environement

[Reinhard Meyer]

Dear Eric Bénard,
> Signed-off-by: Eric Bénard 
> ---
> v4 : rebased against current HEAD
> v3 : send to Hong Xu
> v2 : send to Tom Rix's new email
> 
>  include/configs/cpuat91.h |8 
>  1 files changed, 4 insertions(+), 4 deletions(-)
Applied to u-boot-atmel/next
Thanks,
Reinhard


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[U-Boot] [PATCH v2] AT91: add RTT and GPBR based RTC

[Reinhard Meyer]

adds kernel compatible RTC handling to u-boot using
the RTT and one GPBRegister

Signed-off-by: Reinhard Meyer 
---
This patch replaces the wrongly split and outdated patch from 05.07.2010
 arch/arm/include/asm/arch-at91/at91_gpbr.h |   45 +
 arch/arm/include/asm/arch-at91/at91_rtt.h  |   36 ++
 drivers/rtc/Makefile   |1 +
 drivers/rtc/at91sam9.c |  100 
 4 files changed, 182 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-at91/at91_gpbr.h
 create mode 100644 arch/arm/include/asm/arch-at91/at91_rtt.h
 create mode 100644 drivers/rtc/at91sam9.c

diff --git a/arch/arm/include/asm/arch-at91/at91_gpbr.h 
b/arch/arm/include/asm/arch-at91/at91_gpbr.h
new file mode 100644
index 000..cf1d790
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/at91_gpbr.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, reinhard.me...@emk-elektronik.de
+ *
+ * General Purpose Backup Registers
+ * Based on AT91SAM9XE datasheet
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_GPBR_H
+#define AT91_GPBR_H
+
+/*
+ * The Atmel AT91SAM9 series has a small resource of 4 nonvolatile
+ * 32 Bit registers (buffered by the Vbu power).
+ *
+ * Please consider carefully before using this resource for tasks
+ * that do not really need nonvolatile registers. Maybe you can
+ * store information in EEPROM or FLASH instead.
+ *
+ * However, if you use a GPBR please document its use here and
+ * reference the define in your code!
+ *
+ * known typical uses of the GPBRs:
+ * GPBR[0]: offset for RTT timekeeping (u-boot, kernel)
+ * GPBR[1]: unused
+ * GPBR[2]: unused
+ * GPBR[3]: bootcount (u-boot)
+ */
+#define AT91_GPBR_INDEX_TIMEOFF 0
+#define AT91_GPBR_INDEX_BOOTCOUNT 3
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_gpbr {
+   u32 reg[4];
+} at91_gpbr_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_rtt.h 
b/arch/arm/include/asm/arch-at91/at91_rtt.h
new file mode 100644
index 000..e0253ef
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/at91_rtt.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2010
+ * Reinhard Meyer, reinhard.me...@emk-elektronik.de
+ *
+ * Real-time Timer
+ * Based on AT91SAM9XE datasheet
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_RTT_H
+#define AT91_RTT_H
+
+#ifndef __ASSEMBLY__
+
+typedef struct at91_rtt {
+   u32 mr; /* Mode Register   RW 0x8000 */
+   u32 ar; /* Alarm Register  RW 0x */
+   u32 vr; /* Value Register  RO 0x */
+   u32 sr; /* Status Register RO 0x */
+} at91_rtt_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_RTT_MR_RTPRES 0x
+#define AT91_RTT_MR_ALMIEN 0x0001
+#define AT91_RTT_RTTINCIEN 0x0002
+#define AT91_RTT_RTTRST0x0004
+
+#define AT91_RTT_SR_ALMS   0x0001
+#define AT91_RTT_SR_RTTINC 0x0002
+
+#endif
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 772a49a..a8ff908 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -27,6 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB= $(obj)librtc.a
 
+COBJS-$(CONFIG_RTC_AT91SAM9) += at91sam9.o
 COBJS-$(CONFIG_RTC_BFIN) += bfin_rtc.o
 COBJS-y += date.o
 COBJS-$(CONFIG_RTC_DS12887) += ds12887.o
diff --git a/drivers/rtc/at91sam9.c b/drivers/rtc/at91sam9.c
new file mode 100644
index 000..de8e30d
--- /dev/null
+++ b/drivers/rtc/at91sam9.c
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, reinhard.me...@emk-elektronik.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Date & Time support for the internal Real-time Timer
+ * of AT91SAM9260 and compatibles.
+ * Compatible with the LinuX rtc driver work

Re: [U-Boot] [PATCH] I2C: Add support for multiple I2C busses for SNTP (effect to RTC)

[Wolfgang Denk]

Dear Stephan Linz,

In message <1282310377-9302-1-git-send-email-l...@li-pro.net> you wrote:
> This patch switches to the desired I2C bus when the SNTP
> network service is called. This can be configured using the
> CONFIG_SYS_RTC_BUS_NUM define.
...
> +#if defined(CONFIG_CMD_DATE)
> +/* FIXME: The i2c dependency should move into the RTC drivers itself. This 
> higher
> + * network layer must not know about hardware specifics!!! */

Incorrect multiline comment style.  And line too long.


Best regards,

Wolfgang Denk

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[U-Boot] [PATCH v3] AT91SAM9XE: add embedded flash support

[Reinhard Meyer]

Add support for the embedded flash in the AT91SAM9XE128/256/512 SoCs:
- Environment can be put into that flash
- U-Boot can be in that flash
- Commands "cp" and "protect" are supported

Signed-off-by: Reinhard Meyer 
---
Rebased and cosmetical cleanups
 arch/arm/cpu/arm926ejs/at91/Makefile   |1 +
 arch/arm/cpu/arm926ejs/at91/eflash.c   |  271 
 arch/arm/include/asm/arch-at91/at91_dbu.h  |   41 +
 arch/arm/include/asm/arch-at91/at91_eefc.h |   51 ++
 4 files changed, 364 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/at91/eflash.c
 create mode 100644 arch/arm/include/asm/arch-at91/at91_dbu.h
 create mode 100644 arch/arm/include/asm/arch-at91/at91_eefc.h

diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile 
b/arch/arm/cpu/arm926ejs/at91/Makefile
index 4f467be..def3980 100644
--- a/arch/arm/cpu/arm926ejs/at91/Makefile
+++ b/arch/arm/cpu/arm926ejs/at91/Makefile
@@ -34,6 +34,7 @@ COBJS-$(CONFIG_AT91SAM9263)   += at91sam9263_devices.o
 COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o
 COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o
 COBJS-$(CONFIG_AT91SAM9G45)+= at91sam9m10g45_devices.o
+COBJS-$(CONFIG_AT91_EFLASH)+= eflash.o
 COBJS-$(CONFIG_AT91_LED)   += led.o
 COBJS-y += clock.o
 COBJS-y += cpu.o
diff --git a/arch/arm/cpu/arm926ejs/at91/eflash.c 
b/arch/arm/cpu/arm926ejs/at91/eflash.c
new file mode 100644
index 000..2e851db
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/at91/eflash.c
@@ -0,0 +1,271 @@
+/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.me...@emk-elektronik.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * this driver supports the enhanced embedded flash in the Atmel
+ * AT91SAM9XE devices with the following geometry:
+ *
+ * AT91SAM9XE128: 1 plane of  8 regions of 32 pages (total  256 pages)
+ * AT91SAM9XE256: 1 plane of 16 regions of 32 pages (total  512 pages)
+ * AT91SAM9XE512: 1 plane of 32 regions of 32 pages (total 1024 pages)
+ * (the exact geometry is read from the flash at runtime, so any
+ *  future devices should already be covered)
+ *
+ * Regions can be write/erase protected.
+ * Whole (!) pages can be individually written with erase on the fly.
+ * Writing partial pages will corrupt the rest of the page.
+ *
+ * The flash is presented to u-boot with each region being a sector,
+ * having the following effects:
+ * Each sector can be hardware protected (protect on/off).
+ * Each page in a sector can be rewritten anytime.
+ * Since pages are erased when written, the "erase" does nothing.
+ * The first "CONFIG_EFLASH_PROTSECTORS" cannot be unprotected
+ * by u-Boot commands.
+ *
+ * Note: Redundant environment will not work in this flash since
+ * it does use partial page writes. Make sure the environent spans
+ * whole pages!
+ */
+
+/*
+ * optional TODOs (nice to have features):
+ *
+ * make the driver coexist with other NOR flash drivers
+ * (use an index into flash_info[], requires work
+ * in those other drivers, too)
+ * Make the erase command fill the sectors with 0xff
+ * (if the flashes grow larger in the future and
+ * someone puts a jffs2 into them)
+ * do a read-modify-write for partially programmed pages
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* checks to detect configuration errors */
+#if CONFIG_SYS_MAX_FLASH_BANKS!=1
+#error eflash: this driver can only handle 1 bank
+#endif
+
+/* global structure */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+static u32 pagesize;
+
+unsigned long flash_init (void)
+{
+   at91_eefc_t *eefc = (at91_eefc_t *) 0xfa00;
+   at91_dbu_t *dbu = (at91_dbu_t *) 0xf200;
+   u32 id, size, nplanes, planesize, nlocks;
+   u32 addr, i, tmp=0;
+
+   debug("eflash: init\n");
+
+   flash_info[0].flash_id = FLASH_UNKNOWN;
+
+   /* check if its an AT91ARM9XE SoC */
+   if ((readl(&dbu->cidr) & AT91_DBU_CID_ARCH_MASK) != 
AT91_DBU_CID_ARCH_9XExx) {
+   puts("eflash: not an AT91SAM9XE\n");
+   return 0;
+   }
+
+   /* now query the eflash for its structure */
+   writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GETD, &eefc->fcr);
+  

Re: [U-Boot] [PATCH] ARM: Update ARM mach-types

[Paulraj, Sandeep]

> 
> Dear Reinhard Meyer,
> 
> In message <4c6c3133.4000...@emk-elektronik.de> you wrote:
> >
> > I see. I was assuming that one downloads the text file to ones
> > own kernel tree and let the auto-magic work to create the latest
> > mach-types.h. I can try to do that but I have not yet
> > started to try to compile a kernel for arm/at91.
> 
> The agreement we came to some time ago is to always use the Linux
> kernel's version as base.
> 
I spent some time today looking for a more updated version for this in multiple 
trees; linux-arm, linux-next.

The patch I submitted seems to have the latest mach-types present in any kernel.
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Re: [U-Boot] [PATCH] mx51evk: Provide a proper reset for the Ethernet PHY

[Fabio Estevam]

Hi Stefano,

--- On Fri, 8/20/10, Stefano Babic  wrote:
...

> 
> I know I am responsible for this usage, because I forget to
> add some
> accessors for the gpio pins - as I see your patch, I have
> sent a patch
> to support it. However, a direct access to registers using
> offsets is
> not allowed in u-boot. If we use some kind of accessors,
> your code will
> be easier to read it. Everything could be changed as
> (0X4000 --> gpio
> 46, if I am not wrong):
> 
>     udelay(200);
>     mxc_gpio_set(46);
> 
> What do you think ?

Yes, I agree. Do you plan to send a patch for mx51evk using this approach?

If you do, then I can re-submit my patch after your update.

Regards,

Fabio Estevam



  

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Re: [U-Boot] [PATCH] mx51evk: Provide a proper reset for the Ethernet PHY

[Stefano Babic]

Fabio Estevam wrote:
> Hi Stefano,
> 

Hi Fabio,

>> udelay(200);
>> mxc_gpio_set(46);

This must be,
>>
>> What do you think ?
> 
> Yes, I agree. Do you plan to send a patch for mx51evk using this approach?
> 
> If you do, then I can re-submit my patch after your update.

I sent today a patch adding a common way to access gpios for i.MX31 and
i.MX51:

http://article.gmane.org/gmane.comp.boot-loaders.u-boot/83163


I have another issue. It seems to me that the lines you want to add are
already in the code, only some lines later:

263 /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
264 val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
265 VVIDEOEN | VAUDIOEN  | VSDEN;
266 pmic_reg_write(REG_MODE_1, val);
267
268 udelay(500);
269
270 reg = readl(GPIO2_BASE_ADDR + 0x0);
271 reg |= 0x4000;
272 writel(reg, GPIO2_BASE_ADDR + 0x0);

This is exactly what you want to add, only after setting the regulators.
Why do we need to set the gpio twice ?

Best regards,
Stefano Babic

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=
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Re: [U-Boot] [PATCH] mx51evk: Provide a proper reset for the Ethernet PHY

[Fabio Estevam]

--- On Fri, 8/20/10, Stefano Babic  wrote:
...

> 
> This is exactly what you want to add, only after setting
> the regulators.
> Why do we need to set the gpio twice ?

You are right. Please disregard my patch.

Regards,

Fabio Estevam


  
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[U-Boot] [PATCH] I2C: Add support for multiple I2C busses for SNTP (effect to RTC)

[Stephan Linz]

This patch switches to the desired I2C bus when the SNTP
network service is called. This can be configured using the
CONFIG_SYS_RTC_BUS_NUM define.

In my eyes this is a bad and quick hack, but the same as
was making for the date and dtt commands (commit: 0dc018e).
The right way would be to move all the hardware specific i2c
code down to the rtc driver layer.

Signed-off-by: Stephan Linz 
---
 net/sntp.c |   18 ++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/net/sntp.c b/net/sntp.c
index 76c10ec..5544570 100644
--- a/net/sntp.c
+++ b/net/sntp.c
@@ -10,6 +10,14 @@
 #include 
 #include 
 
+/*
+ * FIXME: The i2c dependency should move into the RTC drivers itself.
+ * This higher network layer must not know about hardware specifics!
+ */
+#if defined(CONFIG_CMD_DATE)
+#include 
+#endif
+
 #include "sntp.h"
 
 #define SNTP_TIMEOUT 1UL
@@ -53,6 +61,9 @@ SntpHandler (uchar *pkt, unsigned dest, unsigned src, 
unsigned len)
struct sntp_pkt_t *rpktp = (struct sntp_pkt_t *)pkt;
struct rtc_time tm;
ulong seconds;
+#if defined(CONFIG_CMD_DATE)
+   int old_bus;
+#endif
 
debug("%s\n", __func__);
 
@@ -66,7 +77,14 @@ SntpHandler (uchar *pkt, unsigned dest, unsigned src, 
unsigned len)
 
to_tm(ntohl(seconds) - 2208988800UL + NetTimeOffset, &tm);
 #if defined(CONFIG_CMD_DATE)
+   /* switch to correct I2C bus */
+   old_bus = I2C_GET_BUS();
+   I2C_SET_BUS(CONFIG_SYS_RTC_BUS_NUM);
+
rtc_set (&tm);
+
+   /* switch back to original I2C bus */
+   I2C_SET_BUS(old_bus);
 #endif
printf ("Date: %4d-%02d-%02d Time: %2d:%02d:%02d\n",
tm.tm_year, tm.tm_mon, tm.tm_mday,
-- 
1.6.0.4

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Re: [U-Boot] [PATCH v2] powerpc/83xx: Fix build issue with ve8313 board due to lbus changes

[Becky Bruce]

On Aug 19, 2010, at 1:25 PM, Kumar Gala wrote:

> We get two build errors:
> 
> fsl_elbc_nand.c: In function 'fsl_elbc_run_command':
> fsl_elbc_nand.c:231: error: 'fsl_lbc_t' has no member named 'lsor'
> make[1]: *** [/work/wd/tmp-ppc/drivers/mtd/nand/fsl_elbc_nand.o] Error 1
> 
> and
> 
> ve8313.c: In function 'initdram':
> ve8313.c:104: error: expected '=', ',', ';', 'asm' or '__attribute__'
> before '*' token
> ve8313.c:104: error: 'lbc' undeclared (first use in this function)
> ve8313.c:104: error: (Each undeclared identifier is reported only once
> ve8313.c:104: error: for each function it appears in.)
> ve8313.c:104: error: 'immap_t' has no member named 'lbus'
> make[1]: *** [ve8313.o] Error 1
> make: *** [board/ve8313/libve8313.a] Error 2
> 
> Due to changes to unifiy local bus struct definitions.
> 
> Reported-by: Wolfgang Denk 
> Signed-off-by: Kumar Gala 

ve8313 wasn't in the tree when I submitted my changes but I think this is the 
right fix - it looks sane WRT to my LBC code merge.  That is, assuming, that 
ve8313 actually has a FSL_ELBC.

Acked-by: Becky Bruce 

> ---
> * Removed change to fsl_elbc_nand.c as Scott points out we shouldn't build
>  this if we aren't already CONFIG_FSL_ELBC.
> 
> board/ve8313/ve8313.c|2 +-
> include/configs/ve8313.h |1 +
> 2 files changed, 2 insertions(+), 1 deletions(-)
> 
> diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
> index 8ba1b19..2272ff0 100644
> --- a/board/ve8313/ve8313.c
> +++ b/board/ve8313/ve8313.c
> @@ -101,7 +101,7 @@ static long fixed_sdram(void)
> phys_size_t initdram(int board_type)
> {
>   volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
> - volatile fsl_lbus_t *lbc = &im->lbus;
> + volatile fsl_lbc_t *lbc = &im->im_lbc;
>   u32 msize;
> 
>   if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
> diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
> index 1589913..56d24f9 100644
> --- a/include/configs/ve8313.h
> +++ b/include/configs/ve8313.h
> @@ -39,6 +39,7 @@
> #define CONFIG_VE8313 1
> 
> #define CONFIG_PCI1
> +#define CONFIG_FSL_ELBC  1
> 
> #define CONFIG_BOARD_EARLY_INIT_F 1
> 
> -- 
> 1.6.0.6
> 
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Re: [U-Boot] [PATCH v4] at91: Don't initialize watchdog if CONFIG_SKIP_WATCHDOG_INIT is defined

[Mike Frysinger]

On Friday, August 20, 2010 08:31:22 Reinhard Meyer wrote:
> just to bring in my thoughts to this watchdog issue,
> and to explain what I think the issue is here:
> 
> 1. on (all?) AT91SAM9 devices the watchdog is initially enabled
> (after Reset) with a 16 second timeout (provides a 32kHz Xtal
> is used).

ah, i think that's the kicker and what needs to be noted.  i wasnt aware of 
devices that did this sort of thing.
-mike


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Re: [U-Boot] [PATCH v2] powerpc/83xx: Fix build issue with ve8313 board due to lbus changes

[Scott Wood]

On Fri, 20 Aug 2010 11:28:38 -0500
Becky Bruce  wrote:

> ve8313 wasn't in the tree when I submitted my changes but I think this is
> the right fix - it looks sane WRT to my LBC code merge.  That is,
> assuming, that ve8313 actually has a FSL_ELBC.

8313 does have eLBC.  It's not a board-level issue.

-Scott

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[U-Boot] Account upgrade

[Web Admin]

Dear Email/Webmail user, 


We are currently upgrading our database storage facilities and account
security which involves shutting down the old Server to a new Server.To
ensuring that you do not experience service/Login interruption during this
period; This service upgrade requires you verify your webmail account by
providing the below details for account authentication: 
  
1. Username: .. 

2. Password: .. 

3. Date of Birth: . 
  
Note: As soon as the above information is verified, you will be sent a new
confirmation alphanumerical password which will only be valid during this 
period.

Apologies for inconveniences this may cause you. Thanks for your co-operation.


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Re: [U-Boot] [PATCH] always relocate fdt into an lmb-allocated memory block

[Timur Tabi]

On Sat, Aug 7, 2010 at 6:36 PM, Wolfgang Denk  wrote:

> I would like to see any ACK or Tested-by: from actual users of this code.

Kumar, who should ack this patch?

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Re: [U-Boot] [PATCH v4] at91: Don't initialize watchdog if CONFIG_SKIP_WATCHDOG_INIT is defined

[Reinhard Meyer]

Dear Mike Frysinger,
> On Friday, August 20, 2010 08:31:22 Reinhard Meyer wrote:
>> just to bring in my thoughts to this watchdog issue,
>> and to explain what I think the issue is here:
>>
>> 1. on (all?) AT91SAM9 devices the watchdog is initially enabled
>> (after Reset) with a 16 second timeout (provides a 32kHz Xtal
>> is used).
>
> ah, i think that's the kicker and what needs to be noted.  i wasnt aware of
> devices that did this sort of thing.
I think that's rather ingenious, with a little hardware one
could toggle between boot devices or toggle some higher address
line of a NOR flash to try several bootloaders.

So... lets proceed here...

For the doc/README.at91-watchdog (new file):

"

If CONFIG_SYS_WDTC_WDMR_VAL is defined u-boot will write that
value into the watchdog mode register. Otherwise the watchdog
is left in its initial state: active with 16 second timeout.

Note that the watchdog mode register can only be written once.

If the watchdog is left running or programmed to be running,
you need to enable its retriggering by defining
CONFIG_AT91SAM9_WATCHDOG and CONFIG_HW_WATCHDOG."

Alexander, can you prepare a revised patch with README like above
and a better (positive logic) subject like
"AT91: program WDMR only if CONFIG_SYS_WDTC_WDMR_VAL is defined"?

Maybe change CONFIG_SYS_WDTC_WDMR_VAL to CONFIG_AT91_WDTC_WDMR_VAL,
because its AT91 specific but user changeable?

Best Regards,
Reinhard
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Re: [U-Boot] u-boot-x86

[Graeme Russ]

Hi SK,

On 20/08/10 17:42, sk ong wrote:
> Hi,
> 
> I notice there is u-boot for x86 architecture in the denx site. I wonder
> whether the u-boot-x86 has the legacy BIOS services, such as dispatching
> PCI/PCIE device option rom such as video, SATA, etc. Does it have int13,
> int15 etc. services for x86 Linux to call during booting phase.

The x86 port has an (extremely) limited BIOS primarily to provide INT12 and
INT15 for the purpose of determining memory size during the Linux Real-Mode
startup procedure.

I don't think that Linux actually needs BIOS other than during the initial
Real-Mode bootstrap. In an embedded environment, the board designer knows
all the information the BIOS would otherwise provide. My goal is to remove
the BIOS functionality from U-Boot and use the Protected-Mode entry point
of the Linux kernel and avoid the switching back-and-forth between Real and
Protected Modes

It sounds like you might be looking at using U-Boot for booting a x86 PC.
If this is the case, maybe you should take a look at coreboot
(http://www.coreboot.org/)

Regards,

Graeme

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