[U-Boot] onenand write fail with on smdkc100

[Naveen Krishna Ch]

Hi All,

das-u-boot $make smdc100_config
das-u-boot $make

Brought u-boot prompt on minicom using Trace32

SMDKC100 # tftp c0008000 uboot.bin

SMDKC100 # onenand erase 0 4

SMDKC100 # onenand write c0008000 0 214c0
OneNAND write: device 0 offset 0, size 214c0  addr c0008000...  0 bytes
written: ERROR

SMDKC100 # onenand write c0008000 0 4

OneNAND write: device 0 offset 0, size 4  addr c0008000...

What could be the problem, Am i missing anything ?

-- 
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(: Naveen Krishna Ch :)
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Re: [U-Boot] onenand write fail with on smdkc100

[Naveen Krishna Ch]

Sorry My Bad.
Does not belong here.

2010/1/12 Naveen Krishna Ch 

> Hi All,
>
> das-u-boot $make smdc100_config
> das-u-boot $make
>
> Brought u-boot prompt on minicom using Trace32
>
> SMDKC100 # tftp c0008000 uboot.bin
>
> SMDKC100 # onenand erase 0 4
>
> SMDKC100 # onenand write c0008000 0 214c0
> OneNAND write: device 0 offset 0, size 214c0  addr c0008000...  0 bytes
> written: ERROR
>
> SMDKC100 # onenand write c0008000 0 4
>
> OneNAND write: device 0 offset 0, size 4  addr c0008000...
>
> What could be the problem, Am i missing anything ?
>
> --
> Shine bright,
> (: Naveen Krishna Ch :)
>



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[U-Boot] Ethernet doesn't work on PXA320

[Dennis Semakin]

Hello,

When I try to ping some host from my board, then U-boot hang.
It's going on when I send EECS signal to MEMR register.
Is there hardware issue?

Thanks
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[U-Boot] [U-boot] [PATCH] Support for the Calao USB-A9260/USB-A9G20 boards

[Gregory Hermant]

The Calao USB-A9260 and USB-9G20 boards are manufactured and sold by Calao 
Systems
. They are built around an AT91SAM9260 ARM SoC
running at 180MHz and an AT91SAM9G20 ARM SoC running at 400MHz respectively.
They feature an Ethernet port, 64Mo of SDRAM, 256Mo of NAND flash, two USB host 
ports,
and an USB device port. They also feature a FTDI2232 converter which provides 
the ability
to use the DBGU serial port & the JTAG port over a USB interface.

Signed-off-by: Gregory Hermant 
---
 MAINTAINERS   |5 +
 MAKEALL   |2 +
 Makefile  |5 +
 board/calao/usb_a9260/Makefile|   55 ++
 board/calao/usb_a9260/config.mk   |1 +
 board/calao/usb_a9260/spi.c   |   50 ++
 board/calao/usb_a9260/usb_a9260.c |  197 +
 include/configs/usb_a9260.h   |  179 +
 8 files changed, 494 insertions(+), 0 deletions(-)
 create mode 100644 board/calao/usb_a9260/Makefile
 create mode 100644 board/calao/usb_a9260/config.mk
 create mode 100644 board/calao/usb_a9260/spi.c
 create mode 100644 board/calao/usb_a9260/usb_a9260.c
 create mode 100644 include/configs/usb_a9260.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 9734b1d..f47acb6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -588,6 +588,11 @@ Kshitij Gupta 
omap1510inn ARM925T
omap1610inn ARM926EJS
 
+Gregory Hermant 
+
+   usb_a9260   ARM926EJS (AT91SAM9G20 SoC)
+   usb_a9g20   ARM926EJS (AT91SAM9G20 SoC)
+
 Grazvydas Ignotas 
 
omap3_pandora   ARM CORTEX-A8 (OMAP3xx SoC)
diff --git a/MAKEALL b/MAKEALL
index ab1bb6f..b07118d 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -657,6 +657,8 @@ LIST_at91=" \
SBC35_A9G20 \
TNY_A9260   \
TNY_A9G20   \
+   USB_A9260   \
+   USB_A9G20   \
 "
 
 #
diff --git a/Makefile b/Makefile
index ed6156f..c5e66a5 100644
--- a/Makefile
+++ b/Makefile
@@ -2874,6 +2874,11 @@ TNY_A9260_config :   unconfig
@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
@$(MKCONFIG) -a tny_a9260 arm arm926ejs tny_a9260 calao at91
 
+USB_A9G20_config \
+USB_A9260_config   :   unconfig
+   @mkdir -p $(obj)include
+   @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
+   @$(MKCONFIG) -a usb_a9260 arm arm926ejs usb_a9260 calao at91
 
 ## ARM Integrator boards - see doc/README-integrator for more info.
 integratorap_config\
diff --git a/board/calao/usb_a9260/Makefile b/board/calao/usb_a9260/Makefile
new file mode 100644
index 000..c092863
--- /dev/null
+++ b/board/calao/usb_a9260/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop 
+# Lead Tech Design 
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS-y+= usb_a9260.o
+COBJS-$(CONFIG_ATMEL_SPI)  += spi.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+   $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+   rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+   rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/calao/usb_a9260/config.mk b/board/calao/usb_a9260/config.mk
new file mode 100644
index 000..ff2cfd1
--- /dev/null
+++ b/board/calao/usb_a9260/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x23f0
diff --git a/board/calao/usb_a9260/spi.c b/board/calao/usb_a9260/spi.c
new file mode 100644
index 000..689dd28
--- /dev/null
+++ b/board/calao/usb_a9260/spi.c
@@ -0,0 +1,50 @@
+

[U-Boot] Ethernet doesn't work on PXA320

[Dennis Semakin]

Hello,

When I try to ping some host from my board, then U-boot hang.
It's going on when I send EECS signal to MEMR register.
Is there hardware issue?

Thanks
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Re: [U-Boot] U-Boot Crashes with Dumps

[anupbehare]

In my case CONFIG_SYS_MONITOR_LEN is 256KB
and CONFIG_SYS_MONITOR_BASE is 0xfffc
my destaddr is 0x1ffd5000

so gd->reloc_off = destaddr - CONFIG_SYS_MONITOR_BASE;
so gd->reloc_off = 0x20015000
also gd->malloc = 0x1fed1000

After that it continuously restarts with error machine check exception.

Is that mean ram initialization is not done or some thing with reloc_off as  
it is going in -ve.



On 12-Jan-2010 12:56pm, Stefan Roese  wrote:

On Tuesday 12 January 2010 08:02:51 anupbeh...@gmail.com wrote:




> I begin use U-Boot at my custom board based on ppc440x5.







What kind of PPC4xx ist this? PPC440EPx?







> Here is Mem Info that we are using on board:




>




> 16MB Nor flash with base address 0xfc00




> 512MB DDR with base addr 0x




> 256kb ISRAM with base addr 0xc000




>




> TEXT_BASE 0xfffc




>




> Tlb entries for board is:




> tlbentry( 0xff00, SZ_16M, 0xff00, 0, AC_R|AC_X|AC_W) --Flash




> tlbentry( 0xc000, SZ_256K, 0xc000, 0, AC_R|AC_W|AC_X|SA_I)




> --ISRAM




> tlbentry( 0x, SZ_256M, 0x, 0, AC_R|AC_W|AC_X|SA_I|SA_G)




> --DDR




> tlbentry( 0x1000, SZ_256M, 0x1000, 0, AC_R|AC_W|AC_X|SA_I|SA_G)




> --DDR




>




>




> I am trying to get a clean build of U-Boot to run on the PPC440x5 based




> customized board. I have the latest versions U-Boot.



> The system executes through board_init_f( ) without any problems, and  
gets




> into board_init_r( ). The console output is as follows:




>




> 512 MB (ECC is ON, 400 MHz, CL 7)




> Top of RAM usable for U-Boot at: 2000




> Reserving 170k for U-Boot at: 1ffd5000




> Reserving 1040k for malloc() at: 1fed1000




> Reserving 128 Bytes for Board Info at: 1fed0f80




> Reserving 64 Bytes for Global Data at: 1fed0f40




> Stack Pointer at: 1fed0f28




> New Stack Pointer is: 1fed0f28




> relocate addr_sp = 1fed0f28, id = 1fed0f40, addr = 1ffd5000




>




> Now running in RAM - U-Boot at: 1ffd5000




>




> NIP: 1FFD7764 XER:  LR: 1FFD7764 REGS: 1fed0e20 TRAP: 0200 DEAR:




> FFED0F18




> MSR: 00021000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00




>




> GPR00: 1FFD7338 1FED0F10 1FED0F40 1FFD5000 1FFD88E0  




> 1FFD7764




> GPR08: 0600 2098 0030 2FAF07FE  C000B330 20002A00




> 20015000




> GPR16:     48FF2422 0610 2C20




> 




> GPR24:  1FED0F40 1FFD5000 1FED5000 1FED0F80 1FFD5000 20002B10




> 1FED1000




> Call backtrace:




> 1FFD88D8 1FFD76D8 




> machine check







When U-Boot crashes/hangs upon relocation to SDRAM, you most likely have a



problem with your SDRAM configuration. Again, which CPU are you using?  
How is




the SDRAM connected (DIMM or onboard). I suggest you check your SDRAM




controller setup again.







> Here I am trying to use backtrace to debug but system is waiting at




> folloing console o/p.




>




> [r...@u-boot]$ cp ../../11dec_rec/u-boot/backtrace .




> [r...@u-boot]$backtrace System.map 0xdffeb000




> Reading symbols from System.map




> Using Address Offset 0xdffeb000







This link might help:







http://www.denx.de/wiki/DULG/DebuggingUBoot







Especially chapter 10.1.2. Debugging of U-Boot After Relocation.







Cheers,




Stefan







--




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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany




Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de




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Re: [U-Boot] U-Boot Crashes with Dumps

[Stefan Roese]

On Tuesday 12 January 2010 10:09:57 anupbeh...@gmail.com wrote:
> In my case CONFIG_SYS_MONITOR_LEN is 256KB
> and CONFIG_SYS_MONITOR_BASE is 0xfffc
> my destaddr is 0x1ffd5000
> 
> so gd->reloc_off = destaddr - CONFIG_SYS_MONITOR_BASE;
> so gd->reloc_off = 0x20015000
> also gd->malloc = 0x1fed1000
> 
> After that it continuously restarts with error machine check exception.
> 
> Is that mean ram initialization is not done or some thing with reloc_off as
> it is going in -ve.

Again, I strongly suspect problems in your SDRAM configuration. You didn't 
provide any answers to my questions: Why CPU type are you using? Are you using 
a DIMM or soldered SDRAM? Which SDRAM setup code are you using?

Cheers,
Stefan

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Re: [U-Boot] U-Boot Crashes with Dumps

[anupbehare]

I am using PPC440GX and DIMM SDRAM.


On 12-Jan-2010 3:20pm, Stefan Roese  wrote:

On Tuesday 12 January 2010 10:09:57 anupbeh...@gmail.com wrote:




> In my case CONFIG_SYS_MONITOR_LEN is 256KB




> and CONFIG_SYS_MONITOR_BASE is 0xfffc




> my destaddr is 0x1ffd5000




>




> so gd->reloc_off = destaddr - CONFIG_SYS_MONITOR_BASE;




> so gd->reloc_off = 0x20015000




> also gd->malloc = 0x1fed1000




>




> After that it continuously restarts with error machine check exception.




>



> Is that mean ram initialization is not done or some thing with  
reloc_off as




> it is going in -ve.







Again, I strongly suspect problems in your SDRAM configuration. You didn't



provide any answers to my questions: Why CPU type are you using? Are you  
using




a DIMM or soldered SDRAM? Which SDRAM setup code are you using?







Cheers,




Stefan







--




DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel




HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany




Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de




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[U-Boot] [PATCH] qe: fixup the snum for MPC8569 Rev2.0

[Liu Yu]

Since 1.0 and 2.0 use different snum table,
we fixup the snum value according to SPRN_SVR.

Signed-off-by: Liu Yu 
---
 board/freescale/mpc8569mds/mpc8569mds.c |   13 +
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mpc8569mds/mpc8569mds.c 
b/board/freescale/mpc8569mds/mpc8569mds.c
index cdd7813..db8ae5d 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -510,6 +510,18 @@ static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
clrbits_8(&bcsr[17], BCSR17_nUSBEN);
 }
 
+static void fdt_board_fixup_qe_snum(void *blob, bd_t *bd)
+{
+   if (mfspr(SPRN_SVR) == 0x80880010) {
+   /* Rev1.0 uses snum 46 */
+   do_fixup_by_compat_u32(blob, "fsl,qe",
+   "fsl,qe-num-snums", 46, 1);
+   } else {
+   do_fixup_by_compat_u32(blob, "fsl,qe",
+   "fsl,qe-num-snums", 76, 1);
+   }
+}
+
 #ifdef CONFIG_PCIE1
 static struct pci_controller pcie1_hose;
 #endif  /* CONFIG_PCIE1 */
@@ -654,5 +666,6 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_board_fixup_esdhc(blob, bd);
fdt_board_fixup_qe_uart(blob, bd);
fdt_board_fixup_qe_usb(blob, bd);
+   fdt_board_fixup_qe_snum(blob, bd);
 }
 #endif
-- 
1.6.4

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Re: [U-Boot] U-Boot Crashes with Dumps

[Stefan Roese]

On Tuesday 12 January 2010 11:07:13 anupbeh...@gmail.com wrote:
> I am using PPC440GX and DIMM SDRAM.

OK, so you are using the code cpu/ppc4xx/44x_spd_ddr.c to configure the SDRAM 
controller. You should enable DEBUG in this code to see a bit more about the 
configuration.

BTW: I suggest you take a look at the ocotea SDRAM config options set in 
include/configs/ocotea.h. You should for example set CONFIG_PROG_SDRAM_TLB and 
then remove the SDRAM TLB entries from your init.S.
 
Cheers,
Stefan

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[U-Boot] [PATCH] video: Fix console display when splashscreen is used

[Matthias Weisser]

If a splashscreen is used the console scrolling used the
scroll size as needed when a logo was displayd. This
patch sets the scroll size to the whole screen if
a splashscreen is shown.

Signed-off-by: Matthias Weisser 
---
 drivers/video/cfb_console.c |   21 -
 1 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 506337b..2391f31 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -260,7 +260,7 @@ voidconsole_cursor (int state);
 #define CURSOR_ON
 #define CURSOR_OFF
 #define CURSOR_SET video_set_hw_cursor(console_col * VIDEO_FONT_WIDTH, \
- (console_row * VIDEO_FONT_HEIGHT) + VIDEO_LOGO_HEIGHT);
+ (console_row * VIDEO_FONT_HEIGHT) + video_logo_height);
 #endif /* CONFIG_VIDEO_HW_CURSOR */
 
 #ifdef CONFIG_VIDEO_LOGO
@@ -298,7 +298,7 @@ voidconsole_cursor (int state);
 #define VIDEO_BURST_LEN(VIDEO_COLS/8)
 
 #ifdef CONFIG_VIDEO_LOGO
-#define CONSOLE_ROWS   ((VIDEO_ROWS - VIDEO_LOGO_HEIGHT) / 
VIDEO_FONT_HEIGHT)
+#define CONSOLE_ROWS   ((VIDEO_ROWS - video_logo_height) / 
VIDEO_FONT_HEIGHT)
 #else
 #define CONSOLE_ROWS   (VIDEO_ROWS / VIDEO_FONT_HEIGHT)
 #endif
@@ -349,6 +349,8 @@ static GraphicDevice *pGD;  /* Pointer to Graphic array */
 static void *video_fb_address; /* frame buffer address */
 static void *video_console_address;/* console buffer start address */
 
+static int video_logo_height = VIDEO_LOGO_HEIGHT;
+
 static int console_col = 0; /* cursor col */
 static int console_row = 0; /* cursor row */
 
@@ -527,7 +529,7 @@ static inline void video_drawstring (int xx, int yy, 
unsigned char *s)
 
 static void video_putchar (int xx, int yy, unsigned char c)
 {
-   video_drawchars (xx, yy + VIDEO_LOGO_HEIGHT, &c, 1);
+   video_drawchars (xx, yy + video_logo_height, &c, 1);
 }
 
 /*/
@@ -620,11 +622,11 @@ static void console_scrollup (void)
 #ifdef VIDEO_HW_BITBLT
video_hw_bitblt (VIDEO_PIXEL_SIZE,  /* bytes per pixel */
 0, /* source pos x */
-VIDEO_LOGO_HEIGHT + VIDEO_FONT_HEIGHT, /* source pos y 
*/
+video_logo_height + VIDEO_FONT_HEIGHT, /* source pos y 
*/
 0, /* dest pos x */
-VIDEO_LOGO_HEIGHT, /* dest pos y */
+video_logo_height, /* dest pos y */
 VIDEO_VISIBLE_COLS,/* frame width */
-VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT - 
VIDEO_FONT_HEIGHT /* frame height */
+VIDEO_VISIBLE_ROWS - video_logo_height - 
VIDEO_FONT_HEIGHT /* frame height */
);
 #else
memcpyl (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND,
@@ -1101,7 +1103,7 @@ void logo_plot (void *screen, int width, int x, int y)
 
int xcount, i;
int skip   = (width - VIDEO_LOGO_WIDTH) * VIDEO_PIXEL_SIZE;
-   int ycount = VIDEO_LOGO_HEIGHT;
+   int ycount = video_logo_height;
unsigned char r, g, b, *logo_red, *logo_blue, *logo_green;
unsigned char *source;
unsigned char *dest = (unsigned char *)screen +
@@ -1225,6 +1227,7 @@ static void *video_logo (void)
 #endif /* CONFIG_SPLASH_SCREEN_ALIGN */
 
if (video_display_bitmap (addr, x, y) == 0) {
+   video_logo_height = 0;
return ((void *) (video_fb_address));
}
}
@@ -1249,7 +1252,7 @@ static void *video_logo (void)
 
 #ifdef CONFIG_CONSOLE_EXTRA_INFO
{
-   int i, n = ((VIDEO_LOGO_HEIGHT - VIDEO_FONT_HEIGHT) / 
VIDEO_FONT_HEIGHT);
+   int i, n = ((video_logo_height - VIDEO_FONT_HEIGHT) / 
VIDEO_FONT_HEIGHT);
 
for (i = 1; i < n; i++) {
video_get_info_str (i, info);
@@ -1278,7 +1281,7 @@ static void *video_logo (void)
}
 #endif
 
-   return (video_fb_address + VIDEO_LOGO_HEIGHT * VIDEO_LINE_LEN);
+   return (video_fb_address + video_logo_height * VIDEO_LINE_LEN);
 }
 #endif
 
-- 
1.5.6.3

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[U-Boot] usage of OTP (one time programmable) flash ?

[Arno Steffen]

The flash (MT29F1G) on my omap board supports OTP. Is there any support by
u-boot to have access (write/read) to that OPT area?
What's to do to get it working and how to use?
I've been searching a lot in the net, but hasn't been succesful with that.
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[U-Boot] Ethernet doesn't work on Colibri PXA320

[Dennis Semakin]

Hello

I have despaired already. U-boot network subsystem in any way doesn't want to 
work on my board. :(
I've found a place where it hang.

When I run any network command (ping, tftpboot, etc...) CPU sends EECS signal 
(EEPROM Chip Select) to 
AX88796 ethernet controller, to its MEMR - MII/EEPROM Management Register 
(address is 0x10001428) and then
system is halted. And  nothing is happen.
This is it...
Should I think that it is hardware issue?


Thansk
Best regards
Dennis Semakin
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[U-Boot] Ethernet doesn't work on Colibri PXA320

[Dennis Semakin]

Hello

I have despaired already. U-boot network subsystem in any way doesn't want to 
work on my board. :(
I've found a place where it hang.

When I run any network command (ping, tftpboot, etc...) CPU sends EECS signal 
(EEPROM Chip Select) to 
AX88796 ethernet controller, to its MEMR - MII/EEPROM Management Register 
(address is 0x10001428) and then
system is halted. And  nothing is happen.
This is it...
Should I think that it is hardware issue?


Thansk
Best regards
Dennis Semakin

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Re: [U-Boot] [beagleboard] RE: TI:OMAP: [PATCH] Add 720Mhz support for Beagle Rev C4

[Premi, Sanjeev]

 

> -Original Message-
> From: u-boot-boun...@lists.denx.de 
> [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Syed 
> Mohammed, Khasim 
> Sent: Tuesday, January 12, 2010 11:35 AM
> To: beaglebo...@googlegroups.com
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] [beagleboard] RE: TI:OMAP: [PATCH] Add 
> 720Mhz support for Beagle Rev C4
> 
> On Mon, Jan 11, 2010 at 10:52 PM, Premi, Sanjeev  wrote:
> >> -Original Message-
> >> From: u-boot-boun...@lists.denx.de
> >> [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Khasim
> >> Syed Mohammed
> >> Sent: Saturday, January 09, 2010 10:17 AM
> >> To: u-boot@lists.denx.de; beaglebo...@googlegroups.com
> >> Subject: [U-Boot] TI:OMAP: [PATCH] Add 720Mhz support for
> >> Beagle Rev C4
> >>
> >> From e28c5e917f9504b724b6587287ad9e1eb0682b11 Mon Sep 17 
> 00:00:00 2001
> >> From: Syed Mohammed Khasim 
> >> Date: Sat, 9 Jan 2010 09:40:32 +0530
> >> Subject: [PATCH] Add 720Mhz support for Beagle Rev C4
> >>
> >> Use the Generic TWL and Clock APIs to get beagle
> >> Rev C4 running at 720Mhz
> >>
> >> Signed-off-by: Syed Mohammed Khasim 
> >> ---
> >>  board/ti/beagle/beagle.c |   20 ++--
> >>  1 files changed, 18 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
> >> index 0def5a6..7985ee9 100644
> >> --- a/board/ti/beagle/beagle.c
> >> +++ b/board/ti/beagle/beagle.c
> >> @@ -122,9 +122,27 @@ int misc_init_r(void)
> >>       struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
> >>       struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
> >>
> >> +     beagle_identify();
> >> +
> >>       twl4030_power_init();
> >>       twl4030_led_init();
> >>
> >> +     if (beagle_revision == REVISION_C4) {
> >> +
> >> +             /* Select TWL4030 VSEL to support 720Mhz */
> >> +
> >> twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
> >> +                                     VAUX2_VSEL_18,
> >> +
> >> TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
> >> +                                     DEV_GRP_P1);
> >> +
> >> +             
> twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VDD1_VSEL,
> >> +                                     VDD1_VSEL_14,
> >> +
> >> TWL4030_PM_RECEIVER_VDD1_DEV_GRP,
> >> +                                     DEV_GRP_P1);
> >> +
> >> +             prcm_config_720mhz();
> >> +     }
> >> +
> >>       /* Configure GPIOs to output */
> >>       writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1),
> >> &gpio6_base->oe);
> >>       writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 
> | GPIO21 |
> >> @@ -136,8 +154,6 @@ int misc_init_r(void)
> >>       writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
> >>               GPIO15 | GPIO14 | GPIO13 | GPIO12,
> >> &gpio5_base->setdataout);
> >>
> >> -     beagle_identify();
> >> -
> >>       dieid_num_r();
> >
> > Khasim,
> >
> > I am not clear about the beagle revisions, but I feel it 
> will be better to
> > check the silicon capability for 720MHz to do the scaling. 
> This patch will
> > need to be updated if there is C5 which also supports 720MHz.
> >
> I was looking for documentation / addendum that points to change in
> silicon revisions - unfortunately I didn't find any.
> 
> I agree that we can base this on Silicon Rev instead of board rev.
> Will change this when I get the documentation for the same.

Khasim,

The steps are defined in the latest TRM.

Best regards,
Sanjeev

> Thanks for the review.
> 
> Regards,
> Khasim
> 
> >>
> >>       return 0;
> >> --
> >> 1.5.6.3
> >> ___
> >> U-Boot mailing list
> >> U-Boot@lists.denx.de
> >> http://lists.denx.de/mailman/listinfo/u-boot
> >>
> > --
> > You received this message because you are subscribed to the 
> Google Groups "Beagle Board" group.
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> beagleboard+unsubscr...@googlegroups.com.
> > For more options, visit this group at 
> http://groups.google.com/group/beagleboard?hl=en.
> >
> >
> >
> >
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Re: [U-Boot] [PATCH v2 0/9] Added support for SPEAr SoCs

[Tom]

Vipin Kumar wrote:
> Hello Tom,
> 
 I am planning to keep the patch order as it is but I would remove
 dependencies eg. SPEAr600 would not contain code that depends on
 a driver added later and so on.

 This should also be OK. Right?
>>> It should remove the 'git bisect' issue, which is the important thing to
>>> me.  The way you did it in v3 should work, its just a bit uglier than
>>> doing it the "right" way that I outlined above.  Eg you modify spear.h
>>> and config.mk each time you add a new driver, basically tweaking the
>>> board support as the patch sequence progresses instead of just adding
>>> proper board support in 1 patch at the end.
>>>
>>> Also, its a bit ugly to add both spear arch support as well as board
>>> support in patch 2/11.  Ideally you'd have 1 patch adding spear
>>> architectural support, then additional patches for drivers, then patches
>>> for boards.
>>>
>> On 2/11, this patch must be split.
>> Arch support split from board support.
>>
>> Moving the driver support before board support would simplify the
>> review. The subsystem custodians would only have to review what they
>> are responsible for.  I would also recommend doing this.
>>
> 
> Changes done as you suggested in patch set version4
> 
Thanks,
I am reviewing this patch set now.
So far it looks ok wrt mechanical checking.
Tom

> Regards
> Vipin

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Re: [U-Boot] [PATCH 0/2] omap3: Optimize detection of cpu revision

[Tom]

Premi, Sanjeev wrote:
>> -Original Message-
>> From: Paulraj, Sandeep 
>> Sent: Thursday, January 07, 2010 9:02 PM
>> To: Premi, Sanjeev; u-boot@lists.denx.de
>> Subject: RE: [PATCH 0/2] omap3: Optimize detection of cpu revision
 -Original Message-
 From: Premi, Sanjeev
 Sent: Tuesday, December 15, 2009 6:48 PM
 To: u-boot@lists.denx.de
 Cc: Premi, Sanjeev
 Subject: [PATCH 0/2] omap3: Optimize detection of cpu revision

 Each call to get_cpu_rev() leads to repetitive
 execution of code to detect the cpu revision.

 This patchset ensures that mechanism to detect
 revision is not executed each time; instead a
 stored value is returned.

 Since, revision info is needed in s_init(),
 the function to identify cpu revision needs
 to be called twice. At the moment, it is
 necessary/ unavoidable.

 Sanjeev Premi (2):
   omap3: Identify the CPU in arch_cpu_init()
   omap3: Identify cpu in s_init()

  cpu/arm_cortexa8/omap3/board.c |2 +
  cpu/arm_cortexa8/omap3/sys_info.c  |   73
 ++--
  include/asm-arm/arch-omap3/sys_proto.h |3 +-
  include/configs/omap3_beagle.h |2 +
  include/configs/omap3_evm.h|2 +
  include/configs/omap3_overo.h  |2 +
  include/configs/omap3_pandora.h|2 +
  include/configs/omap3_zoom1.h  |2 +
  include/configs/omap3_zoom2.h  |2 +
  9 files changed, 66 insertions(+), 24 deletions(-)


>>> Sandeep, Tom,
>>>
>>> Any comments on this series on your queue..
>> Sanjeev,
>>
>> Wolfgang had some comments on this.
>>
>> http://www.mail-archive.com/u-boot@lists.denx.de/msg26568.html
>>
> 
> Did not find this mail in my inbox (may be reason to miss it earlier).
> Anyway, pasting it below to maintain context:
> 
>> Dear "Premi, Sanjeev",
>>
>> In message 
>> you wrote:
>>> Also, I don't believe there is any complexity added as
>>> the contents of register are being read and saved in a
>>> global variable for use later.
>> Global variables are a bad thing if there is not really a good reason
>> to hav ethem. Here it makes no sense to me. Execution time seems
>> uncritical, and there is no kind of hardware wear involved with
>> readin the registers, so like Tom I don't see a reason for this
>> "optimization".
> 
> Tom, Denx,
> 
> As this patch stands, there isn't much code to optimize; but the
> change was meant as enabler for the next set of processors. The
> register and mechanism is same ...just interpretation will differ.
> 
> There is already a patchset for AM35x devices and there will new
> patches for OMAP36x. 
> 
> Also, I believe faster execution time is always better; not just
> in critical sections of code. I possibly used "global" quite loosely;
> while responding earlier. The variable cpu_revision (being discussed)
> here is actually a 'static'. (See patch 1/2).
> 
> But, if we feel otherwise, I can revert to executing detection
> mechanism each time in the function.
> 
> However, are their any comments on remainder of the patch e.g.
> moving the cpu identification eary in the u-boot exectuion. The
> DPLL settings etc will depend upon the si identification.
> 

I am not in favor of the patch.
Please remove it and rework your patchset.
Tom

> Best regards,
> Sanjeev
> 
>> Best regards,
>> Wolfgang Denk
> 
> Best regards,
> Sanjeev
> 
>>> Best regards,
>>> Sanjeev
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Re: [U-Boot] [RFC] MUSB-UDC issues and fixes

[Tom]

Juha Kuikka wrote:
> Hi,
> 
> I ran into some issues with the MUSB-UDC support while adding a new
> Davinci DM850/OMAP-L138 board:
> 
> 1. Move endpoint count into SoC specific musb-header file. This
> implementation only has 4 instead of 15 OMAP2/3 has.
> 2. On DM850 the MUSB interrupts are read from a wrapper, not from MUSB
> block . Add optional interface function to read-and-clear interrupts.
> 3. Problem setting FADDR - in udc_irq() the
> musb_peri_ep0_set_address() gets called on the same run as the ep0
> SET_ADDRESS request is handled. This causes the FADDR to change before
> the status stage interrupt is received and USB session fails. Fixed by
> removing extra call to musb_peri_ep0() from udc_irq(). It should only
> be called when EP0 interrupt is present.
> 4. udc_setup_ep() has a problem when id != 0, epinfo[] is indexed too
> far, this results in wrong EPs configured.
> 
> This is not a final patch, just asking for comments.
> 
> I am investigating another issue where rx endpoint stops receiving
> data when CDC ACM console is used. This happens under heavy inbound
> data conditions, namely using "loads".
> 
> -
> diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c
> index fc43cf4..b6f9bff 100644
> --- a/drivers/usb/musb/musb_udc.c
> +++ b/drivers/usb/musb/musb_udc.c
> @@ -65,8 +65,6 @@
>  /* #define MUSB_DEBUG */
>  #include "musb_debug.h"
> 
> -#define MAX_ENDPOINT 15
> -
>  #define GET_ENDPOINT(dev,ep) \
>  (((struct usb_device_instance *)(dev))->bus->endpoint_array + ep)
> 
> @@ -157,6 +155,17 @@ static void musb_db_regs(void)
>  #define musb_db_regs()
>  #endif /* DEBUG_MUSB */
> 
> +#ifndef CONFIG_MUSB_SOC_IRQ
> +static void musb_get_interrupts(u8 *usb, u16 *rx, u16 *tx)
> +{
> + *usb = readb(&musbr->intrusb);
> + *rx = readw(&musbr->intrrx);
> + *tx = readw(&musbr->intrtx);
> +}
> +#else
> +extern void musb_get_interrupts(u8 *usb, u16 *rx, u16 *tx);
> +#endif
> +

The reading of INT registers clears them.
If all you want in the usb INT's, you will wipe out the rx/tx to
get them.

Tom
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Re: [U-Boot] [beagleboard] RE: TI:OMAP: [PATCH] Add 720Mhz support for Beagle Rev C4

[Syed Mohammed, Khasim]

On Tue, Jan 12, 2010 at 6:52 PM, Premi, Sanjeev  wrote:
>
>
>> -Original Message-
>> From: u-boot-boun...@lists.denx.de
>> [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Syed
>> Mohammed, Khasim
>> Sent: Tuesday, January 12, 2010 11:35 AM
>> To: beaglebo...@googlegroups.com
>> Cc: u-boot@lists.denx.de
>> Subject: Re: [U-Boot] [beagleboard] RE: TI:OMAP: [PATCH] Add
>> 720Mhz support for Beagle Rev C4
>>
>> On Mon, Jan 11, 2010 at 10:52 PM, Premi, Sanjeev  wrote:
>> >> -Original Message-
>> >> From: u-boot-boun...@lists.denx.de
>> >> [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Khasim
>> >> Syed Mohammed
>> >> Sent: Saturday, January 09, 2010 10:17 AM
>> >> To: u-boot@lists.denx.de; beaglebo...@googlegroups.com
>> >> Subject: [U-Boot] TI:OMAP: [PATCH] Add 720Mhz support for
>> >> Beagle Rev C4
>> >>
>> >> From e28c5e917f9504b724b6587287ad9e1eb0682b11 Mon Sep 17
>> 00:00:00 2001
>> >> From: Syed Mohammed Khasim 
>> >> Date: Sat, 9 Jan 2010 09:40:32 +0530
>> >> Subject: [PATCH] Add 720Mhz support for Beagle Rev C4
>> >>
>> >> Use the Generic TWL and Clock APIs to get beagle
>> >> Rev C4 running at 720Mhz
>> >>
>> >> Signed-off-by: Syed Mohammed Khasim 
>> >> ---
>> >>  board/ti/beagle/beagle.c |   20 ++--
>> >>  1 files changed, 18 insertions(+), 2 deletions(-)
>> >>
>> >> diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
>> >> index 0def5a6..7985ee9 100644
>> >> --- a/board/ti/beagle/beagle.c
>> >> +++ b/board/ti/beagle/beagle.c
>> >> @@ -122,9 +122,27 @@ int misc_init_r(void)
>> >>       struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
>> >>       struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
>> >>
>> >> +     beagle_identify();
>> >> +
>> >>       twl4030_power_init();
>> >>       twl4030_led_init();
>> >>
>> >> +     if (beagle_revision == REVISION_C4) {
>> >> +
>> >> +             /* Select TWL4030 VSEL to support 720Mhz */
>> >> +
>> >> twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
>> >> +                                     VAUX2_VSEL_18,
>> >> +
>> >> TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
>> >> +                                     DEV_GRP_P1);
>> >> +
>> >> +
>> twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VDD1_VSEL,
>> >> +                                     VDD1_VSEL_14,
>> >> +
>> >> TWL4030_PM_RECEIVER_VDD1_DEV_GRP,
>> >> +                                     DEV_GRP_P1);
>> >> +
>> >> +             prcm_config_720mhz();
>> >> +     }
>> >> +
>> >>       /* Configure GPIOs to output */
>> >>       writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1),
>> >> &gpio6_base->oe);
>> >>       writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22
>> | GPIO21 |
>> >> @@ -136,8 +154,6 @@ int misc_init_r(void)
>> >>       writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
>> >>               GPIO15 | GPIO14 | GPIO13 | GPIO12,
>> >> &gpio5_base->setdataout);
>> >>
>> >> -     beagle_identify();
>> >> -
>> >>       dieid_num_r();
>> >
>> > Khasim,
>> >
>> > I am not clear about the beagle revisions, but I feel it
>> will be better to
>> > check the silicon capability for 720MHz to do the scaling.
>> This patch will
>> > need to be updated if there is C5 which also supports 720MHz.
>> >
>> I was looking for documentation / addendum that points to change in
>> silicon revisions - unfortunately I didn't find any.
>>
>> I agree that we can base this on Silicon Rev instead of board rev.
>> Will change this when I get the documentation for the same.
>
> Khasim,
>
> The steps are defined in the latest TRM.
>
Thanks for pointing that out. After checking out with Gerald, I prefer
staying with Board revision for this Rev.

I am also waiting for cpu revision detection discussion to stabilize a bit.

Regards,
Khasim

>
>> Thanks for the review.
>>
>> Regards,
>> Khasim
>>
>> >>
>> >>       return 0;
>> >> --
>> >> 1.5.6.3
>> >> ___
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>> >> http://lists.denx.de/mailman/listinfo/u-boot
>> >>
>> > --
>> > You received this message because you are subscribed to the
>> Google Groups "Beagle Board" group.
>> > To post to this group, send email to beaglebo...@googlegroups.com.
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>> beagleboard+unsubscr...@googlegroups.com.
>> > For more options, visit this group at
>> http://groups.google.com/group/beagleboard?hl=en.
>> >
>> >
>> >
>> >
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[U-Boot] TI:OMAP: Re-submitting Beagle REV C4, 720 Mhz and DSS patches

[Khasim Syed Mohammed]

Hi all,

I have incorporated all the review comments so far and re-submitting
the complete patch series.

Regards,
Khasim
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[U-Boot] TI:OMAP: [PATCH 1/7] OMAP3 Beagle Update revision detection

[Khasim Syed Mohammed]

>From 15fbe5ff9ee2fd2f8da4c16805d6c7ccf7244bae Mon Sep 17 00:00:00 2001
From: Syed Mohammed Khasim 
Date: Fri, 8 Jan 2010 20:13:47 +0530
Subject: [PATCH] OMAP3 Beagle Update revision detection

New BeagleBoard revision C4 uses a new ID. Update revision detection.

Signed-off-by: Dirk Behme 
Signed-off-by: Syed Mohammed Khasim 
---
 board/ti/beagle/beagle.c |   65 -
 board/ti/beagle/beagle.h |8 -
 2 files changed, 46 insertions(+), 27 deletions(-)

diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 32d501e..0def5a6 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -38,7 +38,7 @@
 #include 
 #include "beagle.h"

-static int beagle_revision_c;
+static int beagle_revision;

 /*
  * Routine: board_init
@@ -60,41 +60,57 @@ int board_init(void)
 /*
  * Routine: beagle_get_revision
  * Description: Return the revision of the BeagleBoard this code is running on.
- *  If it is a revision Ax/Bx board, this function returns 0,
- *  on a revision C board you will get a 1.
  */
 int beagle_get_revision(void)
 {
-   return beagle_revision_c;
+   return beagle_revision;
 }

 /*
  * Routine: beagle_identify
- * Description: Detect if we are running on a Beagle revision Ax/Bx or
- *  Cx. This can be done by GPIO_171. If this is low, we are
- *  running on a revision C board.
+ * Description: Detect if we are running on a Beagle revision Ax/Bx,
+ * C1/2/3, C4 or D. This can be done by reading
+ * the level of GPIO173, GPIO172 and GPIO171. This should
+ * result in
+ * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
+ * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
+ * GPIO173, GPIO172, GPIO171: 1 0 1 => C4
+ * GPIO173, GPIO172, GPIO171: 0 0 0 => D
  */
 void beagle_identify(void)
 {
-   beagle_revision_c = 0;
-   if (!omap_request_gpio(171)) {
-   unsigned int val;
-
-   omap_set_gpio_direction(171, 1);
-   val = omap_get_gpio_datain(171);
-   omap_free_gpio(171);
-
-   if (val)
-   beagle_revision_c = 0;
-   else
-   beagle_revision_c = 1;
-   }
+   omap_request_gpio(171);
+   omap_request_gpio(172);
+   omap_request_gpio(173);
+   omap_set_gpio_direction(171, 1);
+   omap_set_gpio_direction(172, 1);
+   omap_set_gpio_direction(173, 1);
+
+   beagle_revision = omap_get_gpio_datain(173) << 2 |
+ omap_get_gpio_datain(172) << 1 |
+ omap_get_gpio_datain(171);
+   omap_free_gpio(171);
+   omap_free_gpio(172);
+   omap_free_gpio(173);

printf("Board revision ");
-   if (beagle_revision_c)
-   printf("C\n");
-   else
+
+   switch (beagle_revision) {
+   case REVISION_AXBX:
printf("Ax/Bx\n");
+   break;
+   case REVISION_CX:
+   printf("C1/C2/C3\n");
+   break;
+   case REVISION_C4:
+   printf("C4\n");
+   break;
+   case REVISION_D:
+   printf("D\n");
+   break;
+   default:
+   printf("unknown 0x%02x\n", beagle_revision);
+   }
 }

 /*
@@ -137,7 +153,6 @@ void set_muxconf_regs(void)
 {
MUX_BEAGLE();

-   if (beagle_revision_c) {
+   if (beagle_revision != REVISION_AXBX)
MUX_BEAGLE_C();
-   }
 }
diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
index 7fe6275..b1720c9 100644
--- a/board/ti/beagle/beagle.h
+++ b/board/ti/beagle/beagle.h
@@ -33,7 +33,11 @@ const omap3_sysinfo sysinfo = {
 #endif
 };

-#define BOARD_REVISION_MASK(0x1 << 11)
+/* BeagleBoard revisions */
+#define REVISION_AXBX  0x7
+#define REVISION_CX0x6
+#define REVISION_C40x5
+#define REVISION_D 0x0

 /*
  * IEN  - Input Enable
@@ -264,7 +268,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(HDQ_SIO),(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
MUX_VAL(CP(MCSPI1_CLK), (IEN  | PTU | EN  | M4)) /*GPIO_171*/\
MUX_VAL(CP(MCSPI1_SIMO),(IEN  | PTU | EN  | M4)) /*GPIO_172*/\
-   MUX_VAL(CP(MCSPI1_SOMI),(IEN  | PTD | DIS | M0)) 
/*McSPI1_SOMI*/\
+   MUX_VAL(CP(MCSPI1_SOMI),(IEN  | PTU | EN  | M4)) /*GPIO_173*/\
MUX_VAL(CP(MCSPI1_CS0), (IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
-- 
1.5.6.3
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[U-Boot] TI:OMAP: [PATCH 2/7] Enable I2C bus switching

[Khasim Syed Mohammed]

>From 9045377f255e8a59450a6957e63366b4963281ae Mon Sep 17 00:00:00 2001
From: Syed Mohammed Khasim 
Date: Fri, 8 Jan 2010 20:20:41 +0530
Subject: [PATCH] Enable I2C bus switching

OMAP3 supports Multiple I2C channels, this patch allows
us to use i2c dev  command to switch between busses.

Signed-off-by: Syed Mohammed Khasim 
Acked-by: Heiko Schocher 
---
 drivers/i2c/omap24xx_i2c.c |5 +
 include/configs/omap3_beagle.h |4 
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index ff18991..e8c8184 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -435,3 +435,8 @@ int i2c_set_bus_num(unsigned int bus)

return 0;
 }
+
+int i2c_get_bus_num(void)
+{
+   return (int) current_bus;
+}
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index d1c9cd0..ff6d432 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -100,6 +100,10 @@
 /* DDR - I use Micron DDR */
 #define CONFIG_OMAP3_MICRON_DDR1

+/* Enable Multi Bus support for I2C */
+#define CONFIG_I2C_MULTI_BUS   1
+#define CONFIG_SYS_I2C_NOPROBES{0x0, 0x0}
+
 /* commands to include */
 #include 

-- 
1.5.6.3
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[U-Boot] [PATCH 1/3] Add support to disable cpu's in multicore processors

[Kumar Gala]

Add a disable sub-command to the cpu command that allows for disabling
cores in multicore processors.  This can be useful for systems that are
using multicore chips but aren't utilizing all the cores as a way to
reduce power and possibly improve performance.

Also updated an added missing copyright.

Signed-off-by: Kumar Gala 
---
 common/cmd_mp.c  |3 +++
 cpu/mpc85xx/mp.c |8 +++-
 cpu/mpc86xx/mp.c |   28 
 include/common.h |1 +
 4 files changed, 39 insertions(+), 1 deletions(-)

diff --git a/common/cmd_mp.c b/common/cmd_mp.c
index 71e4303..d78c209 100644
--- a/common/cmd_mp.c
+++ b/common/cmd_mp.c
@@ -46,6 +46,8 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
cpu_reset(cpuid);
} else if (strncmp(argv[2], "status", 6) == 0) {
cpu_status(cpuid);
+   } else if (strncmp(argv[2], "disable", 7) == 0) {
+   return cpu_disable(cpuid);
} else {
cmd_usage(cmdtp);
return 1;
@@ -86,6 +88,7 @@ U_BOOT_CMD(
"Multiprocessor CPU boot manipulation and release",
" reset - Reset cpu \n"
"cpu  status- Status of cpu \n"
+   "cpu  disable   - Disable cpu \n"
"cpu  release  [args] - Release cpu  at  with 
[args]"
 #ifdef CPU_ARCH_HELP
"\n"
diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c
index 6530cb1..6ae7f0a 100644
--- a/cpu/mpc85xx/mp.c
+++ b/cpu/mpc85xx/mp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -68,6 +68,12 @@ int cpu_status(int nr)
return 0;
 }
 
+int cpu_disable(int nr)
+{
+   /* dummy function so common/cmd_mp.c will build */
+   return 1;
+}
+
 static u8 boot_entry_map[4] = {
0,
BOOT_ENTRY_PIR,
diff --git a/cpu/mpc86xx/mp.c b/cpu/mpc86xx/mp.c
index 2940673..ecdf2fb 100644
--- a/cpu/mpc86xx/mp.c
+++ b/cpu/mpc86xx/mp.c
@@ -1,3 +1,25 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
 #include 
 #include 
 #include 
@@ -24,6 +46,12 @@ int cpu_status(int nr)
return 0;
 }
 
+int cpu_disable(int nr)
+{
+   /* dummy function so common/cmd_mp.c will build */
+   return 1;
+}
+
 int cpu_release(int nr, int argc, char *argv[])
 {
/* dummy function so common/cmd_mp.c will build
diff --git a/include/common.h b/include/common.h
index 07897f6..f90da23 100644
--- a/include/common.h
+++ b/include/common.h
@@ -703,6 +703,7 @@ void show_boot_progress(int val);
 #ifdef CONFIG_MP
 int cpu_status(int nr);
 int cpu_reset(int nr);
+int cpu_disable(int nr);
 int cpu_release(int nr, int argc, char *argv[]);
 #endif
 
-- 
1.6.0.6

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[U-Boot] [PATCH 3/3] 85xx: Add support for 'cpu disable' command

[Kumar Gala]

Support disabling of a core via user command 'cpu disable'.

Signed-off-by: Kumar Gala 
---
 cpu/mpc85xx/mp.c |   28 ++--
 1 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c
index 6ae7f0a..73c7f87 100644
--- a/cpu/mpc85xx/mp.c
+++ b/cpu/mpc85xx/mp.c
@@ -68,11 +68,35 @@ int cpu_status(int nr)
return 0;
 }
 
+#ifdef CONFIG_FSL_CORENET
 int cpu_disable(int nr)
 {
-   /* dummy function so common/cmd_mp.c will build */
-   return 1;
+   volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+   setbits_be32(&gur->coredisrl, nr);
+
+   return 0;
 }
+#else
+int cpu_disable(int nr)
+{
+   volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+   switch (nr) {
+   case 0:
+   setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
+   break;
+   case 1:
+   setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
+   break;
+   default:
+   printf("Invalid cpu number for disable %d\n", nr);
+   return 1;
+   }
+   
+   return 0;
+}
+#endif
 
 static u8 boot_entry_map[4] = {
0,
-- 
1.6.0.6

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[U-Boot] [PATCH 2/3] 86xx: Add support for 'cpu disable' command

[Kumar Gala]

Support disabling of a core via user command 'cpu disable'.

Signed-off-by: Kumar Gala 
---
 cpu/mpc86xx/mp.c |   18 --
 include/asm-ppc/immap_86xx.h |   33 ++---
 2 files changed, 34 insertions(+), 17 deletions(-)

diff --git a/cpu/mpc86xx/mp.c b/cpu/mpc86xx/mp.c
index ecdf2fb..2c72752 100644
--- a/cpu/mpc86xx/mp.c
+++ b/cpu/mpc86xx/mp.c
@@ -48,8 +48,22 @@ int cpu_status(int nr)
 
 int cpu_disable(int nr)
 {
-   /* dummy function so common/cmd_mp.c will build */
-   return 1;
+   volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
+   volatile ccsr_gur_t *gur = &immap->im_gur;
+
+   switch (nr) {
+   case 0:
+   setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0);
+   break;
+   case 1:
+   setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1);
+   break;
+   default:
+   printf("Invalid cpu number for disable %d\n", nr);
+   return 1;
+   }
+   
+   return 0;
 }
 
 int cpu_release(int nr, int argc, char *argv[])
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 098f253..fd7acdb 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -1186,17 +1186,8 @@ typedef struct ccsr_rio {
 typedef struct ccsr_gur {
uintporpllsr;   /* 0xe - POR PLL ratio status register */
uintporbmsr;/* 0xe0004 - POR boot mode status register */
-#define MPC8610_PORBMSR_HA  0x0007
-#define MPC8610_PORBMSR_HA_SHIFT   16
-#define MPC8641_PORBMSR_HA  0x0006
-#define MPC8641_PORBMSR_HA_SHIFT   17
uintporimpscr;  /* 0xe0008 - POR I/O impedance status and 
control register */
uintpordevsr;   /* 0xe000c - POR I/O device status regsiter */
-#define MPC8610_PORDEVSR_IO_SEL0x0038
-#define MPC8610_PORDEVSR_IO_SEL_SHIFT  19
-#define MPC8641_PORDEVSR_IO_SEL0x000F
-#define MPC8641_PORDEVSR_IO_SEL_SHIFT  16
-#define MPC86xx_PORDEVSR_CORE1TE   0x0080 /* ASMP (Core1 addr trans) */
uintpordbgmsr;  /* 0xe0010 - POR debug mode status register */
charres1[12];
uintgpporcr;/* 0xe0020 - General-purpose POR configuration 
register */
@@ -1210,11 +1201,6 @@ typedef struct ccsr_gur {
uintpmuxcr; /* 0xe0060 - Alternate function signal 
multiplex control */
charres6[12];
uintdevdisr;/* 0xe0070 - Device disable control */
-#define MPC86xx_DEVDISR_PCIEX1 0x8000
-#define MPC86xx_DEVDISR_PCIEX2 0x4000
-#define MPC86xx_DEVDISR_PCI1   0x8000
-#define MPC86xx_DEVDISR_PCIE1  0x4000
-#define MPC86xx_DEVDISR_PCIE2  0x2000
charres7[12];
uintpowmgtcsr;  /* 0xe0080 - Power management status and 
control register */
charres8[12];
@@ -1225,7 +1211,6 @@ typedef struct ccsr_gur {
uintsvr;/* 0xe00a4 - System version register */
charres10a[8];
uintrstcr;  /* 0xe00b0 - Reset control register */
-#define MPC86xx_RSTCR_HRST_REQ 0x0002
charres10b[1868];
uintclkdvdr;/* 0xe0800 - Clock Divide register */
charres10c[796];
@@ -1250,6 +1235,24 @@ typedef struct ccsr_gur {
charres16[184];
 } ccsr_gur_t;
 
+#define MPC8610_PORBMSR_HA  0x0007
+#define MPC8610_PORBMSR_HA_SHIFT   16
+#define MPC8641_PORBMSR_HA  0x0006
+#define MPC8641_PORBMSR_HA_SHIFT   17
+#define MPC8610_PORDEVSR_IO_SEL0x0038
+#define MPC8610_PORDEVSR_IO_SEL_SHIFT  19
+#define MPC8641_PORDEVSR_IO_SEL0x000F
+#define MPC8641_PORDEVSR_IO_SEL_SHIFT  16
+#define MPC86xx_PORDEVSR_CORE1TE   0x0080 /* ASMP (Core1 addr trans) */
+#define MPC86xx_DEVDISR_PCIEX1 0x8000
+#define MPC86xx_DEVDISR_PCIEX2 0x4000
+#define MPC86xx_DEVDISR_PCI1   0x8000
+#define MPC86xx_DEVDISR_PCIE1  0x4000
+#define MPC86xx_DEVDISR_PCIE2  0x2000
+#define MPC86xx_DEVDISR_CPU0   0x8000
+#define MPC86xx_DEVDISR_CPU1   0x4000
+#define MPC86xx_RSTCR_HRST_REQ 0x0002
+
 /*
  * Watchdog register block(0xe_4000-0xe_4fff)
  */
-- 
1.6.0.6

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[U-Boot] TI:OMAP: [PATCH 3/7] API to set twl4030 voltage and dev group

[Khasim Syed Mohammed]

>From 83928f2ae1e461c48d4dc471a3dcab778b212467 Mon Sep 17 00:00:00 2001
From: Syed Mohammed Khasim 
Date: Tue, 12 Jan 2010 16:19:23 +0530
Subject: [PATCH] API to set twl4030 voltage and dev group

V3:
Incorporated review comments to set voltage first
and then dev group

V2:
Incorporated review comments to split the patch and
add generic API to set the voltage and device group.
http://www.mail-archive.com/u-boot@lists.denx.de/msg27136.html

V1:
Added support for 720 Mhz
http://www.mail-archive.com/u-boot@lists.denx.de/msg27035.html

Signed-off-by: Syed Mohammed Khasim 
---
 drivers/power/twl4030.c |   24 +++-
 include/twl4030.h   |   16 
 2 files changed, 31 insertions(+), 9 deletions(-)

diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c
index eb066cb..f25b58f 100644
--- a/drivers/power/twl4030.c
+++ b/drivers/power/twl4030.c
@@ -59,16 +59,9 @@ void twl4030_power_reset_init(void)
}
 }

-
 /*
  * Power Init
  */
-#define DEV_GRP_P1 0x20
-#define VAUX3_VSEL_28  0x03
-#define DEV_GRP_ALL0xE0
-#define VPLL2_VSEL_18  0x05
-#define VDAC_VSEL_18   0x03
-
 void twl4030_power_init(void)
 {
unsigned char byte;
@@ -98,8 +91,6 @@ void twl4030_power_init(void)
 TWL4030_PM_RECEIVER_VDAC_DEDICATED);
 }

-#define VMMC1_VSEL_30  0x02
-
 void twl4030_power_mmc_init(void)
 {
unsigned char byte;
@@ -113,3 +104,18 @@ void twl4030_power_mmc_init(void)
twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
 TWL4030_PM_RECEIVER_VMMC1_DEDICATED);
 }
+
+/*
+ * Generic function to select Device Group and Voltage
+ */
+void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
+   u8 dev_grp, u8 dev_grp_sel)
+{
+   /* Select the Voltage */
+   twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_val,
+   vsel_reg);
+
+   /* Select the Device Group */
+   twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp_sel,
+   dev_grp);
+}
diff --git a/include/twl4030.h b/include/twl4030.h
index f260ecb..b96c96c 100644
--- a/include/twl4030.h
+++ b/include/twl4030.h
@@ -359,6 +359,22 @@
 #define TWL4030_USB_PHY_DPLL_CLK   (1 << 0)

 /*
+ * Voltage Selection in PM Receiver Module
+ */
+#define VAUX2_VSEL_18  0x05
+#define VDD1_VSEL_14   0x40
+#define VAUX3_VSEL_28  0x03
+#define VPLL2_VSEL_18  0x05
+#define VDAC_VSEL_18   0x03
+#define VMMC1_VSEL_30  0x02
+
+/*
+ * Device Selection
+ */
+#define DEV_GRP_P1 0x20
+#define DEV_GRP_ALL0xE0
+
+/*
  * Convience functions to read and write from TWL4030
  *
  * chip_no is the i2c address, it must be one of the chip addresses
-- 
1.5.6.3
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[U-Boot] TI:OMAP:[PATCH 4/7] Add support for 720Mhz

[Khasim Syed Mohammed]

>From e76f536facfcd14f924dc7089739187cc4e0908d Mon Sep 17 00:00:00 2001
From: Syed Mohammed Khasim 
Date: Tue, 12 Jan 2010 16:32:42 +0530
Subject: [PATCH] Add support for 720Mhz

A New API to allow setting M value to support 720Mhz

Signed-off-by: Syed Mohammed Khasim 
---
 cpu/arm_cortexa8/omap3/clock.c |   21 +
 1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c
index 174c453..d67517a 100644
--- a/cpu/arm_cortexa8/omap3/clock.c
+++ b/cpu/arm_cortexa8/omap3/clock.c
@@ -402,3 +402,24 @@ void per_clocks_enable(void)

sdelay(1000);
 }
+
+/*
+ * Configure PRCM registers to get 720 Mhz
+ *
+ * NOTE: N value doesn't change, only M gets affected
+ */
+void prcm_config_720mhz(void)
+{
+   struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+
+   /* Unlock MPU DPLL (slows things down, and needed later) */
+   sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
+   wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY);
+
+   /* Set M */
+   sr32(&prcm_base->clksel1_pll_mpu, 8, 11, 0x2D0);
+
+   /* lock mode */
+   sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
+   wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY);
+}
-- 
1.5.6.3
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[U-Boot] TI:OMAP: [PATCH 5/7] Add DSS driver for OMAP3

[Khasim Syed Mohammed]

>From 968d36271671359fdd724c5410c5264408d9f612 Mon Sep 17 00:00:00 2001
From: Syed Mohammed Khasim 
Date: Tue, 12 Jan 2010 23:57:28 +0530
Subject: [PATCH] Add DSS driver for OMAP3

Supports dynamic panel configuration
Supports dynamic tv standard selection
Adds support for DSS register access through generic APIs

Incorporated DSS register access using structures.

Previous discussions are here
http://www.mail-archive.com/u-boot@lists.denx.de/msg27150.html

Signed-off-by: Syed Mohammed Khasim 
---
 drivers/video/Makefile   |1 +
 drivers/video/omap3_dss.c|  130 
 include/asm-arm/arch-omap3/dss.h |  173 ++
 3 files changed, 304 insertions(+), 0 deletions(-)
 create mode 100644 drivers/video/omap3_dss.c
 create mode 100644 include/asm-arm/arch-omap3/dss.h

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index bb6b5a0..cb15dc2 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -37,6 +37,7 @@ COBJS-$(CONFIG_SED156X) += sed156x.o
 COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
 COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o
 COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
+COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
 COBJS-y += videomodes.o

 COBJS  := $(COBJS-y)
diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c
new file mode 100644
index 000..69c705a
--- /dev/null
+++ b/drivers/video/omap3_dss.c
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, 
+ * Syed Mohammed Khasim 
+ *
+ * Referred to Linux DSS driver files for OMAP3
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+#include 
+
+/*
+ * Configure VENC for a given Mode (NTSC / PAL)
+ */
+void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
+   u32 height, u32 width)
+{
+   struct venc_regs *venc = (struct venc_regs *) OMAP3_VENC_BASE;
+   struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE;
+   struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
+
+   writel(venc_cfg->status, &venc->status);
+   writel(venc_cfg->f_control, &venc->f_control);
+   writel(venc_cfg->vidout_ctrl, &venc->vidout_ctrl);
+   writel(venc_cfg->sync_ctrl, &venc->sync_ctrl);
+   writel(venc_cfg->llen, &venc->llen);
+   writel(venc_cfg->flens, &venc->flens);
+   writel(venc_cfg->hfltr_ctrl, &venc->hfltr_ctrl);
+   writel(venc_cfg->cc_carr_wss_carr, &venc->cc_carr_wss_carr);
+   writel(venc_cfg->c_phase, &venc->c_phase);
+   writel(venc_cfg->gain_u, &venc->gain_u);
+   writel(venc_cfg->gain_v, &venc->gain_v);
+   writel(venc_cfg->gain_y, &venc->gain_y);
+   writel(venc_cfg->black_level, &venc->black_level);
+   writel(venc_cfg->blank_level, &venc->blank_level);
+   writel(venc_cfg->x_color, &venc->x_color);
+   writel(venc_cfg->m_control, &venc->m_control);
+   writel(venc_cfg->bstamp_wss_data, &venc->bstamp_wss_data);
+   writel(venc_cfg->s_carr, &venc->s_carr);
+   writel(venc_cfg->line21, &venc->line21);
+   writel(venc_cfg->ln_sel, &venc->ln_sel);
+   writel(venc_cfg->l21__wc_ctl, &venc->l21__wc_ctl);
+   writel(venc_cfg->htrigger_vtrigger, &venc->htrigger_vtrigger);
+   writel(venc_cfg->savid__eavid, &venc->savid__eavid);
+   writel(venc_cfg->flen__fal, &venc->flen__fal);
+   writel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset);
+   writel(venc_cfg->hs_int_start_stop_x,
+   &venc->hs_int_start_stop_x);
+   writel(venc_cfg->hs_ext_start_stop_x,
+   &venc->hs_ext_start_stop_x);
+   writel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x);
+   writel(venc_cfg->vs_int_stop_x__vs_int_start_y,
+   &venc->vs_int_stop_x__vs_int_start_y);
+   writel(venc_cfg->vs_int_stop_y__vs_ext_start_x,
+   &venc->vs_int_stop_y__vs_ext_start_x);
+   writel(venc_cfg->vs_ext_stop_x__vs_ext_start_y,
+   &venc->vs_ext_stop_x__vs_ext_start_y);
+   writel(venc_cfg->vs_ext_stop_y, &venc->vs_ext_stop_y);
+   writel(venc_cfg->avid_start_stop_x, &venc->avid_start_stop_x);
+   writel(venc_cfg->avid_start_stop_y, &venc->avid_sta

[U-Boot] TI:OMAP: [PATCH 6/7] Enable DSS driver for Beagle

[Khasim Syed Mohammed]

>From f2e8fee9c6e5ca250cee0b7c4329ca1df0ce686d Mon Sep 17 00:00:00 2001
From: Syed Mohammed Khasim 
Date: Wed, 13 Jan 2010 00:15:55 +0530
Subject: [PATCH] Enable DSS driver for Beagle

Configures DSS to display color bar on Svideo
Configures DSS to display background color on DVID

Signed-off-by: Syed Mohammed Khasim 
---
 board/ti/beagle/beagle.c   |   12 ++
 board/ti/beagle/beagle.h   |   75 
 include/configs/omap3_beagle.h |1 +
 3 files changed, 88 insertions(+), 0 deletions(-)

diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 0def5a6..02e90b5 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -114,6 +114,16 @@ void beagle_identify(void)
 }

 /*
+ * Configure DSS to display background color on DVID
+ * Configure VENC to display color bar on S-Video
+ */
+void display_init(void)
+{
+   omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH);
+   omap3_dss_panel_config(&dvid_cfg);
+}
+
+/*
  * Routine: misc_init_r
  * Description: Configure board specific parts
  */
@@ -124,6 +134,7 @@ int misc_init_r(void)

twl4030_power_init();
twl4030_led_init();
+   display_init();

/* Configure GPIOs to output */
writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
@@ -139,6 +150,7 @@ int misc_init_r(void)
beagle_identify();

dieid_num_r();
+   omap3_dss_enable();

return 0;
 }
diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
index b1720c9..8f9eb50 100644
--- a/board/ti/beagle/beagle.h
+++ b/board/ti/beagle/beagle.h
@@ -23,6 +23,8 @@
 #ifndef _BEAGLE_H_
 #define _BEAGLE_H_

+#include 
+
 const omap3_sysinfo sysinfo = {
DDR_STACKED,
"OMAP3 Beagle board",
@@ -385,4 +387,77 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(UART2_RTS),  (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
MUX_VAL(CP(UART2_TX),   (IDIS | PTD | DIS | M0)) /*UART2_TX*/

+/*
+ * Display Configuration
+ */
+
+#define DVI_BEAGLE_ORANGE_COL  0x00FF8000
+#define VENC_HEIGHT0x00ef
+#define VENC_WIDTH 0x027f
+
+/*
+ * Configure VENC in DSS for Beagle to generate Color Bar
+ *
+ * Kindly refer to OMAP TRM for definition of these values.
+ */
+static const struct venc_regs venc_config_std_tv = {
+   .status = 0x001B,
+   .f_control  = 0x0040,
+   .vidout_ctrl= 0x,
+   .sync_ctrl  = 0x8000,
+   .llen   = 0x8359,
+   .flens  = 0x020C,
+   .hfltr_ctrl = 0x,
+   .cc_carr_wss_carr   = 0x043F2631,
+   .c_phase= 0x0024,
+   .gain_u = 0x0130,
+   .gain_v = 0x0198,
+   .gain_y = 0x01C0,
+   .black_level= 0x006A,
+   .blank_level= 0x005C,
+   .x_color= 0x,
+   .m_control  = 0x0001,
+   .bstamp_wss_data= 0x003F,
+   .s_carr = 0x21F07C1F,
+   .line21 = 0x,
+   .ln_sel = 0x0015,
+   .l21__wc_ctl= 0x1400,
+   .htrigger_vtrigger  = 0x,
+   .savid__eavid   = 0x069300F4,
+   .flen__fal  = 0x0016020C,
+   .lal__phase_reset   = 0x00060107,
+   .hs_int_start_stop_x= 0x008D034E,
+   .hs_ext_start_stop_x= 0x000F0359,
+   .vs_int_start_x = 0x01A0,
+   .vs_int_stop_x__vs_int_start_y  = 0x020501A0,
+   .vs_int_stop_y__vs_ext_start_x  = 0x01AC0024,
+   .vs_ext_stop_x__vs_ext_start_y  = 0x020D01AC,
+   .vs_ext_stop_y  = 0x0006,
+   .avid_start_stop_x  = 0x03480079,
+   .avid_start_stop_y  = 0x02040024,
+   .fid_int_start_x__fid_int_start_y   = 0x0001008A,
+   .fid_int_offset_y__fid_ext_start_x  = 0x01AC0106,
+   .fid_ext_start_y__fid_ext_offset_y  = 0x01060006,
+   .tvdetgp_int_start_stop_x   = 0x00140001,
+   .tvdetgp_int_start_stop_y   = 0x00010001,
+   .gen_ctrl   = 0x00FF,
+   .output_control = 0x000D,
+   .dac_b__dac_c   = 0x
+};
+
+/*
+ *

[U-Boot] TI:OMAP: [PATCH 7/7] Add 720Mhz support for Beagle Rev C4

[Khasim Syed Mohammed]

>From c8d47f8b064329676a0f04cff95eef05fe7f24ba Mon Sep 17 00:00:00 2001
From: Syed Mohammed Khasim 
Date: Wed, 13 Jan 2010 00:26:17 +0530
Subject: [PATCH] Add 720Mhz support for Beagle Rev C4

Use the Generic TWL and Clock APIs to get beagle
Rev C4 running at 720Mhz

Signed-off-by: Syed Mohammed Khasim 
---
 board/ti/beagle/beagle.c |   21 +++--
 1 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 02e90b5..338a8dc 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -132,8 +132,27 @@ int misc_init_r(void)
struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;

+   beagle_identify();
+
twl4030_power_init();
twl4030_led_init();
+
+   if (beagle_revision == REVISION_C4) {
+   
+   /* Select TWL4030 VSEL to support 720Mhz */
+   twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+   VAUX2_VSEL_18,
+   TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+   DEV_GRP_P1);
+
+   twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VDD1_VSEL,
+   VDD1_VSEL_14,
+   TWL4030_PM_RECEIVER_VDD1_DEV_GRP,
+   DEV_GRP_P1);
+
+   prcm_config_720mhz();
+   }
+
display_init();

/* Configure GPIOs to output */
@@ -147,8 +166,6 @@ int misc_init_r(void)
writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);

-   beagle_identify();
-
dieid_num_r();
omap3_dss_enable();

-- 
1.5.6.3
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Re: [U-Boot] [PATCH 3/3] 85xx: Add support for 'cpu disable' command

[Peter Tyser]

Hi Kumar,


 
> +#ifdef CONFIG_FSL_CORENET
>  int cpu_disable(int nr)
>  {
> - /* dummy function so common/cmd_mp.c will build */
> - return 1;
> + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> +
> + setbits_be32(&gur->coredisrl, nr);

Doesn't this need to be "1 << nr"?

Peter

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Re: [U-Boot] [PATCH] usb: musb: add virtual root hub control support

[Remy Bohmer]

Hi,

2010/1/9 Mike Frysinger :
> From: Bryan Wu 
>
> For MUSB devices that do not support multipoint (hubs), we have to emulate
> a root hub so that we can support core operations like resetting ports.
>
> Signed-off-by: Bryan Wu 
> Signed-off-by: Cliff Cai 
> Signed-off-by: Mike Frysinger 
> ---
>  drivers/usb/musb/musb_hcd.c |  429 
> ++-
>  drivers/usb/musb/musb_hcd.h |   55 ++
>  2 files changed, 482 insertions(+), 2 deletions(-)

Applied to u-boot-usb
Thanks.

Remy
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Re: [U-Boot] [PATCH 3/3] 85xx: Add support for 'cpu disable' command

[Kumar Gala]

On Jan 12, 2010, at 1:16 PM, Peter Tyser wrote:

> Hi Kumar,
> 
> 
> 
>> +#ifdef CONFIG_FSL_CORENET
>> int cpu_disable(int nr)
>> {
>> -/* dummy function so common/cmd_mp.c will build */
>> -return 1;
>> +volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
>> +
>> +setbits_be32(&gur->coredisrl, nr);
> 
> Doesn't this need to be "1 << nr"?

Yes, good catch.

- k
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[U-Boot] [PATCH v2 3/3] 85xx: Add support for 'cpu disable' command

[Kumar Gala]

Support disabling of a core via user command 'cpu disable'.

Signed-off-by: Kumar Gala 
---
* Fixed the FSL_CORENET case to be setbits_be32(..., 1 << nr)
  instead of (..., nr), pointed out by Peter T.

- k

 cpu/mpc85xx/mp.c |   28 ++--
 1 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c
index 6ae7f0a..3ac4e14 100644
--- a/cpu/mpc85xx/mp.c
+++ b/cpu/mpc85xx/mp.c
@@ -68,11 +68,35 @@ int cpu_status(int nr)
return 0;
 }
 
+#ifdef CONFIG_FSL_CORENET
 int cpu_disable(int nr)
 {
-   /* dummy function so common/cmd_mp.c will build */
-   return 1;
+   volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+   setbits_be32(&gur->coredisrl, 1 << nr);
+
+   return 0;
 }
+#else
+int cpu_disable(int nr)
+{
+   volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+   switch (nr) {
+   case 0:
+   setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
+   break;
+   case 1:
+   setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
+   break;
+   default:
+   printf("Invalid cpu number for disable %d\n", nr);
+   return 1;
+   }
+   
+   return 0;
+}
+#endif
 
 static u8 boot_entry_map[4] = {
0,
-- 
1.6.0.6

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[U-Boot] Problem with usbtty and loads

[Juha Kuikka]

Hi,

When using console over usb tty the "loads" command does not behave
well. It seems to eat every other character from the stream.

I traced the problem to read_record() function to these lines:

/* Check for the console hangup (if any different from serial) */
if (gd->jt[XF_getc] != getc) {
if (ctrlc()) {
return (-1);
}
}

These end up eating every other character. Not being familiar with the
u-boot console system what would be a proper fix for this?

CONFIG_CONSOLE_MUX is enabled.

 - Juha
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Re: [U-Boot] Pull request - mpc85xx

[Wolfgang Denk]

Dear Kumar Gala,

In message  you wrote:
> The following changes since commit 6ca9da4d42aeb43df5ef29f7d0518009df583b2f:
>   Wolfgang Denk (1):
> Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-mpc85xx master
> 
> Anton Vorontsov (1):
>   mpc85xx: Add 4-bits eSDHC support for MPC8569E-MDS boards
> 
> Becky Bruce (1):
>   ppc/p4080: Add Corenet Platform Cache (CPC) registers
> 
> Dave Liu (5):
>   p4080: add readback to bootpage translation window
>   fsl-ddr: Fix power-down timing settings
>   fsl-ddr: add the override for write leveling
>   fsl-ddr: add override for the Rtt_Wr
>   fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave
> 
> Kumar Gala (23):
>   85xx: Add support for e500mc cache stashing
>   ppc/p4080: Added p4080 SERDES registers & USB offset
>   ppc/8xxx: Don't use pci_cfg on FSL_CORENET platforms
>   85xx: Add support to set DPAA (data path) devices clock frequencies
>   NET: Base support for etsec2.0
>   ppc/85xx: Clean up MPC8544 DS PCI setup code
>   ppc/85xx: Clean up MPC8569 MDS PCI setup code
>   ppc/85xx: Clean up MPC8568 MDS PCI setup code
>   ppc/85xx: Clean up ATUM8548 PCI setup code
>   ppc/85xx: Clean up MPC8548 CDS PCI setup code
>   ppc/86xx: Clean up MPC8610 HPCD PCI setup code
>   ppc/85xx: Move to using fsl_setup_hose on MPC8572 DS
>   ppc/85xx: Move to using fsl_setup_hose on P1/P2 RDB
>   ppc/85xx: Move to using fsl_setup_hose on P2020 DS
>   ppc/85xx: Move to using fsl_setup_hose on TQM 85xx
>   ppc/8xxx: Remove is_fsl_pci_agent
>   ppc/85xx: Add tracking of TLB CAM usage
>   ppc/85xx: Make SPD DDR TLB setup code use dynamic entry allocation
>   ppc/85xx: Remove CONFIG_SYS_DDR_TLB_START
>   ppc/85xx: Make flash TLB entry determined at runtime on FSL boards
>   ppc: Added macro to test for specific SVR revision
>   ppc/85xx: Map boot page guarded for MP boot
>   ppc/p4080: Fix reporting of PME & FM clock frequencies
> 
> Li Yang (1):
>   fsl_law: add SRIO2 target id and law_size_bits() macro
> 
> Mingkai Hu (1):
>   ppc/85xx: Clean up MPC8536 DS PCI setup code
> 
> Sandeep Gopalpet (1):
>   NET: Move MDIO regs out of TSEC Space
> 
>  board/atum8548/atum8548.c |  162 ++-
>  board/freescale/mpc8536ds/mpc8536ds.c |  259 
> -
>  board/freescale/mpc8544ds/mpc8544ds.c |  249 
>  board/freescale/mpc8548cds/mpc8548cds.c   |  141 ++--
>  board/freescale/mpc8568mds/mpc8568mds.c   |  137 +--
>  board/freescale/mpc8569mds/mpc8569mds.c   |  100 +---
>  board/freescale/mpc8572ds/mpc8572ds.c |   16 +-
>  board/freescale/mpc8572ds/tlb.c   |2 +-
>  board/freescale/mpc8610hpcd/mpc8610hpcd.c |  199 +++---
>  board/freescale/p1_p2_rdb/p1_p2_rdb.c |2 +-
>  board/freescale/p1_p2_rdb/pci.c   |   10 +-
>  board/freescale/p1_p2_rdb/tlb.c   |2 +-
>  board/freescale/p2020ds/p2020ds.c |   14 +-
>  board/freescale/p2020ds/tlb.c |2 +-
>  board/tqc/tqm85xx/tqm85xx.c   |8 +-
>  cpu/mpc85xx/cpu_init.c|6 +
>  cpu/mpc85xx/fdt.c |   54 ++
>  cpu/mpc85xx/mp.c  |5 +-
>  cpu/mpc85xx/release.S |   17 ++-
>  cpu/mpc85xx/speed.c   |   12 +-
>  cpu/mpc85xx/start.S   |8 +-
>  cpu/mpc85xx/tlb.c |   76 -
>  cpu/mpc8xxx/ddr/ctrl_regs.c   |   40 +++--
>  cpu/mpc8xxx/ddr/options.c |1 +
>  cpu/mpc8xxx/pci_cfg.c |   47 +-
>  drivers/net/tsec.c|   21 +--
>  drivers/pci/fsl_pci_init.c|9 +
>  include/asm-ppc/config.h  |   13 ++
>  include/asm-ppc/fsl_ddr_sdram.h   |8 +-
>  include/asm-ppc/fsl_law.h |3 +
>  include/asm-ppc/fsl_pci.h |5 +-
>  include/asm-ppc/global_data.h |3 +
>  include/asm-ppc/immap_83xx.h  |8 +-
>  include/asm-ppc/immap_85xx.h  |  171 +++
>  include/asm-ppc/immap_86xx.h  |8 +-
>  include/asm-ppc/mmu.h |2 +
>  include/asm-ppc/processor.h   |3 +
>  include/configs/ATUM8548.h|   18 +-
>  include/configs/MPC8569MDS.h  |4 +
>  include/configs/MPC8572DS.h   |1 -
>  include/configs/P1_P2_RDB.h   |2 -
>  include/configs/P2020DS.h |1 -
>  include/tsec.h|   52 ---
>  43 files changed, 885 insertions(+), 1016 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

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Re: [U-Boot] [GIT PULL] please pull u-boot-mpc83xx

[Wolfgang Denk]

Dear Kim Phillips,

In message <20100107191507.54632118.kim.phill...@freescale.com> you wrote:
> 
> Please pull support for 8315rdb nand boot, the esd VME-CADDY/2, and
> some other fixes:
> 
> The following changes since commit 6ca9da4d42aeb43df5ef29f7d0518009df583b2f:
>   Wolfgang Denk (1):
> Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-mpc83xx.git master
> 
> Anton Vorontsov (1):
>   mpc83xx: Add NAND boot support for MPC8315E-RDB boards
> 
> Heiko Schocher (1):
>   mpc83xx: add support configure bus parking
> 
> Reinhard Arlt (2):
>   mpc83xx: Add support for MPC8349 esd caddy2
>   mpc83xx: vme8349: Fix power up reset sequence for tsi148
> 
> Stefan Roese (1):
>   mpc83xx: spd_sdram.c: Disable memory controller before initializing
> 
>  MAINTAINERS   |1 +
>  MAKEALL   |2 +
>  Makefile  |9 +-
>  board/esd/vme8349/pci.c   |   33 --
>  board/esd/vme8349/vme8349.c   |  195 
> -
>  board/esd/vme8349/vme8349pin.h|   36 ++
>  board/freescale/mpc8315erdb/config.mk |8 ++
>  board/freescale/mpc8315erdb/mpc8315erdb.c |   42 ++
>  board/freescale/mpc8315erdb/sdram.c   |9 ++-
>  cpu/mpc83xx/cpu_init.c|   12 ++
>  cpu/mpc83xx/spd_sdram.c   |9 ++
>  doc/README.mpc8315erdb|   29 -
>  include/configs/MPC8315ERDB.h |   95 +++---
>  include/configs/kmeter1.h |8 ++
>  include/configs/vme8349.h |   98 --
>  15 files changed, 455 insertions(+), 131 deletions(-)
>  create mode 100644 board/esd/vme8349/vme8349pin.h

Applied, thanks.

Best regards,

Wolfgang Denk

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Re: [U-Boot] Pull request: u-boot-usb

[Wolfgang Denk]

Dear Remy Bohmer,

In message <3efb10971001090201w17b02f49me80d823043833...@mail.gmail.com> you 
wrote:
> The following changes since commit
> 6ca9da4d42aeb43df5ef29f7d0518009df583b2f:
>   Wolfgang Denk (1):
> Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-usb.git master
> 
> Ajay Kumar Gupta (4):
>   DA830: Add pinmux for USB0_DRVVBUS
>   DA8xx: Add GPIO register definitions
>   DA8xx: Add MUSB host support
>   DA830: Add usb config
> 
> Bryan Wu (4):
>   usb: musb: make fifo support configurable
>   usb: musb: make multipoint optional
>   usb: musb: change rxcsr register from write to read/modify/write
>   usb: musb: add support for Blackfin MUSB
> 
> Chris Zhang (3):
>   Fix EHCI port reset.
>   Add ppc440epx USB ehci support.
>   Adds EHCI definitions to sequoia board configuration file.
> 
> Mike Frysinger (1):
>   usb: musb: make sure the register layout is packed
> 
> Sanjeev Premi (1):
>   omap3: fix compile warning
> 
>  board/davinci/da830evm/da830evm.c   |8 +
>  drivers/usb/host/Makefile   |1 +
>  drivers/usb/host/ehci-hcd.c |3 +
>  drivers/usb/host/ehci-ppc4xx.c  |   48 +
>  drivers/usb/musb/Makefile   |2 +
>  drivers/usb/musb/blackfin_usb.c |  143 +++
>  drivers/usb/musb/blackfin_usb.h |   99 ++
>  drivers/usb/musb/da8xx.c|  139 ++
>  drivers/usb/musb/da8xx.h|  103 +++
>  drivers/usb/musb/musb_core.c|   18 ++-
>  drivers/usb/musb/musb_core.h|   18 ++-
>  drivers/usb/musb/musb_hcd.c |   26 +++-
>  drivers/usb/musb/musb_hcd.h |4 +-
>  drivers/usb/musb/omap3.c|3 +
>  include/asm-arm/arch-davinci/gpio_defs.h|   14 ++
>  include/asm-blackfin/mach-common/bits/usb.h |  264 
> +++
>  include/configs/da830evm.h  |   38 -
>  include/configs/sequoia.h   |   16 ++-
>  include/usb.h   |3 +-
>  19 files changed, 935 insertions(+), 15 deletions(-)
>  create mode 100644 drivers/usb/host/ehci-ppc4xx.c
>  create mode 100644 drivers/usb/musb/blackfin_usb.c
>  create mode 100644 drivers/usb/musb/blackfin_usb.h
>  create mode 100644 drivers/usb/musb/da8xx.c
>  create mode 100644 drivers/usb/musb/da8xx.h
>  create mode 100644 include/asm-blackfin/mach-common/bits/usb.h

Applied, thanks.

Best regards,

Wolfgang Denk

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] Pull request: nand flash

[Wolfgang Denk]

Dear Scott Wood,

In message <2010080302.ga...@loki.buserror.net> you wrote:
> The following changes since commit 6ca9da4d42aeb43df5ef29f7d0518009df583b2f:
>   Wolfgang Denk (1):
> Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-nand-flash.git master
> 
> Nick Thompson (1):
>   Davinci: davinci_nand.c performance enhancments
> 
> Sanjeev Premi (1):
>   onenand: Fix compile errors due to FlexOneNAND
> 
>  common/env_onenand.c|9 ++-
>  drivers/mtd/nand/davinci_nand.c |  200 
> ---
>  2 files changed, 154 insertions(+), 55 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] ARM pull request

[Wolfgang Denk]

Dear Tom,

In message <4b44dbb6.9030...@windriver.com> you wrote:
> Wolfgang,
> Please pull these changes from arm/master.
> Tom
> 
> The following changes since commit 87d93a1ba2ae23550e1370adb7a3b00af0831165:
>Wolfgang Wegner (1):
>  move prototypes for gunzip() and zunzip() to common.h
> 
> are available in the git repository at:
> 
>git://git.denx.de/u-boot-arm master
> 
> Grazvydas Ignotas (2):
>TWL4030: make LEDs selectable for twl4030_led_init()
>pandora: don't enable VAUX3, VDAC and VPLL2 regulators
> 
> Nick Thompson (3):
>Davinci: Table driven pinmux configuration
>Davinci: Configurable NAND chip selects
>Davinci: NAND enable ECC even when not in NAND boot mode
> 
> Robert P. J. Day (1):
>Remove superfluous uses of V_PROMPT macro.
> 
> Tom Rix (1):
>ARM Update mach-types
> 
>   board/davinci/common/misc.c  |   31 ++
>   board/davinci/common/misc.h  |   13 +
>   board/logicpd/zoom1/zoom1.c  |2 +-
>   board/logicpd/zoom2/zoom2.c  |2 +-
>   board/overo/overo.c  |2 +-
>   board/pandora/pandora.c  |3 +-
>   board/ti/beagle/beagle.c |2 +-
>   board/timll/devkit8000/devkit8000.c  |2 +-
>   drivers/misc/twl4030_led.c   |   18 +-
>   drivers/mtd/nand/davinci_nand.c  |   27 +-
>   include/asm-arm/arch-davinci/emif_defs.h |   13 +-
>   include/asm-arm/mach-types.h |  631 
> +-
>   include/configs/apollon.h|4 +-
>   include/configs/davinci_dm355evm.h   |1 +
>   include/configs/davinci_dm355leopard.h   |1 +
>   include/configs/davinci_dm365evm.h   |1 +
>   include/configs/davinci_dm6467evm.h  |1 +
>   include/configs/davinci_dvevm.h  |1 +
>   include/configs/davinci_schmoogie.h  |1 +
>   include/configs/davinci_sffsdr.h |1 +
>   include/configs/davinci_sonata.h |1 +
>   include/configs/omap2420h4.h |8 +-
>   include/configs/omap3_beagle.h   |4 +-
>   include/configs/omap3_evm.h  |4 +-
>   include/configs/omap3_overo.h|4 +-
>   include/configs/omap3_pandora.h  |4 +-
>   include/configs/omap3_sdp3430.h  |3 +-
>   include/configs/omap3_zoom1.h|4 +-
>   include/twl4030.h|6 +-
>   29 files changed, 723 insertions(+), 72 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] [PATCH v6] TI DaVinci: Driver for the davinci SPI controller

[Paulraj, Sandeep]

> 
> Sudhakar Rajashekhara wrote:
> > From: Sekhar Nori 
> >
> > This adds a driver for the SPI controller found on davinci
> > based SoCs from Texas Instruments.
> >
> > Signed-off-by: Sekhar Nori 
> > Signed-off-by: Sudhakar Rajashekhara 
> > ---
> > Modification from the previous version:
> >  1. One unused member (mr) has been removed from davinci_spi_slave
> > structure.
> >
> Thanks for taking care of this.
> Ack-ed
> Tom

Wolfgang, Tom,

We don't have a repository for SPI as such. If it is OK I would like to add 
this to my u-boot-ti tree.

Thanks,
Sandeep

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Re: [U-Boot] [PATCH v6] TI DaVinci: Driver for the davinci SPI controller

[Tom]

Paulraj, Sandeep wrote:
> 
>> Sudhakar Rajashekhara wrote:
>>> From: Sekhar Nori 
>>>
>>> This adds a driver for the SPI controller found on davinci
>>> based SoCs from Texas Instruments.
>>>
>>> Signed-off-by: Sekhar Nori 
>>> Signed-off-by: Sudhakar Rajashekhara 
>>> ---
>>> Modification from the previous version:
>>>  1. One unused member (mr) has been removed from davinci_spi_slave
>>> structure.
>>>
>> Thanks for taking care of this.
>> Ack-ed
>> Tom
> 
> Wolfgang, Tom,
> 
> We don't have a repository for SPI as such. If it is OK I would like to add 
> this to my u-boot-ti tree.

OK with me.
Tom

> 
> Thanks,
> Sandeep
> 

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Re: [U-Boot] s5pc1xx: update cache routines

[Minkyu Kang]

2009/12/18 Minkyu Kang :
> Because of v7_flush_dcache_all is moved to omap3/cache.S
> and s5pc110 needs cache routines, need to update s5pc1xx cache routines.
>
> l2_cache_enable and l2_caceh_disable are moved from cache.c to cache.S
> and invalidate_dcache is modified for SoC specific.
>
> Signed-off-by: Minkyu Kang 
> ---
>  cpu/arm_cortexa8/s5pc1xx/Makefile        |    4 +-
>  cpu/arm_cortexa8/s5pc1xx/cache.S         |  120 
> ++
>  cpu/arm_cortexa8/s5pc1xx/cache.c         |   43 ---
>  include/asm-arm/arch-s5pc1xx/sys_proto.h |   32 
>  include/configs/smdkc100.h               |    2 -
>  5 files changed, 154 insertions(+), 47 deletions(-)
>  create mode 100644 cpu/arm_cortexa8/s5pc1xx/cache.S
>  delete mode 100644 cpu/arm_cortexa8/s5pc1xx/cache.c
>  create mode 100644 include/asm-arm/arch-s5pc1xx/sys_proto.h
>
> diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile 
> b/cpu/arm_cortexa8/s5pc1xx/Makefile
> index e08d9d8..4f922e6 100644
> --- a/cpu/arm_cortexa8/s5pc1xx/Makefile
> +++ b/cpu/arm_cortexa8/s5pc1xx/Makefile
> @@ -28,9 +28,9 @@ include $(TOPDIR)/config.mk
>
>  LIB    = $(obj)lib$(SOC).a
>
> -SOBJS  = reset.o
> +SOBJS  = cache.o
> +SOBJS  += reset.o
>
> -COBJS  += cache.o
>  COBJS  += clock.o
>  COBJS  += cpu_info.o
>  COBJS  += timer.o
> diff --git a/cpu/arm_cortexa8/s5pc1xx/cache.S 
> b/cpu/arm_cortexa8/s5pc1xx/cache.S
> new file mode 100644
> index 000..23f527a
> --- /dev/null
> +++ b/cpu/arm_cortexa8/s5pc1xx/cache.S
> @@ -0,0 +1,120 @@
> +/*
> + * Copyright (C) 2009 Samsung Electronics
> + * Minkyu Kang 
> + *
> + * based on cpu/arm_cortexa8/omap3/cache.S
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include 
> +
> +.align 5
> +.global invalidate_dcache
> +.global l2_cache_enable
> +.global l2_cache_disable
> +
> +/*
> + * invalidate_dcache()
> + * Invalidate the whole D-cache.
> + *
> + * Corrupted registers: r0-r5, r7, r9-r11
> + */
> +invalidate_dcache:
> +       stmfd   r13!, {r0 - r5, r7, r9 - r12, r14}
> +
> +       cmp     r0, #0xC100                     @ check if the cpu is s5pc100
> +
> +       beq     finished_inval                  @ s5pc100 doesn't need this
> +                                               @ routine
> +       mrc     p15, 1, r0, c0, c0, 1           @ read clidr
> +       ands    r3, r0, #0x700              @ extract loc from clidr
> +       mov     r3, r3, lsr #23                 @ left align loc bit field
> +       beq     finished_inval                  @ if loc is 0, then no need to
> +                                               @ clean
> +       mov     r10, #0                         @ start clean at cache level 0
> +inval_loop1:
> +       add     r2, r10, r10, lsr #1            @ work out 3x current cache
> +                                               @ level
> +       mov     r1, r0, lsr r2                  @ extract cache type bits from
> +                                               @ clidr
> +       and     r1, r1, #7                      @ mask of the bits for current
> +                                               @ cache only
> +       cmp     r1, #2                          @ see what cache we have at
> +                                               @ this level
> +       blt     skip_inval                      @ skip if no cache, or just
> +                                               @ i-cache
> +       mcr     p15, 2, r10, c0, c0, 0          @ select current cache level
> +                                               @ in cssr
> +       mov     r2, #0                          @ operand for mcr SBZ
> +       mcr     p15, 0, r2, c7, c5, 4           @ flush prefetch buffer to
> +                                               @ sych the new cssr&csidr,
> +                                               @ with armv7 this is 'isb',
> +                                               @ but we compile with armv5
> +       mrc     p15, 1, r1, c0, c0, 0           @ read the new csidr
> +       and     r2, r1, #7                      @ extract the length of the
> +                                               @ cache lines
> +       add     r2, r2, #4                      @ add 4 (line length o

[U-Boot] Please pull u-boot-samsung/master

[Minkyu Kang]

Dear Tom,

The following changes since commit 33bf447477ff38eda46529b346677856b53e0f87:
  kevin.morf...@fearnside-systems.co.uk (1):
Add a unified s3c24x0 header file

are available in the git repository at:

  git://git.denx.de/u-boot-samsung master

Minkyu Kang (1):
  s5pc1xx: update cache routines

Seunghyeon Rhee (1):
  samsung: fix DMC1_MEM_CFG for s3c64xx

 cpu/arm_cortexa8/s5pc1xx/Makefile  |4 +-
 cpu/arm_cortexa8/s5pc1xx/cache.S   |  120 
 include/asm-arm/arch-s3c64xx/s3c6400.h |4 +-
 .../asm-arm/arch-s5pc1xx/sys_proto.h   |   27 ++---
 include/configs/smdkc100.h |2 -
 5 files changed, 132 insertions(+), 25 deletions(-)
 create mode 100644 cpu/arm_cortexa8/s5pc1xx/cache.S
 rename cpu/arm_cortexa8/s5pc1xx/cache.c => 
include/asm-arm/arch-s5pc1xx/sys_proto.h (61%)
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[U-Boot] [PATCH 0/9] Add support for i.MX25 SOC and TX25 board

[John Rigby]

The i.MX25 has the same ARM core and shares some ip blocks
with i.MX27 but also borrows from i.MX31.

The TX25 is an i.MX25 based board.  It has only NAND flash
so this port includes nand_spl and mtd/nand changes for
the nand controller in the i.MX25.

Booting from nand also required adding nand_spl boot support 
for arm926ejs.

Support is also included for serial and ethernet.

This port was made possible by a donation of hardware by
DENX Software Engineering.

John Rigby (8):
  mxc_serial replace platform specific clock
  arm926ejs: add nand_spl boot support
  Add v1.1 support to nand_spl fsl nfc driver
  Nand mxc_nand add v1.1 controller support
  fec_mxc: cleanup and factor out imx27 dependencies
  Add support for Freescale MX25 SOC
  fec_mxc: add imx25 support
  Add support for KARO TX25 board

Wolfgang Denk (1):
  env_nand.c: print error message and fail gracefully

 MAINTAINERS  |4 +
 Makefile |4 +
 board/karo/tx25/Makefile |   51 +++
 board/karo/tx25/config.mk|5 +
 board/karo/tx25/lowlevel_init.S  |  131 +++
 board/karo/tx25/tx25.c   |  178 +
 common/env_nand.c|9 +
 cpu/arm926ejs/mx25/Makefile  |   46 +++
 cpu/arm926ejs/mx25/generic.c |  263 +
 cpu/arm926ejs/mx25/reset.c   |   56 +++
 cpu/arm926ejs/mx25/timer.c   |  187 +
 cpu/arm926ejs/mx27/generic.c |5 +
 cpu/arm926ejs/start.S|   42 ++-
 drivers/mtd/nand/mxc_nand.c  |  604 ++
 drivers/net/fec_mxc.c|   57 ++-
 drivers/net/fec_mxc.h|   32 ++-
 drivers/serial/serial_mxc.c  |   16 +-
 include/asm-arm/arch-mx25/clock.h|   36 ++
 include/asm-arm/arch-mx25/imx-regs.h |  330 
 include/asm-arm/arch-mx25/imx25-pinmux.h |  421 +
 include/asm-arm/arch-mx27/clock.h|3 +
 include/asm-arm/arch-mx27/imx-regs.h |   13 +
 include/asm-arm/arch-mx31/mx31.h |1 +
 include/configs/imx27lite.h  |1 +
 include/configs/mx31pdk.h|4 +
 include/configs/tx25.h   |  178 +
 include/fsl_nfc.h|   78 -
 nand_spl/board/karo/tx25/Makefile|   78 
 nand_spl/board/karo/tx25/config.mk   |1 +
 nand_spl/board/karo/tx25/u-boot.lds  |   58 +++
 nand_spl/nand_boot_fsl_nfc.c |   74 +++-
 31 files changed, 2838 insertions(+), 128 deletions(-)
 create mode 100644 board/karo/tx25/Makefile
 create mode 100644 board/karo/tx25/config.mk
 create mode 100644 board/karo/tx25/lowlevel_init.S
 create mode 100644 board/karo/tx25/tx25.c
 create mode 100644 cpu/arm926ejs/mx25/Makefile
 create mode 100644 cpu/arm926ejs/mx25/generic.c
 create mode 100644 cpu/arm926ejs/mx25/reset.c
 create mode 100644 cpu/arm926ejs/mx25/timer.c
 create mode 100644 include/asm-arm/arch-mx25/clock.h
 create mode 100644 include/asm-arm/arch-mx25/imx-regs.h
 create mode 100644 include/asm-arm/arch-mx25/imx25-pinmux.h
 create mode 100644 include/configs/tx25.h
 create mode 100644 nand_spl/board/karo/tx25/Makefile
 create mode 100644 nand_spl/board/karo/tx25/config.mk
 create mode 100644 nand_spl/board/karo/tx25/u-boot.lds

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[U-Boot] [PATCH 2/9] arm926ejs: add nand_spl boot support

[John Rigby]

Add CONFIG_PRELOADER/CONFIG_NAND_SPL support for nand booting
to arm926ejs/start.S

This is derived from CONFIG_PRELOADER support in arm1136/start.S

Signed-off-by: John Rigby 
---
 cpu/arm926ejs/start.S |   42 +-
 1 files changed, 41 insertions(+), 1 deletions(-)

diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S
index 4421b6a..3b81151 100644
--- a/cpu/arm926ejs/start.S
+++ b/cpu/arm926ejs/start.S
@@ -53,6 +53,27 @@
 .globl _start
 _start:
b   reset
+#ifdef CONFIG_PRELOADER
+/* No exception handlers in preloader */
+   ldr pc, _hang
+   ldr pc, _hang
+   ldr pc, _hang
+   ldr pc, _hang
+   ldr pc, _hang
+   ldr pc, _hang
+   ldr pc, _hang
+
+_hang:
+   .word   do_hang
+/* pad to 64 byte boundary */
+   .word   0x12345678
+   .word   0x12345678
+   .word   0x12345678
+   .word   0x12345678
+   .word   0x12345678
+   .word   0x12345678
+   .word   0x12345678
+#else
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@@ -76,6 +97,7 @@ _irq:
 _fiq:
.word fiq
 
+#endif /* CONFIG_PRELOADER */
.balignl 16,0xdeadbeef
 
 
@@ -150,7 +172,6 @@ relocate:   /* relocate U-Boot to 
RAM   */
ldr r1, _TEXT_BASE  /* test if we run from flash or RAM */
cmp r0, r1  /* don't reloc during debug */
beq stack_setup
-
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2  /* r2 <- size of armboot*/
@@ -166,11 +187,14 @@ copy_loop:
/* Set up the stack */
 stack_setup:
ldr r0, _TEXT_BASE  /* upper 128 KiB: relocated uboot   */
+   sub sp, r0, #128/* leave 32 words for abort-stack   */
+#ifndef CONFIG_PRELOADER
sub r0, r0, #CONFIG_SYS_MALLOC_LEN  /* malloc area  
*/
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo 
   */
 #ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 #endif
+#endif /* CONFIG_PRELOADER */
sub sp, r0, #12 /* leave 3 words for abort-stack*/
bic sp, r0, #7  /* 8-byte align stack for ABI 
compliance */
 
@@ -179,6 +203,7 @@ clear_bss:
ldr r1, _bss_end/* stop here*/
mov r2, #0x /* clear*/
 
+#ifndef CONFIG_PRELOADER
 clbss_l:strr2, [r0]/* clear loop...*/
add r0, r0, #4
cmp r0, r1
@@ -186,11 +211,16 @@ clbss_l:str   r2, [r0]/* clear 
loop...*/
 
bl coloured_LED_init
bl red_LED_on
+#endif /* CONFIG_PRELOADER */
 
ldr pc, _start_armboot
 
 _start_armboot:
+#ifdef CONFIG_NAND_SPL
+   .word nand_boot
+#else
.word start_armboot
+#endif /* CONFIG_NAND_SPL */
 
 
 /*
@@ -231,6 +261,7 @@ cpu_init_crit:
mov pc, lr  /* back to my caller */
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 
+#ifndef CONFIG_PRELOADER
 /*
  *
  *
@@ -332,10 +363,18 @@ cpu_init_crit:
.macro get_fiq_stack@ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
+#endif /* CONFIG_PRELOADER */
 
 /*
  * exception handlers
  */
+#ifdef CONFIG_PRELOADER
+   .align  5
+do_hang:
+   ldr sp, _TEXT_BASE  /* switch to abort stack */
+1:
+   bl  1b  /* hang and never return */
+#else  /* !CONFIG_PRELOADER */
.align  5
 undefined_instruction:
get_bad_stack
@@ -398,3 +437,4 @@ fiq:
bl  do_fiq
 
 #endif
+#endif /* CONFIG_PRELOADER */
-- 
1.6.4.2.236.gf324c

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[U-Boot] [PATCH 3/9] Add v1.1 support to nand_spl fsl nfc driver

[John Rigby]

MX25 has a different version of the fsl_nfc
flash controller known as version 1.1.

Add support to the nand_spl fsl_nfc driver
keyed off CONFIG_NAND_NFC_V1_1.

Also add a define CONFIG_NAND_NFC_V1 to the only
existing user configs/mx31pdk.h.

Signed-off-by: John Rigby 
Signed-off-by: Wolfgang Denk 
---
 include/configs/mx31pdk.h|4 ++
 include/fsl_nfc.h|   78 +++--
 nand_spl/nand_boot_fsl_nfc.c |   74 +++
 3 files changed, 128 insertions(+), 28 deletions(-)

diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index fb61432..1608e54 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -48,6 +48,10 @@
 #define CONFIG_SKIP_RELOCATE_UBOOT
 #endif
 
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NAND_MXC_V1
+#endif
+
 /*
  * Size of malloc() pool
  */
diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h
index da5be37..68d9418 100644
--- a/include/fsl_nfc.h
+++ b/include/fsl_nfc.h
@@ -1,5 +1,4 @@
 /*
- *
  * (c) 2009 Magnus Lilja 
  *
  * See file CREDITS for list of people who contributed to this
@@ -25,21 +24,49 @@
 #define __FSL_NFC_H
 
 /*
+ * TODO: Use same register defs for nand_spl mxc nand driver
+ * and mtd mxc nand driver.
+ *
  * Register map and bit definitions for the Freescale NAND Flash
- * Controller present in i.MX31 and other devices.
+ * Controller present in various i.MX devices.
+ *
+ * MX31 and MX27 have version 1 which has
+ * 4 512 byte main buffers and
+ * 4 16 byte spare buffers
+ * to support up to 2K byte pagesize nand.
+ * Reading or writing a 2K page requires 4 FDI/FDO cycles.
+ *
+ * MX25 has version 1.1 which has
+ * 8 512 byte main buffers and
+ * 8 64 byte spare buffers
+ * to support up to 4K byte pagesize nand.
+ * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
+ *  Also some of registers are moved and/or changed meaning as seen below.
  */
+#if defined(CONFIG_NAND_MXC_V1)
+#define NAND_MXC_NR_BUFS   4
+#define NAND_MXC_SPARE_BUF_SIZE16
+#define NAND_MXC_REG_OFFSET0xe00
+#define NAND_MXC_2K_MULTI_CYCLE1
+#elif defined(CONFIG_NAND_MXC_V1_1)
+#define NAND_MXC_NR_BUFS   8
+#define NAND_MXC_SPARE_BUF_SIZE64
+#define NAND_MXC_REG_OFFSET0x1e00
+#else
+#error "define CONFIG_NAND_MXC_VXXX to use the mxc spl_nand driver"
+#endif
 
 struct fsl_nfc_regs {
-   u32 main_area0[128]; /* @0x000 */
-   u32 main_area1[128];
-   u32 main_area2[128];
-   u32 main_area3[128];
-   u32 spare_area0[4];
-   u32 spare_area1[4];
-   u32 spare_area2[4];
-   u32 spare_area3[4];
-   u32 reserved1[64 - 16 + 64 * 5];
-   u16 bufsiz; /* @ 0xe00 */
+   u8 main_area[NAND_MXC_NR_BUFS][512];
+   u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
+   /*
+* reserved size is offset of nfc registers
+* minus total main and spare sizes
+*/
+   u8 reserved1[NAND_MXC_REG_OFFSET
+   - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
+#if defined(CONFIG_NAND_MXC_V1)
+   u16 bufsiz;
u16 reserved2;
u16 buffer_address;
u16 flash_add;
@@ -54,6 +81,30 @@ struct fsl_nfc_regs {
u16 nand_flash_wr_pr_st;
u16 nand_flash_config1;
u16 nand_flash_config2;
+#elif defined(CONFIG_NAND_MXC_V1_1)
+   u16 reserved2[2];
+   u16 buffer_address;
+   u16 flash_add;
+   u16 flash_cmd;
+   u16 configuration;
+   u16 ecc_status_result;
+   u16 ecc_status_result2;
+   u16 spare_area_size;
+   u16 nf_wr_prot;
+   u16 reserved3[2];
+   u16 nand_flash_wr_pr_st;
+   u16 nand_flash_config1;
+   u16 nand_flash_config2;
+   u16 reserved4;
+   u16 unlock_start_blk_add0;
+   u16 unlock_end_blk_add0;
+   u16 unlock_start_blk_add1;
+   u16 unlock_end_blk_add1;
+   u16 unlock_start_blk_add2;
+   u16 unlock_end_blk_add2;
+   u16 unlock_start_blk_add3;
+   u16 unlock_end_blk_add3;
+#endif
 };
 
 /*
@@ -98,6 +149,9 @@ struct fsl_nfc_regs {
  */
 #define NFC_INT0x8000
 
+#ifdef CONFIG_NAND_MXC_V1_1
+#define NFC_4_8N_ECC   (1 << 0)
+#endif
 #define NFC_SP_EN  (1 << 2)
 #define NFC_ECC_EN (1 << 3)
 #define NFC_INT_MSK(1 << 4)
diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c
index a9df2a8..02d8330 100644
--- a/nand_spl/nand_boot_fsl_nfc.c
+++ b/nand_spl/nand_boot_fsl_nfc.c
@@ -26,13 +26,17 @@
 
 #include 
 #include 
+#ifdef CONFIG_MX31
 #include 
+#else
+#include 
+#endif
 #include 
 #include 
 
-static struct fsl_nfc_regs *nfc;
+struct fsl_nfc_regs *nfc;
 
-static void nfc_wait_ready(void)
+void nfc_wait_ready(void)
 {
uint32_t tmp;
 
@@ -45,13 +49,35 @@ static void nfc_wait_ready(void)
writew(tmp, &nfc->nand_flash_config2);
 }
 
-static void nfc_nand_init(void)
+void nfc_nand_init(void)
 {
+#if d

[U-Boot] [PATCH 4/9] Nand mxc_nand add v1.1 controller support

[John Rigby]

Add support for version 1.1 of the nfc nand flash
controller which is on the i.mx25 soc.

Use CONFIG_NAND_MXC_V1 and CONFIG_NAND_MXC_V1_1 to
differentiate between the two supported versions.

Add a define CONFIG_NAND_MXC_V1 to imx27lite board config.

Also factor out some soc specific nand geometry config
into a new inline routine and a couple of defines:
mxc_get_nfc_info
IMX_NFC_IS_16BIT
IMX_NFC_IS_2KPAGE

Added to imx-regs.h.

Signed-off-by: John Rigby 
Earlier-version-signed-off-by: Wolfgang Denk 
---
 drivers/mtd/nand/mxc_nand.c  |  604 ++
 include/asm-arm/arch-mx27/imx-regs.h |   13 +
 include/configs/imx27lite.h  |1 +
 3 files changed, 546 insertions(+), 72 deletions(-)

diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index eb0323f..e83420f 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -22,27 +22,55 @@
 #include 
 #include 
 #include 
-#ifdef CONFIG_MX27
 #include 
-#endif
 
 #define DRIVER_NAME "mxc_nand"
 
+/*
+ * TODO: Use same register defs here as nand_spl mxc nand driver.
+ */
+/*
+ * Register map and bit definitions for the Freescale NAND Flash Controller
+ * present in various i.MX devices.
+ *
+ * MX31 and MX27 have version 1 which has
+ * 4 512 byte main buffers and
+ * 4 16 byte spare buffers
+ * to support up to 2K byte pagesize nand.
+ * Reading or writing a 2K page requires 4 FDI/FDO cycles.
+ *
+ * MX25 has version 1.1 which has
+ * 8 512 byte main buffers and
+ * 8 64 byte spare buffers
+ * to support up to 4K byte pagesize nand.
+ * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
+ *  Also some of registers are moved and/or changed meaning as seen below.
+ */
+#if defined(CONFIG_NAND_MXC_V1)
+#define NAND_MXC_NR_BUFS   4
+#define NAND_MXC_SPARE_BUF_SIZE16
+#define NAND_MXC_REG_OFFSET0xe00
+#define is_mxc_nfc_11()0
+#elif defined(CONFIG_NAND_MXC_V1_1)
+#define NAND_MXC_NR_BUFS   8
+#define NAND_MXC_SPARE_BUF_SIZE64
+#define NAND_MXC_REG_OFFSET0x1e00
+#define is_mxc_nfc_11()1
+#else
+#error "define CONFIG_NAND_MXC_VXXX to use mtd mxc nand driver"
+#endif
 struct nfc_regs {
-/* NFC RAM BUFFER Main area 0 */
-   uint8_t main_area0[0x200];
-   uint8_t main_area1[0x200];
-   uint8_t main_area2[0x200];
-   uint8_t main_area3[0x200];
-/* SPARE BUFFER Spare area 0 */
-   uint8_t spare_area0[0x10];
-   uint8_t spare_area1[0x10];
-   uint8_t spare_area2[0x10];
-   uint8_t spare_area3[0x10];
-   uint8_t pad[0x5c0];
-/* NFC registers */
+   uint8_t main_area[NAND_MXC_NR_BUFS][0x200];
+   uint8_t spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
+   /*
+* reserved size is offset of nfc registers
+* minus total main and spare sizes
+*/
+   uint8_t reserved1[NAND_MXC_REG_OFFSET
+   - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
+#if defined(CONFIG_NAND_MXC_V1)
uint16_t nfc_buf_size;
-   uint16_t reserved;
+   uint16_t reserved2;
uint16_t nfc_buf_addr;
uint16_t nfc_flash_addr;
uint16_t nfc_flash_cmd;
@@ -56,6 +84,30 @@ struct nfc_regs {
uint16_t nfc_nf_wrprst;
uint16_t nfc_config1;
uint16_t nfc_config2;
+#elif defined(CONFIG_NAND_MXC_V1_1)
+   uint16_t reserved2[2];
+   uint16_t nfc_buf_addr;
+   uint16_t nfc_flash_addr;
+   uint16_t nfc_flash_cmd;
+   uint16_t nfc_config;
+   uint16_t nfc_ecc_status_result;
+   uint16_t nfc_ecc_status_result2;
+   uint16_t nfc_spare_area_size;
+   uint16_t nfc_wrprot;
+   uint16_t reserved3[2];
+   uint16_t nfc_nf_wrprst;
+   uint16_t nfc_config1;
+   uint16_t nfc_config2;
+   uint16_t reserved4;
+   uint16_t nfc_unlockstart_blkaddr;
+   uint16_t nfc_unlockend_blkaddr;
+   uint16_t nfc_unlockstart_blkaddr1;
+   uint16_t nfc_unlockend_blkaddr1;
+   uint16_t nfc_unlockstart_blkaddr2;
+   uint16_t nfc_unlockend_blkaddr2;
+   uint16_t nfc_unlockstart_blkaddr3;
+   uint16_t nfc_unlockend_blkaddr3;
+#endif
 };
 
 /*
@@ -100,6 +152,11 @@ struct nfc_regs {
  */
 #define NFC_INT0x8000
 
+#ifdef CONFIG_NAND_MXC_V1_1
+#define NFC_4_8N_ECC   (1 << 0)
+#else
+#define NFC_4_8N_ECC   0
+#endif
 #define NFC_SP_EN   (1 << 2)
 #define NFC_ECC_EN  (1 << 3)
 #define NFC_BIG (1 << 5)
@@ -119,6 +176,7 @@ struct mxc_nand_host {
int pagesize_2k;
int clk_act;
uint16_tcol_addr;
+   unsigned intpage_addr;
 };
 
 static struct mxc_nand_host mxc_host;
@@ -135,17 +193,37 @@ static struct mxc_nand_host *host = &mxc_host;
 #define SPARE_SINGLEBIT_ERROR 0x1
 
 /* OOB placement block for use with hardware ecc generation */
-#ifdef CONFIG_

[U-Boot] [PATCH 8/9] env_nand.c: print error message and fail gracefully

[John Rigby]

From: Wolfgang Denk 

env_nand.c would crash silently if a malloc() for the environment
buffers failed; make it print an error message and fail gracefully,
i. e. use the default environment then.

Signed-off-by: Wolfgang Denk 
---
 common/env_nand.c |9 +
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/common/env_nand.c b/common/env_nand.c
index ca631af..a5166cb 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -298,6 +298,15 @@ void env_relocate_spec (void)
tmp_env1 = (env_t *) malloc(CONFIG_ENV_SIZE);
tmp_env2 = (env_t *) malloc(CONFIG_ENV_SIZE);
 
+   if ((tmp_env1 == NULL) || (tmp_env2 == NULL)) {
+   puts("Can't allocate buffers for environment\n");
+   if (tmp_env1)
+   free (tmp_env1);
+   if (tmp_env2)
+   free (tmp_env2);
+   return use_default();
+   }
+
if (readenv(CONFIG_ENV_OFFSET, (u_char *) tmp_env1))
puts("No Valid Environment Area Found\n");
if (readenv(CONFIG_ENV_OFFSET_REDUND, (u_char *) tmp_env2))
-- 
1.6.4.2.236.gf324c

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[U-Boot] [PATCH 7/9] fec_mxc: add imx25 support

[John Rigby]

Use RMII for imx25
Add code to init gasket that enables RMII

Signed-off-by: John Rigby 
---
 drivers/net/fec_mxc.c |   31 ++-
 drivers/net/fec_mxc.h |   32 ++--
 include/asm-arm/arch-mx25/clock.h |1 +
 3 files changed, 61 insertions(+), 3 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index b5619eb..f109485 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -347,6 +347,34 @@ static int fec_open(struct eth_device *edev)
 */
writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
&fec->eth->ecntrl);
+#ifdef CONFIG_MX25
+   udelay(100);
+   /*
+* setup the MII gasket for RMII mode
+*/
+
+   /* disable the gasket */
+   writew(0, &fec->eth->miigsk_enr);
+
+   /* wait for the gasket to be disabled */
+   while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
+   udelay(2);
+
+   /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
+   writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
+
+   /* re-enable the gasket */
+   writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
+
+   /* wait until MII gasket is ready */
+   int max_loops = 10;
+   while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
+   if (--max_loops <= 0) {
+   printf("WAIT for MII Gasket ready timed out\n");
+   break;
+   }
+   }
+#endif
 
miiphy_wait_aneg(edev);
miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR);
@@ -498,7 +526,8 @@ static void fec_halt(struct eth_device *dev)
 * Disable the Ethernet Controller
 * Note: this will also reset the BD index counter!
 */
-   writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, 
&fec->eth->ecntrl);
+   writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
+   &fec->eth->ecntrl);
fec->rbd_index = 0;
fec->tbd_index = 0;
debug("eth_halt: done\n");
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 6cb1bfc..5d0d69d 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -145,9 +145,17 @@ struct ethernet_regs {
uint32_t r_fdxfc;   /* MBAR_ETH + 0x2DC */
uint32_t ieee_r_octets_ok;  /* MBAR_ETH + 0x2E0 */
 
-   uint32_t res14[6];  /* MBAR_ETH + 0x2E4-2FC */
-
+   uint32_t res14[7];  /* MBAR_ETH + 0x2E4-2FC */
+
+#ifdef CONFIG_MX25
+   uint16_t miigsk_cfgr;   /* MBAR_ETH + 0x300 */
+   uint16_t res15[3];  /* MBAR_ETH + 0x302-306 */
+   uint16_t miigsk_enr;/* MBAR_ETH + 0x308 */
+   uint16_t res16[3];  /* MBAR_ETH + 0x30a-30e */
+   uint32_t res17[60]; /* MBAR_ETH + 0x300-3FF */
+#else
uint32_t res15[64]; /* MBAR_ETH + 0x300-3FF */
+#endif
 };
 
 #define FEC_IEVENT_HBERR   0x8000
@@ -196,6 +204,26 @@ struct ethernet_regs {
 #define FEC_ECNTRL_RESET   0x0001  /* reset the FEC */
 #define FEC_ECNTRL_ETHER_EN0x0002  /* enable the FEC */
 
+#ifdef CONFIG_MX25
+/* defines for MIIGSK */
+/* RMII frequency control: 0=50MHz, 1=5MHz */
+#define MIIGSK_CFGR_FRCONT (1 << 6)
+/* loopback mode */
+#define MIIGSK_CFGR_LBMODE (1 << 4)
+/* echo mode */
+#define MIIGSK_CFGR_EMODE  (1 << 3)
+/* MII gasket mode field */
+#define MIIGSK_CFGR_IF_MODE_MASK   (3 << 0)
+/* MMI/7-Wire mode */
+#define MIIGSK_CFGR_IF_MODE_MII(0 << 0)
+/* RMII mode */
+#define MIIGSK_CFGR_IF_MODE_RMII   (1 << 0)
+/* reflects MIIGSK Enable bit (RO) */
+#define MIIGSK_ENR_READY   (1 << 2)
+/* enable MIGSK (set by default) */
+#define MIIGSK_ENR_EN  (1 << 1)
+#endif
+
 /**
  * @brief Descriptor buffer alignment
  *
diff --git a/include/asm-arm/arch-mx25/clock.h 
b/include/asm-arm/arch-mx25/clock.h
index b0752e7..c59f588 100644
--- a/include/asm-arm/arch-mx25/clock.h
+++ b/include/asm-arm/arch-mx25/clock.h
@@ -30,6 +30,7 @@ ulong imx_get_perclk(int clk);
 ulong imx_get_ahbclk(void);
 
 #define imx_get_uartclk() imx_get_perclk(15)
+#define imx_get_fecclk() (imx_get_ahbclk()/2)
 
 
 #endif /* __ASM_ARCH_CLOCK_H */
-- 
1.6.4.2.236.gf324c

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[U-Boot] [PATCH 5/9] fec_mxc: cleanup and factor out imx27 dependencies

[John Rigby]

general cleanup
move clock init to cpu_eth_init in cpu/arm926ejs/mx27/generic.c
make MX27 specific phy init conditional on CONFIG_MX27
replace call to imx_get_ahbclk with one to imx_get_fecclk
and define imx_get_fecclk in include/asm-arm/arch-mx27/clock.h

Signed-off-by: John Rigby 
---
 cpu/arm926ejs/mx27/generic.c  |5 +
 drivers/net/fec_mxc.c |   28 +---
 include/asm-arm/arch-mx27/clock.h |1 +
 3 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c
index da05c55..30cf544 100644
--- a/cpu/arm926ejs/mx27/generic.c
+++ b/cpu/arm926ejs/mx27/generic.c
@@ -166,6 +166,11 @@ int print_cpuinfo (void)
 int cpu_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FEC_MXC)
+   struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+   /* enable FEC clock */
+   writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
+   writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
return fecmxc_initialize(bis);
 #else
return 0;
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 19116f2..b5619eb 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -151,7 +151,9 @@ static int miiphy_restart_aneg(struct eth_device *dev)
 * Wake up from sleep if necessary
 * Reset PHY, then delay 300ns
 */
+#ifdef CONFIG_MX27
miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF);
+#endif
miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
PHY_BMCR_RESET);
udelay(1000);
@@ -343,7 +345,8 @@ static int fec_open(struct eth_device *edev)
/*
 * Enable FEC-Lite controller
 */
-   writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
+   writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
+   &fec->eth->ecntrl);
 
miiphy_wait_aneg(edev);
miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR);
@@ -415,10 +418,10 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
 * and do not drop the Preamble.
 */
-   writelimx_get_ahbclk() / 100) + 2) / 5) << 1,
+   writelimx_get_fecclk() / 100) + 2) / 5) << 1,
&fec->eth->mii_speed);
debug("fec_init: mii_speed %#lx\n",
-   (((imx_get_ahbclk() / 100) + 2) / 5) << 1);
+   (((imx_get_fecclk() / 100) + 2) / 5) << 1);
}
/*
 * Set Opcode/Pause Duration Register
@@ -475,7 +478,7 @@ static void fec_halt(struct eth_device *dev)
/*
 * issue graceful stop command to the FEC transmitter if necessary
 */
-   writel(FEC_ECNTRL_RESET | readl(&fec->eth->x_cntrl),
+   writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
&fec->eth->x_cntrl);
 
debug("eth_halt: wait for stop regs\n");
@@ -483,7 +486,7 @@ static void fec_halt(struct eth_device *dev)
 * wait for graceful stop to register
 */
while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
-   ;   /* FIXME ensure time */
+   udelay(1);
 
/*
 * Disable SmartDMA tasks
@@ -495,7 +498,7 @@ static void fec_halt(struct eth_device *dev)
 * Disable the Ethernet Controller
 * Note: this will also reset the BD index counter!
 */
-   writel(0, &fec->eth->ecntrl);
+   writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, 
&fec->eth->ecntrl);
fec->rbd_index = 0;
fec->tbd_index = 0;
debug("eth_halt: done\n");
@@ -554,7 +557,7 @@ static int fec_send(struct eth_device *dev, volatile void* 
packet, int length)
 * wait until frame is sent .
 */
while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
-   /* FIXME: Timeout */
+   udelay(1);
}
debug("fec_send: status 0x%x index %d\n",
readw(&fec->tbd_base[fec->tbd_index].status),
@@ -651,7 +654,6 @@ static int fec_recv(struct eth_device *dev)
 
 static int fec_probe(bd_t *bd)
 {
-   struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
struct eth_device *edev;
struct fec_priv *fec = &gfec;
unsigned char ethaddr_str[20];
@@ -659,10 +661,6 @@ static int fec_probe(bd_t *bd)
char *tmp = getenv("ethaddr");
char *end;
 
-   /* enable FEC clock */
-   writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
-   writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
-
/* create and fill edev struct */
edev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!edev) {
@@ -681,7 +679,7 @@ static int fec_probe(bd_t *bd)
fec->xcv_type = MII100;
 
/* Reset chip. */

[U-Boot] [PATCH 9/9] Add support for KARO TX25 board

[John Rigby]

This is an i.MX25 base board with only NAND
so it uses nand_spl to boot.

Signed-off-by: John Rigby 

Tune configuration, add support for (redundant) environment in NAND.
Signed-off-by: Wolfgang Denk 
---
 MAINTAINERS |4 +
 Makefile|4 +
 board/karo/tx25/Makefile|   51 ++
 board/karo/tx25/config.mk   |5 +
 board/karo/tx25/lowlevel_init.S |  131 +
 board/karo/tx25/tx25.c  |  178 +++
 include/configs/tx25.h  |  178 +++
 nand_spl/board/karo/tx25/Makefile   |   78 +++
 nand_spl/board/karo/tx25/config.mk  |1 +
 nand_spl/board/karo/tx25/u-boot.lds |   58 +++
 10 files changed, 688 insertions(+), 0 deletions(-)
 create mode 100644 board/karo/tx25/Makefile
 create mode 100644 board/karo/tx25/config.mk
 create mode 100644 board/karo/tx25/lowlevel_init.S
 create mode 100644 board/karo/tx25/tx25.c
 create mode 100644 include/configs/tx25.h
 create mode 100644 nand_spl/board/karo/tx25/Makefile
 create mode 100644 nand_spl/board/karo/tx25/config.mk
 create mode 100644 nand_spl/board/karo/tx25/u-boot.lds

diff --git a/MAINTAINERS b/MAINTAINERS
index 48db504..50a11b7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -688,6 +688,10 @@ Tom Rix 
 
omap3_zoom2 ARM CORTEX-A8 (OMAP3xx SoC)
 
+John Rigby 
+
+   tx25i.MX25
+
 Stefan Roese 
 
ixdpg425xscale
diff --git a/Makefile b/Makefile
index 1abe64a..d701407 100644
--- a/Makefile
+++ b/Makefile
@@ -3068,6 +3068,10 @@ trab_old_config: unconfig
}
@$(MKCONFIG) -a $(call xtract_trab,$@) arm arm920t trab NULL s3c24x0
 
+tx25_config: unconfig
+   @$(MKCONFIG) $(@:_config=) arm arm926ejs tx25 karo mx25
+   @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
 VCMA9_config   :   unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t vcma9 mpl s3c24x0
 
diff --git a/board/karo/tx25/Makefile b/board/karo/tx25/Makefile
new file mode 100644
index 000..b0e610f
--- /dev/null
+++ b/board/karo/tx25/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2009 DENX Software Engineering
+# Author: John Rigby 
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS  := tx25.o
+SOBJS  := lowlevel_init.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+   $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+   rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+   rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
+
diff --git a/board/karo/tx25/config.mk b/board/karo/tx25/config.mk
new file mode 100644
index 000..732a14a
--- /dev/null
+++ b/board/karo/tx25/config.mk
@@ -0,0 +1,5 @@
+ifdef CONFIG_NAND_SPL
+TEXT_BASE = 0x81ec
+else
+TEXT_BASE = 0x81f0
+endif
diff --git a/board/karo/tx25/lowlevel_init.S b/board/karo/tx25/lowlevel_init.S
new file mode 100644
index 000..823df10
--- /dev/null
+++ b/board/karo/tx25/lowlevel_init.S
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby 
+ *
+ * Based on U-Boot and RedBoot sources for several different i.mx
+ * platforms.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, I

[U-Boot] [PATCH 1/9] mxc_serial replace platform specific clock

[John Rigby]

remove ifdef'd clock selection code from
serial_mxc.c and replace with call to imx_get_uartclk

Add definitions for imx_get_uartclk to imx31 and imx27
include files.

This makes it easier to add new imx platforms.

Signed-off-by: John Rigby 
---
 drivers/serial/serial_mxc.c   |6 +-
 include/asm-arm/arch-mx27/clock.h |2 ++
 include/asm-arm/arch-mx31/mx31.h  |1 +
 3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index acc5b7d..7dcedf6 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -166,11 +166,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void serial_setbrg (void)
 {
-#ifdef CONFIG_MX31
-   u32 clk = mx31_get_ipg_clk();
-#else
-   u32 clk = imx_get_perclk1();
-#endif
+   u32 clk = imx_get_uartclk();
 
if (!gd->baudrate)
gd->baudrate = CONFIG_BAUDRATE;
diff --git a/include/asm-arm/arch-mx27/clock.h 
b/include/asm-arm/arch-mx27/clock.h
index 5fc75c5..472e8f2 100644
--- a/include/asm-arm/arch-mx27/clock.h
+++ b/include/asm-arm/arch-mx27/clock.h
@@ -36,4 +36,6 @@ ulong imx_get_perclk2(void);
 ulong imx_get_perclk3(void);
 ulong imx_get_ahbclk(void);
 
+#define imx_get_uartclk imx_get_perclk1
+
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/include/asm-arm/arch-mx31/mx31.h b/include/asm-arm/arch-mx31/mx31.h
index 53b9f27..3cc4b35 100644
--- a/include/asm-arm/arch-mx31/mx31.h
+++ b/include/asm-arm/arch-mx31/mx31.h
@@ -25,6 +25,7 @@
 #define __ASM_ARCH_MX31_H
 
 extern u32 mx31_get_ipg_clk(void);
+#define imx_get_uartclk mx31_get_ipg_clk
 extern void mx31_gpio_mux(unsigned long mode);
 
 enum mx31_gpio_direction {
-- 
1.6.4.2.236.gf324c

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[U-Boot] [PATCH 6/9] Add support for Freescale MX25 SOC

[John Rigby]

ARM926EJS core with MX31 peripherals.

Signed-off-by: John Rigby 
Earlier Version Signed-off-by: Wolfgang Denk 
---
 cpu/arm926ejs/mx25/Makefile  |   46 
 cpu/arm926ejs/mx25/generic.c |  263 +++
 cpu/arm926ejs/mx25/reset.c   |   56 
 cpu/arm926ejs/mx25/timer.c   |  187 +
 drivers/serial/serial_mxc.c  |   10 +-
 include/asm-arm/arch-mx25/clock.h|   35 +++
 include/asm-arm/arch-mx25/imx-regs.h |  330 +++
 include/asm-arm/arch-mx25/imx25-pinmux.h |  421 ++
 8 files changed, 1343 insertions(+), 5 deletions(-)
 create mode 100644 cpu/arm926ejs/mx25/Makefile
 create mode 100644 cpu/arm926ejs/mx25/generic.c
 create mode 100644 cpu/arm926ejs/mx25/reset.c
 create mode 100644 cpu/arm926ejs/mx25/timer.c
 create mode 100644 include/asm-arm/arch-mx25/clock.h
 create mode 100644 include/asm-arm/arch-mx25/imx-regs.h
 create mode 100644 include/asm-arm/arch-mx25/imx25-pinmux.h

diff --git a/cpu/arm926ejs/mx25/Makefile b/cpu/arm926ejs/mx25/Makefile
new file mode 100644
index 000..55c1e89
--- /dev/null
+++ b/cpu/arm926ejs/mx25/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).a
+
+COBJS  = generic.o timer.o
+MX27OBJS = reset.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS   += $(addprefix $(SRCTREE)/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c))
+OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS))
+
+all:   $(obj).depend $(LIB)
+
+$(LIB):$(OBJS)
+   $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/cpu/arm926ejs/mx25/generic.c b/cpu/arm926ejs/mx25/generic.c
new file mode 100644
index 000..694841d
--- /dev/null
+++ b/cpu/arm926ejs/mx25/generic.c
@@ -0,0 +1,263 @@
+/*
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby 
+ *
+ * Based on mx27/generic.c:
+ *  Copyright (c) 2008 Eric Jarrige 
+ *  Copyright (c) 2009 Ilya Yanok 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#ifdef CONFIG_MXC_MMC
+#include 
+#endif
+
+/*
+ *  get the system pll clock in Hz
+ *
+ *  mfi + mfn / (mfd +1)
+ *  f = 2 * f_ref * 
+ *pd + 1
+ */
+static unsigned int imx_decode_pll (unsigned int pll, unsigned int f_ref)
+{
+   unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
+   & CCM_PLL_MFI_MASK;
+   unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT)
+   & CCM_PLL_MFN_MASK;
+   unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
+   & CCM_PLL_MFD_MASK;
+   unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
+   & CCM_PLL_PD_MASK;
+
+   mfi = mfi <= 5 ? 5 : mfi;
+
+   return lldiv (2 * (u64) f_ref * (mfi * (mfd + 1) + mfn),
+ (mfd + 1) * (pd + 1));
+}
+
+static ulong imx_get_mpllclk (void)
+{
+   struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+   ulong fref = 2400;
+
+   return imx_decode_pll (readl (&ccm->mpctl), fref);
+}
+
+ulong imx_get_armclk (void)
+{
+   struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+   ulong cctl = readl 

Re: [U-Boot] [PATCH V4 1/3] Initial support for Marvell Orion5x SoC

[Albert ARIBAUD]

Prafulla Wadaskar a écrit :

>> +#define ORION5X_REG_CPUCS_WIN_BAR(x) 
>> (ORION5X_REGISTER(0x1500) + (x * 0x08))
>> +#define ORION5X_REG_CPUCS_WIN_SZ(x)  
>> (ORION5X_REGISTER(0x1504) + (x * 0x08))
> 
> As pointed by wolfgang earlier, you can use c-structures here too.
> -Magic numbers 1500, 1504 can be replaced by appropreate macros like- 
> CPU_CS0_BAR, CPU_CS0_SZ
> -Struct pointer can be declared in cpu.h like
>#define ORION5X_SDRAM_ADRDEC_BASE  (ORION5X_REGISTER(0x1500))
>ref( table 114 in 5182 users manual)
> 
> I know it's coming from referenced code but lets make new code the best. Also 
> I will be updating old code too.

Agreed and fixed for V5.

>> +/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
>> +#define MV88F5181_DEV_ID0x5181
>> +#define MV88F5181_REV_B13
>> +#define MV88F5181L_REV_A0   8
>> +#define MV88F5181L_REV_A1   9
>> +/* Orion-NAS (88F5182) */
>> +#define MV88F5182_DEV_ID0x5182
>> +#define MV88F5182_REV_A22
>> +/* Orion-2 (88F5281) */
>> +#define MV88F5281_DEV_ID0x5281
>> +#define MV88F5281_REV_D04
>> +#define MV88F5281_REV_D15
>> +#define MV88F5281_REV_D26
>> +/* Orion-1-90 (88F6183) */
>> +#define MV88F6183_DEV_ID0x6183
>> +#define MV88F6183_REV_B03
> 
> These are Chip specific, should be moved to mv88f5182.h and similar headers 
> for other Supported Chips

The reason why they are defined this way is that they are for 
identifying the real device/revision on which you are running u-boot, as 
opposed to the intended device/revision for which you built it; they are 
only useful for parts of the code which are common to all orion5x 
variants (such as print_cpuinfo). Variant-specific code would not need 
it as it knows already which variant it is for.

> Regards.
> Prafulla . .

Amicalement,
-- 
Albert.
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Re: [U-Boot] U-Boot Crashes with Dumps

[Stefan Roese]

[Please keep the list on Cc]

On Wednesday 13 January 2010 08:21:32 anupbeh...@gmail.com wrote:
> I am using denali controller.
> Here we can not use 44x_spd_ddr.c as registers are complitly different, so
> we have implemented sdram.c for doing specific initialization...

This seems wrong. You are using the 440GX *and* the Denali SDRAM core? The 
440GX doesn't use the Denali SDRAM controller. Only the 440EPx/GRx use Denali.

Please explain what you are doing here.
 
> We have done ddr training, which was successfully completed I think that
> means DDR initialization is proper.

What exactly do you mean with "ddr training"? DDR setup is complex stuff. Many 
things can go wrong here.
 
> But when the control enter into board_init_r() we get machine check
> exception and u-boot is in continuously reboot mode.

If you are sure that your SDRAM setup is correct, then you need to debug where 
exactly this crash happens. Either use the JTAG debugger (BDI2000/3000) or add 
printf's. But I still suspect SDRAM problems.
 
> after that we are not able to access the flash with Crack monkey tool to
> flash the u-boot binary .

"Crack monkey tool"? What's that? You should be able to access the FLASH again 
after resetting the CPU.
 
Cheers,
Stefan

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HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de
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Re: [U-Boot] [PATCH V4 1/3] Initial support for Marvell Orion5x SoC

[Albert ARIBAUD]

Prafulla Wadaskar a écrit :

>>  cpu/arm926ejs/orion5x/cpu.c  |  258 
> snip
> 
>> +int print_cpuinfo(void)

> The above checks should be #ifdefed with CONFIG_88F (SOC type)
> There is no need to check for all SoC names, this will also reduce code size.

As stated in my answer re: the declaration of the dev/rev constants, I 
believe that this place, of all place, should not be conditionally built 
depending on the device, because it is there to positively identify the 
device/revision we're running our code on even if not built for the 
right variant.

Amicalement,
-- 
Albert.
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