Re: [Qemu-devel] [PATCH v3 0/8] msix: Support specifying offsets, BARs, and capability location
On 2012-06-14 23:31, Michael S. Tsirkin wrote: > On Thu, Jun 14, 2012 at 12:15:42PM -0600, Alex Williamson wrote: >> v3: >> - more patches, smaller diff, must be headed in the right direction >> - macros for all hardcoded values in msix_init_exclusive_bar >> - fold msix_add_config into msix_init allowing less churn to moving >>around msix_uninit >> - note native endian bug >> - split msix_mmio_read move to separate patch >> - split changing return value of msix_uninit to separate patch >> >> Thanks, >> >> Alex > > Thanks, applied all. > Will test/push next week. Could you publish your queue? I'd like to rebase my missing bits. Thanks, Ja signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] [PATCH v3 0/8] msix: Support specifying offsets, BARs, and capability location
On Mon, Jun 18, 2012 at 09:06:01AM +0200, Jan Kiszka wrote: > On 2012-06-14 23:31, Michael S. Tsirkin wrote: > > On Thu, Jun 14, 2012 at 12:15:42PM -0600, Alex Williamson wrote: > >> v3: > >> - more patches, smaller diff, must be headed in the right direction > >> - macros for all hardcoded values in msix_init_exclusive_bar > >> - fold msix_add_config into msix_init allowing less churn to moving > >>around msix_uninit > >> - note native endian bug > >> - split msix_mmio_read move to separate patch > >> - split changing return value of msix_uninit to separate patch > >> > >> Thanks, > >> > >> Alex > > > > Thanks, applied all. > > Will test/push next week. > > Could you publish your queue? I'd like to rebase my missing bits. > > Thanks, > Ja > Will do. FYI Anthony said on irc he objects to the caching approach, asked for more time to review it all. Maybe we'll have to go back to your original idea of a special API just for assigned devices. -- MST
[Qemu-devel] [RFC] ARMCPU: Halting a CPU from Device Land
Hi Andreas,
For the Xilinx Zynq platform, we need to be able to halt a CPU from a
device (the zynq_slcr). E.G, if I write a 1 to a register bit in my
device, then that device effects a halt of a CPU. Looking at the QOM
stuff the API for a CPU is (include/qemu/cpu.h):
typedef struct CPUClass {
/*< private >*/
ObjectClass parent_class;
/*< public >*/
void (*reset)(CPUState *cpu);
} CPUClass;
The only API function is to reset a CPU. Thats means that if I link up
my CPU to my device the only thing it can do is reset the CPU? Are
there plans to extend this API to include some common functions such
as halting and resuming etc? How hard is this to do in a generic (non
ARM) way?
Peter,
Can it be done is an ARM specific way? Is there a one line killer to
halt an ARM cpu that we could add the to ARMCPU API?
Regards,
Peter
Re: [Qemu-devel] [PATCHv2 1/1] Add usb option in machine options to enable/disable usb
Li Zhang writes:
> On Fri, Jun 15, 2012 at 10:34 PM, Markus Armbruster wrote:
>> Li Zhang writes:
>>
>>> On Fri, Jun 15, 2012 at 8:04 PM, Markus Armbruster
>>> wrote:
Li Zhang writes:
> For pseries machine, it needs to enable usb to add
> keyboard or usb mouse. -usb option won't be used in
> the future, and machine options is a better way to
> enable usb.
>
> So this patch is to add usb option to machine options
> (-machine type=psereis,usb=on/off)to enable/disable
> usb controller.
>
> In this patch, usb_on is an global option which can
> be checked by machines.
> For example, on pseries, it will check if usb_on is 1,
> if it is 1, it will create one usb ohci controller.
> As the following:
> if (usb_on == 1) {
> pci_create_simple(bus, -1, "pci-ohci");
> }
>
> In this patch, usb is on by default. So, for -nodefault,
> usb should be set off in the command line as the following:
> -machine type=pseries,usb=off.
>
> Signed-off-by: Li Zhang
>
> ---
> hw/spapr.c | 5 +
> sysemu.h | 1 +
> vl.c | 17 +
> 3 files changed, 23 insertions(+)
>
> diff --git a/hw/spapr.c b/hw/spapr.c
> index d0bddbc..1feb739 100644
> --- a/hw/spapr.c
> +++ b/hw/spapr.c
> @@ -661,6 +661,11 @@ static void ppc_spapr_init(ram_addr_t ram_size,
> spapr_vscsi_create(spapr->vio_bus);
> }
>
> + if (usb_on == 1) {
> + pci_create_simple(QLIST_FIRST(&spapr->phbs)->host_state.bus,
> + -1, "pci-ohci");
> + }
> +
> if (rma_size < (MIN_RMA_SLOF << 20)) {
> fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
> "%ldM guest RMA (Real Mode Area memory)\n",
> MIN_RMA_SLOF);
> diff --git a/sysemu.h b/sysemu.h
> index bc2c788..08134ae 100644
> --- a/sysemu.h
> +++ b/sysemu.h
> @@ -109,6 +109,7 @@ extern int vga_interface_type;
> #define vmsvga_enabled (vga_interface_type == VGA_VMWARE)
> #define qxl_enabled (vga_interface_type == VGA_QXL)
>
> +extern int usb_on;
> extern int graphic_width;
> extern int graphic_height;
> extern int graphic_depth;
> diff --git a/vl.c b/vl.c
> index 204d85b..b200203 100644
> --- a/vl.c
> +++ b/vl.c
> @@ -202,6 +202,7 @@ int smp_cpus = 1;
> int max_cpus = 0;
> int smp_cores = 1;
> int smp_threads = 1;
> +int usb_on = 0;
> #ifdef CONFIG_VNC
> const char *vnc_display;
> #endif
> @@ -758,6 +759,21 @@ static int bt_parse(const char *opt)
> return 1;
> }
>
> +static int get_usb_opt(QemuOpts *opts)
> +{
> + const char *usb_opt = NULL;
Useless initializer.
>>> Thanks. I will remove it.
> + int usb_on = 0;
> +
> + if (NULL == qemu_opt_get(opts, "usb"))
> + qemu_opt_set(opts, "usb", "on");
Why are you changing opts?
>>> USB is enabled by default when there is no usb option setting.
>>> For example,
>>> using # qemu-system-ppc64 -machine type=pseries
>>> There is no usb option, but usb is set on.
>>
>> Isn't it off by default for at least some machines now?
>>
> OK. This default setting is decided by the machine.
> In the new version, I put this setting in machine.
> It can be set off or on.
> For psereis it sets on.
Makes sense.
Perhaps we really have three kinds of machines, not just two:
1. Must have USB: main() sets usb_enabled to true.
2. May have USB: usb_enabled = -usb or -usbdevice given
3. Can't have USB: fail if the user tries to enable it.
Code sketch:
/* init USB devices */
if (!machine->has_usb) {
if (usb_enabled)
[report error; should point to the offending options]
exit(1);
}
} else {
if (machine->has_usb > 0) {
usb_enabled = 1;
}
if (usb_enabled) {
if (foreach_device_config(DEV_USB, usb_parse) < 0)
exit(1);
}
}
>> Anyway, I don't see why we need to update opts. Who's using the updated
>> opts?
>>
> psereis will use this opts.
> usb kbd and mouse will be needed with vga enabled.
Do they use the updated QemuOpts *opts? I'd expect them to use usb_on,
or whatever flag variable governs USB (now: usb_enabled).
[...]
[Qemu-devel] Any better way to access CPUArchState in vl.c?
Hi all, Say I want to print env->some_field in vl.c. I #include "dyngen-exec.h" in vl.c, but got compilation error immediately. /tmp/chenwj/qemu/dyngen-exec.h:64:10: error: attempt to use poisoned "CPUArchState" /tmp/chenwj/qemu/dyngen-exec.h:64:23: error: expected '=', ',', ';', 'asm' or '__attribute__' before '*' token /tmp/chenwj/qemu/dyngen-exec.h:64:24: error: attempt to use poisoned "env" After googling, I figure out QEMU poison some identifiers which cannot be used in target indenpent code. Although we can get some_field by the following way, int some_field = &env->some_field; but it's not very convenient if we have many field of CPUState want to access. Is there a better way to do so? Thanks! Regards, chenwj [1] http://stackoverflow.com/questions/9461625/gcc-error-message-attempt-to-use-poisoned-target-i386 -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O.C.) Tel:886-2-2788-3799 #1667 Homepage: http://people.cs.nctu.edu.tw/~chenwj
Re: [Qemu-devel] [PATCHv2 1/1] Add usb option in machine options to enable/disable usb
>
> 3. Can't have USB: fail if the user tries to enable it.
>
> Code sketch:
>
> /* init USB devices */
> if (!machine->has_usb) {
> if (usb_enabled)
> [report error; should point to the offending options]
> exit(1);
> }
> } else {
> if (machine->has_usb > 0) {
> usb_enabled = 1;
> }
> if (usb_enabled) {
> if (foreach_device_config(DEV_USB, usb_parse) < 0)
> exit(1);
> }
> }
>
>
>>> Anyway, I don't see why we need to update opts. Who's using the updated
>>> opts?
>>>
>> psereis will use this opts.
>> usb kbd and mouse will be needed with vga enabled.
>
> Do they use the updated QemuOpts *opts? I'd expect them to use usb_on,
> or whatever flag variable governs USB (now: usb_enabled).
>
I think whats going on here is Li is trying to do the right thing by
using QEMU opts for this new machine functionality, however, its
getting tangled with all this global state replication of -usb. Isnt
there predecessor work here in getting rid of usb_enabled first? To
that end, I think what is being proposed here is two (somewhat
independent) patches. One patch for changing usb to QEMU_OPTS that
primarily does this:
diff --git a/sysemu.h b/sysemu.h
index bc2c788..9f5ce2c 100644
--- a/sysemu.h
+++ b/sysemu.h
@@ -117,7 +117,6 @@ extern const char *keyboard_layout;
extern int win2k_install_hack;
extern int alt_grab;
extern int ctrl_grab;
-extern int usb_enabled;
extern int smp_cpus;
extern int max_cpus;
extern int cursor_hide;
[6] Donegedit ./sysemu.h
And the second patch which is the pseries machine model stuff.
Which way round probably doesnt matter right? You could make your
machine model use the extern int usb_enabled initially then move it
across to machine opts along with the rest of the usb subsystem. Or
you could fix USB first (globally) then build on top of it. But I
think that this patch as is, is going to do is introduce is a
duplicate -usb implementation which is a little messy (even if it is
only an intermediary state).
Regards,
Peter
> [...]
>
Re: [Qemu-devel] [PATCHv2 1/1] Add usb option in machine options to enable/disable usb
On Mon, Jun 18, 2012 at 3:29 PM, Markus Armbruster wrote:
> Li Zhang writes:
>
>> On Fri, Jun 15, 2012 at 10:34 PM, Markus Armbruster
>> wrote:
>>> Li Zhang writes:
>>>
On Fri, Jun 15, 2012 at 8:04 PM, Markus Armbruster
wrote:
> Li Zhang writes:
>
>> For pseries machine, it needs to enable usb to add
>> keyboard or usb mouse. -usb option won't be used in
>> the future, and machine options is a better way to
>> enable usb.
>>
>> So this patch is to add usb option to machine options
>> (-machine type=psereis,usb=on/off)to enable/disable
>> usb controller.
>>
>> In this patch, usb_on is an global option which can
>> be checked by machines.
>> For example, on pseries, it will check if usb_on is 1,
>> if it is 1, it will create one usb ohci controller.
>> As the following:
>> if (usb_on == 1) {
>> pci_create_simple(bus, -1, "pci-ohci");
>> }
>>
>> In this patch, usb is on by default. So, for -nodefault,
>> usb should be set off in the command line as the following:
>> -machine type=pseries,usb=off.
>>
>> Signed-off-by: Li Zhang
>>
>> ---
>> hw/spapr.c | 5 +
>> sysemu.h | 1 +
>> vl.c | 17 +
>> 3 files changed, 23 insertions(+)
>>
>> diff --git a/hw/spapr.c b/hw/spapr.c
>> index d0bddbc..1feb739 100644
>> --- a/hw/spapr.c
>> +++ b/hw/spapr.c
>> @@ -661,6 +661,11 @@ static void ppc_spapr_init(ram_addr_t ram_size,
>> spapr_vscsi_create(spapr->vio_bus);
>> }
>>
>> + if (usb_on == 1) {
>> + pci_create_simple(QLIST_FIRST(&spapr->phbs)->host_state.bus,
>> + -1, "pci-ohci");
>> + }
>> +
>> if (rma_size < (MIN_RMA_SLOF << 20)) {
>> fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
>> "%ldM guest RMA (Real Mode Area memory)\n",
>> MIN_RMA_SLOF);
>> diff --git a/sysemu.h b/sysemu.h
>> index bc2c788..08134ae 100644
>> --- a/sysemu.h
>> +++ b/sysemu.h
>> @@ -109,6 +109,7 @@ extern int vga_interface_type;
>> #define vmsvga_enabled (vga_interface_type == VGA_VMWARE)
>> #define qxl_enabled (vga_interface_type == VGA_QXL)
>>
>> +extern int usb_on;
>> extern int graphic_width;
>> extern int graphic_height;
>> extern int graphic_depth;
>> diff --git a/vl.c b/vl.c
>> index 204d85b..b200203 100644
>> --- a/vl.c
>> +++ b/vl.c
>> @@ -202,6 +202,7 @@ int smp_cpus = 1;
>> int max_cpus = 0;
>> int smp_cores = 1;
>> int smp_threads = 1;
>> +int usb_on = 0;
>> #ifdef CONFIG_VNC
>> const char *vnc_display;
>> #endif
>> @@ -758,6 +759,21 @@ static int bt_parse(const char *opt)
>> return 1;
>> }
>>
>> +static int get_usb_opt(QemuOpts *opts)
>> +{
>> + const char *usb_opt = NULL;
>
> Useless initializer.
Thanks. I will remove it.
>
>> + int usb_on = 0;
>> +
>> + if (NULL == qemu_opt_get(opts, "usb"))
>> + qemu_opt_set(opts, "usb", "on");
>
> Why are you changing opts?
USB is enabled by default when there is no usb option setting.
For example,
using # qemu-system-ppc64 -machine type=pseries
There is no usb option, but usb is set on.
>>>
>>> Isn't it off by default for at least some machines now?
>>>
>> OK. This default setting is decided by the machine.
>> In the new version, I put this setting in machine.
>> It can be set off or on.
>> For psereis it sets on.
>
> Makes sense.
>
> Perhaps we really have three kinds of machines, not just two:
>
> 1. Must have USB: main() sets usb_enabled to true.
We only hope to use usb option of machine options, not use -usb or -usbdevice,
which will be removed in the future.
But there are still some machines are using it.
>
> 2. May have USB: usb_enabled = -usb or -usbdevice given
>
For one machine, if it uses usb option in machine, usb_enabled can't
work for this machine.
In fact, even if user use -usb, it still doesn't work.
> 3. Can't have USB: fail if the user tries to enable it.
>
> Code sketch:
>
> /* init USB devices */
> if (!machine->has_usb) {
> if (usb_enabled)
> [report error; should point to the offending options]
> exit(1);
> }
> } else {
> if (machine->has_usb > 0) {
> usb_enabled = 1;
> }
> if (usb_enabled) {
> if (foreach_device_config(DEV_USB, usb_parse) < 0)
> exit(1);
> }
> }
>
>
In fact, I really hope to remove usb_enabled.
>>> Anyway, I don't see why we need to update opts. Who's using the updated
>>> opts?
>>>
>> psereis will use this opts.
>> usb kbd and mouse will be needed with vga enabled.
>
> Do they use the updated QemuOpts *opts? I'd expect them to use usb_on,
> or whatever flag variable governs USB (no
Re: [Qemu-devel] [PATCH v3 3/5] osdep: Enable qemu_open to dup pre-opened fd
Am 15.06.2012 22:00, schrieb Eric Blake: > On 06/15/2012 01:19 PM, Corey Bryant wrote: > There are some flags that I don't think we'll be able to change. For example: O_RDONLY, O_WRONLY, O_RDWR. I assume libvirt would open all files O_RDWR. >>> >>> I think we need to check all of them and fail qemu_open() if they don't >>> match. Those that qemu can change, should be just changed, of course. >>> >> >> Ok. I remember a scenario where QEMU opens a file read-only (perhaps to >> check headers and determine the file format) before re-opening it >> read-write. Perhaps this is only when format= isn't specified with >> -drive. I'm thinking we may need to change flags to read-write where >> they used to be read-only, in some circumstances. > > In those situations, libvirt would pass fd with O_RDWR, and qemu_open() > would be fine requesting O_RDONLY the first time (subset is okay), and > O_RDWR the second time. Where you have to error out is where libvirt > passes O_RDONLY but qemu wants O_RDWR, and so forth. Let's try it with requiring an exact match first. If you pass the format, I think the probing is completely avoided indeed, and having read-only images really opened O_RDONLY protects against stupid mistakes. Or if we really need to open the file for probing, maybe we could add a flag that relaxes the check and that isn't used in the real bdrv_open(). Kevin
Re: [Qemu-devel] [PATCHv2 1/1] Add usb option in machine options to enable/disable usb
On Mon, Jun 18, 2012 at 3:54 PM, Peter Crosthwaite
wrote:
>>
>> 3. Can't have USB: fail if the user tries to enable it.
>>
>> Code sketch:
>>
>> /* init USB devices */
>> if (!machine->has_usb) {
>> if (usb_enabled)
>> [report error; should point to the offending options]
>> exit(1);
>> }
>> } else {
>> if (machine->has_usb > 0) {
>> usb_enabled = 1;
>> }
>> if (usb_enabled) {
>> if (foreach_device_config(DEV_USB, usb_parse) < 0)
>> exit(1);
>> }
>> }
>>
>>
Anyway, I don't see why we need to update opts. Who's using the updated
opts?
>>> psereis will use this opts.
>>> usb kbd and mouse will be needed with vga enabled.
>>
>> Do they use the updated QemuOpts *opts? I'd expect them to use usb_on,
>> or whatever flag variable governs USB (now: usb_enabled).
>>
>
> I think whats going on here is Li is trying to do the right thing by
> using QEMU opts for this new machine functionality, however, its
> getting tangled with all this global state replication of -usb. Isnt
> there predecessor work here in getting rid of usb_enabled first? To
I won't introduce global state any more in the latest version.
It just gets the usb_on from machine options.
It won't use usb_enabled.
> that end, I think what is being proposed here is two (somewhat
> independent) patches. One patch for changing usb to QEMU_OPTS that
> primarily does this:
>
> diff --git a/sysemu.h b/sysemu.h
> index bc2c788..9f5ce2c 100644
> --- a/sysemu.h
> +++ b/sysemu.h
> @@ -117,7 +117,6 @@ extern const char *keyboard_layout;
> extern int win2k_install_hack;
> extern int alt_grab;
> extern int ctrl_grab;
> -extern int usb_enabled;
> extern int smp_cpus;
> extern int max_cpus;
> extern int cursor_hide;
> [6] Done gedit ./sysemu.h
>
> And the second patch which is the pseries machine model stuff.
>
> Which way round probably doesnt matter right? You could make your
Because there are some machines using usb_enabled.
So I'd rather to left it as global state and add another usb option in
machine options.
Then the machine can get usb option from machine options to enable usb.
So the latest patch won't introduce the global state.
I will send out the latest version later.
> machine model use the extern int usb_enabled initially then move it
> across to machine opts along with the rest of the usb subsystem. Or
> you could fix USB first (globally) then build on top of it. But I
> think that this patch as is, is going to do is introduce is a
> duplicate -usb implementation which is a little messy (even if it is
> only an intermediary state).
> Regards,
> Peter
>
>> [...]
>>
--
Best Regards
-Li
Re: [Qemu-devel] [RFC] [PATCHv2 2/2] Adding basic calls to libseccomp in vl.c
On Fri, Jun 15, 2012 at 07:06:10PM +, Blue Swirl wrote:
> On Wed, Jun 13, 2012 at 8:30 PM, Daniel P. Berrange
> wrote:
> > On Wed, Jun 13, 2012 at 04:20:22PM -0300, Eduardo Otubo wrote:
> >> I added a syscall struct using priority levels as described in the
> >> libseccomp man page. The priority numbers are based to the frequency
> >> they appear in a sample strace from a regular qemu guest run under
> >> libvirt.
> >>
> >> Libseccomp generates linear BPF code to filter system calls, those rules
> >> are read one after another. The priority system places the most common
> >> rules first in order to reduce the overhead when processing them.
> >>
> >> Also, since this is just a first RFC, the whitelist is a little raw. We
> >> might need your help to improve, test and fine tune the set of system
> >> calls.
> >>
> >> v2: Fixed some style issues
> >> Removed code from vl.c and created qemu-seccomp.[ch]
> >> Now using ARRAY_SIZE macro
> >> Added more syscalls without priority/frequency set yet
> >>
> >> Signed-off-by: Eduardo Otubo
> >> ---
> >> qemu-seccomp.c | 73
> >>
> >> qemu-seccomp.h | 9 +++
> >> vl.c | 7 ++
> >> 3 files changed, 89 insertions(+)
> >> create mode 100644 qemu-seccomp.c
> >> create mode 100644 qemu-seccomp.h
> >>
> >> diff --git a/qemu-seccomp.c b/qemu-seccomp.c
> >> new file mode 100644
> >> index 000..048b7ba
> >> --- /dev/null
> >> +++ b/qemu-seccomp.c
> >> @@ -0,0 +1,73 @@
> >> +#include
> >> +#include
> >> +#include "qemu-seccomp.h"
> >> +
> >> +static struct QemuSeccompSyscall seccomp_whitelist[] = {
> >> + { SCMP_SYS(timer_settime), 255 },
> >> + { SCMP_SYS(timer_gettime), 254 },
> >> + { SCMP_SYS(futex), 253 },
> >> + { SCMP_SYS(select), 252 },
> >> + { SCMP_SYS(recvfrom), 251 },
> >> + { SCMP_SYS(sendto), 250 },
> >> + { SCMP_SYS(read), 249 },
> >> + { SCMP_SYS(brk), 248 },
> >> + { SCMP_SYS(clone), 247 },
> >> + { SCMP_SYS(mmap), 247 },
> >> + { SCMP_SYS(mprotect), 246 },
> >> + { SCMP_SYS(ioctl), 245 },
> >> + { SCMP_SYS(recvmsg), 245 },
> >> + { SCMP_SYS(sendmsg), 245 },
> >> + { SCMP_SYS(accept), 245 },
> >> + { SCMP_SYS(connect), 245 },
> >> + { SCMP_SYS(bind), 245 },
> >> + { SCMP_SYS(listen), 245 },
> >> + { SCMP_SYS(ioctl), 245 },
> >> + { SCMP_SYS(eventfd), 245 },
> >> + { SCMP_SYS(rt_sigprocmask), 245 },
> >> + { SCMP_SYS(write), 244 },
> >> + { SCMP_SYS(fcntl), 243 },
> >> + { SCMP_SYS(tgkill), 242 },
> >> + { SCMP_SYS(rt_sigaction), 242 },
> >> + { SCMP_SYS(pipe2), 242 },
> >> + { SCMP_SYS(munmap), 242 },
> >> + { SCMP_SYS(mremap), 242 },
> >> + { SCMP_SYS(getsockname), 242 },
> >> + { SCMP_SYS(getpeername), 242 },
> >> + { SCMP_SYS(fdatasync), 242 },
> >> + { SCMP_SYS(close), 242 }
> >
> > execve(), so QEMU can run things like the ifup/down
> > scripts, the samba daemon (sic), exec: migration protocol,
> > etc, etc
>
> I think allowing execve() would render seccomp pretty much useless.
So do I, but in the previous posting it was stated[1] that the
intent is to allow all syscalls QEMU needs, and not have
any loss of current functionality. Hence I'm reporting all syscalls
that are missing that QEMU needs.
Daniel
[1] https://lists.gnu.org/archive/html/qemu-devel/2012-05/msg00928.html
--
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|: http://libvirt.org -o- http://virt-manager.org :|
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|: http://entangle-photo.org -o- http://live.gnome.org/gtk-vnc :|
Re: [Qemu-devel] How to measure guest memory access (qemu_ld/qemu_st) time?
> The reason why we want to do the measuring is we want to use KVM (sounds > crazy > idea) MMU virtualization to speedup the guest -> host memory address > translation. > I talked to some people on LinuxCon Japan, included Paolo, about this idea. > The > feedback I got is we can only use shadow page table rather than EPT/NPT to do > the address translation (if possible!) since different ISA (ARM and x86, for > example) have different page table format. Besides, QEMU has to use ioctl to > ask > KVM to get the translation result, but it's an overkill as the ARM page table > is quite simple, which can be done in user mode very fast. Anyone would like to give a comment on this? ;) From the talk with Laurent on #qemu, he said the way he thought of is translating GVA -> GPA manually (through software), then try to insert GPA -> HPA into EPT, that's the only way HW can help. Regards, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O.C.) Tel:886-2-2788-3799 #1667 Homepage: http://people.cs.nctu.edu.tw/~chenwj
Re: [Qemu-devel] [RFC] [PATCHv2 2/2] Adding basic calls to libseccomp in vl.c
On Fri, Jun 15, 2012 at 05:02:19PM -0400, Paul Moore wrote: > On Friday, June 15, 2012 07:06:10 PM Blue Swirl wrote: > > I think allowing execve() would render seccomp pretty much useless. > > Not necessarily. > > I'll agree that it does seem a bit odd to allow execve(), but there is still > value in enabling seccomp to disable potentially buggy/exploitable syscalls. > Let's not forget that we have over 300 syscalls on x86_64, not including the > 32 bit versions, and even if we add all of the new syscalls suggested in this > thread we are still talking about a small subset of syscalls. As far as > security goes, the old adage of "less is more" applies. I can sort of see this argument, but *only* if the QEMU process is being run under a dedicated, fully unprivileged (from a DAC pov) user, completely separate from anything else on the system. If QEMU were being run as root, then even with seccomp, it could trivially just overwrite some binary in /bin, update /proc/core-pattern to point to this binary, and then crash itself. Now that core handling binary will execute without any of the seccomp filters applied. Similarly if QEMU is being run in the user's desktop session, I'm sure there is some kind of similar attack possible by changing a config setting for the user's GNOME/KDE session, and then waiting for GNOME/KDE to execute the script that QEMU just wrote out, once again bypassing seccomp. Regards, Daniel -- |: http://berrange.com -o-http://www.flickr.com/photos/dberrange/ :| |: http://libvirt.org -o- http://virt-manager.org :| |: http://autobuild.org -o- http://search.cpan.org/~danberr/ :| |: http://entangle-photo.org -o- http://live.gnome.org/gtk-vnc :|
Re: [Qemu-devel] [RFC] [PATCHv2 2/2] Adding basic calls to libseccomp in vl.c
On Fri, Jun 15, 2012 at 07:04:45PM +, Blue Swirl wrote:
> On Wed, Jun 13, 2012 at 8:33 PM, Daniel P. Berrange
> wrote:
> > On Wed, Jun 13, 2012 at 07:56:06PM +, Blue Swirl wrote:
> >> On Wed, Jun 13, 2012 at 7:20 PM, Eduardo Otubo
> >> wrote:
> >> > I added a syscall struct using priority levels as described in the
> >> > libseccomp man page. The priority numbers are based to the frequency
> >> > they appear in a sample strace from a regular qemu guest run under
> >> > libvirt.
> >> >
> >> > Libseccomp generates linear BPF code to filter system calls, those rules
> >> > are read one after another. The priority system places the most common
> >> > rules first in order to reduce the overhead when processing them.
> >> >
> >> > Also, since this is just a first RFC, the whitelist is a little raw. We
> >> > might need your help to improve, test and fine tune the set of system
> >> > calls.
> >> >
> >> > v2: Fixed some style issues
> >> > Removed code from vl.c and created qemu-seccomp.[ch]
> >> > Now using ARRAY_SIZE macro
> >> > Added more syscalls without priority/frequency set yet
> >> >
> >> > Signed-off-by: Eduardo Otubo
> >> > ---
> >> > qemu-seccomp.c | 73
> >> >
> >> > qemu-seccomp.h | 9 +++
> >> > vl.c | 7 ++
> >> > 3 files changed, 89 insertions(+)
> >> > create mode 100644 qemu-seccomp.c
> >> > create mode 100644 qemu-seccomp.h
> >> >
> >> > diff --git a/qemu-seccomp.c b/qemu-seccomp.c
> >> > new file mode 100644
> >> > index 000..048b7ba
> >> > --- /dev/null
> >> > +++ b/qemu-seccomp.c
> >> > @@ -0,0 +1,73 @@
> >>
> >> Copyright and license info missing.
> >>
> >> > +#include
> >> > +#include
> >> > +#include "qemu-seccomp.h"
> >> > +
> >> > +static struct QemuSeccompSyscall seccomp_whitelist[] = {
> >>
> >> 'const'
> >>
> >> > + { SCMP_SYS(timer_settime), 255 },
> >> > + { SCMP_SYS(timer_gettime), 254 },
> >> > + { SCMP_SYS(futex), 253 },
> >> > + { SCMP_SYS(select), 252 },
> >> > + { SCMP_SYS(recvfrom), 251 },
> >> > + { SCMP_SYS(sendto), 250 },
> >> > + { SCMP_SYS(read), 249 },
> >> > + { SCMP_SYS(brk), 248 },
> >> > + { SCMP_SYS(clone), 247 },
> >> > + { SCMP_SYS(mmap), 247 },
> >> > + { SCMP_SYS(mprotect), 246 },
> >> > + { SCMP_SYS(ioctl), 245 },
> >> > + { SCMP_SYS(recvmsg), 245 },
> >> > + { SCMP_SYS(sendmsg), 245 },
> >> > + { SCMP_SYS(accept), 245 },
> >> > + { SCMP_SYS(connect), 245 },
> >> > + { SCMP_SYS(bind), 245 },
> >>
> >> It would be nice to avoid connect() and bind(). Perhaps seccomp init
> >> should be postponed to after all sockets have been created?
> >
> > If you want to migrate your guest, you need to be able to
> > call connect() at an arbitrary point in the QEMU process'
> > lifecycle. So you can't avoid allowing connect(). Similarly
> > if you want to allow hotplug of NICs (and their backends)
> > then you need to have both bind() + connect() available.
>
> That's bad. Migration could conceivably be extended to use file
> descriptor passing, but hotplug is more tricky.
As with execve(), i'm reporting this on the basis that on the previous
patch posting I was told we must whitelist any syscalls QEMU can
conceivably use to avoid any loss in functionality.
Daniel
--
|: http://berrange.com -o-http://www.flickr.com/photos/dberrange/ :|
|: http://libvirt.org -o- http://virt-manager.org :|
|: http://autobuild.org -o- http://search.cpan.org/~danberr/ :|
|: http://entangle-photo.org -o- http://live.gnome.org/gtk-vnc :|
Re: [Qemu-devel] [RFC] [PATCHv2 2/2] Adding basic calls to libseccomp in vl.c
On Mon, Jun 18, 2012 at 09:31:03AM +0100, Daniel P. Berrange wrote: > On Fri, Jun 15, 2012 at 05:02:19PM -0400, Paul Moore wrote: > > On Friday, June 15, 2012 07:06:10 PM Blue Swirl wrote: > > > I think allowing execve() would render seccomp pretty much useless. > > > > Not necessarily. > > > > I'll agree that it does seem a bit odd to allow execve(), but there is > > still > > value in enabling seccomp to disable potentially buggy/exploitable > > syscalls. > > Let's not forget that we have over 300 syscalls on x86_64, not including > > the > > 32 bit versions, and even if we add all of the new syscalls suggested in > > this > > thread we are still talking about a small subset of syscalls. As far as > > security goes, the old adage of "less is more" applies. > > I can sort of see this argument, but *only* if the QEMU process is being > run under a dedicated, fully unprivileged (from a DAC pov) user, completely > separate from anything else on the system. Or, of course, for a QEMU already confined by SELinux. > If QEMU were being run as root, then even with seccomp, it could trivially > just overwrite some binary in /bin, update /proc/core-pattern to point to > this binary, and then crash itself. Now that core handling binary will > execute without any of the seccomp filters applied. > > Similarly if QEMU is being run in the user's desktop session, I'm sure there > is some kind of similar attack possible by changing a config setting for the > user's GNOME/KDE session, and then waiting for GNOME/KDE to execute the script > that QEMU just wrote out, once again bypassing seccomp. Daniel -- |: http://berrange.com -o-http://www.flickr.com/photos/dberrange/ :| |: http://libvirt.org -o- http://virt-manager.org :| |: http://autobuild.org -o- http://search.cpan.org/~danberr/ :| |: http://entangle-photo.org -o- http://live.gnome.org/gtk-vnc :|
Re: [Qemu-devel] How to management KVM virtual machines via libvirt?
On Sat, Jun 16, 2012 at 08:00:00PM +0800, 陳韋任 (Wei-Ren Chen) wrote: > CC'ed to libvirt-users. > > On Sat, Jun 16, 2012 at 07:00:59PM +0800, GaoYi wrote: > > Hi all, > > > > I am trying to management the VMs created by KVM commandline. However, I > > found the libvirt cannot connect to the VMs or manage it from virsh. Can > > anybody provide any help? > > Best, > > Shouldn't this go to libvirt mailing list? > > http://libvirt.org/contact.html There is a way to tell libvirt to attach to an externally launched KVM process, provided you have configured it with a monitor socket using the UNIX protocol. This is not always entirely successful though, due to the sheer number of different ways QEMU can be launched, which libvirt does not always understand: http://berrange.com/posts/2011/07/13/attaching-libvirt-to-an-externally-launched-kvm-instance/ In the long run, I'd really recommend just launch the guests via libvirt in the first place Daniel -- |: http://berrange.com -o-http://www.flickr.com/photos/dberrange/ :| |: http://libvirt.org -o- http://virt-manager.org :| |: http://autobuild.org -o- http://search.cpan.org/~danberr/ :| |: http://entangle-photo.org -o- http://live.gnome.org/gtk-vnc :|
Re: [Qemu-devel] [PATCH] make: automatically include dependencies in recursive subdir rules (v2)
On 2012-06-18 02:32, Andreas Färber wrote: > Am 18.06.2012 02:01, schrieb Anthony Liguori: >> I think I understand enough of what's going on in these rules to ensure this >> is >> right. But I could certainly use a second or third opinion... >> >> Signed-off-by: Anthony Liguori >> --- >> v1 -> v2 >> - Remove unnecessary includes (Andreas) >> - Add a sub makefile for hw/kvm (Andreas) >> --- >> Makefile |4 ++-- >> Makefile.dis |2 +- >> Makefile.target |2 +- >> Makefile.user |2 +- >> hw/i386/Makefile.objs |2 +- >> hw/kvm/Makefile.objs |1 + >> rules.mak |1 + >> 7 files changed, 8 insertions(+), 6 deletions(-) >> create mode 100644 hw/kvm/Makefile.objs >> >> diff --git a/Makefile b/Makefile >> index cce45fb..593bd9b 100644 >> --- a/Makefile >> +++ b/Makefile >> @@ -405,5 +405,5 @@ tar: >> Makefile: $(GENERATED_HEADERS) >> >> # Include automatically generated dependency files >> --include $(wildcard *.d audio/*.d slirp/*.d block/*.d net/*.d ui/*.d >> qapi/*.d) >> --include $(wildcard qga/*.d hw/*.d hw/usb/*.d qom/*.d) >> +# All subdir dependencies come automatically from our recursive subdir rules >> +-include $(wildcard *.d) >> diff --git a/Makefile.dis b/Makefile.dis >> index 3e1fcaf..09060f0 100644 >> --- a/Makefile.dis >> +++ b/Makefile.dis >> @@ -20,4 +20,4 @@ clean: >> rm -f *.o *.d *.a *~ >> >> # Include automatically generated dependency files >> --include $(wildcard *.d */*.d) >> +-include $(wildcard *.d) >> diff --git a/Makefile.target b/Makefile.target >> index 2907aad..550d889 100644 >> --- a/Makefile.target >> +++ b/Makefile.target >> @@ -216,4 +216,4 @@ GENERATED_HEADERS += config-target.h >> Makefile: $(GENERATED_HEADERS) >> >> # Include automatically generated dependency files >> --include $(wildcard *.d */*.d) >> +-include $(wildcard *.d) >> diff --git a/Makefile.user b/Makefile.user >> index b717820..0ffefe8 100644 >> --- a/Makefile.user >> +++ b/Makefile.user >> @@ -23,4 +23,4 @@ clean: >> done >> >> # Include automatically generated dependency files >> --include $(wildcard *.d */*.d) >> +-include $(wildcard *.d) >> diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs >> index d43f1df..eb171b7 100644 >> --- a/hw/i386/Makefile.objs >> +++ b/hw/i386/Makefile.objs >> @@ -7,7 +7,7 @@ obj-y += debugcon.o multiboot.o >> obj-y += pc_piix.o >> obj-y += pc_sysfw.o >> obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o >> -obj-$(CONFIG_KVM) += kvm/clock.o kvm/apic.o kvm/i8259.o kvm/ioapic.o >> kvm/i8254.o >> +obj-y += kvm/ > > This will work technically but I still feel this is wrong semantically. > The pre-Paolo and current way is picking specific files from the hw/kvm/ > directory. Your change above implies that in hw/kvm/ only x86 files can > live, which I dislike. As suggested before, I would prefer if x86-only > files were moved to an x86-specific location - the place for that > existing since Paolo's refactoring would be hw/i386/. CC'ing Jan. That > would match Paolo's reply in the unicore32 thread on future file > placement. Alternatives would be hw/i386/kvm/ or hw/kvm/i386/; we're > talking about a handful of files only though, so I don't think they > require a new subdirectory. Some per-arch separation is required, at least in the build process. We'll see power and arm stubs for in-kernel devices soon. Jan -- Siemens AG, Corporate Technology, CT T DE IT 1 Corporate Competence Center Embedded Linux
[Qemu-devel] [PATCH 1/2] Add usb option in machine options to enable/disable usb
For pseries machine, it needs to enable usb to add
keyboard or usb mouse. -usb option won't be used in
the future, and machine options is a better way to
enable usb.
So this patch is to add usb option to machine options
(-machine type=psereis,usb=on/off)to enable/disable
usb controller.
For specific machines, they will get the machine option
and then create usb controller according to usb option.
In this patch, usb is on by default on pseries.
So, for -nodefault,usb should be set off in the command
line as the following:
-machine type=pseries,usb=off.
Signed-off-by: Li Zhang
---
hw/spapr.c| 10 ++
qemu-config.c |4
2 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/hw/spapr.c b/hw/spapr.c
index d0bddbc..8d158d7 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -529,6 +529,8 @@ static void ppc_spapr_init(ram_addr_t ram_size,
long load_limit, rtas_limit, fw_size;
long pteg_shift = 17;
char *filename;
+QemuOpts * machine_opts;
+bool usb_on = false;
spapr = g_malloc0(sizeof(*spapr));
QLIST_INIT(&spapr->phbs);
@@ -661,6 +663,14 @@ static void ppc_spapr_init(ram_addr_t ram_size,
spapr_vscsi_create(spapr->vio_bus);
}
+machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
+if (machine_opts)
+usb_on = qemu_opt_get_bool(machine_opts, "usb", true);
+
+if (usb_on) {
+pci_create_simple(QLIST_FIRST(&spapr->phbs)->host_state.bus,
+ -1, "pci-ohci");
+}
if (rma_size < (MIN_RMA_SLOF << 20)) {
fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
"%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF);
diff --git a/qemu-config.c b/qemu-config.c
index bb3bff4..cdab765 100644
--- a/qemu-config.c
+++ b/qemu-config.c
@@ -583,6 +583,10 @@ static QemuOptsList qemu_machine_opts = {
.name = "dtb",
.type = QEMU_OPT_STRING,
.help = "Linux kernel device tree file",
+},{
+.name = "usb",
+.type = QEMU_OPT_BOOL,
+.help = "Set on/off to enable/disable usb",
},
{ /* End of list */ }
},
--
1.7.7.6
Re: [Qemu-devel] [PATCH v3 0/8] msix: Support specifying offsets, BARs, and capability location
On 2012-06-18 09:19, Michael S. Tsirkin wrote: > On Mon, Jun 18, 2012 at 09:06:01AM +0200, Jan Kiszka wrote: >> On 2012-06-14 23:31, Michael S. Tsirkin wrote: >>> On Thu, Jun 14, 2012 at 12:15:42PM -0600, Alex Williamson wrote: v3: - more patches, smaller diff, must be headed in the right direction - macros for all hardcoded values in msix_init_exclusive_bar - fold msix_add_config into msix_init allowing less churn to moving around msix_uninit - note native endian bug - split msix_mmio_read move to separate patch - split changing return value of msix_uninit to separate patch Thanks, Alex >>> >>> Thanks, applied all. >>> Will test/push next week. >> >> Could you publish your queue? I'd like to rebase my missing bits. >> >> Thanks, >> Ja >> > > Will do. FYI Anthony said on irc he objects to the caching approach, > asked for more time to review it all. Maybe we'll have to > go back to your original idea of a special API just for > assigned devices. Yes, we can still add caching on top. I really like to have some hook upstream soon as time is running out quickly for the 1.2 merge window and there is still some work to do on the qemu-kvm side. Jan -- Siemens AG, Corporate Technology, CT T DE IT 1 Corporate Competence Center Embedded Linux
Re: [Qemu-devel] [PATCH 1/2] Add usb option in machine options to enable/disable usb
Hi Li Zhang, Perhaps you miss "[PATCH v3 1/2]" in the subject? Regards, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O.C.) Tel:886-2-2788-3799 #1667 Homepage: http://people.cs.nctu.edu.tw/~chenwj
[Qemu-devel] [PATCHv3 02/14] unicore32-softmmu: Add coprocessor 0(sysctrl) and 1(ocd) instruction support
Coprocessor 0 is system control coprocessor, and we need get/set its contents.
Also, all cache/tlb ops shoule be implemented here, but just ignored with no
harm.
Coprocessor 1 is OCD (on-chip-debugger), which is used for faked console,
so we could output chars to this console without graphic card.
Signed-off-by: Guan Xuetao
---
target-unicore32/helper.c| 177 +-
target-unicore32/helper.h| 17 ++---
target-unicore32/translate.c | 75 ++-
3 files changed, 221 insertions(+), 48 deletions(-)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 9b8ff06..42a39e5 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -14,6 +14,14 @@
#include "helper.h"
#include "host-utils.h"
+#undef DEBUG_UC32
+
+#ifdef DEBUG_UC32
+#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...) do {} while (0)
+#endif
+
CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
{
UniCore32CPU *cpu;
@@ -45,6 +53,138 @@ uint32_t HELPER(clz)(uint32_t x)
return clz32(x);
}
+#ifndef CONFIG_USER_ONLY
+void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
+uint32_t cop)
+{
+/*
+ * movc pp.nn, rn, #imm9
+ * rn: UCOP_REG_D
+ * nn: UCOP_REG_N
+ * 1: sys control reg.
+ * 2: page table base reg.
+ * 3: data fault status reg.
+ * 4: insn fault status reg.
+ * 5: cache op. reg.
+ * 6: tlb op. reg.
+ * imm9: split UCOP_IMM10 with bit5 is 0
+ */
+switch (creg) {
+case 1:
+if (cop != 0) goto unrecognized;
+env->cp0.c1_sys = val;
+break;
+case 2:
+if (cop != 0) goto unrecognized;
+env->cp0.c2_base = val;
+break;
+case 3:
+if (cop != 0) goto unrecognized;
+env->cp0.c3_faultstatus = val;
+break;
+case 4:
+if (cop != 0) goto unrecognized;
+env->cp0.c4_faultaddr = val;
+break;
+case 5:
+switch(cop) {
+case 28:
+DPRINTF("Invalidate Entire I&D cache\n");
+return;
+case 20:
+DPRINTF("Invalidate Entire Icache\n");
+return;
+case 12:
+DPRINTF("Invalidate Entire Dcache\n");
+return;
+case 10:
+DPRINTF("Clean Entire Dcache\n");
+return;
+case 14:
+DPRINTF("Flush Entire Dcache\n");
+return;
+case 13:
+DPRINTF("Invalidate Dcache line\n");
+return;
+case 11:
+DPRINTF("Clean Dcache line\n");
+return;
+case 15:
+DPRINTF("Flush Dcache line\n");
+return;
+}
+break;
+case 6:
+if ((cop <= 6) && (cop >=2)) {
+/* invalid all tlb */
+tlb_flush(env, 1);
+return;
+}
+break;
+default:
+goto unrecognized;
+}
+return;
+unrecognized:
+cpu_abort(env, "Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
+creg, cop);
+}
+
+uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t creg, uint32_t cop)
+{
+/*
+ * movc rd, pp.nn, #imm9
+ * rd: UCOP_REG_D
+ * nn: UCOP_REG_N
+ * 0: cpuid and cachetype
+ * 1: sys control reg.
+ * 2: page table base reg.
+ * 3: data fault status reg.
+ * 4: insn fault status reg.
+ * imm9: split UCOP_IMM10 with bit5 is 0
+ */
+switch (creg) {
+case 0:
+switch (cop) {
+case 0:
+return env->cp0.c0_cpuid;
+case 1:
+return env->cp0.c0_cachetype;
+}
+break;
+case 1:
+if (cop == 0) {
+return env->cp0.c1_sys;
+}
+break;
+case 2:
+if (cop == 0) {
+return env->cp0.c2_base;
+}
+break;
+case 3:
+if (cop == 0) {
+return env->cp0.c3_faultstatus;
+}
+break;
+case 4:
+if (cop == 0) {
+return env->cp0.c4_faultaddr;
+}
+break;
+}
+cpu_abort(env, "Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
+creg, cop);
+}
+
+void helper_cp1_putc(target_ulong x)
+{
+printf("%c", x);
+fflush(NULL);
+return;
+}
+#endif
+
#ifdef CONFIG_USER_ONLY
void switch_mode(CPUUniCore32State *env, int mode)
{
@@ -66,43 +206,6 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env,
target_ulong address,
}
#endif
-/* These should probably raise undefined insn exceptions. */
-void HELPER(set_cp)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
-{
-int op1 = (insn >> 8) & 0xf;
-cpu_abort(env, "cp%i insn %08x\n", op1, insn);
-return;
-}
-
-uint32_t HELPER(get_cp)(CPUUniCore32State *env, uint32_t i
[Qemu-devel] [PATCHv3 04/14] target-unicore32: Drop UC32_CPUID macros
From: Andreas Färber Any code that depends on a particular CPU type can now go through callbacks on the QOM UniCore32CPUClass. Signed-off-by: Andreas Färber --- target-unicore32/cpu.h |4 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h index 91766a4..ff99bda 100644 --- a/target-unicore32/cpu.h +++ b/target-unicore32/cpu.h @@ -122,10 +122,6 @@ void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask) #define UC32_HWCAP_CMOV 4 /* 1 << 2 */ #define UC32_HWCAP_UCF648 /* 1 << 3 */ -#define UC32_CPUID(env) (env->cp0.c0_cpuid) -#define UC32_CPUID_UCV2 0x40010863 -#define UC32_CPUID_ANY 0x - #define cpu_inituc32_cpu_init #define cpu_execuc32_cpu_exec #define cpu_signal_handler uc32_cpu_signal_handler -- 1.7.0.4
[Qemu-devel] [PATCHv3 01/14] unicore32-softmmu: Add unicore32-softmmu build support
This patch adds unicore32-softmmu build support, include configure,
makefile, arch_init, and all missing functions needed by softmmu.
Although all missing functions are empty, unicore32-softmmu could
be build successfully.
Signed-off-by: Guan Xuetao
---
arch_init.c |2 +
arch_init.h |1 +
configure |1 +
default-configs/unicore32-softmmu.mak |1 +
hw/unicore32/Makefile.objs|1 +
target-unicore32/Makefile.objs|2 +-
target-unicore32/helper.c | 27 +++---
target-unicore32/machine.c| 23 +++
target-unicore32/op_helper.c | 24 +++-
target-unicore32/softmmu.c| 39 +
10 files changed, 106 insertions(+), 15 deletions(-)
create mode 100644 default-configs/unicore32-softmmu.mak
create mode 100644 hw/unicore32/Makefile.objs
create mode 100644 target-unicore32/machine.c
create mode 100644 target-unicore32/softmmu.c
diff --git a/arch_init.c b/arch_init.c
index a9e8b74..007acb3 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -81,6 +81,8 @@ int graphic_depth = 15;
#define QEMU_ARCH QEMU_ARCH_SPARC
#elif defined(TARGET_XTENSA)
#define QEMU_ARCH QEMU_ARCH_XTENSA
+#elif defined(TARGET_UNICORE32)
+#define QEMU_ARCH QEMU_ARCH_UNICORE32
#endif
const uint32_t arch_type = QEMU_ARCH;
diff --git a/arch_init.h b/arch_init.h
index c7cb94a..5298139 100644
--- a/arch_init.h
+++ b/arch_init.h
@@ -16,6 +16,7 @@ enum {
QEMU_ARCH_SH4 = 1024,
QEMU_ARCH_SPARC = 2048,
QEMU_ARCH_XTENSA = 4096,
+QEMU_ARCH_UNICORE32 = 8192,
};
extern const uint32_t arch_type;
diff --git a/configure b/configure
index c2366ee..4fa2f10 100755
--- a/configure
+++ b/configure
@@ -935,6 +935,7 @@ sparc64-softmmu \
s390x-softmmu \
xtensa-softmmu \
xtensaeb-softmmu \
+unicore32-softmmu \
"
fi
# the following are Linux specific
diff --git a/default-configs/unicore32-softmmu.mak
b/default-configs/unicore32-softmmu.mak
new file mode 100644
index 000..5f04fe3
--- /dev/null
+++ b/default-configs/unicore32-softmmu.mak
@@ -0,0 +1 @@
+# Default configuration for unicore32-softmmu
diff --git a/hw/unicore32/Makefile.objs b/hw/unicore32/Makefile.objs
new file mode 100644
index 000..b6a3383
--- /dev/null
+++ b/hw/unicore32/Makefile.objs
@@ -0,0 +1 @@
+# For UniCore32 machines and boards
diff --git a/target-unicore32/Makefile.objs b/target-unicore32/Makefile.objs
index 2e0e093..6af1089 100644
--- a/target-unicore32/Makefile.objs
+++ b/target-unicore32/Makefile.objs
@@ -1,4 +1,4 @@
obj-y += translate.o op_helper.o helper.o cpu.o
-obj-$(CONFIG_SOFTMMU) += machine.o
+obj-$(CONFIG_SOFTMMU) += machine.o softmmu.o
$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 9fe4a37..9b8ff06 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2010-2011 GUAN Xue-tao
+ * Copyright (C) 2010-2012 Guan Xuetao
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -45,18 +45,26 @@ uint32_t HELPER(clz)(uint32_t x)
return clz32(x);
}
+#ifdef CONFIG_USER_ONLY
+void switch_mode(CPUUniCore32State *env, int mode)
+{
+if (mode != ASR_MODE_USER) {
+cpu_abort(env, "Tried to switch out of user mode\n");
+}
+}
+
void do_interrupt(CPUUniCore32State *env)
{
-env->exception_index = -1;
+cpu_abort(env, "NO interrupt in user mode\n");
}
-int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
int rw,
- int mmu_idx)
+int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
+ int access_type, int mmu_idx)
{
-env->exception_index = UC32_EXCP_TRAP;
-env->cp0.c4_faultaddr = address;
+cpu_abort(env, "NO mmu fault in user mode\n");
return 1;
}
+#endif
/* These should probably raise undefined insn exceptions. */
void HELPER(set_cp)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
@@ -84,13 +92,6 @@ uint32_t HELPER(get_cp0)(CPUUniCore32State *env, uint32_t
insn)
return 0;
}
-void switch_mode(CPUUniCore32State *env, int mode)
-{
-if (mode != ASR_MODE_USER) {
-cpu_abort(env, "Tried to switch out of user mode\n");
-}
-}
-
void HELPER(set_r29_banked)(CPUUniCore32State *env, uint32_t mode, uint32_t
val)
{
cpu_abort(env, "banked r29 write\n");
diff --git a/target-unicore32/machine.c b/target-unicore32/machine.c
new file mode 100644
index 000..60b2ec1
--- /dev/null
+++ b/target-unicore32/machine.c
@@ -0,0 +1,23 @@
+/*
+ * Generic machine functions for UniCore32 ISA
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of t
[Qemu-devel] [PATCHv3 08/14] unicore32-softmmu: Add puv3 interrupt support
This patch adds puv3 interrupt support, include interrupt controler
device simulation and interrupt handler in puv3 machine.
Signed-off-by: Guan Xuetao
---
hw/Makefile.objs |3 +
hw/puv3.c| 23 +-
hw/puv3_intc.c | 135 ++
3 files changed, 160 insertions(+), 1 deletions(-)
create mode 100644 hw/puv3_intc.c
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 3d77259..96a3c07 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -66,6 +66,9 @@ hw-obj-$(CONFIG_XILINX) += xilinx_uartlite.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
+# PKUnity SoC devices
+hw-obj-$(CONFIG_PUV3) += puv3_intc.o
+
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/puv3.c b/hw/puv3.c
index 0dc129d..690e4f8 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -22,9 +22,30 @@
#define KERNEL_LOAD_ADDR0x0300
#define KERNEL_MAX_SIZE 0x0080 /* Just a guess */
+static void puv3_intc_cpu_handler(void *opaque, int irq, int level)
+{
+CPUUniCore32State *env = (CPUUniCore32State *)opaque;
+
+assert(irq == 0);
+if (level) {
+cpu_interrupt(env, CPU_INTERRUPT_HARD);
+} else {
+cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+}
+}
+
static void puv3_soc_init(CPUUniCore32State *env)
{
-/* TODO */
+qemu_irq *cpu_intc, irqs[PUV3_IRQS_NR];
+DeviceState *dev;
+int i;
+
+/* Initialize interrupt controller */
+cpu_intc = qemu_allocate_irqs(puv3_intc_cpu_handler, env, 1);
+dev = sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, *cpu_intc);
+for (i = 0; i < PUV3_IRQS_NR; i++) {
+irqs[i] = qdev_get_gpio_in(dev, i);
+}
}
static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
diff --git a/hw/puv3_intc.c b/hw/puv3_intc.c
new file mode 100644
index 000..ec8fa71
--- /dev/null
+++ b/hw/puv3_intc.c
@@ -0,0 +1,135 @@
+/*
+ * INTC device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "sysbus.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+qemu_irq parent_irq;
+
+uint32_t reg_ICMR;
+uint32_t reg_ICPR;
+} PUV3INTCState;
+
+/* Update interrupt status after enabled or pending bits have been changed. */
+static void puv3_intc_update(PUV3INTCState *s)
+{
+if (s->reg_ICMR & s->reg_ICPR) {
+qemu_irq_raise(s->parent_irq);
+} else {
+qemu_irq_lower(s->parent_irq);
+}
+}
+
+/* Process a change in an external INTC input. */
+static void puv3_intc_handler(void *opaque, int irq, int level)
+{
+PUV3INTCState *s = (PUV3INTCState *)opaque;
+
+DPRINTF("irq 0x%x, level 0x%x\n", irq, level);
+if (level) {
+s->reg_ICPR |= (1 << irq);
+} else {
+s->reg_ICPR &= ~(1 << irq);
+}
+puv3_intc_update(s);
+}
+
+static uint64_t puv3_intc_read(void *opaque, target_phys_addr_t offset,
+unsigned size)
+{
+PUV3INTCState *s = (PUV3INTCState *)opaque;
+uint32_t ret = 0;
+
+switch (offset) {
+case 0x04: /* INTC_ICMR */
+ret = s->reg_ICMR;
+break;
+case 0x0c: /* INTC_ICIP */
+ret = s->reg_ICPR; /* the same value with ICPR */
+break;
+default:
+hw_error("puv3_intc_read: Bad offset %x\n", (int)offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+return ret;
+}
+
+static void puv3_intc_write(void *opaque, target_phys_addr_t offset,
+uint64_t value, unsigned size)
+{
+PUV3INTCState *s = (PUV3INTCState *)opaque;
+
+DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+switch (offset) {
+case 0x00: /* INTC_ICLR */
+case 0x14: /* INTC_ICCR */
+break;
+case 0x04: /* INTC_ICMR */
+s->reg_ICMR = value;
+break;
+default:
+hw_error("puv3_intc_write: Bad offset 0x%x\n", (int)offset);
+return;
+}
+puv3_intc_update(s);
+}
+
+static const MemoryRegionOps puv3_intc_ops = {
+.read = puv3_intc_read,
+.write = puv3_intc_write,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int puv3_intc_init(SysBusDevice *dev)
+{
+PUV3INTCState *s = FROM_SYSBUS(PUV3INTCState, dev);
+
+qdev_init_gpio_in(&s->busdev.qdev, puv3_intc_handler, PUV3_IRQS_NR);
+sysbus_init_irq(&s->busdev, &s->parent_irq);
+
+s->reg_ICMR = 0;
+s->reg_ICPR = 0;
+
+memory_region_init_io(&s->iomem, &puv3_intc_ops, s, "puv3_intc",
+PUV3_REGS_OFFSET);
+sysbus_init_mmio(dev, &s->iomem);
+
+return 0;
+}
+
+static voi
Re: [Qemu-devel] [PATCH] make: automatically include dependencies in recursive subdir rules (v2)
On 18 June 2012 10:13, Jan Kiszka wrote: > On 2012-06-18 02:32, Andreas Färber wrote: >> This will work technically but I still feel this is wrong semantically. >> The pre-Paolo and current way is picking specific files from the hw/kvm/ >> directory. Your change above implies that in hw/kvm/ only x86 files can >> live, which I dislike. > Some per-arch separation is required, at least in the build process. > We'll see power and arm stubs for in-kernel devices soon. Indeed -- I have a hw/kvm/arm_gic.c in the qemu-linaro tree, so if you break building that I'll have to unbreak it :-) (Does architecture-specific separation make much sense in general? Not all devices are architecture-specific. I'd have thought that a functional split eg timer/serial/usb like the linux kernel layout would be better.) -- PMM
[Qemu-devel] [PATCH 2/2] spapr: Add support for -vga option
Also instanciate the USB keyboard and mouse when that option is used
(you can still use -device to create individual devices without all
the defaults)
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Li Zhang
---
hw/spapr.c | 43 ++-
1 files changed, 42 insertions(+), 1 deletions(-)
diff --git a/hw/spapr.c b/hw/spapr.c
index 8d158d7..c7b6e9d 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -45,6 +45,8 @@
#include "kvm.h"
#include "kvm_ppc.h"
#include "pci.h"
+#include "pc.h"
+#include "usb.h"
#include "exec-memory.h"
@@ -82,6 +84,7 @@
#define PHANDLE_XICP0x
sPAPREnvironment *spapr;
+static int spapr_has_graphics;
qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num,
enum xics_irq_type type)
@@ -222,6 +225,9 @@ static void *spapr_create_fdt_skel(const char *cpu_model,
_FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop;
}
_FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));
+_FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
+_FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
+_FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
_FDT((fdt_end_node(fdt)));
@@ -457,7 +463,9 @@ static void spapr_finalize_fdt(sPAPREnvironment *spapr,
}
}
-spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
+if (!spapr_has_graphics) {
+spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
+}
_FDT((fdt_pack(fdt)));
@@ -510,6 +518,30 @@ static void spapr_cpu_reset(void *opaque)
cpu_reset(CPU(cpu));
}
+static int spapr_vga_init(PCIBus *pci_bus)
+{
+/* Default is nothing */
+#if 0 /* Enable this once we merge a SLOF which works with Cirrus */
+if (cirrus_vga_enabled) {
+pci_cirrus_vga_init(pci_bus);
+} else
+#endif
+if (vmsvga_enabled) {
+fprintf(stderr, "Warning: vmware_vga not available,"
+" using standard VGA instead\n");
+pci_vga_init(pci_bus);
+#ifdef CONFIG_SPICE
+} else if (qxl_enabled) {
+pci_create_simple(pci_bus, -1, "qxl-vga");
+#endif
+} else if (std_vga_enabled) {
+pci_vga_init(pci_bus);
+} else {
+return 0;
+}
+return 1;
+}
+
/* pSeries LPAR / sPAPR hardware init */
static void ppc_spapr_init(ram_addr_t ram_size,
const char *boot_device,
@@ -663,6 +695,11 @@ static void ppc_spapr_init(ram_addr_t ram_size,
spapr_vscsi_create(spapr->vio_bus);
}
+/* Graphics */
+if (spapr_vga_init(QLIST_FIRST(&spapr->phbs)->host_state.bus)) {
+spapr_has_graphics = 1;
+}
+
machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
if (machine_opts)
usb_on = qemu_opt_get_bool(machine_opts, "usb", true);
@@ -670,6 +707,10 @@ static void ppc_spapr_init(ram_addr_t ram_size,
if (usb_on) {
pci_create_simple(QLIST_FIRST(&spapr->phbs)->host_state.bus,
-1, "pci-ohci");
+if (spapr_has_graphics) {
+usbdevice_create("keyboard");
+usbdevice_create("mouse");
+}
}
if (rma_size < (MIN_RMA_SLOF << 20)) {
fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
--
1.7.7.6
[Qemu-devel] [PATCHv3 00/14] unicore32: add softmmu support and puv3 machine
These patches implement softmmu support on unicore32 architecture. Based on master branch of qemu, the patches can be fetched from: git://github.com/gxt/QEMU.git unicore32 UniCore32 CPU is embedded in PKUnity-3 SoC, so we add necessary puv3 devices simulation codes together. Only minimal system control modules are simulated, to make linux kernel boot and busybox run in initramfs. Any advice is greatly appreciated. Thanks, Guan Xuetao Andreas Färber (1): target-unicore32: Drop UC32_CPUID macros Guan Xuetao (13): unicore32-softmmu: Add unicore32-softmmu build support unicore32-softmmu: Add coprocessor 0(sysctrl) and 1(ocd) instruction support unicore32-softmmu: Make UniCore32 cpuid & exceptions correct and runable unicore32-softmmu: Implement softmmu specific functions unicore32-softmmu: Make sure that kernel can access user space unicore32-softmmu: Add puv3 soc/board support unicore32-softmmu: Add puv3 interrupt support unicore32-softmmu: Add puv3 ostimer support unicore32-softmmu: Add puv3 gpio support unicore32-softmmu: Add puv3 pm support unicore32-softmmu: Add puv3 dma support unicore32-softmmu: Add ps2 support unicore32-softmmu: Add maintainer information for UniCore32 machine MAINTAINERS |7 + arch_init.c |2 + arch_init.h |1 + configure |1 + cpu-exec.c|1 + default-configs/unicore32-softmmu.mak |4 + hw/Makefile.objs |7 + hw/puv3.c | 130 hw/puv3.h | 49 ++ hw/puv3_dma.c | 109 + hw/puv3_gpio.c| 141 + hw/puv3_intc.c| 135 + hw/puv3_ost.c | 151 +++ hw/puv3_pm.c | 148 ++ hw/unicore32/Makefile.objs|6 + linux-user/main.c |3 +- target-unicore32/Makefile.objs|2 +- target-unicore32/cpu.c| 19 ++- target-unicore32/cpu.h| 12 +- target-unicore32/helper.c | 174 +- target-unicore32/helper.h | 17 +-- target-unicore32/machine.c| 23 +++ target-unicore32/op_helper.c | 44 ++- target-unicore32/softmmu.c| 267 + target-unicore32/translate.c | 111 -- 25 files changed, 1493 insertions(+), 71 deletions(-) create mode 100644 default-configs/unicore32-softmmu.mak create mode 100644 hw/puv3.c create mode 100644 hw/puv3.h create mode 100644 hw/puv3_dma.c create mode 100644 hw/puv3_gpio.c create mode 100644 hw/puv3_intc.c create mode 100644 hw/puv3_ost.c create mode 100644 hw/puv3_pm.c create mode 100644 hw/unicore32/Makefile.objs create mode 100644 target-unicore32/machine.c create mode 100644 target-unicore32/softmmu.c
[Qemu-devel] [PATCH 2/2] fdc: Move floppy geometry guessing back from block.c
Commit 5bbdbb46 moved it to block.c because "other geometry guessing
functions already reside in block.c". Device-specific functionality
should be kept in device code, not the block layer. Move it back.
Disk geometry guessing is still in block.c. To be moved out in a
later patch series.
Bonus: the floppy type used in pc_cmos_init() now obviously matches
the one in the FDrive. Before, we relied on
bdrv_get_floppy_geometry_hint() picking the same type both in
fd_revalidate() and in pc_cmos_init().
Signed-off-by: Markus Armbruster
---
block.c | 101 ---
block.h | 18 -
hw/fdc.c | 122 -
hw/fdc.h | 10 +-
hw/pc.c | 13 ++-
5 files changed, 124 insertions(+), 140 deletions(-)
diff --git a/block.c b/block.c
index f5e7cb6..66789d5 100644
--- a/block.c
+++ b/block.c
@@ -2243,107 +2243,6 @@ void bdrv_set_io_limits(BlockDriverState *bs,
bs->io_limits_enabled = bdrv_io_limits_enabled(bs);
}
-/* Recognize floppy formats */
-typedef struct FDFormat {
-FDriveType drive;
-uint8_t last_sect;
-uint8_t max_track;
-uint8_t max_head;
-FDriveRate rate;
-} FDFormat;
-
-static const FDFormat fd_formats[] = {
-/* First entry is default format */
-/* 1.44 MB 3"1/2 floppy disks */
-{ FDRIVE_DRV_144, 18, 80, 1, FDRIVE_RATE_500K, },
-{ FDRIVE_DRV_144, 20, 80, 1, FDRIVE_RATE_500K, },
-{ FDRIVE_DRV_144, 21, 80, 1, FDRIVE_RATE_500K, },
-{ FDRIVE_DRV_144, 21, 82, 1, FDRIVE_RATE_500K, },
-{ FDRIVE_DRV_144, 21, 83, 1, FDRIVE_RATE_500K, },
-{ FDRIVE_DRV_144, 22, 80, 1, FDRIVE_RATE_500K, },
-{ FDRIVE_DRV_144, 23, 80, 1, FDRIVE_RATE_500K, },
-{ FDRIVE_DRV_144, 24, 80, 1, FDRIVE_RATE_500K, },
-/* 2.88 MB 3"1/2 floppy disks */
-{ FDRIVE_DRV_288, 36, 80, 1, FDRIVE_RATE_1M, },
-{ FDRIVE_DRV_288, 39, 80, 1, FDRIVE_RATE_1M, },
-{ FDRIVE_DRV_288, 40, 80, 1, FDRIVE_RATE_1M, },
-{ FDRIVE_DRV_288, 44, 80, 1, FDRIVE_RATE_1M, },
-{ FDRIVE_DRV_288, 48, 80, 1, FDRIVE_RATE_1M, },
-/* 720 kB 3"1/2 floppy disks */
-{ FDRIVE_DRV_144, 9, 80, 1, FDRIVE_RATE_250K, },
-{ FDRIVE_DRV_144, 10, 80, 1, FDRIVE_RATE_250K, },
-{ FDRIVE_DRV_144, 10, 82, 1, FDRIVE_RATE_250K, },
-{ FDRIVE_DRV_144, 10, 83, 1, FDRIVE_RATE_250K, },
-{ FDRIVE_DRV_144, 13, 80, 1, FDRIVE_RATE_250K, },
-{ FDRIVE_DRV_144, 14, 80, 1, FDRIVE_RATE_250K, },
-/* 1.2 MB 5"1/4 floppy disks */
-{ FDRIVE_DRV_120, 15, 80, 1, FDRIVE_RATE_500K, },
-{ FDRIVE_DRV_120, 18, 80, 1, FDRIVE_RATE_500K, },
-{ FDRIVE_DRV_120, 18, 82, 1, FDRIVE_RATE_500K, },
-{ FDRIVE_DRV_120, 18, 83, 1, FDRIVE_RATE_500K, },
-{ FDRIVE_DRV_120, 20, 80, 1, FDRIVE_RATE_500K, },
-/* 720 kB 5"1/4 floppy disks */
-{ FDRIVE_DRV_120, 9, 80, 1, FDRIVE_RATE_250K, },
-{ FDRIVE_DRV_120, 11, 80, 1, FDRIVE_RATE_250K, },
-/* 360 kB 5"1/4 floppy disks */
-{ FDRIVE_DRV_120, 9, 40, 1, FDRIVE_RATE_300K, },
-{ FDRIVE_DRV_120, 9, 40, 0, FDRIVE_RATE_300K, },
-{ FDRIVE_DRV_120, 10, 41, 1, FDRIVE_RATE_300K, },
-{ FDRIVE_DRV_120, 10, 42, 1, FDRIVE_RATE_300K, },
-/* 320 kB 5"1/4 floppy disks */
-{ FDRIVE_DRV_120, 8, 40, 1, FDRIVE_RATE_250K, },
-{ FDRIVE_DRV_120, 8, 40, 0, FDRIVE_RATE_250K, },
-/* 360 kB must match 5"1/4 better than 3"1/2... */
-{ FDRIVE_DRV_144, 9, 80, 0, FDRIVE_RATE_250K, },
-/* end */
-{ FDRIVE_DRV_NONE, -1, -1, 0, 0, },
-};
-
-void bdrv_get_floppy_geometry_hint(BlockDriverState *bs, int *nb_heads,
- int *max_track, int *last_sect,
- FDriveType drive_in, FDriveType *drive,
- FDriveRate *rate)
-{
-const FDFormat *parse;
-uint64_t nb_sectors, size;
-int i, first_match, match;
-
-bdrv_get_geometry(bs, &nb_sectors);
-match = -1;
-first_match = -1;
-for (i = 0; ; i++) {
-parse = &fd_formats[i];
-if (parse->drive == FDRIVE_DRV_NONE) {
-break;
-}
-if (drive_in == parse->drive ||
-drive_in == FDRIVE_DRV_NONE) {
-size = (parse->max_head + 1) * parse->max_track *
-parse->last_sect;
-if (nb_sectors == size) {
-match = i;
-break;
-}
-if (first_match == -1) {
-first_match = i;
-}
-}
-}
-if (match == -1) {
-if (first_match == -1) {
-match = 1;
-} else {
-match = first_match;
-}
-parse = &fd_formats[match];
-}
-*nb_heads = parse->max_head + 1;
-*max_track = parse->max_track;
-*last_sect = parse->last_sect;
-*drive = parse->drive;
-*rate = parse->rate;
-}
-
int bdrv_get_translation_hint(BlockDriverState *bs)
{
return bs->translation;
diff --git a/block.h b/block.h
index d135652..f4c77a1 100644
--- a/block.h
Re: [Qemu-devel] [PATCH] qemu-config: Use QEMU instead of Qemu
On Sat, Jun 16, 2012 at 09:29:10AM +0200, Stefan Weil wrote: > This new 'Qemu' was recently added. > Replace it by the official all upper case 'QEMU'. > > Signed-off-by: Stefan Weil > --- > qemu-config.h |2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Thanks, applied to the trivial patches tree: https://github.com/stefanha/qemu/commits/trivial-patches Stefan
[Qemu-devel] [PATCHv3 07/14] unicore32-softmmu: Add puv3 soc/board support
This patch only add puv3 soc/board support, which introduces puv3
machine description, and specifies console type.
Signed-off-by: Guan Xuetao
---
default-configs/unicore32-softmmu.mak |1 +
hw/puv3.c | 93 +
hw/puv3.h | 49 +
hw/unicore32/Makefile.objs|5 ++
4 files changed, 148 insertions(+), 0 deletions(-)
create mode 100644 hw/puv3.c
create mode 100644 hw/puv3.h
diff --git a/default-configs/unicore32-softmmu.mak
b/default-configs/unicore32-softmmu.mak
index 5f04fe3..726a338 100644
--- a/default-configs/unicore32-softmmu.mak
+++ b/default-configs/unicore32-softmmu.mak
@@ -1 +1,2 @@
# Default configuration for unicore32-softmmu
+CONFIG_PUV3=y
diff --git a/hw/puv3.c b/hw/puv3.c
new file mode 100644
index 000..0dc129d
--- /dev/null
+++ b/hw/puv3.c
@@ -0,0 +1,93 @@
+/*
+ * Generic PKUnity SoC machine and board descriptor
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "console.h"
+#include "elf.h"
+#include "exec-memory.h"
+#include "sysbus.h"
+#include "boards.h"
+#include "loader.h"
+#include "pc.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+#define KERNEL_LOAD_ADDR0x0300
+#define KERNEL_MAX_SIZE 0x0080 /* Just a guess */
+
+static void puv3_soc_init(CPUUniCore32State *env)
+{
+/* TODO */
+}
+
+static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
+{
+MemoryRegion *ram_memory = g_new(MemoryRegion, 1);
+
+/* SDRAM at address zero. */
+memory_region_init_ram(ram_memory, "puv3.ram", ram_size);
+vmstate_register_ram_global(ram_memory);
+memory_region_add_subregion(get_system_memory(), 0, ram_memory);
+}
+
+static void puv3_load_kernel(const char *kernel_filename)
+{
+int size;
+
+assert(kernel_filename != NULL);
+
+/* only zImage format supported */
+size = load_image_targphys(kernel_filename, KERNEL_LOAD_ADDR,
+KERNEL_MAX_SIZE);
+if (size < 0) {
+hw_error("Load kernel error: '%s'\n", kernel_filename);
+}
+
+/* cheat curses that we have a graphic console, only under ocd console */
+graphic_console_init(NULL, NULL, NULL, NULL, NULL);
+}
+
+static void puv3_init(ram_addr_t ram_size, const char *boot_device,
+ const char *kernel_filename, const char *kernel_cmdline,
+ const char *initrd_filename, const char *cpu_model)
+{
+CPUUniCore32State *env;
+
+if (initrd_filename) {
+hw_error("Please use kernel built-in initramdisk.\n");
+}
+
+if (!cpu_model) {
+cpu_model = "UniCore-II";
+}
+
+env = cpu_init(cpu_model);
+if (!env) {
+hw_error("Unable to find CPU definition\n");
+}
+
+puv3_soc_init(env);
+puv3_board_init(env, ram_size);
+puv3_load_kernel(kernel_filename);
+}
+
+static QEMUMachine puv3_machine = {
+.name = "puv3",
+.desc = "PKUnity Version-3 based on UniCore32",
+.init = puv3_init,
+.use_scsi = 0,
+};
+
+static void puv3_machine_init(void)
+{
+qemu_register_machine(&puv3_machine);
+}
+
+machine_init(puv3_machine_init)
diff --git a/hw/puv3.h b/hw/puv3.h
new file mode 100644
index 000..bcfc978
--- /dev/null
+++ b/hw/puv3.h
@@ -0,0 +1,49 @@
+/*
+ * Misc PKUnity SoC declarations
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#ifndef __PUV3_H__
+#define __PUV3_H__
+
+#define PUV3_REGS_OFFSET(0x1000) /* 4K is reasonable */
+
+/* PKUnity System bus (AHB): 0xc000 - 0xedff (640MB) */
+#define PUV3_DMA_BASE (0xc020) /* AHB-4 */
+
+/* PKUnity Peripheral bus (APB): 0xee00 - 0xefff (128MB) */
+#define PUV3_GPIO_BASE (0xee50) /* APB-5 */
+#define PUV3_INTC_BASE (0xee60) /* APB-6 */
+#define PUV3_OST_BASE (0xee80) /* APB-8 */
+#define PUV3_PM_BASE(0xeea0) /* APB-10 */
+#define PUV3_PS2_BASE (0xeeb0) /* APB-11 */
+
+/* Hardware interrupts */
+#define PUV3_IRQS_NR(32)
+
+#define PUV3_IRQS_GPIOLOW0 (0)
+#define PUV3_IRQS_GPIOLOW1 (1)
+#define PUV3_IRQS_GPIOLOW2 (2)
+#define PUV3_IRQS_GPIOLOW3 (3)
+#define PUV3_IRQS_GPIOLOW4 (4)
+#define PUV3_IRQS_GPIOLOW5 (5)
+#define PUV3_IRQS_GPIOLOW6 (6)
+#define PUV3_IRQS_GPIOLOW7 (7)
+#define PUV3_IRQS_GPIOHIGH (8)
+#define PUV3_IRQS_PS2_KBD (22)
+#define PUV3_IRQS_PS2_AUX (23)
+#define PU
Re: [Qemu-devel] [Qemu-trivial] [PATCH] checkpatch: Add QEMU specific rule
On Sun, Jun 17, 2012 at 06:57:41AM +0200, Stefan Weil wrote: > The new rule detects two wrong variants of QEMU. > It was tested with commit b5a8fe5e. > > Signed-off-by: Stefan Weil > --- > scripts/checkpatch.pl |5 + > 1 files changed, 5 insertions(+), 0 deletions(-) Thanks, applied to the trivial patches tree: https://github.com/stefanha/qemu/commits/trivial-patches Stefan
[Qemu-devel] [PATCH 1/2] fdc: Drop broken code for user-defined floppy geometry
bdrv_get_floppy_geometry_hint() fails to store through its parameter
drive when bs has a geometry hint. Makes fd_revalidate() assign
random crap to drv->drive.
Has been broken that way for ages. Harmless, because:
* The only way to set a geometry hint is -drive if=none,cyls=...
Since commit c219331e, probably unintentional.
* The only use of drv->drive is as argument to another
bdrv_get_floppy_geometry_hint(). Which doesn't use it, since the
geometry hint is still there.
Drop the broken code, ignore -drive parameter cyls, heads and secs for
floppies even with if=none, just like before commit c219331e. Matches
-help, which explains cyls, heads, secs as "hard disk physical
geometry".
Signed-off-by: Markus Armbruster
---
block.c | 62 --
hw/fdc.c |3 ---
2 files changed, 28 insertions(+), 37 deletions(-)
diff --git a/block.c b/block.c
index 0acdcac..f5e7cb6 100644
--- a/block.c
+++ b/block.c
@@ -2308,46 +2308,40 @@ void bdrv_get_floppy_geometry_hint(BlockDriverState
*bs, int *nb_heads,
uint64_t nb_sectors, size;
int i, first_match, match;
-bdrv_get_geometry_hint(bs, nb_heads, max_track, last_sect);
-if (*nb_heads != 0 && *max_track != 0 && *last_sect != 0) {
-/* User defined disk */
-*rate = FDRIVE_RATE_500K;
-} else {
-bdrv_get_geometry(bs, &nb_sectors);
-match = -1;
-first_match = -1;
-for (i = 0; ; i++) {
-parse = &fd_formats[i];
-if (parse->drive == FDRIVE_DRV_NONE) {
+bdrv_get_geometry(bs, &nb_sectors);
+match = -1;
+first_match = -1;
+for (i = 0; ; i++) {
+parse = &fd_formats[i];
+if (parse->drive == FDRIVE_DRV_NONE) {
+break;
+}
+if (drive_in == parse->drive ||
+drive_in == FDRIVE_DRV_NONE) {
+size = (parse->max_head + 1) * parse->max_track *
+parse->last_sect;
+if (nb_sectors == size) {
+match = i;
break;
}
-if (drive_in == parse->drive ||
-drive_in == FDRIVE_DRV_NONE) {
-size = (parse->max_head + 1) * parse->max_track *
-parse->last_sect;
-if (nb_sectors == size) {
-match = i;
-break;
-}
-if (first_match == -1) {
-first_match = i;
-}
-}
-}
-if (match == -1) {
if (first_match == -1) {
-match = 1;
-} else {
-match = first_match;
+first_match = i;
}
-parse = &fd_formats[match];
}
-*nb_heads = parse->max_head + 1;
-*max_track = parse->max_track;
-*last_sect = parse->last_sect;
-*drive = parse->drive;
-*rate = parse->rate;
}
+if (match == -1) {
+if (first_match == -1) {
+match = 1;
+} else {
+match = first_match;
+}
+parse = &fd_formats[match];
+}
+*nb_heads = parse->max_head + 1;
+*max_track = parse->max_track;
+*last_sect = parse->last_sect;
+*drive = parse->drive;
+*rate = parse->rate;
}
int bdrv_get_translation_hint(BlockDriverState *bs)
diff --git a/hw/fdc.c b/hw/fdc.c
index 78b4e33..132b1e3 100644
--- a/hw/fdc.c
+++ b/hw/fdc.c
@@ -189,9 +189,6 @@ static void fd_revalidate(FDrive *drv)
&last_sect, drv->drive, &drive, &rate);
if (!bdrv_is_inserted(drv->bs)) {
FLOPPY_DPRINTF("No disk in drive\n");
-} else if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
-FLOPPY_DPRINTF("User defined disk (%d %d %d)\n",
- nb_heads - 1, max_track, last_sect);
} else {
FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
max_track, last_sect, ro ? "ro" : "rw");
--
1.7.6.5
Re: [Qemu-devel] [Qemu-trivial] [PATCH] arm_gic: Send dbg msgs to stderr not stdout
On Mon, Jun 18, 2012 at 11:00:18AM +1000, Peter A. G. Crosthwaite wrote: > Signed-off-by: Peter A. G. Crosthwaite > --- > hw/arm_gic.c |2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) Thanks, applied to the trivial patches tree: https://github.com/stefanha/qemu/commits/trivial-patches Stefan
[Qemu-devel] [PATCH 0/2] Floppy geometry cleanup
Markus Armbruster (2): fdc: Drop broken code for user-defined floppy geometry fdc: Move floppy geometry guessing back from block.c block.c | 107 - block.h | 18 - hw/fdc.c | 125 +++-- hw/fdc.h | 10 - hw/pc.c | 13 +- 5 files changed, 124 insertions(+), 149 deletions(-) -- 1.7.6.5
[Qemu-devel] [PATCHv3 09/14] unicore32-softmmu: Add puv3 ostimer support
This patch adds puv3 ostimer support, include os timer
device simulation and ptimer support in puv3 machine.
Signed-off-by: Guan Xuetao
---
default-configs/unicore32-softmmu.mak |1 +
hw/Makefile.objs |1 +
hw/puv3.c |3 +
hw/puv3_ost.c | 151 +
4 files changed, 156 insertions(+), 0 deletions(-)
create mode 100644 hw/puv3_ost.c
diff --git a/default-configs/unicore32-softmmu.mak
b/default-configs/unicore32-softmmu.mak
index 726a338..4d4fbfc 100644
--- a/default-configs/unicore32-softmmu.mak
+++ b/default-configs/unicore32-softmmu.mak
@@ -1,2 +1,3 @@
# Default configuration for unicore32-softmmu
CONFIG_PUV3=y
+CONFIG_PTIMER=y
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 96a3c07..a769058 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -68,6 +68,7 @@ hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
# PKUnity SoC devices
hw-obj-$(CONFIG_PUV3) += puv3_intc.o
+hw-obj-$(CONFIG_PUV3) += puv3_ost.o
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/puv3.c b/hw/puv3.c
index 690e4f8..6164a4d 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -46,6 +46,9 @@ static void puv3_soc_init(CPUUniCore32State *env)
for (i = 0; i < PUV3_IRQS_NR; i++) {
irqs[i] = qdev_get_gpio_in(dev, i);
}
+
+/* Initialize minimal necessary devices for kernel booting */
+sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]);
}
static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
diff --git a/hw/puv3_ost.c b/hw/puv3_ost.c
new file mode 100644
index 000..6c90050
--- /dev/null
+++ b/hw/puv3_ost.c
@@ -0,0 +1,151 @@
+/*
+ * OSTimer device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "sysbus.h"
+#include "ptimer.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+/* puv3 ostimer implementation. */
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+QEMUBH *bh;
+qemu_irq irq;
+ptimer_state *ptimer;
+
+uint32_t reg_OSMR0;
+uint32_t reg_OSCR;
+uint32_t reg_OSSR;
+uint32_t reg_OIER;
+} PUV3OSTState;
+
+static uint64_t puv3_ost_read(void *opaque, target_phys_addr_t offset,
+unsigned size)
+{
+PUV3OSTState *s = (PUV3OSTState *)opaque;
+uint32_t ret = 0;
+
+switch (offset) {
+case 0x10: /* Counter Register */
+ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer);
+break;
+case 0x14: /* Status Register */
+ret = s->reg_OSSR;
+break;
+case 0x1c: /* Interrupt Enable Register */
+ret = s->reg_OIER;
+break;
+default:
+hw_error("puv3_ost_read: Bad offset %x\n", (int)offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+return ret;
+}
+
+static void puv3_ost_write(void *opaque, target_phys_addr_t offset,
+uint64_t value, unsigned size)
+{
+PUV3OSTState *s = (PUV3OSTState *)opaque;
+
+DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+switch (offset) {
+case 0x00: /* Match Register 0 */
+s->reg_OSMR0 = value;
+if (s->reg_OSMR0 > s->reg_OSCR) {
+ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
+} else {
+ptimer_set_count(s->ptimer, s->reg_OSMR0 +
+(0x - s->reg_OSCR));
+}
+ptimer_run(s->ptimer, 2);
+break;
+case 0x14: /* Status Register */
+assert(value == 0);
+if (s->reg_OSSR) {
+s->reg_OSSR = value;
+qemu_irq_lower(s->irq);
+}
+break;
+case 0x1c: /* Interrupt Enable Register */
+s->reg_OIER = value;
+break;
+default:
+hw_error("puv3_ost_write: Bad offset %x\n", (int)offset);
+}
+}
+
+static const MemoryRegionOps puv3_ost_ops = {
+.read = puv3_ost_read,
+.write = puv3_ost_write,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void puv3_ost_tick(void *opaque)
+{
+PUV3OSTState *s = (PUV3OSTState *)opaque;
+
+DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n",
+s->reg_OSCR, s->reg_OSMR0);
+
+s->reg_OSCR = s->reg_OSMR0;
+if (s->reg_OIER) {
+s->reg_OSSR = 1;
+qemu_irq_raise(s->irq);
+}
+}
+
+static int puv3_ost_init(SysBusDevice *dev)
+{
+PUV3OSTState *s = FROM_SYSBUS(PUV3OSTState, dev);
+
+s->reg_OIER = 0;
+s->reg_OSSR = 0;
+s->reg_OSMR0 = 0;
+s->reg_OSCR = 0;
+
+sysbus_init_irq(dev, &s->irq);
+
+s->bh = qemu_bh_new(puv3_ost_tick, s);
+s->ptimer = ptimer_init(s->b
Re: [Qemu-devel] [PATCH v3 0/8] msix: Support specifying offsets, BARs, and capability location
On Mon, Jun 18, 2012 at 11:23:41AM +0200, Jan Kiszka wrote: > On 2012-06-18 09:19, Michael S. Tsirkin wrote: > > On Mon, Jun 18, 2012 at 09:06:01AM +0200, Jan Kiszka wrote: > >> On 2012-06-14 23:31, Michael S. Tsirkin wrote: > >>> On Thu, Jun 14, 2012 at 12:15:42PM -0600, Alex Williamson wrote: > v3: > - more patches, smaller diff, must be headed in the right direction > - macros for all hardcoded values in msix_init_exclusive_bar > - fold msix_add_config into msix_init allowing less churn to moving > around msix_uninit > - note native endian bug > - split msix_mmio_read move to separate patch > - split changing return value of msix_uninit to separate patch > > Thanks, > > Alex > >>> > >>> Thanks, applied all. > >>> Will test/push next week. > >> > >> Could you publish your queue? I'd like to rebase my missing bits. > >> > >> Thanks, > >> Ja > >> > > > > Will do. FYI Anthony said on irc he objects to the caching approach, > > asked for more time to review it all. Maybe we'll have to > > go back to your original idea of a special API just for > > assigned devices. > > Yes, we can still add caching on top. > > I really like to have some hook upstream soon as time is running out > quickly for the 1.2 merge window and there is still some work to do on > the qemu-kvm side. > > Jan Anthony are your ideas for 1.2 timeframe? > -- > Siemens AG, Corporate Technology, CT T DE IT 1 > Corporate Competence Center Embedded Linux
[Qemu-devel] [PATCHv3 12/14] unicore32-softmmu: Add puv3 dma support
This patch adds puv3 dma (Direct Memory Access) support,
include dma device simulation for kernel booting.
Signed-off-by: Guan Xuetao
---
hw/Makefile.objs |1 +
hw/puv3.c|1 +
hw/puv3_dma.c| 109 ++
3 files changed, 111 insertions(+), 0 deletions(-)
create mode 100644 hw/puv3_dma.c
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 4641373..4aabb6f 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -71,6 +71,7 @@ hw-obj-$(CONFIG_PUV3) += puv3_intc.o
hw-obj-$(CONFIG_PUV3) += puv3_ost.o
hw-obj-$(CONFIG_PUV3) += puv3_gpio.o
hw-obj-$(CONFIG_PUV3) += puv3_pm.o
+hw-obj-$(CONFIG_PUV3) += puv3_dma.o
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/puv3.c b/hw/puv3.c
index c86613d..2fd02d1 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -49,6 +49,7 @@ static void puv3_soc_init(CPUUniCore32State *env)
/* Initialize minimal necessary devices for kernel booting */
sysbus_create_simple("puv3_pm", PUV3_PM_BASE, NULL);
+sysbus_create_simple("puv3_dma", PUV3_DMA_BASE, NULL);
sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]);
sysbus_create_varargs("puv3_gpio", PUV3_GPIO_BASE,
irqs[PUV3_IRQS_GPIOLOW0], irqs[PUV3_IRQS_GPIOLOW1],
diff --git a/hw/puv3_dma.c b/hw/puv3_dma.c
new file mode 100644
index 000..6b41906
--- /dev/null
+++ b/hw/puv3_dma.c
@@ -0,0 +1,109 @@
+/*
+ * DMA device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "hw.h"
+#include "sysbus.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+#define PUV3_DMA_CH_NR (6)
+#define PUV3_DMA_CH_MASK(0xff)
+#define PUV3_DMA_CH(offset) ((offset) >> 8)
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+uint32_t reg_CFG[PUV3_DMA_CH_NR];
+} PUV3DMAState;
+
+static uint64_t puv3_dma_read(void *opaque, target_phys_addr_t offset,
+unsigned size)
+{
+PUV3DMAState *s = (PUV3DMAState *) opaque;
+uint32_t ret;
+
+assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
+
+switch (offset & PUV3_DMA_CH_MASK) {
+case 0x10:
+ret = s->reg_CFG[PUV3_DMA_CH(offset)];
+break;
+default:
+hw_error("%s: Bad offset 0x%x\n", __func__, offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+
+return ret;
+}
+
+static void puv3_dma_write(void *opaque, target_phys_addr_t offset,
+uint64_t value, unsigned size)
+{
+PUV3DMAState *s = (PUV3DMAState *) opaque;
+
+assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
+
+switch (offset & PUV3_DMA_CH_MASK) {
+case 0x10:
+s->reg_CFG[PUV3_DMA_CH(offset)] = value;
+break;
+default:
+hw_error("%s: Bad offset 0x%x\n", __func__, offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+}
+
+static const MemoryRegionOps puv3_dma_ops = {
+.read = puv3_dma_read,
+.write = puv3_dma_write,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int puv3_dma_init(SysBusDevice *dev)
+{
+PUV3DMAState *s = FROM_SYSBUS(PUV3DMAState, dev);
+int i;
+
+for (i = 0; i < PUV3_DMA_CH_NR; i++) {
+s->reg_CFG[i] = 0x0;
+}
+
+memory_region_init_io(&s->iomem, &puv3_dma_ops, s, "puv3_dma",
+PUV3_REGS_OFFSET);
+sysbus_init_mmio(dev, &s->iomem);
+
+return 0;
+}
+
+static void puv3_dma_class_init(ObjectClass *klass, void *data)
+{
+SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+sdc->init = puv3_dma_init;
+}
+
+static const TypeInfo puv3_dma_info = {
+.name = "puv3_dma",
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(PUV3DMAState),
+.class_init = puv3_dma_class_init,
+};
+
+static void puv3_dma_register_type(void)
+{
+type_register_static(&puv3_dma_info);
+}
+
+type_init(puv3_dma_register_type)
--
1.7.0.4
Re: [Qemu-devel] Any better way to access CPUArchState in vl.c?
Hi Wei-Ren, Am 18.06.2012 09:47, schrieb 陳韋任 (Wei-Ren Chen): > Say I want to print env->some_field in vl.c. I #include "dyngen-exec.h" > in vl.c, but got compilation error immediately. > > /tmp/chenwj/qemu/dyngen-exec.h:64:10: error: attempt to use poisoned > "CPUArchState" > /tmp/chenwj/qemu/dyngen-exec.h:64:23: error: expected '=', ',', ';', 'asm' > or '__attribute__' before '*' token > /tmp/chenwj/qemu/dyngen-exec.h:64:24: error: attempt to use poisoned "env" > > After googling, I figure out QEMU poison some identifiers which cannot be used > in target indenpent code. Although we can get some_field by the following way, > > int some_field = &env->some_field; > > but it's not very convenient if we have many field of CPUState want to > access. Is > there a better way to do so? Thanks! Poisoned is the "env" variable. You cannot just #include "dyngen-exec.h" and expect it to be usable since AREG0 targets don't guarantee it's set properly (may be NULL even with traditional targets at times). CPUArchState should currently be usable in vl.c, you just need explicit access to it (e.g., a function argument). Question is, what are you trying to do? In particular, of which CPU (think SMP) are you trying to print ->some_field? :) Regards, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
[Qemu-devel] [PATCHv3 03/14] unicore32-softmmu: Make UniCore32 cpuid & exceptions correct and runable
This patch initializes the cpuid to exactly correct value because
linux kernel will check it.
In addition, the exception types are specified in proper situations.
Then it could make exceptions generated correctly and timely.
Signed-off-by: Guan Xuetao
---
cpu-exec.c |1 +
linux-user/main.c |3 ++-
target-unicore32/cpu.c | 19 ++-
target-unicore32/cpu.h |8 +---
4 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 624c409..534bcba 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -419,6 +419,7 @@ int cpu_exec(CPUArchState *env)
#elif defined(TARGET_UNICORE32)
if (interrupt_request & CPU_INTERRUPT_HARD
&& !(env->uncached_asr & ASR_I)) {
+env->exception_index = UC32_EXCP_INTR;
do_interrupt(env);
next_tb = 0;
}
diff --git a/linux-user/main.c b/linux-user/main.c
index 49108b8..18f261d 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -958,7 +958,8 @@ void cpu_loop(CPUUniCore32State *env)
}
}
break;
-case UC32_EXCP_TRAP:
+case UC32_EXCP_DTRAP:
+case UC32_EXCP_ITRAP:
info.si_signo = SIGSEGV;
info.si_errno = 0;
/* XXX: check env->error_code */
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index de63f58..3425bbe 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -1,7 +1,7 @@
/*
* QEMU UniCore32 CPU
*
- * Copyright (c) 2010-2011 GUAN Xue-tao
+ * Copyright (c) 2010-2012 Guan Xuetao
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
* This program is free software; you can redistribute it and/or modify
@@ -32,13 +32,16 @@ static void unicore_ii_cpu_initfn(Object *obj)
UniCore32CPU *cpu = UNICORE32_CPU(obj);
CPUUniCore32State *env = &cpu->env;
-env->cp0.c0_cpuid = 0x40010863;
+env->cp0.c0_cpuid = 0x4d000863;
+env->cp0.c0_cachetype = 0x0d152152;
+env->cp0.c1_sys = 0x2000;
+env->cp0.c2_base = 0x0;
+env->cp0.c3_faultstatus = 0x0;
+env->cp0.c4_faultaddr = 0x0;
+env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
set_feature(env, UC32_HWCAP_CMOV);
set_feature(env, UC32_HWCAP_UCF64);
-env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
-env->cp0.c0_cachetype = 0x1dd20d2;
-env->cp0.c1_sys = 0x00090078;
}
static void uc32_any_cpu_initfn(Object *obj)
@@ -47,6 +50,7 @@ static void uc32_any_cpu_initfn(Object *obj)
CPUUniCore32State *env = &cpu->env;
env->cp0.c0_cpuid = 0x;
+env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
set_feature(env, UC32_HWCAP_CMOV);
set_feature(env, UC32_HWCAP_UCF64);
@@ -65,8 +69,13 @@ static void uc32_cpu_initfn(Object *obj)
cpu_exec_init(env);
env->cpu_model_str = object_get_typename(obj);
+#ifdef CONFIG_USER_ONLY
env->uncached_asr = ASR_MODE_USER;
env->regs[31] = 0;
+#else
+env->uncached_asr = ASR_MODE_PRIV;
+env->regs[31] = 0x0300;
+#endif
tlb_flush(env, 1);
}
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 81c14ff..91766a4 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -1,7 +1,7 @@
/*
* UniCore32 virtual CPU header
*
- * Copyright (C) 2010-2011 GUAN Xue-tao
+ * Copyright (C) 2010-2012 Guan Xuetao
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -89,8 +89,10 @@ typedef struct CPUUniCore32State {
#define ASR_NZCV(ASR_N | ASR_Z | ASR_C | ASR_V)
#define ASR_RESERVED(~(ASR_M | ASR_I | ASR_NZCV))
-#define UC32_EXCP_PRIV (ASR_MODE_PRIV)
-#define UC32_EXCP_TRAP (ASR_MODE_TRAP)
+#define UC32_EXCP_PRIV (1)
+#define UC32_EXCP_ITRAP (2)
+#define UC32_EXCP_DTRAP (3)
+#define UC32_EXCP_INTR (4)
/* Return the current ASR value. */
target_ulong cpu_asr_read(CPUUniCore32State *env1);
--
1.7.0.4
[Qemu-devel] [PATCHv3 06/14] unicore32-softmmu: Make sure that kernel can access user space
As a matter of course, we need to access user space in kernel code,
so we need to correct load/store decoders to indicate correct memory
region.
Signed-off-by: Guan Xuetao
---
target-unicore32/translate.c | 36 ++--
1 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index fd51a61..f3c3d71 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -33,9 +33,16 @@ typedef struct DisasContext {
int condlabel;
struct TranslationBlock *tb;
int singlestep_enabled;
+#ifndef CONFIG_USER_ONLY
+int user;
+#endif
} DisasContext;
-#define IS_USER(s) 1
+#ifndef CONFIG_USER_ONLY
+#define IS_USER(s) (s->user)
+#else
+#define IS_USER(s) 1
+#endif
/* These instructions trap after executing, so defer them until after the
conditional executions state has been updated. */
@@ -1551,12 +1558,12 @@ static void do_misc(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
/* load/store I_offset and R_offset */
static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
-unsigned int i;
+unsigned int mmu_idx;
TCGv tmp;
TCGv tmp2;
tmp2 = load_reg(s, UCOP_REG_N);
-i = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
+mmu_idx = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
/* immediate */
if (UCOP_SET_P) {
@@ -1566,17 +1573,17 @@ static void do_ldst_ir(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
if (UCOP_SET_L) {
/* load */
if (UCOP_SET_B) {
-tmp = gen_ld8u(tmp2, i);
+tmp = gen_ld8u(tmp2, mmu_idx);
} else {
-tmp = gen_ld32(tmp2, i);
+tmp = gen_ld32(tmp2, mmu_idx);
}
} else {
/* store */
tmp = load_reg(s, UCOP_REG_D);
if (UCOP_SET_B) {
-gen_st8(tmp, tmp2, i);
+gen_st8(tmp, tmp2, mmu_idx);
} else {
-gen_st32(tmp, tmp2, i);
+gen_st32(tmp, tmp2, mmu_idx);
}
}
if (!UCOP_SET_P) {
@@ -1679,7 +1686,7 @@ static void do_ldst_hwsb(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
/* load/store multiple words */
static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
-unsigned int val, i;
+unsigned int val, i, mmu_idx;
int j, n, reg, user, loaded_base;
TCGv tmp;
TCGv tmp2;
@@ -1700,6 +1707,7 @@ static void do_ldst_m(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
}
}
+mmu_idx = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
addr = load_reg(s, UCOP_REG_N);
/* compute total size */
@@ -1744,7 +1752,7 @@ static void do_ldst_m(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
}
if (UCOP_SET(i)) {
if (UCOP_SET_L) { /* load */
-tmp = gen_ld32(addr, IS_USER(s));
+tmp = gen_ld32(addr, mmu_idx);
if (reg == 31) {
gen_bx(s, tmp);
} else if (user) {
@@ -1772,7 +1780,7 @@ static void do_ldst_m(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
} else {
tmp = load_reg(s, reg);
}
-gen_st32(tmp, addr, IS_USER(s));
+gen_st32(tmp, addr, mmu_idx);
}
j++;
/* no need to add after the last transfer */
@@ -1961,6 +1969,14 @@ static inline void
gen_intermediate_code_internal(CPUUniCore32State *env,
max_insns = CF_COUNT_MASK;
}
+#ifndef CONFIG_USER_ONLY
+if ((env->uncached_asr & ASR_M) == ASR_MODE_USER) {
+dc->user = 1;
+} else {
+dc->user = 0;
+}
+#endif
+
gen_icount_start();
do {
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
--
1.7.0.4
Re: [Qemu-devel] [RFC] ARMCPU: Halting a CPU from Device Land
Hi Peter,
Am 18.06.2012 09:22, schrieb Peter Crosthwaite:
> Hi Andreas,
>
> For the Xilinx Zynq platform, we need to be able to halt a CPU from a
> device (the zynq_slcr). E.G, if I write a 1 to a register bit in my
> device, then that device effects a halt of a CPU. Looking at the QOM
> stuff the API for a CPU is (include/qemu/cpu.h):
>
> typedef struct CPUClass {
> /*< private >*/
> ObjectClass parent_class;
> /*< public >*/
>
> void (*reset)(CPUState *cpu);
> } CPUClass;
>
> The only API function is to reset a CPU. Thats means that if I link up
> my CPU to my device the only thing it can do is reset the CPU? Are
> there plans to extend this API to include some common functions such
> as halting and resuming etc? How hard is this to do in a generic (non
> ARM) way?
>
> Peter,
>
> Can it be done is an ARM specific way? Is there a one line killer to
> halt an ARM cpu that we could add the to ARMCPU API?
I'll answer both:
There's the QOM CPUState part 4 series on the list that sequentially
moves more and more fields into CPUState. So far the good news. The bad
news is that merging the halted field movement - despite on the list -
depends on refactorings of the TLB that I haven't gotten around to yet.
(Still caught up in packaging v1.1.)
The ARM-specific way is to cast your CPUState with ARM_CPU(), assuming
your Zynq device is compiled per target like most ARM devices currently
are, then you can access ->env (CPUARMState), which still has the halted
field.
Cheers,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
[Qemu-devel] [PATCHv3 05/14] unicore32-softmmu: Implement softmmu specific functions
This patch implements softmmu specific functions, include tlb_fill,
switch_mode, do_interrupt and uc32_cpu_handle_mmu_fault.
So the full exception handlers and page table walking could work now.
Signed-off-by: Guan Xuetao
---
target-unicore32/op_helper.c | 22 -
target-unicore32/softmmu.c | 236 +-
2 files changed, 253 insertions(+), 5 deletions(-)
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index d96d2c8..8ecab86 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -267,6 +267,26 @@ uint32_t HELPER(ror_cc)(uint32_t x, uint32_t i)
void tlb_fill(CPUUniCore32State *env1, target_ulong addr, int is_write, int
mmu_idx,
uintptr_t retaddr)
{
-cpu_abort(env, "%s not supported yet\n", __func__);
+TranslationBlock *tb;
+CPUUniCore32State *saved_env;
+unsigned long pc;
+int ret;
+
+saved_env = env;
+env = env1;
+ret = uc32_cpu_handle_mmu_fault(env, addr, is_write, mmu_idx);
+if (unlikely(ret)) {
+if (retaddr) {
+/* now we have a real cpu fault */
+pc = (unsigned long)retaddr;
+tb = tb_find_pc(pc);
+if (tb) {/* the PC is inside the translated code.
+It means that we have a virtual CPU fault */
+cpu_restore_state(tb, env, pc);
+}
+}
+cpu_loop_exit(env);
+}
+env = saved_env;
}
#endif
diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
index 6fec77e..373f94b 100644
--- a/target-unicore32/softmmu.c
+++ b/target-unicore32/softmmu.c
@@ -14,21 +14,249 @@
#include
+#undef DEBUG_UC32
+
+#ifdef DEBUG_UC32
+#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...) do {} while (0)
+#endif
+
+#define SUPERPAGE_SIZE (1 << 22)
+#define UC32_PAGETABLE_READ(1 << 8)
+#define UC32_PAGETABLE_WRITE (1 << 7)
+#define UC32_PAGETABLE_EXEC(1 << 6)
+#define UC32_PAGETABLE_EXIST (1 << 2)
+#define PAGETABLE_TYPE(x) ((x) & 3)
+
+
+/* Map CPU modes onto saved register banks. */
+static inline int bank_number(int mode)
+{
+switch (mode) {
+case ASR_MODE_USER:
+case ASR_MODE_SUSR:
+return 0;
+case ASR_MODE_PRIV:
+return 1;
+case ASR_MODE_TRAP:
+return 2;
+case ASR_MODE_EXTN:
+return 3;
+case ASR_MODE_INTR:
+return 4;
+}
+cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
+return -1;
+}
+
void switch_mode(CPUUniCore32State *env, int mode)
{
-cpu_abort(env, "%s not supported yet\n", __func__);
+int old_mode;
+int i;
+
+old_mode = env->uncached_asr & ASR_M;
+if (mode == old_mode) {
+return;
+}
+
+i = bank_number(old_mode);
+env->banked_r29[i] = env->regs[29];
+env->banked_r30[i] = env->regs[30];
+env->banked_bsr[i] = env->bsr;
+
+i = bank_number(mode);
+env->regs[29] = env->banked_r29[i];
+env->regs[30] = env->banked_r30[i];
+env->bsr = env->banked_bsr[i];
}
+/* Handle a CPU exception. */
void do_interrupt(CPUUniCore32State *env)
{
-cpu_abort(env, "%s not supported yet\n", __func__);
+uint32_t addr;
+int new_mode;
+
+switch (env->exception_index) {
+case UC32_EXCP_PRIV:
+new_mode = ASR_MODE_PRIV;
+addr = 0x08;
+break;
+case UC32_EXCP_ITRAP:
+DPRINTF("itrap happened at %x\n", env->regs[31]);
+new_mode = ASR_MODE_TRAP;
+addr = 0x0c;
+break;
+case UC32_EXCP_DTRAP:
+DPRINTF("dtrap happened at %x\n", env->regs[31]);
+new_mode = ASR_MODE_TRAP;
+addr = 0x10;
+break;
+case UC32_EXCP_INTR:
+new_mode = ASR_MODE_INTR;
+addr = 0x18;
+break;
+default:
+cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
+return;
+}
+/* High vectors. */
+if (env->cp0.c1_sys & (1 << 13)) {
+addr += 0x;
+}
+
+switch_mode(env, new_mode);
+env->bsr = cpu_asr_read(env);
+env->uncached_asr = (env->uncached_asr & ~ASR_M) | new_mode;
+env->uncached_asr |= ASR_I;
+/* The PC already points to the proper instruction. */
+env->regs[30] = env->regs[31];
+env->regs[31] = addr;
+env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+}
+
+static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
+int access_type, int is_user, uint32_t *phys_ptr, int *prot,
+target_ulong *page_size)
+{
+int code;
+uint32_t table;
+uint32_t desc;
+uint32_t phys_addr;
+
+/* Pagetable walk. */
+/* Lookup l1 descriptor. */
+table = env->cp0.c2_base & 0xf000;
+table |= (address >> 20) & 0xffc;
+desc = ldl_phys(table);
+code = 0;
+switch (PAGETABLE_TYPE(desc)) {
+case 3:
+/* Superpage */
+if (!(desc & UC32_PAGETABLE_EXIST)) {
+
[Qemu-devel] [PATCHv3 14/14] unicore32-softmmu: Add maintainer information for UniCore32 machine
Signed-off-by: Guan Xuetao --- MAINTAINERS |7 +++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index b45f075..eb5d93a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -394,6 +394,13 @@ M: Alexander Graf S: Maintained F: hw/s390-*.c +UniCore32 Machines +- +PKUnity-3 SoC initramfs-with-busybox +M: Guan Xuetao +S: Maintained +F: hw/puv3* + X86 Machines PC -- 1.7.0.4
[Qemu-devel] [PATCHv3 13/14] unicore32-softmmu: Add ps2 support
This patch adds ps2/keyboard support, and enables CONFIG_PCKBD.
Signed-off-by: Guan Xuetao
---
default-configs/unicore32-softmmu.mak |1 +
hw/puv3.c |5 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/default-configs/unicore32-softmmu.mak
b/default-configs/unicore32-softmmu.mak
index 4d4fbfc..de38577 100644
--- a/default-configs/unicore32-softmmu.mak
+++ b/default-configs/unicore32-softmmu.mak
@@ -1,3 +1,4 @@
# Default configuration for unicore32-softmmu
CONFIG_PUV3=y
CONFIG_PTIMER=y
+CONFIG_PCKBD=y
diff --git a/hw/puv3.c b/hw/puv3.c
index 2fd02d1..389271f 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -38,6 +38,7 @@ static void puv3_soc_init(CPUUniCore32State *env)
{
qemu_irq *cpu_intc, irqs[PUV3_IRQS_NR];
DeviceState *dev;
+MemoryRegion *i8042 = g_new(MemoryRegion, 1);
int i;
/* Initialize interrupt controller */
@@ -57,6 +58,10 @@ static void puv3_soc_init(CPUUniCore32State *env)
irqs[PUV3_IRQS_GPIOLOW4], irqs[PUV3_IRQS_GPIOLOW5],
irqs[PUV3_IRQS_GPIOLOW6], irqs[PUV3_IRQS_GPIOLOW7],
irqs[PUV3_IRQS_GPIOHIGH], NULL);
+
+/* Keyboard (i8042), mouse disabled for nographic */
+i8042_mm_init(irqs[PUV3_IRQS_PS2_KBD], NULL, i8042, PUV3_REGS_OFFSET, 4);
+memory_region_add_subregion(get_system_memory(), PUV3_PS2_BASE, i8042);
}
static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
--
1.7.0.4
[Qemu-devel] [PATCHv3 10/14] unicore32-softmmu: Add puv3 gpio support
This patch adds puv3 gpio (General Purpose Input/Output) support,
include gpio device simulation and its interrupt support.
Signed-off-by: Guan Xuetao
---
hw/Makefile.objs |1 +
hw/puv3.c|6 ++
hw/puv3_gpio.c | 141 ++
3 files changed, 148 insertions(+), 0 deletions(-)
create mode 100644 hw/puv3_gpio.c
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index a769058..a9709f5 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -69,6 +69,7 @@ hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
# PKUnity SoC devices
hw-obj-$(CONFIG_PUV3) += puv3_intc.o
hw-obj-$(CONFIG_PUV3) += puv3_ost.o
+hw-obj-$(CONFIG_PUV3) += puv3_gpio.o
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/puv3.c b/hw/puv3.c
index 6164a4d..80aaa27 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -49,6 +49,12 @@ static void puv3_soc_init(CPUUniCore32State *env)
/* Initialize minimal necessary devices for kernel booting */
sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]);
+sysbus_create_varargs("puv3_gpio", PUV3_GPIO_BASE,
+irqs[PUV3_IRQS_GPIOLOW0], irqs[PUV3_IRQS_GPIOLOW1],
+irqs[PUV3_IRQS_GPIOLOW2], irqs[PUV3_IRQS_GPIOLOW3],
+irqs[PUV3_IRQS_GPIOLOW4], irqs[PUV3_IRQS_GPIOLOW5],
+irqs[PUV3_IRQS_GPIOLOW6], irqs[PUV3_IRQS_GPIOLOW7],
+irqs[PUV3_IRQS_GPIOHIGH], NULL);
}
static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
diff --git a/hw/puv3_gpio.c b/hw/puv3_gpio.c
new file mode 100644
index 000..2c1b44b
--- /dev/null
+++ b/hw/puv3_gpio.c
@@ -0,0 +1,141 @@
+/*
+ * GPIO device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "hw.h"
+#include "sysbus.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+qemu_irq irq[9];
+
+uint32_t reg_GPLR;
+uint32_t reg_GPDR;
+uint32_t reg_GPIR;
+} PUV3GPIOState;
+
+static uint64_t puv3_gpio_read(void *opaque, target_phys_addr_t offset,
+unsigned size)
+{
+PUV3GPIOState *s = (PUV3GPIOState *) opaque;
+uint32_t ret;
+
+switch (offset) {
+case 0x00:
+ret = s->reg_GPLR;
+break;
+case 0x04:
+ret = s->reg_GPDR;
+break;
+case 0x20:
+ret = s->reg_GPIR;
+break;
+default:
+hw_error("%s: Bad offset 0x%x\n", __func__, offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+
+return ret;
+}
+
+static void puv3_gpio_write(void *opaque, target_phys_addr_t offset,
+uint64_t value, unsigned size)
+{
+PUV3GPIOState *s = (PUV3GPIOState *) opaque;
+
+DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+switch (offset) {
+case 0x04:
+s->reg_GPDR = value;
+break;
+case 0x08:
+if (s->reg_GPDR & value) {
+s->reg_GPLR |= value;
+} else {
+hw_error("write gpio input port error!");
+}
+break;
+case 0x0c:
+if (s->reg_GPDR & value) {
+s->reg_GPLR &= ~value;
+} else {
+hw_error("write gpio input port error!");
+}
+break;
+case 0x10: /* GRER */
+case 0x14: /* GFER */
+case 0x18: /* GEDR */
+break;
+case 0x20: /* GPIR */
+s->reg_GPIR = value;
+break;
+default:
+hw_error("%s: Bad offset 0x%x\n", __func__, offset);
+}
+}
+
+static const MemoryRegionOps puv3_gpio_ops = {
+.read = puv3_gpio_read,
+.write = puv3_gpio_write,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int puv3_gpio_init(SysBusDevice *dev)
+{
+PUV3GPIOState *s = FROM_SYSBUS(PUV3GPIOState, dev);
+
+s->reg_GPLR = 0;
+s->reg_GPDR = 0;
+
+/* FIXME: these irqs not handled yet */
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW0]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW1]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW2]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW3]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW4]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW5]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW6]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW7]);
+sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOHIGH]);
+
+memory_region_init_io(&s->iomem, &puv3_gpio_ops, s, "puv3_gpio",
+PUV3_REGS_OFFSET);
+sysbus_init_mmio(dev, &s->iomem);
+
+return 0;
+}
+
+static void puv3_gpio_class_init(ObjectClass *klass, void *data)
+{
+SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLA
[Qemu-devel] [PATCHv3 11/14] unicore32-softmmu: Add puv3 pm support
This patch adds puv3 pm (power management) support,
include pm device simulation for kernel booting.
Signed-off-by: Guan Xuetao
---
hw/Makefile.objs |1 +
hw/puv3.c|1 +
hw/puv3_pm.c | 148 ++
3 files changed, 150 insertions(+), 0 deletions(-)
create mode 100644 hw/puv3_pm.c
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index a9709f5..4641373 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -70,6 +70,7 @@ hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
hw-obj-$(CONFIG_PUV3) += puv3_intc.o
hw-obj-$(CONFIG_PUV3) += puv3_ost.o
hw-obj-$(CONFIG_PUV3) += puv3_gpio.o
+hw-obj-$(CONFIG_PUV3) += puv3_pm.o
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/puv3.c b/hw/puv3.c
index 80aaa27..c86613d 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -48,6 +48,7 @@ static void puv3_soc_init(CPUUniCore32State *env)
}
/* Initialize minimal necessary devices for kernel booting */
+sysbus_create_simple("puv3_pm", PUV3_PM_BASE, NULL);
sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]);
sysbus_create_varargs("puv3_gpio", PUV3_GPIO_BASE,
irqs[PUV3_IRQS_GPIOLOW0], irqs[PUV3_IRQS_GPIOLOW1],
diff --git a/hw/puv3_pm.c b/hw/puv3_pm.c
new file mode 100644
index 000..4b914ed
--- /dev/null
+++ b/hw/puv3_pm.c
@@ -0,0 +1,148 @@
+/*
+ * Power Management device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "hw.h"
+#include "sysbus.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion iomem;
+
+uint32_t reg_PMCR;
+uint32_t reg_PCGR;
+uint32_t reg_PLL_SYS_CFG;
+uint32_t reg_PLL_DDR_CFG;
+uint32_t reg_PLL_VGA_CFG;
+uint32_t reg_DIVCFG;
+} PUV3PMState;
+
+static uint64_t puv3_pm_read(void *opaque, target_phys_addr_t offset,
+unsigned size)
+{
+PUV3PMState *s = (PUV3PMState *) opaque;
+uint32_t ret;
+
+switch (offset) {
+case 0x14:
+ret = s->reg_PCGR;
+break;
+case 0x18:
+ret = s->reg_PLL_SYS_CFG;
+break;
+case 0x1c:
+ret = s->reg_PLL_DDR_CFG;
+break;
+case 0x20:
+ret = s->reg_PLL_VGA_CFG;
+break;
+case 0x24:
+ret = s->reg_DIVCFG;
+break;
+case 0x28: /* PLL SYS STATUS */
+ret = 0x2401;
+break;
+case 0x2c: /* PLL DDR STATUS */
+ret = 0x00100c00;
+break;
+case 0x30: /* PLL VGA STATUS */
+ret = 0x3801;
+break;
+case 0x34: /* DIV STATUS */
+ret = 0x22f52015;
+break;
+case 0x38: /* SW RESET */
+ret = 0x0;
+break;
+case 0x44: /* PLL DFC DONE */
+ret = 0x7;
+break;
+default:
+hw_error("%s: Bad offset 0x%x\n", __func__, offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+
+return ret;
+}
+
+static void puv3_pm_write(void *opaque, target_phys_addr_t offset,
+uint64_t value, unsigned size)
+{
+PUV3PMState *s = (PUV3PMState *) opaque;
+
+switch (offset) {
+case 0x0:
+s->reg_PMCR = value;
+case 0x14:
+s->reg_PCGR = value;
+break;
+case 0x18:
+s->reg_PLL_SYS_CFG = value;
+break;
+case 0x1c:
+s->reg_PLL_DDR_CFG = value;
+break;
+case 0x20:
+s->reg_PLL_VGA_CFG = value;
+break;
+case 0x24:
+case 0x38:
+break;
+default:
+hw_error("%s: Bad offset 0x%x\n", __func__, offset);
+}
+DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+}
+
+static const MemoryRegionOps puv3_pm_ops = {
+.read = puv3_pm_read,
+.write = puv3_pm_write,
+.impl = {
+.min_access_size = 4,
+.max_access_size = 4,
+},
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int puv3_pm_init(SysBusDevice *dev)
+{
+PUV3PMState *s = FROM_SYSBUS(PUV3PMState, dev);
+
+s->reg_PCGR = 0x0;
+
+memory_region_init_io(&s->iomem, &puv3_pm_ops, s, "puv3_pm",
+PUV3_REGS_OFFSET);
+sysbus_init_mmio(dev, &s->iomem);
+
+return 0;
+}
+
+static void puv3_pm_class_init(ObjectClass *klass, void *data)
+{
+SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+sdc->init = puv3_pm_init;
+}
+
+static const TypeInfo puv3_pm_info = {
+.name = "puv3_pm",
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(PUV3PMState),
+.class_init = puv3_pm_class_init,
+};
+
+static void puv3_pm_register_type(void)
+{
+type_register_static(&puv3_pm_info);
+}
+
+type_init(puv3_pm_register_type)
--
1.7.0.4
Re: [Qemu-devel] [PATCH] net: roll back qdev_prop_vlan
On Sun, Jun 17, 2012 at 12:30:32AM +0800, zwu.ker...@gmail.com wrote:
> +static int print_vlan(DeviceState *dev, Property *prop, char *dest, size_t
> len)
> +{
> +NetClientState **ptr = qdev_get_prop_ptr(dev, prop);
> +
> +if (*ptr) {
> +unsigned int id;
> +if (!net_hub_id_for_client(*ptr, &id)) {
> +return snprintf(dest, len, "%d", id);
Unsigned int should be %u. Source code scanners or the compiler could
warn about this so it's worth changing.
> +}
> +}
> +
> +return snprintf(dest, len, "");
> +}
> +
> +static void get_vlan(Object *obj, Visitor *v, void *opaque,
> + const char *name, Error **errp)
> +{
> +DeviceState *dev = DEVICE(obj);
> +Property *prop = opaque;
> +NetClientState **ptr = qdev_get_prop_ptr(dev, prop);
> +int64_t id = -1;
> +
> +if (*ptr) {
> +unsigned int hub_id;
> +net_hub_id_for_client(*ptr, &hub_id);
It's unclear what happens if net_hub_id_for_client() fails but it looks
like hub_id may be uninitialized.
Stefan
Re: [Qemu-devel] [PATCH v3 0/8] msix: Support specifying offsets, BARs, and capability location
On 2012-06-18 11:57, Michael S. Tsirkin wrote: > On Mon, Jun 18, 2012 at 11:23:41AM +0200, Jan Kiszka wrote: >> On 2012-06-18 09:19, Michael S. Tsirkin wrote: >>> On Mon, Jun 18, 2012 at 09:06:01AM +0200, Jan Kiszka wrote: On 2012-06-14 23:31, Michael S. Tsirkin wrote: > On Thu, Jun 14, 2012 at 12:15:42PM -0600, Alex Williamson wrote: >> v3: >> - more patches, smaller diff, must be headed in the right direction >> - macros for all hardcoded values in msix_init_exclusive_bar >> - fold msix_add_config into msix_init allowing less churn to moving >>around msix_uninit >> - note native endian bug >> - split msix_mmio_read move to separate patch >> - split changing return value of msix_uninit to separate patch >> >> Thanks, >> >> Alex > > Thanks, applied all. > Will test/push next week. Could you publish your queue? I'd like to rebase my missing bits. Thanks, Ja >>> >>> Will do. FYI Anthony said on irc he objects to the caching approach, >>> asked for more time to review it all. Maybe we'll have to >>> go back to your original idea of a special API just for >>> assigned devices. >> >> Yes, we can still add caching on top. >> >> I really like to have some hook upstream soon as time is running out >> quickly for the 1.2 merge window and there is still some work to do on >> the qemu-kvm side. >> >> Jan > > Anthony are your ideas for 1.2 timeframe? http://wiki.qemu.org/Planning/1.2 Jan -- Siemens AG, Corporate Technology, CT T DE IT 1 Corporate Competence Center Embedded Linux
Re: [Qemu-devel] [PATCH] make: automatically include dependencies in recursive subdir rules (v2)
Am 18.06.2012 11:31, schrieb Peter Maydell: > On 18 June 2012 10:13, Jan Kiszka wrote: >> On 2012-06-18 02:32, Andreas Färber wrote: >>> This will work technically but I still feel this is wrong semantically. >>> The pre-Paolo and current way is picking specific files from the hw/kvm/ >>> directory. Your change above implies that in hw/kvm/ only x86 files can >>> live, which I dislike. > >> Some per-arch separation is required, at least in the build process. >> We'll see power and arm stubs for in-kernel devices soon. > > Indeed -- I have a hw/kvm/arm_gic.c in the qemu-linaro tree, so > if you break building that I'll have to unbreak it :-) > > (Does architecture-specific separation make much sense in general? > Not all devices are architecture-specific. I'd have thought that > a functional split eg timer/serial/usb like the linux kernel layout > would be better.) Maybe you're misreading me? I was saying iff a device is specifically (not accidentally) for one target foo then it may/should be placed into hw/foo/ directory. We already have a hw/usb/ directory, and as long as there are no target dependencies and sufficient files I see nothing wrong with hw/timer/ or hw/serial/. Cheers, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH] make: automatically include dependencies in recursive subdir rules (v2)
On 18 June 2012 11:42, Andreas Färber wrote: > Am 18.06.2012 11:31, schrieb Peter Maydell: >> (Does architecture-specific separation make much sense in general? >> Not all devices are architecture-specific. I'd have thought that >> a functional split eg timer/serial/usb like the linux kernel layout >> would be better.) > > Maybe you're misreading me? I was saying iff a device is specifically > (not accidentally) for one target foo then it may/should be placed into > hw/foo/ directory. Yes, I'm saying that seems like a confusing split, because a few devices for target foo will be in hw/foo and a number more in hw/, and there'll probably be cases where something in hw/foo has to move out into hw/ when a new target comes along that happens to reuse it. So rather than having hw/foo where foo == target-name, I'm suggesting hw/foo where foo == kind-of-device. As you say we've already moved a bit down this road with usb, for instance. -- PMM
Re: [Qemu-devel] [PATCH] make: automatically include dependencies in recursive subdir rules (v2)
Am 18.06.2012 12:56, schrieb Peter Maydell: > On 18 June 2012 11:42, Andreas Färber wrote: >> Am 18.06.2012 11:31, schrieb Peter Maydell: >>> (Does architecture-specific separation make much sense in general? >>> Not all devices are architecture-specific. I'd have thought that >>> a functional split eg timer/serial/usb like the linux kernel layout >>> would be better.) >> >> Maybe you're misreading me? I was saying iff a device is specifically >> (not accidentally) for one target foo then it may/should be placed into >> hw/foo/ directory. > > Yes, I'm saying that seems like a confusing split, because a few > devices for target foo will be in hw/foo and a number more in hw/, > and there'll probably be cases where something in hw/foo has to > move out into hw/ when a new target comes along that happens to > reuse it. So rather than having hw/foo where foo == target-name, > I'm suggesting hw/foo where foo == kind-of-device. As you say > we've already moved a bit down this road with usb, for instance. But the point is that hw/foo/ is required for the new Makefile system, so we have the empty folders anyway, whereas putting target-specific stuff into, e.g., hw/apic/ will not solve the dependency issue that I tracked down here. If you do have an automated solution to that, please spill it out. :) Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [RFC] ARMCPU: Halting a CPU from Device Land
On Mon, Jun 18, 2012 at 8:07 PM, Andreas Färber wrote:
> Hi Peter,
>
> Am 18.06.2012 09:22, schrieb Peter Crosthwaite:
>> Hi Andreas,
>>
>> For the Xilinx Zynq platform, we need to be able to halt a CPU from a
>> device (the zynq_slcr). E.G, if I write a 1 to a register bit in my
>> device, then that device effects a halt of a CPU. Looking at the QOM
>> stuff the API for a CPU is (include/qemu/cpu.h):
>>
>> typedef struct CPUClass {
>> /*< private >*/
>> ObjectClass parent_class;
>> /*< public >*/
>>
>> void (*reset)(CPUState *cpu);
>> } CPUClass;
>>
>> The only API function is to reset a CPU. Thats means that if I link up
>> my CPU to my device the only thing it can do is reset the CPU? Are
>> there plans to extend this API to include some common functions such
>> as halting and resuming etc? How hard is this to do in a generic (non
>> ARM) way?
>>
>> Peter,
>>
>> Can it be done is an ARM specific way? Is there a one line killer to
>> halt an ARM cpu that we could add the to ARMCPU API?
>
> I'll answer both:
>
> There's the QOM CPUState part 4 series on the list that sequentially
> moves more and more fields into CPUState. So far the good news. The bad
> news is that merging the halted field movement - despite on the list -
> depends on refactorings of the TLB that I haven't gotten around to yet.
> (Still caught up in packaging v1.1.)
>
> The ARM-specific way is to cast your CPUState with ARM_CPU(), assuming
> your Zynq device is compiled per target like most ARM devices currently
> are, then you can access ->env (CPUARMState), which still has the halted
> field.
Hi Andreas,
So whats the sensible course of action implementation wise? #include
cpu.h in my device, cast to ARM_CPU(), ->env->halted = 1, with a /*
FIXME */ ?? Cos this approach seems hacky so is it really acceptable
if I were to create a series that does this today?
Regards,
Peter
>
> Cheers,
> Andreas
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH] make: automatically include dependencies in recursive subdir rules (v2)
On 18 June 2012 12:35, Andreas Färber wrote: > But the point is that hw/foo/ is required for the new Makefile system, > so we have the empty folders anyway, whereas putting target-specific > stuff into, e.g., hw/apic/ will not solve the dependency issue that I > tracked down here. Why should our makefile system mandate empty directories in the source tree hierarchy? That seems like a bug to me... -- PMM
Re: [Qemu-devel] [PATCH RFC] virtio-pci: add MMIO property
On Tue, Mar 20, 2012 at 10:22:42AM +1030, Rusty Russell wrote: > On Mon, 19 Mar 2012 17:13:06 -0500, Anthony Liguori > wrote: > > > Maybe just make this a hidden option like x-miio? > > > > x-violate-the-virtio-spec-to-trick-old-linux-drivers-into-working-on-power? > > "To configure the device, we use the first I/O region of the PCI > device." > > Meh, it does sound a little like we are specifying that it's an PCI I/O > bar. > > Let's resurrect the PCI-v2 idea, which is ready to implement now, and a > nice cleanup? Detach it from the change-of-ring-format idea which is > turning out to be a tarpit. > > Thanks, > Rusty. Yes. But it seems silly to even write code to play with device config in memory when we agreed the right thing to do is to use a config vq everywhere. Now a question: does a oconfig vq look like a PCI specific feature to you, a work-around for lack of multibyte atomic accesses? If yes it's sane to make it a PCI capability. Or is it something most transports would need? If yes we need a feature bit and this is a chicken and egg problem ... > -- > How could I marry someone with more hair than me? http://baldalex.org
Re: [Qemu-devel] [PATCH 0/8] s390: SCLP console and misc
Alex, are you going to pull the non-controversial patches? We would then send a reworked sclp patch set later on (when ready) - and everything that you also want us to rework. The alternative is to resend the considered good patches in a separate patch set. Christian
Re: [Qemu-devel] [PATCH] make: automatically include dependencies in recursive subdir rules (v2)
On 06/18/2012 04:13 AM, Jan Kiszka wrote: On 2012-06-18 02:32, Andreas Färber wrote: Am 18.06.2012 02:01, schrieb Anthony Liguori: This will work technically but I still feel this is wrong semantically. The pre-Paolo and current way is picking specific files from the hw/kvm/ directory. Your change above implies that in hw/kvm/ only x86 files can live, which I dislike. As suggested before, I would prefer if x86-only files were moved to an x86-specific location - the place for that existing since Paolo's refactoring would be hw/i386/. CC'ing Jan. That would match Paolo's reply in the unicore32 thread on future file placement. Alternatives would be hw/i386/kvm/ or hw/kvm/i386/; we're talking about a handful of files only though, so I don't think they require a new subdirectory. Some per-arch separation is required, at least in the build process. We'll see power and arm stubs for in-kernel devices soon. i8259.o i8254.o ioapic.o don't need to be arch specific apic.o ought to be renamed to lapic.o and moved to target-i386/kvm/ I think clock.o also more than likely belongs in target-i386/kvm/. It would have to be implemented as part of the CPU core if it ever existed IRL. In general, if is logically part of a CPU core, it ought to be in target-$(ARCH). Otherwise, it shouldn't be built as a target specific object. Regards, Anthony Liguori Jan
Re: [Qemu-devel] [PATCH] net: roll back qdev_prop_vlan
Good catch, thanks, please next version.
On Mon, Jun 18, 2012 at 6:22 PM, Stefan Hajnoczi
wrote:
> On Sun, Jun 17, 2012 at 12:30:32AM +0800, zwu.ker...@gmail.com wrote:
>> +static int print_vlan(DeviceState *dev, Property *prop, char *dest, size_t
>> len)
>> +{
>> + NetClientState **ptr = qdev_get_prop_ptr(dev, prop);
>> +
>> + if (*ptr) {
>> + unsigned int id;
>> + if (!net_hub_id_for_client(*ptr, &id)) {
>> + return snprintf(dest, len, "%d", id);
>
> Unsigned int should be %u. Source code scanners or the compiler could
> warn about this so it's worth changing.
>
>> + }
>> + }
>> +
>> + return snprintf(dest, len, "");
>> +}
>> +
>> +static void get_vlan(Object *obj, Visitor *v, void *opaque,
>> + const char *name, Error **errp)
>> +{
>> + DeviceState *dev = DEVICE(obj);
>> + Property *prop = opaque;
>> + NetClientState **ptr = qdev_get_prop_ptr(dev, prop);
>> + int64_t id = -1;
>> +
>> + if (*ptr) {
>> + unsigned int hub_id;
>> + net_hub_id_for_client(*ptr, &hub_id);
>
> It's unclear what happens if net_hub_id_for_client() fails but it looks
> like hub_id may be uninitialized.
>
> Stefan
>
--
Regards,
Zhi Yong Wu
[Qemu-devel] [PATCH v2] net: roll back qdev_prop_vlan
From: Zhi Yong Wu
We're trying to preserve backward compatibility. This
command-line break:
x86_64-softmmu/qemu-system-x86_64 -net user,vlan=1 -device virtio-net-pci,vlan=1
Instead of dropping the qdev_prop_vlan completely the
hw/qdev-properties.c code needs to call net/hub.h external functions
to implement equivalent functionality.
The change from v1:
1.) %d -> %u [stefanha]
2.) the error handling when net_hub_id_for_client fails [stefanha]
Signed-off-by: Zhi Yong Wu
---
hw/qdev-properties.c | 77 ++
hw/qdev.h|3 ++
net.h|1 +
net/hub.c| 25
net/hub.h|1 +
5 files changed, 107 insertions(+), 0 deletions(-)
diff --git a/hw/qdev-properties.c b/hw/qdev-properties.c
index 1c13bda..e553386 100644
--- a/hw/qdev-properties.c
+++ b/hw/qdev-properties.c
@@ -2,6 +2,7 @@
#include "qdev.h"
#include "qerror.h"
#include "blockdev.h"
+#include "net/hub.h"
void *qdev_get_prop_ptr(DeviceState *dev, Property *prop)
{
@@ -623,6 +624,82 @@ PropertyInfo qdev_prop_netdev = {
.set = set_netdev,
};
+/* --- vlan --- */
+
+static int print_vlan(DeviceState *dev, Property *prop, char *dest, size_t len)
+{
+NetClientState **ptr = qdev_get_prop_ptr(dev, prop);
+
+if (*ptr) {
+unsigned int id;
+if (!net_hub_id_for_client(*ptr, &id)) {
+return snprintf(dest, len, "%u", id);
+}
+}
+
+return snprintf(dest, len, "");
+}
+
+static void get_vlan(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+DeviceState *dev = DEVICE(obj);
+Property *prop = opaque;
+NetClientState **ptr = qdev_get_prop_ptr(dev, prop);
+int64_t id = -1;
+
+if (*ptr) {
+unsigned int hub_id;
+if(!net_hub_id_for_client(*ptr, &hub_id)) {
+ id = (int64_t)hub_id;
+}
+}
+
+visit_type_int(v, &id, name, errp);
+}
+
+static void set_vlan(Object *obj, Visitor *v, void *opaque,
+ const char *name, Error **errp)
+{
+DeviceState *dev = DEVICE(obj);
+Property *prop = opaque;
+NetClientState **ptr = qdev_get_prop_ptr(dev, prop);
+Error *local_err = NULL;
+int64_t id;
+NetClientState *hubport;
+
+if (dev->state != DEV_STATE_CREATED) {
+error_set(errp, QERR_PERMISSION_DENIED);
+return;
+}
+
+visit_type_int(v, &id, name, &local_err);
+if (local_err) {
+error_propagate(errp, local_err);
+return;
+}
+
+if (id == -1) {
+*ptr = NULL;
+return;
+}
+
+hubport = net_hub_port_find(id);
+if (!hubport) {
+error_set(errp, QERR_INVALID_PARAMETER_VALUE,
+ name, prop->info->name);
+return;
+}
+*ptr = hubport;
+}
+
+PropertyInfo qdev_prop_vlan = {
+.name = "vlan",
+.print = print_vlan,
+.get = get_vlan,
+.set = set_vlan,
+};
+
/* --- pointer --- */
/* Not a proper property, just for dirty hacks. TODO Remove it! */
diff --git a/hw/qdev.h b/hw/qdev.h
index edbf8fa..f4aea27 100644
--- a/hw/qdev.h
+++ b/hw/qdev.h
@@ -222,6 +222,7 @@ extern PropertyInfo qdev_prop_macaddr;
extern PropertyInfo qdev_prop_losttickpolicy;
extern PropertyInfo qdev_prop_drive;
extern PropertyInfo qdev_prop_netdev;
+extern PropertyInfo qdev_prop_vlan;
extern PropertyInfo qdev_prop_pci_devfn;
extern PropertyInfo qdev_prop_blocksize;
@@ -276,6 +277,8 @@ extern PropertyInfo qdev_prop_blocksize;
DEFINE_PROP(_n, _s, _f, qdev_prop_string, char*)
#define DEFINE_PROP_NETDEV(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_netdev, NetClientState*)
+#define DEFINE_PROP_VLAN(_n, _s, _f) \
+DEFINE_PROP(_n, _s, _f, qdev_prop_vlan, NetClientState*)
#define DEFINE_PROP_DRIVE(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_drive, BlockDriverState *)
#define DEFINE_PROP_MACADDR(_n, _s, _f) \
diff --git a/net.h b/net.h
index 08306a4..c4e56cc 100644
--- a/net.h
+++ b/net.h
@@ -22,6 +22,7 @@ typedef struct NICConf {
#define DEFINE_NIC_PROPERTIES(_state, _conf)\
DEFINE_PROP_MACADDR("mac", _state, _conf.macaddr),\
+DEFINE_PROP_VLAN("vlan", _state, _conf.peer), \
DEFINE_PROP_NETDEV("netdev", _state, _conf.peer), \
DEFINE_PROP_INT32("bootindex", _state, _conf.bootindex, -1)
diff --git a/net/hub.c b/net/hub.c
index efd90b5..001f818 100644
--- a/net/hub.c
+++ b/net/hub.c
@@ -205,6 +205,31 @@ NetClientState *net_hub_find_client_by_name(unsigned int
hub_id,
}
/**
+ * Find a available port on a hub; otherwise create one new port
+ */
+NetClientState *net_hub_port_find(unsigned int hub_id)
+{
+NetHub *hub;
+NetHubPort *port;
+NetClientState *nc;
+
+QLIST_FOREACH(hub, &hubs, next) {
+if (hub->id == hub_id) {
+QLIST_FOREACH(port, &hub->ports, next)
[Qemu-devel] [PATCH] qcow2: preserve free_byte_offset when qcow2_alloc_bytes() fails
When qcow2_alloc_clusters() error handling code was introduced in commit
5d757b563d59142ca81e1073a8e8396750a0ad1a, the value of free_byte_offset
was clobbered in the error case. This patch keeps free_byte_offset at 0
so we will try to allocate clusters again next time this function is
called.
Signed-off-by: Stefan Hajnoczi
---
block/qcow2-refcount.c |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/block/qcow2-refcount.c b/block/qcow2-refcount.c
index 812c93c..2d5420c 100644
--- a/block/qcow2-refcount.c
+++ b/block/qcow2-refcount.c
@@ -627,10 +627,11 @@ int64_t qcow2_alloc_bytes(BlockDriverState *bs, int size)
BLKDBG_EVENT(bs->file, BLKDBG_CLUSTER_ALLOC_BYTES);
assert(size > 0 && size <= s->cluster_size);
if (s->free_byte_offset == 0) {
-s->free_byte_offset = qcow2_alloc_clusters(bs, s->cluster_size);
-if (s->free_byte_offset < 0) {
-return s->free_byte_offset;
+offset = qcow2_alloc_clusters(bs, s->cluster_size);
+if (offset < 0) {
+return offset;
}
+s->free_byte_offset = offset;
}
redo:
free_in_cluster = s->cluster_size -
--
1.7.10
Re: [Qemu-devel] [PATCH v2] net: roll back qdev_prop_vlan
On Mon, Jun 18, 2012 at 1:57 PM, wrote: > From: Zhi Yong Wu > > We're trying to preserve backward compatibility. This > command-line break: > > x86_64-softmmu/qemu-system-x86_64 -net user,vlan=1 -device > virtio-net-pci,vlan=1 > > Instead of dropping the qdev_prop_vlan completely the > hw/qdev-properties.c code needs to call net/hub.h external functions > to implement equivalent functionality. > > The change from v1: > 1.) %d -> %u [stefanha] > 2.) the error handling when net_hub_id_for_client fails [stefanha] > > Signed-off-by: Zhi Yong Wu > --- > hw/qdev-properties.c | 77 > ++ > hw/qdev.h | 3 ++ > net.h | 1 + > net/hub.c | 25 > net/hub.h | 1 + > 5 files changed, 107 insertions(+), 0 deletions(-) Reviewed-by: Stefan Hajnoczi
Re: [Qemu-devel] [PATCH] make: automatically include dependencies in recursive subdir rules (v2)
On 2012-06-18 14:47, Anthony Liguori wrote: > On 06/18/2012 04:13 AM, Jan Kiszka wrote: >> On 2012-06-18 02:32, Andreas Färber wrote: >>> Am 18.06.2012 02:01, schrieb Anthony Liguori: >>> This will work technically but I still feel this is wrong semantically. >>> The pre-Paolo and current way is picking specific files from the hw/kvm/ >>> directory. Your change above implies that in hw/kvm/ only x86 files can >>> live, which I dislike. As suggested before, I would prefer if x86-only >>> files were moved to an x86-specific location - the place for that >>> existing since Paolo's refactoring would be hw/i386/. CC'ing Jan. That >>> would match Paolo's reply in the unicore32 thread on future file >>> placement. Alternatives would be hw/i386/kvm/ or hw/kvm/i386/; we're >>> talking about a handful of files only though, so I don't think they >>> require a new subdirectory. >> >> Some per-arch separation is required, at least in the build process. >> We'll see power and arm stubs for in-kernel devices soon. > > i8259.o i8254.o ioapic.o don't need to be arch specific In theory. In practice they carry quite a bit of the PC architecture (i8254: HPET and PC speaker port, i8259: ELCR). Maybe not the IOAPIC. It was once reused on IA64, but that arch is dead. > > apic.o ought to be renamed to lapic.o and moved to target-i386/kvm/ "apic" is fine as name as the code covers both cases. Should be move hw/apic* as well? > > I think clock.o also more than likely belongs in target-i386/kvm/. It would > have to be implemented as part of the CPU core if it ever existed IRL. > > In general, if is logically part of a CPU core, it ought to be in > target-$(ARCH). Otherwise, it shouldn't be built as a target specific object. There are some practical things like lacking types or defines in the KVM API that most probably prevent building certain KVM devices for all targets unconditionally. Jan -- Siemens AG, Corporate Technology, CT T DE IT 1 Corporate Competence Center Embedded Linux
Re: [Qemu-devel] [PATCH] qcow2: fix #ifdef'd qcow2_check_refcounts() callers
Am 15.06.2012 17:41, schrieb Stefan Hajnoczi: > The DEBUG_ALLOC qcow2.h macro enables additional consistency checks > throughout the code. This makes it easier to spot corruptions that are > introduced during development. Since consistency check is an expensive > operation the DEBUG_ALLOC macro is used to compile checks out in normal > builds and qcow2_check_refcounts() calls missed the addition of a new > function argument. > > Signed-off-by: Stefan Hajnoczi Thanks, applied to the block branch. Kevin
Re: [Qemu-devel] [PATCH] qcow2: preserve free_byte_offset when qcow2_alloc_bytes() fails
Am 18.06.2012 15:00, schrieb Stefan Hajnoczi: > When qcow2_alloc_clusters() error handling code was introduced in commit > 5d757b563d59142ca81e1073a8e8396750a0ad1a, the value of free_byte_offset > was clobbered in the error case. This patch keeps free_byte_offset at 0 > so we will try to allocate clusters again next time this function is > called. > > Signed-off-by: Stefan Hajnoczi Thanks, applied to the block branch. And I guess we should get test case 026 fixed up and extended to cover this. Kevin
Re: [Qemu-devel] [PATCH] qcow2: preserve free_byte_offset when qcow2_alloc_bytes() fails
On Mon, Jun 18, 2012 at 2:11 PM, Kevin Wolf wrote: > Am 18.06.2012 15:00, schrieb Stefan Hajnoczi: >> When qcow2_alloc_clusters() error handling code was introduced in commit >> 5d757b563d59142ca81e1073a8e8396750a0ad1a, the value of free_byte_offset >> was clobbered in the error case. This patch keeps free_byte_offset at 0 >> so we will try to allocate clusters again next time this function is >> called. >> >> Signed-off-by: Stefan Hajnoczi > > Thanks, applied to the block branch. > > And I guess we should get test case 026 fixed up and extended to cover this. I'm not sure what to test. It already returned the error code correctly. The problem was what happened when called again - there would be junk in free_byte_offset. Stefan
Re: [Qemu-devel] [PATCH 3/3] qom: add unit test for Interfaces
On 06/16/2012 05:31 AM, Peter Crosthwaite wrote:
On Thu, Jun 14, 2012 at 6:55 AM, Anthony Liguori wrote:
Signed-off-by: Anthony Liguori
Reviewed-by: Peter A.G. Crosthwaite
---
tests/Makefile |5 +-
tests/test-object.c | 222 +++
2 files changed, 226 insertions(+), 1 deletions(-)
create mode 100644 tests/test-object.c
diff --git a/tests/Makefile b/tests/Makefile
index d66ab19..d1f979d 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -14,6 +14,7 @@ check-unit-y += tests/test-string-input-visitor$(EXESUF)
check-unit-y += tests/test-string-output-visitor$(EXESUF)
check-unit-y += tests/test-coroutine$(EXESUF)
check-unit-y += tests/test-visitor-serialization$(EXESUF)
+check-unit-y += tests/test-object$(EXESUF)
check-block-$(CONFIG_POSIX) += tests/qemu-iotests-quick.sh
@@ -32,7 +33,8 @@ test-obj-y = tests/check-qint.o tests/check-qstring.o
tests/check-qdict.o \
tests/test-coroutine.o tests/test-string-output-visitor.o \
tests/test-string-input-visitor.o tests/test-qmp-output-visitor.o \
tests/test-qmp-input-visitor.o tests/test-qmp-input-strict.o \
- tests/test-qmp-commands.o tests/test-visitor-serialization.o
+ tests/test-qmp-commands.o tests/test-visitor-serialization.o \
+ tests/test-object.o
test-qapi-obj-y = $(qobject-obj-y) $(qapi-obj-y) $(tools-obj-y)
test-qapi-obj-y += tests/test-qapi-visit.o tests/test-qapi-types.o
@@ -66,6 +68,7 @@ tests/test-qmp-input-visitor$(EXESUF):
tests/test-qmp-input-visitor.o $(test-qap
tests/test-qmp-input-strict$(EXESUF): tests/test-qmp-input-strict.o
$(test-qapi-obj-y)
tests/test-qmp-commands$(EXESUF): tests/test-qmp-commands.o
tests/test-qmp-marshal.o $(test-qapi-obj-y)
tests/test-visitor-serialization$(EXESUF): tests/test-visitor-serialization.o
$(test-qapi-obj-y)
+tests/test-object$(EXESUF): tests/test-object.o $(qom-obj-y) $(test-qapi-obj-y)
tests/rtc-test$(EXESUF): tests/rtc-test.o $(trace-obj-y)
tests/m48t59-test$(EXESUF): tests/m48t59-test.o $(trace-obj-y)
diff --git a/tests/test-object.c b/tests/test-object.c
new file mode 100644
index 000..9f41da0
--- /dev/null
+++ b/tests/test-object.c
@@ -0,0 +1,222 @@
+/*
+ * QEMU Object Model unit test
+ *
+ * Copyright IBM, Corp. 2012
+ *
+ * Authors:
+ * Anthony Liguori
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+#include "qemu/object.h"
+#include "module.h"
+
+#define TYPE_HERBIVORE "herbivore"
+
+#define HERBIVORE_CLASS(klass) \
+OBJECT_CLASS_CHECK(HerbivoreClass, (klass), TYPE_HERBIVORE)
+#define HERBIVORE_GET_CLASS(obj) \
+OBJECT_GET_CLASS(HerbivoreClass, (obj), TYPE_HERBIVORE)
+#define HERBIVORE(obj) \
+INTERFACE_CHECK(Herbivore, (obj), TYPE_HERBIVORE)
+
+typedef struct Herbivore
+{
+Object obj;
+} Herbivore;
All this is doing is saying Herbivores are Objects right? A user cant
add anything to this struct given that interfaces are stateless so
could this be simplified to
typedef Object Herbivore;
This is admittedly a little wierd...
Interfaces don't exist as Objects in QOM. They are just classes. But it's very
handy to be able to have a Herbivore type that you can cast objects to.
I probably need to respin this though. INTERFACE_CHECK() asserts that an object
implements the interface class and then just returns the obj and casts it to the
dummy Interface object type.
A better approach would be to just teach object_dynamic_cast to do this for
anythign that's an interface type. That would fix the link problem you pointed
out too. I'll spin a v2.
Regards,
Anthony Liguori
?
+
+typedef struct HerbivoreClass
+{
+InterfaceClass parent;
+
+void (*feed_greens)(Herbivore *obj);
+} HerbivoreClass;
+
+static void herbivore_feed_greens(Herbivore *herbie)
+{
+HerbivoreClass *k = HERBIVORE_GET_CLASS(herbie);
+
+k->feed_greens(herbie);
+}
+
+static TypeInfo herbivore_info = {
+.name = TYPE_HERBIVORE,
+.parent = TYPE_INTERFACE,
+.class_size = sizeof(HerbivoreClass),
+};
+
+#define TYPE_CARNIVORE "carnivore"
+#define CARNIVORE_CLASS(klass) \
+OBJECT_CLASS_CHECK(CarnivoreClass, (klass), TYPE_CARNIVORE)
+#define CARNIVORE_GET_CLASS(obj) \
+OBJECT_GET_CLASS(CarnivoreClass, (obj), TYPE_CARNIVORE)
+#define CARNIVORE(obj) \
+INTERFACE_CHECK(Carnivore, (obj), TYPE_CARNIVORE)
+
+typedef struct Carnivore
+{
+Object parent;
+} Carnivore;
+
+typedef struct CarnivoreClass
+{
+InterfaceClass parent;
+
+void (*feed_bugs)(Carnivore *obj);
+} CarnivoreClass;
+
+static void carnivore_feed_bugs(Carnivore *carnie)
+{
+CarnivoreClass *k = CARNIVORE_GET_CLASS(carnie);
+
+k->feed_bugs(carnie);
+}
+
+static TypeInfo carnivore_info = {
+.name = TYPE_CARNIVORE,
+.parent = TYPE_INTERFACE,
+.class_size = sizeof(CarnivoreClass),
+};
+
+#define TYPE_REPTILE "reptile"
+#define REPTILE(obj) OBJECT_CHECK(Re
Re: [Qemu-devel] [PATCH] qcow2: preserve free_byte_offset when qcow2_alloc_bytes() fails
Am 18.06.2012 15:16, schrieb Stefan Hajnoczi: > On Mon, Jun 18, 2012 at 2:11 PM, Kevin Wolf wrote: >> Am 18.06.2012 15:00, schrieb Stefan Hajnoczi: >>> When qcow2_alloc_clusters() error handling code was introduced in commit >>> 5d757b563d59142ca81e1073a8e8396750a0ad1a, the value of free_byte_offset >>> was clobbered in the error case. This patch keeps free_byte_offset at 0 >>> so we will try to allocate clusters again next time this function is >>> called. >>> >>> Signed-off-by: Stefan Hajnoczi >> >> Thanks, applied to the block branch. >> >> And I guess we should get test case 026 fixed up and extended to cover this. > > I'm not sure what to test. It already returned the error code > correctly. The problem was what happened when called again - there > would be junk in free_byte_offset. Then this is what needs to be tested. For example: 1. Configure blkdebug to fail on BLKDBG_CLUSTER_ALLOC_BYTES once 2. write_compressed() fails with the configured errno, s->cluster_size is corrupted in the old version. 3. write_compressed() is expected to succeed. The buggy version may succeed as well, or fail somewhere else because of the negative (or wrapped around, huge) offset. There are different ways to check if we wrote to the right offset, probably the best way is to combine them: 4a. The obvious one: Read the data back. May or may not reveal a bug, depending on what the read code does with negative offsets. 4b. qemu-img info. The image file size is an indicator for this bug. 4c. Repeat the same procedure with a different cluster and a different pattern. Read back both. If the second one has overwritten the first one, there is a problem. Kevin
Re: [Qemu-devel] [PATCH 0/8] s390: SCLP console and misc
On 18.06.2012, at 14:35, Christian Borntraeger wrote: > Alex, > > are you going to pull the non-controversial patches? > We would then send a reworked sclp patch set later on (when > ready) - and everything that you also want us to rework. Yes, sorry. My patch queue currently has the following patches. Please let me know if I did forget any uncontroversial ones :). Alexander Graf (2): s390x: fix s390 virtio aliases kvm: Update kernel headers Christian Borntraeger (1): s390: stop target cpu on sigp initial reset Jens Freimann (1): s390: make kvm_stat work on s390 Alex
[Qemu-devel] [PULL 0/4] s390 patch queue 2012-06-18
Hi Blue / Aurelien, This is my current patch queue for s390. Please pull. Alex The following changes since commit eb2aeacf983a2a88a2b31e8fee067c38bd10abd3: malc (1): audio/winwave: Fix typo are available in the git repository at: git://repo.or.cz/qemu/agraf.git s390-for-upstream Alexander Graf (2): s390x: fix s390 virtio aliases kvm: Update kernel headers Christian Borntraeger (1): s390: stop target cpu on sigp initial reset Jens Freimann (1): s390: make kvm_stat work on s390 hw/qdev-monitor.c| 27 --- linux-headers/asm-s390/kvm.h |5 + linux-headers/linux/kvm.h|1 + scripts/kvm/kvm_stat | 26 +- target-s390x/kvm.c |1 + 5 files changed, 52 insertions(+), 8 deletions(-)
[Qemu-devel] [PATCH 4/4] s390: stop target cpu on sigp initial reset
From: Christian Borntraeger
We must not run the target cpu after an initial reset. This makes
system_reset more reliable for smp guests.
Signed-off-by: Christian Borntraeger
Signed-off-by: Alexander Graf
---
target-s390x/kvm.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/target-s390x/kvm.c b/target-s390x/kvm.c
index 5800fd6..ec08dd0 100644
--- a/target-s390x/kvm.c
+++ b/target-s390x/kvm.c
@@ -314,6 +314,7 @@ static int s390_cpu_initial_reset(CPUS390XState *env)
{
int i;
+s390_del_running_cpu(env);
if (kvm_vcpu_ioctl(env, KVM_S390_INITIAL_RESET, NULL) < 0) {
perror("cannot init reset vcpu");
}
--
1.6.0.2
Re: [Qemu-devel] [PATCH 0/8] s390: SCLP console and misc
On 18/06/12 15:33, Alexander Graf wrote: > > On 18.06.2012, at 14:35, Christian Borntraeger wrote: > >> Alex, >> >> are you going to pull the non-controversial patches? >> We would then send a reworked sclp patch set later on (when >> ready) - and everything that you also want us to rework. > > Yes, sorry. My patch queue currently has the following patches. Please let me > know if I did forget any uncontroversial ones :). What about - the last version of the autodetect map private that was reviewed by Jan? - s390: Fix the storage increment size calculation? > > > Alexander Graf (2): > s390x: fix s390 virtio aliases > kvm: Update kernel headers > > Christian Borntraeger (1): > s390: stop target cpu on sigp initial reset > > Jens Freimann (1): > s390: make kvm_stat work on s390 > > > Alex
Re: [Qemu-devel] [PATCH v3] s390: autodetect map private
On 15.06.2012, at 17:10, Christian Borntraeger wrote: > By default qemu will use MAP_PRIVATE for guest pages. This will write > protect pages and thus break on s390 systems that dont support this feature. > Therefore qemu has a hack to always use MAP_SHARED for s390. But MAP_SHARED > has other problems (no dirty pages tracking, a lot more swap overhead etc.) > Newer systems allow the distinction via KVM_CAP_S390_COW. With this feature > qemu can use the standard qemu alloc if available, otherwise it will use > the old s390 hack. Thanks, applied to s390-next. Alex
Re: [Qemu-devel] [PATCH 3/3] qom: add unit test for Interfaces
>>> +#define HERBIVORE(obj) \
>>> + INTERFACE_CHECK(Herbivore, (obj), TYPE_HERBIVORE)
>>> +
>>> +typedef struct Herbivore
>>> +{
>>> + Object obj;
>>> +} Herbivore;
>>
>>
>> All this is doing is saying Herbivores are Objects right? A user cant
>> add anything to this struct given that interfaces are stateless so
>> could this be simplified to
>>
>> typedef Object Herbivore;
>
>
> This is admittedly a little wierd...
>
> Interfaces don't exist as Objects in QOM.
Not in the sense that they used too, but all objects that implement an
interface are still OBJECTs just through the inheritance path of their
concrete class, which is the point of this struct yes?
They are just classes. But it's
> very handy to be able to have a Herbivore type that you can cast objects to.
>
Yes I agree in full, but the typedef definition is functionally
equivalent to what you have there, and removes the temptation to add
fields to the object type. Having a skeletal struct there gives the
illusion to readers that interface objects are in someway extensible.
> I probably need to respin this though. INTERFACE_CHECK() asserts that an
> object implements the interface class and then just returns the obj and
> casts it to the dummy Interface object type.
>
> A better approach would be to just teach object_dynamic_cast to do this for
> anythign that's an interface type. That would fix the link problem you
> pointed out too. I'll spin a v2.
Please see my patch, I have a little 3 patch series up on the list.
that starts with your v1, does the axi-stream stuff then fixes that
bug.
Regards,
Peter
>
> Regards,
>
> Anthony Liguori
>
>>
>> ?
>>
>>> +
>>> +typedef struct HerbivoreClass
>>> +{
>>> + InterfaceClass parent;
>>> +
>>> + void (*feed_greens)(Herbivore *obj);
Re: [Qemu-devel] [PATCH 8/8] s390: Fix the storage increment size calculation
On 12.06.2012, at 16:57, Jeng-fang Wang wrote: > Yes, you can refer to AR10040-03-POK, Service-Call Logical Processor > Architecture for S/390 and z/Architecture, Figure 2-6 Minimum storage > increment and subincrement size. :) > Is that one publicly available anywhere? Alex
Re: [Qemu-devel] q35 chipset support
Anthony Liguori writes: > On 06/15/2012 02:04 AM, Markus Armbruster wrote: >> Anthony Liguori writes: >> >>> On 06/14/2012 02:54 PM, Jason Baron wrote: Hi, I recently updated Isaku Yamahata's q35 patches to work on the latest qemu and seabios trees. On the qemu side, most of the changes revolved around updating to use QOM and updates to the memory API. I was also able to drop quite a few patches that had already been resolved by the current qemu tree. The trees seem pretty stable and can be found here: git://github.com/jibaron/q35-qemu.git git://github.com/jibaron/q35-seabios.git >>> >>> I'm got the beginnings of a feature page started: >>> >>> http://wiki.qemu.org/Features/Q35 >>> >>> The approach above will not work in a QOM world unfortunately. We >>> need to do quite a bit of ground work before adding another chipset. >>> The biggest task is converting devices to not require an ISA bus since >>> ICH9 simply doesn't have an ISA bus. >> >> Could you explain briefly why use of a software ISA bus construct >> matters for device models and/or guests? > > No, but I can provide a long explanation :-) Thanks! > The I440FX has a very basic device topology. The PCI host is the > memory controller and there's a PCI device that happens to have the > SuperI/O chip + a PCI-ISA bridge. There's no IOMMU and interrupt > routing is simple. PC interrupt routing is hardly ever "simple", but I get what you mean ;) > The Q35 is much more sophisticated. The PCI-e complex itself can > present interesting topologies and the legacy PCI bus sits within the > PCI-e complex. You can still have a PCI-ISA bridge but the SuperI/O > chip is not part of it. Rather that's off of a separate bus (the LPC) > which does not logically reside within the PCI-e complex. Let's whether I understand. The platform devices do *not* sit behind a PCI-ISA bridge (in fact, no such bridge exists normally). Instead, they're connected via LPC. What I don't get is why that connection can't be modelled as an ISA bus. Provided by a Systembus-ISA bridge if you like. > And because there is an IOMMU, this topology is visible to the guest. > > Granted, initial Q35 support won't come with an IOMMU, but we will > need to do this eventually. There's already non-x86 patches floating > around. Normally, I would say we should deal with this later when we > need an IOMMU but part of the reason this is so hard to fix for the PC > already is the first set of Q35 patches we merged ages ago that > introduced the silliness of pc_piix.c. The first step in cleaning > this all up is essentially reverting that first set of patches. > > So we need to fix our topological representation of platform devices > before we start adding more complex chipsets. Otherwise, we're going > to end up in a bad situation in the near future. I'm not sufficiently familiar with the first set of Q35 patches to risk an opinion here...
Re: [Qemu-devel] [PATCH 0/8] s390: SCLP console and misc
On 18.06.2012, at 15:41, Christian Borntraeger wrote: > On 18/06/12 15:33, Alexander Graf wrote: >> >> On 18.06.2012, at 14:35, Christian Borntraeger wrote: >> >>> Alex, >>> >>> are you going to pull the non-controversial patches? >>> We would then send a reworked sclp patch set later on (when >>> ready) - and everything that you also want us to rework. >> >> Yes, sorry. My patch queue currently has the following patches. Please let >> me know if I did forget any uncontroversial ones :). > > What about > - the last version of the autodetect map private that was reviewed by Jan? Yup, applied that one. > - s390: Fix the storage increment size calculation? That's not uncontroversial yet. I still need to see some documentation - or blindly trust you guys :(. Alex
Re: [Qemu-devel] [PATCH 3/3] qom: add unit test for Interfaces
Am 18.06.2012 15:46, schrieb Peter Crosthwaite:
+#define HERBIVORE(obj) \
+INTERFACE_CHECK(Herbivore, (obj), TYPE_HERBIVORE)
+
+typedef struct Herbivore
+{
+Object obj;
+} Herbivore;
>>>
>>>
>>> All this is doing is saying Herbivores are Objects right? A user cant
>>> add anything to this struct given that interfaces are stateless so
>>> could this be simplified to
>>>
>>> typedef Object Herbivore;
>>
>>
>> This is admittedly a little wierd...
>>
>> Interfaces don't exist as Objects in QOM.
>
> Not in the sense that they used too, but all objects that implement an
> interface are still OBJECTs just through the inheritance path of their
> concrete class, which is the point of this struct yes?
>
> They are just classes. But it's
>> very handy to be able to have a Herbivore type that you can cast objects to.
>>
>
> Yes I agree in full, but the typedef definition is functionally
> equivalent to what you have there, and removes the temptation to add
> fields to the object type. Having a skeletal struct there gives the
> illusion to readers that interface objects are in someway extensible.
Why have a typedef at all then? You can just use Object directly. If
that ever changes it leads to all kinds of problems (well, necessary
adjustments), as seen in the pci_host series.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] q35 chipset support
Anthony Liguori writes: > On 06/15/2012 12:57 PM, Jason Baron wrote: >> On Thu, Jun 14, 2012 at 03:16:03PM -0500, Anthony Liguori wrote: >>> On 06/14/2012 02:54 PM, Jason Baron wrote: Hi, I recently updated Isaku Yamahata's q35 patches to work on the latest qemu and seabios trees. On the qemu side, most of the changes revolved around updating to use QOM and updates to the memory API. I was also able to drop quite a few patches that had already been resolved by the current qemu tree. The trees seem pretty stable and can be found here: git://github.com/jibaron/q35-qemu.git git://github.com/jibaron/q35-seabios.git >>> >>> I'm got the beginnings of a feature page started: >>> >>> http://wiki.qemu.org/Features/Q35 >>> >>> The approach above will not work in a QOM world unfortunately. We >>> need to do quite a bit of ground work before adding another chipset. >>> The biggest task is converting devices to not require an ISA bus >>> since ICH9 simply doesn't have an ISA bus. >>> >> >> Right, there is no h/w isa bus, but the LPC interface chip is modeled as an >> isa >> bridge. So having an isa bus hanging off of it doesn't seem unreasonable. >> Unless >> there is some more fundamental reason not do it this way? >> >> It hows up in lspci as: >> >> 00:1f.0 ISA bridge: Intel Corporation 82801IB (ICH9) LPC Interface >> Controller (rev 02) > > It's not a question of ISA vs. LPC, it's which devices are actually on > that bus. See my respond to Markus's note. Maybe I'm naive, but platform devices handing off an ISA bus provided by that ICH9 ISA bridge looks like a fair approximation to me. Yes, the actual wiring is LPC, but that's a hardware detail invisible to device models and guest, isn't it? Of course, you can't connect anything but the platform devices to that bus. To connect other ISA devices, you'd have to add a second ISA bridge. I suspect that's what you meant by "You can still have a PCI-ISA bridge but the SuperI/O chip is not part of it" elsewhere in this thread. No idea whether such beasts exist in the physical world, and how they work.
Re: [Qemu-devel] [RFC] [PATCHv2 2/2] Adding basic calls to libseccomp in vl.c
On Monday, June 18, 2012 09:31:03 AM Daniel P. Berrange wrote: > On Fri, Jun 15, 2012 at 05:02:19PM -0400, Paul Moore wrote: > > On Friday, June 15, 2012 07:06:10 PM Blue Swirl wrote: > > > I think allowing execve() would render seccomp pretty much useless. > > > > Not necessarily. > > > > I'll agree that it does seem a bit odd to allow execve(), but there is > > still value in enabling seccomp to disable potentially buggy/exploitable > > syscalls. Let's not forget that we have over 300 syscalls on x86_64, not > > including the 32 bit versions, and even if we add all of the new syscalls > > suggested in this thread we are still talking about a small subset of > > syscalls. As far as security goes, the old adage of "less is more" > > applies. > > I can sort of see this argument, but *only* if the QEMU process is being > run under a dedicated, fully unprivileged (from a DAC pov) user, completely > separate from anything else on the system. > > Or, of course, for a QEMU already confined by SELinux. Agreed ... and considering at least one major distribution takes this approach it seems like reasonable functionality to me. Confining QEMU, either through DAC and/or MAC, when faced with potentially malicious guests is just good sense. -- paul moore security and virtualization @ redhat
[Qemu-devel] [PATCH 2/4] kvm: Update kernel headers
Corresponding kvm.git hash: 4e3c8a1b1c
Signed-off-by: Alexander Graf
---
linux-headers/asm-s390/kvm.h |5 +
linux-headers/linux/kvm.h|1 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/linux-headers/asm-s390/kvm.h b/linux-headers/asm-s390/kvm.h
index 9607667..bdcbe0f 100644
--- a/linux-headers/asm-s390/kvm.h
+++ b/linux-headers/asm-s390/kvm.h
@@ -52,4 +52,9 @@ struct kvm_sync_regs {
__u32 acrs[16]; /* access registers */
__u64 crs[16]; /* control registers */
};
+
+#define KVM_REG_S390_TODPR (KVM_REG_S390 | KVM_REG_SIZE_U32 | 0x1)
+#define KVM_REG_S390_EPOCHDIFF (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x2)
+#define KVM_REG_S390_CPU_TIMER (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x3)
+#define KVM_REG_S390_CLOCK_COMP (KVM_REG_S390 | KVM_REG_SIZE_U64 | 0x4)
#endif
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index c4426ec..5a9d4e3 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -616,6 +616,7 @@ struct kvm_ppc_smmu_info {
#define KVM_CAP_KVMCLOCK_CTRL 76
#define KVM_CAP_SIGNAL_MSI 77
#define KVM_CAP_PPC_GET_SMMU_INFO 78
+#define KVM_CAP_S390_COW 79
#ifdef KVM_CAP_IRQ_ROUTING
--
1.6.0.2
Re: [Qemu-devel] [RFC] [PATCHv2 2/2] Adding basic calls to libseccomp in vl.c
On Mon, Jun 18, 2012 at 09:52:44AM -0400, Paul Moore wrote: > On Monday, June 18, 2012 09:31:03 AM Daniel P. Berrange wrote: > > On Fri, Jun 15, 2012 at 05:02:19PM -0400, Paul Moore wrote: > > > On Friday, June 15, 2012 07:06:10 PM Blue Swirl wrote: > > > > I think allowing execve() would render seccomp pretty much useless. > > > > > > Not necessarily. > > > > > > I'll agree that it does seem a bit odd to allow execve(), but there is > > > still value in enabling seccomp to disable potentially buggy/exploitable > > > syscalls. Let's not forget that we have over 300 syscalls on x86_64, not > > > including the 32 bit versions, and even if we add all of the new syscalls > > > suggested in this thread we are still talking about a small subset of > > > syscalls. As far as security goes, the old adage of "less is more" > > > applies. > > > > I can sort of see this argument, but *only* if the QEMU process is being > > run under a dedicated, fully unprivileged (from a DAC pov) user, completely > > separate from anything else on the system. > > > > Or, of course, for a QEMU already confined by SELinux. > > Agreed ... and considering at least one major distribution takes this > approach > it seems like reasonable functionality to me. Confining QEMU, either through > DAC and/or MAC, when faced with potentially malicious guests is just good > sense. Good, I'm not missing anything then. I'd suggest that future iterations of these patches explicitly mention the deployment scenarios in which this technology is able to offer increases security, and also describe the scenarios where it will not improve things. Regards, Daniel -- |: http://berrange.com -o-http://www.flickr.com/photos/dberrange/ :| |: http://libvirt.org -o- http://virt-manager.org :| |: http://autobuild.org -o- http://search.cpan.org/~danberr/ :| |: http://entangle-photo.org -o- http://live.gnome.org/gtk-vnc :|
[Qemu-devel] [PATCH 13/22] qdev: Clean up global properties
From: Paolo Bonzini
Now that global properties do not depend on buses anymore, set
them directly in the device instance_init function.
Signed-off-by: Paolo Bonzini
Signed-off-by: Andreas Färber
---
hw/qdev-monitor.c |1 -
hw/qdev.c |2 +-
2 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/hw/qdev-monitor.c b/hw/qdev-monitor.c
index b608eb4..390d467 100644
--- a/hw/qdev-monitor.c
+++ b/hw/qdev-monitor.c
@@ -440,7 +440,6 @@ DeviceState *qdev_device_add(QemuOpts *opts)
/* create device, set properties */
qdev = DEVICE(object_new(driver));
qdev_set_parent_bus(qdev, bus);
-qdev_prop_set_globals(qdev);
id = qemu_opts_id(opts);
if (id) {
diff --git a/hw/qdev.c b/hw/qdev.c
index f239902..483f2e6 100644
--- a/hw/qdev.c
+++ b/hw/qdev.c
@@ -111,7 +111,6 @@ DeviceState *qdev_try_create(BusState *bus, const char
*type)
}
qdev_set_parent_bus(dev, bus);
-qdev_prop_set_globals(dev);
return dev;
}
@@ -618,6 +617,7 @@ static void device_initfn(Object *obj)
qdev_prop_set_defaults(dev, DEVICE_CLASS(class)->props);
class = object_class_get_parent(class);
} while (class != object_class_by_name(TYPE_DEVICE));
+qdev_prop_set_globals(dev);
}
/* Unlink device from bus and free the structure. */
--
1.7.7
[Qemu-devel] [PATCH 19/22] qbus: Make child devices links
From: Anthony Liguori
Make qbus children show up as link<> properties. There is no stable
addressing for qbus children so we use an unstable naming convention.
This is okay in QOM though because the composition name is expected to
be what's stable.
Signed-off-by: Anthony Liguori
Signed-off-by: Paolo Bonzini
Signed-off-by: Andreas Färber
---
hw/acpi_piix4.c | 10 ---
hw/i2c.c |5 ++-
hw/intel-hda.c | 15 +++
hw/lsi53c895a.c |5 ++-
hw/qdev-monitor.c| 26
hw/qdev.c| 64 +
hw/qdev.h| 10 ++-
hw/s390-virtio-bus.c | 25 +--
hw/scsi-bus.c| 13 ++
hw/spapr_pci.c |7 +++--
hw/spapr_vio.c | 25 ++-
hw/spapr_vty.c |6 +++-
hw/ssi.c | 14 ++
hw/virtio-scsi.c |6 ++--
qom/object.c | 11 +++-
15 files changed, 159 insertions(+), 83 deletions(-)
diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
index 0345490..a11c8e7 100644
--- a/hw/acpi_piix4.c
+++ b/hw/acpi_piix4.c
@@ -284,7 +284,7 @@ static const VMStateDescription vmstate_acpi = {
static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots)
{
-DeviceState *qdev, *next;
+BusChild *kid, *next;
BusState *bus = qdev_get_parent_bus(&s->dev.qdev);
int slot = ffs(slots) - 1;
bool slot_free = true;
@@ -292,7 +292,8 @@ static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned
slots)
/* Mark request as complete */
s->pci0_status.down &= ~(1U << slot);
-QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
+QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
+DeviceState *qdev = kid->child;
PCIDevice *dev = PCI_DEVICE(qdev);
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
if (PCI_SLOT(dev->devfn) == slot) {
@@ -313,7 +314,7 @@ static void piix4_update_hotplug(PIIX4PMState *s)
{
PCIDevice *dev = &s->dev;
BusState *bus = qdev_get_parent_bus(&dev->qdev);
-DeviceState *qdev, *next;
+BusChild *kid, *next;
/* Execute any pending removes during reset */
while (s->pci0_status.down) {
@@ -323,7 +324,8 @@ static void piix4_update_hotplug(PIIX4PMState *s)
s->pci0_hotplug_enable = ~0;
s->pci0_slot_device_present = 0;
-QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
+QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
+DeviceState *qdev = kid->child;
PCIDevice *pdev = PCI_DEVICE(qdev);
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev);
int slot = PCI_SLOT(pdev->devfn);
diff --git a/hw/i2c.c b/hw/i2c.c
index 319b249..296bece 100644
--- a/hw/i2c.c
+++ b/hw/i2c.c
@@ -86,11 +86,12 @@ int i2c_bus_busy(i2c_bus *bus)
/* TODO: Make this handle multiple masters. */
int i2c_start_transfer(i2c_bus *bus, uint8_t address, int recv)
{
-DeviceState *qdev;
+BusChild *kid;
I2CSlave *slave = NULL;
I2CSlaveClass *sc;
-QTAILQ_FOREACH(qdev, &bus->qbus.children, sibling) {
+QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
+DeviceState *qdev = kid->child;
I2CSlave *candidate = I2C_SLAVE_FROM_QDEV(qdev);
if (candidate->address == address) {
slave = candidate;
diff --git a/hw/intel-hda.c b/hw/intel-hda.c
index e343096..c11fd30 100644
--- a/hw/intel-hda.c
+++ b/hw/intel-hda.c
@@ -78,10 +78,11 @@ static int hda_codec_dev_exit(DeviceState *qdev)
HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
{
-DeviceState *qdev;
+BusChild *kid;
HDACodecDevice *cdev;
-QTAILQ_FOREACH(qdev, &bus->qbus.children, sibling) {
+QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
+DeviceState *qdev = kid->child;
cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
if (cdev->cad == cad) {
return cdev;
@@ -483,10 +484,11 @@ static void intel_hda_parse_bdl(IntelHDAState *d,
IntelHDAStream *st)
static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool
running, bool output)
{
-DeviceState *qdev;
+BusChild *kid;
HDACodecDevice *cdev;
-QTAILQ_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
+QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
+DeviceState *qdev = kid->child;
HDACodecDeviceClass *cdc;
cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
@@ -1105,15 +1107,16 @@ static const MemoryRegionOps intel_hda_mmio_ops = {
static void intel_hda_reset(DeviceState *dev)
{
+BusChild *kid;
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev);
-DeviceState *qdev;
HDACodecDevice *cdev;
intel_hda_regs_reset(d);
d->wall_base_ns = qemu_get_clock_ns(vm_clock);
/* reset codecs */
-QTAILQ_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
+QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
+
[Qemu-devel] [PATCH 3/4] s390: make kvm_stat work on s390
From: Jens Freimann
Add s390_exit_reasons so kvm_stat doesn't crash when called on s390.
Look for 'vendor_id' in /proc/cpuinfo as well, instead of just for
'flags', so we can determine if we run on S390.
Signed-off-by: Jens Freimann
Signed-off-by: Alexander Graf
---
scripts/kvm/kvm_stat | 26 +-
1 files changed, 25 insertions(+), 1 deletions(-)
diff --git a/scripts/kvm/kvm_stat b/scripts/kvm/kvm_stat
index 56d2bd7..e8d68f0 100755
--- a/scripts/kvm/kvm_stat
+++ b/scripts/kvm/kvm_stat
@@ -141,15 +141,39 @@ svm_exit_reasons = {
0x400: 'NPF',
}
+s390_exit_reasons = {
+ 0x000: 'UNKNOWN',
+ 0x001: 'EXCEPTION',
+ 0x002: 'IO',
+ 0x003: 'HYPERCALL',
+ 0x004: 'DEBUG',
+ 0x005: 'HLT',
+ 0x006: 'MMIO',
+ 0x007: 'IRQ_WINDOW_OPEN',
+ 0x008: 'SHUTDOWN',
+ 0x009: 'FAIL_ENTRY',
+ 0x010: 'INTR',
+ 0x011: 'SET_TPR',
+ 0x012: 'TPR_ACCESS',
+ 0x013: 'S390_SIEIC',
+ 0x014: 'S390_RESET',
+ 0x015: 'DCR',
+ 0x016: 'NMI',
+ 0x017: 'INTERNAL_ERROR',
+ 0x018: 'OSI',
+ 0x019: 'PAPR_HCALL',
+}
+
vendor_exit_reasons = {
'vmx': vmx_exit_reasons,
'svm': svm_exit_reasons,
+'IBM/S390': s390_exit_reasons,
}
exit_reasons = None
for line in file('/proc/cpuinfo').readlines():
-if line.startswith('flags'):
+if line.startswith('flags') or line.startswith('vendor_id'):
for flag in line.split():
if flag in vendor_exit_reasons:
exit_reasons = vendor_exit_reasons[flag]
--
1.6.0.2
[Qemu-devel] [PATCH 14/22] qdev: Remove qdev_prop_set_defaults
From: Paolo Bonzini
Instead, qdev_property_add_static can set the default.
Signed-off-by: Paolo Bonzini
Reviewed-by: Anthony Liguori
Signed-off-by: Andreas Färber
---
hw/qdev-properties.c | 22 --
hw/qdev.c| 26 +++---
hw/qdev.h|1 -
3 files changed, 23 insertions(+), 26 deletions(-)
diff --git a/hw/qdev-properties.c b/hw/qdev-properties.c
index 04e8326..f4b9a0e 100644
--- a/hw/qdev-properties.c
+++ b/hw/qdev-properties.c
@@ -1106,28 +1106,6 @@ void qdev_prop_set_ptr(DeviceState *dev, const char
*name, void *value)
*ptr = value;
}
-void qdev_prop_set_defaults(DeviceState *dev, Property *props)
-{
-Object *obj = OBJECT(dev);
-if (!props)
-return;
-for (; props->name; props++) {
-Error *errp = NULL;
-if (props->qtype == QTYPE_NONE) {
-continue;
-}
-if (props->qtype == QTYPE_QBOOL) {
-object_property_set_bool(obj, props->defval, props->name, &errp);
-} else if (props->info->enum_table) {
-object_property_set_str(obj,
props->info->enum_table[props->defval],
-props->name, &errp);
-} else if (props->qtype == QTYPE_QINT) {
-object_property_set_int(obj, props->defval, props->name, &errp);
-}
-assert_no_error(errp);
-}
-}
-
static QTAILQ_HEAD(, GlobalProperty) global_props =
QTAILQ_HEAD_INITIALIZER(global_props);
static void qdev_prop_register_global(GlobalProperty *prop)
diff --git a/hw/qdev.c b/hw/qdev.c
index 483f2e6..7f18590 100644
--- a/hw/qdev.c
+++ b/hw/qdev.c
@@ -579,6 +579,9 @@ void qdev_property_add_legacy(DeviceState *dev, Property
*prop,
void qdev_property_add_static(DeviceState *dev, Property *prop,
Error **errp)
{
+Error *local_err = NULL;
+Object *obj = OBJECT(dev);
+
/*
* TODO qdev_prop_ptr does not have getters or setters. It must
* go now that it can be replaced with links. The test should be
@@ -588,10 +591,28 @@ void qdev_property_add_static(DeviceState *dev, Property
*prop,
return;
}
-object_property_add(OBJECT(dev), prop->name, prop->info->name,
+object_property_add(obj, prop->name, prop->info->name,
prop->info->get, prop->info->set,
prop->info->release,
-prop, errp);
+prop, &local_err);
+
+if (local_err) {
+error_propagate(errp, local_err);
+return;
+}
+if (prop->qtype == QTYPE_NONE) {
+return;
+}
+
+if (prop->qtype == QTYPE_QBOOL) {
+object_property_set_bool(obj, prop->defval, prop->name, &local_err);
+} else if (prop->info->enum_table) {
+object_property_set_str(obj, prop->info->enum_table[prop->defval],
+prop->name, &local_err);
+} else if (prop->qtype == QTYPE_QINT) {
+object_property_set_int(obj, prop->defval, prop->name, &local_err);
+}
+assert_no_error(local_err);
}
static void device_initfn(Object *obj)
@@ -614,7 +635,6 @@ static void device_initfn(Object *obj)
qdev_property_add_legacy(dev, prop, NULL);
qdev_property_add_static(dev, prop, NULL);
}
-qdev_prop_set_defaults(dev, DEVICE_CLASS(class)->props);
class = object_class_get_parent(class);
} while (class != object_class_by_name(TYPE_DEVICE));
qdev_prop_set_globals(dev);
diff --git a/hw/qdev.h b/hw/qdev.h
index 5f62f80..1af5382 100644
--- a/hw/qdev.h
+++ b/hw/qdev.h
@@ -309,7 +309,6 @@ void qdev_prop_set_macaddr(DeviceState *dev, const char
*name, uint8_t *value);
void qdev_prop_set_enum(DeviceState *dev, const char *name, int value);
/* FIXME: Remove opaque pointer properties. */
void qdev_prop_set_ptr(DeviceState *dev, const char *name, void *value);
-void qdev_prop_set_defaults(DeviceState *dev, Property *props);
void qdev_prop_register_global_list(GlobalProperty *props);
void qdev_prop_set_globals(DeviceState *dev);
--
1.7.7
[Qemu-devel] [PATCH 17/22] qdev: Convert busses to QEMU Object Model
From: Anthony Liguori
This is far less interesting than it sounds. We simply add an Object to each
BusState and then register the types appropriately. Most of the interesting
refactoring will follow in the next patches.
Since we're changing fundamental type names (BusInfo -> BusClass), it all needs
to convert at once. Fortunately, not a lot of code is affected.
Signed-off-by: Anthony Liguori
Signed-off-by: Paolo Bonzini
[AF: Made all new bus TypeInfos static const.]
[AF: Made qbus_free() call object_delete(), required {qom,glib}_allocated]
Signed-off-by: Andreas Färber
---
hw/i2c.c | 15 ++---
hw/ide/internal.h |3 ++
hw/ide/qdev.c | 21 ---
hw/intel-hda.c| 12 ---
hw/intel-hda.h|3 ++
hw/isa-bus.c | 23 +
hw/isa.h |3 ++
hw/pci-hotplug.c |6 +---
hw/pci.c | 29 +++--
hw/pci_bridge.c |2 +-
hw/pci_internals.h|3 +-
hw/qdev-monitor.c | 33 ---
hw/qdev.c | 73 +---
hw/qdev.h | 46 ++---
hw/s390-virtio-bus.c | 12 ---
hw/s390-virtio-bus.h |4 ++
hw/scsi-bus.c | 23 +
hw/scsi.h |3 ++
hw/spapr_vio.c| 12 ---
hw/spapr_vio.h|3 ++
hw/ssi.c | 15 ++---
hw/sysbus.c | 27 ++-
hw/sysbus.h |3 ++
hw/usb.h |3 ++
hw/usb/bus.c | 25 +
hw/usb/dev-smartcard-reader.c | 15 ++---
hw/virtio-serial-bus.c| 24 ++---
27 files changed, 299 insertions(+), 142 deletions(-)
diff --git a/hw/i2c.c b/hw/i2c.c
index af5979e..319b249 100644
--- a/hw/i2c.c
+++ b/hw/i2c.c
@@ -22,9 +22,13 @@ static Property i2c_props[] = {
DEFINE_PROP_END_OF_LIST(),
};
-static struct BusInfo i2c_bus_info = {
-.name = "I2C",
-.size = sizeof(i2c_bus),
+#define TYPE_I2C_BUS "i2c-bus"
+#define I2C_BUS(obj) OBJECT_CHECK(i2c_bus, (obj), TYPE_I2C_BUS)
+
+static const TypeInfo i2c_bus_info = {
+.name = TYPE_I2C_BUS,
+.parent = TYPE_BUS,
+.instance_size = sizeof(i2c_bus),
};
static void i2c_bus_pre_save(void *opaque)
@@ -62,7 +66,7 @@ i2c_bus *i2c_init_bus(DeviceState *parent, const char *name)
{
i2c_bus *bus;
-bus = FROM_QBUS(i2c_bus, qbus_create(&i2c_bus_info, parent, name));
+bus = FROM_QBUS(i2c_bus, qbus_create(TYPE_I2C_BUS, parent, name));
vmstate_register(NULL, -1, &vmstate_i2c_bus, bus);
return bus;
}
@@ -219,7 +223,7 @@ static void i2c_slave_class_init(ObjectClass *klass, void
*data)
{
DeviceClass *k = DEVICE_CLASS(klass);
k->init = i2c_slave_qdev_init;
-k->bus_info = &i2c_bus_info;
+k->bus_type = TYPE_I2C_BUS;
k->props = i2c_props;
}
@@ -234,6 +238,7 @@ static TypeInfo i2c_slave_type_info = {
static void i2c_slave_register_types(void)
{
+type_register_static(&i2c_bus_info);
type_register_static(&i2c_slave_type_info);
}
diff --git a/hw/ide/internal.h b/hw/ide/internal.h
index f8a027d..1a02f57 100644
--- a/hw/ide/internal.h
+++ b/hw/ide/internal.h
@@ -25,6 +25,9 @@ typedef struct IDEState IDEState;
typedef struct IDEDMA IDEDMA;
typedef struct IDEDMAOps IDEDMAOps;
+#define TYPE_IDE_BUS "IDE"
+#define IDE_BUS(obj) OBJECT_CHECK(IDEBus, (obj), TYPE_IDE_BUS)
+
/* Bits of HD_STATUS */
#define ERR_STAT 0x01
#define INDEX_STAT 0x02
diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c
index a91e878..c122395 100644
--- a/hw/ide/qdev.c
+++ b/hw/ide/qdev.c
@@ -32,15 +32,23 @@ static Property ide_props[] = {
DEFINE_PROP_END_OF_LIST(),
};
-static struct BusInfo ide_bus_info = {
-.name = "IDE",
-.size = sizeof(IDEBus),
-.get_fw_dev_path = idebus_get_fw_dev_path,
+static void ide_bus_class_init(ObjectClass *klass, void *data)
+{
+BusClass *k = BUS_CLASS(klass);
+
+k->get_fw_dev_path = idebus_get_fw_dev_path;
+}
+
+static const TypeInfo ide_bus_info = {
+.name = TYPE_IDE_BUS,
+.parent = TYPE_BUS,
+.instance_size = sizeof(IDEBus),
+.class_init = ide_bus_class_init,
};
void ide_bus_new(IDEBus *idebus, DeviceState *dev, int bus_id)
{
-qbus_create_inplace(&idebus->qbus, &ide_bus_info, dev, NULL);
+qbus_create_inplace(&idebus->qbus, TYPE_IDE_BUS, dev, NULL);
idebus->bus_id = bus_id;
}
@@ -249,7 +257,7 @@ static void ide_device_class_init(ObjectClass *klass, void
*data)
{
DeviceClass *k = DEVICE_CLASS(klass);
k->init = ide_qdev_init;
-k->bus_info = &ide_bus_info;
+k->bus_type = TYPE_IDE_BUS;
k->props = ide_props;
}
@@ -264,6 +272,7 @@ static TypeInfo ide_device_type_info = {
static void ide_re
Re: [Qemu-devel] [RFC] [PATCHv2 2/2] Adding basic calls to libseccomp in vl.c
On Monday, June 18, 2012 02:55:35 PM Daniel P. Berrange wrote: > On Mon, Jun 18, 2012 at 09:52:44AM -0400, Paul Moore wrote: > > On Monday, June 18, 2012 09:31:03 AM Daniel P. Berrange wrote: > > > On Fri, Jun 15, 2012 at 05:02:19PM -0400, Paul Moore wrote: > > > > On Friday, June 15, 2012 07:06:10 PM Blue Swirl wrote: > > > > > I think allowing execve() would render seccomp pretty much useless. > > > > > > > > Not necessarily. > > > > > > > > I'll agree that it does seem a bit odd to allow execve(), but there is > > > > still value in enabling seccomp to disable potentially > > > > buggy/exploitable > > > > syscalls. Let's not forget that we have over 300 syscalls on x86_64, > > > > not > > > > including the 32 bit versions, and even if we add all of the new > > > > syscalls > > > > suggested in this thread we are still talking about a small subset of > > > > syscalls. As far as security goes, the old adage of "less is more" > > > > applies. > > > > > > I can sort of see this argument, but *only* if the QEMU process is being > > > run under a dedicated, fully unprivileged (from a DAC pov) user, > > > completely > > > separate from anything else on the system. > > > > > > Or, of course, for a QEMU already confined by SELinux. > > > > Agreed ... and considering at least one major distribution takes this > > approach it seems like reasonable functionality to me. Confining QEMU, > > either through DAC and/or MAC, when faced with potentially malicious > > guests is just good sense. > > Good, I'm not missing anything then. I'd suggest that future iterations > of these patches explicitly mention the deployment scenarios in which > this technology is able to offer increases security, and also describe > the scenarios where it will not improve things. Sounds like a reasonable request to me. -- paul moore security and virtualization @ redhat
Re: [Qemu-devel] q35 chipset support
On 06/18/2012 08:51 AM, Markus Armbruster wrote: Anthony Liguori writes: On 06/15/2012 02:04 AM, Markus Armbruster wrote: Anthony Liguori writes: On 06/14/2012 02:54 PM, Jason Baron wrote: Hi, I recently updated Isaku Yamahata's q35 patches to work on the latest qemu and seabios trees. On the qemu side, most of the changes revolved around updating to use QOM and updates to the memory API. I was also able to drop quite a few patches that had already been resolved by the current qemu tree. The trees seem pretty stable and can be found here: git://github.com/jibaron/q35-qemu.git git://github.com/jibaron/q35-seabios.git I'm got the beginnings of a feature page started: http://wiki.qemu.org/Features/Q35 The approach above will not work in a QOM world unfortunately. We need to do quite a bit of ground work before adding another chipset. The biggest task is converting devices to not require an ISA bus since ICH9 simply doesn't have an ISA bus. Could you explain briefly why use of a software ISA bus construct matters for device models and/or guests? No, but I can provide a long explanation :-) Thanks! The I440FX has a very basic device topology. The PCI host is the memory controller and there's a PCI device that happens to have the SuperI/O chip + a PCI-ISA bridge. There's no IOMMU and interrupt routing is simple. PC interrupt routing is hardly ever "simple", but I get what you mean ;) The Q35 is much more sophisticated. The PCI-e complex itself can present interesting topologies and the legacy PCI bus sits within the PCI-e complex. You can still have a PCI-ISA bridge but the SuperI/O chip is not part of it. Rather that's off of a separate bus (the LPC) which does not logically reside within the PCI-e complex. Let's whether I understand. The platform devices do *not* sit behind a PCI-ISA bridge (in fact, no such bridge exists normally). Instead, they're connected via LPC. No, *some* platform devices are connected via LPC. Some are not. To give you an example: both LPC and ISA provide a bus-level DMA interface. When you think of IOMMU modeling, it looks something like this: Floppy controller: isa_memory_read(isa_dev, ...) -> talks to DMA controller DMA controller: Implemented in PIIX4 for I440FX, within ICH9 for q35 Uses cpu_physical_memory_rw() which takes the get_system() MemoryRegion So we cannot have the DMA controller be a ISA/LPC device as we do today because the ISA bus should only use isa_memory_read() which is implemented by the DMA controller. We have an infinite modeling loop today :-) What I don't get is why that connection can't be modelled as an ISA bus. Provided by a Systembus-ISA bridge if you like. To be clear, it's not LPC vs. ISA. We can't just make all platform devices an X bus device. There's more of a hierarchy and it's guest visible once we throw in an IOMMU capable chipset. Regards, Anthony Liguori And because there is an IOMMU, this topology is visible to the guest. Granted, initial Q35 support won't come with an IOMMU, but we will need to do this eventually. There's already non-x86 patches floating around. Normally, I would say we should deal with this later when we need an IOMMU but part of the reason this is so hard to fix for the PC already is the first set of Q35 patches we merged ages ago that introduced the silliness of pc_piix.c. The first step in cleaning this all up is essentially reverting that first set of patches. So we need to fix our topological representation of platform devices before we start adding more complex chipsets. Otherwise, we're going to end up in a bad situation in the near future. I'm not sufficiently familiar with the first set of Q35 patches to risk an opinion here...
[Qemu-devel] [PATCH 06/22] qom: Drop type_register_static_alias() macro
From: Paolo Bonzini
It's unused.
Signed-off-by: Paolo Bonzini
Signed-off-by: Andreas Färber
---
include/qemu/object.h |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/include/qemu/object.h b/include/qemu/object.h
index ff5444f..b16d99b 100644
--- a/include/qemu/object.h
+++ b/include/qemu/object.h
@@ -527,8 +527,6 @@ const char *object_get_typename(Object *obj);
*/
Type type_register_static(const TypeInfo *info);
-#define type_register_static_alias(info, name) do { } while (0)
-
/**
* type_register:
* @info: The #TypeInfo of the new type
--
1.7.7
Re: [Qemu-devel] q35 chipset support
On 06/17/2012 03:25 AM, Michael S. Tsirkin wrote: On Fri, Jun 15, 2012 at 12:58:33PM -0500, Anthony Liguori wrote: The Q35 is much more sophisticated. The PCI-e complex itself can present interesting topologies and the legacy PCI bus sits within the PCI-e complex. Ah, so we can mix in PCI as well? Cool. How does such a mixed topology look? It does, but I'm having a really hard time deciphering the spec here. Here's what it says: "The ICH9 PCI interface provides a 33 MHz, Revision 2.3 implementation. The ICH9 integrates a PCI arbiter that supports up to four external PCI bus masters in addition to the internal ICH9 requests. This allows for combinations of up to four PCI down devices and PCI slots." So my interpretation of this is that it provides the ability to expose legacy PCI slots. I can't get a reading though on how this shows up in the PCI topology though. It sounds like it would show up as a separate PCI domain. Regards, Anthony Liguori
[Qemu-devel] [PATCH 1/4] s390x: fix s390 virtio aliases
Some of the virtio devices have the same frontend name, but actually
implement different devices behind the scenes through aliases.
The indicator which device type to use is the architecture. On s390, we
want s390 virtio devices. On everything else, we want PCI devices.
Reflect this in the alias selection code. This way we fix commands like
-device virtio-blk on s390x which with this patch applied select the
correct virtio-blk-s390 device rather than virtio-blk-pci.
Reported-by: Christian Borntraeger
Signed-off-by: Anthony Liguori
Signed-off-by: Alexander Graf
---
hw/qdev-monitor.c | 27 ---
1 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/hw/qdev-monitor.c b/hw/qdev-monitor.c
index b01ef06..f83b3ad 100644
--- a/hw/qdev-monitor.c
+++ b/hw/qdev-monitor.c
@@ -20,6 +20,7 @@
#include "qdev.h"
#include "monitor.h"
#include "qmp-commands.h"
+#include "arch_init.h"
/*
* Aliases were a bad idea from the start. Let's keep them
@@ -29,16 +30,18 @@ typedef struct QDevAlias
{
const char *typename;
const char *alias;
+uint32_t arch_mask;
} QDevAlias;
static const QDevAlias qdev_alias_table[] = {
-{ "virtio-blk-pci", "virtio-blk" },
-{ "virtio-net-pci", "virtio-net" },
-{ "virtio-serial-pci", "virtio-serial" },
-{ "virtio-balloon-pci", "virtio-balloon" },
-{ "virtio-blk-s390", "virtio-blk" },
-{ "virtio-net-s390", "virtio-net" },
-{ "virtio-serial-s390", "virtio-serial" },
+{ "virtio-blk-pci", "virtio-blk", QEMU_ARCH_ALL & ~QEMU_ARCH_S390X },
+{ "virtio-net-pci", "virtio-net", QEMU_ARCH_ALL & ~QEMU_ARCH_S390X },
+{ "virtio-serial-pci", "virtio-serial", QEMU_ARCH_ALL & ~QEMU_ARCH_S390X },
+{ "virtio-balloon-pci", "virtio-balloon",
+QEMU_ARCH_ALL & ~QEMU_ARCH_S390X },
+{ "virtio-blk-s390", "virtio-blk", QEMU_ARCH_S390X },
+{ "virtio-net-s390", "virtio-net", QEMU_ARCH_S390X },
+{ "virtio-serial-s390", "virtio-serial", QEMU_ARCH_S390X },
{ "lsi53c895a", "lsi" },
{ "ich9-ahci", "ahci" },
{ }
@@ -50,6 +53,11 @@ static const char *qdev_class_get_alias(DeviceClass *dc)
int i;
for (i = 0; qdev_alias_table[i].typename; i++) {
+if (qdev_alias_table[i].arch_mask &&
+!(qdev_alias_table[i].arch_mask & arch_type)) {
+continue;
+}
+
if (strcmp(qdev_alias_table[i].typename, typename) == 0) {
return qdev_alias_table[i].alias;
}
@@ -110,6 +118,11 @@ static const char *find_typename_by_alias(const char
*alias)
int i;
for (i = 0; qdev_alias_table[i].alias; i++) {
+if (qdev_alias_table[i].arch_mask &&
+!(qdev_alias_table[i].arch_mask & arch_type)) {
+continue;
+}
+
if (strcmp(qdev_alias_table[i].alias, alias) == 0) {
return qdev_alias_table[i].typename;
}
--
1.6.0.2
[Qemu-devel] Status of query-netdev QMP command
Hello, I've read from the GSoC/2010 that some work was being done creating a query-netdev QMP command: http://wiki.qemu.org/Google_Summer_of_Code_2010/QMP#query-netdev The status says that "mentor has merged it into his tree", but I cannot see this command anywhere upstream, and it will come really handy for what I'm trying to do, do someone know where this has gone? Thanks, Roger.
Re: [Qemu-devel] q35 chipset support
On Fri, Jun 15, 2012 at 12:58:33PM -0500, Anthony Liguori wrote: > So we need to fix our topological representation of platform devices > before we start adding more complex chipsets. Otherwise, we're > going to end up in a bad situation in the near future. OTOH more in-tree examples especially for x86 will keep us honest: help make sure abstractions make sense, and prevent people from special casing piix because this is the prevalent platform for kvm ATM. -- MST
Re: [Qemu-devel] q35 chipset support
On 06/18/2012 09:20 AM, Michael S. Tsirkin wrote: On Fri, Jun 15, 2012 at 12:58:33PM -0500, Anthony Liguori wrote: So we need to fix our topological representation of platform devices before we start adding more complex chipsets. Otherwise, we're going to end up in a bad situation in the near future. OTOH more in-tree examples especially for x86 will keep us honest: help make sure abstractions make sense, and prevent people from special casing piix because this is the prevalent platform for kvm ATM. Yes, more in-tree *correct* examples. I'm very much in favor of merging q35. Regards, Anthony Liguori
[Qemu-devel] The latest qemu.git/master build break
HI, When i want to rebase my hub-based network patchset to latest qemu.git/master, i found the build break. lt LINK libcacard.la ar: libcacard/cac.o: No such file or directory make[1]: *** [libcacard.la] Error 1 make: *** [subdir-libcacard] Error 2 -- Regards, Zhi Yong Wu
Re: [Qemu-devel] q35 chipset support
On Mon, Jun 18, 2012 at 09:16:24AM -0500, Anthony Liguori wrote: > On 06/17/2012 03:25 AM, Michael S. Tsirkin wrote: > >On Fri, Jun 15, 2012 at 12:58:33PM -0500, Anthony Liguori wrote: > >>The Q35 is much more sophisticated. The PCI-e complex itself can > >>present interesting topologies and the legacy PCI bus sits within > >>the PCI-e complex. > > > >Ah, so we can mix in PCI as well? Cool. How does > >such a mixed topology look? > > It does, but I'm having a really hard time deciphering the spec > here. Here's what it says: > > "The ICH9 PCI interface provides a 33 MHz, Revision 2.3 implementation. The > ICH9 > integrates a PCI arbiter that supports up to four external PCI bus > masters in addition to the internal ICH9 requests. This allows for > combinations of up to four PCI down devices and PCI slots." > > So my interpretation of this is that it provides the ability to > expose legacy PCI slots. I can't get a reading though on how this > shows up in the PCI topology though. > > It sounds like it would show up as a separate PCI domain. > > Regards, > > Anthony Liguori Actually I found a box with ICH9 http://fpaste.org/VREA/ or see attached. It looks like there's at least one PCI bridge attached to the host bridge. > > [mst@tuck ~]$ lspci 00:00.0 Host bridge: Intel Corporation Mobile 4 Series Chipset Memory Controller Hub (rev 07) 00:02.0 VGA compatible controller: Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller (rev 07) 00:02.1 Display controller: Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller (rev 07) 00:03.0 Communication controller: Intel Corporation Mobile 4 Series Chipset MEI Controller (rev 07) 00:03.3 Serial controller: Intel Corporation Mobile 4 Series Chipset AMT SOL Redirection (rev 07) 00:19.0 Ethernet controller: Intel Corporation 82567LM Gigabit Network Connection (rev 03) 00:1a.0 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #4 (rev 03) 00:1a.1 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #5 (rev 03) 00:1a.2 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #6 (rev 03) 00:1a.7 USB Controller: Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #2 (rev 03) 00:1b.0 Audio device: Intel Corporation 82801I (ICH9 Family) HD Audio Controller (rev 03) 00:1c.0 PCI bridge: Intel Corporation 82801I (ICH9 Family) PCI Express Port 1 (rev 03) 00:1c.1 PCI bridge: Intel Corporation 82801I (ICH9 Family) PCI Express Port 2 (rev 03) 00:1c.3 PCI bridge: Intel Corporation 82801I (ICH9 Family) PCI Express Port 4 (rev 03) 00:1c.4 PCI bridge: Intel Corporation 82801I (ICH9 Family) PCI Express Port 5 (rev 03) 00:1d.0 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 (rev 03) 00:1d.1 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 (rev 03) 00:1d.2 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 (rev 03) 00:1d.7 USB Controller: Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 (rev 03) 00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev 93) 00:1f.0 ISA bridge: Intel Corporation ICH9M-E LPC Interface Controller (rev 03) 00:1f.2 SATA controller: Intel Corporation ICH9M/M-E SATA AHCI Controller (rev 03) 00:1f.3 SMBus: Intel Corporation 82801I (ICH9 Family) SMBus Controller (rev 03) 03:00.0 Network controller: Intel Corporation PRO/Wireless 5100 AGN [Shiloh] Network Connection 15:00.0 CardBus bridge: Ricoh Co Ltd RL5c476 II (rev ba) 15:00.1 FireWire (IEEE 1394): Ricoh Co Ltd R5C832 IEEE 1394 Controller (rev 04) 15:00.2 SD Host controller: Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter (rev 21) 15:00.4 System peripheral: Ricoh Co Ltd R5C592 Memory Stick Bus Host Adapter (rev 11) 15:00.5 System peripheral: Ricoh Co Ltd xD-Picture Card Controller (rev 11) [mst@tuck ~]$ sudo lspci -vv [sudo] password for mst: 00:00.0 Host bridge: Intel Corporation Mobile 4 Series Chipset Memory Controller Hub (rev 07) Subsystem: Lenovo Device 20e0 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- Kernel driver in use: agpgart-intel 00:02.0 VGA compatible controller: Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller (rev 07) (prog-if 00 [VGA controller]) Subsystem: Lenovo Device 20e4 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- [disabled] Capabilities: [90] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 41a1 Capabilities: [d0] Power Management version 3 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D
[Qemu-devel] [PATCH 03/22] qom: Add object_child_foreach()
From: Paolo Bonzini
A utility function that will be used to implement hierarchical realization.
Signed-off-by: Paolo Bonzini
Reviewed-by: Anthony Liguori
[AF: Drop unrelated whitespace change, add Returns: in documentation]
[AF: Use new object_property_is_child() helper.]
Signed-off-by: Andreas Färber
---
include/qemu/object.h | 14 ++
qom/object.c | 17 +
2 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/include/qemu/object.h b/include/qemu/object.h
index 487559c..ce9e51f 100644
--- a/include/qemu/object.h
+++ b/include/qemu/object.h
@@ -918,6 +918,20 @@ void object_property_add_str(Object *obj, const char *name,
struct Error **errp);
/**
+ * object_child_foreach:
+ * @obj: the object whose children will be navigated
+ * @fn: the iterator function to be called
+ * @opaque: an opaque value that will be passed to the iterator
+ *
+ * Call @fn passing each child of @obj and @opaque to it, until @fn returns
+ * non-zero.
+ *
+ * Returns: The last value returned by @fn, or 0 if there is no child.
+ */
+int object_child_foreach(Object *obj, int (*fn)(Object *child, void *opaque),
+ void *opaque);
+
+/**
* container_get:
* @root: root of the #path, e.g., object_get_root()
* @path: path to the container
diff --git a/qom/object.c b/qom/object.c
index 105c649..7a70d52 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -607,6 +607,23 @@ void object_class_foreach(void (*fn)(ObjectClass *klass,
void *opaque),
g_hash_table_foreach(type_table_get(), object_class_foreach_tramp, &data);
}
+int object_child_foreach(Object *obj, int (*fn)(Object *child, void *opaque),
+ void *opaque)
+{
+ObjectProperty *prop;
+int ret = 0;
+
+QTAILQ_FOREACH(prop, &obj->properties, node) {
+if (object_property_is_child(prop)) {
+ret = fn(prop->opaque, opaque);
+if (ret != 0) {
+break;
+}
+}
+}
+return ret;
+}
+
static void object_class_get_list_tramp(ObjectClass *klass, void *opaque)
{
GSList **list = opaque;
--
1.7.7
[Qemu-devel] [PATCH 08/22] m48t59: Rename "type" property to "model"
From: Paolo Bonzini
This resolves a name conflict with the qdev "type" property that is
about to move into Object.
Signed-off-by: Paolo Bonzini
[AF: Add braces missing in original code.]
Signed-off-by: Andreas Färber
---
hw/m48t59.c | 40 ++--
1 files changed, 22 insertions(+), 18 deletions(-)
diff --git a/hw/m48t59.c b/hw/m48t59.c
index 0c50f45..dd6cb37 100644
--- a/hw/m48t59.c
+++ b/hw/m48t59.c
@@ -65,7 +65,7 @@ struct M48t59State {
/* NVRAM storage */
uint8_t *buffer;
/* Model parameters */
-uint32_t type; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
+uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
/* NVRAM storage */
uint16_t addr;
uint8_t lock;
@@ -197,10 +197,11 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t
val)
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
/* check for NVRAM access */
-if ((NVRAM->type == 2 && addr < 0x7f8) ||
-(NVRAM->type == 8 && addr < 0x1ff8) ||
-(NVRAM->type == 59 && addr < 0x1ff0))
+if ((NVRAM->model == 2 && addr < 0x7f8) ||
+(NVRAM->model == 8 && addr < 0x1ff8) ||
+(NVRAM->model == 59 && addr < 0x1ff0)) {
goto do_write;
+}
/* TOD access */
switch (addr) {
@@ -334,10 +335,11 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t
val)
tmp = from_bcd(val);
if (tmp >= 0 && tmp <= 99) {
get_time(NVRAM, &tm);
-if (NVRAM->type == 8)
+if (NVRAM->model == 8) {
tm.tm_year = from_bcd(val) + 68; // Base year is 1968
-else
+} else {
tm.tm_year = from_bcd(val);
+}
set_time(NVRAM, &tm);
}
break;
@@ -362,10 +364,11 @@ uint32_t m48t59_read (void *opaque, uint32_t addr)
uint32_t retval = 0xFF;
/* check for NVRAM access */
-if ((NVRAM->type == 2 && addr < 0x078f) ||
-(NVRAM->type == 8 && addr < 0x1ff8) ||
-(NVRAM->type == 59 && addr < 0x1ff0))
+if ((NVRAM->model == 2 && addr < 0x078f) ||
+(NVRAM->model == 8 && addr < 0x1ff8) ||
+(NVRAM->model == 59 && addr < 0x1ff0)) {
goto do_read;
+}
/* TOD access */
switch (addr) {
@@ -439,10 +442,11 @@ uint32_t m48t59_read (void *opaque, uint32_t addr)
case 0x07FF:
/* year */
get_time(NVRAM, &tm);
-if (NVRAM->type == 8)
+if (NVRAM->model == 8) {
retval = to_bcd(tm.tm_year - 68); // Base year is 1968
-else
+} else {
retval = to_bcd(tm.tm_year);
+}
break;
default:
/* Check lock registers state */
@@ -633,7 +637,7 @@ static const MemoryRegionOps m48t59_io_ops = {
/* Initialisation routine */
M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
- uint32_t io_base, uint16_t size, int type)
+ uint32_t io_base, uint16_t size, int model)
{
DeviceState *dev;
SysBusDevice *s;
@@ -641,7 +645,7 @@ M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t
mem_base,
M48t59State *state;
dev = qdev_create(NULL, "m48t59");
-qdev_prop_set_uint32(dev, "type", type);
+qdev_prop_set_uint32(dev, "model", model);
qdev_prop_set_uint32(dev, "size", size);
qdev_prop_set_uint32(dev, "io_base", io_base);
qdev_init_nofail(dev);
@@ -661,14 +665,14 @@ M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t
mem_base,
}
M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
- int type)
+ int model)
{
M48t59ISAState *d;
ISADevice *dev;
M48t59State *s;
dev = isa_create(bus, "m48t59_isa");
-qdev_prop_set_uint32(&dev->qdev, "type", type);
+qdev_prop_set_uint32(&dev->qdev, "model", model);
qdev_prop_set_uint32(&dev->qdev, "size", size);
qdev_prop_set_uint32(&dev->qdev, "io_base", io_base);
qdev_init_nofail(&dev->qdev);
@@ -686,7 +690,7 @@ M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base,
uint16_t size,
static void m48t59_init_common(M48t59State *s)
{
s->buffer = g_malloc0(s->size);
-if (s->type == 59) {
+if (s->model == 59) {
s->alrm_timer = qemu_new_timer_ns(rtc_clock, &alarm_cb, s);
s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s);
}
@@ -722,7 +726,7 @@ static int m48t59_init1(SysBusDevice *dev)
static Property m48t59_isa_properties[] = {
DEFINE_PROP_UINT32("size",M48t59ISAState, state.size,-1),
-DEFINE_PROP_UINT32("type",M48t59ISAState, state.type,-1),
+DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1),
DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0),
DEFINE_PROP_END_OF_LIST(),
};
@@ -746,7 +750,7 @@ static TypeInfo m48t59_isa_info = {
static Property m48t59_properties[] = {
DE
Re: [Qemu-devel] q35 chipset support
On Mon, Jun 18, 2012 at 09:22:43AM -0500, Anthony Liguori wrote: > On 06/18/2012 09:20 AM, Michael S. Tsirkin wrote: > >On Fri, Jun 15, 2012 at 12:58:33PM -0500, Anthony Liguori wrote: > >>So we need to fix our topological representation of platform devices > >>before we start adding more complex chipsets. Otherwise, we're > >>going to end up in a bad situation in the near future. > > > >OTOH more in-tree examples especially for x86 will keep us > >honest: help make sure abstractions make sense, > >and prevent people from special casing piix because > >this is the prevalent platform for kvm ATM. > > Yes, more in-tree *correct* examples. I'm very much in favor of merging q35. > > Regards, > > Anthony Liguori But is there a way to build a correct chipset right now? Or is this blocked waiting for more infrastructure to get merged? -- MST
[Qemu-devel] [PATCH 12/22] qdev: Move bus properties to abstract superclasses
From: Paolo Bonzini
In qdev, each bus in practice identified an abstract superclass, but
this was mostly hidden. In QOM, instead, these abstract classes are
explicit so we can move bus properties there.
All bus property walks are removed, and all device property walks
are changed to look along the class hierarchy instead.
We would have duplicates if class A defines some properties and its
subclass B does not define any, because class_b->props will be
left equal to class_a->props.
The solution here is to reintroduce the class_base_init TypeInfo
callback, that was present in one of the early QOM versions but
removed (on my request...) before committing.
This breaks global bus properties, an obscure feature when used
with the command-line which is actually useful and used when used by
backwards-compatible machine types. So this patch also adjusts the
global bus properties in hw/pc_piix.c to refer to the abstract class.
Globals and other properties must be modified in the same patch to
avoid complications related to initialization ordering.
Signed-off-by: Paolo Bonzini
Signed-off-by: Andreas Färber
---
hw/i2c.c |2 +-
hw/ide/qdev.c |2 +-
hw/intel-hda.c|2 +-
hw/pc_piix.c |7 +++--
hw/pci.c |2 +-
hw/qdev-monitor.c | 41 +++
hw/qdev-properties.c | 38 ++--
hw/qdev.c | 47 ++--
hw/qdev.h |5
hw/scsi-bus.c |2 +-
hw/spapr_vio.c|2 +-
hw/usb/bus.c |2 +-
hw/usb/dev-smartcard-reader.c |2 +-
hw/virtio-serial-bus.c|2 +-
14 files changed, 73 insertions(+), 83 deletions(-)
diff --git a/hw/i2c.c b/hw/i2c.c
index cb10b1d..af5979e 100644
--- a/hw/i2c.c
+++ b/hw/i2c.c
@@ -25,7 +25,6 @@ static Property i2c_props[] = {
static struct BusInfo i2c_bus_info = {
.name = "I2C",
.size = sizeof(i2c_bus),
-.props = i2c_props,
};
static void i2c_bus_pre_save(void *opaque)
@@ -221,6 +220,7 @@ static void i2c_slave_class_init(ObjectClass *klass, void
*data)
DeviceClass *k = DEVICE_CLASS(klass);
k->init = i2c_slave_qdev_init;
k->bus_info = &i2c_bus_info;
+k->props = i2c_props;
}
static TypeInfo i2c_slave_type_info = {
diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c
index b67df3d..a91e878 100644
--- a/hw/ide/qdev.c
+++ b/hw/ide/qdev.c
@@ -36,7 +36,6 @@ static struct BusInfo ide_bus_info = {
.name = "IDE",
.size = sizeof(IDEBus),
.get_fw_dev_path = idebus_get_fw_dev_path,
-.props = ide_props,
};
void ide_bus_new(IDEBus *idebus, DeviceState *dev, int bus_id)
@@ -251,6 +250,7 @@ static void ide_device_class_init(ObjectClass *klass, void
*data)
DeviceClass *k = DEVICE_CLASS(klass);
k->init = ide_qdev_init;
k->bus_info = &ide_bus_info;
+k->props = ide_props;
}
static TypeInfo ide_device_type_info = {
diff --git a/hw/intel-hda.c b/hw/intel-hda.c
index 0994f6b..e2bd41e 100644
--- a/hw/intel-hda.c
+++ b/hw/intel-hda.c
@@ -37,7 +37,6 @@ static Property hda_props[] = {
static struct BusInfo hda_codec_bus_info = {
.name = "HDA",
.size = sizeof(HDACodecBus),
-.props = hda_props,
};
void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus,
@@ -1278,6 +1277,7 @@ static void hda_codec_device_class_init(ObjectClass
*klass, void *data)
k->init = hda_codec_dev_init;
k->exit = hda_codec_dev_exit;
k->bus_info = &hda_codec_bus_info;
+k->props = hda_props;
}
static TypeInfo hda_codec_device_type_info = {
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index f49b0aa..d68f77a 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -29,6 +29,7 @@
#include "apic.h"
#include "pci.h"
#include "pci_ids.h"
+#include "usb.h"
#include "net.h"
#include "boards.h"
#include "ide.h"
@@ -374,7 +375,7 @@ static QEMUMachine pc_machine_v1_1 = {
.property = "vapic",\
.value= "off",\
},{\
-.driver = "USB",\
+.driver = TYPE_USB_DEVICE,\
.property = "full-path",\
.value= "no",\
}
@@ -447,7 +448,7 @@ static QEMUMachine pc_machine_v0_14 = {
#define PC_COMPAT_0_13 \
PC_COMPAT_0_14,\
{\
-.driver = "PCI",\
+.driver = TYPE_PCI_DEVICE,\
.property = "command_serr_enable",\
.value= "off",\
},{\
@@ -519,7 +520,7 @@ static QEMUMachine pc_machine_v0_12 = {
.property = "vectors",\
.value= stringify(0),\
},{\
-.driver = "PCI",\
+.driver = TYPE_PCI_DEVICE,\
.property = "rombar",\
.value= stringify(0),\
}
diff --git a/hw/pci.c b/hw/pci.c
index 377039e..09ce4e7 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -
[Qemu-devel] [PATCH 15/22] qdev: Use wrapper for qdev_get_path
From: Anthony Liguori
This makes it easier to remove it from BusInfo.
Signed-off-by: Anthony Liguori
Signed-off-by: Paolo Bonzini
[AF: Drop now unnecessary NULL initialization in scsibus_get_dev_path()]
Signed-off-by: Andreas Färber
---
exec.c|4 ++--
hw/qdev.c | 16
hw/qdev.h |2 ++
hw/scsi-bus.c |6 ++
hw/usb/bus.c |5 ++---
hw/usb/desc.c |5 +++--
savevm.c | 12 ++--
7 files changed, 33 insertions(+), 17 deletions(-)
diff --git a/exec.c b/exec.c
index 5c9b762..b5d6885 100644
--- a/exec.c
+++ b/exec.c
@@ -2603,8 +2603,8 @@ void qemu_ram_set_idstr(ram_addr_t addr, const char
*name, DeviceState *dev)
assert(new_block);
assert(!new_block->idstr[0]);
-if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) {
-char *id = dev->parent_bus->info->get_dev_path(dev);
+if (dev) {
+char *id = qdev_get_dev_path(dev);
if (id) {
snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
g_free(id);
diff --git a/hw/qdev.c b/hw/qdev.c
index 7f18590..7b2802d 100644
--- a/hw/qdev.c
+++ b/hw/qdev.c
@@ -494,6 +494,22 @@ char* qdev_get_fw_dev_path(DeviceState *dev)
return strdup(path);
}
+char *qdev_get_dev_path(DeviceState *dev)
+{
+BusInfo *businfo;
+
+if (!dev || !dev->parent_bus) {
+return NULL;
+}
+
+businfo = dev->parent_bus->info;
+if (businfo->get_dev_path) {
+return businfo->get_dev_path(dev);
+}
+
+return NULL;
+}
+
/**
* Legacy property handling
*/
diff --git a/hw/qdev.h b/hw/qdev.h
index 1af5382..013ccf2 100644
--- a/hw/qdev.h
+++ b/hw/qdev.h
@@ -352,4 +352,6 @@ void qdev_set_parent_bus(DeviceState *dev, BusState *bus);
extern int qdev_hotplug;
+char *qdev_get_dev_path(DeviceState *dev);
+
#endif
diff --git a/hw/scsi-bus.c b/hw/scsi-bus.c
index a1d75b9..e79bb54 100644
--- a/hw/scsi-bus.c
+++ b/hw/scsi-bus.c
@@ -1453,12 +1453,10 @@ static char *scsibus_get_dev_path(DeviceState *dev)
{
SCSIDevice *d = DO_UPCAST(SCSIDevice, qdev, dev);
DeviceState *hba = dev->parent_bus->parent;
-char *id = NULL;
+char *id;
char *path;
-if (hba && hba->parent_bus && hba->parent_bus->info->get_dev_path) {
-id = hba->parent_bus->info->get_dev_path(hba);
-}
+id = qdev_get_dev_path(hba);
if (id) {
path = g_strdup_printf("%s/%d:%d:%d", id, d->channel, d->id, d->lun);
} else {
diff --git a/hw/usb/bus.c b/hw/usb/bus.c
index 64887d5..8b08f93 100644
--- a/hw/usb/bus.c
+++ b/hw/usb/bus.c
@@ -467,9 +467,8 @@ static char *usb_get_dev_path(DeviceState *qdev)
DeviceState *hcd = qdev->parent_bus->parent;
char *id = NULL;
-if ((dev->flags & (1 << USB_DEV_FLAG_FULL_PATH)) &&
-hcd && hcd->parent_bus && hcd->parent_bus->info->get_dev_path) {
-id = hcd->parent_bus->info->get_dev_path(hcd);
+if (dev->flags & (1 << USB_DEV_FLAG_FULL_PATH)) {
+id = qdev_get_dev_path(hcd);
}
if (id) {
char *ret = g_strdup_printf("%s/%s", id, dev->port->path);
diff --git a/hw/usb/desc.c b/hw/usb/desc.c
index e8a3c6a..0a9d3c9 100644
--- a/hw/usb/desc.c
+++ b/hw/usb/desc.c
@@ -432,12 +432,13 @@ void usb_desc_create_serial(USBDevice *dev)
const USBDesc *desc = usb_device_get_usb_desc(dev);
int index = desc->id.iSerialNumber;
char serial[64];
+char *path;
int dst;
assert(index != 0 && desc->str[index] != NULL);
dst = snprintf(serial, sizeof(serial), "%s", desc->str[index]);
-if (hcd && hcd->parent_bus && hcd->parent_bus->info->get_dev_path) {
-char *path = hcd->parent_bus->info->get_dev_path(hcd);
+path = qdev_get_dev_path(hcd);
+if (path) {
dst += snprintf(serial+dst, sizeof(serial)-dst, "-%s", path);
}
dst += snprintf(serial+dst, sizeof(serial)-dst, "-%s", dev->port->path);
diff --git a/savevm.c b/savevm.c
index 2d18bab..818ddfc 100644
--- a/savevm.c
+++ b/savevm.c
@@ -1248,8 +1248,8 @@ int register_savevm_live(DeviceState *dev,
se->is_ram = 1;
}
-if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) {
-char *id = dev->parent_bus->info->get_dev_path(dev);
+if (dev) {
+char *id = qdev_get_dev_path(dev);
if (id) {
pstrcpy(se->idstr, sizeof(se->idstr), id);
pstrcat(se->idstr, sizeof(se->idstr), "/");
@@ -1292,8 +1292,8 @@ void unregister_savevm(DeviceState *dev, const char
*idstr, void *opaque)
SaveStateEntry *se, *new_se;
char id[256] = "";
-if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) {
-char *path = dev->parent_bus->info->get_dev_path(dev);
+if (dev) {
+char *path = qdev_get_dev_path(dev);
if (path) {
pstrcpy(id, sizeof(id), path);
pstrcat(id, sizeof(id), "/");
@@ -1334,8 +1334,8 @@ int vmstate_register_with_alias_id(DeviceState *dev, int
instance_id,
se->alias_i
Re: [Qemu-devel] q35 chipset support
On Mon, Jun 18, 2012 at 03:52:34PM +0200, Markus Armbruster wrote: > Anthony Liguori writes: > > > On 06/15/2012 12:57 PM, Jason Baron wrote: > >> On Thu, Jun 14, 2012 at 03:16:03PM -0500, Anthony Liguori wrote: > >>> On 06/14/2012 02:54 PM, Jason Baron wrote: > Hi, > > I recently updated Isaku Yamahata's q35 patches to work on the latest > qemu and > seabios trees. On the qemu side, most of the changes revolved around > updating > to use QOM and updates to the memory API. I was also able to drop quite > a few > patches that had already been resolved by the current qemu tree. > > The trees seem pretty stable and can be found here: > > git://github.com/jibaron/q35-qemu.git > git://github.com/jibaron/q35-seabios.git > >>> > >>> I'm got the beginnings of a feature page started: > >>> > >>> http://wiki.qemu.org/Features/Q35 > >>> > >>> The approach above will not work in a QOM world unfortunately. We > >>> need to do quite a bit of ground work before adding another chipset. > >>> The biggest task is converting devices to not require an ISA bus > >>> since ICH9 simply doesn't have an ISA bus. > >>> > >> > >> Right, there is no h/w isa bus, but the LPC interface chip is modeled as > >> an isa > >> bridge. So having an isa bus hanging off of it doesn't seem unreasonable. > >> Unless > >> there is some more fundamental reason not do it this way? > >> > >> It hows up in lspci as: > >> > >> 00:1f.0 ISA bridge: Intel Corporation 82801IB (ICH9) LPC Interface > >> Controller (rev 02) > > > > It's not a question of ISA vs. LPC, it's which devices are actually on > > that bus. See my respond to Markus's note. > > Maybe I'm naive, but platform devices handing off an ISA bus provided by > that ICH9 ISA bridge looks like a fair approximation to me. Yes, the > actual wiring is LPC, but that's a hardware detail invisible to device > models and guest, isn't it? > > Of course, you can't connect anything but the platform devices to that > bus. To connect other ISA devices, you'd have to add a second ISA > bridge. I suspect that's what you meant by "You can still have a > PCI-ISA bridge but the SuperI/O chip is not part of it" elsewhere in > this thread. > > No idea whether such beasts exist in the physical world, and how they > work. See a dump from an old machine of mine (thinkpad T500 FWIW): it does have an ISA bridge behind the root bus.
