Re: [Mesa-dev] [PATCH 2/2] i965: Fix typo in nir_op_pack_double_2x32_split handling

[Iago Toral]

On Fri, 2016-10-14 at 10:23 -0700, Ian Romanick wrote:
> On 10/08/2016 09:33 AM, Eduardo Lima Mitev wrote:
> > 
> > On 10/08/2016 02:12 AM, Ian Romanick wrote:
> > > 
> > > From: Ian Romanick 
> > > 
> > > This was found partially by inspection and partially by hitting a
> > > problem while working on nir_op_pack_int64_2x32_split.  The code
> > > previously would 'continue' if (instr->src[i].src.is_ssa), but
> > > the code
> > > immediately following in the loop treats instr->src[i] as an SSA
> > > value.
> > > 
> > > Signed-off-by: Ian Romanick 
> > > Cc: mesa-sta...@lists.freedesktop.org
> > > Cc: Iago Toral Quiroga 
> > > ---
> > >  src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > 
> > > diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> > > b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> > > index 4e68ffb..2cbcab1 100644
> > > --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> > > +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> > > @@ -1208,7 +1208,7 @@ fs_visitor::nir_emit_alu(const fs_builder
> > > &bld, nir_alu_instr *instr)
> > > * the unpack operation.
> > > */
> > >    for (int i = 0; i < 2; i++) {
> > > - if (instr->src[i].src.is_ssa)
> > > + if (!instr->src[i].src.is_ssa)
> > >  continue;
> > >  
> > Good catch!
> But maybe not.  Re-running this through the CI shows about 1,000 test
> regressions due to assertion failures.  I looked at the rest of the
> loop, and I'm really not sure how this works:

Urgh, what a mess, I think it is very likely that I initially wrote
this optimization like this:

if (is_ssa) {
   ...
   if (is_alu) {
  ...
   }
}

And eventually decided to change that to this style:

if (!is_ssa)
  continue:

if (!is_alu)
  continue:

...

But forgot to change all the conditions, resulting in the opt never
running again. We did not notice this because thanks to Curro's work on
fixing spilling on the FS backend with his SIMD32 patches, the piglit
tests that would fail to compile without this optimization started to
spill just fine and pass without this.

I am sending a patch to get this fixed. Even if the nir algebraic opt
pass seems like a better place to do this I guess we want this fixed
until we do that.

This is what is wrong:

>   for (int i = 0; i < 2; i++) {
>  if (instr->src[i].src.is_ssa)
> continue;

This should be:

if (!instr->src[i].src.is_ssa)
   continue;

>  const nir_instr *parent_instr = instr->src[i].src.ssa-
> >parent_instr;
> 
> We skip this if the source is SSA, but then we use it as SSA.
> 
>  if (parent_instr->type == nir_instr_type_alu)
> continue;

This should be:

if (parent_instr->type != nir_instr_type_alu)
   continue;

>  const nir_alu_instr *alu_parent =
> nir_instr_as_alu(parent_instr);
> 
> We skip this if the parent is ALU, but then we use it as ALU.  The
> assertion failure occurs inside nir_instr_as_alu.
> 
>  if (alu_parent->op == nir_op_unpack_double_2x32_split_x ||
>  alu_parent->op == nir_op_unpack_double_2x32_split_y)
> continue;

This should be != && !=

>  if (!alu_parent->src[0].src.is_ssa)
> continue;

This one is correct.

>  op[i] = get_nir_src(alu_parent->src[0].src);
>  op[i] = offset(retype(op[i], BRW_REGISTER_TYPE_DF), bld,
> alu_parent->src[0].swizzle[channel]);
>  if (alu_parent->op == nir_op_unpack_double_2x32_split_y)
> op[i] = subscript(op[i], BRW_REGISTER_TYPE_UD, 1);
>  else
> op[i] = subscript(op[i], BRW_REGISTER_TYPE_UD, 0);
>   }
> 
> Were you guys ever able to make this optimization trigger?  I suspect
> that the very first continue always occurs, so none of this actually
> happens.  Either way, it seems like this optimization should happen
> in
> nir_opt_algebraic instead.

I was able to make it trigger when I wrote the initial version. In fact
I wrote this because otherwise, before the spilling fixes that Curro
implemented in the FS backend, without this optimization some tests (I
think some varying-packing tests for doubles) would fail to compile. I
remember this went through a few changes during review and I probably
messed it up at some point.

> This has come up because I need to do something similar for
> int64.  All
> of the lowering passes for int64 will generate a lot of
> unpack(pack(...)) type sequences.  I'm doing the lowering in GLSL IR,
> so I've also done the algebraic optimization in GLSL IR.
> 
> > 
> > Both patches are:
> > 
> > Reviewed-by: Eduardo Lima Mitev 
> > 
> > > 
> > >   const nir_instr *parent_instr = instr->src[i].src.ssa-
> > > >parent_instr;
> > > 
> 
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Re: [Mesa-dev] [PATCH] radeonsi: clear DB_RENDER_OVERRIDE

[Nicolai Hähnle]

On 13.10.2016 18:54, Marek Olšák wrote:

From: Marek Olšák 

Vulkan doesn't set these fields even though it doesn't use HiS.
HiS is disabled by programming DB_SRESULTS_COMPARE_STATEn to 0.


This probably has no effect, but it makes sense to handle state more 
similar to Vulkan in general.


Reviewed-by: Nicolai Hähnle 


---
 src/gallium/drivers/radeonsi/si_state.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index b23749c..732f9e9 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3918,23 +3918,21 @@ static void si_init_config(struct si_context *sctx)
   S_028230_ER_LINE_LR(0x1A) |
   S_028230_ER_LINE_RL(0x26) |
   S_028230_ER_LINE_TB(0xA) |
   S_028230_ER_LINE_BT(0xA));
/* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
-   si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
-  S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
-  S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
+   si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);

si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);

if (sctx->b.chip_class >= CIK) {
si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, 
S_00B51C_CU_EN(0x));
si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, 
S_00B31C_CU_EN(0x));
si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, 
S_00B21C_CU_EN(0x));


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Re: [Mesa-dev] [PATCH v3 25/25] configure.ac: Add required LLVM versions to the top

[Michel Dänzer]

On 14/10/16 07:02 PM, Emil Velikov wrote:
> On 14 October 2016 at 09:45, Michel Dänzer  wrote:
>> On 14/10/16 05:14 PM, Emil Velikov wrote:
>>> On 14 October 2016 at 01:45, Michel Dänzer  wrote:
 On 13/10/16 07:14 PM, Emil Velikov wrote:
> On 13 October 2016 at 04:07, Michel Dänzer  wrote:
>> On 13/10/16 03:37 AM, Tobias Droste wrote:
>>> Am Mittwoch, 12. Oktober 2016, 11:53:50 CEST schrieb Emil Velikov:
>
> +LLVM_VERSION_REQUIRED_OPENCL=3.6.0
> +LLVM_VERSION_REQUIRED_R600=3.6.0
> +LLVM_VERSION_REQUIRED_RADEONSI=3.6.0

 There's a small related gotcha: as-is at build time we get the
 different codepaths thus, as people build against shared LLVM (hello
 Archlinux, I'm looking at you) and update their LLVM without
 rebuilding mesa (Arch I'm looking at you again) things go funny.
>>
>> What exactly happened there? LLVM upstream generates shared libraries
>> named libLLVM-..so*, so it shouldn't be possible for a
>> simple LLVM package update to break Mesa, unless Arch did something
>> really stupid.
>>
> The issue is not specific to Arch, but anyone who links against shared 
> LLVM.
>
> Here is another take on it:
> At least swr and r600/radeonsi depend at _build_ time on the _patch_
> version of LLVM. The latter of which is not part of the DSO name. Thus
> at runtime as you change your LLVM (3.9.x>3.9.y) you'll execute the
> "3.9.x" codepath even though you are be using "3.9.y" LLVM.

 That should be fine, since 3.9.y is backwards compatible with 3.9.x.

 Debian doesn't automatically recompile Mesa in such cases either, and I
 haven't seen any problems there because of that.

 So, what exactly was the problem?

>>> Just grep through for LLVM_.*PATCH and you'll see it. Portable code
>>> should not check that at compile time.
>>
>> This is getting a bit annoying... Please explicitly say what you think
>> is a problem, especially after being asked to do so multiple times.
>>
> AFAICT picking on like an old bat can be annoying, so I've tried to avoid it.
> Regardless, as per your request:

Thank you.


> * src/gallium/drivers/radeon/r600_pipe_common.c
> No actual bug, yet misleading.

If you want to call it that... I'd say this can be useful for detecting
the problems you're thinking of. :)


> * src/gallium/drivers/radeonsi/si_pipe.c
> Update to 3.6.2+, still missing tessellation unless you rebuild mesa.

Right, exactly the same as with static linking.

> The latter bug in itself.

Not sure what you mean by that.


> Downgrade - TBD, depending on the (fixed) LLVM bugs.

Building against one version of LLVM and then downgrading the shared
library to an older version is indeed the only case we're currently not
handling gracefully. It should be rather rare though.


> src/gallium/drivers/swr/rasterizer/jitter/scripts/gen_llvm_ir_macros.py
> Reversed argument order. No issues if the whole things gets inlined
> into mesa, fun experience otherwise.

If the newer LLVM version doesn't work with code compiled for the older
version, I'd consider that an LLVM bug.


> Using a runtime check for shared libs [...] the "better" choice, imho.

Right, that would probably be the best solution. Any volunteers to make
it happen?


> That or just bump the requirement ?

That wouldn't protect against the shared library being downgraded to an
older version.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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Re: [Mesa-dev] [PATCH] gallium/hud: Sensor extension is segfaulting.

[Nicolai Hähnle]

On 13.10.2016 19:29, Steven Toth wrote:

Round two of the patchset, incorporating feedback
from nhaeh...@gmail.com

The fixes in this set address bugfix #68169, HUD crashing
when testing with unigine (heaven).

The bug also manifested itself as a lack of data in
HUD charts when multiple instanced were created and
destroyed in a specific order, a use case not witnessed
with glxgears.

These patches:
1. mutex protect the internal object lists.
2. reference count object access for destruction purposes.

Patchset tested with glxgears/demo and unigine.

Signed-off-by: Steven Toth 
---
 src/gallium/auxiliary/hud/hud_cpufreq.c  | 33 ++
 src/gallium/auxiliary/hud/hud_diskstat.c | 39 ++
 src/gallium/auxiliary/hud/hud_nic.c  | 37 +
 src/gallium/auxiliary/hud/hud_sensors_temp.c | 41 ++--
 4 files changed, 125 insertions(+), 25 deletions(-)

diff --git a/src/gallium/auxiliary/hud/hud_cpufreq.c 
b/src/gallium/auxiliary/hud/hud_cpufreq.c
index 4501bbb..e193568 100644
--- a/src/gallium/auxiliary/hud/hud_cpufreq.c
+++ b/src/gallium/auxiliary/hud/hud_cpufreq.c
@@ -37,6 +37,8 @@
 #include "util/list.h"
 #include "os/os_time.h"
 #include "util/u_memory.h"
+#include "util/u_inlines.h"
+#include "os/os_thread.h"
 #include 
 #include 
 #include 
@@ -57,21 +59,28 @@ struct cpufreq_info
char sysfs_filename[128];
uint64_t KHz;
uint64_t last_time;
+   struct pipe_reference refcnt;
 };

 static int gcpufreq_count = 0;
 static struct list_head gcpufreq_list;
+static pipe_mutex gcpufreq_mutex;

 static struct cpufreq_info *
 find_cfi_by_index(int cpu_index, int mode)
 {
+   struct cpufreq_info *ret = 0;
+   pipe_mutex_lock(gcpufreq_mutex);
list_for_each_entry(struct cpufreq_info, cfi, &gcpufreq_list, list) {
   if (cfi->mode != mode)
  continue;
-  if (cfi->cpu_index == cpu_index)
- return cfi;
+  if (cfi->cpu_index == cpu_index) {
+ ret = cfi;
+ break;
+  }
}
-   return 0;
+   pipe_mutex_unlock(gcpufreq_mutex);
+   return ret;
 }

 static int
@@ -116,8 +125,14 @@ static void
 free_query_data(void *p)
 {
struct cpufreq_info *cfi = (struct cpufreq_info *)p;
-   list_del(&cfi->list);
-   FREE(cfi);
+   /* atomic dec */
+   if (pipe_reference(&cfi->refcnt, NULL)) {
+  pipe_mutex_lock(gcpufreq_mutex);
+  list_del(&cfi->list);
+  gcpufreq_count--;
+  pipe_mutex_unlock(gcpufreq_mutex);
+  FREE(cfi);
+   }
 }

 /**
@@ -159,6 +174,7 @@ hud_cpufreq_graph_install(struct hud_pane *pane, int 
cpu_index,
   return;
}

+   pipe_reference(NULL, &cfi->refcnt); /* atomic inc */


There is a race condition here where another thread frees cfi between 
the time that you took it from the linked list and this reference count 
increase.


Anyway, I'm sorry for not having looked more closely before, but the 
whole logic of the cpufreq_info life cycle feels a bit off to me right now.


It looks like you're trying to do a lazy one-time initialization of all 
cpufreq_info objects that are ever required in hud_get_num_cpufreq. 
That's fine as a pattern, but then you simply shouldn't ever free those 
objects in free_query_data.


You'd keep them around until program exit; they will appear in a leak 
check as "still reachable" (and that only if the HUD was used), which is 
fine in my book.


Then the only thing you need to mutex-protect is the initialization, to 
ensure that it happens exactly once and that nobody tries to 
find_cfi_index until the list is initialized.




gr->query_data = cfi;
gr->query_new_value = query_cfi_load;

@@ -180,8 +196,12 @@ add_object(const char *name, const char *fn, int objmode, 
int cpu_index)
strcpy(cfi->sysfs_filename, fn);
cfi->mode = objmode;
cfi->cpu_index = cpu_index;
+   pipe_reference_init(&cfi->refcnt, 1);
+
+   pipe_mutex_lock(gcpufreq_mutex);
list_addtail(&cfi->list, &gcpufreq_list);
gcpufreq_count++;
+   pipe_mutex_unlock(gcpufreq_mutex);
 }

 /**
@@ -205,6 +225,7 @@ hud_get_num_cpufreq(bool displayhelp)
/* Scan /sys/devices.../cpu, for every object type we support, create
 * and persist an object to represent its different metrics.
 */
+   pipe_mutex_init(gcpufreq_mutex);
list_inithead(&gcpufreq_list);
DIR *dir = opendir("/sys/devices/system/cpu");


There's a closedir missing.

I'm going to skip the other files because I believe they follow a 
similar pattern. Just one more thing: as it stands, the query_*_load 
functions will also go wonky when multiple contexts are actually used to 
show a HUD at the same time. I don't think it hurts the stability of the 
program, but it might lead to confusing output when the values of e.g. 
dsi->last_stat and dsi->last_time will interfere between multiple HUD 
contexts.


Nicolai
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Re: [Mesa-dev] [PATCH] radeonsi: shorten "shader->selector" to "sel" in si_shader_create

[Nicolai Hähnle]

Reviewed-by: Nicolai Hähnle 

On 13.10.2016 19:16, Marek Olšák wrote:

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_shader.c | 15 ---
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index b2d7699..e6edd90 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -7850,35 +7850,36 @@ static void si_fix_num_sgprs(struct si_shader *shader)
 {
unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */

shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
 }

 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
 struct si_shader *shader,
 struct pipe_debug_callback *debug)
 {
-   struct si_shader *mainp = shader->selector->main_shader_part;
+   struct si_shader_selector *sel = shader->selector;
+   struct si_shader *mainp = sel->main_shader_part;
int r;

/* LS, ES, VS are compiled on demand if the main part hasn't been
 * compiled for that stage.
 */
if (!mainp ||
-   (shader->selector->type == PIPE_SHADER_VERTEX &&
+   (sel->type == PIPE_SHADER_VERTEX &&
 (shader->key.vs.as_es != mainp->key.vs.as_es ||
  shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
-   (shader->selector->type == PIPE_SHADER_TESS_EVAL &&
+   (sel->type == PIPE_SHADER_TESS_EVAL &&
 shader->key.tes.as_es != mainp->key.tes.as_es) ||
-   (shader->selector->type == PIPE_SHADER_TESS_CTRL &&
+   (sel->type == PIPE_SHADER_TESS_CTRL &&
 shader->key.tcs.epilog.inputs_to_copy) ||
-   shader->selector->type == PIPE_SHADER_COMPUTE) {
+   sel->type == PIPE_SHADER_COMPUTE) {
/* Monolithic shader (compiled as a whole, has many variants,
 * may take a long time to compile).
 */
r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
if (r)
return r;
} else {
/* The shader consists of 2-3 parts:
 *
 * - the middle part is the user shader, it has 1 variant only
@@ -7898,21 +7899,21 @@ int si_shader_create(struct si_screen *sscreen, 
LLVMTargetMachineRef tm,
shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
memcpy(shader->info.vs_output_param_offset,
   mainp->info.vs_output_param_offset,
   sizeof(mainp->info.vs_output_param_offset));
shader->info.uses_instanceid = mainp->info.uses_instanceid;
shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
shader->info.nr_param_exports = mainp->info.nr_param_exports;

/* Select prologs and/or epilogs. */
-   switch (shader->selector->type) {
+   switch (sel->type) {
case PIPE_SHADER_VERTEX:
if (!si_shader_select_vs_parts(sscreen, tm, shader, 
debug))
return -1;
break;
case PIPE_SHADER_TESS_CTRL:
if (!si_shader_select_tcs_parts(sscreen, tm, shader, 
debug))
return -1;
break;
case PIPE_SHADER_TESS_EVAL:
if (!si_shader_select_tes_parts(sscreen, tm, shader, 
debug))
@@ -7939,21 +7940,21 @@ int si_shader_create(struct si_screen *sscreen, 
LLVMTargetMachineRef tm,
}
if (shader->epilog) {
shader->config.num_sgprs = 
MAX2(shader->config.num_sgprs,

shader->epilog->config.num_sgprs);
shader->config.num_vgprs = 
MAX2(shader->config.num_vgprs,

shader->epilog->config.num_vgprs);
}
}

si_fix_num_sgprs(shader);
-   si_shader_dump(sscreen, shader, debug, shader->selector->info.processor,
+   si_shader_dump(sscreen, shader, debug, sel->info.processor,
   stderr);

/* Upload. */
r = si_shader_binary_upload(sscreen, shader);
if (r) {
fprintf(stderr, "LLVM failed to upload shader\n");
return r;
}

return 0;


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Re: [Mesa-dev] [PATCH 1/6] util: add vector util code.

[Nicolai Hähnle]

On 14.10.2016 05:16, Dave Airlie wrote:

From: Dave Airlie 

This is ported from anv, both anv and radv can share this.

Signed-off-by: Dave Airlie 
---
 src/util/Makefile.sources |  4 +-
 src/util/u_vector.c   | 98 +++
 src/util/u_vector.h   | 85 
 3 files changed, 186 insertions(+), 1 deletion(-)
 create mode 100644 src/util/u_vector.c
 create mode 100644 src/util/u_vector.h

diff --git a/src/util/Makefile.sources b/src/util/Makefile.sources
index 8b17bcf..b7b1e91 100644
--- a/src/util/Makefile.sources
+++ b/src/util/Makefile.sources
@@ -35,7 +35,9 @@ MESA_UTIL_FILES :=\
strtod.h \
texcompress_rgtc_tmp.h \
u_atomic.h \
-   u_endian.h
+   u_endian.h \
+   u_vector.c \
+   u_vector.h

 MESA_UTIL_GENERATED_FILES = \
format_srgb.c

[snip]

diff --git a/src/util/u_vector.h b/src/util/u_vector.h
new file mode 100644
index 000..ea52837
--- /dev/null
+++ b/src/util/u_vector.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#ifndef U_VECTOR_H
+#define U_VECTOR_H
+
+#include 
+#include 
+#include "util/u_math.h"
+#include "util/macros.h"
+
+static inline uint32_t
+u_align_u32(uint32_t v, uint32_t a)
+{
+   assert(a != 0 && a == (a & -a));
+   return (v + a - 1) & ~(a - 1);
+}


This fits better in u_math.h

Nicolai


+
+struct u_vector {
+   uint32_t head;
+   uint32_t tail;
+   uint32_t element_size;
+   uint32_t size;
+   void *data;
+};
+
+int u_vector_init(struct u_vector *queue, uint32_t element_size, uint32_t 
size);
+void *u_vector_add(struct u_vector *queue);
+void *u_vector_remove(struct u_vector *queue);
+
+static inline int
+u_vector_length(struct u_vector *queue)
+{
+   return (queue->head - queue->tail) / queue->element_size;
+}
+
+static inline void *
+u_vector_head(struct u_vector *vector)
+{
+   assert(vector->tail < vector->head);
+   return (void *)((char *)vector->data +
+   ((vector->head - vector->element_size) &
+(vector->size - 1)));
+}
+
+static inline void *
+u_vector_tail(struct u_vector *vector)
+{
+   return (void *)((char *)vector->data + (vector->tail & (vector->size - 1)));
+}
+
+static inline void
+u_vector_finish(struct u_vector *queue)
+{
+   free(queue->data);
+}
+
+#define u_vector_foreach(elem, queue)  \
+   static_assert(__builtin_types_compatible_p(__typeof__(queue), struct u_vector *), 
""); \
+   for (uint32_t __u_vector_offset = (queue)->tail;
\
+elem = (queue)->data + (__u_vector_offset & ((queue)->size - 1)), 
__u_vector_offset < (queue)->head; \
+__u_vector_offset += (queue)->element_size)
+
+
+#endif
+


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Re: [Mesa-dev] [PATCH 4/6] util: move min/max/clamp macros to util macros.h

[Nicolai Hähnle]

Apart from the comment I sent on the first patch, patch 1&4 are

Reviewed-by: Nicolai Hähnle 

On 14.10.2016 05:16, Dave Airlie wrote:

From: Dave Airlie 

Although the vulkan drivers include mesa macros.h, for
radv I'd like to move away from that.

Signed-off-by: Dave Airlie 
---
 src/mesa/main/macros.h | 13 -
 src/util/macros.h  | 13 +
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/src/mesa/main/macros.h b/src/mesa/main/macros.h
index ed207d4..03a228b 100644
--- a/src/mesa/main/macros.h
+++ b/src/mesa/main/macros.h
@@ -660,19 +660,6 @@ INTERP_4F(GLfloat t, GLfloat dst[4], const GLfloat out[4], 
const GLfloat in[4])



-/** Clamp X to [MIN,MAX] */
-#define CLAMP( X, MIN, MAX )  ( (X)<(MIN) ? (MIN) : ((X)>(MAX) ? (MAX) : (X)) )
-
-/** Minimum of two values: */
-#define MIN2( A, B )   ( (A)<(B) ? (A) : (B) )
-
-/** Maximum of two values: */
-#define MAX2( A, B )   ( (A)>(B) ? (A) : (B) )
-
-/** Minimum and maximum of three values: */
-#define MIN3( A, B, C ) ((A) < (B) ? MIN2(A, C) : MIN2(B, C))
-#define MAX3( A, B, C ) ((A) > (B) ? MAX2(A, C) : MAX2(B, C))
-
 static inline unsigned
 minify(unsigned value, unsigned levels)
 {
diff --git a/src/util/macros.h b/src/util/macros.h
index 9dea2a0..27d1b62 100644
--- a/src/util/macros.h
+++ b/src/util/macros.h
@@ -229,4 +229,17 @@ do {   \
 /** Compute ceiling of integer quotient of A divided by B. */
 #define DIV_ROUND_UP( A, B )  ( (A) % (B) == 0 ? (A)/(B) : (A)/(B)+1 )

+/** Clamp X to [MIN,MAX] */
+#define CLAMP( X, MIN, MAX )  ( (X)<(MIN) ? (MIN) : ((X)>(MAX) ? (MAX) : (X)) )
+
+/** Minimum of two values: */
+#define MIN2( A, B )   ( (A)<(B) ? (A) : (B) )
+
+/** Maximum of two values: */
+#define MAX2( A, B )   ( (A)>(B) ? (A) : (B) )
+
+/** Minimum and maximum of three values: */
+#define MIN3( A, B, C ) ((A) < (B) ? MIN2(A, C) : MIN2(B, C))
+#define MAX3( A, B, C ) ((A) > (B) ? MAX2(A, C) : MAX2(B, C))
+
 #endif /* UTIL_MACROS_H */


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[Mesa-dev] [PATCH] i965/fs/nir: fix double pack from previous unpack optimization

[Iago Toral Quiroga]

It seems I initially wrote this as:

if (cond_for_opt) {
  
}

and then I modified the style at some point to be like:

if (!cond_for_opt)
   continue;


But I did not re-write all the conditions accordingly.
---

I tested this quickly on a haswell with our fp64 branch and it did not
show any regressions. I verified the optimization was being triggered
(it kicked in for 210 out of 1303 shader tests, which includes vec4 tests,
so it kicks in a lot).

I also noticed that at least in a couple of cases that I inspected manually,
copy propagation was able to achieve the same result, making this opt
unnecessary, but that might not always work out, since removing the same
optimization for the unpack from previous pack case led to worse code in the
cases that I inspected manually, so I guess we should keep both optimizations
for now.

 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 4e68ffb..6307b5c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -1208,16 +1208,16 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, 
nir_alu_instr *instr)
* the unpack operation.
*/
   for (int i = 0; i < 2; i++) {
- if (instr->src[i].src.is_ssa)
+ if (!instr->src[i].src.is_ssa)
 continue;
 
  const nir_instr *parent_instr = instr->src[i].src.ssa->parent_instr;
- if (parent_instr->type == nir_instr_type_alu)
+ if (parent_instr->type != nir_instr_type_alu)
 continue;
 
  const nir_alu_instr *alu_parent = nir_instr_as_alu(parent_instr);
- if (alu_parent->op == nir_op_unpack_double_2x32_split_x ||
- alu_parent->op == nir_op_unpack_double_2x32_split_y)
+ if (alu_parent->op != nir_op_unpack_double_2x32_split_x &&
+ alu_parent->op != nir_op_unpack_double_2x32_split_y)
 continue;
 
  if (!alu_parent->src[0].src.is_ssa)
-- 
2.7.4

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[Mesa-dev] [Bug 98275] Segmentation fault when using VAAPI acceleration in VLC after installing oibaf's optimized drivers

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98275

--- Comment #1 from Nicolai Hähnle  ---
Could you please provide a backtrace of the crash? (Make sure that debug symbol
packages are installed.)

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Re: [Mesa-dev] anv/radv: WSI sharing code

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan 

On 10/17/2016 03:24 PM, Dave Airlie wrote:
> This series builds on top of the previous sharing patches I sent.
> 
> The aim here is to share the X11 and wayland WSI code between
> the two vulkan drivers so we have a consistent implementation and
> one place to fix bugs.
> 
> The series modifies the anv code in place until it's suitable
> for sharing, then it moves it to shared directory, and ports
> radv to use it.
> 
> The final code leaves the WSI APIs in the drivers, but they
> call directly into the shared code once they shed their driver
> specific structs, and pick a pAllocator.
> 
> Dave.
> 
> ___
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> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> 



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[Mesa-dev] [Bug 98172] Concurrent call to glClientWaitSync results in segfault in one of the waiters.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98172

--- Comment #19 from Michel Dänzer  ---
(In reply to shinji.suzuki from comment #16)
> Created attachment 127317 [details] [review]
> Arbitration on so->fence through per sync-object mutex.

One minor comment below, otherwise looks good to me. Feel free to submit the
patch generated by git format-patch to the mesa-dev mailing list for review.


+   if (type == GL_SYNC_FENCE) {
+  struct st_sync_object * so = 
+ (struct st_sync_object*)CALLOC_STRUCT(st_sync_object);
+  mtx_init(&so->mtx, mtx_plain);
+  return (struct gl_sync_object *)so;
+   } else
   return NULL;

This can be written as:

   if (type == GL_SYNC_FENCE) {
  [...]
   }

   return NULL;

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Re: [Mesa-dev] [PATCH 09/10] st/vdpau: implement the new DMA-buf based interop

[Marek Olšák]

Reverting the whole commit is too much. You can just remove the PIPE BIND
SHARED usage if you need to.

Marek

On Oct 17, 2016 6:43 AM, "Ilia Mirkin"  wrote:

> On Thu, Sep 15, 2016 at 4:54 PM, Marek Olšák  wrote:
> > On Thu, Sep 15, 2016 at 5:14 AM, Dave Airlie  wrote:
> >> On 15 September 2016 at 13:03, Ilia Mirkin 
> wrote:
> >>> On Wed, Sep 14, 2016 at 10:15 PM, Michel Dänzer 
> wrote:
> > No, the current impl is pretty radeon-specific (note - it doesn't
> work
> > on nouveau, and no other drivers support the interfaces, so ... it's
> > radeon-specific).
> 
>  We're getting into semantics here, but since the reason it doesn't
> work
>  well with nouveau is a fundamental issue in nouveau (which should also
>  affect at least DRI3 in general), while you may call it "de facto
> radeon
>  specific" if you're so inclined, that doesn't make the implementation
>  actually radeon specific.
> >>>
> >>> No one's reported any issues with DRI3, I use it on my home desktop
> >>> every day. And VDPAU used to work great until these changes to
> >>> st/vdpau went in. Prior to those changes in st/vdpau, saying that
> >>> "shared == gart" was a perfectly reasonable thing to say, since no one
> >>> tried blending/readback on those surfaces (or at least not enough for
> >>> it to matter). But now ... poof ... it doesn't work [actually, worse -
> >>> it works - but can't come close to keeping up with 24fps video].
> >>>
> >>> Anyways, I realize this is a losing argument. Interfaces and usages
> >>> move forward and change over time. This happens to be a change that
> >>> leaves nouveau behind. As a spare-time contributor, I can't keep up
> >>> with multiple full timers. I had hoped that there'd be some way to
> >>> make it all still work, but that doesn't seem to be the case.
> >>> Unfortunately end users are going to lose out on functionality as a
> >>> result.
> >>
> >> So (a) this is a regression, regressions aren't allowed, so it would
> >> be good to back the change out until it can be fixed.
> >>
> >> The problem is the combo of LINEAR and SHARED means that
> >> GART placement is most likely, radeon should be doing the same
> >> in most circumstances.
> >>
> >> We should possible introduced SHARED_OTHER_GPU maybe
> >> and use that throughout the stack where it matters.
> >
> > The main problem is that nouveau lacks a proper memory management and
> > buffers are pinned after allocation forever.
> >
> > The workaround is to add PIPE_BIND_something, which would do what you
> > need it to do, and use it where you need to use it. I don't care about
> > the name as long as it works for nouveau. Does that sound reasonable?
>
> I don't really care how it's resolved, but the current situation is
> unacceptable.
>
>  - Reverting definitely works.
>  - Dropping libvdpau_nouveau definitely works.
>  - Adding a new flag may work, depends on details, would require a
> bunch of testing.
>
> Dave sent a patch for the first, I've sent a patch for the second. I
> don't think a patch for the third has materialized.
>
>   -ilia
>
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Re: [Mesa-dev] [PATCH] egl/dri2: add a libname to dlopen for OpenBSD

[Eric Engestrom]

On Sunday, 2016-10-16 16:38:35 +1100, Jonathan Gray wrote:
> On OpenBSD try to dlopen 'libglapi.so', ld.so will find
> the highest major/minor version and open it in this case.
> 
> Avoids '#error Unknown glapi provider for this platform' at build time.
> 
> Signed-off-by: Jonathan Gray 

LGTM, and I guess the other *BSD will want the same since 7a9c92d0 broke
them too.

Fixes: 7a9c92d071d010066349 ("egl/dri2: non-shared glapi cleanups")
Reviewed-by: Eric Engestrom 

Side note, I don't understand why we hardcode the version everywhere
(except Android). I can see it's been like that since that code was
added nearly 6 years ago (218381d9), but I couldn't find an explanation
in the logs, or any mention of it in the thread I found [1].
Emil, do you know?

[1] https://lists.freedesktop.org/archives/mesa-dev/2010-December/004476.html

> ---
>  src/egl/drivers/dri2/egl_dri2.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
> index 8785e31..9655a49 100644
> --- a/src/egl/drivers/dri2/egl_dri2.c
> +++ b/src/egl/drivers/dri2/egl_dri2.c
> @@ -2802,7 +2802,7 @@ static EGLBoolean
>  dri2_load(_EGLDriver *drv)
>  {
> struct dri2_egl_driver *dri2_drv = dri2_egl_driver(drv);
> -#ifdef HAVE_ANDROID_PLATFORM
> +#if defined(HAVE_ANDROID_PLATFORM) || defined(__OpenBSD__)
> const char *libname = "libglapi.so";
>  #elif defined(__APPLE__)
> const char *libname = "libglapi.0.dylib";
> -- 
> 2.9.3
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Re: [Mesa-dev] [PATCH] egl: remove docs directory from EXTRA_DIST

[Eric Engestrom]

On Sunday, 2016-10-16 21:06:25 +1100, Jonathan Gray wrote:
> The egl docs directory no longer exists as of
> 88b5c36fe1a1546bf633ee161a6715efc593acbd.
> 
> Remove it from EXTRA_DIST to unbreak 'make dist'
> 
> Signed-off-by: Jonathan Gray 

Reviewed-by: Eric Engestrom 
Tested-by: Eric Engestrom 

> ---
>  src/egl/Makefile.am | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am
> index 95ee6cc..304b0d3 100644
> --- a/src/egl/Makefile.am
> +++ b/src/egl/Makefile.am
> @@ -132,6 +132,5 @@ EXTRA_DIST = \
>   egl-symbols-check \
>   SConscript \
>   drivers/haiku \
> - docs \
>   main/egl.def \
>   main/README.txt
> -- 
> 2.9.3
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[Mesa-dev] [PATCH mesa] gbm: add a couple missing includes

[Eric Engestrom]

Needed for memset() and drmIoctl().

Signed-off-by: Eric Engestrom 
---
 src/gbm/backends/dri/gbm_driint.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gbm/backends/dri/gbm_driint.h 
b/src/gbm/backends/dri/gbm_driint.h
index 1644fac..26376ef 100644
--- a/src/gbm/backends/dri/gbm_driint.h
+++ b/src/gbm/backends/dri/gbm_driint.h
@@ -28,6 +28,8 @@
 #ifndef _GBM_DRI_INTERNAL_H_
 #define _GBM_DRI_INTERNAL_H_
 
+#include 
+#include 
 #include 
 #include "gbmint.h"
 #include "c11/threads.h"
-- 
Cheers,
  Eric

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Re: [Mesa-dev] [PATCH mesa] gbm: add a couple missing includes

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan 

On 10/17/2016 09:39 PM, Eric Engestrom wrote:
> Needed for memset() and drmIoctl().
> 
> Signed-off-by: Eric Engestrom 
> ---
>  src/gbm/backends/dri/gbm_driint.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/src/gbm/backends/dri/gbm_driint.h 
> b/src/gbm/backends/dri/gbm_driint.h
> index 1644fac..26376ef 100644
> --- a/src/gbm/backends/dri/gbm_driint.h
> +++ b/src/gbm/backends/dri/gbm_driint.h
> @@ -28,6 +28,8 @@
>  #ifndef _GBM_DRI_INTERNAL_H_
>  #define _GBM_DRI_INTERNAL_H_
>  
> +#include 
> +#include 
>  #include 
>  #include "gbmint.h"
>  #include "c11/threads.h"
> 



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[Mesa-dev] [Bug 98281] 'message's in ctx->Debug.LogMessages[] seem to leak.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98281

--- Comment #2 from shinji.suz...@gmail.com ---
The amount of memory being in use may be bounded. But I believe there are
blocks that don't get released until process termination. Having unreleased
memory brings bad user experience to users of valgrind or any kind of memory
debugging tools.

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Re: [Mesa-dev] [PATCH] egl/android: fix error in droid_add_configs_for_visuals()

[Eric Engestrom]

On Monday, 2016-10-17 09:04:56 +0300, Tapani Pälli wrote:
> This was some kind of leftover in commit acd35c8 and format_count
> array variable (declared in outer scope) should be used instead.
> 
> Signed-off-by: Tapani Pälli 

Fixes: acd35c8758dc73240903 ("egl/android: tweak 
droid_add_configs_for_visuals()")
Reviewed-by: Eric Engestrom 

> ---
>  src/egl/drivers/dri2/platform_android.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/src/egl/drivers/dri2/platform_android.c 
> b/src/egl/drivers/dri2/platform_android.c
> index 6a4122a..6a110e2 100644
> --- a/src/egl/drivers/dri2/platform_android.c
> +++ b/src/egl/drivers/dri2/platform_android.c
> @@ -787,8 +787,6 @@ droid_add_configs_for_visuals(_EGLDriver *drv, 
> _EGLDisplay *dpy)
>   continue;
>  
>for (j = 0; j < ARRAY_SIZE(visuals); j++) {
> - int format_count = 0;
> -
>   config_attrs[1] = visuals[j].format;
>   config_attrs[3] = visuals[j].format;
>  
> -- 
> 2.7.4
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Re: [Mesa-dev] [PATCH] egl/android: fix error in droid_add_configs_for_visuals()

[Emil Velikov]

On 17 October 2016 at 07:04, Tapani Pälli  wrote:
> This was some kind of leftover in commit acd35c8 and format_count
> array variable (declared in outer scope) should be used instead.
>
Which brings the question - do we want to enable -Wshadow for the C
sources. The C++ ones [used to] produce too much noise so they're out
of the question.

Either way, r-b and pushed to master.

Thanks
Emil
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Re: [Mesa-dev] [PATCH v2] egl/wayland: Avoid race conditions when on non-main thread

[Emil Velikov]

On 16 October 2016 at 14:55, Daniel Stone  wrote:

> With those fixed, assuming we're fine with an increased hard dep:
Wayland 1.11 has been out for a 3+ months so it's perfectly reasonable imho.

-Emil
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Re: [Mesa-dev] [PATCH] st/nine: Fix multisample limit check

[Emil Velikov]

On 16 October 2016 at 23:06, Axel Davy  wrote:
> I've pushed this just now to be sure it makes it for mesa 13.
>
Which reminds me that I should beat up our existing
get-extra-pick-list.sh to track the offending SHA through the branch
and "nominate" the fix. Currently if only checks if the SHA has been
cherry-picked to the branch.

-Emil
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Re: [Mesa-dev] [PATCH v2 05/16] loader: reimplement loader_get_user_preferred_fd via libdrm

[Emil Velikov]

On 15 October 2016 at 08:59, Axel Davy  wrote:
> On 14/10/2016 22:33, Emil Velikov wrote:
>>
>> On 14 October 2016 at 20:21, Axel Davy  wrote:
>>
>>> The code looks good. With the minor nitpick fixed, this patch is:
>>> Reviewed-by: Axel Davy 
>>>
>> Thanks. If you can skim through any of the other patches that'll be
>> appreciated.
>> Emil
>>
> I've looked through the entire serie, and the patches look good to me
> (except the small typo in the commit title of the 11th patch). You can add
> my r-b.
>
Thanks !
Emil
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Re: [Mesa-dev] [PATCH] egl/dri2: add a libname to dlopen for OpenBSD

[Emil Velikov]

On 17 October 2016 at 10:53, Eric Engestrom  wrote:
> On Sunday, 2016-10-16 16:38:35 +1100, Jonathan Gray wrote:
>> On OpenBSD try to dlopen 'libglapi.so', ld.so will find
>> the highest major/minor version and open it in this case.
>>
>> Avoids '#error Unknown glapi provider for this platform' at build time.
>>
>> Signed-off-by: Jonathan Gray 
>
> LGTM, and I guess the other *BSD will want the same since 7a9c92d0 broke
> them too.
>
I'm not 100% sure about that. OpenBSD (unlike other BSD) did bump the
major when the ABI breaks due to 'internal' changes - think of
off_t/time_t on 32 vs 64bit systems and alike.

Unlike Linux kernel/distros, BSDs tend to be more relaxed when in
comes to ABI, I believe. Don't quote me on that one ;-)

> Fixes: 7a9c92d071d010066349 ("egl/dri2: non-shared glapi cleanups")
> Reviewed-by: Eric Engestrom 
>
> Side note, I don't understand why we hardcode the version everywhere
> (except Android). I can see it's been like that since that code was
> added nearly 6 years ago (218381d9), but I couldn't find an explanation
> in the logs, or any mention of it in the thread I found [1].
> Emil, do you know?
>
The ABI must be stable. Since a) we (and linux distros in general)
have the greater flexibility to "mix and match" components and b)
glapi is/was used by xserver as well, the initial goal was that the
ABI should not break, ever. See some the src/mapi changes by Brian
Paul, which rework the nop calls due to different calling convention
and stack corruption on Windows and the follow up fix to keep those
Windows only and stable for everyone else
be71bbfaa2ad201b570b56847a13328fc359d0ee.

Emil
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Re: [Mesa-dev] [PATCH] egl/dri2: add a libname to dlopen for OpenBSD

[Jonathan Gray]

On Mon, Oct 17, 2016 at 12:39:11PM +0100, Emil Velikov wrote:
> On 17 October 2016 at 10:53, Eric Engestrom  wrote:
> > On Sunday, 2016-10-16 16:38:35 +1100, Jonathan Gray wrote:
> >> On OpenBSD try to dlopen 'libglapi.so', ld.so will find
> >> the highest major/minor version and open it in this case.
> >>
> >> Avoids '#error Unknown glapi provider for this platform' at build time.
> >>
> >> Signed-off-by: Jonathan Gray 
> >
> > LGTM, and I guess the other *BSD will want the same since 7a9c92d0 broke
> > them too.
> >
> I'm not 100% sure about that. OpenBSD (unlike other BSD) did bump the
> major when the ABI breaks due to 'internal' changes - think of
> off_t/time_t on 32 vs 64bit systems and alike.
> 
> Unlike Linux kernel/distros, BSDs tend to be more relaxed when in
> comes to ABI, I believe. Don't quote me on that one ;-)

OpenBSD tends to favour simplified interfaces over backwards compatiblity
and is more like a research system in that respect.  As the kernel
and userland are one source tree ioctl compat largely doesn't exist.
System calls get deprecated and removed over the course of a few releases.
So we didn't go through the pain of duplicated systems calls for off_t
as mentioned, and don't go in for symbol versioning.  Just major.minor
library versioning, which is roughly symbol removals, major crank,
symbol additions minor crank.

I believe FreeBSD tends to go in for backwards compatibility more
but am not familiar with the details.  They also have a different ld.so.

Perhaps an else case for 'libglapi.so.0' would be appropriate for all
the other various unices instead of the #error ?

> 
> > Fixes: 7a9c92d071d010066349 ("egl/dri2: non-shared glapi cleanups")
> > Reviewed-by: Eric Engestrom 
> >
> > Side note, I don't understand why we hardcode the version everywhere
> > (except Android). I can see it's been like that since that code was
> > added nearly 6 years ago (218381d9), but I couldn't find an explanation
> > in the logs, or any mention of it in the thread I found [1].
> > Emil, do you know?
> >
> The ABI must be stable. Since a) we (and linux distros in general)
> have the greater flexibility to "mix and match" components and b)
> glapi is/was used by xserver as well, the initial goal was that the
> ABI should not break, ever. See some the src/mapi changes by Brian
> Paul, which rework the nop calls due to different calling convention
> and stack corruption on Windows and the follow up fix to keep those
> Windows only and stable for everyone else
> be71bbfaa2ad201b570b56847a13328fc359d0ee.
> 
> Emil
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[Mesa-dev] [Bug 98271] [radeonsi]Playing videos with vdpau or vaapi hardware acceleration crashes my pc

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98271

--- Comment #2 from Christian König  ---
(In reply to John from comment #1)
> I may have the same problem, and I know how to trigger it *easily*:

Thanks, that is a very valuable information. Going to try to reproduce this,
cause previously that sounded like a bug we will never get a grip on.

> Since snpidek gave an entry point, I guess we should try bisecting this.

Yeah, completely agree. If you can reproduce it more or less reliable please
try to bisect the issue between 11.2.2-1 and 12.0.3.

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[Mesa-dev] [Bug 98279] [vulkan/radeon] dota2 -vulkan hangs the GPU on R9-390

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98279

Emil Velikov  changed:

   What|Removed |Added

 CC|emil.l.veli...@gmail.com|

--- Comment #1 from Emil Velikov  ---
Jan, I'm not working on radv, so not sure how I can help here. Dropping myself
from the CC list.

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[Mesa-dev] [Bug 98281] 'message's in ctx->Debug.LogMessages[] seem to leak.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98281

--- Comment #3 from Emil Velikov  ---
Of the top of my head, it sounds like one is using PushDebugGroup without a
corresponding Pop.

Can you attach a simple program which reproduces this ? Ideally one which does
not depend on glew, in order to isolate a problem with it.

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[Mesa-dev] [Bug 98279] [vulkan/radeon] dota2 -vulkan hangs the GPU on R9-390

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98279

--- Comment #2 from Jan Ziak <0xe2.0x9a.0...@gmail.com> ---
(In reply to Emil Velikov from comment #1)
> Jan, I'm not working on radv, so not sure how I can help here. Dropping
> myself from the CC list.

Ok. I found your name in
https://cgit.freedesktop.org/mesa/mesa/commit/?id=3fd0cafc1c04b35707e9f862d07edd0599fe18fa
when I was adding people to the CC list.

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Re: [Mesa-dev] [PACH v2] glsl: SSBO unsized array declarations, if present, must be declared last

[Iago Toral]

On Sun, 2016-10-16 at 17:00 +1100, Timothy Arceri wrote:
> On Fri, 2016-10-14 at 14:30 +0200, Iago Toral Quiroga wrote:
> > 
> > From the ARB_shader_storage_buffer_object spec:
> > 
> > "In a shader storage block, the last member may be declared without
> > an explicit
> >  size.  In this case, the effective array size is inferred at run-
> > time from
> >  the size of the data store backing the interface block.  Such
> > unsized
> >  arrays may be indexed with general integer expressions, but may
> > not
> > be
> >  passed as an argument to a function or indexed with a negative
> > constant
> >  expression."
> > 
> > dEQP tests that SSBOs that declare field members after an unsized
> > array
> > declaration fail to compile.
> > 
> > Fixes the remaining subcase of the following dEQP tests:
> > dEQP-
> > GLES31.functional.debug.negative_coverage.callbacks.shader.compile_
> > co
> > mpute_shader
> > dEQP-
> > GLES31.functional.debug.negative_coverage.get_error.shader.compile_
> > co
> > mpute_shader
> > dEQP-
> > GLES31.functional.debug.negative_coverage.log.shader.compile_comput
> > e_
> > shader
> > 
> > v2: only update has_unsized_array while we have not found a
> > previous
> > unsized
> > array declaration.
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98132
> > ---
> >  src/compiler/glsl/ast_to_hir.cpp | 8 
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git a/src/compiler/glsl/ast_to_hir.cpp
> > b/src/compiler/glsl/ast_to_hir.cpp
> > index c3c8cef..462838a 100644
> > --- a/src/compiler/glsl/ast_to_hir.cpp
> > +++ b/src/compiler/glsl/ast_to_hir.cpp
> > @@ -6645,6 +6645,7 @@
> > ast_process_struct_or_iface_block_members(exec_list *instructions,
> >  
> > bool first_member = true;
> > bool first_member_has_explicit_location = false;
> > +   bool has_unsized_array = false;
> >  
> > unsigned i = 0;
> > foreach_list_typed (ast_declarator_list, decl_list, link,
> > declarations) {
> > @@ -6840,6 +6841,13 @@
> > ast_process_struct_or_iface_block_members(exec_list *instructions,
> >  
> >   const struct glsl_type *field_type =
> >  process_array_type(&loc, decl_type, decl-
> > > 
> > > array_specifier, state);
> > +
> > + if (has_unsized_array && var_mode ==
> > ir_var_shader_storage)
> > +_mesa_glsl_error(&loc, state, "SSBO member declared "
> > + "after unsized array.");
> > + else if (!has_unsized_array)
> > +has_unsized_array = field_type->is_unsized_array();
> > +
> I suspect this fixes named ifc blocks? There is code to detect these
> for unnamed ifc blocks and an is_unsized_array_last_element()
> function.

No, the dEQP test case is not a named interface block.

> I think you want to merge to code from the two of these checks (I
> think
> here is the correct spot) and probably remove
> the is_unsized_array_last_element() helper.

I have been looking into this and the problem seems to be more complex:

The problem with that code is that it is not handling this case, it is
simply producing an error for any unsized array that is not in an SSBO,
but it is not doing anything if the array is in an SSBO. It looks like
Dave changed this and moved the ssbo check to the linker instead
because the desktop spec allows to use unsized arrays that are not last
if the unsized array is implicitly sized. See 5b2675093e863a52.

With this we should be producing an error, but we do it at link time,
not at compile time, which is what dEQP expects. I have been discussing
this with Samuel and the relevant aspect of the spec is this:

"Except for the last declared member of a shader storage block (section
4.3.9 “Interface Blocks”), the size of an array must be declared
(explicitly sized) before it is indexed with anything other than an
integral constant expression. (...) Violation of any of these rules
result in compile-time errors."

So according to this a shader that declares an unsized array and never
uses it (which is the case of this dEQP test), is fine, because we
never try to index it. That would mean that the dEQP test is actually
bogus as is, since it has an empty main function. That said, if the
array is used, is not implicitly sized and is not the last member of
the ssbo, then spec would expect a compile-time error instead of a
link-time error.

I'll see if I can write a patch for this.

> > 
> >   validate_array_dimensions(field_type, state, &loc);
> >   fields[i].type = field_type;
> >   fields[i].name = decl->identifier;
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[Mesa-dev] [PATCH 11/14] glsl_to_tgsi: remove code for fixing up TGSI labels

[Marek Olšák]

From: Marek Olšák 

I don't know what this was supposed to do, but all TGSI labels were
always 0.
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 92 +-
 1 file changed, 2 insertions(+), 90 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 293654c..65db521 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -5096,24 +5096,20 @@ glsl_to_tgsi_visitor::renumber_registers(void)
   new_index++;
}
 
rename_temp_registers(num_renames, renames);
this->next_temp = new_index;
ralloc_free(renames);
ralloc_free(first_reads);
 }
 
 /* - TGSI conversion stuff -- 
*/
-struct label {
-   unsigned branch_target;
-   unsigned token;
-};
 
 /**
  * Intermediate state used during shader translation.
  */
 struct st_translate {
struct ureg_program *ureg;
 
unsigned temps_size;
struct ureg_dst *temps;
 
@@ -5133,39 +5129,21 @@ struct st_translate {
struct ureg_src shared_memory;
unsigned *array_sizes;
struct inout_decl *input_decls;
unsigned num_input_decls;
struct inout_decl *output_decls;
unsigned num_output_decls;
 
const GLuint *inputMapping;
const GLuint *outputMapping;
 
-   /* For every instruction that contains a label, keep
-* details so that we can go back afterwards and emit the correct
-* tgsi instruction number for each label.
-*/
-   struct label *labels;
-   unsigned labels_size;
-   unsigned labels_count;
-
-   /* Keep a record of the tgsi instruction number that each mesa
-* instruction starts at, will be used to fix up labels after
-* translation.
-*/
-   unsigned *insn;
-   unsigned insn_size;
-   unsigned insn_count;
-
unsigned procType;  /**< PIPE_SHADER_VERTEX/FRAGMENT */
-
-   boolean error;
 };
 
 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
 unsigned
 _mesa_sysval_to_semantic(unsigned sysval)
 {
switch (sysval) {
/* Vertex shader */
case SYSTEM_VALUE_VERTEX_ID:
   return TGSI_SEMANTIC_VERTEXID;
@@ -5223,67 +5201,20 @@ _mesa_sysval_to_semantic(unsigned sysval)
/* Unhandled */
case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX:
case SYSTEM_VALUE_GLOBAL_INVOCATION_ID:
case SYSTEM_VALUE_VERTEX_CNT:
default:
   assert(!"Unexpected SYSTEM_VALUE_ enum");
   return TGSI_SEMANTIC_COUNT;
}
 }
 
-
-/**
- * Make note of a branch to a label in the TGSI code.
- * After we've emitted all instructions, we'll go over the list
- * of labels built here and patch the TGSI code with the actual
- * location of each label.
- */
-static unsigned *get_label(struct st_translate *t, unsigned branch_target)
-{
-   unsigned i;
-
-   if (t->labels_count + 1 >= t->labels_size) {
-  t->labels_size = 1 << (util_logbase2(t->labels_size) + 1);
-  t->labels = (struct label *)realloc(t->labels,
-  t->labels_size * sizeof(struct 
label));
-  if (t->labels == NULL) {
- static unsigned dummy;
- t->error = TRUE;
- return &dummy;
-  }
-   }
-
-   i = t->labels_count++;
-   t->labels[i].branch_target = branch_target;
-   return &t->labels[i].token;
-}
-
-/**
- * Called prior to emitting the TGSI code for each instruction.
- * Allocate additional space for instructions if needed.
- * Update the insn[] array so the next glsl_to_tgsi_instruction points to
- * the next TGSI instruction.
- */
-static void set_insn_start(struct st_translate *t, unsigned start)
-{
-   if (t->insn_count + 1 >= t->insn_size) {
-  t->insn_size = 1 << (util_logbase2(t->insn_size) + 1);
-  t->insn = (unsigned *)realloc(t->insn, t->insn_size * 
sizeof(t->insn[0]));
-  if (t->insn == NULL) {
- t->error = TRUE;
- return;
-  }
-   }
-
-   t->insn[t->insn_count++] = start;
-}
-
 /**
  * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
  */
 static struct ureg_src
 emit_immediate(struct st_translate *t,
gl_constant_value values[4],
int type, int size)
 {
struct ureg_program *ureg = t->ureg;
 
@@ -5570,24 +5501,21 @@ compile_tgsi_instruction(struct st_translate *t,
for (i = 0; i < num_src; i++)
   src[i] = translate_src(t, &inst->src[i]);
 
switch(inst->op) {
case TGSI_OPCODE_BGNLOOP:
case TGSI_OPCODE_ELSE:
case TGSI_OPCODE_ENDLOOP:
case TGSI_OPCODE_IF:
case TGSI_OPCODE_UIF:
   assert(num_dst == 0);
-  ureg_label_insn(ureg,
-  inst->op,
-  src, num_src,
-  get_label(t, 0));
+  ureg_insn(ureg, inst->op, NULL, 0, src, num_src);
   return;
 
case TGSI_OPCODE_TEX:
case TGSI_OPCODE_TXB:
case TGSI_OPCODE_TXD:
case TGSI_OPCODE_TXL:
case TGSI_OPCODE_TXP:
case TGSI_OPCODE_TXQ:
case TGSI_OPCODE_TXQS:
case TGSI_OPCODE_TXF:
@@ -6300,31 +6228,22 @@ st_translate_

[Mesa-dev] [PATCH 14/14] mesa: remove gl_shader_compiler_options::EmitNoNoise

[Marek Olšák]

From: Marek Olšák 

it's always true
---
 src/mesa/drivers/dri/i915/i915_context.c | 1 -
 src/mesa/drivers/dri/i965/brw_compiler.c | 1 -
 src/mesa/main/mtypes.h   | 1 -
 src/mesa/program/ir_to_mesa.cpp  | 3 +--
 src/mesa/state_tracker/st_extensions.c   | 2 --
 5 files changed, 1 insertion(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i915_context.c 
b/src/mesa/drivers/dri/i915/i915_context.c
index a7604a1..05a2ad1 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -253,21 +253,20 @@ i915CreateContext(int api,
 
/* FINISHME: Are there other options that should be enabled for software
 * FINISHME: vertex shaders?
 */
ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].EmitNoIndirectSampler =
   true;
 
struct gl_shader_compiler_options *const fs_options =
   & ctx->Const.ShaderCompilerOptions[MESA_SHADER_FRAGMENT];
fs_options->MaxIfDepth = 0;
-   fs_options->EmitNoNoise = true;
fs_options->EmitNoPow = true;
fs_options->EmitNoIndirectInput = true;
fs_options->EmitNoIndirectOutput = true;
fs_options->EmitNoIndirectUniform = true;
fs_options->EmitNoIndirectTemp = true;
fs_options->EmitNoIndirectSampler = true;
 
ctx->Const.MaxDrawBuffers = 1;
ctx->Const.QueryCounterBits.SamplesPassed = 0;
 
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.c 
b/src/mesa/drivers/dri/i965/brw_compiler.c
index 27cbd40..4fcc51b 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.c
+++ b/src/mesa/drivers/dri/i965/brw_compiler.c
@@ -116,21 +116,20 @@ brw_compiler_create(void *mem_ctx, const struct 
gen_device_info *devinfo)
   devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
 
/* We want the GLSL compiler to emit code that uses condition codes */
for (int i = 0; i < MESA_SHADER_STAGES; i++) {
   compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
   compiler->glsl_compiler_options[i].MaxIfDepth =
  devinfo->gen < 6 ? 16 : UINT_MAX;
 
-  compiler->glsl_compiler_options[i].EmitNoNoise = true;
   compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
   compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
   compiler->glsl_compiler_options[i].LowerCombinedClipCullDistance = true;
 
   bool is_scalar = compiler->scalar_stage[i];
 
   compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
   compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
   compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 701f055..f2ecd6e 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2990,21 +2990,20 @@ struct gl_pipeline_shader_state
 };
 
 /**
  * Compiler options for a single GLSL shaders type
  */
 struct gl_shader_compiler_options
 {
/** Driver-selectable options: */
GLboolean EmitNoLoops;
GLboolean EmitNoCont;  /**< Emit CONT opcode? */
-   GLboolean EmitNoNoise; /**< Emit NOISE opcodes? */
GLboolean EmitNoPow;   /**< Emit POW opcodes? */
GLboolean EmitNoSat;   /**< Emit SAT opcodes? */
GLboolean LowerCombinedClipCullDistance; /** Lower gl_ClipDistance and
   * gl_CullDistance together from
   * float[8] to vec4[2]
   **/
 
/**
 * \name Forms of indirect addressing the driver cannot do.
 */
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index d0e83cc..be10432 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -2989,22 +2989,21 @@ _mesa_ir_link_shader(struct gl_context *ctx, struct 
gl_shader_program *prog)
options, ctx->Const.NativeIntegers)
   || progress;
 
 progress = lower_quadop_vector(ir, true) || progress;
 
 if (options->MaxIfDepth == 0)
progress = lower_discard(ir) || progress;
 
 progress = lower_if_to_cond_assign(ir, options->MaxIfDepth) || 
progress;
 
-if (options->EmitNoNoise)
-   progress = lower_noise(ir) || progress;
+ progress = lower_noise(ir) || progress;
 
 /* If there are forms of indirect addressing that the driver
  * cannot handle, perform the lowering pass.
  */
 if (options->EmitNoIndirectInput || options->EmitNoIndirectOutput
 || options->EmitNoIndirectTemp || options->EmitNoIndirectUniform)
   progress =
 
lower_variable_index_to_cond_assign(prog->_LinkedShaders[i]->Stage, ir,
 options->EmitNoIndirectInput,
 

[Mesa-dev] [PATCH 13/14] mesa: remove gl_shader_compiler_options::EmitNoMainReturn

[Marek Olšák]

From: Marek Olšák 

it's always true
---
 src/mesa/drivers/dri/i915/i915_context.c   | 1 -
 src/mesa/drivers/dri/i965/brw_compiler.c   | 1 -
 src/mesa/main/mtypes.h | 1 -
 src/mesa/program/ir_to_mesa.cpp| 9 -
 src/mesa/state_tracker/st_extensions.c | 1 -
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +-
 6 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i915_context.c 
b/src/mesa/drivers/dri/i915/i915_context.c
index 83aaf9e..a7604a1 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -255,21 +255,20 @@ i915CreateContext(int api,
 * FINISHME: vertex shaders?
 */
ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].EmitNoIndirectSampler =
   true;
 
struct gl_shader_compiler_options *const fs_options =
   & ctx->Const.ShaderCompilerOptions[MESA_SHADER_FRAGMENT];
fs_options->MaxIfDepth = 0;
fs_options->EmitNoNoise = true;
fs_options->EmitNoPow = true;
-   fs_options->EmitNoMainReturn = true;
fs_options->EmitNoIndirectInput = true;
fs_options->EmitNoIndirectOutput = true;
fs_options->EmitNoIndirectUniform = true;
fs_options->EmitNoIndirectTemp = true;
fs_options->EmitNoIndirectSampler = true;
 
ctx->Const.MaxDrawBuffers = 1;
ctx->Const.QueryCounterBits.SamplesPassed = 0;
 
_tnl_init_vertices(ctx, ctx->Const.MaxArrayLockSize + 12,
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.c 
b/src/mesa/drivers/dri/i965/brw_compiler.c
index 86b1eaa..27cbd40 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.c
+++ b/src/mesa/drivers/dri/i965/brw_compiler.c
@@ -117,21 +117,20 @@ brw_compiler_create(void *mem_ctx, const struct 
gen_device_info *devinfo)
compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
 
/* We want the GLSL compiler to emit code that uses condition codes */
for (int i = 0; i < MESA_SHADER_STAGES; i++) {
   compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
   compiler->glsl_compiler_options[i].MaxIfDepth =
  devinfo->gen < 6 ? 16 : UINT_MAX;
 
   compiler->glsl_compiler_options[i].EmitNoNoise = true;
-  compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
   compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
   compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
   compiler->glsl_compiler_options[i].LowerCombinedClipCullDistance = true;
 
   bool is_scalar = compiler->scalar_stage[i];
 
   compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
   compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
   compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 5368440..701f055 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2990,21 +2990,20 @@ struct gl_pipeline_shader_state
 };
 
 /**
  * Compiler options for a single GLSL shaders type
  */
 struct gl_shader_compiler_options
 {
/** Driver-selectable options: */
GLboolean EmitNoLoops;
GLboolean EmitNoCont;  /**< Emit CONT opcode? */
-   GLboolean EmitNoMainReturn;/**< Emit CONT/RET opcodes? */
GLboolean EmitNoNoise; /**< Emit NOISE opcodes? */
GLboolean EmitNoPow;   /**< Emit POW opcodes? */
GLboolean EmitNoSat;   /**< Emit SAT opcodes? */
GLboolean LowerCombinedClipCullDistance; /** Lower gl_ClipDistance and
   * gl_CullDistance together from
   * float[8] to vec4[2]
   **/
 
/**
 * \name Forms of indirect addressing the driver cannot do.
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index debc18d..d0e83cc 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -2154,25 +2154,24 @@ ir_to_mesa_visitor::visit(ir_texture *ir)
default:
   assert(!"Should not get here.");
}
 
this->result = result_src;
 }
 
 void
 ir_to_mesa_visitor::visit(ir_return *ir)
 {
-   /* Non-void functions should have been inlined.  We may still emit RETs
-* from main() unless the EmitNoMainReturn option is set.
+   /* Non-void functions should have been inlined and RETs should have been
+* lowered.
 */
-   assert(!ir->get_value());
-   emit(ir, OPCODE_RET);
+   unreachable("ir_return not supported");
 }
 
 void
 ir_to_mesa_visitor::visit(ir_discard *ir)
 {
if (!ir->condition)
   ir->condition = new(mem_ctx) ir_constant(true);
 
ir->condition->accept(this);
this->result.negate = ~this->result.negate;
@@ -2977,21 +2976,21 @@ _mesa_ir_link_shader(struct gl_context *ctx, struct 
gl_shader_program *prog)
 
   do {
 progress = false;
 
 /

[Mesa-dev] [PATCH 09/14] mesa_to_tgsi: remove remnants of flow control and subroutine support

[Marek Olšák]

From: Marek Olšák 

---
 src/mesa/state_tracker/st_mesa_to_tgsi.c | 93 +---
 1 file changed, 1 insertion(+), 92 deletions(-)

diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.c 
b/src/mesa/state_tracker/st_mesa_to_tgsi.c
index c8ed26c..4c26d92 100644
--- a/src/mesa/state_tracker/st_mesa_to_tgsi.c
+++ b/src/mesa/state_tracker/st_mesa_to_tgsi.c
@@ -44,116 +44,42 @@
 #include "util/u_debug.h"
 #include "util/u_math.h"
 #include "util/u_memory.h"
 #include "st_glsl_to_tgsi.h" /* for _mesa_sysval_to_semantic */
 
 
 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) |\
(1 << PROGRAM_CONSTANT) | \
(1 << PROGRAM_UNIFORM))
 
-
-struct label {
-   unsigned branch_target;
-   unsigned token;
-};
-
-
 /**
  * Intermediate state used during shader translation.
  */
 struct st_translate {
struct ureg_program *ureg;
 
struct ureg_dst temps[MAX_PROGRAM_TEMPS];
struct ureg_src *constants;
struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
struct ureg_dst address[1];
struct ureg_src samplers[PIPE_MAX_SAMPLERS];
struct ureg_src systemValues[SYSTEM_VALUE_MAX];
 
const GLuint *inputMapping;
const GLuint *outputMapping;
 
-   /* For every instruction that contains a label (eg CALL), keep
-* details so that we can go back afterwards and emit the correct
-* tgsi instruction number for each label.
-*/
-   struct label *labels;
-   unsigned labels_size;
-   unsigned labels_count;
-
-   /* Keep a record of the tgsi instruction number that each mesa
-* instruction starts at, will be used to fix up labels after
-* translation.
-*/
-   unsigned *insn;
-   unsigned insn_size;
-   unsigned insn_count;
-
unsigned procType;  /**< PIPE_SHADER_VERTEX/FRAGMENT */
-
-   boolean error;
 };
 
 
 /**
- * Make note of a branch to a label in the TGSI code.
- * After we've emitted all instructions, we'll go over the list
- * of labels built here and patch the TGSI code with the actual
- * location of each label.
- */
-static unsigned *get_label( struct st_translate *t,
-unsigned branch_target )
-{
-   unsigned i;
-
-   if (t->labels_count + 1 >= t->labels_size) {
-  t->labels_size = 1 << (util_logbase2(t->labels_size) + 1);
-  t->labels = realloc(t->labels, t->labels_size * sizeof t->labels[0]);
-  if (t->labels == NULL) {
- static unsigned dummy;
- t->error = TRUE;
- return &dummy;
-  }
-   }
-
-   i = t->labels_count++;
-   t->labels[i].branch_target = branch_target;
-   return &t->labels[i].token;
-}
-
-
-/**
- * Called prior to emitting the TGSI code for each Mesa instruction.
- * Allocate additional space for instructions if needed.
- * Update the insn[] array so the next Mesa instruction points to
- * the next TGSI instruction.
- */
-static void set_insn_start( struct st_translate *t,
-unsigned start )
-{
-   if (t->insn_count + 1 >= t->insn_size) {
-  t->insn_size = 1 << (util_logbase2(t->insn_size) + 1);
-  t->insn = realloc(t->insn, t->insn_size * sizeof t->insn[0]);
-  if (t->insn == NULL) {
- t->error = TRUE;
- return;
-  }
-   }
-
-   t->insn[t->insn_count++] = start;
-}
-
-
-/**
  * Map a Mesa dst register to a TGSI ureg_dst register.
  */
 static struct ureg_dst
 dst_register( struct st_translate *t,
   gl_register_file file,
   GLuint index )
 {
switch( file ) {
case PROGRAM_UNDEFINED:
   return ureg_dst_undef();
@@ -1088,34 +1014,17 @@ st_translate_mesa_program(
 TGSI_RETURN_TYPE_FLOAT,
 TGSI_RETURN_TYPE_FLOAT,
 TGSI_RETURN_TYPE_FLOAT,
 TGSI_RETURN_TYPE_FLOAT);
 
   }
}
 
/* Emit each instruction in turn:
 */
-   for (i = 0; i < program->NumInstructions; i++) {
-  set_insn_start( t, ureg_get_instruction_number( ureg ));
+   for (i = 0; i < program->NumInstructions; i++)
   compile_instruction(ctx, t, &program->Instructions[i]);
-   }
-
-   /* Fix up all emitted labels:
-*/
-   for (i = 0; i < t->labels_count; i++) {
-  ureg_fixup_label( ureg,
-t->labels[i].token,
-t->insn[t->labels[i].branch_target] );
-   }
 
 out:
-   free(t->insn);
-   free(t->labels);
free(t->constants);
-
-   if (t->error) {
-  debug_printf("%s: translate error flag set\n", __func__);
-   }
-
return ret;
 }
-- 
2.7.4

___
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[Mesa-dev] [PATCH 01/14] glsl_to_tgsi: use array_id for temp arrays instead of hacking high bits

[Marek Olšák]

From: Marek Olšák 

---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 31 ++
 1 file changed, 19 insertions(+), 12 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index fd2485d..5bc2661 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -83,54 +83,57 @@ static int swizzle_for_type(const glsl_type *type, int 
component = 0)
swizzle += component * MAKE_SWIZZLE4(1, 1, 1, 1);
return swizzle;
 }
 
 /**
  * This struct is a corresponding struct to TGSI ureg_src.
  */
 class st_src_reg {
 public:
st_src_reg(gl_register_file file, int index, const glsl_type *type,
-  int component = 0)
+  int component = 0, unsigned array_id = 0)
{
+  assert(file != PROGRAM_ARRAY || array_id != 0);
   this->file = file;
   this->index = index;
   this->swizzle = swizzle_for_type(type, component);
   this->negate = 0;
   this->index2D = 0;
   this->type = type ? type->base_type : GLSL_TYPE_ERROR;
   this->reladdr = NULL;
   this->reladdr2 = NULL;
   this->has_index2 = false;
   this->double_reg2 = false;
-  this->array_id = 0;
+  this->array_id = array_id;
   this->is_double_vertex_input = false;
}
 
st_src_reg(gl_register_file file, int index, enum glsl_base_type type)
{
+  assert(file != PROGRAM_ARRAY); /* need array_id > 0 */
   this->type = type;
   this->file = file;
   this->index = index;
   this->index2D = 0;
   this->swizzle = SWIZZLE_XYZW;
   this->negate = 0;
   this->reladdr = NULL;
   this->reladdr2 = NULL;
   this->has_index2 = false;
   this->double_reg2 = false;
   this->array_id = 0;
   this->is_double_vertex_input = false;
}
 
st_src_reg(gl_register_file file, int index, enum glsl_base_type type, int 
index2D)
{
+  assert(file != PROGRAM_ARRAY); /* need array_id > 0 */
   this->type = type;
   this->file = file;
   this->index = index;
   this->index2D = index2D;
   this->swizzle = SWIZZLE_XYZW;
   this->negate = 0;
   this->reladdr = NULL;
   this->reladdr2 = NULL;
   this->has_index2 = false;
   this->double_reg2 = false;
@@ -172,33 +175,35 @@ public:
 */
bool double_reg2;
unsigned array_id;
bool is_double_vertex_input;
 };
 
 class st_dst_reg {
 public:
st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type, 
int index)
{
+  assert(file != PROGRAM_ARRAY); /* need array_id > 0 */
   this->file = file;
   this->index = index;
   this->index2D = 0;
   this->writemask = writemask;
   this->reladdr = NULL;
   this->reladdr2 = NULL;
   this->has_index2 = false;
   this->type = type;
   this->array_id = 0;
}
 
st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type)
{
+  assert(file != PROGRAM_ARRAY); /* need array_id > 0 */
   this->file = file;
   this->index = 0;
   this->index2D = 0;
   this->writemask = writemask;
   this->reladdr = NULL;
   this->reladdr2 = NULL;
   this->has_index2 = false;
   this->type = type;
   this->array_id = 0;
}
@@ -289,21 +294,21 @@ public:
class function_entry *function; /* Set on TGSI_OPCODE_CAL or 
TGSI_OPCODE_BGNSUB */
const struct tgsi_opcode_info *info;
 };
 
 class variable_storage : public exec_node {
 public:
variable_storage(ir_variable *var, gl_register_file file, int index,
 unsigned array_id = 0)
   : file(file), index(index), component(0), var(var), array_id(array_id)
{
-  /* empty */
+  assert(file != PROGRAM_ARRAY || array_id != 0);
}
 
gl_register_file file;
int index;
 
/* Explicit component location. This is given in terms of the GLSL-style
 * swizzles where each double is a single component, i.e. for 64-bit types
 * it can only be 0 or 1.
 */
int component;
@@ -1255,21 +1260,22 @@ glsl_to_tgsi_visitor::get_temp(const glsl_type *type)
src.negate = 0;
 
if (!options->EmitNoIndirectTemp && type_has_array_or_matrix(type)) {
   if (next_array >= max_num_arrays) {
  max_num_arrays += 32;
  array_sizes = (unsigned*)
 realloc(array_sizes, sizeof(array_sizes[0]) * max_num_arrays);
   }
 
   src.file = PROGRAM_ARRAY;
-  src.index = next_array << 16 | 0x8000;
+  src.index = 0;
+  src.array_id = next_array + 1;
   array_sizes[next_array] = type_size(type);
   ++next_array;
 
} else {
   src.file = PROGRAM_TEMPORARY;
   src.index = next_temp;
   next_temp += type_size(type);
}
 
if (type->is_array() || type->is_record()) {
@@ -1330,21 +1336,22 @@ glsl_to_tgsi_visitor::visit(ir_variable *ir)
  dst = undef_dst;
   } else {
  /* The variable_storage constructor allocates slots b

[Mesa-dev] [PATCH 06/14] glsl_to_tgsi: merge buffer and sampler fields in glsl_to_tgsi_instruction

[Marek Olšák]

From: Marek Olšák 

sizeof(glsl_to_tgsi_instruction): 416 -> 384
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 63 +++---
 1 file changed, 31 insertions(+), 32 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index b3654fe..b7280e3 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -265,23 +265,22 @@ st_dst_reg::st_dst_reg(st_src_reg reg)
this->has_index2 = reg.has_index2;
this->array_id = reg.array_id;
 }
 
 class glsl_to_tgsi_instruction : public exec_node {
 public:
DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction)
 
st_dst_reg dst[2];
st_src_reg src[4];
-   st_src_reg sampler; /**< sampler register */
+   st_src_reg resource; /**< sampler or buffer register */
st_src_reg tex_offsets[MAX_GLSL_TEXTURE_OFFSET];
-   st_src_reg buffer; /**< buffer register */
 
/** Pointer to the ir source this tree came from for debugging */
ir_instruction *ir;
 
unsigned op:8; /**< TGSI opcode */
unsigned saturate:1;
unsigned is_64bit_expanded:1;
unsigned sampler_base:5;
unsigned sampler_array_size:6; /**< 1-based size of sampler array, 1 if not 
array */
unsigned tex_target:4; /**< One of TEXTURE_*_INDEX */
@@ -2273,21 +2272,21 @@ glsl_to_tgsi_visitor::visit_expression(ir_expression* 
ir, st_src_reg *op)
   st_src_reg buffer(
 PROGRAM_BUFFER,
 ctx->Const.Program[shader->Stage].MaxAtomicBuffers +
 (const_offset ? const_offset->value.u[0] : 0),
 GLSL_TYPE_UINT);
   if (!const_offset) {
  buffer.reladdr = ralloc(mem_ctx, st_src_reg);
  *buffer.reladdr = op[0];
  emit_arl(ir, sampler_reladdr, op[0]);
   }
-  emit_asm(ir, TGSI_OPCODE_RESQ, result_dst)->buffer = buffer;
+  emit_asm(ir, TGSI_OPCODE_RESQ, result_dst)->resource = buffer;
   break;
}
 
case ir_unop_vote_any:
   emit_asm(ir, TGSI_OPCODE_VOTE_ANY, result_dst, op[0]);
   break;
case ir_unop_vote_all:
   emit_asm(ir, TGSI_OPCODE_VOTE_ALL, result_dst, op[0]);
   break;
case ir_unop_vote_eq:
@@ -3304,21 +3303,21 @@ 
glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
  break;
   }
   default:
  assert(!"Unexpected intrinsic");
  return;
   }
 
   inst = emit_asm(ir, opcode, dst, offset, data, data2);
}
 
-   inst->buffer = buffer;
+   inst->resource = buffer;
 }
 
 void
 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call *ir)
 {
exec_node *param = ir->actual_parameters.get_head();
 
ir_rvalue *block = ((ir_instruction *)param)->as_rvalue();
 
param = param->get_next();
@@ -3417,27 +3416,27 @@ glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call *ir)
if (!param->is_tail_sentinel()) {
   access = ((ir_instruction *)param)->as_constant();
   assert(access);
}
 
/* The emit_asm() might have actually split the op into pieces, e.g. for
 * double stores. We have to go back and fix up all the generated ops.
 */
unsigned op = inst->op;
do {
-  inst->buffer = buffer;
+  inst->resource = buffer;
   if (access)
  inst->buffer_access = access->value.u[0];
   inst = (glsl_to_tgsi_instruction *)inst->get_prev();
   if (inst->op == TGSI_OPCODE_UADD)
  inst = (glsl_to_tgsi_instruction *)inst->get_prev();
-   } while (inst && inst->op == op && inst->buffer.file == PROGRAM_UNDEFINED);
+   } while (inst && inst->op == op && inst->resource.file == 
PROGRAM_UNDEFINED);
 }
 
 void
 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call *ir)
 {
switch (ir->callee->intrinsic_id) {
case ir_intrinsic_memory_barrier:
   emit_asm(ir, TGSI_OPCODE_MEMBAR, undef_dst,
st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER |
   TGSI_MEMBAR_ATOMIC_BUFFER |
@@ -3490,34 +3489,34 @@ glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call 
*ir)
if (ir->return_deref) {
   ir->return_deref->accept(this);
   dst = st_dst_reg(this->result);
   dst.writemask = (1 << ir->return_deref->type->vector_elements) - 1;
}
 
glsl_to_tgsi_instruction *inst;
 
if (ir->callee->intrinsic_id == ir_intrinsic_shared_load) {
   inst = emit_asm(ir, TGSI_OPCODE_LOAD, dst, off);
-  inst->buffer = buffer;
+  inst->resource = buffer;
} else if (ir->callee->intrinsic_id == ir_intrinsic_shared_store) {
   param = param->get_next();
   ir_rvalue *val = ((ir_instruction *)param)->as_rvalue();
   val->accept(this);
 
   param = param->get_next();
   ir_constant *write_mask = ((ir_instruction *)param)->as_constant();
   assert(write_mask);
   dst.writemask = write_mask->value.u[0];
 
   dst.type = this->result.type;
   inst = emit_asm(ir, TGSI_OPCODE_STORE, dst, off, this->result);
-  inst->buffer = buffer;
+  inst->resource = buffer;
}

[Mesa-dev] [PATCH 02/14] glsl_to_tgsi: remove unused parameters from calc_deref_offsets

[Marek Olšák]

From: Marek Olšák 

---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 14 +-
 1 file changed, 5 insertions(+), 9 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 5bc2661..b857a5b 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -551,24 +551,22 @@ public:
void emit_scalar(ir_instruction *ir, unsigned op,
 st_dst_reg dst, st_src_reg src0, st_src_reg src1);
 
void emit_arl(ir_instruction *ir, st_dst_reg dst, st_src_reg src0);
 
void get_deref_offsets(ir_dereference *ir,
   unsigned *array_size,
   unsigned *base,
   unsigned *index,
   st_src_reg *reladdr);
-  void calc_deref_offsets(ir_dereference *head,
-  ir_dereference *tail,
+  void calc_deref_offsets(ir_dereference *tail,
   unsigned *array_elements,
-  unsigned *base,
   unsigned *index,
   st_src_reg *indirect,
   unsigned *location);
st_src_reg canonicalize_gather_offset(st_src_reg offset);
 
bool try_emit_mad(ir_expression *ir,
   int mul_operand);
bool try_emit_mad_for_and_not(ir_expression *ir,
   int mul_operand);
 
@@ -3878,35 +3876,33 @@ glsl_to_tgsi_visitor::visit(ir_call *ir)
 r.index++;
  }
   }
}
 
/* Process return value. */
this->result = entry->return_reg;
 }
 
 void
-glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference *head,
- ir_dereference *tail,
+glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference *tail,
  unsigned *array_elements,
- unsigned *base,
  unsigned *index,
  st_src_reg *indirect,
  unsigned *location)
 {
switch (tail->ir_type) {
case ir_type_dereference_record: {
   ir_dereference_record *deref_record = tail->as_dereference_record();
   const glsl_type *struct_type = deref_record->record->type;
   int field_index = 
deref_record->record->type->field_index(deref_record->field);
 
-  calc_deref_offsets(head, deref_record->record->as_dereference(), 
array_elements, base, index, indirect, location);
+  calc_deref_offsets(deref_record->record->as_dereference(), 
array_elements, index, indirect, location);
 
   assert(field_index >= 0);
   *location += struct_type->record_location_offset(field_index);
   break;
}
 
case ir_type_dereference_array: {
   ir_dereference_array *deref_arr = tail->as_dereference_array();
   ir_constant *array_index = 
deref_arr->array_index->constant_expression_value();
 
@@ -3929,21 +3925,21 @@ glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference 
*head,
  else {
 temp_dst = st_dst_reg(*indirect);
 temp_dst.writemask = 1;
 emit_asm(NULL, TGSI_OPCODE_ADD, temp_dst, *indirect, temp_reg);
  }
   } else
  *index += array_index->value.u[0] * *array_elements;
 
   *array_elements *= deref_arr->array->type->length;
 
-  calc_deref_offsets(head, deref_arr->array->as_dereference(), 
array_elements, base, index, indirect, location);
+  calc_deref_offsets(deref_arr->array->as_dereference(), array_elements, 
index, indirect, location);
   break;
}
default:
   break;
}
 }
 
 void
 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference *ir,
 unsigned *array_size,
@@ -3956,21 +3952,21 @@ glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference 
*ir,
ir_variable *var = ir->variable_referenced();
 
memset(reladdr, 0, sizeof(*reladdr));
reladdr->file = PROGRAM_UNDEFINED;
 
*base = 0;
*array_size = 1;
 
assert(var);
location = var->data.location;
-   calc_deref_offsets(ir, ir, array_size, base, index, reladdr, &location);
+   calc_deref_offsets(ir, array_size, index, reladdr, &location);
 
/*
 * If we end up with no indirect then adjust the base to the index,
 * and set the array size to 1.
 */
if (reladdr->file == PROGRAM_UNDEFINED) {
   *base = *index;
   *array_size = 1;
}
 
-- 
2.7.4

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[Mesa-dev] [PATCH 07/14] glsl_to_tgsi: allocate glsl_to_tgsi_instruction::tex_offsets on demand

[Marek Olšák]

From: Marek Olšák 

sizeof(glsl_to_tgsi_instruction): 384 -> 264
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index b7280e3..2ae15c9 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -266,21 +266,21 @@ st_dst_reg::st_dst_reg(st_src_reg reg)
this->array_id = reg.array_id;
 }
 
 class glsl_to_tgsi_instruction : public exec_node {
 public:
DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction)
 
st_dst_reg dst[2];
st_src_reg src[4];
st_src_reg resource; /**< sampler or buffer register */
-   st_src_reg tex_offsets[MAX_GLSL_TEXTURE_OFFSET];
+   st_src_reg *tex_offsets;
 
/** Pointer to the ir source this tree came from for debugging */
ir_instruction *ir;
 
unsigned op:8; /**< TGSI opcode */
unsigned saturate:1;
unsigned is_64bit_expanded:1;
unsigned sampler_base:5;
unsigned sampler_array_size:6; /**< 1-based size of sampler array, 1 if not 
array */
unsigned tex_target:4; /**< One of TEXTURE_*_INDEX */
@@ -4269,20 +4269,23 @@ glsl_to_tgsi_visitor::visit(ir_texture *ir)
inst->resource.index = sampler_index;
inst->sampler_array_size = sampler_array_size;
inst->sampler_base = sampler_base;
 
if (reladdr.file != PROGRAM_UNDEFINED) {
   inst->resource.reladdr = ralloc(mem_ctx, st_src_reg);
   memcpy(inst->resource.reladdr, &reladdr, sizeof(reladdr));
}
 
if (ir->offset) {
+  if (!inst->tex_offsets)
+ inst->tex_offsets = rzalloc_array(inst, st_src_reg, 
MAX_GLSL_TEXTURE_OFFSET);
+
   for (i = 0; i < MAX_GLSL_TEXTURE_OFFSET && offset[i].file != 
PROGRAM_UNDEFINED; i++)
  inst->tex_offsets[i] = offset[i];
   inst->tex_offset_num_offset = i;
}
 
switch (sampler_type->sampler_dimensionality) {
case GLSL_SAMPLER_DIM_1D:
   inst->tex_target = (sampler_type->sampler_array)
  ? TEXTURE_1D_ARRAY_INDEX : TEXTURE_1D_INDEX;
   break;
-- 
2.7.4

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[Mesa-dev] [PATCH 03/14] glsl_to_tgsi: remove unused st_translate::tex_offsets

[Marek Olšák]

From: Marek Olšák 

---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index b857a5b..93673fa 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -5286,21 +5286,20 @@ struct st_translate {
struct ureg_src *immediates;
int num_immediates;
struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
struct ureg_dst address[3];
struct ureg_src samplers[PIPE_MAX_SAMPLERS];
struct ureg_src buffers[PIPE_MAX_SHADER_BUFFERS];
struct ureg_src images[PIPE_MAX_SHADER_IMAGES];
struct ureg_src systemValues[SYSTEM_VALUE_MAX];
struct ureg_src shared_memory;
-   struct tgsi_texture_offset tex_offsets[MAX_GLSL_TEXTURE_OFFSET];
unsigned *array_sizes;
struct inout_decl *input_decls;
unsigned num_input_decls;
struct inout_decl *output_decls;
unsigned num_output_decls;
 
const GLuint *inputMapping;
const GLuint *outputMapping;
 
/* For every instruction that contains a label (eg CALL), keep
-- 
2.7.4

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[Mesa-dev] [PATCH 2/6] gallium/radeon: remove unused radeon_llvm_reg_index_soa

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/radeon_llvm.h| 2 --
 src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 5 -
 2 files changed, 7 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_llvm.h 
b/src/gallium/drivers/radeon/radeon_llvm.h
index 367e4c0..b4b968b 100644
--- a/src/gallium/drivers/radeon/radeon_llvm.h
+++ b/src/gallium/drivers/radeon/radeon_llvm.h
@@ -114,22 +114,20 @@ void radeon_llvm_context_init(struct radeon_llvm_context 
*ctx,
   const char *triple,
  const struct tgsi_shader_info *info,
  const struct tgsi_token *tokens);
 
 void radeon_llvm_create_func(struct radeon_llvm_context *ctx,
 LLVMTypeRef *return_types, unsigned 
num_return_elems,
 LLVMTypeRef *ParamTypes, unsigned ParamCount);
 
 void radeon_llvm_dispose(struct radeon_llvm_context *ctx);
 
-unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan);
-
 void radeon_llvm_finalize_module(struct radeon_llvm_context *ctx,
 bool run_verifier);
 
 LLVMValueRef radeon_llvm_emit_fetch_64bit(struct lp_build_tgsi_context 
*bld_base,
  enum tgsi_opcode_type type,
  LLVMValueRef ptr,
  LLVMValueRef ptr2);
 
 LLVMValueRef radeon_llvm_saturate(struct lp_build_tgsi_context *bld_base,
   LLVMValueRef value);
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c 
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 2713cc6..2d424d5 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -145,25 +145,20 @@ push_flow(struct radeon_llvm_context *ctx)
}
 
flow = &ctx->flow[ctx->flow_depth];
ctx->flow_depth++;
 
flow->next_block = NULL;
flow->loop_entry_block = NULL;
return flow;
 }
 
-unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
-{
-   return (index * 4) + chan;
-}
-
 static LLVMValueRef emit_swizzle(struct lp_build_tgsi_context *bld_base,
 LLVMValueRef value,
 unsigned swizzle_x,
 unsigned swizzle_y,
 unsigned swizzle_z,
 unsigned swizzle_w)
 {
LLVMValueRef swizzles[4];
LLVMTypeRef i32t =
LLVMInt32TypeInContext(bld_base->base.gallivm->context);
-- 
2.7.4

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[Mesa-dev] [PATCH 1/6] radeonsi: move LLVM ALU codegen into radeonsi

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/radeon_llvm.h   |9 -
 .../drivers/radeon/radeon_setup_tgsi_llvm.c|  979 +--
 src/gallium/drivers/radeonsi/Makefile.sources  |2 +
 src/gallium/drivers/radeonsi/si_shader.c   |9 +-
 src/gallium/drivers/radeonsi/si_shader_internal.h  |   37 +
 src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c  | 1012 
 6 files changed, 1056 insertions(+), 992 deletions(-)
 create mode 100644 src/gallium/drivers/radeonsi/si_shader_internal.h
 create mode 100644 src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c

diff --git a/src/gallium/drivers/radeon/radeon_llvm.h 
b/src/gallium/drivers/radeon/radeon_llvm.h
index 6010254..367e4c0 100644
--- a/src/gallium/drivers/radeon/radeon_llvm.h
+++ b/src/gallium/drivers/radeon/radeon_llvm.h
@@ -103,45 +103,36 @@ struct radeon_llvm_context {
 LLVMTypeRef tgsi2llvmtype(struct lp_build_tgsi_context *bld_base,
  enum tgsi_opcode_type type);
 
 LLVMValueRef bitcast(struct lp_build_tgsi_context *bld_base,
 enum tgsi_opcode_type type, LLVMValueRef value);
 
 LLVMValueRef radeon_llvm_bound_index(struct radeon_llvm_context *ctx,
 LLVMValueRef index,
 unsigned num);
 
-void radeon_llvm_emit_prepare_cube_coords(struct lp_build_tgsi_context 
*bld_base,
- struct lp_build_emit_data *emit_data,
- LLVMValueRef *coords_arg,
- LLVMValueRef *derivs_arg);
-
 void radeon_llvm_context_init(struct radeon_llvm_context *ctx,
   const char *triple,
  const struct tgsi_shader_info *info,
  const struct tgsi_token *tokens);
 
 void radeon_llvm_create_func(struct radeon_llvm_context *ctx,
 LLVMTypeRef *return_types, unsigned 
num_return_elems,
 LLVMTypeRef *ParamTypes, unsigned ParamCount);
 
 void radeon_llvm_dispose(struct radeon_llvm_context *ctx);
 
 unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan);
 
 void radeon_llvm_finalize_module(struct radeon_llvm_context *ctx,
 bool run_verifier);
 
-void build_tgsi_intrinsic_nomem(const struct lp_build_tgsi_action *action,
-   struct lp_build_tgsi_context *bld_base,
-   struct lp_build_emit_data *emit_data);
-
 LLVMValueRef radeon_llvm_emit_fetch_64bit(struct lp_build_tgsi_context 
*bld_base,
  enum tgsi_opcode_type type,
  LLVMValueRef ptr,
  LLVMValueRef ptr2);
 
 LLVMValueRef radeon_llvm_saturate(struct lp_build_tgsi_context *bld_base,
   LLVMValueRef value);
 
 LLVMValueRef radeon_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_src_register *reg,
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c 
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index c843541..2713cc6 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -1008,871 +1008,34 @@ static void uif_emit(const struct lp_build_tgsi_action 
*action,
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMValueRef cond;
 
cond = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
bitcast(bld_base, TGSI_TYPE_UNSIGNED, emit_data->args[0]),
bld_base->int_bld.zero, "");
 
if_cond_emit(action, bld_base, emit_data, cond);
 }
 
-static void kill_if_fetch_args(struct lp_build_tgsi_context *bld_base,
-  struct lp_build_emit_data *emit_data)
-{
-   const struct tgsi_full_instruction *inst = emit_data->inst;
-   struct gallivm_state *gallivm = bld_base->base.gallivm;
-   LLVMBuilderRef builder = gallivm->builder;
-   unsigned i;
-   LLVMValueRef conds[TGSI_NUM_CHANNELS];
-
-   for (i = 0; i < TGSI_NUM_CHANNELS; i++) {
-   LLVMValueRef value = lp_build_emit_fetch(bld_base, inst, 0, i);
-   conds[i] = LLVMBuildFCmp(builder, LLVMRealOLT, value,
-   bld_base->base.zero, "");
-   }
-
-   /* Or the conditions together */
-   for (i = TGSI_NUM_CHANNELS - 1; i > 0; i--) {
-   conds[i - 1] = LLVMBuildOr(builder, conds[i], conds[i - 1], "");
-   }
-
-   emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
-   emit_data->arg_count = 1;
-   emit_data->args[0] = LLVMBuildSelect(builder, conds[0],
-   lp_build_const_float(gallivm, -1.0f),
-

[Mesa-dev] [PATCH 4/6] radeonsi: import all TGSI->LLVM code from gallium/radeon

[Marek Olšák]

From: Marek Olšák 

---
 .../drivers/r600/evergreen_compute_internal.h  |1 -
 src/gallium/drivers/radeon/Makefile.sources|6 +-
 src/gallium/drivers/radeon/radeon_llvm.h   |  151 ---
 src/gallium/drivers/radeon/radeon_llvm_emit.c  |  241 
 src/gallium/drivers/radeon/radeon_llvm_emit.h  |   46 -
 .../drivers/radeon/radeon_setup_tgsi_llvm.c| 1157 
 src/gallium/drivers/radeonsi/Makefile.sources  |1 +
 src/gallium/drivers/radeonsi/si_pipe.c |2 +-
 src/gallium/drivers/radeonsi/si_shader.c   |2 -
 src/gallium/drivers/radeonsi/si_shader_internal.h  |  132 ++
 src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c  |1 -
 .../drivers/radeonsi/si_shader_tgsi_setup.c| 1379 
 12 files changed, 1514 insertions(+), 1605 deletions(-)
 delete mode 100644 src/gallium/drivers/radeon/radeon_llvm.h
 delete mode 100644 src/gallium/drivers/radeon/radeon_llvm_emit.c
 delete mode 100644 src/gallium/drivers/radeon/radeon_llvm_emit.h
 create mode 100644 src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c

diff --git a/src/gallium/drivers/r600/evergreen_compute_internal.h 
b/src/gallium/drivers/r600/evergreen_compute_internal.h
index e6ff760..34d96f6 100644
--- a/src/gallium/drivers/r600/evergreen_compute_internal.h
+++ b/src/gallium/drivers/r600/evergreen_compute_internal.h
@@ -20,21 +20,20 @@
  *
  * Authors:
  *  Adam Rak 
  */
  
 #ifndef EVERGREEN_COMPUTE_INTERNAL_H
 #define EVERGREEN_COMPUTE_INTERNAL_H
 
 #include "r600_asm.h"
 #ifdef HAVE_OPENCL
-#include "radeon/radeon_llvm.h"
 #include 
 #endif
 
 struct r600_pipe_compute {
struct r600_context *ctx;
 
struct radeon_shader_binary binary;
struct r600_resource *code_bo;
struct r600_bytecode bc;
 
diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources
index 049da60..3e13dae 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -18,15 +18,11 @@ C_SOURCES := \
radeon_vce_50.c \
radeon_vce_52.c \
radeon_vce.c \
radeon_vce.h \
radeon_video.c \
radeon_video.h \
radeon_winsys.h
 
 LLVM_C_FILES := \
radeon_elf_util.c \
-   radeon_elf_util.h \
-   radeon_llvm_emit.c \
-   radeon_llvm_emit.h \
-   radeon_llvm.h \
-   radeon_setup_tgsi_llvm.c
+   radeon_elf_util.h
diff --git a/src/gallium/drivers/radeon/radeon_llvm.h 
b/src/gallium/drivers/radeon/radeon_llvm.h
deleted file mode 100644
index b4b968b..000
--- a/src/gallium/drivers/radeon/radeon_llvm.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Copyright 2011 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 
THE
- * SOFTWARE.
- *
- * Authors: Tom Stellard 
- *
- */
-
-#ifndef RADEON_LLVM_H
-#define RADEON_LLVM_H
-
-#include 
-#include "gallivm/lp_bld_init.h"
-#include "gallivm/lp_bld_tgsi.h"
-#include "tgsi/tgsi_parse.h"
-
-#define RADEON_LLVM_MAX_INPUT_SLOTS 32
-#define RADEON_LLVM_MAX_INPUTS 32 * 4
-#define RADEON_LLVM_MAX_OUTPUTS 32 * 4
-
-#define RADEON_LLVM_INITIAL_CF_DEPTH 4
-
-#define RADEON_LLVM_MAX_SYSTEM_VALUES 4
-
-struct radeon_llvm_flow;
-
-struct radeon_llvm_context {
-   struct lp_build_tgsi_soa_context soa;
-
-   /*=== Front end configuration ===*/
-
-   /* Instructions that are not described by any of the TGSI opcodes. */
-
-   /** This function is responsible for initilizing the inputs array and 
will be
- * called once for each input declared in the TGSI shader.
- */
-   void (*load_input)(struct radeon_llvm_context *,
-  unsigned input_index,
-  const struct tgsi_full_declaration *decl,
-  LLVMValueRef out[4]);
-
-   void (*load_system_value)(struct radeon_llvm_context *,
-  

Re: [Mesa-dev] [PATCH 10/14] glsl_to_tgsi: remove subroutine support

[Ilia Mirkin]

nouveau supports PIPE_SHADER_CAP_SUBROUTINES and properly details with
RET opcodes. The alternative is that the st lowers the whole thing
into a loop which adds IMHO unnecessary complexity to the resulting
code. Any reason not to leave that in place?

  -ilia

On Mon, Oct 17, 2016 at 9:39 AM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> Never used. The GLSL compiler doesn't even look at EmitNoFunctions.
> ---
>  src/mesa/state_tracker/st_extensions.c |   6 +-
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 212 
> +
>  2 files changed, 7 insertions(+), 211 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_extensions.c 
> b/src/mesa/state_tracker/st_extensions.c
> index b87a3db..13b7ae4 100644
> --- a/src/mesa/state_tracker/st_extensions.c
> +++ b/src/mesa/state_tracker/st_extensions.c
> @@ -265,24 +265,22 @@ void st_init_limits(struct pipe_screen *screen,
>
>options->EmitNoNoise = TRUE;
>
>/* TODO: make these more fine-grained if anyone needs it */
>options->MaxIfDepth =
>   screen->get_shader_param(screen, sh,
>PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH);
>options->EmitNoLoops =
>   !screen->get_shader_param(screen, sh,
> PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH);
> -  options->EmitNoFunctions =
> - !screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_SUBROUTINES);
> -  options->EmitNoMainReturn =
> - !screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_SUBROUTINES);
> +  options->EmitNoFunctions = true;
> +  options->EmitNoMainReturn = true;
>
>options->EmitNoCont =
>   !screen->get_shader_param(screen, sh,
> PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED);
>
>options->EmitNoIndirectInput =
>   !screen->get_shader_param(screen, sh,
> PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR);
>options->EmitNoIndirectOutput =
>   !screen->get_shader_param(screen, sh,
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index 2ae15c9..293654c 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -284,21 +284,20 @@ public:
> unsigned sampler_base:5;
> unsigned sampler_array_size:6; /**< 1-based size of sampler array, 1 if 
> not array */
> unsigned tex_target:4; /**< One of TEXTURE_*_INDEX */
> glsl_base_type tex_type:4;
> unsigned tex_shadow:1;
> unsigned image_format:9;
> unsigned tex_offset_num_offset:3;
> unsigned dead_mask:4; /**< Used in dead code elimination */
> unsigned buffer_access:3; /**< buffer access type */
>
> -   class function_entry *function; /* Set on TGSI_OPCODE_CAL or 
> TGSI_OPCODE_BGNSUB */
> const struct tgsi_opcode_info *info;
>  };
>
>  class variable_storage : public exec_node {
>  public:
> variable_storage(ir_variable *var, gl_register_file file, int index,
>  unsigned array_id = 0)
>: file(file), index(index), component(0), var(var), array_id(array_id)
> {
>assert(file != PROGRAM_ARRAY || array_id != 0);
> @@ -324,52 +323,20 @@ public:
>this->size32 = size32;
>this->type = type;
> }
>
> /* doubles are stored across 2 gl_constant_values */
> gl_constant_value values[4];
> int size32; /**< Number of 32-bit components (1-4) */
> int type; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
>  };
>
> -class function_entry : public exec_node {
> -public:
> -   ir_function_signature *sig;
> -
> -   /**
> -* identifier of this function signature used by the program.
> -*
> -* At the point that TGSI instructions for function calls are
> -* generated, we don't know the address of the first instruction of
> -* the function body.  So we make the BranchTarget that is called a
> -* small integer and rewrite them during set_branchtargets().
> -*/
> -   int sig_id;
> -
> -   /**
> -* Pointer to first instruction of the function body.
> -*
> -* Set during function body emits after main() is processed.
> -*/
> -   glsl_to_tgsi_instruction *bgn_inst;
> -
> -   /**
> -* Index of the first instruction of the function body in actual TGSI.
> -*
> -* Set after conversion from glsl_to_tgsi_instruction to TGSI.
> -*/
> -   int inst;
> -
> -   /** Storage for the return value. */
> -   st_src_reg return_reg;
> -};
> -
>  static st_src_reg undef_src = st_src_reg(PROGRAM_UNDEFINED, 0, 
> GLSL_TYPE_ERROR);
>  static st_dst_reg undef_dst = st_dst_reg(PROGRAM_UNDEFINED, SWIZZLE_NOOP, 
> GLSL_TYPE_ERROR);
>
>  struct inout_decl {
> unsigned mesa_index;
> unsigned array_id; /* TGSI ArrayID; 1-based: 0 means not an array */
> unsigned size;
> enum glsl_base_type base_type;
> ubyte usage_mask; /* GLSL-style usage-mask,  i.

[Mesa-dev] [PATCH 08/14] mesa_to_tgsi: drop support for instructions that can't occur here

[Marek Olšák]

From: Marek Olšák 

---
 src/mesa/state_tracker/st_mesa_to_tgsi.c | 72 
 1 file changed, 72 deletions(-)

diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.c 
b/src/mesa/state_tracker/st_mesa_to_tgsi.c
index b989257..c8ed26c 100644
--- a/src/mesa/state_tracker/st_mesa_to_tgsi.c
+++ b/src/mesa/state_tracker/st_mesa_to_tgsi.c
@@ -498,116 +498,78 @@ static void emit_swz( struct st_translate *t,
 static unsigned
 translate_opcode( unsigned op )
 {
switch( op ) {
case OPCODE_ARL:
   return TGSI_OPCODE_ARL;
case OPCODE_ABS:
   return TGSI_OPCODE_ABS;
case OPCODE_ADD:
   return TGSI_OPCODE_ADD;
-   case OPCODE_BGNLOOP:
-  return TGSI_OPCODE_BGNLOOP;
-   case OPCODE_BGNSUB:
-  return TGSI_OPCODE_BGNSUB;
-   case OPCODE_BRK:
-  return TGSI_OPCODE_BRK;
-   case OPCODE_CAL:
-  return TGSI_OPCODE_CAL;
case OPCODE_CMP:
   return TGSI_OPCODE_CMP;
-   case OPCODE_CONT:
-  return TGSI_OPCODE_CONT;
case OPCODE_COS:
   return TGSI_OPCODE_COS;
-   case OPCODE_DDX:
-  return TGSI_OPCODE_DDX;
-   case OPCODE_DDY:
-  return TGSI_OPCODE_DDY;
-   case OPCODE_DP2:
-  return TGSI_OPCODE_DP2;
case OPCODE_DP3:
   return TGSI_OPCODE_DP3;
case OPCODE_DP4:
   return TGSI_OPCODE_DP4;
case OPCODE_DPH:
   return TGSI_OPCODE_DPH;
case OPCODE_DST:
   return TGSI_OPCODE_DST;
-   case OPCODE_ELSE:
-  return TGSI_OPCODE_ELSE;
-   case OPCODE_ENDIF:
-  return TGSI_OPCODE_ENDIF;
-   case OPCODE_ENDLOOP:
-  return TGSI_OPCODE_ENDLOOP;
-   case OPCODE_ENDSUB:
-  return TGSI_OPCODE_ENDSUB;
case OPCODE_EX2:
   return TGSI_OPCODE_EX2;
case OPCODE_EXP:
   return TGSI_OPCODE_EXP;
case OPCODE_FLR:
   return TGSI_OPCODE_FLR;
case OPCODE_FRC:
   return TGSI_OPCODE_FRC;
-   case OPCODE_IF:
-  return TGSI_OPCODE_IF;
-   case OPCODE_TRUNC:
-  return TGSI_OPCODE_TRUNC;
case OPCODE_KIL:
   return TGSI_OPCODE_KILL_IF;
case OPCODE_LG2:
   return TGSI_OPCODE_LG2;
case OPCODE_LOG:
   return TGSI_OPCODE_LOG;
case OPCODE_LIT:
   return TGSI_OPCODE_LIT;
case OPCODE_LRP:
   return TGSI_OPCODE_LRP;
case OPCODE_MAD:
   return TGSI_OPCODE_MAD;
case OPCODE_MAX:
   return TGSI_OPCODE_MAX;
case OPCODE_MIN:
   return TGSI_OPCODE_MIN;
case OPCODE_MOV:
   return TGSI_OPCODE_MOV;
case OPCODE_MUL:
   return TGSI_OPCODE_MUL;
-   case OPCODE_NOP:
-  return TGSI_OPCODE_NOP;
case OPCODE_POW:
   return TGSI_OPCODE_POW;
case OPCODE_RCP:
   return TGSI_OPCODE_RCP;
-   case OPCODE_RET:
-  return TGSI_OPCODE_RET;
case OPCODE_SCS:
   return TGSI_OPCODE_SCS;
case OPCODE_SGE:
   return TGSI_OPCODE_SGE;
case OPCODE_SIN:
   return TGSI_OPCODE_SIN;
case OPCODE_SLT:
   return TGSI_OPCODE_SLT;
-   case OPCODE_SSG:
-  return TGSI_OPCODE_SSG;
case OPCODE_SUB:
   return TGSI_OPCODE_SUB;
case OPCODE_TEX:
   return TGSI_OPCODE_TEX;
case OPCODE_TXB:
   return TGSI_OPCODE_TXB;
-   case OPCODE_TXD:
-  return TGSI_OPCODE_TXD;
-   case OPCODE_TXL:
-  return TGSI_OPCODE_TXL;
case OPCODE_TXP:
   return TGSI_OPCODE_TXP;
case OPCODE_XPD:
   return TGSI_OPCODE_XPD;
case OPCODE_END:
   return TGSI_OPCODE_END;
default:
   debug_assert( 0 );
   return TGSI_OPCODE_NOP;
}
@@ -636,43 +598,22 @@ compile_instruction(
   inst->Saturate);
 
for (i = 0; i < num_src; i++) 
   src[i] = translate_src( t, &inst->SrcReg[i] );
 
switch( inst->Opcode ) {
case OPCODE_SWZ:
   emit_swz( t, dst[0], &inst->SrcReg[0] );
   return;
 
-   case OPCODE_BGNLOOP:
-   case OPCODE_CAL:
-   case OPCODE_ELSE:
-   case OPCODE_ENDLOOP:
-  debug_assert(num_dst == 0);
-  ureg_label_insn( ureg,
-   translate_opcode( inst->Opcode ),
-   src, num_src,
-   get_label( t, inst->BranchTarget ));
-  return;
-
-   case OPCODE_IF:
-  debug_assert(num_dst == 0);
-  ureg_label_insn( ureg,
-   ctx->Const.NativeIntegers ? TGSI_OPCODE_UIF : 
TGSI_OPCODE_IF,
-   src, num_src,
-   get_label( t, inst->BranchTarget ));
-  return;
-
case OPCODE_TEX:
case OPCODE_TXB:
-   case OPCODE_TXD:
-   case OPCODE_TXL:
case OPCODE_TXP:
   src[num_src++] = t->samplers[inst->TexSrcUnit];
   ureg_tex_insn( ureg,
  translate_opcode( inst->Opcode ),
  dst, num_dst, 
  st_translate_texture_target( inst->TexSrcTarget,
inst->TexShadow ),
  NULL, 0,
  src, num_src );
   return;
@@ -686,33 +627,20 @@ compile_instruction(
   break;
 
case OPCODE_XPD:
   dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ );
   ur

[Mesa-dev] [PATCH 04/14] glsl_to_tgsi: reduce the size of st_dst_reg and st_src_reg

[Marek Olšák]

From: Marek Olšák 

I noticed that glsl_to_tgsi_instruction is too huge.

sizeof(glsl_to_tgsi_instruction): 752 -> 464 (-38%)
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 71 +-
 1 file changed, 40 insertions(+), 31 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 93673fa..78d9409 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -152,37 +152,38 @@ public:
   this->reladdr = NULL;
   this->reladdr2 = NULL;
   this->has_index2 = false;
   this->double_reg2 = false;
   this->array_id = 0;
   this->is_double_vertex_input = false;
}
 
explicit st_src_reg(st_dst_reg reg);
 
-   gl_register_file file; /**< PROGRAM_* from Mesa */
-   int index; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
-   int index2D;
-   GLuint swizzle; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
-   int negate; /**< NEGATE_XYZW mask from mesa */
-   enum glsl_base_type type; /** GLSL_TYPE_* from GLSL IR (enum 
glsl_base_type) */
-   /** Register index should be offset by the integer in this reg. */
-   st_src_reg *reladdr;
-   st_src_reg *reladdr2;
-   bool has_index2;
+   int16_t index; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
+   int16_t index2D;
+   uint16_t swizzle; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
+   int negate:4; /**< NEGATE_XYZW mask from mesa */
+   enum glsl_base_type type:4; /** GLSL_TYPE_* from GLSL IR (enum 
glsl_base_type) */
+   unsigned has_index2:1;
+   gl_register_file file:5; /**< PROGRAM_* from Mesa */
/*
 * Is this the second half of a double register pair?
 * currently used for input mapping only.
 */
-   bool double_reg2;
-   unsigned array_id;
-   bool is_double_vertex_input;
+   unsigned double_reg2:1;
+   unsigned is_double_vertex_input:1;
+   unsigned array_id:10;
+
+   /** Register index should be offset by the integer in this reg. */
+   st_src_reg *reladdr;
+   st_src_reg *reladdr2;
 };
 
 class st_dst_reg {
 public:
st_dst_reg(gl_register_file file, int writemask, enum glsl_base_type type, 
int index)
{
   assert(file != PROGRAM_ARRAY); /* need array_id > 0 */
   this->file = file;
   this->index = index;
   this->index2D = 0;
@@ -216,30 +217,31 @@ public:
   this->index2D = 0;
   this->writemask = 0;
   this->reladdr = NULL;
   this->reladdr2 = NULL;
   this->has_index2 = false;
   this->array_id = 0;
}
 
explicit st_dst_reg(st_src_reg reg);
 
-   gl_register_file file; /**< PROGRAM_* from Mesa */
-   int index; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
-   int index2D;
-   int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
-   enum glsl_base_type type; /** GLSL_TYPE_* from GLSL IR (enum 
glsl_base_type) */
+   int16_t index; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
+   int16_t index2D;
+   gl_register_file file:5; /**< PROGRAM_* from Mesa */
+   unsigned writemask:4; /**< Bitfield of WRITEMASK_[XYZW] */
+   enum glsl_base_type type:4; /** GLSL_TYPE_* from GLSL IR (enum 
glsl_base_type) */
+   unsigned has_index2:1;
+   unsigned array_id:10;
+
/** Register index should be offset by the integer in this reg. */
st_src_reg *reladdr;
st_src_reg *reladdr2;
-   bool has_index2;
-   unsigned array_id;
 };
 
 st_src_reg::st_src_reg(st_dst_reg reg)
 {
this->type = reg.type;
this->file = reg.file;
this->index = reg.index;
this->swizzle = SWIZZLE_XYZW;
this->negate = 0;
this->reladdr = reg.reladdr;
@@ -445,21 +447,21 @@ public:
 
int glsl_version;
bool native_integers;
bool have_sqrt;
bool have_fma;
bool use_shared_memory;
 
variable_storage *find_variable_storage(ir_variable *var);
 
int add_constant(gl_register_file file, gl_constant_value values[8],
-int size, int datatype, GLuint *swizzle_out);
+int size, int datatype, uint16_t *swizzle_out);
 
function_entry *get_function_signature(ir_function_signature *sig);
 
st_src_reg get_temp(const glsl_type *type);
void reladdr_to_temp(ir_instruction *ir, st_src_reg *reg, int *num_reladdr);
 
st_src_reg st_src_reg_for_double(double val);
st_src_reg st_src_reg_for_float(float val);
st_src_reg st_src_reg_for_int(int val);
st_src_reg st_src_reg_for_type(enum glsl_base_type type, int val);
@@ -549,25 +551,25 @@ public:
 st_dst_reg dst, st_src_reg src0);
 
void emit_scalar(ir_instruction *ir, unsigned op,
 st_dst_reg dst, st_src_reg src0, st_src_reg src1);
 
void emit_arl(ir_instruction *ir, st_dst_reg dst, st_src_reg src0);
 
void get_deref_offsets(ir_dereference *ir,
   unsigned *array_size,
   unsigned *base,
-  unsigned *index,
+  uint16_t *index

[Mesa-dev] [PATCH 12/14] mesa: remove gl_shader_compiler_options::EmitNoFunctions

[Marek Olšák]

From: Marek Olšák 

---
 src/mesa/main/mtypes.h | 1 -
 src/mesa/state_tracker/st_extensions.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index ff20226..5368440 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2989,21 +2989,20 @@ struct gl_pipeline_shader_state
struct _mesa_HashTable *Objects;
 };
 
 /**
  * Compiler options for a single GLSL shaders type
  */
 struct gl_shader_compiler_options
 {
/** Driver-selectable options: */
GLboolean EmitNoLoops;
-   GLboolean EmitNoFunctions;
GLboolean EmitNoCont;  /**< Emit CONT opcode? */
GLboolean EmitNoMainReturn;/**< Emit CONT/RET opcodes? */
GLboolean EmitNoNoise; /**< Emit NOISE opcodes? */
GLboolean EmitNoPow;   /**< Emit POW opcodes? */
GLboolean EmitNoSat;   /**< Emit SAT opcodes? */
GLboolean LowerCombinedClipCullDistance; /** Lower gl_ClipDistance and
   * gl_CullDistance together from
   * float[8] to vec4[2]
   **/
 
diff --git a/src/mesa/state_tracker/st_extensions.c 
b/src/mesa/state_tracker/st_extensions.c
index 13b7ae4..ebb5d0a 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -265,21 +265,20 @@ void st_init_limits(struct pipe_screen *screen,
 
   options->EmitNoNoise = TRUE;
 
   /* TODO: make these more fine-grained if anyone needs it */
   options->MaxIfDepth =
  screen->get_shader_param(screen, sh,
   PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH);
   options->EmitNoLoops =
  !screen->get_shader_param(screen, sh,
PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH);
-  options->EmitNoFunctions = true;
   options->EmitNoMainReturn = true;
 
   options->EmitNoCont =
  !screen->get_shader_param(screen, sh,
PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED);
 
   options->EmitNoIndirectInput =
  !screen->get_shader_param(screen, sh,
PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR);
   options->EmitNoIndirectOutput =
-- 
2.7.4

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 10/14] glsl_to_tgsi: remove subroutine support

[Marek Olšák]

From: Marek Olšák 

Never used. The GLSL compiler doesn't even look at EmitNoFunctions.
---
 src/mesa/state_tracker/st_extensions.c |   6 +-
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 212 +
 2 files changed, 7 insertions(+), 211 deletions(-)

diff --git a/src/mesa/state_tracker/st_extensions.c 
b/src/mesa/state_tracker/st_extensions.c
index b87a3db..13b7ae4 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -265,24 +265,22 @@ void st_init_limits(struct pipe_screen *screen,
 
   options->EmitNoNoise = TRUE;
 
   /* TODO: make these more fine-grained if anyone needs it */
   options->MaxIfDepth =
  screen->get_shader_param(screen, sh,
   PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH);
   options->EmitNoLoops =
  !screen->get_shader_param(screen, sh,
PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH);
-  options->EmitNoFunctions =
- !screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_SUBROUTINES);
-  options->EmitNoMainReturn =
- !screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_SUBROUTINES);
+  options->EmitNoFunctions = true;
+  options->EmitNoMainReturn = true;
 
   options->EmitNoCont =
  !screen->get_shader_param(screen, sh,
PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED);
 
   options->EmitNoIndirectInput =
  !screen->get_shader_param(screen, sh,
PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR);
   options->EmitNoIndirectOutput =
  !screen->get_shader_param(screen, sh,
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 2ae15c9..293654c 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -284,21 +284,20 @@ public:
unsigned sampler_base:5;
unsigned sampler_array_size:6; /**< 1-based size of sampler array, 1 if not 
array */
unsigned tex_target:4; /**< One of TEXTURE_*_INDEX */
glsl_base_type tex_type:4;
unsigned tex_shadow:1;
unsigned image_format:9;
unsigned tex_offset_num_offset:3;
unsigned dead_mask:4; /**< Used in dead code elimination */
unsigned buffer_access:3; /**< buffer access type */
 
-   class function_entry *function; /* Set on TGSI_OPCODE_CAL or 
TGSI_OPCODE_BGNSUB */
const struct tgsi_opcode_info *info;
 };
 
 class variable_storage : public exec_node {
 public:
variable_storage(ir_variable *var, gl_register_file file, int index,
 unsigned array_id = 0)
   : file(file), index(index), component(0), var(var), array_id(array_id)
{
   assert(file != PROGRAM_ARRAY || array_id != 0);
@@ -324,52 +323,20 @@ public:
   this->size32 = size32;
   this->type = type;
}
 
/* doubles are stored across 2 gl_constant_values */
gl_constant_value values[4];
int size32; /**< Number of 32-bit components (1-4) */
int type; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
 };
 
-class function_entry : public exec_node {
-public:
-   ir_function_signature *sig;
-
-   /**
-* identifier of this function signature used by the program.
-*
-* At the point that TGSI instructions for function calls are
-* generated, we don't know the address of the first instruction of
-* the function body.  So we make the BranchTarget that is called a
-* small integer and rewrite them during set_branchtargets().
-*/
-   int sig_id;
-
-   /**
-* Pointer to first instruction of the function body.
-*
-* Set during function body emits after main() is processed.
-*/
-   glsl_to_tgsi_instruction *bgn_inst;
-
-   /**
-* Index of the first instruction of the function body in actual TGSI.
-*
-* Set after conversion from glsl_to_tgsi_instruction to TGSI.
-*/
-   int inst;
-
-   /** Storage for the return value. */
-   st_src_reg return_reg;
-};
-
 static st_src_reg undef_src = st_src_reg(PROGRAM_UNDEFINED, 0, 
GLSL_TYPE_ERROR);
 static st_dst_reg undef_dst = st_dst_reg(PROGRAM_UNDEFINED, SWIZZLE_NOOP, 
GLSL_TYPE_ERROR);
 
 struct inout_decl {
unsigned mesa_index;
unsigned array_id; /* TGSI ArrayID; 1-based: 0 means not an array */
unsigned size;
enum glsl_base_type base_type;
ubyte usage_mask; /* GLSL-style usage-mask,  i.e. single bit per double */
 };
@@ -404,22 +371,20 @@ find_array_type(struct inout_decl *decls, unsigned count, 
unsigned array_id)
 struct rename_reg_pair {
int old_reg;
int new_reg;
 };
 
 struct glsl_to_tgsi_visitor : public ir_visitor {
 public:
glsl_to_tgsi_visitor();
~glsl_to_tgsi_visitor();
 
-   function_entry *current_function;
-
struct gl_context *ctx;
struct gl_program *prog;
struct gl_shader_program *shader_program;
struct gl_linked_shader *shader;
struct gl_shader_compiler_options *options

[Mesa-dev] [PATCH 05/14] glsl_to_tgsi: reduce the size of glsl_to_tgsi_instruction using bitfields

[Marek Olšák]

From: Marek Olšák 

sizeof(glsl_to_tgsi_instruction): 464 -> 416
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 33 +++---
 1 file changed, 16 insertions(+), 17 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 78d9409..b3654fe 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -263,42 +263,41 @@ st_dst_reg::st_dst_reg(st_src_reg reg)
this->index2D = reg.index2D;
this->reladdr2 = reg.reladdr2;
this->has_index2 = reg.has_index2;
this->array_id = reg.array_id;
 }
 
 class glsl_to_tgsi_instruction : public exec_node {
 public:
DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction)
 
-   unsigned op;
st_dst_reg dst[2];
st_src_reg src[4];
-   /** Pointer to the ir source this tree came from for debugging */
-   ir_instruction *ir;
-   GLboolean cond_update;
-   bool saturate;
-   bool is_64bit_expanded;
st_src_reg sampler; /**< sampler register */
-   int sampler_base;
-   int sampler_array_size; /**< 1-based size of sampler array, 1 if not array 
*/
-   int tex_target; /**< One of TEXTURE_*_INDEX */
-   glsl_base_type tex_type;
-   GLboolean tex_shadow;
-   unsigned image_format;
-
st_src_reg tex_offsets[MAX_GLSL_TEXTURE_OFFSET];
-   unsigned tex_offset_num_offset;
-   int dead_mask; /**< Used in dead code elimination */
-
st_src_reg buffer; /**< buffer register */
-   unsigned buffer_access; /**< buffer access type */
+
+   /** Pointer to the ir source this tree came from for debugging */
+   ir_instruction *ir;
+
+   unsigned op:8; /**< TGSI opcode */
+   unsigned saturate:1;
+   unsigned is_64bit_expanded:1;
+   unsigned sampler_base:5;
+   unsigned sampler_array_size:6; /**< 1-based size of sampler array, 1 if not 
array */
+   unsigned tex_target:4; /**< One of TEXTURE_*_INDEX */
+   glsl_base_type tex_type:4;
+   unsigned tex_shadow:1;
+   unsigned image_format:9;
+   unsigned tex_offset_num_offset:3;
+   unsigned dead_mask:4; /**< Used in dead code elimination */
+   unsigned buffer_access:3; /**< buffer access type */
 
class function_entry *function; /* Set on TGSI_OPCODE_CAL or 
TGSI_OPCODE_BGNSUB */
const struct tgsi_opcode_info *info;
 };
 
 class variable_storage : public exec_node {
 public:
variable_storage(ir_variable *var, gl_register_file file, int index,
 unsigned array_id = 0)
   : file(file), index(index), component(0), var(var), array_id(array_id)
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 10/14] glsl_to_tgsi: remove subroutine support

[Marek Olšák]

On Mon, Oct 17, 2016 at 3:44 PM, Ilia Mirkin  wrote:
> nouveau supports PIPE_SHADER_CAP_SUBROUTINES and properly details with
> RET opcodes. The alternative is that the st lowers the whole thing
> into a loop which adds IMHO unnecessary complexity to the resulting
> code. Any reason not to leave that in place?

It had already been disabled and probably broken too. If you have no
interest in fixing and using it within a reasonable time frame, there
is no reason for the code to be there.

Marek
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[Mesa-dev] [PATCH] gallium/tgsi: add missing #include

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/auxiliary/tgsi/tgsi_util.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_util.h 
b/src/gallium/auxiliary/tgsi/tgsi_util.h
index ca07bfd..83a930b 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_util.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_util.h
@@ -25,20 +25,22 @@
  * 
  **/
 
 #ifndef TGSI_UTIL_H
 #define TGSI_UTIL_H
 
 #if defined __cplusplus
 extern "C" {
 #endif
 
+#include "pipe/p_shader_tokens.h"
+
 struct tgsi_src_register;
 struct tgsi_full_src_register;
 struct tgsi_full_instruction;
 
 void *
 tgsi_align_128bit(
void *unaligned );
 
 unsigned
 tgsi_util_get_src_register_swizzle(
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 10/14] glsl_to_tgsi: remove subroutine support

[Ilia Mirkin]

On Mon, Oct 17, 2016 at 9:46 AM, Marek Olšák  wrote:
> On Mon, Oct 17, 2016 at 3:44 PM, Ilia Mirkin  wrote:
>> nouveau supports PIPE_SHADER_CAP_SUBROUTINES and properly details with
>> RET opcodes. The alternative is that the st lowers the whole thing
>> into a loop which adds IMHO unnecessary complexity to the resulting
>> code. Any reason not to leave that in place?
>
> It had already been disabled and probably broken too. If you have no
> interest in fixing and using it within a reasonable time frame, there
> is no reason for the code to be there.

What's broken about it? To the best of my knowledge, it's working
fine. I'm specifically talking about RET (from the "MAIN" function),
not subroutines in general.
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[Mesa-dev] [PATCH 3/6] gallium/radeon: simplify initialization of 64-bit gallivm builders

[Marek Olšák]

From: Marek Olšák 

---
 .../drivers/radeon/radeon_setup_tgsi_llvm.c| 22 --
 1 file changed, 4 insertions(+), 18 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c 
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 2d424d5..c06eb3e 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -1061,38 +1061,24 @@ void radeon_llvm_context_init(struct 
radeon_llvm_context *ctx, const char *tripl
type.floating = true;
type.fixed = false;
type.sign = true;
type.norm = false;
type.width = 32;
type.length = 1;
 
lp_build_context_init(&bld_base->base, &ctx->gallivm, type);
lp_build_context_init(&ctx->soa.bld_base.uint_bld, &ctx->gallivm, 
lp_uint_type(type));
lp_build_context_init(&ctx->soa.bld_base.int_bld, &ctx->gallivm, 
lp_int_type(type));
-   {
-   struct lp_type dbl_type;
-   dbl_type = type;
-   dbl_type.width *= 2;
-   lp_build_context_init(&ctx->soa.bld_base.dbl_bld, 
&ctx->gallivm, dbl_type);
-   }
-   {
-   struct lp_type dtype;
-   dtype = lp_uint_type(type);
-   dtype.width *= 2;
-   lp_build_context_init(&ctx->soa.bld_base.uint64_bld, 
&ctx->gallivm, dtype);
-   }
-   {
-   struct lp_type dtype;
-   dtype = lp_int_type(type);
-   dtype.width *= 2;
-   lp_build_context_init(&ctx->soa.bld_base.int64_bld, 
&ctx->gallivm, dtype);
-   }
+   type.width *= 2;
+   lp_build_context_init(&ctx->soa.bld_base.dbl_bld, &ctx->gallivm, type);
+   lp_build_context_init(&ctx->soa.bld_base.uint64_bld, &ctx->gallivm, 
lp_uint_type(type));
+   lp_build_context_init(&ctx->soa.bld_base.int64_bld, &ctx->gallivm, 
lp_int_type(type));
 
bld_base->soa = 1;
bld_base->emit_store = radeon_llvm_emit_store;
bld_base->emit_swizzle = emit_swizzle;
bld_base->emit_declaration = emit_declaration;
bld_base->emit_immediate = emit_immediate;
 
bld_base->emit_fetch_funcs[TGSI_FILE_IMMEDIATE] = 
radeon_llvm_emit_fetch;
bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = radeon_llvm_emit_fetch;
bld_base->emit_fetch_funcs[TGSI_FILE_TEMPORARY] = 
radeon_llvm_emit_fetch;
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 10/14] glsl_to_tgsi: remove subroutine support

[Marek Olšák]

On Mon, Oct 17, 2016 at 3:48 PM, Ilia Mirkin  wrote:
> On Mon, Oct 17, 2016 at 9:46 AM, Marek Olšák  wrote:
>> On Mon, Oct 17, 2016 at 3:44 PM, Ilia Mirkin  wrote:
>>> nouveau supports PIPE_SHADER_CAP_SUBROUTINES and properly details with
>>> RET opcodes. The alternative is that the st lowers the whole thing
>>> into a loop which adds IMHO unnecessary complexity to the resulting
>>> code. Any reason not to leave that in place?
>>
>> It had already been disabled and probably broken too. If you have no
>> interest in fixing and using it within a reasonable time frame, there
>> is no reason for the code to be there.
>
> What's broken about it? To the best of my knowledge, it's working
> fine. I'm specifically talking about RET (from the "MAIN" function),
> not subroutines in general.

OK. I thought you were talking about subroutines.

The RET opcode support can stay there if somebody wants it very much.

However, have you seen any apps using "return" in "main"?
Is there any serious performance concern with lowering "return" to a
conditional branch, such that it's beneficial for drivers to implement
RET?
If so, shouldn't it be fixed in the GLSL compiler instead?
Is it worth having a rarely-used codepath in glsl_to_tgsi that most
drivers skip anyway?

Marek
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Re: [Mesa-dev] [PATCH] gallium/hud: Sensor extension is segfaulting.

[Brian Paul]

For the subject line we usually say what we're fixing.  I'd suggest 
something like "gallium/hud: fix segfault in sensor extension code".


-Brian

On 10/13/2016 11:29 AM, Steven Toth wrote:

Round two of the patchset, incorporating feedback
from nhaeh...@gmail.com

The fixes in this set address bugfix #68169, HUD crashing
when testing with unigine (heaven).

The bug also manifested itself as a lack of data in
HUD charts when multiple instanced were created and
destroyed in a specific order, a use case not witnessed
with glxgears.

These patches:
1. mutex protect the internal object lists.
2. reference count object access for destruction purposes.

Patchset tested with glxgears/demo and unigine.

Signed-off-by: Steven Toth 



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[Mesa-dev] [PATCH 6/6] radeonsi: rename prefixes from radeon to si

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_pipe.c |   2 +-
 src/gallium/drivers/radeonsi/si_shader.c   |  96 ++---
 src/gallium/drivers/radeonsi/si_shader_internal.h  |  70 +-
 .../drivers/radeonsi/si_shader_tgsi_setup.c| 150 ++---
 4 files changed, 159 insertions(+), 159 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 7924375..a9faa75 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -119,21 +119,21 @@ static void si_emit_string_marker(struct pipe_context 
*ctx,
struct si_context *sctx = (struct si_context *)ctx;
 
dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 }
 
 static LLVMTargetMachineRef
 si_create_llvm_target_machine(struct si_screen *sscreen)
 {
const char *triple = "amdgcn--";
 
-   return LLVMCreateTargetMachine(radeon_llvm_get_r600_target(triple), 
triple,
+   return LLVMCreateTargetMachine(si_llvm_get_amdgpu_target(triple), 
triple,
   
r600_get_llvm_processor_name(sscreen->b.family),
 #if HAVE_LLVM >= 0x0308
   sscreen->b.debug_flags & DBG_SI_SCHED ?
   SI_LLVM_DEFAULT_FEATURES 
",+si-scheduler" :
 #endif
   SI_LLVM_DEFAULT_FEATURES,
   LLVMCodeGenLevelDefault,
   LLVMRelocDefault,
   LLVMCodeModelDefault);
 }
diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index bca07ac..cbf2090 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -478,21 +478,21 @@ static LLVMValueRef get_bounded_indirect_index(struct 
si_shader_context *ctx,
 {
LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
 
/* LLVM 3.8: If indirect resource indexing is used:
 * - SI & CIK hang
 * - VI crashes
 */
if (HAVE_LLVM <= 0x0308)
return LLVMGetUndef(ctx->i32);
 
-   return radeon_llvm_bound_index(ctx, result, num);
+   return si_llvm_bound_index(ctx, result, num);
 }
 
 
 /**
  * Calculate a dword address given an input or output register and a stride.
  */
 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
   const struct tgsi_full_dst_register *dst,
   const struct tgsi_full_src_register *src,
   LLVMValueRef vertex_dw_stride,
@@ -869,21 +869,21 @@ static LLVMValueRef buffer_load(struct 
lp_build_tgsi_context *bld_base,
return LLVMBuildExtractElement(gallivm->builder, value,
lp_build_const_int32(gallivm, swizzle), "");
}
 
value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
  swizzle * 4, 1, 0);
 
value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
   swizzle * 4 + 4, 1, 0);
 
-   return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
+   return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
 }
 
 /**
  * Load from LDS.
  *
  * \param type output value type
  * \param swizzle  offset (typically 0..3); it can be ~0, which loads a 
vec4
  * \param dw_addr  address in dwords
  */
 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
@@ -906,21 +906,21 @@ static LLVMValueRef lds_load(struct lp_build_tgsi_context 
*bld_base,
 
dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
lp_build_const_int32(gallivm, swizzle));
 
value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
if (tgsi_type_is_64bit(type)) {
LLVMValueRef value2;
dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
   lp_build_const_int32(gallivm, swizzle + 
1));
value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
-   return radeon_llvm_emit_fetch_64bit(bld_base, type, value, 
value2);
+   return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
}
 
return LLVMBuildBitCast(gallivm->builder, value,
tgsi2llvmtype(bld_base, type), "");
 }
 
 /**
  * Store to LDS.
  *
  * \param swizzle  offset (typically 0..3)
@@ -1008,21 +1008,21 @@ static void store_output_tcs(struct 
lp_build_tgsi_context *bld_base,
unsigned chan_index;
LLVMValueRef dw_addr, stride;
LLVMValueRef rw_buffers, buffer, base, buf_addr;
LLVMValueRef values[4];
 
/* Only handle per-patch and per-vertex outputs here.
 *

Re: [Mesa-dev] [PATCH 09/14] mesa_to_tgsi: remove remnants of flow control and subroutine support

[Ilia Mirkin]

Patches 1-9 are Reviewed-by: Ilia Mirkin 

On Mon, Oct 17, 2016 at 9:39 AM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> ---
>  src/mesa/state_tracker/st_mesa_to_tgsi.c | 93 
> +---
>  1 file changed, 1 insertion(+), 92 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.c 
> b/src/mesa/state_tracker/st_mesa_to_tgsi.c
> index c8ed26c..4c26d92 100644
> --- a/src/mesa/state_tracker/st_mesa_to_tgsi.c
> +++ b/src/mesa/state_tracker/st_mesa_to_tgsi.c
> @@ -44,116 +44,42 @@
>  #include "util/u_debug.h"
>  #include "util/u_math.h"
>  #include "util/u_memory.h"
>  #include "st_glsl_to_tgsi.h" /* for _mesa_sysval_to_semantic */
>
>
>  #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) |\
> (1 << PROGRAM_CONSTANT) | \
> (1 << PROGRAM_UNIFORM))
>
> -
> -struct label {
> -   unsigned branch_target;
> -   unsigned token;
> -};
> -
> -
>  /**
>   * Intermediate state used during shader translation.
>   */
>  struct st_translate {
> struct ureg_program *ureg;
>
> struct ureg_dst temps[MAX_PROGRAM_TEMPS];
> struct ureg_src *constants;
> struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
> struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
> struct ureg_dst address[1];
> struct ureg_src samplers[PIPE_MAX_SAMPLERS];
> struct ureg_src systemValues[SYSTEM_VALUE_MAX];
>
> const GLuint *inputMapping;
> const GLuint *outputMapping;
>
> -   /* For every instruction that contains a label (eg CALL), keep
> -* details so that we can go back afterwards and emit the correct
> -* tgsi instruction number for each label.
> -*/
> -   struct label *labels;
> -   unsigned labels_size;
> -   unsigned labels_count;
> -
> -   /* Keep a record of the tgsi instruction number that each mesa
> -* instruction starts at, will be used to fix up labels after
> -* translation.
> -*/
> -   unsigned *insn;
> -   unsigned insn_size;
> -   unsigned insn_count;
> -
> unsigned procType;  /**< PIPE_SHADER_VERTEX/FRAGMENT */
> -
> -   boolean error;
>  };
>
>
>  /**
> - * Make note of a branch to a label in the TGSI code.
> - * After we've emitted all instructions, we'll go over the list
> - * of labels built here and patch the TGSI code with the actual
> - * location of each label.
> - */
> -static unsigned *get_label( struct st_translate *t,
> -unsigned branch_target )
> -{
> -   unsigned i;
> -
> -   if (t->labels_count + 1 >= t->labels_size) {
> -  t->labels_size = 1 << (util_logbase2(t->labels_size) + 1);
> -  t->labels = realloc(t->labels, t->labels_size * sizeof t->labels[0]);
> -  if (t->labels == NULL) {
> - static unsigned dummy;
> - t->error = TRUE;
> - return &dummy;
> -  }
> -   }
> -
> -   i = t->labels_count++;
> -   t->labels[i].branch_target = branch_target;
> -   return &t->labels[i].token;
> -}
> -
> -
> -/**
> - * Called prior to emitting the TGSI code for each Mesa instruction.
> - * Allocate additional space for instructions if needed.
> - * Update the insn[] array so the next Mesa instruction points to
> - * the next TGSI instruction.
> - */
> -static void set_insn_start( struct st_translate *t,
> -unsigned start )
> -{
> -   if (t->insn_count + 1 >= t->insn_size) {
> -  t->insn_size = 1 << (util_logbase2(t->insn_size) + 1);
> -  t->insn = realloc(t->insn, t->insn_size * sizeof t->insn[0]);
> -  if (t->insn == NULL) {
> - t->error = TRUE;
> - return;
> -  }
> -   }
> -
> -   t->insn[t->insn_count++] = start;
> -}
> -
> -
> -/**
>   * Map a Mesa dst register to a TGSI ureg_dst register.
>   */
>  static struct ureg_dst
>  dst_register( struct st_translate *t,
>gl_register_file file,
>GLuint index )
>  {
> switch( file ) {
> case PROGRAM_UNDEFINED:
>return ureg_dst_undef();
> @@ -1088,34 +1014,17 @@ st_translate_mesa_program(
>  TGSI_RETURN_TYPE_FLOAT,
>  TGSI_RETURN_TYPE_FLOAT,
>  TGSI_RETURN_TYPE_FLOAT,
>  TGSI_RETURN_TYPE_FLOAT);
>
>}
> }
>
> /* Emit each instruction in turn:
>  */
> -   for (i = 0; i < program->NumInstructions; i++) {
> -  set_insn_start( t, ureg_get_instruction_number( ureg ));
> +   for (i = 0; i < program->NumInstructions; i++)
>compile_instruction(ctx, t, &program->Instructions[i]);
> -   }
> -
> -   /* Fix up all emitted labels:
> -*/
> -   for (i = 0; i < t->labels_count; i++) {
> -  ureg_fixup_label( ureg,
> -t->labels[i].token,
> -t->insn[t->labels[i].branch_target] );
> -   }
>
>  out:
> -   free(t->insn);
> -   free(t->labels);
> free(t->constants);
> -
> -   if (t->error) {
> -  debug_printf("%s: translate error flag set\n", __func__);
> -   }
>

Re: [Mesa-dev] [PATCH 10/14] glsl_to_tgsi: remove subroutine support

[Ilia Mirkin]

On Mon, Oct 17, 2016 at 9:59 AM, Marek Olšák  wrote:
> On Mon, Oct 17, 2016 at 3:48 PM, Ilia Mirkin  wrote:
>> On Mon, Oct 17, 2016 at 9:46 AM, Marek Olšák  wrote:
>>> On Mon, Oct 17, 2016 at 3:44 PM, Ilia Mirkin  wrote:
 nouveau supports PIPE_SHADER_CAP_SUBROUTINES and properly details with
 RET opcodes. The alternative is that the st lowers the whole thing
 into a loop which adds IMHO unnecessary complexity to the resulting
 code. Any reason not to leave that in place?
>>>
>>> It had already been disabled and probably broken too. If you have no
>>> interest in fixing and using it within a reasonable time frame, there
>>> is no reason for the code to be there.
>>
>> What's broken about it? To the best of my knowledge, it's working
>> fine. I'm specifically talking about RET (from the "MAIN" function),
>> not subroutines in general.
>
> OK. I thought you were talking about subroutines.
>
> The RET opcode support can stay there if somebody wants it very much.
>
> However, have you seen any apps using "return" in "main"?

Yes. Among other things, a lot of compute shaders do if (foo) return;
somewhere at the top. See this example from F1 2015:
http://hastebin.com/vacevigoyi.go - I've seen it in the middle too
though.

> Is there any serious performance concern with lowering "return" to a
> conditional branch, such that it's beneficial for drivers to implement
> RET?

Depends on the driver. Nouveau's control flow analysis isn't extremely
sophisticated to undo the lowering that the GLSL compiler does. Which
means extra instructions, and extra RA complexity since the whole main
function ends up inside a loop.

> If so, shouldn't it be fixed in the GLSL compiler instead?

Well, from what I recall, the GLSL compiler's lowering goes something like

void main() {
  if (foo) return;
  ...
}

to

void main() {
  while (true) {
 if (foo)
break;
 ...
 break;
  }
}

With additional complexity if the return is inside a for/while loop itself.

> Is it worth having a rarely-used codepath in glsl_to_tgsi that most
> drivers skip anyway?

It's 2 lines of code... one to stop the GLSL compiler from doing the
lowering, and another to emit the RET opcode when you see the
ir_op_return or whatever it's called. IMHO not such a great burden.

All the other subroutines stuff can go as far as I'm concerned, I
doubt anyone will care to implement glsl subroutines that way.

  -ilia
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Re: [Mesa-dev] [PATCH 10/14] glsl_to_tgsi: remove subroutine support

[Marek Olšák]

On Mon, Oct 17, 2016 at 4:10 PM, Ilia Mirkin  wrote:
> On Mon, Oct 17, 2016 at 9:59 AM, Marek Olšák  wrote:
>> On Mon, Oct 17, 2016 at 3:48 PM, Ilia Mirkin  wrote:
>>> On Mon, Oct 17, 2016 at 9:46 AM, Marek Olšák  wrote:
 On Mon, Oct 17, 2016 at 3:44 PM, Ilia Mirkin  wrote:
> nouveau supports PIPE_SHADER_CAP_SUBROUTINES and properly details with
> RET opcodes. The alternative is that the st lowers the whole thing
> into a loop which adds IMHO unnecessary complexity to the resulting
> code. Any reason not to leave that in place?

 It had already been disabled and probably broken too. If you have no
 interest in fixing and using it within a reasonable time frame, there
 is no reason for the code to be there.
>>>
>>> What's broken about it? To the best of my knowledge, it's working
>>> fine. I'm specifically talking about RET (from the "MAIN" function),
>>> not subroutines in general.
>>
>> OK. I thought you were talking about subroutines.
>>
>> The RET opcode support can stay there if somebody wants it very much.
>>
>> However, have you seen any apps using "return" in "main"?
>
> Yes. Among other things, a lot of compute shaders do if (foo) return;
> somewhere at the top. See this example from F1 2015:
> http://hastebin.com/vacevigoyi.go - I've seen it in the middle too
> though.
>
>> Is there any serious performance concern with lowering "return" to a
>> conditional branch, such that it's beneficial for drivers to implement
>> RET?
>
> Depends on the driver. Nouveau's control flow analysis isn't extremely
> sophisticated to undo the lowering that the GLSL compiler does. Which
> means extra instructions, and extra RA complexity since the whole main
> function ends up inside a loop.
>
>> If so, shouldn't it be fixed in the GLSL compiler instead?
>
> Well, from what I recall, the GLSL compiler's lowering goes something like
>
> void main() {
>   if (foo) return;
>   ...
> }
>
> to
>
> void main() {
>   while (true) {
>  if (foo)
> break;
>  ...
>  break;
>   }
> }
>
> With additional complexity if the return is inside a for/while loop itself.
>
>> Is it worth having a rarely-used codepath in glsl_to_tgsi that most
>> drivers skip anyway?
>
> It's 2 lines of code... one to stop the GLSL compiler from doing the
> lowering, and another to emit the RET opcode when you see the
> ir_op_return or whatever it's called. IMHO not such a great burden.
>
> All the other subroutines stuff can go as far as I'm concerned, I
> doubt anyone will care to implement glsl subroutines that way.
>
>   -ilia

OK, sounds good.

Marek
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Re: [Mesa-dev] [PATCH 10/14] glsl_to_tgsi: remove subroutine support

[Marek Olšák]

I'm adding back this:

   options->EmitNoMainReturn =
  !screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_SUBROUTINES);

And:

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 293654c..5f28d07 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -4176,7 +4176,9 @@ glsl_to_tgsi_visitor::visit(ir_texture *ir)
 void
 glsl_to_tgsi_visitor::visit(ir_return *ir)
 {
-   assert(0);
+   assert(!ir->get_value());
+
+   emit_asm(ir, TGSI_OPCODE_RET);
 }

 void
@@ -4416,7 +4418,8 @@ glsl_to_tgsi_visitor::simplify_cmp(void)
   inst->dst[1].reladdr || inst->dst[1].reladdr2 ||
   tgsi_get_opcode_info(inst->op)->is_branch ||
   inst->op == TGSI_OPCODE_CONT ||
-  inst->op == TGSI_OPCODE_END) {
+  inst->op == TGSI_OPCODE_END ||
+  inst->op == TGSI_OPCODE_RET) {
  break;
   }


Hopefully that should restore the RET support.

Marek


On Mon, Oct 17, 2016 at 4:12 PM, Marek Olšák  wrote:
> On Mon, Oct 17, 2016 at 4:10 PM, Ilia Mirkin  wrote:
>> On Mon, Oct 17, 2016 at 9:59 AM, Marek Olšák  wrote:
>>> On Mon, Oct 17, 2016 at 3:48 PM, Ilia Mirkin  wrote:
 On Mon, Oct 17, 2016 at 9:46 AM, Marek Olšák  wrote:
> On Mon, Oct 17, 2016 at 3:44 PM, Ilia Mirkin  wrote:
>> nouveau supports PIPE_SHADER_CAP_SUBROUTINES and properly details with
>> RET opcodes. The alternative is that the st lowers the whole thing
>> into a loop which adds IMHO unnecessary complexity to the resulting
>> code. Any reason not to leave that in place?
>
> It had already been disabled and probably broken too. If you have no
> interest in fixing and using it within a reasonable time frame, there
> is no reason for the code to be there.

 What's broken about it? To the best of my knowledge, it's working
 fine. I'm specifically talking about RET (from the "MAIN" function),
 not subroutines in general.
>>>
>>> OK. I thought you were talking about subroutines.
>>>
>>> The RET opcode support can stay there if somebody wants it very much.
>>>
>>> However, have you seen any apps using "return" in "main"?
>>
>> Yes. Among other things, a lot of compute shaders do if (foo) return;
>> somewhere at the top. See this example from F1 2015:
>> http://hastebin.com/vacevigoyi.go - I've seen it in the middle too
>> though.
>>
>>> Is there any serious performance concern with lowering "return" to a
>>> conditional branch, such that it's beneficial for drivers to implement
>>> RET?
>>
>> Depends on the driver. Nouveau's control flow analysis isn't extremely
>> sophisticated to undo the lowering that the GLSL compiler does. Which
>> means extra instructions, and extra RA complexity since the whole main
>> function ends up inside a loop.
>>
>>> If so, shouldn't it be fixed in the GLSL compiler instead?
>>
>> Well, from what I recall, the GLSL compiler's lowering goes something like
>>
>> void main() {
>>   if (foo) return;
>>   ...
>> }
>>
>> to
>>
>> void main() {
>>   while (true) {
>>  if (foo)
>> break;
>>  ...
>>  break;
>>   }
>> }
>>
>> With additional complexity if the return is inside a for/while loop itself.
>>
>>> Is it worth having a rarely-used codepath in glsl_to_tgsi that most
>>> drivers skip anyway?
>>
>> It's 2 lines of code... one to stop the GLSL compiler from doing the
>> lowering, and another to emit the RET opcode when you see the
>> ir_op_return or whatever it's called. IMHO not such a great burden.
>>
>> All the other subroutines stuff can go as far as I'm concerned, I
>> doubt anyone will care to implement glsl subroutines that way.
>>
>>   -ilia
>
> OK, sounds good.
>
> Marek
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Re: [Mesa-dev] [PATCH 3/5] st/va: Return surface formats depending on config chroma format

[Julien Isorce]

Hi Mark,

Thx for the patch. I can see it has already landed.

I just tried it with gstreamer-vaapi and it causes problem since they
create the config like this for VPP:

va_status = vaCreateConfig (filter->va_display, VAProfileNone,
  VAEntrypointVideoProc, NULL, 0, &filter->va_config);

As you can see num attrivs is 0 so it makes vaQuerySurfaceAttributes to
return no supported format
because config->rt_format is 0.

So I plan to make a patch that looks like this:


--- a/src/gallium/state_trackers/va/surface.c
+++ b/src/gallium/state_trackers/va/surface.c
@@ -419,7 +419,7 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx,
VAConfigID config_id,
/* vlVaCreateConfig returns PIPE_VIDEO_PROFILE_UNKNOWN
 * only for VAEntrypointVideoProc. */
if (config->profile == PIPE_VIDEO_PROFILE_UNKNOWN) {
-  if (config->rt_format == VA_RT_FORMAT_RGB32) {
+  if (!config->rt_format || config->rt_format == VA_RT_FORMAT_RGB32) {
  for (j = 0; j < ARRAY_SIZE(vpp_surface_formats); ++j) {
 attribs[i].type = VASurfaceAttribPixelFormat;
 attribs[i].value.type = VAGenericValueTypeInteger;
@@ -427,7 +427,8 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx,
VAConfigID config_id,
 attribs[i].value.value.i =
PipeFormatToVaFourcc(vpp_surface_formats[j]);
 i++;
  }
-  } else if (config->rt_format == VA_RT_FORMAT_YUV420) {
+  }
+  if (!config->rt_format || config->rt_format == VA_RT_FORMAT_YUV420) {
  attribs[i].type = VASurfaceAttribPixelFormat;
  attribs[i].value.type = VAGenericValueTypeInteger;
  attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE |
VA_SURFACE_ATTRIB_SETTABLE;


Will it be ok for whatever test application you are using ?

Not that the intel va driver always return the full list for vpp.

Cheers
Julien







On 12 October 2016 at 23:53, Mark Thompson  wrote:

> This makes the supported format actually match the configuration, and
> allows the user to observe that NV12 is supported for video processing
> where previously they couldn't (though it did always work if they
> blindly tried to use it anyway).
> ---
>  src/gallium/state_trackers/va/surface.c | 12 ++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/state_trackers/va/surface.c
> b/src/gallium/state_trackers/va/surface.c
> index 173e7d9..5e92980 100644
> --- a/src/gallium/state_trackers/va/surface.c
> +++ b/src/gallium/state_trackers/va/surface.c
> @@ -419,11 +419,19 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx,
> VAConfigID config_id,
> /* vlVaCreateConfig returns PIPE_VIDEO_PROFILE_UNKNOWN
>  * only for VAEntrypointVideoProc. */
> if (config->profile == PIPE_VIDEO_PROFILE_UNKNOWN) {
> -  for (j = 0; j < ARRAY_SIZE(vpp_surface_formats); ++j) {
> +  if (config->rt_format == VA_RT_FORMAT_RGB32) {
> + for (j = 0; j < ARRAY_SIZE(vpp_surface_formats); ++j) {
> +attribs[i].type = VASurfaceAttribPixelFormat;
> +attribs[i].value.type = VAGenericValueTypeInteger;
> +attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE |
> VA_SURFACE_ATTRIB_SETTABLE;
> +attribs[i].value.value.i = PipeFormatToVaFourcc(vpp_
> surface_formats[j]);
> +i++;
> + }
> +  } else if (config->rt_format == VA_RT_FORMAT_YUV420) {
>   attribs[i].type = VASurfaceAttribPixelFormat;
>   attribs[i].value.type = VAGenericValueTypeInteger;
>   attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE |
> VA_SURFACE_ATTRIB_SETTABLE;
> - attribs[i].value.value.i = PipeFormatToVaFourcc(vpp_
> surface_formats[j]);
> + attribs[i].value.value.i = VA_FOURCC_NV12;
>   i++;
>}
> } else {
> --
> 2.9.3
>
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Re: [Mesa-dev] [PATCH 10/14] glsl_to_tgsi: remove subroutine support

[Ilia Mirkin]

On Mon, Oct 17, 2016 at 10:20 AM, Marek Olšák  wrote:
> I'm adding back this:
>
>options->EmitNoMainReturn =
>   !screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_SUBROUTINES);
>
> And:
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index 293654c..5f28d07 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -4176,7 +4176,9 @@ glsl_to_tgsi_visitor::visit(ir_texture *ir)
>  void
>  glsl_to_tgsi_visitor::visit(ir_return *ir)
>  {
> -   assert(0);
> +   assert(!ir->get_value());
> +
> +   emit_asm(ir, TGSI_OPCODE_RET);
>  }
>
>  void
> @@ -4416,7 +4418,8 @@ glsl_to_tgsi_visitor::simplify_cmp(void)
>inst->dst[1].reladdr || inst->dst[1].reladdr2 ||
>tgsi_get_opcode_info(inst->op)->is_branch ||
>inst->op == TGSI_OPCODE_CONT ||
> -  inst->op == TGSI_OPCODE_END) {
> +  inst->op == TGSI_OPCODE_END ||
> +  inst->op == TGSI_OPCODE_RET) {
>   break;
>}
>
>
> Hopefully that should restore the RET support.

Thanks. I think that should be enough. I won't be able to test
anything today, in all likelihood, but probably could tomorrow.
Perhaps Samuel will have time to play with it.

  -ilia
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[Mesa-dev] [PATCH 10/14] glsl_to_tgsi: remove subroutine support

[Marek Olšák]

From: Marek Olšák 

Never used. The GLSL compiler doesn't even look at EmitNoFunctions.

v2: add back "return" support in "main"
---
 src/mesa/state_tracker/st_extensions.c |   3 +-
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 207 +
 2 files changed, 5 insertions(+), 205 deletions(-)

diff --git a/src/mesa/state_tracker/st_extensions.c 
b/src/mesa/state_tracker/st_extensions.c
index b87a3db..6ed00ab 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -265,22 +265,21 @@ void st_init_limits(struct pipe_screen *screen,
 
   options->EmitNoNoise = TRUE;
 
   /* TODO: make these more fine-grained if anyone needs it */
   options->MaxIfDepth =
  screen->get_shader_param(screen, sh,
   PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH);
   options->EmitNoLoops =
  !screen->get_shader_param(screen, sh,
PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH);
-  options->EmitNoFunctions =
- !screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_SUBROUTINES);
+  options->EmitNoFunctions = true;
   options->EmitNoMainReturn =
  !screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_SUBROUTINES);
 
   options->EmitNoCont =
  !screen->get_shader_param(screen, sh,
PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED);
 
   options->EmitNoIndirectInput =
  !screen->get_shader_param(screen, sh,
PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR);
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 2ae15c9..5f28d07 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -284,21 +284,20 @@ public:
unsigned sampler_base:5;
unsigned sampler_array_size:6; /**< 1-based size of sampler array, 1 if not 
array */
unsigned tex_target:4; /**< One of TEXTURE_*_INDEX */
glsl_base_type tex_type:4;
unsigned tex_shadow:1;
unsigned image_format:9;
unsigned tex_offset_num_offset:3;
unsigned dead_mask:4; /**< Used in dead code elimination */
unsigned buffer_access:3; /**< buffer access type */
 
-   class function_entry *function; /* Set on TGSI_OPCODE_CAL or 
TGSI_OPCODE_BGNSUB */
const struct tgsi_opcode_info *info;
 };
 
 class variable_storage : public exec_node {
 public:
variable_storage(ir_variable *var, gl_register_file file, int index,
 unsigned array_id = 0)
   : file(file), index(index), component(0), var(var), array_id(array_id)
{
   assert(file != PROGRAM_ARRAY || array_id != 0);
@@ -324,52 +323,20 @@ public:
   this->size32 = size32;
   this->type = type;
}
 
/* doubles are stored across 2 gl_constant_values */
gl_constant_value values[4];
int size32; /**< Number of 32-bit components (1-4) */
int type; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
 };
 
-class function_entry : public exec_node {
-public:
-   ir_function_signature *sig;
-
-   /**
-* identifier of this function signature used by the program.
-*
-* At the point that TGSI instructions for function calls are
-* generated, we don't know the address of the first instruction of
-* the function body.  So we make the BranchTarget that is called a
-* small integer and rewrite them during set_branchtargets().
-*/
-   int sig_id;
-
-   /**
-* Pointer to first instruction of the function body.
-*
-* Set during function body emits after main() is processed.
-*/
-   glsl_to_tgsi_instruction *bgn_inst;
-
-   /**
-* Index of the first instruction of the function body in actual TGSI.
-*
-* Set after conversion from glsl_to_tgsi_instruction to TGSI.
-*/
-   int inst;
-
-   /** Storage for the return value. */
-   st_src_reg return_reg;
-};
-
 static st_src_reg undef_src = st_src_reg(PROGRAM_UNDEFINED, 0, 
GLSL_TYPE_ERROR);
 static st_dst_reg undef_dst = st_dst_reg(PROGRAM_UNDEFINED, SWIZZLE_NOOP, 
GLSL_TYPE_ERROR);
 
 struct inout_decl {
unsigned mesa_index;
unsigned array_id; /* TGSI ArrayID; 1-based: 0 means not an array */
unsigned size;
enum glsl_base_type base_type;
ubyte usage_mask; /* GLSL-style usage-mask,  i.e. single bit per double */
 };
@@ -404,22 +371,20 @@ find_array_type(struct inout_decl *decls, unsigned count, 
unsigned array_id)
 struct rename_reg_pair {
int old_reg;
int new_reg;
 };
 
 struct glsl_to_tgsi_visitor : public ir_visitor {
 public:
glsl_to_tgsi_visitor();
~glsl_to_tgsi_visitor();
 
-   function_entry *current_function;
-
struct gl_context *ctx;
struct gl_program *prog;
struct gl_shader_program *shader_program;
struct gl_linked_shader *shader;
struct gl_shader_compiler_options *options;
 
int next_temp;
 
unsigned *array_sizes;
unsigned max_num_arrays;
@@ -44

Re: [Mesa-dev] [PATCH 10/14] glsl_to_tgsi: remove subroutine support

[Marek Olšák]

On Mon, Oct 17, 2016 at 4:23 PM, Ilia Mirkin  wrote:
> On Mon, Oct 17, 2016 at 10:20 AM, Marek Olšák  wrote:
>> I'm adding back this:
>>
>>options->EmitNoMainReturn =
>>   !screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_SUBROUTINES);
>>
>> And:
>>
>> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
>> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
>> index 293654c..5f28d07 100644
>> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
>> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
>> @@ -4176,7 +4176,9 @@ glsl_to_tgsi_visitor::visit(ir_texture *ir)
>>  void
>>  glsl_to_tgsi_visitor::visit(ir_return *ir)
>>  {
>> -   assert(0);
>> +   assert(!ir->get_value());
>> +
>> +   emit_asm(ir, TGSI_OPCODE_RET);
>>  }
>>
>>  void
>> @@ -4416,7 +4418,8 @@ glsl_to_tgsi_visitor::simplify_cmp(void)
>>inst->dst[1].reladdr || inst->dst[1].reladdr2 ||
>>tgsi_get_opcode_info(inst->op)->is_branch ||
>>inst->op == TGSI_OPCODE_CONT ||
>> -  inst->op == TGSI_OPCODE_END) {
>> +  inst->op == TGSI_OPCODE_END ||
>> +  inst->op == TGSI_OPCODE_RET) {
>>   break;
>>}
>>
>>
>> Hopefully that should restore the RET support.
>
> Thanks. I think that should be enough. I won't be able to test
> anything today, in all likelihood, but probably could tomorrow.
> Perhaps Samuel will have time to play with it.

No worries. I've tested it on softpipe.

Marek
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Re: [Mesa-dev] [PATCH 13/14] mesa: remove gl_shader_compiler_options::EmitNoMainReturn

[Marek Olšák]

Please ignore this patch. Nouveau wants to support "return" in "main".

Marek

On Mon, Oct 17, 2016 at 3:39 PM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> it's always true
> ---
>  src/mesa/drivers/dri/i915/i915_context.c   | 1 -
>  src/mesa/drivers/dri/i965/brw_compiler.c   | 1 -
>  src/mesa/main/mtypes.h | 1 -
>  src/mesa/program/ir_to_mesa.cpp| 9 -
>  src/mesa/state_tracker/st_extensions.c | 1 -
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +-
>  6 files changed, 5 insertions(+), 10 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i915/i915_context.c 
> b/src/mesa/drivers/dri/i915/i915_context.c
> index 83aaf9e..a7604a1 100644
> --- a/src/mesa/drivers/dri/i915/i915_context.c
> +++ b/src/mesa/drivers/dri/i915/i915_context.c
> @@ -255,21 +255,20 @@ i915CreateContext(int api,
>  * FINISHME: vertex shaders?
>  */
> 
> ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].EmitNoIndirectSampler =
>true;
>
> struct gl_shader_compiler_options *const fs_options =
>& ctx->Const.ShaderCompilerOptions[MESA_SHADER_FRAGMENT];
> fs_options->MaxIfDepth = 0;
> fs_options->EmitNoNoise = true;
> fs_options->EmitNoPow = true;
> -   fs_options->EmitNoMainReturn = true;
> fs_options->EmitNoIndirectInput = true;
> fs_options->EmitNoIndirectOutput = true;
> fs_options->EmitNoIndirectUniform = true;
> fs_options->EmitNoIndirectTemp = true;
> fs_options->EmitNoIndirectSampler = true;
>
> ctx->Const.MaxDrawBuffers = 1;
> ctx->Const.QueryCounterBits.SamplesPassed = 0;
>
> _tnl_init_vertices(ctx, ctx->Const.MaxArrayLockSize + 12,
> diff --git a/src/mesa/drivers/dri/i965/brw_compiler.c 
> b/src/mesa/drivers/dri/i965/brw_compiler.c
> index 86b1eaa..27cbd40 100644
> --- a/src/mesa/drivers/dri/i965/brw_compiler.c
> +++ b/src/mesa/drivers/dri/i965/brw_compiler.c
> @@ -117,21 +117,20 @@ brw_compiler_create(void *mem_ctx, const struct 
> gen_device_info *devinfo)
> compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
> compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
>
> /* We want the GLSL compiler to emit code that uses condition codes */
> for (int i = 0; i < MESA_SHADER_STAGES; i++) {
>compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
>compiler->glsl_compiler_options[i].MaxIfDepth =
>   devinfo->gen < 6 ? 16 : UINT_MAX;
>
>compiler->glsl_compiler_options[i].EmitNoNoise = true;
> -  compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
>compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
>compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
>compiler->glsl_compiler_options[i].LowerCombinedClipCullDistance = 
> true;
>
>bool is_scalar = compiler->scalar_stage[i];
>
>compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
>compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
>compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
>
> diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
> index 5368440..701f055 100644
> --- a/src/mesa/main/mtypes.h
> +++ b/src/mesa/main/mtypes.h
> @@ -2990,21 +2990,20 @@ struct gl_pipeline_shader_state
>  };
>
>  /**
>   * Compiler options for a single GLSL shaders type
>   */
>  struct gl_shader_compiler_options
>  {
> /** Driver-selectable options: */
> GLboolean EmitNoLoops;
> GLboolean EmitNoCont;  /**< Emit CONT opcode? */
> -   GLboolean EmitNoMainReturn;/**< Emit CONT/RET opcodes? */
> GLboolean EmitNoNoise; /**< Emit NOISE opcodes? */
> GLboolean EmitNoPow;   /**< Emit POW opcodes? */
> GLboolean EmitNoSat;   /**< Emit SAT opcodes? */
> GLboolean LowerCombinedClipCullDistance; /** Lower gl_ClipDistance and
>* gl_CullDistance together from
>* float[8] to vec4[2]
>**/
>
> /**
>  * \name Forms of indirect addressing the driver cannot do.
> diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
> index debc18d..d0e83cc 100644
> --- a/src/mesa/program/ir_to_mesa.cpp
> +++ b/src/mesa/program/ir_to_mesa.cpp
> @@ -2154,25 +2154,24 @@ ir_to_mesa_visitor::visit(ir_texture *ir)
> default:
>assert(!"Should not get here.");
> }
>
> this->result = result_src;
>  }
>
>  void
>  ir_to_mesa_visitor::visit(ir_return *ir)
>  {
> -   /* Non-void functions should have been inlined.  We may still emit RETs
> -* from main() unless the EmitNoMainReturn option is set.
> +   /* Non-void functions should have been inlined and RETs should have been
> +* lowered.
>  */
> -   assert(!ir->get_value());
> -   emit(ir, OPCODE_RET);
> +   unreachable("ir_return not supported");
>  }
>
>  void
>  ir_to_mesa_v

[Mesa-dev] [Bug 98281] 'message's in ctx->Debug.LogMessages[] seem to leak.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98281

--- Comment #4 from Eero Tamminen  ---
(In reply to Suzuki, Shinji from comment #2)
> The amount of memory being in use may be bounded. But I believe there are
> blocks that don't get released until process termination. Having unreleased
> memory brings bad user experience to users of valgrind or any kind of memory
> debugging tools.

While libraries should not leak even in their destroy/exit functions... If you
just want to debug run-time leaks instead of things leaked in the application
termination procedure, there's a way to do that with Valgrind.

Just terminate the program with a signal that Valgrind can catch, but the
program itself doesn't (e.g. SIGBUS, SIGXCPU or SIGTRAP are rarely caught by
programs, but Valgrind catches etc).  That way program's termination code (and
any library functions called by it) cannot leak memory, and Valgrind will list
only leaks happening during normal run-time.

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[Mesa-dev] [PATCH] st/va: Default to YUV420 RT format when creating a config

[Mark Thompson]

The default will only be used if the VAConfigRTFormat attribute is not
provided by the user.
---
On 17/10/16 15:21, Julien Isorce wrote:
> Hi Mark,
> 
> Thx for the patch. I can see it has already landed.
> 
> I just tried it with gstreamer-vaapi and it causes problem since they create 
> the
> config like this for VPP:
> 
> va_status = vaCreateConfig (filter->va_display, VAProfileNone,
>   VAEntrypointVideoProc, NULL, 0, &filter->va_config);
> 
> As you can see num attrivs is 0 so it makes vaQuerySurfaceAttributes to return
> no supported format
> because config->rt_format is 0.
> 
> So I plan to make a patch that looks like this:
> 
> 
> --- a/src/gallium/state_trackers/va/surface.c
> +++ b/src/gallium/state_trackers/va/surface.c
> @@ -419,7 +419,7 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx, 
> VAConfigID
> config_id,
> /* vlVaCreateConfig returns PIPE_VIDEO_PROFILE_UNKNOWN
>  * only for VAEntrypointVideoProc. */
> if (config->profile == PIPE_VIDEO_PROFILE_UNKNOWN) {
> -  if (config->rt_format == VA_RT_FORMAT_RGB32) {
> +  if (!config->rt_format || config->rt_format == VA_RT_FORMAT_RGB32) {
>   for (j = 0; j < ARRAY_SIZE(vpp_surface_formats); ++j) {
>  attribs[i].type = VASurfaceAttribPixelFormat;
>  attribs[i].value.type = VAGenericValueTypeInteger;
> @@ -427,7 +427,8 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx, 
> VAConfigID
> config_id,
>  attribs[i].value.value.i =
> PipeFormatToVaFourcc(vpp_surface_formats[j]);
>  i++;
>   }
> -  } else if (config->rt_format == VA_RT_FORMAT_YUV420) {
> +  }
> +  if (!config->rt_format || config->rt_format == VA_RT_FORMAT_YUV420) {
>   attribs[i].type = VASurfaceAttribPixelFormat;
>   attribs[i].value.type = VAGenericValueTypeInteger;
>   attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE |
> VA_SURFACE_ATTRIB_SETTABLE;
> 
> 
> Will it be ok for whatever test application you are using ?
> 
> Not that the intel va driver always return the full list for vpp.
> 
> Cheers
> Julien

Hi Julien,

On vaCreateConfig(), va.h says:
/**
 * Create a configuration for the decode pipeline
 * it passes in the attribute list that specifies the attributes it cares
 * about, with the rest taking default values.
 */

I think that means that it should be fixed there instead?  That is, if we don't
pass the render target format attribute, just assume a default value which I
suppose should be VA_RT_FORMAT_YUV420.

So, something like the enclosing patch?  (Not tested.)

Thanks,

- Mark


 src/gallium/state_trackers/va/config.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/state_trackers/va/config.c
b/src/gallium/state_trackers/va/config.c
index 2f96eb6..f2a89b7 100644
--- a/src/gallium/state_trackers/va/config.c
+++ b/src/gallium/state_trackers/va/config.c
@@ -182,6 +182,9 @@ vlVaCreateConfig(VADriverContextP ctx, VAProfile profile,
VAEntrypoint entrypoin
if (!config)
   return VA_STATUS_ERROR_ALLOCATION_FAILED;

+   // Default value, overwritten by the VAConfigRTformat attribute if present.
+   config->rt_format = VA_RT_FORMAT_YUV420;
+
if (profile == VAProfileNone && entrypoint == VAEntrypointVideoProc) {
   config->entrypoint = VAEntrypointVideoProc;
   config->profile = PIPE_VIDEO_PROFILE_UNKNOWN;
-- 
2.7.4


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Re: [Mesa-dev] [PATCH 05/14] glsl_to_tgsi: reduce the size of glsl_to_tgsi_instruction using bitfields

[Roland Scheidegger]

Am 17.10.2016 um 15:39 schrieb Marek Olšák:
> From: Marek Olšák 
> 
> sizeof(glsl_to_tgsi_instruction): 464 -> 416
> ---
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 33 
> +++---
>  1 file changed, 16 insertions(+), 17 deletions(-)
> 
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index 78d9409..b3654fe 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -263,42 +263,41 @@ st_dst_reg::st_dst_reg(st_src_reg reg)
> this->index2D = reg.index2D;
> this->reladdr2 = reg.reladdr2;
> this->has_index2 = reg.has_index2;
> this->array_id = reg.array_id;
>  }
>  
>  class glsl_to_tgsi_instruction : public exec_node {
>  public:
> DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction)
>  
> -   unsigned op;
> st_dst_reg dst[2];
> st_src_reg src[4];
> -   /** Pointer to the ir source this tree came from for debugging */
> -   ir_instruction *ir;
> -   GLboolean cond_update;
> -   bool saturate;
> -   bool is_64bit_expanded;
> st_src_reg sampler; /**< sampler register */
> -   int sampler_base;
> -   int sampler_array_size; /**< 1-based size of sampler array, 1 if not 
> array */
> -   int tex_target; /**< One of TEXTURE_*_INDEX */
> -   glsl_base_type tex_type;
> -   GLboolean tex_shadow;
> -   unsigned image_format;
> -
> st_src_reg tex_offsets[MAX_GLSL_TEXTURE_OFFSET];
> -   unsigned tex_offset_num_offset;
> -   int dead_mask; /**< Used in dead code elimination */
> -
> st_src_reg buffer; /**< buffer register */
> -   unsigned buffer_access; /**< buffer access type */
> +
> +   /** Pointer to the ir source this tree came from for debugging */
> +   ir_instruction *ir;
> +
> +   unsigned op:8; /**< TGSI opcode */
Maybe should throw in some static assert somewhere that TGSI_OPCODE_LAST
is <= 255.
Given how close we're to the limit I wouldn't quite bet on it staying 8
bits forever (though of course it would need some changes elsewhere too).

Roland



> +   unsigned saturate:1;
> +   unsigned is_64bit_expanded:1;
> +   unsigned sampler_base:5;
> +   unsigned sampler_array_size:6; /**< 1-based size of sampler array, 1 if 
> not array */
> +   unsigned tex_target:4; /**< One of TEXTURE_*_INDEX */
> +   glsl_base_type tex_type:4;
> +   unsigned tex_shadow:1;
> +   unsigned image_format:9;
> +   unsigned tex_offset_num_offset:3;
> +   unsigned dead_mask:4; /**< Used in dead code elimination */
> +   unsigned buffer_access:3; /**< buffer access type */
>  
> class function_entry *function; /* Set on TGSI_OPCODE_CAL or 
> TGSI_OPCODE_BGNSUB */
> const struct tgsi_opcode_info *info;
>  };
>  
>  class variable_storage : public exec_node {
>  public:
> variable_storage(ir_variable *var, gl_register_file file, int index,
>  unsigned array_id = 0)
>: file(file), index(index), component(0), var(var), array_id(array_id)
> 

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[Mesa-dev] [Bug 98271] [radeonsi]Playing videos with vdpau or vaapi hardware acceleration crashes my pc

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98271

--- Comment #3 from John  ---
Well I tried bisecting it today assuming 11.2.2 and got nowhere so I tried at
commit3a9f6283f435f90ca1a2901be39ec9d629c95bb6 and it still froze.

Because of that I am not sure if that is the same problem or not...

I'll attach a few things in case.

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[Mesa-dev] [Bug 98271] [radeonsi]Playing videos with vdpau or vaapi hardware acceleration crashes my pc

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98271

--- Comment #4 from John  ---
Created attachment 127357
  --> https://bugs.freedesktop.org/attachment.cgi?id=127357&action=edit
A quick script I wrote to trigger the issue.

It takes a video file as an input (I used an X264 mkv movie file if it
matters).

It doesn't happen as quickly as I thought originally, as I've had runs up to 25
minutes (and some in seconds..).
I added the 2nd sleep to simulate better the speed at which I would usually
press keys, but maybe it just delays the whole thing, not sure.

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Re: [Mesa-dev] [PATCH] st/va: Default to YUV420 RT format when creating a config

[Mark Thompson]

On 17/10/16 15:42, Mark Thompson wrote:
> The default will only be used if the VAConfigRTFormat attribute is not
> provided by the user.
> ---
> On 17/10/16 15:21, Julien Isorce wrote:
>> Hi Mark,
>>
>> Thx for the patch. I can see it has already landed.
>>
>> I just tried it with gstreamer-vaapi and it causes problem since they create 
>> the
>> config like this for VPP:
>>
>> va_status = vaCreateConfig (filter->va_display, VAProfileNone,
>>   VAEntrypointVideoProc, NULL, 0, &filter->va_config);
>>
>> As you can see num attrivs is 0 so it makes vaQuerySurfaceAttributes to 
>> return
>> no supported format
>> because config->rt_format is 0.
>>
>> So I plan to make a patch that looks like this:
>>
>>
>> --- a/src/gallium/state_trackers/va/surface.c
>> +++ b/src/gallium/state_trackers/va/surface.c
>> @@ -419,7 +419,7 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx, 
>> VAConfigID
>> config_id,
>> /* vlVaCreateConfig returns PIPE_VIDEO_PROFILE_UNKNOWN
>>  * only for VAEntrypointVideoProc. */
>> if (config->profile == PIPE_VIDEO_PROFILE_UNKNOWN) {
>> -  if (config->rt_format == VA_RT_FORMAT_RGB32) {
>> +  if (!config->rt_format || config->rt_format == VA_RT_FORMAT_RGB32) {
>>   for (j = 0; j < ARRAY_SIZE(vpp_surface_formats); ++j) {
>>  attribs[i].type = VASurfaceAttribPixelFormat;
>>  attribs[i].value.type = VAGenericValueTypeInteger;
>> @@ -427,7 +427,8 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx, 
>> VAConfigID
>> config_id,
>>  attribs[i].value.value.i =
>> PipeFormatToVaFourcc(vpp_surface_formats[j]);
>>  i++;
>>   }
>> -  } else if (config->rt_format == VA_RT_FORMAT_YUV420) {
>> +  }
>> +  if (!config->rt_format || config->rt_format == VA_RT_FORMAT_YUV420) {
>>   attribs[i].type = VASurfaceAttribPixelFormat;
>>   attribs[i].value.type = VAGenericValueTypeInteger;
>>   attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE |
>> VA_SURFACE_ATTRIB_SETTABLE;
>>
>>
>> Will it be ok for whatever test application you are using ?
>>
>> Not that the intel va driver always return the full list for vpp.
>>
>> Cheers
>> Julien
> 
> Hi Julien,
> 
> On vaCreateConfig(), va.h says:
> /**
>  * Create a configuration for the decode pipeline
>  * it passes in the attribute list that specifies the attributes it cares
>  * about, with the rest taking default values.
>  */
> 
> I think that means that it should be fixed there instead?  That is, if we 
> don't
> pass the render target format attribute, just assume a default value which I
> suppose should be VA_RT_FORMAT_YUV420.
> 
> So, something like the enclosing patch?  (Not tested.)

Hmm.  The i965 driver uses all of the possible values (depending on the
profile/entrypoint) ored together here - thats probably a more compatible choice
than YUV420 only.

Thanks,

- Mark


That is, add:

>  src/gallium/state_trackers/va/config.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/src/gallium/state_trackers/va/config.c
> b/src/gallium/state_trackers/va/config.c
> index 2f96eb6..f2a89b7 100644
> --- a/src/gallium/state_trackers/va/config.c
> +++ b/src/gallium/state_trackers/va/config.c
> @@ -182,6 +182,9 @@ vlVaCreateConfig(VADriverContextP ctx, VAProfile profile,
> VAEntrypoint entrypoin
> if (!config)
>return VA_STATUS_ERROR_ALLOCATION_FAILED;
> 
> +   // Default value, overwritten by the VAConfigRTformat attribute if 
> present.
> +   config->rt_format = VA_RT_FORMAT_YUV420;
> +
> if (profile == VAProfileNone && entrypoint == VAEntrypointVideoProc) {
>config->entrypoint = VAEntrypointVideoProc;
>config->profile = PIPE_VIDEO_PROFILE_UNKNOWN;

config->rt_format |= VA_RT_FORMAT_RGB32;

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[Mesa-dev] [Bug 98271] [radeonsi]Playing videos with vdpau or vaapi hardware acceleration crashes my pc

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98271

--- Comment #5 from John  ---
Created attachment 127358
  --> https://bugs.freedesktop.org/attachment.cgi?id=127358&action=edit
dmesg written by the script before I restart the machine

Since there are quite some lines in dmesg about the issue, the computer is
obviously not fully dead.

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[Mesa-dev] [Bug 98271] [radeonsi]Playing videos with vdpau or vaapi hardware acceleration crashes my pc

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98271

--- Comment #8 from John  ---
I'll try today to go a bit further than 11.2, if anything in the logs give you
an idea of a good starting point please do share.

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[Mesa-dev] [Bug 98271] [radeonsi]Playing videos with vdpau or vaapi hardware acceleration crashes my pc

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98271

John  changed:

   What|Removed |Added

 CC||john.etted...@gmail.com

--- Comment #6 from John  ---
Created attachment 127359
  --> https://bugs.freedesktop.org/attachment.cgi?id=127359&action=edit
another dmesg from another run

not sure if it helps but in case its information is a bit different.

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Re: [Mesa-dev] [PATCH] st/va: Default to YUV420 RT format when creating a config

[Julien Isorce]

Hi Mark,

Yes I actually saw that too in the intel driver though I think it does not
add VA_RT_FORMAT_RGB32 ? Or I missed something ?
Maybe this is a bug. In any case yes as said before " the intel va driver
always return the full list for vpp." from vaQuerySurfaceAttributes
no matter the format selected when creating the config.

So combining all it should probably be something like this:

diff --git a/src/gallium/state_trackers/va/config.c
b/src/gallium/state_trackers/va/config.c
index 2f96eb6..11afc81 100644
--- a/src/gallium/state_trackers/va/config.c
+++ b/src/gallium/state_trackers/va/config.c
@@ -185,6 +185,8 @@ vlVaCreateConfig(VADriverContextP ctx, VAProfile
profile, VAEntrypoint entrypoin
if (profile == VAProfileNone && entrypoint == VAEntrypointVideoProc) {
   config->entrypoint = VAEntrypointVideoProc;
   config->profile = PIPE_VIDEO_PROFILE_UNKNOWN;
+  config->rt_format = VA_RT_FORMAT_YUV420 | VA_RT_FORMAT_RGB32;
+
   for (int i = 0; i < num_attribs; i++) {
  if (attrib_list[i].type == VAConfigAttribRTFormat) {
 if (attrib_list[i].value & (VA_RT_FORMAT_YUV420 |
VA_RT_FORMAT_RGB32)) {
diff --git a/src/gallium/state_trackers/va/surface.c
b/src/gallium/state_trackers/va/surface.c
index 5e92980..f8513d9 100644
--- a/src/gallium/state_trackers/va/surface.c
+++ b/src/gallium/state_trackers/va/surface.c
@@ -419,7 +419,7 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx,
VAConfigID config_id,
/* vlVaCreateConfig returns PIPE_VIDEO_PROFILE_UNKNOWN
 * only for VAEntrypointVideoProc. */
if (config->profile == PIPE_VIDEO_PROFILE_UNKNOWN) {
-  if (config->rt_format == VA_RT_FORMAT_RGB32) {
+  if (config->rt_format & VA_RT_FORMAT_RGB32) {
  for (j = 0; j < ARRAY_SIZE(vpp_surface_formats); ++j) {
 attribs[i].type = VASurfaceAttribPixelFormat;
 attribs[i].value.type = VAGenericValueTypeInteger;
@@ -427,7 +427,8 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx,
VAConfigID config_id,
 attribs[i].value.value.i =
PipeFormatToVaFourcc(vpp_surface_formats[j]);
 i++;
  }
-  } else if (config->rt_format == VA_RT_FORMAT_YUV420) {
+  }
+  if (config->rt_format & VA_RT_FORMAT_YUV420) {
  attribs[i].type = VASurfaceAttribPixelFormat;
  attribs[i].value.type = VAGenericValueTypeInteger;
  attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE |
VA_SURFACE_ATTRIB_SETTABLE;

Will it be ok for your case ?

Cheers
Julien






On 17 October 2016 at 15:54, Mark Thompson  wrote:

> On 17/10/16 15:42, Mark Thompson wrote:
> > The default will only be used if the VAConfigRTFormat attribute is not
> > provided by the user.
> > ---
> > On 17/10/16 15:21, Julien Isorce wrote:
> >> Hi Mark,
> >>
> >> Thx for the patch. I can see it has already landed.
> >>
> >> I just tried it with gstreamer-vaapi and it causes problem since they
> create the
> >> config like this for VPP:
> >>
> >> va_status = vaCreateConfig (filter->va_display, VAProfileNone,
> >>   VAEntrypointVideoProc, NULL, 0, &filter->va_config);
> >>
> >> As you can see num attrivs is 0 so it makes vaQuerySurfaceAttributes to
> return
> >> no supported format
> >> because config->rt_format is 0.
> >>
> >> So I plan to make a patch that looks like this:
> >>
> >>
> >> --- a/src/gallium/state_trackers/va/surface.c
> >> +++ b/src/gallium/state_trackers/va/surface.c
> >> @@ -419,7 +419,7 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx,
> VAConfigID
> >> config_id,
> >> /* vlVaCreateConfig returns PIPE_VIDEO_PROFILE_UNKNOWN
> >>  * only for VAEntrypointVideoProc. */
> >> if (config->profile == PIPE_VIDEO_PROFILE_UNKNOWN) {
> >> -  if (config->rt_format == VA_RT_FORMAT_RGB32) {
> >> +  if (!config->rt_format || config->rt_format ==
> VA_RT_FORMAT_RGB32) {
> >>   for (j = 0; j < ARRAY_SIZE(vpp_surface_formats); ++j) {
> >>  attribs[i].type = VASurfaceAttribPixelFormat;
> >>  attribs[i].value.type = VAGenericValueTypeInteger;
> >> @@ -427,7 +427,8 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx,
> VAConfigID
> >> config_id,
> >>  attribs[i].value.value.i =
> >> PipeFormatToVaFourcc(vpp_surface_formats[j]);
> >>  i++;
> >>   }
> >> -  } else if (config->rt_format == VA_RT_FORMAT_YUV420) {
> >> +  }
> >> +  if (!config->rt_format || config->rt_format ==
> VA_RT_FORMAT_YUV420) {
> >>   attribs[i].type = VASurfaceAttribPixelFormat;
> >>   attribs[i].value.type = VAGenericValueTypeInteger;
> >>   attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE |
> >> VA_SURFACE_ATTRIB_SETTABLE;
> >>
> >>
> >> Will it be ok for whatever test application you are using ?
> >>
> >> Not that the intel va driver always return the full list for vpp.
> >>
> >> Cheers
> >> Julien
> >
> > Hi Julien,
> >
> > On vaCreateConfig(), va.h says:
> > /**
> >  * Create a configuration for the decode pipeline
> >  * it passes in the attribute list 

Re: [Mesa-dev] [PATCH] st/va: Default to YUV420 RT format when creating a config

[Mark Thompson]

On 17/10/16 16:13, Julien Isorce wrote:
> Hi Mark,
> 
> Yes I actually saw that too in the intel driver though I think it does not add
> VA_RT_FORMAT_RGB32 ? Or I missed something ?
> Maybe this is a bug. In any case yes as said before " the intel va driver 
> always
> return the full list for vpp." from vaQuerySurfaceAttributes
> no matter the format selected when creating the config.

Looks like the lack of RGB32 has already been noted and fixed:
.

> So combining all it should probably be something like this:
> 
> diff --git a/src/gallium/state_trackers/va/config.c
> b/src/gallium/state_trackers/va/config.c
> index 2f96eb6..11afc81 100644
> --- a/src/gallium/state_trackers/va/config.c
> +++ b/src/gallium/state_trackers/va/config.c
> @@ -185,6 +185,8 @@ vlVaCreateConfig(VADriverContextP ctx, VAProfile profile,
> VAEntrypoint entrypoin
> if (profile == VAProfileNone && entrypoint == VAEntrypointVideoProc) {
>config->entrypoint = VAEntrypointVideoProc;
>config->profile = PIPE_VIDEO_PROFILE_UNKNOWN;
> +  config->rt_format = VA_RT_FORMAT_YUV420 | VA_RT_FORMAT_RGB32;
> +
>for (int i = 0; i < num_attribs; i++) {
>   if (attrib_list[i].type == VAConfigAttribRTFormat) {
>  if (attrib_list[i].value & (VA_RT_FORMAT_YUV420 |
> VA_RT_FORMAT_RGB32)) {

Please set a default for the non-VideoProc case too, so that codecs have the
same behaviour.

> diff --git a/src/gallium/state_trackers/va/surface.c
> b/src/gallium/state_trackers/va/surface.c
> index 5e92980..f8513d9 100644
> --- a/src/gallium/state_trackers/va/surface.c
> +++ b/src/gallium/state_trackers/va/surface.c
> @@ -419,7 +419,7 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx, 
> VAConfigID
> config_id,
> /* vlVaCreateConfig returns PIPE_VIDEO_PROFILE_UNKNOWN
>  * only for VAEntrypointVideoProc. */
> if (config->profile == PIPE_VIDEO_PROFILE_UNKNOWN) {
> -  if (config->rt_format == VA_RT_FORMAT_RGB32) {
> +  if (config->rt_format & VA_RT_FORMAT_RGB32) {
>   for (j = 0; j < ARRAY_SIZE(vpp_surface_formats); ++j) {
>  attribs[i].type = VASurfaceAttribPixelFormat;
>  attribs[i].value.type = VAGenericValueTypeInteger;
> @@ -427,7 +427,8 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx, 
> VAConfigID
> config_id,
>  attribs[i].value.value.i =
> PipeFormatToVaFourcc(vpp_surface_formats[j]);
>  i++;
>   }
> -  } else if (config->rt_format == VA_RT_FORMAT_YUV420) {
> +  }
> +  if (config->rt_format & VA_RT_FORMAT_YUV420) {
>   attribs[i].type = VASurfaceAttribPixelFormat;
>   attribs[i].value.type = VAGenericValueTypeInteger;
>   attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE |
> VA_SURFACE_ATTRIB_SETTABLE;
> 
> Will it be ok for your case ?
> 
> Cheers
> Julien

Yeah, that seems right to me (with the small change above).

Thanks,

- Mark

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Re: [Mesa-dev] [PATCH 0/6] EGL_MESA_platform_surfaceless (v2)

[Adam Jackson]

On Fri, 2016-10-14 at 10:48 -0700, Chad Versace wrote:
> Some people privately asked why we need to create this EGL platform.
> I want to respond publicly.
> 
> Mesa *already* *has* this EGL platform. In my view, the issue at hand
> isn't whether to create or to not create the platform. It's whether to
> specify its behavior (formally in an extension spec) or not.
> 
> My motivation in writing the EGL_MESA_platform_surfaceless spec was not
> to introduce any new features or behavior.  My motivation was to
> document longstanding existing behavior in Chrome OS, that upstream Mesa
> eventually subsumed.
> 
> During XDC, some people outside of the Chrome OS community complained to
> me that the behavior of platform_surfaceless was ill-defined and
> unstable, and they wanted the situation fixed. So I wrote a spec.

As one of the people who complained: the big issue I had with the
surfaceless platform was that the only way to use it was to set an
environment variable before calling eglGetDisplay, which is just
pointlessly unlike how you use every other platform. I was _happy_ when
I discovered the feature, I was only unhappy with its interface.

- ajax
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[Mesa-dev] [Bug 98271] [radeonsi]Playing videos with vdpau or vaapi hardware acceleration crashes my pc

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98271

--- Comment #7 from John  ---
Created attachment 127360
  --> https://bugs.freedesktop.org/attachment.cgi?id=127360&action=edit
Xorg log

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Re: [Mesa-dev] [PATCH] egl/dri2: add a libname to dlopen for OpenBSD

[Eric Engestrom]

On Monday, 2016-10-17 22:53:20 +1100, Jonathan Gray wrote:
> On Mon, Oct 17, 2016 at 12:39:11PM +0100, Emil Velikov wrote:
> > On 17 October 2016 at 10:53, Eric Engestrom  
> > wrote:
> > > On Sunday, 2016-10-16 16:38:35 +1100, Jonathan Gray wrote:
> > >> On OpenBSD try to dlopen 'libglapi.so', ld.so will find
> > >> the highest major/minor version and open it in this case.
> > >>
> > >> Avoids '#error Unknown glapi provider for this platform' at build time.
> > >>
> > >> Signed-off-by: Jonathan Gray 
> > >
> > > LGTM, and I guess the other *BSD will want the same since 7a9c92d0 broke
> > > them too.
> > >
> > I'm not 100% sure about that. OpenBSD (unlike other BSD) did bump the
> > major when the ABI breaks due to 'internal' changes - think of
> > off_t/time_t on 32 vs 64bit systems and alike.
> > 
> > Unlike Linux kernel/distros, BSDs tend to be more relaxed when in
> > comes to ABI, I believe. Don't quote me on that one ;-)
> 
> OpenBSD tends to favour simplified interfaces over backwards compatiblity
> and is more like a research system in that respect.  As the kernel
> and userland are one source tree ioctl compat largely doesn't exist.
> System calls get deprecated and removed over the course of a few releases.
> So we didn't go through the pain of duplicated systems calls for off_t
> as mentioned, and don't go in for symbol versioning.  Just major.minor
> library versioning, which is roughly symbol removals, major crank,
> symbol additions minor crank.
> 
> I believe FreeBSD tends to go in for backwards compatibility more
> but am not familiar with the details.  They also have a different ld.so.
> 
> Perhaps an else case for 'libglapi.so.0' would be appropriate for all
> the other various unices instead of the #error ?

Yeah actually, I'm thinking reverting this hunk of 7a9c92d0 might be a better,
to avoid the potentially huge list of every *BSD and other Unix:

8<
@@ -2808,10 +2808,8 @@ dri2_load(_EGLDriver *drv)
const char *libname = "libglapi.0.dylib";
 #elif defined(__CYGWIN__)
const char *libname = "cygglapi-0.dll";
-#elif defined(__linux__)
+#else
const char *libname = "libglapi.so.0";
-#else
-#error Unknown glapi provider for this platform
 #endif
void *handle;
 
>8

> 
> > 
> > > Fixes: 7a9c92d071d010066349 ("egl/dri2: non-shared glapi cleanups")
> > > Reviewed-by: Eric Engestrom 
> > >
> > > Side note, I don't understand why we hardcode the version everywhere
> > > (except Android). I can see it's been like that since that code was
> > > added nearly 6 years ago (218381d9), but I couldn't find an explanation
> > > in the logs, or any mention of it in the thread I found [1].
> > > Emil, do you know?
> > >
> > The ABI must be stable. Since a) we (and linux distros in general)
> > have the greater flexibility to "mix and match" components and b)
> > glapi is/was used by xserver as well, the initial goal was that the
> > ABI should not break, ever. See some the src/mapi changes by Brian
> > Paul, which rework the nop calls due to different calling convention
> > and stack corruption on Windows and the follow up fix to keep those
> > Windows only and stable for everyone else
> > be71bbfaa2ad201b570b56847a13328fc359d0ee.

Right, makes sense. Thanks for spending the time to educate me :P

> > 
> > Emil
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[Mesa-dev] [PATCH 5/5] anv: setup appropriate border color structures on gen7/gen75

[Lionel Landwerlin]

Up to this point we were using the gen8+ structures. Altough this commit
doesn't fixes the border color CTS tests, this is a step in the right
direction to fix the following tests :

dEQP-VK.pipeline.sampler.view_type.2d.format.*.address_modes.all_mode_clamp_to_border_*

Signed-off-by: Lionel Landwerlin 
---
 src/intel/vulkan/anv_cmd_buffer.c |  10 ++
 src/intel/vulkan/anv_device.c |  42 +---
 src/intel/vulkan/anv_genX.h   |   3 +-
 src/intel/vulkan/anv_private.h|   7 ++
 src/intel/vulkan/genX_state.c | 220 --
 5 files changed, 208 insertions(+), 74 deletions(-)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index b051489..a63f3d9 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -931,6 +931,16 @@ anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer 
*cmd_buffer,
   if (sampler == NULL)
  continue;
 
+  /* On Haswell, although the border color structures are 20 dwords long
+   * and must be aligned at 512 bytes, the position of the 8/16/32bits
+   * colors overlap, meaning we can't have a single color structure
+   * configured for all formats. We therefore need to reemit the sampler
+   * structure for the used format. */
+  if (cmd_buffer->device->info.is_haswell) {
+ gen75_pack_sampler_state(cmd_buffer->device, sampler,
+  desc->image_view->vk_format);
+  }
+
   memcpy(state->map + (s * 16),
  sampler->state, sizeof(sampler->state));
}
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index ce1b9c1..4e69307 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -724,46 +724,6 @@ anv_queue_finish(struct anv_queue *queue)
 {
 }
 
-static struct anv_state
-anv_state_pool_emit_data(struct anv_state_pool *pool, size_t size, size_t 
align, const void *p)
-{
-   struct anv_state state;
-
-   state = anv_state_pool_alloc(pool, size, align);
-   memcpy(state.map, p, size);
-
-   if (!pool->block_pool->device->info.has_llc)
-  anv_state_clflush(state);
-
-   return state;
-}
-
-struct gen8_border_color {
-   union {
-  float float32[4];
-  uint32_t uint32[4];
-   };
-   /* Pad out to 64 bytes */
-   uint32_t _pad[12];
-};
-
-static void
-anv_device_init_border_colors(struct anv_device *device)
-{
-   static const struct gen8_border_color border_colors[] = {
-  [VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK] =  { .float32 = { 0.0, 0.0, 
0.0, 0.0 } },
-  [VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK] =   { .float32 = { 0.0, 0.0, 
0.0, 1.0 } },
-  [VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE] =   { .float32 = { 1.0, 1.0, 
1.0, 1.0 } },
-  [VK_BORDER_COLOR_INT_TRANSPARENT_BLACK] ={ .uint32 = { 0, 0, 0, 0 } 
},
-  [VK_BORDER_COLOR_INT_OPAQUE_BLACK] = { .uint32 = { 0, 0, 0, 1 } 
},
-  [VK_BORDER_COLOR_INT_OPAQUE_WHITE] = { .uint32 = { 1, 1, 1, 1 } 
},
-   };
-
-   device->border_colors = 
anv_state_pool_emit_data(&device->dynamic_state_pool,
-sizeof(border_colors), 64,
-border_colors);
-}
-
 VkResult
 anv_device_submit_simple_batch(struct anv_device *device,
struct anv_batch *batch)
@@ -926,7 +886,7 @@ VkResult anv_CreateDevice(
 
anv_device_init_blorp(device);
 
-   anv_device_init_border_colors(device);
+   ANV_GEN_DISPATCH(device, border_colors_setup, device);
 
*pDevice = anv_device_to_handle(device);
 
diff --git a/src/intel/vulkan/anv_genX.h b/src/intel/vulkan/anv_genX.h
index 27c55b9..a4a39e1 100644
--- a/src/intel/vulkan/anv_genX.h
+++ b/src/intel/vulkan/anv_genX.h
@@ -28,7 +28,7 @@
 /*
  * Gen-specific function declarations.  This header must *not* be included
  * directly.  Instead, it is included multiple times by anv_private.h.
- * 
+ *
  * In this header file, the usual genx() macro is available.
  */
 
@@ -37,6 +37,7 @@
 #endif
 
 VkResult genX(init_device_state)(struct anv_device *device);
+void genX(border_colors_setup)(struct anv_device *device);
 
 void genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer 
*cmd_buffer);
 
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 69e6aac..faebbb2 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -643,6 +643,7 @@ struct anv_device {
 struct blorp_contextblorp;
 
 struct anv_stateborder_colors;
+uint32_tborder_color_align;
 
 struct anv_queuequeue;
 
@@ -1732,6 +1733,8 @@ void anv_buffer_view_fill_image_param(struct anv_device 
*device,
 
 struct anv_sampler {
uint32_t state[4];
+
+   VkSamplerCreateInfo info;
 };
 
 struct anv_framebuffer {
@@ -1783,6 +1786,10 @@ struct anv_query_pool {
str

[Mesa-dev] [PATCH 3/5] anv: add util functions to query max bpc & integer formats

[Lionel Landwerlin]

Signed-off-by: Lionel Landwerlin 
---
 src/intel/vulkan/vk_format_info.h | 300 ++
 1 file changed, 300 insertions(+)

diff --git a/src/intel/vulkan/vk_format_info.h 
b/src/intel/vulkan/vk_format_info.h
index 5c5a1f3..0c1d865 100644
--- a/src/intel/vulkan/vk_format_info.h
+++ b/src/intel/vulkan/vk_format_info.h
@@ -53,6 +53,306 @@ vk_format_aspects(VkFormat format)
 }
 
 static inline bool
+vk_format_is_integer(VkFormat format)
+{
+   switch (format) {
+   case VK_FORMAT_R8_UINT:
+   case VK_FORMAT_R8_SINT:
+   case VK_FORMAT_R8G8_UINT:
+   case VK_FORMAT_R8G8_SINT:
+   case VK_FORMAT_R8G8B8_UINT:
+   case VK_FORMAT_R8G8B8_SINT:
+   case VK_FORMAT_B8G8R8_UINT:
+   case VK_FORMAT_B8G8R8_SINT:
+   case VK_FORMAT_R8G8B8A8_UINT:
+   case VK_FORMAT_R8G8B8A8_SINT:
+   case VK_FORMAT_B8G8R8A8_UINT:
+   case VK_FORMAT_B8G8R8A8_SINT:
+   case VK_FORMAT_A8B8G8R8_UINT_PACK32:
+   case VK_FORMAT_A8B8G8R8_SINT_PACK32:
+   case VK_FORMAT_A2R10G10B10_UINT_PACK32:
+   case VK_FORMAT_A2R10G10B10_SINT_PACK32:
+   case VK_FORMAT_A2B10G10R10_UINT_PACK32:
+   case VK_FORMAT_A2B10G10R10_SINT_PACK32:
+   case VK_FORMAT_R16_UINT:
+   case VK_FORMAT_R16_SINT:
+   case VK_FORMAT_R16G16_UINT:
+   case VK_FORMAT_R16G16_SINT:
+   case VK_FORMAT_R16G16B16_UINT:
+   case VK_FORMAT_R16G16B16_SINT:
+   case VK_FORMAT_R16G16B16A16_UINT:
+   case VK_FORMAT_R16G16B16A16_SINT:
+   case VK_FORMAT_R32_UINT:
+   case VK_FORMAT_R32_SINT:
+   case VK_FORMAT_R32G32_UINT:
+   case VK_FORMAT_R32G32_SINT:
+   case VK_FORMAT_R32G32B32_UINT:
+   case VK_FORMAT_R32G32B32_SINT:
+   case VK_FORMAT_R32G32B32A32_UINT:
+   case VK_FORMAT_R32G32B32A32_SINT:
+   case VK_FORMAT_R64_UINT:
+   case VK_FORMAT_R64_SINT:
+   case VK_FORMAT_R64G64_UINT:
+   case VK_FORMAT_R64G64_SINT:
+   case VK_FORMAT_R64G64B64_UINT:
+   case VK_FORMAT_R64G64B64_SINT:
+   case VK_FORMAT_R64G64B64A64_UINT:
+   case VK_FORMAT_R64G64B64A64_SINT:
+   case VK_FORMAT_S8_UINT:
+   case VK_FORMAT_D16_UNORM_S8_UINT:
+   case VK_FORMAT_D24_UNORM_S8_UINT:
+   case VK_FORMAT_D32_SFLOAT_S8_UINT:
+  return true;
+
+   default:
+  return false;
+   }
+}
+
+static inline uint32_t
+vk_format_max_bpc(VkFormat format)
+{
+   switch (format) {
+   case VK_FORMAT_R4G4_UNORM_PACK8:
+   case VK_FORMAT_R4G4B4A4_UNORM_PACK16:
+   case VK_FORMAT_B4G4R4A4_UNORM_PACK16:
+  return 4;
+
+   case VK_FORMAT_R5G6B5_UNORM_PACK16:
+   case VK_FORMAT_B5G6R5_UNORM_PACK16:
+  return 6;
+
+   case VK_FORMAT_R5G5B5A1_UNORM_PACK16:
+   case VK_FORMAT_B5G5R5A1_UNORM_PACK16:
+   case VK_FORMAT_A1R5G5B5_UNORM_PACK16:
+  return 5;
+
+   case VK_FORMAT_R8_UNORM:
+   case VK_FORMAT_R8_SNORM:
+   case VK_FORMAT_R8_USCALED:
+   case VK_FORMAT_R8_SSCALED:
+   case VK_FORMAT_R8_UINT:
+   case VK_FORMAT_R8_SINT:
+   case VK_FORMAT_R8_SRGB:
+   case VK_FORMAT_R8G8_UNORM:
+   case VK_FORMAT_R8G8_SNORM:
+   case VK_FORMAT_R8G8_USCALED:
+   case VK_FORMAT_R8G8_SSCALED:
+   case VK_FORMAT_R8G8_UINT:
+   case VK_FORMAT_R8G8_SINT:
+   case VK_FORMAT_R8G8_SRGB:
+   case VK_FORMAT_R8G8B8_UNORM:
+   case VK_FORMAT_R8G8B8_SNORM:
+   case VK_FORMAT_R8G8B8_USCALED:
+   case VK_FORMAT_R8G8B8_SSCALED:
+   case VK_FORMAT_R8G8B8_UINT:
+   case VK_FORMAT_R8G8B8_SINT:
+   case VK_FORMAT_R8G8B8_SRGB:
+   case VK_FORMAT_B8G8R8_UNORM:
+   case VK_FORMAT_B8G8R8_SNORM:
+   case VK_FORMAT_B8G8R8_USCALED:
+   case VK_FORMAT_B8G8R8_SSCALED:
+   case VK_FORMAT_B8G8R8_UINT:
+   case VK_FORMAT_B8G8R8_SINT:
+   case VK_FORMAT_B8G8R8_SRGB:
+   case VK_FORMAT_R8G8B8A8_UNORM:
+   case VK_FORMAT_R8G8B8A8_SNORM:
+   case VK_FORMAT_R8G8B8A8_USCALED:
+   case VK_FORMAT_R8G8B8A8_SSCALED:
+   case VK_FORMAT_R8G8B8A8_UINT:
+   case VK_FORMAT_R8G8B8A8_SINT:
+   case VK_FORMAT_R8G8B8A8_SRGB:
+   case VK_FORMAT_B8G8R8A8_UNORM:
+   case VK_FORMAT_B8G8R8A8_SNORM:
+   case VK_FORMAT_B8G8R8A8_USCALED:
+   case VK_FORMAT_B8G8R8A8_SSCALED:
+   case VK_FORMAT_B8G8R8A8_UINT:
+   case VK_FORMAT_B8G8R8A8_SINT:
+   case VK_FORMAT_B8G8R8A8_SRGB:
+   case VK_FORMAT_A8B8G8R8_UNORM_PACK32:
+   case VK_FORMAT_A8B8G8R8_SNORM_PACK32:
+   case VK_FORMAT_A8B8G8R8_USCALED_PACK32:
+   case VK_FORMAT_A8B8G8R8_SSCALED_PACK32:
+   case VK_FORMAT_A8B8G8R8_UINT_PACK32:
+   case VK_FORMAT_A8B8G8R8_SINT_PACK32:
+   case VK_FORMAT_A8B8G8R8_SRGB_PACK32:
+  return 8;
+
+   case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
+   case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
+   case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
+   case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
+   case VK_FORMAT_A2R10G10B10_UINT_PACK32:
+   case VK_FORMAT_A2R10G10B10_SINT_PACK32:
+   case VK_FORMAT_A2B10G10R10_UNORM_PACK32:
+   case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
+   case VK_FORMAT_A2B10G10R10_USCALED_PACK32:
+   case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
+   case VK_FORMAT_A2B10G10R10_UINT_PACK32:
+   case VK_FORMAT_A2B10G10R10_SINT_PACK32:
+  return 10;
+
+   case VK_FORMAT_R16_UNORM:
+   case VK_FORMAT_R16_SNORM:
+   case VK_FORMAT_R16_USCALED:
+   case VK_FORMAT_R16_SSCALED:
+   ca

[Mesa-dev] [PATCH 2/5] intel: aubinator: decode border color

[Lionel Landwerlin]

Signed-off-by: Lionel Landwerlin 
---
 src/intel/tools/aubinator.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index d716a65..cda91d1 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -265,13 +265,20 @@ dump_samplers(struct gen_spec *spec, uint32_t offset)
uint32_t i;
uint64_t start;
struct gen_group *sampler_state;
+   struct gen_group *border_color;
 
sampler_state = gen_spec_find_struct(spec, "SAMPLER_STATE");
+   border_color = gen_spec_find_struct(spec, "SAMPLER_BORDER_COLOR_STATE");
 
start = dynamic_state_base + offset;
for (i = 0; i < 4; i++) {
+  uint32_t *border_color_offset = gtt + start + i * 16 + 8;
+
   printf("sampler state %d\n", i);
   decode_structure(spec, sampler_state, gtt + start + i * 16);
+  printf("sampler state border color %d\n", i);
+  decode_structure(spec, border_color,
+   gtt + dynamic_state_base + *border_color_offset);
}
 }
 
-- 
2.9.3

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[Mesa-dev] [PATCH 4/5] anv: add dispatch macro to find right function for given generation

[Lionel Landwerlin]

Signed-off-by: Lionel Landwerlin 
---
 src/intel/vulkan/anv_cmd_buffer.c | 33 ++---
 src/intel/vulkan/anv_device.c | 19 +--
 src/intel/vulkan/anv_private.h| 23 +++
 3 files changed, 30 insertions(+), 45 deletions(-)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index 5bcd5e0..b051489 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -356,19 +356,9 @@ VkResult anv_ResetCommandBuffer(
 void
 anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
 {
-   switch (cmd_buffer->device->info.gen) {
-   case 7:
-  if (cmd_buffer->device->info.is_haswell)
- return gen75_cmd_buffer_emit_state_base_address(cmd_buffer);
-  else
- return gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
-   case 8:
-  return gen8_cmd_buffer_emit_state_base_address(cmd_buffer);
-   case 9:
-  return gen9_cmd_buffer_emit_state_base_address(cmd_buffer);
-   default:
-  unreachable("unsupported gen\n");
-   }
+   ANV_GEN_DISPATCH(cmd_buffer->device,
+cmd_buffer_emit_state_base_address,
+cmd_buffer);
 }
 
 VkResult anv_BeginCommandBuffer(
@@ -714,20 +704,9 @@ static struct anv_state
 anv_cmd_buffer_alloc_null_surface_state(struct anv_cmd_buffer *cmd_buffer,
 struct anv_framebuffer *fb)
 {
-   switch (cmd_buffer->device->info.gen) {
-   case 7:
-  if (cmd_buffer->device->info.is_haswell) {
- return gen75_cmd_buffer_alloc_null_surface_state(cmd_buffer, fb);
-  } else {
- return gen7_cmd_buffer_alloc_null_surface_state(cmd_buffer, fb);
-  }
-   case 8:
-  return gen8_cmd_buffer_alloc_null_surface_state(cmd_buffer, fb);
-   case 9:
-  return gen9_cmd_buffer_alloc_null_surface_state(cmd_buffer, fb);
-   default:
-  unreachable("Invalid hardware generation");
-   }
+   return ANV_GEN_DISPATCH(cmd_buffer->device,
+   cmd_buffer_alloc_null_surface_state,
+   cmd_buffer, fb);
 }
 
 VkResult
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 53b9b1b..ce1b9c1 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -920,24 +920,7 @@ VkResult anv_CreateDevice(
 
anv_queue_init(device, &device->queue);
 
-   switch (device->info.gen) {
-   case 7:
-  if (!device->info.is_haswell)
- result = gen7_init_device_state(device);
-  else
- result = gen75_init_device_state(device);
-  break;
-   case 8:
-  result = gen8_init_device_state(device);
-  break;
-   case 9:
-  result = gen9_init_device_state(device);
-  break;
-   default:
-  /* Shouldn't get here as we don't create physical devices for any other
-   * gens. */
-  unreachable("unhandled gen");
-   }
+   result = ANV_GEN_DISPATCH(device, init_device_state, device);
if (result != VK_SUCCESS)
   goto fail_fd;
 
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index c9d102d..69e6aac 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1873,6 +1873,29 @@ ANV_DEFINE_STRUCT_CASTS(anv_common, VkMemoryBarrier)
 ANV_DEFINE_STRUCT_CASTS(anv_common, VkBufferMemoryBarrier)
 ANV_DEFINE_STRUCT_CASTS(anv_common, VkImageMemoryBarrier)
 
+#define ANV_GEN_DISPATCH(device, name, ...)  \
+   ({\
+  __typeof(gen7_ ## name)* __func = NULL;\
+  switch ((device)->info.gen) {  \
+  case 7:\
+ if ((device)->info.is_haswell) {\
+__func = gen75_ ## name; \
+ } else {\
+__func = gen7_ ## name;  \
+ }   \
+ break;  \
+  case 8:\
+ __func = gen8_ ## name; \
+ break;  \
+  case 9:\
+ __func = gen9_ ## name; \
+ break;  \
+  default:   \
+ unreachable("unhandled gen");   \
+  }; \
+  __func( __VA_ARGS__);  \
+   })
+
 /* Gen-specific function declarations */
 #ifdef genX
 #  include "anv_genX.h"
-- 
2.9.3

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[Mesa-dev] [PATCH 0/5] Anv border colors on IVB/HSW

[Lionel Landwerlin]

Hi,

Spoiler alert, this series doesn't actually make the border colors work on
IvyBridge and Haswell. It still brings some useful changes (I think).

On Haswell, it seems the hardware always reads the border color from the
offset 0 of the "Dynamic State Memory Address", regardless of what offset is
programmed in the "Border Color Pointer" field of the SAMPLER_STATE
structure. Maybe some kind of cache invalidation is missing in this series?
Any idea/pointer is more than welcome!

Cheers,

Lionel Landwerlin (5):
  intel: genxml: add SAMPLER_BORDER_COLOR_STATE structures
  intel: aubinator: decode border color
  anv: add util functions to query max bpc & integer formats
  anv: add dispatch macro to find right function for given generation
  anv: setup appropriate border color structures on gen7/gen75

 src/intel/genxml/gen6.xml |  32 
 src/intel/genxml/gen7.xml |  12 ++
 src/intel/genxml/gen75.xml|  40 +
 src/intel/genxml/gen8.xml |  12 ++
 src/intel/genxml/gen9.xml |  12 ++
 src/intel/tools/aubinator.c   |   7 +
 src/intel/vulkan/anv_cmd_buffer.c |  43 ++
 src/intel/vulkan/anv_device.c |  61 +---
 src/intel/vulkan/anv_genX.h   |   3 +-
 src/intel/vulkan/anv_private.h|  30 
 src/intel/vulkan/genX_state.c | 220 
 src/intel/vulkan/vk_format_info.h | 300 ++
 12 files changed, 653 insertions(+), 119 deletions(-)

--
2.9.3
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[Mesa-dev] [PATCH 1/5] intel: genxml: add SAMPLER_BORDER_COLOR_STATE structures

[Lionel Landwerlin]

Signed-off-by: Lionel Landwerlin 
---
 src/intel/genxml/gen6.xml  | 32 
 src/intel/genxml/gen7.xml  | 12 
 src/intel/genxml/gen75.xml | 40 
 src/intel/genxml/gen8.xml  | 12 
 src/intel/genxml/gen9.xml  | 12 
 5 files changed, 108 insertions(+)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 211716b..7ba8954 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -372,6 +372,38 @@
 
   
 
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
   
 
 
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index eabb244..a950603 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -428,6 +428,18 @@
 
   
 
+  
+
+
+
+
+
+
+
+
+
+  
+
   
 
 
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 27a12cb..42f66cb 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -438,6 +438,46 @@
 
   
 
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
   
 
 
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index ee62614..a281f01 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -358,6 +358,18 @@
 
   
 
+  
+
+
+
+
+
+
+
+
+
+  
+
   
 
 
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 9c81c5a..665b61f 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -382,6 +382,18 @@
 
   
 
+  
+
+
+
+
+
+
+
+
+
+  
+
   
 
 
-- 
2.9.3

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Re: [Mesa-dev] [PATCH 6/6] anv: add dispatch macro to find right function for given generation

[Kenneth Graunke]

On Wednesday, October 12, 2016 11:28:04 PM PDT Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin 
> ---
>  src/intel/vulkan/anv_cmd_buffer.c | 33 ++---
>  src/intel/vulkan/anv_device.c | 19 +--
>  src/intel/vulkan/anv_pipeline.c   | 30 --
>  src/intel/vulkan/anv_private.h| 23 +++
>  4 files changed, 34 insertions(+), 71 deletions(-)
> 
> diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
> b/src/intel/vulkan/anv_cmd_buffer.c
> index 5bcd5e0..b051489 100644
> --- a/src/intel/vulkan/anv_cmd_buffer.c
> +++ b/src/intel/vulkan/anv_cmd_buffer.c
> @@ -356,19 +356,9 @@ VkResult anv_ResetCommandBuffer(
>  void
>  anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
>  {
> -   switch (cmd_buffer->device->info.gen) {
> -   case 7:
> -  if (cmd_buffer->device->info.is_haswell)
> - return gen75_cmd_buffer_emit_state_base_address(cmd_buffer);
> -  else
> - return gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
> -   case 8:
> -  return gen8_cmd_buffer_emit_state_base_address(cmd_buffer);
> -   case 9:
> -  return gen9_cmd_buffer_emit_state_base_address(cmd_buffer);
> -   default:
> -  unreachable("unsupported gen\n");
> -   }
> +   ANV_GEN_DISPATCH(cmd_buffer->device,
> +cmd_buffer_emit_state_base_address,
> +cmd_buffer);
>  }
>  
>  VkResult anv_BeginCommandBuffer(
> @@ -714,20 +704,9 @@ static struct anv_state
>  anv_cmd_buffer_alloc_null_surface_state(struct anv_cmd_buffer *cmd_buffer,
>  struct anv_framebuffer *fb)
>  {
> -   switch (cmd_buffer->device->info.gen) {
> -   case 7:
> -  if (cmd_buffer->device->info.is_haswell) {
> - return gen75_cmd_buffer_alloc_null_surface_state(cmd_buffer, fb);
> -  } else {
> - return gen7_cmd_buffer_alloc_null_surface_state(cmd_buffer, fb);
> -  }
> -   case 8:
> -  return gen8_cmd_buffer_alloc_null_surface_state(cmd_buffer, fb);
> -   case 9:
> -  return gen9_cmd_buffer_alloc_null_surface_state(cmd_buffer, fb);
> -   default:
> -  unreachable("Invalid hardware generation");
> -   }
> +   return ANV_GEN_DISPATCH(cmd_buffer->device,
> +   cmd_buffer_alloc_null_surface_state,
> +   cmd_buffer, fb);
>  }
>  
>  VkResult
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index 24f7227..6dfdfdb 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -921,24 +921,7 @@ VkResult anv_CreateDevice(
>  
> anv_queue_init(device, &device->queue);
>  
> -   switch (device->info.gen) {
> -   case 7:
> -  if (!device->info.is_haswell)
> - result = gen7_init_device_state(device);
> -  else
> - result = gen75_init_device_state(device);
> -  break;
> -   case 8:
> -  result = gen8_init_device_state(device);
> -  break;
> -   case 9:
> -  result = gen9_init_device_state(device);
> -  break;
> -   default:
> -  /* Shouldn't get here as we don't create physical devices for any other
> -   * gens. */
> -  unreachable("unhandled gen");
> -   }
> +   result = ANV_GEN_DISPATCH(device, init_device_state, device);
> if (result != VK_SUCCESS)
>goto fail_fd;
>  
> diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
> index 6b393a6..f9f1cbf 100644
> --- a/src/intel/vulkan/anv_pipeline.c
> +++ b/src/intel/vulkan/anv_pipeline.c
> @@ -1182,19 +1182,8 @@ anv_graphics_pipeline_create(
> ANV_FROM_HANDLE(anv_device, device, _device);
> ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
>  
> -   switch (device->info.gen) {
> -   case 7:
> -  if (device->info.is_haswell)
> - return gen75_graphics_pipeline_create(_device, cache, pCreateInfo, 
> extra, pAllocator, pPipeline);
> -  else
> - return gen7_graphics_pipeline_create(_device, cache, pCreateInfo, 
> extra, pAllocator, pPipeline);
> -   case 8:
> -  return gen8_graphics_pipeline_create(_device, cache, pCreateInfo, 
> extra, pAllocator, pPipeline);
> -   case 9:
> -  return gen9_graphics_pipeline_create(_device, cache, pCreateInfo, 
> extra, pAllocator, pPipeline);
> -   default:
> -  unreachable("unsupported gen\n");
> -   }
> +   return ANV_GEN_DISPATCH(device, graphics_pipeline_create,
> +   _device, cache, pCreateInfo, extra, pAllocator, 
> pPipeline);
>  }
>  
>  VkResult anv_CreateGraphicsPipelines(
> @@ -1235,19 +1224,8 @@ static VkResult anv_compute_pipeline_create(
> ANV_FROM_HANDLE(anv_device, device, _device);
> ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
>  
> -   switch (device->info.gen) {
> -   case 7:
> -  if (device->info.is_haswell)
> - return gen75_compute_pipeline_create(_device, cache, pCreateInfo, 
> pAllocator, pPipeline);
> -  else
> - return gen7_

[Mesa-dev] [Bug 98271] [radeonsi]Playing videos with vdpau or vaapi hardware acceleration crashes my pc

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98271

Andy Furniss  changed:

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 Attachment #127360|text/x-log  |text/plain
  mime type||

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Re: [Mesa-dev] [PATCH 1/6] intel: genxml: add SO_WRITE_OFFSET register

[Kenneth Graunke]

On Wednesday, October 12, 2016 11:27:59 PM PDT Lionel Landwerlin wrote:
> One of the register we happen to program but don't have a description for
> yet.
> 
> Signed-off-by: Lionel Landwerlin 
> ---
>  src/intel/genxml/gen6.xml  | 5 +
>  src/intel/genxml/gen7.xml  | 5 +
>  src/intel/genxml/gen75.xml | 5 +
>  src/intel/genxml/gen8.xml  | 5 +
>  src/intel/genxml/gen9.xml  | 5 +
>  5 files changed, 25 insertions(+)
> 
> diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
> index 52d0ecb..8fc02e0 100644
> --- a/src/intel/genxml/gen6.xml
> +++ b/src/intel/genxml/gen6.xml
> @@ -1968,4 +1968,9 @@
>   type="offset"/>
>
>  
> +  
> +
> +
> +  
> +
>  
> diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
> index 44bb2a7..a5a0571 100644
> --- a/src/intel/genxml/gen7.xml
> +++ b/src/intel/genxml/gen7.xml
> @@ -2521,6 +2521,11 @@
>   end="43" type="MEMORY_OBJECT_CONTROL_STATE"/>
>
>  
> +  
> +
> +
> +  

It looks like this will only handle SO_WRITE_OFFSET0, but not the other
three registers?  (There's only one on Gen6, but 4 on Gen7+.)


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Re: [Mesa-dev] [PATCH 5/6] anv: replace , with ; in anv_batch_emit()

[Kenneth Graunke]

On Wednesday, October 12, 2016 11:28:03 PM PDT Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin 
> ---
>  src/intel/vulkan/genX_cmd_buffer.c| 20 ++--
>  src/intel/vulkan/genX_pipeline_util.h |  4 ++--
>  2 files changed, 12 insertions(+), 12 deletions(-)

This patch is:
Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH] egl/android: fix error in droid_add_configs_for_visuals()

[Eric Engestrom]

On Monday, 2016-10-17 12:04:00 +0100, Emil Velikov wrote:
> On 17 October 2016 at 07:04, Tapani Pälli  wrote:
> > This was some kind of leftover in commit acd35c8 and format_count
> > array variable (declared in outer scope) should be used instead.
> >
> Which brings the question - do we want to enable -Wshadow for the C
> sources. The C++ ones [used to] produce too much noise so they're out
> of the question.

I just had a look at what -Wshadow shows, and it's quite spammy at the
moment, so we might want to have a few cleanup commits before enabling
it, but most of them are just generic var names that could be improved
anyway (color, index, block, etc.). A few of those are in macros, making
the spam even worse, but at the same time easier to fix :)

This var name cleanup sounds like a good introduction task for a newbie,
as it will get you to dive all over the code and have to read a bunch of
code blocks to figure out better names.
I don't have much free time right now anyway, so if no-one's done it by
the time I do (probably in 2-3 weeks) I'll give it a go.

Cheers,
  Eric

> 
> Either way, r-b and pushed to master.
> 
> Thanks
> Emil
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[Mesa-dev] [Bug 98271] [radeonsi]Playing videos with vdpau or vaapi hardware acceleration crashes my pc

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98271

Andy Furniss  changed:

   What|Removed |Added

 Attachment #127357|application/x-shellscript   |text/plain
  mime type||

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[Mesa-dev] [Bug 98279] [vulkan/radeon] dota2 -vulkan hangs the GPU on R9-390

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98279

--- Comment #3 from Manuel Iglesias  ---
Created attachment 127362
  --> https://bugs.freedesktop.org/attachment.cgi?id=127362&action=edit
the log before the computer lock

I got the same problem and i got in dmesg this before the computer crashes.
PD: i got the same GPU R9 390

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Re: [Mesa-dev] [PATCH 6/6] anv: add dispatch macro to find right function for given generation

[Jason Ekstrand]

As a side-note, I pushed code on Friday that gets rid of two of these (the
create_pipeline calls).  I think the best way to solve
emit_state_base_address is by moving a bit of code into genX_cmd_buffer.c.
null surface states probably need to be moved into ISL.

In other words, while it's a nice cleanup, I think the correct answer for
almost all cases is to just stop doing the switches.

On Mon, Oct 17, 2016 at 8:51 AM, Kenneth Graunke 
wrote:

> On Wednesday, October 12, 2016 11:28:04 PM PDT Lionel Landwerlin wrote:
> > Signed-off-by: Lionel Landwerlin 
> > ---
> >  src/intel/vulkan/anv_cmd_buffer.c | 33 ++
> ---
> >  src/intel/vulkan/anv_device.c | 19 +--
> >  src/intel/vulkan/anv_pipeline.c   | 30 --
> >  src/intel/vulkan/anv_private.h| 23 +++
> >  4 files changed, 34 insertions(+), 71 deletions(-)
> >
> > diff --git a/src/intel/vulkan/anv_cmd_buffer.c
> b/src/intel/vulkan/anv_cmd_buffer.c
> > index 5bcd5e0..b051489 100644
> > --- a/src/intel/vulkan/anv_cmd_buffer.c
> > +++ b/src/intel/vulkan/anv_cmd_buffer.c
> > @@ -356,19 +356,9 @@ VkResult anv_ResetCommandBuffer(
> >  void
> >  anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
> *cmd_buffer)
> >  {
> > -   switch (cmd_buffer->device->info.gen) {
> > -   case 7:
> > -  if (cmd_buffer->device->info.is_haswell)
> > - return gen75_cmd_buffer_emit_state_base_address(cmd_buffer);
> > -  else
> > - return gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
> > -   case 8:
> > -  return gen8_cmd_buffer_emit_state_base_address(cmd_buffer);
> > -   case 9:
> > -  return gen9_cmd_buffer_emit_state_base_address(cmd_buffer);
> > -   default:
> > -  unreachable("unsupported gen\n");
> > -   }
> > +   ANV_GEN_DISPATCH(cmd_buffer->device,
> > +cmd_buffer_emit_state_base_address,
> > +cmd_buffer);
> >  }
> >
> >  VkResult anv_BeginCommandBuffer(
> > @@ -714,20 +704,9 @@ static struct anv_state
> >  anv_cmd_buffer_alloc_null_surface_state(struct anv_cmd_buffer
> *cmd_buffer,
> >  struct anv_framebuffer *fb)
> >  {
> > -   switch (cmd_buffer->device->info.gen) {
> > -   case 7:
> > -  if (cmd_buffer->device->info.is_haswell) {
> > - return gen75_cmd_buffer_alloc_null_surface_state(cmd_buffer,
> fb);
> > -  } else {
> > - return gen7_cmd_buffer_alloc_null_surface_state(cmd_buffer,
> fb);
> > -  }
> > -   case 8:
> > -  return gen8_cmd_buffer_alloc_null_surface_state(cmd_buffer, fb);
> > -   case 9:
> > -  return gen9_cmd_buffer_alloc_null_surface_state(cmd_buffer, fb);
> > -   default:
> > -  unreachable("Invalid hardware generation");
> > -   }
> > +   return ANV_GEN_DISPATCH(cmd_buffer->device,
> > +   cmd_buffer_alloc_null_surface_state,
> > +   cmd_buffer, fb);
> >  }
> >
> >  VkResult
> > diff --git a/src/intel/vulkan/anv_device.c
> b/src/intel/vulkan/anv_device.c
> > index 24f7227..6dfdfdb 100644
> > --- a/src/intel/vulkan/anv_device.c
> > +++ b/src/intel/vulkan/anv_device.c
> > @@ -921,24 +921,7 @@ VkResult anv_CreateDevice(
> >
> > anv_queue_init(device, &device->queue);
> >
> > -   switch (device->info.gen) {
> > -   case 7:
> > -  if (!device->info.is_haswell)
> > - result = gen7_init_device_state(device);
> > -  else
> > - result = gen75_init_device_state(device);
> > -  break;
> > -   case 8:
> > -  result = gen8_init_device_state(device);
> > -  break;
> > -   case 9:
> > -  result = gen9_init_device_state(device);
> > -  break;
> > -   default:
> > -  /* Shouldn't get here as we don't create physical devices for any
> other
> > -   * gens. */
> > -  unreachable("unhandled gen");
> > -   }
> > +   result = ANV_GEN_DISPATCH(device, init_device_state, device);
> > if (result != VK_SUCCESS)
> >goto fail_fd;
> >
> > diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_
> pipeline.c
> > index 6b393a6..f9f1cbf 100644
> > --- a/src/intel/vulkan/anv_pipeline.c
> > +++ b/src/intel/vulkan/anv_pipeline.c
> > @@ -1182,19 +1182,8 @@ anv_graphics_pipeline_create(
> > ANV_FROM_HANDLE(anv_device, device, _device);
> > ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
> >
> > -   switch (device->info.gen) {
> > -   case 7:
> > -  if (device->info.is_haswell)
> > - return gen75_graphics_pipeline_create(_device, cache,
> pCreateInfo, extra, pAllocator, pPipeline);
> > -  else
> > - return gen7_graphics_pipeline_create(_device, cache,
> pCreateInfo, extra, pAllocator, pPipeline);
> > -   case 8:
> > -  return gen8_graphics_pipeline_create(_device, cache,
> pCreateInfo, extra, pAllocator, pPipeline);
> > -   case 9:
> > -  return gen9_graphics_pipeline_create(_device, cache,
> pCreateInfo, extra, pAllocator, pPipeline);
> > -   default:
> > -

[Mesa-dev] [Bug 98271] [radeonsi]Playing videos with vdpau or vaapi hardware acceleration crashes my pc

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98271

--- Comment #9 from Andy Furniss  ---
(In reply to John from comment #4)
> Created attachment 127357 [details]
> A quick script I wrote to trigger the issue.

For me this would use s/w dec + --vo=opengl with current mpv.

I guess you have a config or something that changes the mpv defaults? If so
maybe specify what they are, though I don't think I can reproduce with TONGA
using amdgpu anyway.

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[Mesa-dev] [PATCH v2] intel: aubinator: use different colors to signal batch start/end

[Kenneth Graunke]

From: Lionel Landwerlin 

This makes the stream of commands a bit easier to read.

v2 (Ken): Use bold text on green headers for easier readability;
  swap the green and blue headers so the majority stay blue.

Signed-off-by: Lionel Landwerlin 
Signed-off-by: Kenneth Graunke 
---
 src/intel/tools/aubinator.c | 15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

Hi Lionel,

Your patch makes most headers basically unreadable in my terminal
(Konsole with the "Linux Colors" scheme):
http://whitecape.org/paste/konsole-linux-colors-aubinator-ll.png

How about this instead?  With bold text, the green is reasonably
readable, but I still find the blue nicer, so I kept that on the
majority of headers.  The bright green makes the batch start/end
stand out, which is a nice visual cue...

http://whitecape.org/paste/konsole-linux-colors-aubinator-kl.png

diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index d716a65..31c1f89 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -50,8 +50,9 @@
 #define AUB_MI_BATCH_BUFFER_END (0x0500 << 16)
 
 #define CSI "\e["
-#define HEADER CSI "37;44m"
-#define NORMAL CSI "0m"
+#define BLUE_HEADER  CSI "0;44m"
+#define GREEN_HEADER CSI "1;42m"
+#define NORMAL   CSI "0m"
 
 /* options */
 
@@ -727,9 +728,13 @@ parse_commands(struct gen_spec *spec, uint32_t *cmds, int 
size, int engine)
   const char *color, *reset_color = NORMAL;
   uint64_t offset;
 
-  if (option_full_decode)
- color = HEADER;
-  else
+  if (option_full_decode) {
+ if ((p[0] & 0x) == AUB_MI_BATCH_BUFFER_START ||
+ (p[0] & 0x) == AUB_MI_BATCH_BUFFER_END)
+color = GREEN_HEADER;
+ else
+color = BLUE_HEADER;
+  } else
  color = NORMAL;
 
   if (option_color == COLOR_NEVER) {
-- 
2.10.0

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[Mesa-dev] [Bug 98281] 'message's in ctx->Debug.LogMessages[] seem to leak.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98281

--- Comment #5 from Suzuki, Shinji  ---
(In reply to Eero Tamminen from comment #4)
> Just terminate the program with a signal that Valgrind can catch, but the
Thank you for the tip. Very useful when I have to wade my way through tons of
false positives. But I still cherish rare occasion when valgrind quits quietly.

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[Mesa-dev] [Bug 98281] 'message's in ctx->Debug.LogMessages[] seem to leak.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98281

--- Comment #6 from Suzuki, Shinji  ---
(In reply to Emil Velikov from comment #3)
> Can you attach a simple program which reproduces this ? Ideally one which
> does not depend on glew, in order to isolate a problem with it.

Please have a look on the following attachment. In a nutshell, calling
glGetString(GL_EXTENSIONS) within a core-profile context seems to generate the
leak.

==25470== 46 bytes in 1 blocks are definitely lost in loss record 78 of 189
==25470==at 0x4C2DB8F: malloc (in
/usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
==25470==by 0x8DED4C8: debug_message_store (debug_output.c:226)
==25470==by 0x8DED6EC: debug_log_message (debug_output.c:634)
==25470==by 0x8DED6EC: log_msg_locked_and_unlock (debug_output.c:868)
==25470==by 0x8E0D49C: _mesa_error (errors.c:330)
==25470==by 0x8E7FBD3: _mesa_GetString (getstring.c:139)
==25470==by 0x401DF8: main (test.cpp:193)

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[Mesa-dev] [Bug 98281] 'message's in ctx->Debug.LogMessages[] seem to leak.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98281

--- Comment #7 from Suzuki, Shinji  ---
Created attachment 127363
  --> https://bugs.freedesktop.org/attachment.cgi?id=127363&action=edit
A program to reproduce leak by calling glGetString(GL_EXTENSIONS) with
core-profile

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Re: [Mesa-dev] [PATCH v2] intel: aubinator: use different colors to signal batch start/end

[Lionel Landwerlin]

Hi Ken,

Sure, I guess this all depends on your terminal's background color (mine 
is white).

Let's go with your version, having some distinction already helps :)

Reviewed-by: Lionel Landwerlin 

On 17/10/16 17:11, Kenneth Graunke wrote:

From: Lionel Landwerlin 

This makes the stream of commands a bit easier to read.

v2 (Ken): Use bold text on green headers for easier readability;
   swap the green and blue headers so the majority stay blue.

Signed-off-by: Lionel Landwerlin 
Signed-off-by: Kenneth Graunke 
---
  src/intel/tools/aubinator.c | 15 ++-
  1 file changed, 10 insertions(+), 5 deletions(-)

Hi Lionel,

Your patch makes most headers basically unreadable in my terminal
(Konsole with the "Linux Colors" scheme):
http://whitecape.org/paste/konsole-linux-colors-aubinator-ll.png

How about this instead?  With bold text, the green is reasonably
readable, but I still find the blue nicer, so I kept that on the
majority of headers.  The bright green makes the batch start/end
stand out, which is a nice visual cue...

http://whitecape.org/paste/konsole-linux-colors-aubinator-kl.png

diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index d716a65..31c1f89 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -50,8 +50,9 @@
  #define AUB_MI_BATCH_BUFFER_END (0x0500 << 16)
  
  #define CSI "\e["

-#define HEADER CSI "37;44m"
-#define NORMAL CSI "0m"
+#define BLUE_HEADER  CSI "0;44m"
+#define GREEN_HEADER CSI "1;42m"
+#define NORMAL   CSI "0m"
  
  /* options */
  
@@ -727,9 +728,13 @@ parse_commands(struct gen_spec *spec, uint32_t *cmds, int size, int engine)

const char *color, *reset_color = NORMAL;
uint64_t offset;
  
-  if (option_full_decode)

- color = HEADER;
-  else
+  if (option_full_decode) {
+ if ((p[0] & 0x) == AUB_MI_BATCH_BUFFER_START ||
+ (p[0] & 0x) == AUB_MI_BATCH_BUFFER_END)
+color = GREEN_HEADER;
+ else
+color = BLUE_HEADER;
+  } else
   color = NORMAL;
  
if (option_color == COLOR_NEVER) {



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[Mesa-dev] [PATCH] st/va: set default rt formats when calling vaCreateConfig

[Julien Isorce]

As specified in va.h, default value should be set on attributes
not present in the input list.

Signed-off-by: Julien Isorce 
---
 src/gallium/state_trackers/va/config.c  | 9 +
 src/gallium/state_trackers/va/surface.c | 5 +++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/gallium/state_trackers/va/config.c 
b/src/gallium/state_trackers/va/config.c
index 2f96eb6..fb236f1 100644
--- a/src/gallium/state_trackers/va/config.c
+++ b/src/gallium/state_trackers/va/config.c
@@ -195,6 +195,11 @@ vlVaCreateConfig(VADriverContextP ctx, VAProfile profile, 
VAEntrypoint entrypoin
 }
  }
   }
+
+  /* Default value if not specified in the input attributes. */
+  if (!config->rt_format)
+config->rt_format = VA_RT_FORMAT_YUV420 | VA_RT_FORMAT_RGB32;
+
   pipe_mutex_lock(drv->mutex);
   *config_id = handle_table_add(drv->htab, config);
   pipe_mutex_unlock(drv->mutex);
@@ -256,6 +261,10 @@ vlVaCreateConfig(VADriverContextP ctx, VAProfile profile, 
VAEntrypoint entrypoin
   }
}
 
+   /* Default value if not specified in the input attributes. */
+   if (!config->rt_format)
+ config->rt_format = VA_RT_FORMAT_YUV420;
+
pipe_mutex_lock(drv->mutex);
*config_id = handle_table_add(drv->htab, config);
pipe_mutex_unlock(drv->mutex);
diff --git a/src/gallium/state_trackers/va/surface.c 
b/src/gallium/state_trackers/va/surface.c
index 5e92980..f8513d9 100644
--- a/src/gallium/state_trackers/va/surface.c
+++ b/src/gallium/state_trackers/va/surface.c
@@ -419,7 +419,7 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx, VAConfigID 
config_id,
/* vlVaCreateConfig returns PIPE_VIDEO_PROFILE_UNKNOWN
 * only for VAEntrypointVideoProc. */
if (config->profile == PIPE_VIDEO_PROFILE_UNKNOWN) {
-  if (config->rt_format == VA_RT_FORMAT_RGB32) {
+  if (config->rt_format & VA_RT_FORMAT_RGB32) {
  for (j = 0; j < ARRAY_SIZE(vpp_surface_formats); ++j) {
 attribs[i].type = VASurfaceAttribPixelFormat;
 attribs[i].value.type = VAGenericValueTypeInteger;
@@ -427,7 +427,8 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx, VAConfigID 
config_id,
 attribs[i].value.value.i = 
PipeFormatToVaFourcc(vpp_surface_formats[j]);
 i++;
  }
-  } else if (config->rt_format == VA_RT_FORMAT_YUV420) {
+  }
+  if (config->rt_format & VA_RT_FORMAT_YUV420) {
  attribs[i].type = VASurfaceAttribPixelFormat;
  attribs[i].value.type = VAGenericValueTypeInteger;
  attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | 
VA_SURFACE_ATTRIB_SETTABLE;
-- 
1.9.1

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Re: [Mesa-dev] [PATCH] egl/dri2: add a libname to dlopen for OpenBSD

[Emil Velikov]

On 17 October 2016 at 16:39, Eric Engestrom  wrote:
> On Monday, 2016-10-17 22:53:20 +1100, Jonathan Gray wrote:
>> On Mon, Oct 17, 2016 at 12:39:11PM +0100, Emil Velikov wrote:
>> > On 17 October 2016 at 10:53, Eric Engestrom  
>> > wrote:
>> > > On Sunday, 2016-10-16 16:38:35 +1100, Jonathan Gray wrote:
>> > >> On OpenBSD try to dlopen 'libglapi.so', ld.so will find
>> > >> the highest major/minor version and open it in this case.
>> > >>
>> > >> Avoids '#error Unknown glapi provider for this platform' at build time.
>> > >>
>> > >> Signed-off-by: Jonathan Gray 
>> > >
>> > > LGTM, and I guess the other *BSD will want the same since 7a9c92d0 broke
>> > > them too.
>> > >
>> > I'm not 100% sure about that. OpenBSD (unlike other BSD) did bump the
>> > major when the ABI breaks due to 'internal' changes - think of
>> > off_t/time_t on 32 vs 64bit systems and alike.
>> >
>> > Unlike Linux kernel/distros, BSDs tend to be more relaxed when in
>> > comes to ABI, I believe. Don't quote me on that one ;-)
>>
>> OpenBSD tends to favour simplified interfaces over backwards compatiblity
>> and is more like a research system in that respect.  As the kernel
>> and userland are one source tree ioctl compat largely doesn't exist.
>> System calls get deprecated and removed over the course of a few releases.
>> So we didn't go through the pain of duplicated systems calls for off_t
>> as mentioned, and don't go in for symbol versioning.  Just major.minor
>> library versioning, which is roughly symbol removals, major crank,
>> symbol additions minor crank.
>>
>> I believe FreeBSD tends to go in for backwards compatibility more
>> but am not familiar with the details.  They also have a different ld.so.
>>
>> Perhaps an else case for 'libglapi.so.0' would be appropriate for all
>> the other various unices instead of the #error ?
>
> Yeah actually, I'm thinking reverting this hunk of 7a9c92d0 might be a better,
> to avoid the potentially huge list of every *BSD and other Unix:
>
Fwiw I've intentionally added the hunk since I was a bit lazy to check
if the BSD(s?)/Solaris/others have bumped the major locally. Having a
closer look that's not the case, so indeed we can add revert to
libglapi.so.0 in the else statement.

Jonathan, how about we with the above instead ?

Thanks
Emil
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Re: [Mesa-dev] [PATCH] st/va: Default to YUV420 RT format when creating a config

[Julien Isorce]

On 17 October 2016 at 16:27, Mark Thompson  wrote:

> On 17/10/16 16:13, Julien Isorce wrote:
> > Hi Mark,
> >
> > Yes I actually saw that too in the intel driver though I think it does
> not add
> > VA_RT_FORMAT_RGB32 ? Or I missed something ?
> > Maybe this is a bug. In any case yes as said before " the intel va
> driver always
> > return the full list for vpp." from vaQuerySurfaceAttributes
> > no matter the format selected when creating the config.
>
> Looks like the lack of RGB32 has already been noted and fixed:
>  e748bc7f0565d59a7ec2ba038e76a0a1de19c15c>.
>

Great, thx for the link.


>
> > So combining all it should probably be something like this:
> >
> > diff --git a/src/gallium/state_trackers/va/config.c
> > b/src/gallium/state_trackers/va/config.c
> > index 2f96eb6..11afc81 100644
> > --- a/src/gallium/state_trackers/va/config.c
> > +++ b/src/gallium/state_trackers/va/config.c
> > @@ -185,6 +185,8 @@ vlVaCreateConfig(VADriverContextP ctx, VAProfile
> profile,
> > VAEntrypoint entrypoin
> > if (profile == VAProfileNone && entrypoint == VAEntrypointVideoProc)
> {
> >config->entrypoint = VAEntrypointVideoProc;
> >config->profile = PIPE_VIDEO_PROFILE_UNKNOWN;
> > +  config->rt_format = VA_RT_FORMAT_YUV420 | VA_RT_FORMAT_RGB32;
> > +
> >for (int i = 0; i < num_attribs; i++) {
> >   if (attrib_list[i].type == VAConfigAttribRTFormat) {
> >  if (attrib_list[i].value & (VA_RT_FORMAT_YUV420 |
> > VA_RT_FORMAT_RGB32)) {
>
> Please set a default for the non-VideoProc case too, so that codecs have
> the
> same behaviour.
>

Oups


>
> > diff --git a/src/gallium/state_trackers/va/surface.c
> > b/src/gallium/state_trackers/va/surface.c
> > index 5e92980..f8513d9 100644
> > --- a/src/gallium/state_trackers/va/surface.c
> > +++ b/src/gallium/state_trackers/va/surface.c
> > @@ -419,7 +419,7 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx,
> VAConfigID
> > config_id,
> > /* vlVaCreateConfig returns PIPE_VIDEO_PROFILE_UNKNOWN
> >  * only for VAEntrypointVideoProc. */
> > if (config->profile == PIPE_VIDEO_PROFILE_UNKNOWN) {
> > -  if (config->rt_format == VA_RT_FORMAT_RGB32) {
> > +  if (config->rt_format & VA_RT_FORMAT_RGB32) {
> >   for (j = 0; j < ARRAY_SIZE(vpp_surface_formats); ++j) {
> >  attribs[i].type = VASurfaceAttribPixelFormat;
> >  attribs[i].value.type = VAGenericValueTypeInteger;
> > @@ -427,7 +427,8 @@ vlVaQuerySurfaceAttributes(VADriverContextP ctx,
> VAConfigID
> > config_id,
> >  attribs[i].value.value.i =
> > PipeFormatToVaFourcc(vpp_surface_formats[j]);
> >  i++;
> >   }
> > -  } else if (config->rt_format == VA_RT_FORMAT_YUV420) {
> > +  }
> > +  if (config->rt_format & VA_RT_FORMAT_YUV420) {
> >   attribs[i].type = VASurfaceAttribPixelFormat;
> >   attribs[i].value.type = VAGenericValueTypeInteger;
> >   attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE |
> > VA_SURFACE_ATTRIB_SETTABLE;
> >
> > Will it be ok for your case ?
> >
> > Cheers
> > Julien
>
> Yeah, that seems right to me (with the small change above).
>

I sent the patch to mesa-dev few minutes ago, please have a look, thx.

Cheers
Julien


>
> Thanks,
>
> - Mark
>
>
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