[llvm-commits] CVS: llvm/lib/Target/X86/README.txt
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.57 -> 1.58
---
Log message:
Some updates
---
Diffs of the changes: (+31 -9)
README.txt | 40 +++-
1 files changed, 31 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.57 llvm/lib/Target/X86/README.txt:1.58
--- llvm/lib/Target/X86/README.txt:1.57 Thu Feb 16 22:20:13 2006
+++ llvm/lib/Target/X86/README.txt Mon Feb 20 13:58:27 2006
@@ -39,6 +39,19 @@
This should use fiadd on chips where it is profitable:
double foo(double P, int *I) { return P+*I; }
+We have fiadd patterns now but the followings have the same cost and
+complexity. We need a way to specify the later is more profitable.
+
+def FpADD32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
+[(set RFP:$dst, (fadd RFP:$src1,
+ (extloadf64f32 addr:$src2)))]>;
+// ST(0) = ST(0) + [mem32]
+
+def FpIADD32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
+[(set RFP:$dst, (fadd RFP:$src1,
+ (X86fild addr:$src2, i32)))]>;
+// ST(0) = ST(0) + [mem32int]
+
//===-===//
The FP stackifier needs to be global. Also, it should handle simple permutates
@@ -386,11 +399,6 @@
//===-===//
-The x86 backend currently supports dynamic-no-pic. Need to add asm
-printer support for static and PIC.
-
-//===-===//
-
We should generate bts/btr/etc instructions on targets where they are cheap or
when codesize is important. e.g., for:
@@ -419,10 +427,6 @@
//===-===//
-Use fisttp to do FP to integer conversion whenever it is available.
-
-//===-===//
-
Instead of the following for memset char*, 1, 10:
movl $16843009, 4(%edx)
@@ -475,3 +479,21 @@
which is probably slower, but it's interesting at least :)
+//===-===//
+
+Currently the x86 codegen isn't very good at mixing SSE and FPStack
+code:
+
+unsigned int foo(double x) { return x; }
+
+foo:
+ subl $20, %esp
+ movsd 24(%esp), %xmm0
+ movsd %xmm0, 8(%esp)
+ fldl 8(%esp)
+ fisttpll (%esp)
+ movl (%esp), %eax
+ addl $20, %esp
+ ret
+
+This will be solved when we go to a dynamic programming based isel.
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp
Changes in directory llvm-poolalloc/lib/PoolAllocate:
PointerCompress.cpp updated: 1.65 -> 1.66
---
Log message:
Fix cae of malloc of array of objects instead of just malloc of objects
Fixes Shootout/lists (see regression directory for test case)
---
Diffs of the changes: (+13 -0)
PointerCompress.cpp | 13 +
1 files changed, 13 insertions(+)
Index: llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp
diff -u llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp:1.65
llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp:1.66
--- llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp:1.65Wed Jan 25
16:07:36 2006
+++ llvm-poolalloc/lib/PoolAllocate/PointerCompress.cpp Mon Feb 20 16:03:14 2006
@@ -654,6 +654,19 @@
// pointed to the start of a node!
const Type *NTy = PointerType::get(PI->getNewType());
+ //Check if we have a pointer to an array of Original Types this happens if
+ //you do a malloc of [n x OrigTy] for a pool of Type OrigTy
+ if(isa(GEPI.getOperand(0)->getType())) {
+const Type* PT =
+ cast(GEPI.getOperand(0)->getType())->getElementType();
+if(isa(PT)) {
+ if (cast(PT)->getElementType() == PI->getNode()->getType())
+NTy = PointerType::get(ArrayType::get(PI->getNewType(),
+
cast(PT)->getNumElements()));
+}
+ }
+
+
gep_type_iterator GTI = gep_type_begin(GEPI), E = gep_type_end(GEPI);
for (unsigned i = 1, e = GEPI.getNumOperands(); i != e; ++i, ++GTI) {
Value *Idx = GEPI.getOperand(i);
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/ValueTypes.h
Changes in directory llvm/include/llvm/CodeGen: ValueTypes.h updated: 1.17 -> 1.18 --- Log message: Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32). --- Diffs of the changes: (+13 -7) ValueTypes.h | 20 +--- 1 files changed, 13 insertions(+), 7 deletions(-) Index: llvm/include/llvm/CodeGen/ValueTypes.h diff -u llvm/include/llvm/CodeGen/ValueTypes.h:1.17 llvm/include/llvm/CodeGen/ValueTypes.h:1.18 --- llvm/include/llvm/CodeGen/ValueTypes.h:1.17 Tue Feb 7 20:05:45 2006 +++ llvm/include/llvm/CodeGen/ValueTypes.h Mon Feb 20 16:34:53 2006 @@ -48,13 +48,16 @@ Vector = 13, // This is an abstract vector type, which will // be expanded into a target vector type, or scalars // if no matching vector type is available. -v16i8 = 14, // 16 x i8 -v8i16 = 15, // 8 x i16 -v4i32 = 16, // 4 x i32 -v2i64 = 17, // 2 x i64 +v8i8 = 14, // 8 x i8 +v4i16 = 15, // 4 x i16 +v2i32 = 16, // 2 x i32 +v16i8 = 17, // 16 x i8 +v8i16 = 18, // 8 x i16 +v4i32 = 19, // 4 x i32 +v2i64 = 20, // 2 x i64 -v4f32 = 18, // 4 x f32 -v2f64 = 19, // 2 x f64 +v4f32 = 21, // 4 x f32 +v2f64 = 22, // 2 x f64 LAST_VALUETYPE, // This always remains at the end of the list. }; @@ -96,7 +99,10 @@ case MVT::f32 : case MVT::i32 : return 32; case MVT::f64 : -case MVT::i64 : return 64; +case MVT::i64 : +case MVT::v8i8: +case MVT::v4i16: +case MVT::v2i32:return 64; case MVT::f80 : return 80; case MVT::f128: case MVT::i128: ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/Target.td
Changes in directory llvm/lib/Target: Target.td updated: 1.70 -> 1.71 --- Log message: Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32). --- Diffs of the changes: (+9 -6) Target.td | 15 +-- 1 files changed, 9 insertions(+), 6 deletions(-) Index: llvm/lib/Target/Target.td diff -u llvm/lib/Target/Target.td:1.70 llvm/lib/Target/Target.td:1.71 --- llvm/lib/Target/Target.td:1.70 Fri Jan 27 02:09:42 2006 +++ llvm/lib/Target/Target.td Mon Feb 20 16:34:53 2006 @@ -39,12 +39,15 @@ def FlagVT : ValueType<0 , 11>; // Condition code or machine flag def isVoid : ValueType<0 , 12>; // Produces no value def Vector : ValueType<0 , 13>; // Abstract vector value -def v16i8 : ValueType<128, 14>; // 16 x i8 vector value -def v8i16 : ValueType<128, 15>; // 8 x i16 vector value -def v4i32 : ValueType<128, 16>; // 4 x i32 vector value -def v2i64 : ValueType<128, 17>; // 2 x i64 vector value -def v4f32 : ValueType<128, 18>; // 4 x f32 vector value -def v2f64 : ValueType<128, 19>; // 2 x f64 vector value +def v8i8 : ValueType<64 , 14>; // 8 x i8 vector value +def v4i16 : ValueType<64 , 15>; // 4 x i16 vector value +def v2i32 : ValueType<64 , 16>; // 2 x i32 vector value +def v16i8 : ValueType<128, 17>; // 16 x i8 vector value +def v8i16 : ValueType<128, 18>; // 8 x i16 vector value +def v4i32 : ValueType<128, 19>; // 4 x i32 vector value +def v2i64 : ValueType<128, 20>; // 2 x i64 vector value +def v4f32 : ValueType<128, 21>; // 4 x f32 vector value +def v2f64 : ValueType<128, 22>; // 2 x f64 vector value //===--===// // Register file description - These classes are used to fill in the target ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp
Changes in directory llvm/utils/TableGen: CodeGenTarget.cpp updated: 1.54 -> 1.55 --- Log message: Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32). --- Diffs of the changes: (+3 -0) CodeGenTarget.cpp |3 +++ 1 files changed, 3 insertions(+) Index: llvm/utils/TableGen/CodeGenTarget.cpp diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.54 llvm/utils/TableGen/CodeGenTarget.cpp:1.55 --- llvm/utils/TableGen/CodeGenTarget.cpp:1.54 Thu Jan 26 19:45:06 2006 +++ llvm/utils/TableGen/CodeGenTarget.cpp Mon Feb 20 16:34:53 2006 @@ -47,6 +47,9 @@ case MVT::f128: return "f128"; case MVT::Flag: return "Flag"; case MVT::isVoid:return "void"; + case MVT::v8i8: return "v8i8"; + case MVT::v4i16: return "v4i16"; + case MVT::v2i32: return "v2i32"; case MVT::v16i8: return "v16i8"; case MVT::v8i16: return "v8i16"; case MVT::v4i32: return "v4i32"; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td X86RegisterInfo.cpp X86RegisterInfo.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.239 -> 1.240
X86RegisterInfo.cpp updated: 1.124 -> 1.125
X86RegisterInfo.td updated: 1.28 -> 1.29
---
Log message:
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
---
Diffs of the changes: (+37 -20)
X86InstrInfo.td | 16
X86RegisterInfo.cpp | 12 ++--
X86RegisterInfo.td | 29 +++--
3 files changed, 37 insertions(+), 20 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.239
llvm/lib/Target/X86/X86InstrInfo.td:1.240
--- llvm/lib/Target/X86/X86InstrInfo.td:1.239 Fri Feb 17 20:36:28 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Mon Feb 20 16:34:53 2006
@@ -3026,32 +3026,32 @@
// XMM Packed Floating point support (requires SSE / SSE2)
//===--===//
-def MOVAPSrr : I<0x28, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
+def MOVAPSrr : I<0x28, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
"movaps {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE1]>, TB;
-def MOVAPDrr : I<0x28, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
+def MOVAPDrr : I<0x28, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
"movapd {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE2]>, TB, OpSize;
-def MOVAPSrm : I<0x28, MRMSrcMem, (ops V4F4:$dst, f128mem:$src),
+def MOVAPSrm : I<0x28, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
"movaps {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE1]>, TB;
-def MOVAPSmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V4F4:$src),
+def MOVAPSmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V4F32:$src),
"movaps {$src, $dst|$dst, $src}",[]>,
Requires<[HasSSE1]>, TB;
-def MOVAPDrm : I<0x28, MRMSrcMem, (ops V2F8:$dst, f128mem:$src),
+def MOVAPDrm : I<0x28, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
"movapd {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE1]>, TB, OpSize;
-def MOVAPDmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V2F8:$src),
+def MOVAPDmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V2F64:$src),
"movapd {$src, $dst|$dst, $src}",[]>,
Requires<[HasSSE2]>, TB, OpSize;
// Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
// Upper bits are disregarded.
-def FsMOVAPSrr : I<0x28, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
+def FsMOVAPSrr : I<0x28, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
"movaps {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE1]>, TB;
-def FsMOVAPDrr : I<0x28, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
+def FsMOVAPDrr : I<0x28, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
"movapd {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE2]>, TB, OpSize;
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.124
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.125
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.124 Thu Feb 16 16:45:17 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Mon Feb 20 16:34:53 2006
@@ -61,9 +61,9 @@
Opc = X86::MOVSSmr;
} else if (RC == &X86::FR64RegClass) {
Opc = X86::MOVSDmr;
- } else if (RC == &X86::V4F4RegClass) {
+ } else if (RC == &X86::V4F32RegClass) {
Opc = X86::MOVAPSmr;
- } else if (RC == &X86::V2F8RegClass) {
+ } else if (RC == &X86::V2F64RegClass) {
Opc = X86::MOVAPDmr;
} else {
assert(0 && "Unknown regclass");
@@ -89,9 +89,9 @@
Opc = X86::MOVSSrm;
} else if (RC == &X86::FR64RegClass) {
Opc = X86::MOVSDrm;
- } else if (RC == &X86::V4F4RegClass) {
+ } else if (RC == &X86::V4F32RegClass) {
Opc = X86::MOVAPSrm;
- } else if (RC == &X86::V2F8RegClass) {
+ } else if (RC == &X86::V2F64RegClass) {
Opc = X86::MOVAPDrm;
} else {
assert(0 && "Unknown regclass");
@@ -113,9 +113,9 @@
Opc = X86::MOV16rr;
} else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
Opc = X86::FpMOV;
- } else if (RC == &X86::FR32RegClass || RC == &X86::V4F4RegClass) {
+ } else if (RC == &X86::FR32RegClass || RC == &X86::V4F32RegClass) {
Opc = X86::FsMOVAPSrr;
- } else if (RC == &X86::FR64RegClass || RC == &X86::V2F8RegClass) {
+ } else if (RC == &X86::FR64RegClass || RC == &X86::V2F64RegClass) {
Opc = X86::FsMOVAPDrr;
} else {
assert(0 && "Unknown regclass");
Index: llvm/lib/Target/X86/X86RegisterInfo.td
diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.28
llvm/lib/Target/X86/X86RegisterInfo.td:1.29
--- llvm/lib/Target/X86/X86RegisterInfo.td:1.28 Wed Jan 25 18:29:36 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.td Mon Feb 20 16:34:53 2006
@@ -40,6 +40,12 @@
def DL : RegisterGroup<"DL", [DX,EDX]>; def BL :
RegisterGroup<"BL",[BX,EBX]>;
de
[llvm-commits] CVS: llvm/lib/CodeGen/ValueTypes.cpp
Changes in directory llvm/lib/CodeGen: ValueTypes.cpp updated: 1.6 -> 1.7 --- Log message: Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32). --- Diffs of the changes: (+3 -0) ValueTypes.cpp |3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/CodeGen/ValueTypes.cpp diff -u llvm/lib/CodeGen/ValueTypes.cpp:1.6 llvm/lib/CodeGen/ValueTypes.cpp:1.7 --- llvm/lib/CodeGen/ValueTypes.cpp:1.6 Mon Nov 28 23:45:28 2005 +++ llvm/lib/CodeGen/ValueTypes.cpp Mon Feb 20 16:34:53 2006 @@ -34,6 +34,9 @@ case MVT::Other: return "ch"; case MVT::Flag: return "flag"; case MVT::Vector:return "vec"; + case MVT::v8i8: return "v8i8"; + case MVT::v4i16: return "v4i16"; + case MVT::v2i32: return "v2i32"; case MVT::v16i8: return "v16i8"; case MVT::v8i16: return "v8i16"; case MVT::v4i32: return "v4i32"; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86RegisterInfo.td
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.125 -> 1.126
X86RegisterInfo.td updated: 1.29 -> 1.30
---
Log message:
Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64.
Added generic vector types: VR64 and VR128.
---
Diffs of the changes: (+27 -9)
X86RegisterInfo.cpp |8 ++--
X86RegisterInfo.td | 28 +---
2 files changed, 27 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.125
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.126
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.125 Mon Feb 20 16:34:53 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Mon Feb 20 19:38:21 2006
@@ -113,10 +113,14 @@
Opc = X86::MOV16rr;
} else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
Opc = X86::FpMOV;
- } else if (RC == &X86::FR32RegClass || RC == &X86::V4F32RegClass) {
+ } else if (RC == &X86::FR32RegClass) {
Opc = X86::FsMOVAPSrr;
- } else if (RC == &X86::FR64RegClass || RC == &X86::V2F64RegClass) {
+ } else if (RC == &X86::FR64RegClass) {
Opc = X86::FsMOVAPDrr;
+ } else if (RC == &X86::V4F32RegClass) {
+Opc = X86::MOVAPSrr;
+ } else if (RC == &X86::V2F64RegClass) {
+Opc = X86::MOVAPDrr;
} else {
assert(0 && "Unknown regclass");
abort();
Index: llvm/lib/Target/X86/X86RegisterInfo.td
diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.29
llvm/lib/Target/X86/X86RegisterInfo.td:1.30
--- llvm/lib/Target/X86/X86RegisterInfo.td:1.29 Mon Feb 20 16:34:53 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.td Mon Feb 20 19:38:21 2006
@@ -140,13 +140,22 @@
}
// Vector integer registers: V8I8, the 8 x i8 class, V4I16, the 4 x i16 class,
-// and V2I32, the 2 x i32 class.
-def V8I8 : RegisterClass<"X86", [v8i8], 64, [MM0, MM1, MM2, MM3, MM4, MM5,
- MM6, MM7]>;
-def V4I16 : RegisterClass<"X86", [v4i16], 64, [MM0, MM1, MM2, MM3, MM4, MM5,
- MM6, MM7]>;
-def V2I32 : RegisterClass<"X86", [v2i32], 64, [MM0, MM1, MM2, MM3, MM4, MM5,
- MM6, MM7]>;
+// V2I32, the 2 x i32 class, V16I8, the 16 x i8 class, V8I16, the 8 x i16
class,
+// V4I32, the 4 x i32 class, and V2I64, the 2 x i64 class.
+def V8I8 : RegisterClass<"X86", [v8i8], 64,
+ [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
+def V4I16 : RegisterClass<"X86", [v4i16], 64,
+ [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
+def V2I32 : RegisterClass<"X86", [v2i32], 64,
+ [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
+def V16I8 : RegisterClass<"X86", [v16i8], 128,
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
+def V8I16 : RegisterClass<"X86", [v8i16], 128,
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
+def V4I32 : RegisterClass<"X86", [v4i32], 128,
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
+def V2I64 : RegisterClass<"X86", [v2i64], 128,
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
// Vector floating point registers: V4F4, the 4 x f32 class, and V2F8,
// the 2 x f64 class.
@@ -155,3 +164,8 @@
def V2F64 : RegisterClass<"X86", [v2f64], 128,
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
+// Generic vector registers: VR64 and VR128.
+def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32], 64,
+ [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
+def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32,
v2f64],128,
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.240 -> 1.241
---
Log message:
Added MMX and XMM packed integer move instructions, movd and movq.
---
Diffs of the changes: (+46 -0)
X86InstrInfo.td | 46 ++
1 files changed, 46 insertions(+)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.240
llvm/lib/Target/X86/X86InstrInfo.td:1.241
--- llvm/lib/Target/X86/X86InstrInfo.td:1.240 Mon Feb 20 16:34:53 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Mon Feb 20 19:39:57 2006
@@ -3023,6 +3023,52 @@
//===--===//
+// MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
+//===--===//
+
+// Move Instructions
+def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, R32:$src),
+ "movd {$src, $dst|$dst, $src}", []>, TB,
+ Requires<[HasSSE1]>;
+def MOVD64rm : I<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
+ "movd {$src, $dst|$dst, $src}", []>, TB,
+ Requires<[HasSSE1]>;
+def MOVD64mr : I<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
+ "movd {$src, $dst|$dst, $src}", []>, TB,
+ Requires<[HasSSE1]>;
+
+def MOVD128rr : I<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src),
+ "movd {$src, $dst|$dst, $src}", []>, TB, OpSize,
+Requires<[HasSSE2]>;
+def MOVD128rm : I<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
+ "movd {$src, $dst|$dst, $src}", []>, TB, OpSize,
+Requires<[HasSSE2]>;
+def MOVD128mr : I<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
+ "movd {$src, $dst|$dst, $src}", []>, TB, OpSize,
+Requires<[HasSSE2]>;
+
+
+def MOVQ64rr : I<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
+ "movq {$src, $dst|$dst, $src}", []>, TB,
+ Requires<[HasSSE1]>;
+def MOVQ64rm : I<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
+ "movq {$src, $dst|$dst, $src}", []>, TB,
+ Requires<[HasSSE1]>;
+def MOVQ64mr : I<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
+ "movq {$src, $dst|$dst, $src}", []>, TB,
+ Requires<[HasSSE1]>;
+
+def MOVQ128rr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src),
+ "movq {$src, $dst|$dst, $src}", []>, XS,
+Requires<[HasSSE2]>;
+def MOVQ128rm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
+ "movq {$src, $dst|$dst, $src}", []>, XS,
+Requires<[HasSSE2]>;
+def MOVQ128mr : I<0xD6, MRMSrcMem, (ops i64mem:$dst, VR128:$src),
+ "movq {$src, $dst|$dst, $src}", []>, TB, OpSize,
+Requires<[HasSSE2]>;
+
+//===--===//
// XMM Packed Floating point support (requires SSE / SSE2)
//===--===//
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.241 -> 1.242
---
Log message:
Added separate alias instructions for SSE logical ops that operate on
non-packed types.
---
Diffs of the changes: (+171 -96)
X86InstrInfo.td | 267 +++-
1 files changed, 171 insertions(+), 96 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.241
llvm/lib/Target/X86/X86InstrInfo.td:1.242
--- llvm/lib/Target/X86/X86InstrInfo.td:1.241 Mon Feb 20 19:39:57 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Mon Feb 20 20:24:38 2006
@@ -356,8 +356,11 @@
def extloadi8i1: PatFrag<(ops node:$ptr), (i8 (extload node:$ptr, i1))>;
def extloadf64f32 : PatFrag<(ops node:$ptr), (f64 (extload node:$ptr, f32))>;
-def X86loadpf32: PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
-def X86loadpf64: PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
+def X86loadpf32: PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
+def X86loadpf64: PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
+
+def X86loadpv4f32 : PatFrag<(ops node:$ptr), (v4f32 (X86loadp node:$ptr))>;
+def X86loadpv2f64 : PatFrag<(ops node:$ptr), (v2f64 (X86loadp node:$ptr))>;
//===--===//
// Instruction templates...
@@ -705,18 +708,6 @@
"mov{l} {$src, $dst|$dst, $src}",
[(store R32:$src, addr:$dst)]>;
-// Pseudo-instructions that map movr0 to xor.
-// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-def MOV8r0 : I<0x30, MRMInitReg, (ops R8 :$dst),
- "xor{b} $dst, $dst",
- [(set R8:$dst, 0)]>;
-def MOV16r0 : I<0x31, MRMInitReg, (ops R16:$dst),
- "xor{w} $dst, $dst",
- [(set R16:$dst, 0)]>, OpSize;
-def MOV32r0 : I<0x31, MRMInitReg, (ops R32:$dst),
- "xor{l} $dst, $dst",
- [(set R32:$dst, 0)]>;
-
//===--===//
// Fixed-Register Multiplication and Division Instructions...
//
@@ -2485,15 +2476,6 @@
[(X86cmp FR64:$src1, (loadf64 addr:$src2))]>,
Requires<[HasSSE2]>, TB, OpSize;
-// Pseudo-instructions that map fld0 to pxor for sse.
-// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-def FLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
- "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
- Requires<[HasSSE1]>, TB, OpSize;
-def FLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
- "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
- Requires<[HasSSE2]>, TB, OpSize;
-
let isTwoAddress = 1 in {
// SSE Scalar Arithmetic
let isCommutable = 1 in {
@@ -2583,71 +2565,6 @@
(ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
"cmp${cc}sd {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE2]>, XD;
-
-// SSE Logical - these all operate on packed values
-let isCommutable = 1 in {
-def ANDPSrr : I<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
-"andps {$src2, $dst|$dst, $src2}",
-[(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>,
- Requires<[HasSSE1]>, TB;
-def ANDPDrr : I<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
-"andpd {$src2, $dst|$dst, $src2}",
-[(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>,
- Requires<[HasSSE2]>, TB, OpSize;
-def ORPSrr : I<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
-"orps {$src2, $dst|$dst, $src2}", []>,
- Requires<[HasSSE1]>, TB;
-def ORPDrr : I<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
-"orpd {$src2, $dst|$dst, $src2}", []>,
- Requires<[HasSSE2]>, TB, OpSize;
-def XORPSrr : I<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
-"xorps {$src2, $dst|$dst, $src2}",
-[(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>,
- Requires<[HasSSE1]>, TB;
-def XORPDrr : I<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
-"xorpd {$src2, $dst|$dst, $src2}",
-[(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>,
- Requires<[HasSSE2]>, TB, OpSize;
-}
-def ANDPSrm : I<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
-"andps {$src2, $dst|$dst, $src2}",
-[(set FR32:$dst, (X86fand FR32:$src1,
- (X86loadpf32 addr:$src2)))]>,
- Requires<[HasSSE1]>, TB;
-def ANDPDrm : I<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
-"andpd {$src2, $dst|$dst, $src2}",
-[(set FR64:$dst, (X86fand FR64:$src1,
- (X86lo
