Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.239 -> 1.240
X86RegisterInfo.cpp updated: 1.124 -> 1.125
X86RegisterInfo.td updated: 1.28 -> 1.29
---
Log message:
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
---
Diffs of the changes: (+37 -20)
X86InstrInfo.td | 16 ++++++++--------
X86RegisterInfo.cpp | 12 ++++++------
X86RegisterInfo.td | 29 +++++++++++++++++++++++------
3 files changed, 37 insertions(+), 20 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.239
llvm/lib/Target/X86/X86InstrInfo.td:1.240
--- llvm/lib/Target/X86/X86InstrInfo.td:1.239 Fri Feb 17 20:36:28 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Mon Feb 20 16:34:53 2006
@@ -3026,32 +3026,32 @@
// XMM Packed Floating point support (requires SSE / SSE2)
//===----------------------------------------------------------------------===//
-def MOVAPSrr : I<0x28, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
+def MOVAPSrr : I<0x28, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
"movaps {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE1]>, TB;
-def MOVAPDrr : I<0x28, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
+def MOVAPDrr : I<0x28, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
"movapd {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE2]>, TB, OpSize;
-def MOVAPSrm : I<0x28, MRMSrcMem, (ops V4F4:$dst, f128mem:$src),
+def MOVAPSrm : I<0x28, MRMSrcMem, (ops V4F32:$dst, f128mem:$src),
"movaps {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE1]>, TB;
-def MOVAPSmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V4F4:$src),
+def MOVAPSmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V4F32:$src),
"movaps {$src, $dst|$dst, $src}",[]>,
Requires<[HasSSE1]>, TB;
-def MOVAPDrm : I<0x28, MRMSrcMem, (ops V2F8:$dst, f128mem:$src),
+def MOVAPDrm : I<0x28, MRMSrcMem, (ops V2F64:$dst, f128mem:$src),
"movapd {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE1]>, TB, OpSize;
-def MOVAPDmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V2F8:$src),
+def MOVAPDmr : I<0x29, MRMDestMem, (ops f128mem:$dst, V2F64:$src),
"movapd {$src, $dst|$dst, $src}",[]>,
Requires<[HasSSE2]>, TB, OpSize;
// Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
// Upper bits are disregarded.
-def FsMOVAPSrr : I<0x28, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
+def FsMOVAPSrr : I<0x28, MRMSrcReg, (ops V4F32:$dst, V4F32:$src),
"movaps {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE1]>, TB;
-def FsMOVAPDrr : I<0x28, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
+def FsMOVAPDrr : I<0x28, MRMSrcReg, (ops V2F64:$dst, V2F64:$src),
"movapd {$src, $dst|$dst, $src}", []>,
Requires<[HasSSE2]>, TB, OpSize;
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.124
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.125
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.124 Thu Feb 16 16:45:17 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Mon Feb 20 16:34:53 2006
@@ -61,9 +61,9 @@
Opc = X86::MOVSSmr;
} else if (RC == &X86::FR64RegClass) {
Opc = X86::MOVSDmr;
- } else if (RC == &X86::V4F4RegClass) {
+ } else if (RC == &X86::V4F32RegClass) {
Opc = X86::MOVAPSmr;
- } else if (RC == &X86::V2F8RegClass) {
+ } else if (RC == &X86::V2F64RegClass) {
Opc = X86::MOVAPDmr;
} else {
assert(0 && "Unknown regclass");
@@ -89,9 +89,9 @@
Opc = X86::MOVSSrm;
} else if (RC == &X86::FR64RegClass) {
Opc = X86::MOVSDrm;
- } else if (RC == &X86::V4F4RegClass) {
+ } else if (RC == &X86::V4F32RegClass) {
Opc = X86::MOVAPSrm;
- } else if (RC == &X86::V2F8RegClass) {
+ } else if (RC == &X86::V2F64RegClass) {
Opc = X86::MOVAPDrm;
} else {
assert(0 && "Unknown regclass");
@@ -113,9 +113,9 @@
Opc = X86::MOV16rr;
} else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
Opc = X86::FpMOV;
- } else if (RC == &X86::FR32RegClass || RC == &X86::V4F4RegClass) {
+ } else if (RC == &X86::FR32RegClass || RC == &X86::V4F32RegClass) {
Opc = X86::FsMOVAPSrr;
- } else if (RC == &X86::FR64RegClass || RC == &X86::V2F8RegClass) {
+ } else if (RC == &X86::FR64RegClass || RC == &X86::V2F64RegClass) {
Opc = X86::FsMOVAPDrr;
} else {
assert(0 && "Unknown regclass");
Index: llvm/lib/Target/X86/X86RegisterInfo.td
diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.28
llvm/lib/Target/X86/X86RegisterInfo.td:1.29
--- llvm/lib/Target/X86/X86RegisterInfo.td:1.28 Wed Jan 25 18:29:36 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.td Mon Feb 20 16:34:53 2006
@@ -40,6 +40,12 @@
def DL : RegisterGroup<"DL", [DX,EDX]>; def BL :
RegisterGroup<"BL",[BX,EBX]>;
def AH : RegisterGroup<"AH", [AX,EAX]>; def CH :
RegisterGroup<"CH",[CX,ECX]>;
def DH : RegisterGroup<"DH", [DX,EDX]>; def BH :
RegisterGroup<"BH",[BX,EBX]>;
+
+ // MMX Registers. These are actually aliased to ST0 .. ST7
+ def MM0 : Register<"MM0">; def MM1 : Register<"MM1">;
+ def MM2 : Register<"MM2">; def MM3 : Register<"MM3">;
+ def MM4 : Register<"MM4">; def MM5 : Register<"MM5">;
+ def MM6 : Register<"MM6">; def MM7 : Register<"MM7">;
// Pseudo Floating Point registers
def FP0 : Register<"FP0">; def FP1 : Register<"FP1">;
@@ -108,12 +114,6 @@
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
def FR64 : RegisterClass<"X86", [f64], 64,
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
-// Vector floating point registers: V4F4, the 4 x f32 class, and V2F8,
-// the 2 x f64 class.
-def V4F4 : RegisterClass<"X86", [f32], 32,
- [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
-def V2F8 : RegisterClass<"X86", [f64], 64,
- [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
// FIXME: This sets up the floating point register files as though they are f64
// values, though they really are f80 values. This will cause us to spill
@@ -138,3 +138,20 @@
}
}];
}
+
+// Vector integer registers: V8I8, the 8 x i8 class, V4I16, the 4 x i16 class,
+// and V2I32, the 2 x i32 class.
+def V8I8 : RegisterClass<"X86", [v8i8], 64, [MM0, MM1, MM2, MM3, MM4, MM5,
+ MM6, MM7]>;
+def V4I16 : RegisterClass<"X86", [v4i16], 64, [MM0, MM1, MM2, MM3, MM4, MM5,
+ MM6, MM7]>;
+def V2I32 : RegisterClass<"X86", [v2i32], 64, [MM0, MM1, MM2, MM3, MM4, MM5,
+ MM6, MM7]>;
+
+// Vector floating point registers: V4F4, the 4 x f32 class, and V2F8,
+// the 2 x f64 class.
+def V4F32 : RegisterClass<"X86", [v4f32], 128,
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
+def V2F64 : RegisterClass<"X86", [v2f64], 128,
+ [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
+
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