[llvm-branch-commits] [llvm] release/19.x: [RegisterCoalescer] Fix SUBREG_TO_REG handling in the RegisterCoalescer. (#96839) (PR #101071)
https://github.com/qcolombet approved this pull request. Thanks for the back port. LGTM https://github.com/llvm/llvm-project/pull/101071 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm-branch] r244976 - [release_37] Revert r242173 since it breaks R9 290X.
Author: qcolombet
Date: Thu Aug 13 17:52:11 2015
New Revision: 244976
URL: http://llvm.org/viewvc/llvm-project?rev=244976&view=rev
Log:
[release_37] Revert r242173 since it breaks R9 290X.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91588
Modified:
llvm/branches/release_37/include/llvm/CodeGen/LiveRegMatrix.h
llvm/branches/release_37/include/llvm/CodeGen/MachineRegisterInfo.h
llvm/branches/release_37/lib/CodeGen/ExecutionDepsFix.cpp
llvm/branches/release_37/lib/CodeGen/LiveRegMatrix.cpp
llvm/branches/release_37/lib/CodeGen/MachineRegisterInfo.cpp
llvm/branches/release_37/lib/CodeGen/PrologEpilogInserter.cpp
llvm/branches/release_37/lib/CodeGen/RegAllocFast.cpp
llvm/branches/release_37/lib/CodeGen/VirtRegMap.cpp
llvm/branches/release_37/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
llvm/branches/release_37/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/branches/release_37/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
llvm/branches/release_37/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp
llvm/branches/release_37/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/branches/release_37/lib/Target/Hexagon/HexagonFrameLowering.cpp
llvm/branches/release_37/lib/Target/PowerPC/PPCFrameLowering.cpp
llvm/branches/release_37/lib/Target/Sparc/SparcFrameLowering.cpp
llvm/branches/release_37/lib/Target/X86/X86FloatingPoint.cpp
llvm/branches/release_37/lib/Target/X86/X86FrameLowering.cpp
Modified: llvm/branches/release_37/include/llvm/CodeGen/LiveRegMatrix.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/include/llvm/CodeGen/LiveRegMatrix.h?rev=244976&r1=244975&r2=244976&view=diff
==
--- llvm/branches/release_37/include/llvm/CodeGen/LiveRegMatrix.h (original)
+++ llvm/branches/release_37/include/llvm/CodeGen/LiveRegMatrix.h Thu Aug 13
17:52:11 2015
@@ -32,11 +32,13 @@ namespace llvm {
class LiveInterval;
class LiveIntervalAnalysis;
+class MachineRegisterInfo;
class TargetRegisterInfo;
class VirtRegMap;
class LiveRegMatrix : public MachineFunctionPass {
const TargetRegisterInfo *TRI;
+ MachineRegisterInfo *MRI;
LiveIntervals *LIS;
VirtRegMap *VRM;
Modified: llvm/branches/release_37/include/llvm/CodeGen/MachineRegisterInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/include/llvm/CodeGen/MachineRegisterInfo.h?rev=244976&r1=244975&r2=244976&view=diff
==
--- llvm/branches/release_37/include/llvm/CodeGen/MachineRegisterInfo.h
(original)
+++ llvm/branches/release_37/include/llvm/CodeGen/MachineRegisterInfo.h Thu Aug
13 17:52:11 2015
@@ -95,8 +95,20 @@ private:
return MO->Contents.Reg.Next;
}
+ /// UsedRegUnits - This is a bit vector that is computed and set by the
+ /// register allocator, and must be kept up to date by passes that run after
+ /// register allocation (though most don't modify this). This is used
+ /// so that the code generator knows which callee save registers to save and
+ /// for other target specific uses.
+ /// This vector has bits set for register units that are modified in the
+ /// current function. It doesn't include registers clobbered by function
+ /// calls with register mask operands.
+ BitVector UsedRegUnits;
+
/// UsedPhysRegMask - Additional used physregs including aliases.
/// This bit vector represents all the registers clobbered by function calls.
+ /// It can model things that UsedRegUnits can't, such as function calls that
+ /// clobber ymm7 but preserve the low half in xmm7.
BitVector UsedPhysRegMask;
/// ReservedRegs - This is a bit vector of reserved registers. The target
@@ -641,12 +653,55 @@ public:
/// ignored.
bool isPhysRegModified(unsigned PhysReg) const;
+
//======//
+ // Physical Register Use Info
+
//======//
+
+ /// isPhysRegUsed - Return true if the specified register is used in this
+ /// function. Also check for clobbered aliases and registers clobbered by
+ /// function calls with register mask operands.
+ ///
+ /// This only works after register allocation.
+ bool isPhysRegUsed(unsigned Reg) const {
+if (UsedPhysRegMask.test(Reg))
+ return true;
+for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
+ Units.isValid(); ++Units)
+ if (UsedRegUnits.test(*Units))
+return true;
+return false;
+ }
+
+ /// Mark the specified register unit as used in this function.
+ /// This should only be called during and after register allocation.
+ void setRegUnitUsed(unsigned RegUnit) {
+UsedRegUnits.set(RegUnit);
+ }
+
+ /// setPhysRegUsed - Mark the specified register used in this function.
+ /// This should only be called during and after register allocati
[llvm-branch-commits] [llvm-branch] r258268 - Merging r258207:
Author: qcolombet
Date: Tue Jan 19 19:09:12 2016
New Revision: 258268
URL: http://llvm.org/viewvc/llvm-project?rev=258268&view=rev
Log:
Merging r258207:
r258207 | qcolombet | 2016-01-19 14:31:12 -0800 (Tue, 19 Jan 2016) | 1 line
[MachineFunction] Constify getter. NFC.
Modified:
llvm/branches/release_38/ (props changed)
llvm/branches/release_38/include/llvm/CodeGen/MachineFunction.h
llvm/branches/release_38/lib/CodeGen/MachineFunction.cpp
Propchange: llvm/branches/release_38/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Jan 19 19:09:12 2016
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257902,257905,257925,257929-257930,257977,257979,257997,258168
+/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257902,257905,257925,257929-257930,257977,257979,257997,258168,258207
Modified: llvm/branches/release_38/include/llvm/CodeGen/MachineFunction.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/include/llvm/CodeGen/MachineFunction.h?rev=258268&r1=258267&r2=258268&view=diff
==
--- llvm/branches/release_38/include/llvm/CodeGen/MachineFunction.h (original)
+++ llvm/branches/release_38/include/llvm/CodeGen/MachineFunction.h Tue Jan 19
19:09:12 2016
@@ -295,7 +295,7 @@ public:
}
/// Should we be emitting segmented stack stuff for the function
- bool shouldSplitStack();
+ bool shouldSplitStack() const;
/// getNumBlockIDs - Return the number of MBB ID's allocated.
///
Modified: llvm/branches/release_38/lib/CodeGen/MachineFunction.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/CodeGen/MachineFunction.cpp?rev=258268&r1=258267&r2=258268&view=diff
==
--- llvm/branches/release_38/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/branches/release_38/lib/CodeGen/MachineFunction.cpp Tue Jan 19
19:09:12 2016
@@ -163,7 +163,7 @@ getOrCreateJumpTableInfo(unsigned EntryK
}
/// Should we be emitting segmented stack stuff for the function
-bool MachineFunction::shouldSplitStack() {
+bool MachineFunction::shouldSplitStack() const {
return getFunction()->hasFnAttribute("split-stack");
}
___
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[llvm-branch-commits] [llvm-branch] r258269 - Merging r258221:
Author: qcolombet
Date: Tue Jan 19 19:14:03 2016
New Revision: 258269
URL: http://llvm.org/viewvc/llvm-project?rev=258269&view=rev
Log:
Merging r258221:
r258221 | qcolombet | 2016-01-19 15:29:03 -0800 (Tue, 19 Jan 2016) | 8 lines
[X86] Do not run shrink-wrapping on function with split-stack attribute or HiPE
calling convention.
The implementation of the related callbacks in the x86 backend for such
functions are not ready to deal with a prologue block that is not the entry
block of the function.
This fixes PR26107, but the longer term solution would be to fix those
callbacks.
Modified:
llvm/branches/release_38/ (props changed)
llvm/branches/release_38/lib/Target/X86/X86FrameLowering.cpp
llvm/branches/release_38/test/CodeGen/X86/x86-shrink-wrap-unwind.ll
Propchange: llvm/branches/release_38/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Jan 19 19:14:03 2016
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257902,257905,257925,257929-257930,257977,257979,257997,258168,258207
+/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257902,257905,257925,257929-257930,257977,257979,257997,258168,258207,258221
Modified: llvm/branches/release_38/lib/Target/X86/X86FrameLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/X86/X86FrameLowering.cpp?rev=258269&r1=258268&r2=258269&view=diff
==
--- llvm/branches/release_38/lib/Target/X86/X86FrameLowering.cpp (original)
+++ llvm/branches/release_38/lib/Target/X86/X86FrameLowering.cpp Tue Jan 19
19:14:03 2016
@@ -2031,6 +2031,10 @@ void X86FrameLowering::adjustForSegmente
unsigned TlsReg, TlsOffset;
DebugLoc DL;
+ // To support shrink-wrapping we would need to insert the new blocks
+ // at the right place and update the branches to PrologueMBB.
+ assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported
yet");
+
unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
"Scratch register is live-in");
@@ -2271,6 +2275,11 @@ void X86FrameLowering::adjustForHiPEProl
MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
MachineFrameInfo *MFI = MF.getFrameInfo();
DebugLoc DL;
+
+ // To support shrink-wrapping we would need to insert the new blocks
+ // at the right place and update the branches to PrologueMBB.
+ assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported
yet");
+
// HiPE-specific values
const unsigned HipeLeafWords = 24;
const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
@@ -2584,7 +2593,14 @@ bool X86FrameLowering::canUseAsEpilogue(
bool X86FrameLowering::enableShrinkWrapping(const MachineFunction &MF) const {
// If we may need to emit frameless compact unwind information, give
// up as this is currently broken: PR25614.
- return MF.getFunction()->hasFnAttribute(Attribute::NoUnwind) || hasFP(MF);
+ return (MF.getFunction()->hasFnAttribute(Attribute::NoUnwind) || hasFP(MF))
&&
+ // The lowering of segmented stack and HiPE only support entry blocks
+ // as prologue blocks: PR26107.
+ // This limitation may be lifted if we fix:
+ // - adjustForSegmentedStacks
+ // - adjustForHiPEPrologue
+ MF.getFunction()->getCallingConv() != CallingConv::HiPE &&
+ !MF.shouldSplitStack();
}
MachineBasicBlock::iterator X86FrameLowering::restoreWin32EHStackPointers(
Modified: llvm/branches/release_38/test/CodeGen/X86/x86-shrink-wrap-unwind.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/X86/x86-shrink-wrap-unwind.ll?rev=258269&r1=258268&r2=258269&view=diff
==
--- llvm/branches/release_38/test/CodeGen/X86/x86-shrink-wrap-unwind.ll
(original)
+++ llvm/branches/release_38/test/CodeGen/X86/x86-shrink-wrap-unwind.ll Tue Jan
19 19:14:03 2016
@@ -1,11 +1,5 @@
; RUN: llc %s -o - | FileCheck %s --check-prefix=CHECK
;
-; This test checks that we do not use shrink-wrapping when
-; the function does not have any frame pointer and may unwind.
-; This is a workaround for a limitation in the emission of
-; the CFI directives, that are not correct in such case.
-; PR25614
-;
; Note: This test cannot be merged with the shrink-wrapping tests
; because the booleans set on the command line take precedence on
; the target logic that disable shrink-wrapping.
@@ -13,6 +7,12 @@ target datalayout = "e-m:o-i64:64-i128:1
target triple = "x86_64-apple-macosx"
+; This test checks that we do
[llvm-branch-commits] [llvm-branch] r261586 - [AArch64] Fix bug in prolog clobbering live reg when shrink wrapping.
Author: qcolombet
Date: Mon Feb 22 16:27:47 2016
New Revision: 261586
URL: http://llvm.org/viewvc/llvm-project?rev=261586&view=rev
Log:
[AArch64] Fix bug in prolog clobbering live reg when shrink wrapping.
This adapts r261349 to the release branch.
Modified:
llvm/branches/release_38/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/branches/release_38/lib/Target/AArch64/AArch64FrameLowering.h
llvm/branches/release_38/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
llvm/branches/release_38/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
Modified: llvm/branches/release_38/lib/Target/AArch64/AArch64FrameLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AArch64/AArch64FrameLowering.cpp?rev=261586&r1=261585&r2=261586&view=diff
==
--- llvm/branches/release_38/lib/Target/AArch64/AArch64FrameLowering.cpp
(original)
+++ llvm/branches/release_38/lib/Target/AArch64/AArch64FrameLowering.cpp Mon
Feb 22 16:27:47 2016
@@ -275,6 +275,18 @@ static bool isCSSave(MachineInstr *MBBI)
MBBI->getOpcode() == AArch64::STPDpre;
}
+bool AArch64FrameLowering::canUseAsPrologue(
+const MachineBasicBlock &MBB) const {
+ const MachineFunction *MF = MBB.getParent();
+ const AArch64Subtarget &Subtarget = MF->getSubtarget();
+ const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
+
+ // Don't need a scratch register if we're not going to re-align the stack.
+ // Otherwise, we may need a scratch register to be available and we do not
+ // support that for now.
+ return !RegInfo->needsStackRealignment(*MF);
+}
+
void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = MBB.begin();
Modified: llvm/branches/release_38/lib/Target/AArch64/AArch64FrameLowering.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AArch64/AArch64FrameLowering.h?rev=261586&r1=261585&r2=261586&view=diff
==
--- llvm/branches/release_38/lib/Target/AArch64/AArch64FrameLowering.h
(original)
+++ llvm/branches/release_38/lib/Target/AArch64/AArch64FrameLowering.h Mon Feb
22 16:27:47 2016
@@ -37,6 +37,8 @@ public:
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const
override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
override;
+ bool canUseAsPrologue(const MachineBasicBlock &MBB) const override;
+
int getFrameIndexReference(const MachineFunction &MF, int FI,
unsigned &FrameReg) const override;
int resolveFrameIndexReference(const MachineFunction &MF, int FI,
Modified:
llvm/branches/release_38/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll?rev=261586&r1=261585&r2=261586&view=diff
==
---
llvm/branches/release_38/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
(original)
+++
llvm/branches/release_38/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
Mon Feb 22 16:27:47 2016
@@ -522,10 +522,10 @@ bb1:
; CHECK-LABEL: realign_conditional2
; Extra realignment in the prologue (performance issue).
-; CHECK: tbz {{.*}} .[[LABEL:.*]]
; CHECK: sub x9, sp, #32// =32
; CHECK: and sp, x9, #0xffe0
; CHECK: mov x19, sp
+; CHECK: tbz {{.*}} .[[LABEL:.*]]
; Stack is realigned in a non-entry BB.
; CHECK: sub [[REG:x[01-9]+]], sp, #64
; CHECK: and sp, [[REG]], #0xffe0
Modified: llvm/branches/release_38/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/AArch64/arm64-shrink-wrapping.ll?rev=261586&r1=261585&r2=261586&view=diff
==
--- llvm/branches/release_38/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
(original)
+++ llvm/branches/release_38/test/CodeGen/AArch64/arm64-shrink-wrapping.ll Mon
Feb 22 16:27:47 2016
@@ -630,3 +630,88 @@ loop2b:
end:
ret void
}
+
+; Don't do shrink-wrapping when we need to re-align the stack pointer.
+; See bug 26642.
+; CHECK-LABEL: stack_realign:
+; CHECK-NOT: lsl w[[LSL1:[0-9]+]], w0, w1
+; CHECK-NOT: lsl w[[LSL2:[0-9]+]], w1, w0
+; CHECK: stp x29, x30, [sp, #-16]!
+; CHECK: mov x29, sp
+; CHECK: sub x{{[0-9]+}}, sp, #16
+; CHECK-DAG: lsl w[[LSL1:[0-9]+]], w0, w1
+; CHECK-DAG: lsl w[[LSL2:[0-9]+]], w1, w0
+; CHECK-DAG: str w[[LSL1]],
+; CHECK-DAG: str w[[LSL2]],
+
+define i32 @stack_realign(i32 %a, i32 %b, i32* %ptr1, i32* %ptr2) {
+ %tmp = alloca i32, align 32
+ %shl1 = shl i32 %a, %b
+ %shl2 = shl i32 %b, %a
+ %tmp2 = icmp slt i32 %a, %b
+ br i1 %tmp2, l
[llvm-branch-commits] [llvm] 905623b - [NFC][LICM] Minor improvements to debug output
Author: Quentin Colombet
Date: 2021-01-11T18:02:49-08:00
New Revision: 905623b64df0c865d4dddc4a60aff9751fbaa0e0
URL:
https://github.com/llvm/llvm-project/commit/905623b64df0c865d4dddc4a60aff9751fbaa0e0
DIFF:
https://github.com/llvm/llvm-project/commit/905623b64df0c865d4dddc4a60aff9751fbaa0e0.diff
LOG: [NFC][LICM] Minor improvements to debug output
Added a utility function in Value class to print block name and use
block labels for unnamed blocks.
Changed LICM to call this function in its debug output.
Patch by Xiaoqing Wu
Differential Revision: https://reviews.llvm.org/D93577
Added:
Modified:
llvm/include/llvm/IR/Value.h
llvm/lib/IR/Value.cpp
llvm/lib/Transforms/Scalar/LICM.cpp
Removed:
diff --git a/llvm/include/llvm/IR/Value.h b/llvm/include/llvm/IR/Value.h
index 4f0336b44d28..e84840a30e96 100644
--- a/llvm/include/llvm/IR/Value.h
+++ b/llvm/include/llvm/IR/Value.h
@@ -281,6 +281,10 @@ class Value {
/// \note It is an error to call V->takeName(V).
void takeName(Value *V);
+#ifndef NDEBUG
+ std::string getNameOrAsOperand() const;
+#endif
+
/// Change all uses of this to point to a new Value.
///
/// Go through the uses list for this definition and make each use point to
diff --git a/llvm/lib/IR/Value.cpp b/llvm/lib/IR/Value.cpp
index 51a84b6af241..572f37a32410 100644
--- a/llvm/lib/IR/Value.cpp
+++ b/llvm/lib/IR/Value.cpp
@@ -430,6 +430,18 @@ void Value::takeName(Value *V) {
ST->reinsertValue(this);
}
+#ifndef NDEBUG
+std::string Value::getNameOrAsOperand() const {
+ if (!getName().empty())
+return std::string(getName());
+
+ std::string BBName;
+ raw_string_ostream OS(BBName);
+ printAsOperand(OS, false);
+ return OS.str();
+}
+#endif
+
void Value::assertModuleIsMaterializedImpl() const {
#ifndef NDEBUG
const GlobalValue *GV = dyn_cast(this);
diff --git a/llvm/lib/Transforms/Scalar/LICM.cpp
b/llvm/lib/Transforms/Scalar/LICM.cpp
index c26d588d9d45..d2b4ba296f41 100644
--- a/llvm/lib/Transforms/Scalar/LICM.cpp
+++ b/llvm/lib/Transforms/Scalar/LICM.cpp
@@ -221,6 +221,9 @@ struct LegacyLICMPass : public LoopPass {
if (skipLoop(L))
return false;
+LLVM_DEBUG(dbgs() << "Perform LICM on Loop with header at block "
+ << L->getHeader()->getNameOrAsOperand() << "\n");
+
auto *SE = getAnalysisIfAvailable();
MemorySSA *MSSA = EnableMSSALoopDependency
? (&getAnalysis().getMSSA())
@@ -697,9 +700,10 @@ class ControlFlowHoister {
// If not involved in a pending branch, hoist to preheader
BasicBlock *InitialPreheader = CurLoop->getLoopPreheader();
if (It == HoistableBranches.end()) {
- LLVM_DEBUG(dbgs() << "LICM using " << InitialPreheader->getName()
-<< " as hoist destination for " << BB->getName()
-<< "\n");
+ LLVM_DEBUG(dbgs() << "LICM using "
+<< InitialPreheader->getNameOrAsOperand()
+<< " as hoist destination for "
+<< BB->getNameOrAsOperand() << "\n");
HoistDestinationMap[BB] = InitialPreheader;
return InitialPreheader;
}
@@ -978,7 +982,7 @@ bool llvm::hoistRegion(DomTreeNode *N, AAResults *AA,
LoopInfo *LI,
HoistPoint = Dominator->getTerminator();
}
LLVM_DEBUG(dbgs() << "LICM rehoisting to "
- << HoistPoint->getParent()->getName()
+ << HoistPoint->getParent()->getNameOrAsOperand()
<< ": " << *I << "\n");
moveInstructionBefore(*I, *HoistPoint, *SafetyInfo, MSSAU, SE);
HoistPoint = I;
@@ -1737,8 +1741,8 @@ static void hoist(Instruction &I, const DominatorTree
*DT, const Loop *CurLoop,
BasicBlock *Dest, ICFLoopSafetyInfo *SafetyInfo,
MemorySSAUpdater *MSSAU, ScalarEvolution *SE,
OptimizationRemarkEmitter *ORE) {
- LLVM_DEBUG(dbgs() << "LICM hoisting to " << Dest->getName() << ": " << I
-<< "\n");
+ LLVM_DEBUG(dbgs() << "LICM hoisting to " << Dest->getNameOrAsOperand() << ":
"
+<< I << "\n");
ORE->emit([&]() {
return OptimizationRemark(DEBUG_TYPE, "Hoisted", &I) << "hoisting "
<< ore::NV("Inst",
&I);
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[llvm-branch-commits] [llvm] [Coalescer] Consider NewMI's subreg index when updating lanemask. (PR #121780)
https://github.com/qcolombet edited https://github.com/llvm/llvm-project/pull/121780 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [Coalescer] Consider NewMI's subreg index when updating lanemask. (PR #121780)
@@ -1508,14 +1508,14 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP, //undef %2.subreg:reg = INST %1:reg ; DefMI (rematerializable), // ; DefSubIdx = subreg //%3:reg = COPY %2 ; SrcIdx = DstIdx = 0 -// = SOMEINSTR %3:reg +// = SOMEINSTR %3:reg, %2 qcolombet wrote: Is this part of the change intended? https://github.com/llvm/llvm-project/pull/121780 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [Coalescer] Consider NewMI's subreg index when updating lanemask. (PR #121780)
https://github.com/qcolombet approved this pull request. Looks good. https://github.com/llvm/llvm-project/pull/121780 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Use default shouldRewriteCopySrc (PR #125535)
https://github.com/qcolombet approved this pull request. https://github.com/llvm/llvm-project/pull/125535 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] PeepholeOpt: Fix looking for def of current copy to coalesce (PR #125533)
@@ -1002,17 +1003,15 @@ bool PeepholeOptimizer::optimizeCondBranch(MachineInstr
&MI) {
/// share the same register file as \p Reg and \p SubReg. The client should
/// then be capable to rewrite all intermediate PHIs to get the next source.
/// \return False if no alternative sources are available. True otherwise.
-bool PeepholeOptimizer::findNextSource(RegSubRegPair RegSubReg,
qcolombet wrote:
Could you update the comment with the documentation for the additional
parameters.
https://github.com/llvm/llvm-project/pull/125533
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[llvm-branch-commits] [llvm] PeepholeOpt: Fix looking for def of current copy to coalesce (PR #125533)
https://github.com/qcolombet approved this pull request. Let's roll with it then! https://github.com/llvm/llvm-project/pull/125533 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] RegAlloc: Do not fatal error if there are no registers in the alloc order (PR #119640)
@@ -192,3 +177,50 @@ void RegAllocBase::enqueue(const LiveInterval *LI) {
<< " in skipped register class\n");
}
}
+
+MCPhysReg RegAllocBase::getErrorAssignment(const TargetRegisterClass &RC,
+ const MachineInstr *CtxMI) {
+ MachineFunction &MF = VRM->getMachineFunction();
+
+ // Avoid printing the error for every single instance of the register. It
+ // would be better if this were per register class.
+ bool EmitError = !MF.getProperties().hasProperty(
+ MachineFunctionProperties::Property::FailedRegAlloc);
+ if (EmitError)
+
MF.getProperties().set(MachineFunctionProperties::Property::FailedRegAlloc);
+
+ const Function &Fn = MF.getFunction();
+ LLVMContext &Context = Fn.getContext();
+
+ ArrayRef AllocOrder = RegClassInfo.getOrder(&RC);
+ if (AllocOrder.empty()) {
+// If the allocation order is empty, it likely means all registers in the
+// class are reserved. We still to need to pick something, so look at the
+// underlying class.
+ArrayRef RawRegs = RC.getRegisters();
+
+if (EmitError) {
+ DiagnosticInfoRegAllocFailure DI(
+ "no registers from class available to allocate", Fn,
+ CtxMI ? CtxMI->getDebugLoc() : DiagnosticLocation());
+ Context.diagnose(DI);
+}
+
+assert(!RawRegs.empty() && "register classes cannot have no registers");
+return RawRegs.front();
+ }
+
+ if (EmitError) {
qcolombet wrote:
If we emit only the first error, is there a point in even trying to continue to
compile?
I guess I am asking what is the use cases we are trying to enable with this
patch Series.
https://github.com/llvm/llvm-project/pull/119640
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[llvm-branch-commits] [llvm] RegAlloc: Do not fatal error if there are no registers in the alloc order (PR #119640)
https://github.com/qcolombet approved this pull request. https://github.com/llvm/llvm-project/pull/119640 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] RegAlloc: Fix failure on undef use when all registers are reserved (PR #119647)
https://github.com/qcolombet approved this pull request. https://github.com/llvm/llvm-project/pull/119647 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] PeepholeOpt: Stop allocating tiny helper classes (PR #123936)
https://github.com/qcolombet approved this pull request. I only skimmed through the changes but they make sense. Do you see any compile time improvements over these? Otherwise LGTM. (The PR/commit could have the NFC tag, right?) https://github.com/llvm/llvm-project/pull/123936 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] PeepholeOpt: Remove check for subreg index on a def operand (PR #123943)
https://github.com/qcolombet approved this pull request. Nice catch! https://github.com/llvm/llvm-project/pull/123943 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] PeepholeOpt: Simplify tracking of current op for copy and reg_sequence (PR #124224)
https://github.com/qcolombet approved this pull request. https://github.com/llvm/llvm-project/pull/124224 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] RegAllocGreedy: Fix subrange based instruction split logic (PR #120199)
@@ -1387,18 +1357,34 @@ static bool readsLaneSubset(const MachineRegisterInfo
&MRI,
DestSrc->Destination->getSubReg() == DestSrc->Source->getSubReg())
return false;
+ Register Reg = VirtReg.reg();
+
// FIXME: We're only considering uses, but should be consider defs too?
- LaneBitmask ReadMask = getInstReadLaneMask(MRI, *TRI, *MI, VirtReg.reg());
+ LaneBitmask UseMask;
+ SmallVector, 8> Ops;
+ (void)AnalyzeVirtRegInBundle(const_cast(*MI), Reg, &Ops);
- LaneBitmask LiveAtMask;
- for (const LiveInterval::SubRange &S : VirtReg.subranges()) {
-if (S.liveAt(Use))
- LiveAtMask |= S.LaneMask;
+ for (auto [MI, OpIdx] : Ops) {
+const MachineOperand &MO = MI->getOperand(OpIdx);
+assert(MO.isReg() && MO.getReg() == Reg);
+unsigned SubReg = MO.getSubReg();
+if (SubReg == 0 && MO.isUse()) {
+ if (MO.isUndef())
+continue;
+ return false;
qcolombet wrote:
Ah that makes sense. Thanks for updating the comment of the function.
https://github.com/llvm/llvm-project/pull/120199
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[llvm-branch-commits] [llvm] RegAllocGreedy: Fix subrange based instruction split logic (PR #120199)
https://github.com/qcolombet approved this pull request. https://github.com/llvm/llvm-project/pull/120199 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] PeepholeOpt: Allow introducing subregister uses on reg_sequence (PR #127052)
https://github.com/qcolombet approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/127052 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] CodeGen: Trim redundant template argument from defusechain_iterator (PR #135024)
https://github.com/qcolombet approved this pull request. https://github.com/llvm/llvm-project/pull/135024 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][memref][NFC] Simplify `constifyIndexValues` (PR #135940)
https://github.com/qcolombet approved this pull request. https://github.com/llvm/llvm-project/pull/135940 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][memref][NFC] Simplify `constifyIndexValues` (PR #135940)
@@ -88,101 +88,30 @@ SmallVector memref::getMixedSizes(OpBuilder
&builder,
// Utility functions for propagating static information
//===--===//
-/// Helper function that infers the constant values from a list of \p values,
-/// a \p memRefTy, and another helper function \p getAttributes.
-/// The inferred constant values replace the related `OpFoldResult` in
-/// \p values.
+/// Helper function that sets values[i] to constValues[i] if the latter is a
+/// static value, as indicated by ShapedType::kDynamic.
///
-/// \note This function shouldn't be used directly, instead, use the
-/// `getConstifiedMixedXXX` methods from the related operations.
-///
-/// \p getAttributes retuns a list of potentially constant values, as
determined
-/// by \p isDynamic, from the given \p memRefTy. The returned list must have as
-/// many elements as \p values or be empty.
-///
-/// E.g., consider the following example:
-/// ```
-/// memref.reinterpret_cast %base to <...> strides: [2, %dyn_stride] :
-/// memref to memref>
-/// ```
-/// `ReinterpretCastOp::getMixedStrides()` will return `[2, %dyn_stride]`.
-/// Now using this helper function with:
-/// - `values == [2, %dyn_stride]`,
-/// - `memRefTy == memref>`
-/// - `getAttributes == getConstantStrides` (i.e., a wrapper around
-/// `getStridesAndOffset`), and
-/// - `isDynamic == ShapedType::isDynamic`
-/// Will yield: `values == [2, 1]`
-static void constifyIndexValues(
-SmallVectorImpl &values, MemRefType memRefTy,
-MLIRContext *ctxt,
-llvm::function_ref(MemRefType)> getAttributes,
-llvm::function_ref isDynamic) {
- SmallVector constValues = getAttributes(memRefTy);
- Builder builder(ctxt);
- for (const auto &it : llvm::enumerate(constValues)) {
-int64_t constValue = it.value();
-if (!isDynamic(constValue))
- values[it.index()] = builder.getIndexAttr(constValue);
- }
- for (OpFoldResult &ofr : values) {
-if (auto attr = dyn_cast(ofr)) {
- // FIXME: We shouldn't need to do that, but right now, the static indices
- // are created with the wrong type: `i64` instead of `index`.
- // As a result, if we were to keep the attribute as is, we may fail to
see
- // that two attributes are equal because one would have the i64 type and
- // the other the index type.
- // The alternative would be to create constant indices with getI64Attr in
- // this and the previous loop, but it doesn't logically make sense (we
are
- // dealing with indices here) and would only strenghten the inconsistency
- // around how static indices are created (some places use getI64Attr,
- // others use getIndexAttr).
- // The workaround here is to stick to the IndexAttr type for all the
- // values, hence we recreate the attribute even when it is already static
- // to make sure the type is consistent.
- ofr = builder.getIndexAttr(llvm::cast(attr).getInt());
+/// If constValues[i] is dynamic, tries to extract a constant value from
+/// value[i] to allow for additional folding opportunities. Also convertes all
+/// existing attributes to index attributes. (They may be i64 attributes.)
+static void constifyIndexValues(SmallVectorImpl &values,
+ArrayRef constValues) {
+ assert(constValues.size() == values.size() &&
+ "incorrect number of const values");
+ for (int64_t i = 0, e = constValues.size(); i < e; ++i) {
qcolombet wrote:
Could we use `enumerate` here?
https://github.com/llvm/llvm-project/pull/135940
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[llvm-branch-commits] [llvm] PeepholeOpt: Remove subreg def check for bitcast (PR #130086)
https://github.com/qcolombet approved this pull request. https://github.com/llvm/llvm-project/pull/130086 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] PeepholeOpt: Remove subreg def check for insert_subreg (PR #130085)
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[llvm-branch-commits] [llvm] PeepholeOpt: Handle subregister compose when looking through reg_sequence (PR #127051)
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[llvm-branch-commits] [llvm] RegAlloc: Use new approach to handling failed allocations (PR #128469)
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[llvm-branch-commits] [llvm] Reapply "RegAlloc: Fix verifier error after failed allocation (#119690)" (PR #128400)
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