Author: qcolombet
Date: Thu Aug 13 17:52:11 2015
New Revision: 244976
URL: http://llvm.org/viewvc/llvm-project?rev=244976&view=rev
Log:
[release_37] Revert r242173 since it breaks R9 290X.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91588
Modified:
llvm/branches/release_37/include/llvm/CodeGen/LiveRegMatrix.h
llvm/branches/release_37/include/llvm/CodeGen/MachineRegisterInfo.h
llvm/branches/release_37/lib/CodeGen/ExecutionDepsFix.cpp
llvm/branches/release_37/lib/CodeGen/LiveRegMatrix.cpp
llvm/branches/release_37/lib/CodeGen/MachineRegisterInfo.cpp
llvm/branches/release_37/lib/CodeGen/PrologEpilogInserter.cpp
llvm/branches/release_37/lib/CodeGen/RegAllocFast.cpp
llvm/branches/release_37/lib/CodeGen/VirtRegMap.cpp
llvm/branches/release_37/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
llvm/branches/release_37/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/branches/release_37/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
llvm/branches/release_37/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp
llvm/branches/release_37/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/branches/release_37/lib/Target/Hexagon/HexagonFrameLowering.cpp
llvm/branches/release_37/lib/Target/PowerPC/PPCFrameLowering.cpp
llvm/branches/release_37/lib/Target/Sparc/SparcFrameLowering.cpp
llvm/branches/release_37/lib/Target/X86/X86FloatingPoint.cpp
llvm/branches/release_37/lib/Target/X86/X86FrameLowering.cpp
Modified: llvm/branches/release_37/include/llvm/CodeGen/LiveRegMatrix.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/include/llvm/CodeGen/LiveRegMatrix.h?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/include/llvm/CodeGen/LiveRegMatrix.h (original)
+++ llvm/branches/release_37/include/llvm/CodeGen/LiveRegMatrix.h Thu Aug 13
17:52:11 2015
@@ -32,11 +32,13 @@ namespace llvm {
class LiveInterval;
class LiveIntervalAnalysis;
+class MachineRegisterInfo;
class TargetRegisterInfo;
class VirtRegMap;
class LiveRegMatrix : public MachineFunctionPass {
const TargetRegisterInfo *TRI;
+ MachineRegisterInfo *MRI;
LiveIntervals *LIS;
VirtRegMap *VRM;
Modified: llvm/branches/release_37/include/llvm/CodeGen/MachineRegisterInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/include/llvm/CodeGen/MachineRegisterInfo.h?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/include/llvm/CodeGen/MachineRegisterInfo.h
(original)
+++ llvm/branches/release_37/include/llvm/CodeGen/MachineRegisterInfo.h Thu Aug
13 17:52:11 2015
@@ -95,8 +95,20 @@ private:
return MO->Contents.Reg.Next;
}
+ /// UsedRegUnits - This is a bit vector that is computed and set by the
+ /// register allocator, and must be kept up to date by passes that run after
+ /// register allocation (though most don't modify this). This is used
+ /// so that the code generator knows which callee save registers to save and
+ /// for other target specific uses.
+ /// This vector has bits set for register units that are modified in the
+ /// current function. It doesn't include registers clobbered by function
+ /// calls with register mask operands.
+ BitVector UsedRegUnits;
+
/// UsedPhysRegMask - Additional used physregs including aliases.
/// This bit vector represents all the registers clobbered by function calls.
+ /// It can model things that UsedRegUnits can't, such as function calls that
+ /// clobber ymm7 but preserve the low half in xmm7.
BitVector UsedPhysRegMask;
/// ReservedRegs - This is a bit vector of reserved registers. The target
@@ -641,12 +653,55 @@ public:
/// ignored.
bool isPhysRegModified(unsigned PhysReg) const;
+
//===--------------------------------------------------------------------===//
+ // Physical Register Use Info
+
//===--------------------------------------------------------------------===//
+
+ /// isPhysRegUsed - Return true if the specified register is used in this
+ /// function. Also check for clobbered aliases and registers clobbered by
+ /// function calls with register mask operands.
+ ///
+ /// This only works after register allocation.
+ bool isPhysRegUsed(unsigned Reg) const {
+ if (UsedPhysRegMask.test(Reg))
+ return true;
+ for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
+ Units.isValid(); ++Units)
+ if (UsedRegUnits.test(*Units))
+ return true;
+ return false;
+ }
+
+ /// Mark the specified register unit as used in this function.
+ /// This should only be called during and after register allocation.
+ void setRegUnitUsed(unsigned RegUnit) {
+ UsedRegUnits.set(RegUnit);
+ }
+
+ /// setPhysRegUsed - Mark the specified register used in this function.
+ /// This should only be called during and after register allocation.
+ void setPhysRegUsed(unsigned Reg) {
+ for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
+ Units.isValid(); ++Units)
+ UsedRegUnits.set(*Units);
+ }
+
/// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
/// This corresponds to the bit mask attached to register mask operands.
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
UsedPhysRegMask.setBitsNotInMask(RegMask);
}
+ /// setPhysRegUnused - Mark the specified register unused in this function.
+ /// This should only be called during and after register allocation.
+ void setPhysRegUnused(unsigned Reg) {
+ UsedPhysRegMask.reset(Reg);
+ for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
+ Units.isValid(); ++Units)
+ UsedRegUnits.reset(*Units);
+ }
+
+
//===--------------------------------------------------------------------===//
// Reserved Register Info
//===--------------------------------------------------------------------===//
Modified: llvm/branches/release_37/lib/CodeGen/ExecutionDepsFix.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/CodeGen/ExecutionDepsFix.cpp?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/lib/CodeGen/ExecutionDepsFix.cpp (original)
+++ llvm/branches/release_37/lib/CodeGen/ExecutionDepsFix.cpp Thu Aug 13
17:52:11 2015
@@ -733,14 +733,12 @@ bool ExeDepsFix::runOnMachineFunction(Ma
// If no relevant registers are used in the function, we can skip it
// completely.
bool anyregs = false;
- const MachineRegisterInfo &MRI = mf.getRegInfo();
for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end();
- I != E && !anyregs; ++I)
- for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
- if (!MRI.reg_nodbg_empty(*AI)) {
- anyregs = true;
- break;
- }
+ I != E; ++I)
+ if (MF->getRegInfo().isPhysRegUsed(*I)) {
+ anyregs = true;
+ break;
+ }
if (!anyregs) return false;
// Initialize the AliasMap on the first use.
Modified: llvm/branches/release_37/lib/CodeGen/LiveRegMatrix.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/CodeGen/LiveRegMatrix.cpp?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/lib/CodeGen/LiveRegMatrix.cpp (original)
+++ llvm/branches/release_37/lib/CodeGen/LiveRegMatrix.cpp Thu Aug 13 17:52:11
2015
@@ -15,12 +15,12 @@
#include "RegisterCoalescer.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
using namespace llvm;
@@ -49,6 +49,7 @@ void LiveRegMatrix::getAnalysisUsage(Ana
bool LiveRegMatrix::runOnMachineFunction(MachineFunction &MF) {
TRI = MF.getSubtarget().getRegisterInfo();
+ MRI = &MF.getRegInfo();
LIS = &getAnalysis<LiveIntervals>();
VRM = &getAnalysis<VirtRegMap>();
@@ -100,6 +101,7 @@ void LiveRegMatrix::assign(LiveInterval
<< " to " << PrintReg(PhysReg, TRI) << ':');
assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
+ MRI->setPhysRegUsed(PhysReg);
foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
const LiveRange &Range) {
Modified: llvm/branches/release_37/lib/CodeGen/MachineRegisterInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/CodeGen/MachineRegisterInfo.cpp?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/lib/CodeGen/MachineRegisterInfo.cpp (original)
+++ llvm/branches/release_37/lib/CodeGen/MachineRegisterInfo.cpp Thu Aug 13
17:52:11 2015
@@ -29,6 +29,7 @@ MachineRegisterInfo::MachineRegisterInfo
TracksSubRegLiveness(false) {
VRegInfo.reserve(256);
RegAllocHints.reserve(256);
+ UsedRegUnits.resize(getTargetRegisterInfo()->getNumRegUnits());
UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs());
// Create the physreg use/def lists.
Modified: llvm/branches/release_37/lib/CodeGen/PrologEpilogInserter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/CodeGen/PrologEpilogInserter.cpp?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/branches/release_37/lib/CodeGen/PrologEpilogInserter.cpp Thu Aug 13
17:52:11 2015
@@ -1026,8 +1026,12 @@ PEI::scavengeFrameVirtualRegs(MachineFun
// Replace this reference to the virtual register with the
// scratch register.
assert (ScratchReg && "Missing scratch register!");
+ MachineRegisterInfo &MRI = Fn.getRegInfo();
Fn.getRegInfo().replaceRegWith(Reg, ScratchReg);
+ // Make sure MRI now accounts this register as used.
+ MRI.setPhysRegUsed(ScratchReg);
+
// Because this instruction was processed by the RS before this
// register was allocated, make sure that the RS now records the
// register as being used.
Modified: llvm/branches/release_37/lib/CodeGen/RegAllocFast.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/CodeGen/RegAllocFast.cpp?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/lib/CodeGen/RegAllocFast.cpp (original)
+++ llvm/branches/release_37/lib/CodeGen/RegAllocFast.cpp Thu Aug 13 17:52:11
2015
@@ -986,6 +986,10 @@ void RAFast::AllocateBasicBlock() {
}
}
+ for (UsedInInstrSet::iterator
+ I = UsedInInstr.begin(), E = UsedInInstr.end(); I != E; ++I)
+ MRI->setRegUnitUsed(*I);
+
// Track registers defined by instruction - early clobbers and tied uses at
// this point.
UsedInInstr.clear();
@@ -1046,6 +1050,10 @@ void RAFast::AllocateBasicBlock() {
killVirtReg(VirtDead[i]);
VirtDead.clear();
+ for (UsedInInstrSet::iterator
+ I = UsedInInstr.begin(), E = UsedInInstr.end(); I != E; ++I)
+ MRI->setRegUnitUsed(*I);
+
if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
DEBUG(dbgs() << "-- coalescing: " << *MI);
Coalesced.push_back(MI);
@@ -1095,6 +1103,12 @@ bool RAFast::runOnMachineFunction(Machin
AllocateBasicBlock();
}
+ // Add the clobber lists for all the instructions we skipped earlier.
+ for (const MCInstrDesc *Desc : SkippedInstrs)
+ if (const uint16_t *Defs = Desc->getImplicitDefs())
+ while (*Defs)
+ MRI->setPhysRegUsed(*Defs++);
+
// All machine operands and other references to virtual registers have been
// replaced. Remove the virtual registers.
MRI->clearVirtRegs();
Modified: llvm/branches/release_37/lib/CodeGen/VirtRegMap.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/CodeGen/VirtRegMap.cpp?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/lib/CodeGen/VirtRegMap.cpp (original)
+++ llvm/branches/release_37/lib/CodeGen/VirtRegMap.cpp Thu Aug 13 17:52:11 2015
@@ -163,6 +163,7 @@ class VirtRegRewriter : public MachineFu
SlotIndexes *Indexes;
LiveIntervals *LIS;
VirtRegMap *VRM;
+ SparseSet<unsigned> PhysRegs;
void rewrite();
void addMBBLiveIns();
@@ -318,15 +319,54 @@ void VirtRegRewriter::rewrite() {
SmallVector<unsigned, 8> SuperDeads;
SmallVector<unsigned, 8> SuperDefs;
SmallVector<unsigned, 8> SuperKills;
+ SmallPtrSet<const MachineInstr *, 4> NoReturnInsts;
+
+ // Here we have a SparseSet to hold which PhysRegs are actually encountered
+ // in the MF we are about to iterate over so that later when we call
+ // setPhysRegUsed, we are only doing it for physRegs that were actually found
+ // in the program and not for all of the possible physRegs for the given
+ // target architecture. If the target has a lot of physRegs, then for a small
+ // program there will be a significant compile time reduction here.
+ PhysRegs.clear();
+ PhysRegs.setUniverse(TRI->getNumRegs());
+
+ // The function with uwtable should guarantee that the stack unwinder
+ // can unwind the stack to the previous frame. Thus, we can't apply the
+ // noreturn optimization if the caller function has uwtable attribute.
+ bool HasUWTable = MF->getFunction()->hasFnAttribute(Attribute::UWTable);
for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
MBBI != MBBE; ++MBBI) {
DEBUG(MBBI->print(dbgs(), Indexes));
+ bool IsExitBB = MBBI->succ_empty();
for (MachineBasicBlock::instr_iterator
MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
MachineInstr *MI = MII;
++MII;
+ // Check if this instruction is a call to a noreturn function. If this
+ // is a call to noreturn function and we don't need the stack unwinding
+ // functionality (i.e. this function does not have uwtable attribute and
+ // the callee function has the nounwind attribute), then we can ignore
+ // the definitions set by this instruction.
+ if (!HasUWTable && IsExitBB && MI->isCall()) {
+ for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
+ MOE = MI->operands_end(); MOI != MOE; ++MOI) {
+ MachineOperand &MO = *MOI;
+ if (!MO.isGlobal())
+ continue;
+ const Function *Func = dyn_cast<Function>(MO.getGlobal());
+ if (!Func || !Func->hasFnAttribute(Attribute::NoReturn) ||
+ // We need to keep correct unwind information
+ // even if the function will not return, since the
+ // runtime may need it.
+ !Func->hasFnAttribute(Attribute::NoUnwind))
+ continue;
+ NoReturnInsts.insert(MI);
+ break;
+ }
+ }
+
for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
MOE = MI->operands_end(); MOI != MOE; ++MOI) {
MachineOperand &MO = *MOI;
@@ -335,6 +375,15 @@ void VirtRegRewriter::rewrite() {
if (MO.isRegMask())
MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
+ // If we encounter a VirtReg or PhysReg then get at the PhysReg and add
+ // it to the physreg bitset. Later we use only the PhysRegs that were
+ // actually encountered in the MF to populate the MRI's used physregs.
+ if (MO.isReg() && MO.getReg())
+ PhysRegs.insert(
+ TargetRegisterInfo::isVirtualRegister(MO.getReg()) ?
+ VRM->getPhys(MO.getReg()) :
+ MO.getReg());
+
if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
continue;
unsigned VirtReg = MO.getReg();
@@ -421,5 +470,29 @@ void VirtRegRewriter::rewrite() {
}
}
}
+
+ // Tell MRI about physical registers in use.
+ if (NoReturnInsts.empty()) {
+ for (SparseSet<unsigned>::iterator
+ RegI = PhysRegs.begin(), E = PhysRegs.end(); RegI != E; ++RegI)
+ if (!MRI->reg_nodbg_empty(*RegI))
+ MRI->setPhysRegUsed(*RegI);
+ } else {
+ for (SparseSet<unsigned>::iterator
+ I = PhysRegs.begin(), E = PhysRegs.end(); I != E; ++I) {
+ unsigned Reg = *I;
+ if (MRI->reg_nodbg_empty(Reg))
+ continue;
+ // Check if this register has a use that will impact the rest of the
+ // code. Uses in debug and noreturn instructions do not impact the
+ // generated code.
+ for (MachineInstr &It : MRI->reg_nodbg_instructions(Reg)) {
+ if (!NoReturnInsts.count(&It)) {
+ MRI->setPhysRegUsed(Reg);
+ break;
+ }
+ }
+ }
+ }
}
Modified:
llvm/branches/release_37/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
(original)
+++ llvm/branches/release_37/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
Thu Aug 13 17:52:11 2015
@@ -593,6 +593,7 @@ bool AArch64A57FPLoadBalancing::colorCha
if (Change) {
Substs[MO.getReg()] = Reg;
MO.setReg(Reg);
+ MRI->setPhysRegUsed(Reg);
Changed = true;
}
Modified: llvm/branches/release_37/lib/Target/AArch64/AArch64FrameLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/AArch64/AArch64FrameLowering.cpp?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/AArch64/AArch64FrameLowering.cpp
(original)
+++ llvm/branches/release_37/lib/Target/AArch64/AArch64FrameLowering.cpp Thu
Aug 13 17:52:11 2015
@@ -354,6 +354,7 @@ void AArch64FrameLowering::emitPrologue(
if (NumBytes && NeedsRealignment) {
// Use the first callee-saved register as a scratch register.
scratchSPReg = AArch64::X9;
+ MF.getRegInfo().setPhysRegUsed(scratchSPReg);
}
// If we're a leaf function, try using the red zone.
Modified: llvm/branches/release_37/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
(original)
+++ llvm/branches/release_37/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp Thu
Aug 13 17:52:11 2015
@@ -53,6 +53,7 @@ SIMachineFunctionInfo::SpilledReg SIMach
if (!LaneVGPRs.count(LaneVGPRIdx)) {
unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass);
LaneVGPRs[LaneVGPRIdx] = LaneVGPR;
+ MRI.setPhysRegUsed(LaneVGPR);
// Add this register as live-in to all blocks to avoid machine verifer
// complaining about use of an undefined physical register.
Modified: llvm/branches/release_37/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp
(original)
+++ llvm/branches/release_37/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp Thu Aug
13 17:52:11 2015
@@ -91,6 +91,7 @@ bool SIPrepareScratchRegs::runOnMachineF
if (ScratchOffsetReg != AMDGPU::NoRegister) {
// Found an SGPR to use
+ MRI.setPhysRegUsed(ScratchOffsetReg);
BuildMI(*Entry, I, DL, TII->get(AMDGPU::S_MOV_B32), ScratchOffsetReg)
.addReg(ScratchOffsetPreloadReg);
} else {
Modified: llvm/branches/release_37/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/branches/release_37/lib/Target/AMDGPU/SIRegisterInfo.cpp Thu Aug 13
17:52:11 2015
@@ -499,7 +499,7 @@ unsigned SIRegisterInfo::findUnusedRegis
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
I != E; ++I) {
- if (MRI.reg_nodbg_empty(*I))
+ if (!MRI.isPhysRegUsed(*I))
return *I;
}
return AMDGPU::NoRegister;
Modified: llvm/branches/release_37/lib/Target/Hexagon/HexagonFrameLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/Hexagon/HexagonFrameLowering.cpp?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/Hexagon/HexagonFrameLowering.cpp
(original)
+++ llvm/branches/release_37/lib/Target/Hexagon/HexagonFrameLowering.cpp Thu
Aug 13 17:52:11 2015
@@ -864,13 +864,13 @@ static bool needToReserveScavengingSpill
// Check for an unused caller-saved register.
for ( ; *CallerSavedRegs; ++CallerSavedRegs) {
MCPhysReg FreeReg = *CallerSavedRegs;
- if (!MRI.reg_nodbg_empty(FreeReg))
+ if (MRI.isPhysRegUsed(FreeReg))
continue;
// Check aliased register usage.
bool IsCurrentRegUsed = false;
for (MCRegAliasIterator AI(FreeReg, &HRI, false); AI.isValid(); ++AI)
- if (!MRI.reg_nodbg_empty(*AI)) {
+ if (MRI.isPhysRegUsed(*AI)) {
IsCurrentRegUsed = true;
break;
}
Modified: llvm/branches/release_37/lib/Target/PowerPC/PPCFrameLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/PowerPC/PPCFrameLowering.cpp (original)
+++ llvm/branches/release_37/lib/Target/PowerPC/PPCFrameLowering.cpp Thu Aug 13
17:52:11 2015
@@ -306,10 +306,9 @@ static void HandleVRSaveUpdate(MachineIn
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
DebugLoc dl = MI->getDebugLoc();
- const MachineRegisterInfo &MRI = MF->getRegInfo();
unsigned UsedRegMask = 0;
for (unsigned i = 0; i != 32; ++i)
- if (MRI.isPhysRegModified(VRRegNo[i]))
+ if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
UsedRegMask |= 1 << (31-i);
// Live in and live out values already must be in the mask, so don't bother
Modified: llvm/branches/release_37/lib/Target/Sparc/SparcFrameLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/Sparc/SparcFrameLowering.cpp?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/Sparc/SparcFrameLowering.cpp (original)
+++ llvm/branches/release_37/lib/Target/Sparc/SparcFrameLowering.cpp Thu Aug 13
17:52:11 2015
@@ -190,11 +190,11 @@ static bool LLVM_ATTRIBUTE_UNUSED verify
{
for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
- if (!MRI->reg_nodbg_empty(reg))
+ if (MRI->isPhysRegUsed(reg))
return false;
for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
- if (!MRI->reg_nodbg_empty(reg))
+ if (MRI->isPhysRegUsed(reg))
return false;
return true;
@@ -206,10 +206,10 @@ bool SparcFrameLowering::isLeafProc(Mach
MachineRegisterInfo &MRI = MF.getRegInfo();
MachineFrameInfo *MFI = MF.getFrameInfo();
- return !(MFI->hasCalls() // has calls
- || !MRI.reg_nodbg_empty(SP::L0) // Too many registers needed
- || !MRI.reg_nodbg_empty(SP::O6) // %SP is used
- || hasFP(MF)); // need %FP
+ return !(MFI->hasCalls() // has calls
+ || MRI.isPhysRegUsed(SP::L0) // Too many registers needed
+ || MRI.isPhysRegUsed(SP::O6) // %SP is used
+ || hasFP(MF)); // need %FP
}
void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
@@ -218,13 +218,16 @@ void SparcFrameLowering::remapRegsForLea
// Remap %i[0-7] to %o[0-7].
for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
- if (MRI.reg_nodbg_empty(reg))
+ if (!MRI.isPhysRegUsed(reg))
continue;
unsigned mapped_reg = (reg - SP::I0 + SP::O0);
- assert(MRI.reg_nodbg_empty(mapped_reg));
+ assert(!MRI.isPhysRegUsed(mapped_reg));
// Replace I register with O register.
MRI.replaceRegWith(reg, mapped_reg);
+
+ // Mark the reg unused.
+ MRI.setPhysRegUnused(reg);
}
// Rewrite MBB's Live-ins.
Modified: llvm/branches/release_37/lib/Target/X86/X86FloatingPoint.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/X86/X86FloatingPoint.cpp?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/X86/X86FloatingPoint.cpp (original)
+++ llvm/branches/release_37/lib/Target/X86/X86FloatingPoint.cpp Thu Aug 13
17:52:11 2015
@@ -301,9 +301,8 @@ bool FPS::runOnMachineFunction(MachineFu
bool FPIsUsed = false;
static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
- const MachineRegisterInfo &MRI = MF.getRegInfo();
for (unsigned i = 0; i <= 6; ++i)
- if (!MRI.reg_nodbg_empty(X86::FP0 + i)) {
+ if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
FPIsUsed = true;
break;
}
Modified: llvm/branches/release_37/lib/Target/X86/X86FrameLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/X86/X86FrameLowering.cpp?rev=244976&r1=244975&r2=244976&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/X86/X86FrameLowering.cpp (original)
+++ llvm/branches/release_37/lib/Target/X86/X86FrameLowering.cpp Thu Aug 13
17:52:11 2015
@@ -1682,6 +1682,8 @@ void X86FrameLowering::adjustForSegmente
.addImm(StackSize);
BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
.addImm(X86FI->getArgumentStackSize());
+ MF.getRegInfo().setPhysRegUsed(Reg10);
+ MF.getRegInfo().setPhysRegUsed(Reg11);
} else {
BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
.addImm(X86FI->getArgumentStackSize());
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