================ @@ -1508,14 +1508,14 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP, // undef %2.subreg:reg = INST %1:reg ; DefMI (rematerializable), // ; DefSubIdx = subreg // %3:reg = COPY %2 ; SrcIdx = DstIdx = 0 - // .... = SOMEINSTR %3:reg + // .... = SOMEINSTR %3:reg, %2 ---------------- qcolombet wrote:
Is this part of the change intended? https://github.com/llvm/llvm-project/pull/121780 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits