[llvm-branch-commits] [llvm-branch] r260659 - [AVR] Add release notes for 3.8

2016-02-16 Thread Dylan McKay via llvm-branch-commits 
Author: dylanmckay
Date: Fri Feb 12 00:38:02 2016
New Revision: 260659

URL: http://llvm.org/viewvc/llvm-project?rev=260659&view=rev
Log:
[AVR] Add release notes for 3.8

Modified:
llvm/branches/release_38/docs/ReleaseNotes.rst

Modified: llvm/branches/release_38/docs/ReleaseNotes.rst
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/docs/ReleaseNotes.rst?rev=260659&r1=260658&r2=260659&view=diff
==
--- llvm/branches/release_38/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_38/docs/ReleaseNotes.rst Fri Feb 12 00:38:02 2016
@@ -197,6 +197,12 @@ Changes to the X86 Target
 * Tail call support for ``thiscall``, ``stdcall`, ``vectorcall``, and
   ``fastcall`` functions.
 
+Changes to the AVR Target
+-
+
+Slightly less than half of the AVR backend has been merged in at this point. 
It is still
+missing a number large parts which cause it to be unusable, but is well on the
+road to being completely merged and workable.
 
 Changes to the OCaml bindings
 -


___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm-branch] r294803 - Add release notes for the AVR backend

2017-02-10 Thread Dylan McKay via llvm-branch-commits 
Author: dylanmckay
Date: Fri Feb 10 17:13:12 2017
New Revision: 294803

URL: http://llvm.org/viewvc/llvm-project?rev=294803&view=rev
Log:
Add release notes for the AVR backend

Modified:
llvm/branches/release_40/docs/ReleaseNotes.rst

Modified: llvm/branches/release_40/docs/ReleaseNotes.rst
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/docs/ReleaseNotes.rst?rev=294803&r1=294802&r2=294803&view=diff
==
--- llvm/branches/release_40/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_40/docs/ReleaseNotes.rst Fri Feb 10 17:13:12 2017
@@ -228,9 +228,23 @@ Changes to the AMDGPU Target
 Changes to the AVR Target
 -
 
-* The entire backend has been merged in-tree with all tests passing. All of
-  the instruction selection code and the machine code backend has landed
-  recently and is fully usable.
+This marks the first release where the AVR backend has been completely merged
+from a fork into LLVM trunk. The backend is still marked experimental, but
+is generally quite usable. All downstream development has halted on
+`GitHub `_, and changes now go directly into
+LLVM trunk.
+
+* Instruction selector and pseudo instruction expansion pass landed
+* `read_register` and `write_register` intrinsics are now supported
+* Support stack stores greater than 63-bytes from the bottom of the stack
+* A number of assertion errors have been fixed
+* Support stores to `undef` locations
+* Very basic support for the target has been added to clang
+* Small optimizations to some 16-bit boolean expressions
+
+Most of the work behind the scenes has been on correctness of generated
+assembly, and also fixing some assertions we would hit on some well-formed
+inputs.
 
 Changes to the OCaml bindings
 -


___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm-branch] r309513 - [AVR] Add release notes for 5.0

2017-07-30 Thread Dylan McKay via llvm-branch-commits 
Author: dylanmckay
Date: Sun Jul 30 08:14:22 2017
New Revision: 309513

URL: http://llvm.org/viewvc/llvm-project?rev=309513&view=rev
Log:
[AVR] Add release notes for 5.0

Modified:
llvm/branches/release_50/docs/ReleaseNotes.rst

Modified: llvm/branches/release_50/docs/ReleaseNotes.rst
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/docs/ReleaseNotes.rst?rev=309513&r1=309512&r2=309513&view=diff
==
--- llvm/branches/release_50/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_50/docs/ReleaseNotes.rst Sun Jul 30 08:14:22 2017
@@ -125,7 +125,22 @@ Changes to the AMDGPU Target
 Changes to the AVR Target
 -
 
- During this release ...
+This release consists mainly of bugfixes and implementations of features
+required for compiling basic Rust programs.
+
+* Enable the branch relaxation pass so that we don't crash on large
+  stack load/stores
+
+* Add support for lowering bit-rotations to the native `ror` and `rol`
+  instructions
+
+* Fix bug where function pointers were treated as pointers to RAM and not
+  pointers to program memory
+
+* Fix broken code generaton for shift-by-variable expressions
+
+* Support zero-sized types in argument lists; this is impossible in C,
+  but possible in Rust
 
 Changes to the OCaml bindings
 -


___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm-branch] r314356 - Merging r312905:

2017-09-27 Thread Dylan McKay via llvm-branch-commits 
Author: dylanmckay
Date: Wed Sep 27 15:15:50 2017
New Revision: 314356

URL: http://llvm.org/viewvc/llvm-project?rev=314356&view=rev
Log:
Merging r312905:

r312905 | dylanmckay | 2017-09-11 22:32:51 +1200 (Mon, 11 Sep 2017) | 10 lines

[AVR] Enable the '__do_copy_data' function

Also enables '__do_clear_bss'.

These functions are automaticalled called by the CRT if they are
declared.

We need these to be called otherwise RAM will start completely
uninitialised, even though we need to copy RAM variables from progmem to
RAM.


Added:
llvm/branches/release_50/test/CodeGen/AVR/clear-bss.ll
llvm/branches/release_50/test/CodeGen/AVR/copy-data-to-ram.ll
Modified:
llvm/branches/release_50/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.cpp
llvm/branches/release_50/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.h

Modified: 
llvm/branches/release_50/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.cpp?rev=314356&r1=314355&r2=314356&view=diff
==
--- llvm/branches/release_50/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.cpp 
(original)
+++ llvm/branches/release_50/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.cpp 
Wed Sep 27 15:15:50 2017
@@ -13,6 +13,8 @@
 
 #include "AVRTargetStreamer.h"
 
+#include "llvm/MC/MCContext.h"
+
 namespace llvm {
 
 AVRTargetStreamer::AVRTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
@@ -20,5 +22,23 @@ AVRTargetStreamer::AVRTargetStreamer(MCS
 AVRTargetAsmStreamer::AVRTargetAsmStreamer(MCStreamer &S)
 : AVRTargetStreamer(S) {}
 
+void AVRTargetStreamer::finish() {
+  MCStreamer &OS = getStreamer();
+  MCContext &Context = OS.getContext();
+
+  MCSymbol *DoCopyData = Context.getOrCreateSymbol("__do_copy_data");
+  MCSymbol *DoClearBss = Context.getOrCreateSymbol("__do_clear_bss");
+
+  // FIXME: We can disable __do_copy_data if there are no static RAM variables.
+
+  OS.emitRawComment(" Declaring this symbol tells the CRT that it should");
+  OS.emitRawComment("copy all variables from program memory to RAM on 
startup");
+  OS.EmitSymbolAttribute(DoCopyData, MCSA_Global);
+
+  OS.emitRawComment(" Declaring this symbol tells the CRT that it should");
+  OS.emitRawComment("clear the zeroed data section on startup");
+  OS.EmitSymbolAttribute(DoClearBss, MCSA_Global);
+}
+
 } // end namespace llvm
 

Modified: 
llvm/branches/release_50/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.h
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.h?rev=314356&r1=314355&r2=314356&view=diff
==
--- llvm/branches/release_50/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.h 
(original)
+++ llvm/branches/release_50/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.h 
Wed Sep 27 15:15:50 2017
@@ -19,6 +19,8 @@ class MCStreamer;
 class AVRTargetStreamer : public MCTargetStreamer {
 public:
   explicit AVRTargetStreamer(MCStreamer &S);
+
+  void finish() override;
 };
 
 /// A target streamer for textual AVR assembly code.

Added: llvm/branches/release_50/test/CodeGen/AVR/clear-bss.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/test/CodeGen/AVR/clear-bss.ll?rev=314356&view=auto
==
--- llvm/branches/release_50/test/CodeGen/AVR/clear-bss.ll (added)
+++ llvm/branches/release_50/test/CodeGen/AVR/clear-bss.ll Wed Sep 27 15:15:50 
2017
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=avr | FileCheck %s
+
+; CHECK: .globl __do_clear_bss
+@zeroed = internal constant [3 x i8] zeroinitializer
+

Added: llvm/branches/release_50/test/CodeGen/AVR/copy-data-to-ram.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/test/CodeGen/AVR/copy-data-to-ram.ll?rev=314356&view=auto
==
--- llvm/branches/release_50/test/CodeGen/AVR/copy-data-to-ram.ll (added)
+++ llvm/branches/release_50/test/CodeGen/AVR/copy-data-to-ram.ll Wed Sep 27 
15:15:50 2017
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=avr | FileCheck %s
+
+; CHECK: .globl __do_copy_data
+@str = internal global [3 x i8] c"foo"
+


___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm-branch] r314357 - Merging r314070:

2017-09-27 Thread Dylan McKay via llvm-branch-commits 
Author: dylanmckay
Date: Wed Sep 27 15:17:11 2017
New Revision: 314357

URL: http://llvm.org/viewvc/llvm-project?rev=314357&view=rev
Log:
Merging r314070:

r314070 | dylanmckay | 2017-09-24 14:07:26 +1300 (Sun, 24 Sep 2017) | 6 lines

[AVR] Implement getCmpLibcallReturnType().

This fixes the avr-rust issue (#75) with floating-point comparisons generating 
broken code.
By default, LLVM assumes these comparisons return 32-bit values, but ours are 
8-bit.

Patch By Thomas Backman.


Modified:
llvm/branches/release_50/lib/Target/AVR/AVRISelLowering.h

Modified: llvm/branches/release_50/lib/Target/AVR/AVRISelLowering.h
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AVR/AVRISelLowering.h?rev=314357&r1=314356&r2=314357&view=diff
==
--- llvm/branches/release_50/lib/Target/AVR/AVRISelLowering.h (original)
+++ llvm/branches/release_50/lib/Target/AVR/AVRISelLowering.h Wed Sep 27 
15:17:11 2017
@@ -75,6 +75,11 @@ public:
   MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override {
 return MVT::i8;
   }
+
+  MVT::SimpleValueType getCmpLibcallReturnType() const override {
+return MVT::i8;
+  }
+
   const char *getTargetNodeName(unsigned Opcode) const override;
 
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;


___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm-branch] r314358 - Merging r311620:

2017-09-27 Thread Dylan McKay via llvm-branch-commits 
Author: dylanmckay
Date: Wed Sep 27 15:18:57 2017
New Revision: 314358

URL: http://llvm.org/viewvc/llvm-project?rev=314358&view=rev
Log:
Merging r311620:

r311620 | dylanmckay | 2017-08-24 12:14:38 +1200 (Thu, 24 Aug 2017) | 1 line

[AVR] Use the correct register classes for 16-bit atomic operations


Added:

llvm/branches/release_50/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
Modified:
llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td

Modified: llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td?rev=314358&r1=314357&r2=314358&view=diff
==
--- llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td (original)
+++ llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td Wed Sep 27 15:18:57 
2017
@@ -1238,35 +1238,55 @@ isReMaterializable = 1 in
  Requires<[HasSRAM]>;
 }
 
-class AtomicLoad :
-  Pseudo<(outs DRC:$rd), (ins PTRREGS:$rr), "atomic_op",
+class AtomicLoad :
+  Pseudo<(outs DRC:$rd), (ins PTRRC:$rr), "atomic_op",
  [(set DRC:$rd, (Op i16:$rr))]>;
 
-class AtomicStore :
-  Pseudo<(outs), (ins PTRDISPREGS:$rd, DRC:$rr), "atomic_op",
+class AtomicStore :
+  Pseudo<(outs), (ins PTRRC:$rd, DRC:$rr), "atomic_op",
  [(Op i16:$rd, DRC:$rr)]>;
 
-class AtomicLoadOp :
-  Pseudo<(outs DRC:$rd), (ins PTRREGS:$rr, DRC:$operand),
+class AtomicLoadOp :
+  Pseudo<(outs DRC:$rd), (ins PTRRC:$rr, DRC:$operand),
  "atomic_op",
  [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>;
 
-def AtomicLoad8   : AtomicLoad;
-def AtomicLoad16  : AtomicLoad;
+// FIXME: I think 16-bit atomic binary ops need to mark
+// r0 as clobbered.
 
-def AtomicStore8  : AtomicStore;
-def AtomicStore16 : AtomicStore;
-
-def AtomicLoadAdd8  : AtomicLoadOp;
-def AtomicLoadAdd16 : AtomicLoadOp;
-def AtomicLoadSub8  : AtomicLoadOp;
-def AtomicLoadSub16 : AtomicLoadOp;
-def AtomicLoadAnd8  : AtomicLoadOp;
-def AtomicLoadAnd16 : AtomicLoadOp;
-def AtomicLoadOr8   : AtomicLoadOp;
-def AtomicLoadOr16  : AtomicLoadOp;
-def AtomicLoadXor8  : AtomicLoadOp;
-def AtomicLoadXor16 : AtomicLoadOp;
+// Atomic instructions
+// ===
+//
+// These are all expanded by AVRExpandPseudoInsts
+//
+// 8-bit operations can use any pointer register because
+// they are expanded directly into an LD/ST instruction.
+//
+// 16-bit operations use 16-bit load/store postincrement instructions,
+// which require PTRDISPREGS.
+
+def AtomicLoad8   : AtomicLoad;
+def AtomicLoad16  : AtomicLoad;
+
+def AtomicStore8  : AtomicStore;
+def AtomicStore16 : AtomicStore;
+
+class AtomicLoadOp8 : AtomicLoadOp;
+class AtomicLoadOp16 : AtomicLoadOp;
+
+def AtomicLoadAdd8  : AtomicLoadOp8;
+def AtomicLoadAdd16 : AtomicLoadOp16;
+def AtomicLoadSub8  : AtomicLoadOp8;
+def AtomicLoadSub16 : AtomicLoadOp16;
+def AtomicLoadAnd8  : AtomicLoadOp8;
+def AtomicLoadAnd16 : AtomicLoadOp16;
+def AtomicLoadOr8   : AtomicLoadOp8;
+def AtomicLoadOr16  : AtomicLoadOp16;
+def AtomicLoadXor8  : AtomicLoadOp8;
+def AtomicLoadXor16 : AtomicLoadOp16;
 def AtomicFence : Pseudo<(outs), (ins), "atomic_fence",
  [(atomic_fence imm, imm)]>;
 

Added: 
llvm/branches/release_50/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll?rev=314358&view=auto
==
--- 
llvm/branches/release_50/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
 (added)
+++ 
llvm/branches/release_50/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
 Wed Sep 27 15:18:57 2017
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=avr | FileCheck %s
+
+; At one point, the 16-vit atomic load/store operations we defined in TableGen
+; to use 'PTRREGS', but the pseudo expander would generate LDDW/STDW 
instructions.
+;
+; This would sometimes cause codegen to fail because LDDW requires 
'PTRDISPREGS', and
+; so if we attempted to generate an atomic operation on the X register, it 
would hit
+; an assertion;
+
+%AtomicI16 = type { %UnsafeCell, [0 x i8] }
+%UnsafeCell = type { i16, [0 x i8] }
+
+; CHECK-LABEL: foo
+define i8 @foo(%AtomicI16*) {
+start:
+
+; We should not be generating atomics that use the X register, they will fail 
when emitting MC.
+; CHECK-NOT: X
+  %1 = getelementptr inbounds %AtomicI16, %AtomicI16* %0, i16 0, i32 0, i32 0
+  %2 = load atomic i16, i16* %1 seq_cst, align 2
+  ret i8 0
+}
+


___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-bran

[llvm-branch-commits] [llvm-branch] r314379 - Merging r314179:

2017-09-27 Thread Dylan McKay via llvm-branch-commits 
Author: dylanmckay
Date: Wed Sep 27 23:16:45 2017
New Revision: 314379

URL: http://llvm.org/viewvc/llvm-project?rev=314379&view=rev
Log:
Merging r314179:

r314179 | dylanmckay | 2017-09-26 13:45:27 +1300 (Tue, 26 Sep 2017) | 11 lines

[AVR] Use 1-byte alignment for all data types

This was an oversight in the original backend data layout.

The AVR architecture does not have the concept of unaligned loads - all
loads/stores from all addresses are aligned to one byte.

Discovered in avr-rust issue #64
https://github.com/avr-rust/rust/issues/64

Patch By Gergo Erdi.


Modified:
llvm/branches/release_50/lib/Target/AVR/AVRTargetMachine.cpp

Modified: llvm/branches/release_50/lib/Target/AVR/AVRTargetMachine.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AVR/AVRTargetMachine.cpp?rev=314379&r1=314378&r2=314379&view=diff
==
--- llvm/branches/release_50/lib/Target/AVR/AVRTargetMachine.cpp (original)
+++ llvm/branches/release_50/lib/Target/AVR/AVRTargetMachine.cpp Wed Sep 27 
23:16:45 2017
@@ -25,7 +25,7 @@
 
 namespace llvm {
 
-static const char *AVRDataLayout = 
"e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-n8";
+static const char *AVRDataLayout = 
"e-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8";
 
 /// Processes a CPU name.
 static StringRef getCPU(StringRef CPU) {


___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [cfe-branch] r314381 - Merging r314354:

2017-09-28 Thread Dylan McKay via llvm-branch-commits 
Author: dylanmckay
Date: Thu Sep 28 00:06:54 2017
New Revision: 314381

URL: http://llvm.org/viewvc/llvm-project?rev=314381&view=rev
Log:
Merging r314354:

r314354 | dylanmckay | 2017-09-28 11:09:01 +1300 (Thu, 28 Sep 2017) | 3 lines

[AVR] Update data layout to match current LLVM trunk

The data layout was changed in r314179 to fix atomic loads and stores.


Modified:
cfe/branches/release_50/lib/Basic/Targets.cpp

Modified: cfe/branches/release_50/lib/Basic/Targets.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/branches/release_50/lib/Basic/Targets.cpp?rev=314381&r1=314380&r2=314381&view=diff
==
--- cfe/branches/release_50/lib/Basic/Targets.cpp (original)
+++ cfe/branches/release_50/lib/Basic/Targets.cpp Thu Sep 28 00:06:54 2017
@@ -9350,8 +9350,7 @@ public:
 WIntType = SignedInt;
 Char32Type = UnsignedLong;
 SigAtomicType = SignedChar;
-resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64"
-   "-f32:32:32-f64:64:64-n8");
+resetDataLayout("e-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8");
   }
 
   void getTargetDefines(const LangOptions &Opts,


___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm-branch] r314382 - Merging r314183:

2017-09-28 Thread Dylan McKay via llvm-branch-commits 
Author: dylanmckay
Date: Thu Sep 28 00:13:51 2017
New Revision: 314382

URL: http://llvm.org/viewvc/llvm-project?rev=314382&view=rev
Log:
Merging r314183:

r314183 | dylanmckay | 2017-09-26 15:07:54 +1300 (Tue, 26 Sep 2017) | 3 lines

[AVR] Fix the build after setting alignment to 1 in r314179

Changing all types to be byte-aligned broke a small number of tests.


Modified:
llvm/branches/release_50/test/CodeGen/AVR/call.ll
llvm/branches/release_50/test/CodeGen/AVR/directmem.ll
llvm/branches/release_50/test/CodeGen/AVR/varargs.ll

Modified: llvm/branches/release_50/test/CodeGen/AVR/call.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/test/CodeGen/AVR/call.ll?rev=314382&r1=314381&r2=314382&view=diff
==
--- llvm/branches/release_50/test/CodeGen/AVR/call.ll (original)
+++ llvm/branches/release_50/test/CodeGen/AVR/call.ll Thu Sep 28 00:13:51 2017
@@ -31,8 +31,8 @@ define i8 @calli8_reg() {
 define i8 @calli8_stack() {
 ; CHECK-LABEL: calli8_stack:
 ; CHECK: ldi [[REG1:r[0-9]+]], 10
-; CHECK: push [[REG1]]
-; CHECK: ldi [[REG1]], 11
+; CHECK: ldi [[REG2:r[0-9]+]], 11
+; CHECK: push [[REG2]]
 ; CHECK: push [[REG1]]
 ; CHECK: call foo8_3
 %result1 = call i8 @foo8_3(i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, 
i8 9, i8 10, i8 11)
@@ -142,7 +142,7 @@ define void @testcallprologue() {
 ; CHECK-LABEL: testcallprologue:
 ; CHECK: push r28
 ; CHECK: push r29
-; CHECK: sbiw r28, 28
+; CHECK: sbiw r28, 27
 ; CHECK: ldi [[REG1:r[0-9]+]], 88
 ; CHECK: std Y+9, [[REG1]]
 ; CHECK: ldi [[REG1:r[0-9]+]], 11

Modified: llvm/branches/release_50/test/CodeGen/AVR/directmem.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/test/CodeGen/AVR/directmem.ll?rev=314382&r1=314381&r2=314382&view=diff
==
--- llvm/branches/release_50/test/CodeGen/AVR/directmem.ll (original)
+++ llvm/branches/release_50/test/CodeGen/AVR/directmem.ll Thu Sep 28 00:13:51 
2017
@@ -33,12 +33,12 @@ define i8 @global8_load() {
 
 define void @array8_store() {
 ; CHECK-LABEL: array8_store:
+; CHECK: ldi [[REG1:r[0-9]+]], 3
+; CHECK: sts char.array+2, [[REG1]]
+; CHECK: ldi [[REG3:r[0-9]+]], 1
 ; CHECK: ldi [[REG2:r[0-9]+]], 2
 ; CHECK: sts char.array+1, [[REG2]]
-; CHECK: ldi [[REG1:r[0-9]+]], 1
-; CHECK: sts char.array, [[REG1]]
-; CHECK: ldi [[REG:r[0-9]+]], 3
-; CHECK: sts char.array+2, [[REG]]
+; CHECK: sts char.array, [[REG3]]
   store i8 1, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @char.array, i32 
0, i64 0)
   store i8 2, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @char.array, i32 
0, i64 1)
   store i8 3, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @char.array, i32 
0, i64 2)

Modified: llvm/branches/release_50/test/CodeGen/AVR/varargs.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/test/CodeGen/AVR/varargs.ll?rev=314382&r1=314381&r2=314382&view=diff
==
--- llvm/branches/release_50/test/CodeGen/AVR/varargs.ll (original)
+++ llvm/branches/release_50/test/CodeGen/AVR/varargs.ll Thu Sep 28 00:13:51 
2017
@@ -27,8 +27,8 @@ define i16 @varargs1(i8* nocapture %x, .
 
 define i16 @varargs2(i8* nocapture %x, ...) {
 ; CHECK-LABEL: varargs2:
-; CHECK: ld r24, Z
-; CHECK: ldd r25, Z+1
+; CHECK: ldd r24, [[REG:X|Y|Z]]+{{[0-9]+}}
+; CHECK: ldd r25, [[REG]]+{{[0-9]+}}
   %ap = alloca i8*
   %ap1 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap1)


___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm-branch] r314383 - Merging r314180:

2017-09-28 Thread Dylan McKay via llvm-branch-commits 
Author: dylanmckay
Date: Thu Sep 28 00:18:32 2017
New Revision: 314383

URL: http://llvm.org/viewvc/llvm-project?rev=314383&view=rev
Log:
Merging r314180:

r314180 | dylanmckay | 2017-09-26 13:51:03 +1300 (Tue, 26 Sep 2017) | 7 lines

[AVR] When lowering shifts into loops, put newly generated MBBs in the same
spot as the original MBB

Discovered in avr-rust/rust#62
https://github.com/avr-rust/rust/issues/62

Patch by Gergo Erdi.


Modified:
llvm/branches/release_50/lib/Target/AVR/AVRISelLowering.cpp

Modified: llvm/branches/release_50/lib/Target/AVR/AVRISelLowering.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AVR/AVRISelLowering.cpp?rev=314383&r1=314382&r2=314383&view=diff
==
--- llvm/branches/release_50/lib/Target/AVR/AVRISelLowering.cpp (original)
+++ llvm/branches/release_50/lib/Target/AVR/AVRISelLowering.cpp Thu Sep 28 
00:18:32 2017
@@ -1469,8 +1469,10 @@ MachineBasicBlock *AVRTargetLowering::in
   }
 
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
-  MachineFunction::iterator I = BB->getParent()->begin();
-  ++I;
+
+  MachineFunction::iterator I;
+  for (I = F->begin(); I != F->end() && &(*I) != BB; ++I);
+  if (I != F->end()) ++I;
 
   // Create loop block.
   MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);


___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm-branch] r315832 - Merging r314890:

2017-10-14 Thread Dylan McKay via llvm-branch-commits 
Author: dylanmckay
Date: Sat Oct 14 15:29:18 2017
New Revision: 315832

URL: http://llvm.org/viewvc/llvm-project?rev=315832&view=rev
Log:
Merging r314890:

r314890 | dylanmckay | 2017-10-04 22:51:21 +1300 (Wed, 04 Oct 2017) | 16 lines

[AVR] Fix displacement overflow for LDDW/STDW

In some cases, the code generator attempts to generate instructions such as:

lddw r24, Y+63

which expands to:

ldd r24, Y+63
ldd r25, Y+64 # Oops! This is actually ld r25, Y in the binary

This commit limits the first offset to 62, and thus the second to 63.
It also updates some asserts in AVRExpandPseudoInsts.cpp, including for
INW and OUTW, which appear to be unused.

Patch by Thomas Backman.


Added:
llvm/branches/release_50/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
Modified:
llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp
llvm/branches/release_50/lib/Target/AVR/AVRRegisterInfo.cpp

Modified: llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp?rev=315832&r1=315831&r2=315832&view=diff
==
--- llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp (original)
+++ llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp Sat Oct 14 
15:29:18 2017
@@ -699,7 +699,9 @@ bool AVRExpandPseudo::expandsplitReg(DstReg, DstLoReg, DstHiReg);
 
-  assert(Imm <= 63 && "Offset is out of range");
+  // Since we add 1 to the Imm value for the high byte below, and 63 is the 
highest Imm value
+  // allowed for the instruction, 62 is the limit here.
+  assert(Imm <= 62 && "Offset is out of range");
 
   // Use a temporary register if src and dst registers are the same.
   if (DstReg == SrcReg)
@@ -1074,7 +1076,9 @@ bool AVRExpandPseudo::expandsplitReg(SrcReg, SrcLoReg, SrcHiReg);
 
-  assert(Imm <= 63 && "Offset is out of range");
+  // Since we add 1 to the Imm value for the high byte below, and 63 is the 
highest Imm value
+  // allowed for the instruction, 62 is the limit here.
+  assert(Imm <= 62 && "Offset is out of range");
 
   auto MIBLO = buildMI(MBB, MBBI, OpLo)
 .addReg(DstReg)
@@ -1104,7 +1108,9 @@ bool AVRExpandPseudo::expandsplitReg(DstReg, DstLoReg, DstHiReg);
 
-  assert(Imm <= 63 && "Address is out of range");
+  // Since we add 1 to the Imm value for the high byte below, and 63 is the 
highest Imm value
+  // allowed for the instruction, 62 is the limit here.
+  assert(Imm <= 62 && "Address is out of range");
 
   auto MIBLO = buildMI(MBB, MBBI, OpLo)
 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
@@ -1132,7 +1138,9 @@ bool AVRExpandPseudo::expandsplitReg(SrcReg, SrcLoReg, SrcHiReg);
 
-  assert(Imm <= 63 && "Address is out of range");
+  // Since we add 1 to the Imm value for the high byte below, and 63 is the 
highest Imm value
+  // allowed for the instruction, 62 is the limit here.
+  assert(Imm <= 62 && "Address is out of range");
 
   // 16 bit I/O writes need the high byte first
   auto MIBHI = buildMI(MBB, MBBI, OpHi)

Modified: llvm/branches/release_50/lib/Target/AVR/AVRRegisterInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AVR/AVRRegisterInfo.cpp?rev=315832&r1=315831&r2=315832&view=diff
==
--- llvm/branches/release_50/lib/Target/AVR/AVRRegisterInfo.cpp (original)
+++ llvm/branches/release_50/lib/Target/AVR/AVRRegisterInfo.cpp Sat Oct 14 
15:29:18 2017
@@ -203,7 +203,7 @@ void AVRRegisterInfo::eliminateFrameInde
   // If the offset is too big we have to adjust and restore the frame pointer
   // to materialize a valid load/store with displacement.
   //:TODO: consider using only one adiw/sbiw chain for more than one frame 
index
-  if (Offset > 63) {
+  if (Offset > 62) {
 unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK;
 int AddOffset = Offset - 63 + 1;
 

Added: llvm/branches/release_50/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/test/CodeGen/AVR/std-ldd-immediate-overflow.ll?rev=315832&view=auto
==
--- llvm/branches/release_50/test/CodeGen/AVR/std-ldd-immediate-overflow.ll 
(added)
+++ llvm/branches/release_50/test/CodeGen/AVR/std-ldd-immediate-overflow.ll Sat 
Oct 14 15:29:18 2017
@@ -0,0 +1,18 @@
+; RUN: llc -O0 < %s -march=avr | FileCheck %s
+
+define i32 @std_ldd_overflow() {
+  %src = alloca [4 x i8]
+  %dst = alloca [4 x i8]
+  %buf = alloca [28 x i16]
+  %1 = bitcast [4 x i8]* %src to i32*
+  store i32 0, i32 *%1
+  %2 = bitcast [4 x i8]* %dst to i8*
+  %3 = bitcast [4 x i8]* %src to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i16(i8

[llvm-branch-commits] [llvm-branch] r315834 - Merging r314896:

2017-10-14 Thread Dylan McKay via llvm-branch-commits 
Author: dylanmckay
Date: Sat Oct 14 15:30:19 2017
New Revision: 315834

URL: http://llvm.org/viewvc/llvm-project?rev=315834&view=rev
Log:
Merging r314896:

r314896 | dylanmckay | 2017-10-04 23:33:36 +1300 (Wed, 04 Oct 2017) | 3 lines

[AVR] Elaborate LDWRdPtr into `ld r, X++; ld r+1, X`

Patch by Gergo Erdi.


Modified:
llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp
llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td
llvm/branches/release_50/test/CodeGen/AVR/atomics/load16.ll
llvm/branches/release_50/test/CodeGen/AVR/load.ll
llvm/branches/release_50/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
llvm/branches/release_50/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
llvm/branches/release_50/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
llvm/branches/release_50/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir

Modified: llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp?rev=315834&r1=315833&r2=315834&view=diff
==
--- llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp (original)
+++ llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp Sat Oct 14 
15:30:19 2017
@@ -583,8 +583,8 @@ bool AVRExpandPseudo::expandsplitReg(DstReg, DstLoReg, DstHiReg);
 
   // Use a temporary register if src and dst registers are the same.
@@ -597,6 +597,7 @@ bool AVRExpandPseudo::expandhttp://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td?rev=315834&r1=315833&r2=315834&view=diff
==
--- llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td (original)
+++ llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td Sat Oct 14 15:30:19 
2017
@@ -1152,10 +1152,10 @@ isReMaterializable = 1 in
   //
   // Expands to:
   // ld Rd,   P+
-  // ld Rd+1, P+
+  // ld Rd+1, P
   let Constraints = "@earlyclobber $reg" in
   def LDWRdPtr : Pseudo<(outs DREGS:$reg),
-(ins PTRDISPREGS:$ptrreg),
+(ins PTRREGS:$ptrreg),
 "ldw\t$reg, $ptrreg",
 [(set i16:$reg, (load i16:$ptrreg))]>,
  Requires<[HasSRAM]>;
@@ -1164,7 +1164,7 @@ isReMaterializable = 1 in
 // Indirect loads (with postincrement or predecrement).
 let mayLoad = 1,
 hasSideEffects = 0,
-Constraints = "$ptrreg = $base_wb,@earlyclobber $reg,@earlyclobber $base_wb" in
+Constraints = "$ptrreg = $base_wb,@earlyclobber $reg" in
 {
   def LDRdPtrPi : FSTLD<0,
 0b01,

Modified: llvm/branches/release_50/test/CodeGen/AVR/atomics/load16.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/test/CodeGen/AVR/atomics/load16.ll?rev=315834&r1=315833&r2=315834&view=diff
==
--- llvm/branches/release_50/test/CodeGen/AVR/atomics/load16.ll (original)
+++ llvm/branches/release_50/test/CodeGen/AVR/atomics/load16.ll Sat Oct 14 
15:30:19 2017
@@ -3,8 +3,8 @@
 ; CHECK-LABEL: atomic_load16
 ; CHECK:  in r0, 63
 ; CHECK-NEXT: cli
+; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]+
 ; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]
-; CHECK-NEXT: ldd [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]+
 ; CHECK-NEXT: out 63, r0
 define i16 @atomic_load16(i16* %foo) {
   %val = load atomic i16, i16* %foo unordered, align 2
@@ -29,8 +29,8 @@ define i16 @atomic_load_cmp_swap16(i16*
 ; CHECK-LABEL: atomic_load_add16
 ; CHECK:  in r0, 63
 ; CHECK-NEXT: cli
-; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
-; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
+; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]+
+; CHECK-NEXT: ld [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]
 ; CHECK-NEXT: add [[RR1]], [[TMP:r[0-9]+]]
 ; CHECK-NEXT: adc [[RR2]], [[TMP:r[0-9]+]]
 ; CHECK-NEXT: st [[RD1]], [[RR1]]
@@ -44,8 +44,8 @@ define i16 @atomic_load_add16(i16* %foo)
 ; CHECK-LABEL: atomic_load_sub16
 ; CHECK:  in r0, 63
 ; CHECK-NEXT: cli
-; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
-; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
+; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]+
+; CHECK-NEXT: ld [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]
 ; CHECK-NEXT: sub [[RR1]], [[TMP:r[0-9]+]]
 ; CHECK-NEXT: sbc [[RR2]], [[TMP:r[0-9]+]]
 ; CHECK-NEXT: st [[RD1]], [[RR1]]
@@ -59,8 +59,8 @@ define i16 @atomic_load_sub16(i16* %foo)
 ; CHECK-LABEL: atomic_load_and16
 ; CHECK:  in r0, 63
 ; CHECK-NEXT: cli
-; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
-; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
+; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]+
+; CHECK-NEXT: ld [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]
 ; CHECK-NEXT: and [[RR1]], [[TMP:r[0-9]+]]

[llvm-branch-commits] [llvm-branch] r315835 - Merging r314897:

2017-10-14 Thread Dylan McKay via llvm-branch-commits 
Author: dylanmckay
Date: Sat Oct 14 15:30:44 2017
New Revision: 315835

URL: http://llvm.org/viewvc/llvm-project?rev=315835&view=rev
Log:
Merging r314897:

r314897 | dylanmckay | 2017-10-04 23:36:07 +1300 (Wed, 04 Oct 2017) | 3 lines

[AVR] Factor out mayLoad in tablegen patterns

Patch by Gergo Erdi.


Modified:
llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td

Modified: llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td?rev=315835&r1=315834&r2=315835&view=diff
==
--- llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td (original)
+++ llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td Sat Oct 14 15:30:44 
2017
@@ -1417,6 +1417,7 @@ def STDWPtrQRr : Pseudo<(outs),
 // Load program memory operations.
 let canFoldAsLoad = 1,
 isReMaterializable = 1,
+mayLoad = 1,
 hasSideEffects = 0 in
 {
   let Defs = [R0],
@@ -1437,8 +1438,7 @@ hasSideEffects = 0 in
Requires<[HasLPMX]>;
 
   // Load program memory, while postincrementing the Z register.
-  let mayLoad = 1,
-  Defs = [R31R30] in
+  let Defs = [R31R30] in
   {
 def LPMRdZPi : FLPMX<0,
  1,


___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm-branch] r315836 - Merging r314898:

2017-10-14 Thread Dylan McKay via llvm-branch-commits 
Author: dylanmckay
Date: Sat Oct 14 15:31:06 2017
New Revision: 315836

URL: http://llvm.org/viewvc/llvm-project?rev=315836&view=rev
Log:
Merging r314898:

r314898 | dylanmckay | 2017-10-04 23:37:22 +1300 (Wed, 04 Oct 2017) | 6 lines

[AVR] Implement LPMWRdZ pseudo-instruction's expansion.

FIXME: implementation is mostly copy-pasted from LDWRdPtr, so we should
refactor a bit and unify the two

Patch by Gerdo Erdi.


Modified:
llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp

Modified: llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp?rev=315836&r1=315835&r2=315836&view=diff
==
--- llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp (original)
+++ llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp Sat Oct 14 
15:31:06 2017
@@ -743,7 +743,50 @@ bool AVRExpandPseudo::expand
 bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) {
-  llvm_unreachable("wide LPM is unimplemented");
+  MachineInstr &MI = *MBBI;
+  unsigned OpLo, OpHi, DstLoReg, DstHiReg;
+  unsigned DstReg = MI.getOperand(0).getReg();
+  unsigned TmpReg = 0; // 0 for no temporary register
+  unsigned SrcReg = MI.getOperand(1).getReg();
+  bool SrcIsKill = MI.getOperand(1).isKill();
+  OpLo = AVR::LPMRdZPi;
+  OpHi = AVR::LPMRdZ;
+  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
+
+  // Use a temporary register if src and dst registers are the same.
+  if (DstReg == SrcReg)
+TmpReg = scavengeGPR8(MI);
+
+  unsigned CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;
+  unsigned CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;
+
+  // Load low byte.
+  auto MIBLO = buildMI(MBB, MBBI, OpLo)
+  .addReg(CurDstLoReg, RegState::Define)
+  .addReg(SrcReg);
+
+  // Push low byte onto stack if necessary.
+  if (TmpReg)
+buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
+
+  // Load high byte.
+  auto MIBHI = buildMI(MBB, MBBI, OpHi)
+  .addReg(CurDstHiReg, RegState::Define)
+  .addReg(SrcReg, getKillRegState(SrcIsKill));
+
+  if (TmpReg) {
+// Move the high byte into the final destination.
+buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg);
+
+// Move the low byte from the scratch space into the final destination.
+buildMI(MBB, MBBI, AVR::POPRd).addReg(DstLoReg);
+  }
+
+  MIBLO->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
+  MIBHI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
+
+  MI.eraseFromParent();
+  return true;
 }
 
 template <>


___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits