Author: dylanmckay
Date: Sat Oct 14 15:29:18 2017
New Revision: 315832
URL: http://llvm.org/viewvc/llvm-project?rev=315832&view=rev
Log:
Merging r314890:
------------------------------------------------------------------------
r314890 | dylanmckay | 2017-10-04 22:51:21 +1300 (Wed, 04 Oct 2017) | 16 lines
[AVR] Fix displacement overflow for LDDW/STDW
In some cases, the code generator attempts to generate instructions such as:
lddw r24, Y+63
which expands to:
ldd r24, Y+63
ldd r25, Y+64 # Oops! This is actually ld r25, Y in the binary
This commit limits the first offset to 62, and thus the second to 63.
It also updates some asserts in AVRExpandPseudoInsts.cpp, including for
INW and OUTW, which appear to be unused.
Patch by Thomas Backman.
------------------------------------------------------------------------
Added:
llvm/branches/release_50/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
Modified:
llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp
llvm/branches/release_50/lib/Target/AVR/AVRRegisterInfo.cpp
Modified: llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp?rev=315832&r1=315831&r2=315832&view=diff
==============================================================================
--- llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp (original)
+++ llvm/branches/release_50/lib/Target/AVR/AVRExpandPseudoInsts.cpp Sat Oct 14
15:29:18 2017
@@ -699,7 +699,9 @@ bool AVRExpandPseudo::expand<AVR::LDDWRd
OpHi = AVR::LDDRdPtrQ;
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
- assert(Imm <= 63 && "Offset is out of range");
+ // Since we add 1 to the Imm value for the high byte below, and 63 is the
highest Imm value
+ // allowed for the instruction, 62 is the limit here.
+ assert(Imm <= 62 && "Offset is out of range");
// Use a temporary register if src and dst registers are the same.
if (DstReg == SrcReg)
@@ -1074,7 +1076,9 @@ bool AVRExpandPseudo::expand<AVR::STDWPt
OpHi = AVR::STDPtrQRr;
TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
- assert(Imm <= 63 && "Offset is out of range");
+ // Since we add 1 to the Imm value for the high byte below, and 63 is the
highest Imm value
+ // allowed for the instruction, 62 is the limit here.
+ assert(Imm <= 62 && "Offset is out of range");
auto MIBLO = buildMI(MBB, MBBI, OpLo)
.addReg(DstReg)
@@ -1104,7 +1108,9 @@ bool AVRExpandPseudo::expand<AVR::INWRdA
OpHi = AVR::INRdA;
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
- assert(Imm <= 63 && "Address is out of range");
+ // Since we add 1 to the Imm value for the high byte below, and 63 is the
highest Imm value
+ // allowed for the instruction, 62 is the limit here.
+ assert(Imm <= 62 && "Address is out of range");
auto MIBLO = buildMI(MBB, MBBI, OpLo)
.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
@@ -1132,7 +1138,9 @@ bool AVRExpandPseudo::expand<AVR::OUTWAR
OpHi = AVR::OUTARr;
TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
- assert(Imm <= 63 && "Address is out of range");
+ // Since we add 1 to the Imm value for the high byte below, and 63 is the
highest Imm value
+ // allowed for the instruction, 62 is the limit here.
+ assert(Imm <= 62 && "Address is out of range");
// 16 bit I/O writes need the high byte first
auto MIBHI = buildMI(MBB, MBBI, OpHi)
Modified: llvm/branches/release_50/lib/Target/AVR/AVRRegisterInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AVR/AVRRegisterInfo.cpp?rev=315832&r1=315831&r2=315832&view=diff
==============================================================================
--- llvm/branches/release_50/lib/Target/AVR/AVRRegisterInfo.cpp (original)
+++ llvm/branches/release_50/lib/Target/AVR/AVRRegisterInfo.cpp Sat Oct 14
15:29:18 2017
@@ -203,7 +203,7 @@ void AVRRegisterInfo::eliminateFrameInde
// If the offset is too big we have to adjust and restore the frame pointer
// to materialize a valid load/store with displacement.
//:TODO: consider using only one adiw/sbiw chain for more than one frame
index
- if (Offset > 63) {
+ if (Offset > 62) {
unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK;
int AddOffset = Offset - 63 + 1;
Added: llvm/branches/release_50/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/test/CodeGen/AVR/std-ldd-immediate-overflow.ll?rev=315832&view=auto
==============================================================================
--- llvm/branches/release_50/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
(added)
+++ llvm/branches/release_50/test/CodeGen/AVR/std-ldd-immediate-overflow.ll Sat
Oct 14 15:29:18 2017
@@ -0,0 +1,18 @@
+; RUN: llc -O0 < %s -march=avr | FileCheck %s
+
+define i32 @std_ldd_overflow() {
+ %src = alloca [4 x i8]
+ %dst = alloca [4 x i8]
+ %buf = alloca [28 x i16]
+ %1 = bitcast [4 x i8]* %src to i32*
+ store i32 0, i32 *%1
+ %2 = bitcast [4 x i8]* %dst to i8*
+ %3 = bitcast [4 x i8]* %src to i8*
+ call void @llvm.memcpy.p0i8.p0i8.i16(i8* %2, i8* %3, i16 4, i32 1, i1 false)
+; CHECK-NOT: std {{[XYZ]}}+64, {{r[0-9]+}}
+; CHECK-NOT: ldd {{r[0-9]+}}, {{[XYZ]}}+64
+
+ ret i32 0
+}
+
+declare void @llvm.memcpy.p0i8.p0i8.i16(i8* nocapture writeonly, i8* nocapture
readonly, i16, i32, i1)
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