Author: dylanmckay
Date: Sat Oct 14 15:30:44 2017
New Revision: 315835
URL: http://llvm.org/viewvc/llvm-project?rev=315835&view=rev
Log:
Merging r314897:
------------------------------------------------------------------------
r314897 | dylanmckay | 2017-10-04 23:36:07 +1300 (Wed, 04 Oct 2017) | 3 lines
[AVR] Factor out mayLoad in tablegen patterns
Patch by Gergo Erdi.
------------------------------------------------------------------------
Modified:
llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td
Modified: llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td?rev=315835&r1=315834&r2=315835&view=diff
==============================================================================
--- llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td (original)
+++ llvm/branches/release_50/lib/Target/AVR/AVRInstrInfo.td Sat Oct 14 15:30:44
2017
@@ -1417,6 +1417,7 @@ def STDWPtrQRr : Pseudo<(outs),
// Load program memory operations.
let canFoldAsLoad = 1,
isReMaterializable = 1,
+mayLoad = 1,
hasSideEffects = 0 in
{
let Defs = [R0],
@@ -1437,8 +1438,7 @@ hasSideEffects = 0 in
Requires<[HasLPMX]>;
// Load program memory, while postincrementing the Z register.
- let mayLoad = 1,
- Defs = [R31R30] in
+ let Defs = [R31R30] in
{
def LPMRdZPi : FLPMX<0,
1,
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