Re: [V6 1/2] phy: ralink-usb: add driver for Mediatek/Ralink
Hi Kishon,
Thanks for the review.
On 16/08/17 14:57, Kishon Vijay Abraham I wrote:
Hi,
On Tuesday 15 August 2017 06:17 PM, Harvey Hunt wrote:
From: John Crispin
Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
The driver sets up power and host mode, but also needs to
configure PHY registers for the MT7628 and MT7688.
Signed-off-by: John Crispin
Signed-off-by: Harvey Hunt
Cc: linux-kernel@vger.kernel.org
Cc: linux-media...@lists.infradead.org
---
Changes in V6
* Add binding for MT7628
* Configure PHY registers for MT76{2,8}8
Changes in V5
* Depend on MIPS
Changes in V4
* Remove Allwinner from comment
* Depend on COMPILE_TEST
Changes in V3
* Separate DT bindings
* Update Kconfig text
* Modify John's email address
* Rebase onto v4.13-rc3
Changes in V2
* remove refcounting
* drop empty functions
* dont use static globals
* use explicit compatible strings
drivers/phy/Kconfig | 9 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-ralink-usb.c | 238 +++
3 files changed, 248 insertions(+)
create mode 100644 drivers/phy/phy-ralink-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index c1807d4..a95394b 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -41,6 +41,15 @@ config PHY_PISTACHIO_USB
help
Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.
+config PHY_RALINK_USB
+ tristate "Ralink USB PHY driver"
+ depends on RALINK || COMPILE_TEST
+ depends on MIPS
depends on (RALINK && MIPS) || COMPILE_TEST ??
Aren't they equivalent?
Besides, I will be able to drop the MIPS dependency once I implement
syscon, as discussed later...
+ select GENERIC_PHY
+ help
+ This option enables support for the Ralink USB PHY found inside
+ RT3352, MT7620, MT7628 and MT7688.
+
config PHY_XGENE
tristate "APM X-Gene 15Gbps PHY support"
depends on HAS_IOMEM && OF && (ARM64 || COMPILE_TEST)
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f252201..60ed30b 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
obj-$(CONFIG_PHY_MT65XX_USB3) += phy-mt65xx-usb3.o
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
+obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
obj-$(CONFIG_ARCH_SUNXI) += allwinner/
obj-$(CONFIG_ARCH_MESON) += amlogic/
diff --git a/drivers/phy/phy-ralink-usb.c b/drivers/phy/phy-ralink-usb.c
new file mode 100644
index 000..d027c43
--- /dev/null
+++ b/drivers/phy/phy-ralink-usb.c
We have separate directories for every vendor. Care to add a new directory for
ralink?
Done
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2016 John Crispin
2017
Updated
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
Er.. I think we can't add COMPILE_TEST with this. Why do you have to include
arch specific headers?
I'll remove this header and instead add a syscon node to the SoC's DT
so that the PHY driver can enable its clock and host mode. I'll update
the bindings accordingly.
+
+#define RT_SYSC_REG_SYSCFG10x014
+#define RT_SYSC_REG_CLKCFG10x030
+#define RT_SYSC_REG_USB_PHY_CFG0x05c
+
+#define OFS_U2_PHY_AC0 0x800
+#define OFS_U2_PHY_AC1 0x804
+#define OFS_U2_PHY_AC2 0x808
+#define OFS_U2_PHY_ACR00x810
+#define OFS_U2_PHY_ACR10x814
+#define OFS_U2_PHY_ACR20x818
+#define OFS_U2_PHY_ACR30x81C
+#define OFS_U2_PHY_ACR40x820
+#define OFS_U2_PHY_AMON0 0x824
+#define OFS_U2_PHY_DCR00x860
+#define OFS_U2_PHY_DCR10x864
+#define OFS_U2_PHY_DTM00x868
+#define OFS_U2_PHY_DTM10x86C
+
+#define RT_RSTCTRL_UDEVBIT(25)
+#define RT_RSTCTRL_UHSTBIT(22)
+#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
+
+#define MT7620_CLKCFG1_UPHY0_
[V7] dt-bindings: phy: Add bindings for ralink-usb PHY
From: John Crispin
Add a binding for the USB phy on Mediatek/Ralink SoCs.
Signed-off-by: John Crispin
Signed-off-by: Harvey Hunt
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-media...@lists.infradead.org
---
Changes in V7:
* Add required ralink,sysctl property
Changes in V6:
* Add MT7628 binding
* Add optional reg property
Changes in V5:
* None
Changes in V4:
* None
Changes in V3:
* Split out from first patch
.../devicetree/bindings/phy/ralink-usb-phy.txt | 23 ++
1 file changed, 23 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
new file mode 100644
index 000..9d2868a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
@@ -0,0 +1,23 @@
+Mediatek/Ralink USB PHY
+
+Required properties:
+ - compatible: "ralink,rt3352-usbphy"
+ "mediatek,mt7620-usbphy"
+ "mediatek,mt7628-usbphy"
+ - reg: required for "mediatek,mt7628-usbphy", unused otherwise
+ - #phy-cells: should be 0
+ - ralink,sysctl: a phandle to a ralink syscon register region
+ - resets: the two reset controllers for host and device
+ - reset-names: the names of the 2 reset controllers
+
+Example:
+
+usbphy: phy {
+ compatible = "mediatek,mt7628-usbphy";
+ reg = <0x1012 0x1000>;
+ #phy-cells = <0>;
+
+ ralink,sysctl = <&sysc>;
+ resets = <&rstctrl 22 &rstctrl 25>;
+ reset-names = "host", "device";
+};
--
2.7.4
[V7] phy: ralink-usb: add driver for Mediatek/Ralink
From: John Crispin
Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
The driver sets up power and host mode, but also needs to
configure PHY registers for the MT7628 and MT7688.
Signed-off-by: John Crispin
Signed-off-by: Harvey Hunt
Cc: linux-kernel@vger.kernel.org
Cc: linux-media...@lists.infradead.org
---
Changes in V7
* Create ralink sub directory
* Switch from io{read,write}32 to {read,write}l
* Update copyright year
* Remove MIPS specific header
* Use regmap to access sysctl registers
* Parse syscon phandle to get regmap
* Select CONFIG_MFD_SYSCON
* Remove depends on MIPS
* Rearrange probe function
Changes in V6
* Add binding for MT7628
* Configure PHY registers for MT76{2,8}8
Changes in V5
* Depend on MIPS
Changes in V4
* Remove Allwinner from comment
* Depend on COMPILE_TEST
Changes in V3
* Separate DT bindings
* Update Kconfig text
* Modify John's email address
* Rebase onto v4.13-rc3
Changes in V2
* remove refcounting
* drop empty functions
* dont use static globals
* use explicit compatible strings
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile| 1 +
drivers/phy/ralink/Kconfig | 11 ++
drivers/phy/ralink/Makefile | 1 +
drivers/phy/ralink/phy-ralink-usb.c | 249
5 files changed, 263 insertions(+)
create mode 100644 drivers/phy/ralink/Kconfig
create mode 100644 drivers/phy/ralink/Makefile
create mode 100644 drivers/phy/ralink/phy-ralink-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index c1807d4..3792fd7 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -55,6 +55,7 @@ source "drivers/phy/hisilicon/Kconfig"
source "drivers/phy/marvell/Kconfig"
source "drivers/phy/motorola/Kconfig"
source "drivers/phy/qualcomm/Kconfig"
+source "drivers/phy/ralink/Kconfig"
source "drivers/phy/renesas/Kconfig"
source "drivers/phy/rockchip/Kconfig"
source "drivers/phy/samsung/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f252201..db9174d 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -18,6 +18,7 @@ obj-y += broadcom/\
marvell/ \
motorola/\
qualcomm/\
+ ralink/ \
samsung/ \
st/ \
ti/
diff --git a/drivers/phy/ralink/Kconfig b/drivers/phy/ralink/Kconfig
new file mode 100644
index 000..b17635b
--- /dev/null
+++ b/drivers/phy/ralink/Kconfig
@@ -0,0 +1,11 @@
+#
+# PHY drivers for Ralink platforms.
+#
+config PHY_RALINK_USB
+ tristate "Ralink USB PHY driver"
+ depends on RALINK || COMPILE_TEST
+ select GENERIC_PHY
+ select MFD_SYSCON
+ help
+ This option enables support for the Ralink USB PHY found inside
+ RT3352, MT7620, MT7628 and MT7688.
diff --git a/drivers/phy/ralink/Makefile b/drivers/phy/ralink/Makefile
new file mode 100644
index 000..5c9e326
--- /dev/null
+++ b/drivers/phy/ralink/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
diff --git a/drivers/phy/ralink/phy-ralink-usb.c
b/drivers/phy/ralink/phy-ralink-usb.c
new file mode 100644
index 000..cade326
--- /dev/null
+++ b/drivers/phy/ralink/phy-ralink-usb.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (C) 2017 John Crispin
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define RT_SYSC_REG_SYSCFG10x014
+#define RT_SYSC_REG_CLKCFG10x030
+#define RT_SYSC_REG_USB_PHY_CFG0x05c
+
+#define OFS_U2_PHY_AC0 0x800
+#define OFS_U2_PHY_AC1 0x804
+#define OFS_U2_PHY_AC2 0x808
+#define OFS_U2_PHY_ACR00x810
+#define OFS_U2_PHY_ACR10x814
+#define OFS_U2_PHY_ACR20x818
+#define OFS_U2_PHY_ACR30x81C
+#define OFS_U2_PHY_ACR40x820
+#define OFS_U2_PHY_AMON0 0x824
+#define OFS_U2_PHY_D
Re: [PATCH] MIPS: dts: ralink: Add Mediatek MT7628A SoC
Hi Rob,
Thanks for the review.
On 17/08/17 22:34, Rob Herring wrote:
On Tue, Aug 15, 2017 at 05:28:50PM +0100, Harvey Hunt wrote:
The MT7628A is the successor to the MT7620 and pin compatible with the
MT7688A, although the latter supports only a 1T1R antenna rather than
a 2T2R antenna.
This commit adds support for the following features:
- UART
- USB PHY
- EHCI
- Interrupt controller
- System controller
- Memory controller
- Reset controller
Signed-off-by: Harvey Hunt
Cc: John Crispin
Cc: linux-m...@linux-mips.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-media...@lists.infradead.org
---
Documentation/devicetree/bindings/mips/ralink.txt | 1 +
arch/mips/boot/dts/ralink/mt7628a.dtsi| 125 ++
2 files changed, 126 insertions(+)
create mode 100644 arch/mips/boot/dts/ralink/mt7628a.dtsi
diff --git a/Documentation/devicetree/bindings/mips/ralink.txt
b/Documentation/devicetree/bindings/mips/ralink.txt
index b35a8d0..a16e8d7 100644
--- a/Documentation/devicetree/bindings/mips/ralink.txt
+++ b/Documentation/devicetree/bindings/mips/ralink.txt
@@ -15,3 +15,4 @@ value must be one of the following values:
ralink,rt5350-soc
ralink,mt7620a-soc
ralink,mt7620n-soc
+ ralink,mt7628a-soc
diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi
b/arch/mips/boot/dts/ralink/mt7628a.dtsi
new file mode 100644
index 000..8461fe9
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -0,0 +1,125 @@
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,mt7628a-soc";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mti,mips24KEc";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ resetctrl: resetctrl {
reset-controller {
Done
+ compatible = "ralink,rt2880-reset";
+ #reset-cells = <1>;
+ };
+
+ cpuintc: cpuintc {
interrupt-controller {
Done
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ palmbus@1000 {
+ compatible = "palmbus";
+ reg = <0x1000 0x20>;
+ ranges = <0x0 0x1000 0x1F>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysc@0 {
system-controller@0
Done
+ compatible = "ralink,mt7620a-sysc";
+ reg = <0x0 0x100>;
+ };
+
+ intc: intc@200 {
interrupt-controller@200
Done
+ compatible = "ralink,rt2880-intc";
+ reg = <0x200 0x100>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ resets = <&resetctrl 9>;
+ reset-names = "intc";
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+
+ ralink,intc-registers = <0x9c 0xa0
+0x6c 0xa4
+0x80 0x78>;
+ };
+
+ memc@300 {
memory-controller@300
Done
+ compatible = "ralink,mt7620a-memc";
+ reg = <0x300 0x100>;
+ };
+
+ uartlite@c00 {
serial@c00
And so on. IOW, use standard, generic node names as defined in the DT
spec.
The clocks for the UARTs are using the device names "uartlite", "uart1"
and "uart2" (as defined in arch/mips/ralink/mt7620.c).
Changing the name of the DT nodes causes the serial driver to bail as it
can't find the clock for the device.
arch/mips/boot/dts/ralink/mt7620a.dtsi is already using the uartlite
name, although it hasn't been documented...
Thanks,
Harvey
+ compatible = "ns16550a";
+ reg = <0xc00 0x100>;
+
+ resets = <&resetctrl 12>;
+ reset-names = "uart0";
+
+ interrupt-parent = <&intc>;
+ interrupts = <20>;
+
+ reg-shift = <2>;
+ };
+
+ uart1@d00 {
+ compatible = "ns16550a";
+ reg = <0xd00 0x100>;
+
+ resets = <&resetctrl 19>;
+ res
[PATCH v7] mtd: nand: increase ready wait timeout and report timeouts
From: Alex Smith
If nand_wait_ready() times out, this is silently ignored, and its
caller will then proceed to read from/write to the chip before it is
ready. This can potentially result in corruption with no indication as
to why.
While a 20ms timeout seems like it should be plenty enough, certain
behaviour can cause it to timeout much earlier than expected. The
situation which prompted this change was that CPU 0, which is
responsible for updating jiffies, was holding interrupts disabled
for a fairly long time while writing to the console during a printk,
causing several jiffies updates to be delayed. If CPU 1 happens to
enter the timeout loop in nand_wait_ready() just before CPU 0 re-
enables interrupts and updates jiffies, CPU 1 will immediately time
out when the delayed jiffies updates are made. The result of this is
that nand_wait_ready() actually waits less time than the NAND chip
would normally take to be ready, and then read_page() proceeds to
read out bad data from the chip.
The situation described above may seem unlikely, but in fact it can be
reproduced almost every boot on the MIPS Creator Ci20.
Therefore, this patch increases the timeout to 400ms. This should be
enough to cover cases where jiffies updates get delayed. In nand_wait()
the timeout was previously chosen based on whether erasing or
programming. This is changed to be 400ms unconditionally as well to
avoid similar problems there. nand_wait() is also slightly refactored
to be consistent with nand_wait{,_status}_ready(). These changes should
have no effect during normal operation.
Debugging this was made more difficult by the misleading comment above
nand_wait_ready() stating "The timeout is caught later" - no timeout was
ever reported, leading me away from the real source of the problem.
Therefore, a pr_warn() is added when a timeout does occur so that it is
easier to pinpoint similar problems in future.
Signed-off-by: Alex Smith
Signed-off-by: Harvey Hunt
Reviewed-by: Niklas Cassel
Cc: Alex Smith
Cc: Zubair Lutfullah Kakakhel
Cc: David Woodhouse
Cc: Brian Norris
Cc: Niklas Cassel
Cc: linux-...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
This patch was originally sent in a JZ4780 patch set, but sending
it on its own was deemed more appropriate. Alex Smith sent the
original patch - this is an unmodified version that he has asked me
to send.
v6 -> v7:
- Add Harvey's signed off by.
- Add Alex Smith to CC.
- Add Niklas' reviewed by.
v5 -> v6:
- Incorporate suggestions from Niklas Cassel.
v4 -> v5:
- Remove spurious change.
- Add Ezequiel's Reviewed-by.
v3 -> v4:
- New patch to fix issue encountered in external Ci20 3.18 kernel
branch which also applies upstream.
drivers/mtd/nand/nand_base.c | 33 -
1 file changed, 20 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index ceb68ca..8e58577 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -543,23 +543,32 @@ static void panic_nand_wait_ready(struct mtd_info *mtd,
unsigned long timeo)
}
}
-/* Wait for the ready pin, after a command. The timeout is caught later. */
+/**
+ * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
+ * @mtd: MTD device structure
+ *
+ * Wait for the ready pin after a command, and warn if a timeout occurs.
+ */
void nand_wait_ready(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd->priv;
- unsigned long timeo = jiffies + msecs_to_jiffies(20);
+ unsigned long timeo = 400;
- /* 400ms timeout */
if (in_interrupt() || oops_in_progress)
- return panic_nand_wait_ready(mtd, 400);
+ return panic_nand_wait_ready(mtd, timeo);
led_trigger_event(nand_led_trigger, LED_FULL);
/* Wait until command is processed or timeout occurs */
+ timeo = jiffies + msecs_to_jiffies(timeo);
do {
if (chip->dev_ready(mtd))
- break;
- touch_softlockup_watchdog();
+ goto out;
+ cond_resched();
} while (time_before(jiffies, timeo));
+
+ pr_warn_ratelimited(
+ "timeout while waiting for chip to become ready\n");
+out:
led_trigger_event(nand_led_trigger, LED_OFF);
}
EXPORT_SYMBOL_GPL(nand_wait_ready);
@@ -885,15 +894,13 @@ static void panic_nand_wait(struct mtd_info *mtd, struct
nand_chip *chip,
* @mtd: MTD device structure
* @chip: NAND chip structure
*
- * Wait for command done. This applies to erase and program only. Erase can
- * take up to 400ms and program up to 20ms according to general NAND and
- * SmartMedia specs.
+ * Wait for command done. This applies to erase and program only.
*/
static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
{
- int status, state = chip->state;
- unsigned long time
[PATCH v7,1/3] dt-bindings: binding for jz4780-{nand,bch}
From: Alex Smith
Add DT bindings for NAND devices connected to the NEMC on JZ4780 SoCs,
as well as the hardware BCH controller, used by the jz4780_{nand,bch}
drivers.
Signed-off-by: Alex Smith
Cc: Zubair Lutfullah Kakakhel
Cc: David Woodhouse
Cc: Brian Norris
Cc: linux-...@lists.infradead.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Alex Smith
Signed-off-by: Harvey Hunt
---
v6 -> v7:
- Add nand-ecc-mode to DT bindings.
- Add nand-on-flash-bbt to DT bindings.
v5 -> v6:
- No change.
v4 -> v5:
- Rename ingenic,bch-device to ingenic,bch-controller to fit with
existing convention.
v3 -> v4:
- No change
v2 -> v3:
- Rebase to 4.0-rc6
- Changed ingenic,ecc-size to common nand-ecc-step-size
- Changed ingenic,ecc-strength to common nand-ecc-strength
- Changed ingenic,busy-gpio to common rb-gpios
- Changed ingenic,wp-gpio to common wp-gpios
v1 -> v2:
- Rebase to 4.0-rc3
.../bindings/mtd/ingenic,jz4780-nand.txt | 61 ++
1 file changed, 61 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
new file mode 100644
index 000..44a0468
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
@@ -0,0 +1,61 @@
+* Ingenic JZ4780 NAND/BCH
+
+This file documents the device tree bindings for NAND flash devices on the
+JZ4780. NAND devices are connected to the NEMC controller (described in
+memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
+be children of the NEMC node.
+
+Required NAND device properties:
+- compatible: Should be set to "ingenic,jz4780-nand".
+- reg: For each bank with a NAND chip attached, should specify a bank number,
+ an offset of 0 and a size of 0x100 (i.e. the whole NEMC bank).
+
+Optional NAND device properties:
+- ingenic,bch-controller: To make use of the hardware BCH controller, this
+ property must contain a phandle for the BCH controller node. The required
+ properties for this node are described below. If this is not specified,
+ software BCH will be used instead.
+- nand-ecc-step-size: ECC block size in bytes.
+- nand-ecc-strength: ECC strength (max number of correctable bits).
+- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default
+- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
+- rb-gpios: GPIO specifier for the busy pin.
+- wp-gpios: GPIO specifier for the write protect pin.
+
+Example:
+
+nemc: nemc@1341 {
+ ...
+
+ nand: nand@1 {
+ compatible = "ingenic,jz4780-nand";
+ reg = <1 0 0x100>; /* Bank 1 */
+
+ ingenic,bch-controller = <&bch>;
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+
+ rb-gpios = <&gpa 20 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpf 22 GPIO_ACTIVE_LOW>;
+ };
+};
+
+The BCH controller is a separate SoC component used for error correction on
+NAND devices. The following is a description of the device properties for a
+BCH controller.
+
+Required BCH properties:
+- compatible: Should be set to "ingenic,jz4780-bch".
+- reg: Should specify the BCH controller registers location and length.
+- clocks: Clock for the BCH controller.
+
+Example:
+
+bch: bch@134d {
+ compatible = "ingenic,jz4780-bch";
+ reg = <0x134d 0x1>;
+
+ clocks = <&cgu JZ4780_CLK_BCH>;
+};
--
2.6.0
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[PATCH v7,2/3] mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs
From: Alex Smith Add a driver for NAND devices connected to the NEMC on JZ4780 SoCs, as well as the hardware BCH controller. DMA is not currently implemented. While older 47xx SoCs also have a BCH controller, they are incompatible with the one in the 4780 due to differing register/bit positions, which would make implementing a common driver for them quite messy. Signed-off-by: Alex Smith Reviewed-by: Ezequiel Garcia Cc: Zubair Lutfullah Kakakhel Cc: David Woodhouse Cc: Brian Norris Cc: linux-...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: Alex Smith Signed-off-by: Harvey Hunt --- v6 -> v7: - Include linux/bitops.h. - Default ECC mode to hw. - Only check BCH if we're using hw ECC mode. - Return -ENODEV if we're using hw ECC mode and can't find BCH. - Return -ENODEV if we can't find any banks. - Use set nand_chip->dn so we can use nand_dt_init() to read DT. v5 -> v6: - Remove another printk made useless by changes in v5 (due to devm_ioremap_resource() printing errors itself). v4 -> v5: - Bump RB_DELAY up to be sufficient for the driver to work without a busy GPIO available. - Use readl_poll_timeout instead of custom polling loop. - Remove useless printks. - Change a BUG_ON to WARN_ON. - Remove use of of_translate_address(), use standard platform resource APIs. - Add DRV_NAME define to avoid duplication of the same string. v3 -> v4: - Rebase to 4.2-rc4 - Change ECC_HW_OOB_FIRST to ECC_HW, reading OOB first is not necessary. - Fix argument to get_device() in jz4780_bch_get() v2 -> v3: - Rebase to 4.0-rc6 - Reflect binding changes - get/put_device in bch get/release - Removed empty .remove() callback - Removed .owner - Set mtd->dev.parent v1 -> v2: - Fixed module license macro - Rebase to 4.0-rc3 drivers/mtd/nand/Kconfig | 7 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/jz4780_bch.c | 349 + drivers/mtd/nand/jz4780_bch.h | 42 + drivers/mtd/nand/jz4780_nand.c | 384 + 5 files changed, 783 insertions(+) create mode 100644 drivers/mtd/nand/jz4780_bch.c create mode 100644 drivers/mtd/nand/jz4780_bch.h create mode 100644 drivers/mtd/nand/jz4780_nand.c diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 3324281..8ffd5cd 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -508,6 +508,13 @@ config MTD_NAND_JZ4740 help Enables support for NAND Flash on JZ4740 SoC based boards. +config MTD_NAND_JZ4780 + tristate "Support for NAND on JZ4780 SoC" + depends on MACH_JZ4780 && JZ4780_NEMC + help + Enables support for NAND Flash connected to the NEMC on JZ4780 SoC + based boards, using the BCH controller for hardware error correction. + config MTD_NAND_FSMC tristate "Support for NAND on ST Micros FSMC" depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300 diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 075a027..604b166 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_MTD_NAND_NUC900) += nuc900_nand.o obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o obj-$(CONFIG_MTD_NAND_RICOH) += r852.o obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o +obj-$(CONFIG_MTD_NAND_JZ4780) += jz4780_nand.o jz4780_bch.o obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ obj-$(CONFIG_MTD_NAND_XWAY)+= xway_nand.o obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ diff --git a/drivers/mtd/nand/jz4780_bch.c b/drivers/mtd/nand/jz4780_bch.c new file mode 100644 index 000..047d351 --- /dev/null +++ b/drivers/mtd/nand/jz4780_bch.c @@ -0,0 +1,349 @@ +/* + * JZ4780 BCH controller + * + * Copyright (c) 2015 Imagination Technologies + * Author: Alex Smith + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "jz4780_bch.h" + +#define BCH_BHCR 0x0 +#define BCH_BHCCR 0x8 +#define BCH_BHCNT 0xc +#define BCH_BHDR 0x10 +#define BCH_BHPAR0 0x14 +#define BCH_BHERR0 0x84 +#define BCH_BHINT 0x184 +#define BCH_BHINTES0x188 +#define BCH_BHINTEC0x18c +#define BCH_BHINTE 0x190 + +#define BCH_BHCR_BSEL_SHIFT4 +#define BCH_BHCR_BSEL_MASK (0x7f << BCH_BHCR_BSEL_SHIFT) +#define BCH_BHCR_ENCE BIT(2) +#define BCH_BHC
[PATCH v7,3/3] MIPS: dts: jz4780/ci20: Add NEMC, BCH and NAND device tree nodes
From: Alex Smith
Add device tree nodes for the NEMC and BCH to the JZ4780 device tree,
and make use of them in the Ci20 device tree to add a node for the
board's NAND.
Note that since the pinctrl driver is not yet upstream, this includes
neither pin configuration nor busy/write-protect GPIO pins for the
NAND. Use of the NAND relies on the boot loader to have left the pins
configured in a usable state, which should be the case when booted
from the NAND.
Signed-off-by: Alex Smith
Cc: Zubair Lutfullah Kakakhel
Cc: David Woodhouse
Cc: Brian Norris
Cc: Paul Burton
Cc: linux-...@lists.infradead.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-m...@linux-mips.org
Cc: Alex Smith
Signed-off-by: Harvey Hunt
---
v6 -> v7:
- Add nand-ecc-mode to DT.
- Add nand-on-flash-bbt to DT.
v4 -> v5:
- New patch adding DT nodes for the NAND so that the driver can be
tested.
arch/mips/boot/dts/ingenic/ci20.dts| 54 ++
arch/mips/boot/dts/ingenic/jz4780.dtsi | 26
2 files changed, 80 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
b/arch/mips/boot/dts/ingenic/ci20.dts
index 9fcb9e7..453f1d3 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -42,3 +42,57 @@
&uart4 {
status = "okay";
};
+
+&nemc {
+ status = "okay";
+
+ nand: nand@1 {
+ compatible = "ingenic,jz4780-nand";
+ reg = <1 0 0x100>;
+
+ ingenic,nemc-tAS = <10>;
+ ingenic,nemc-tAH = <5>;
+ ingenic,nemc-tBP = <10>;
+ ingenic,nemc-tAW = <15>;
+ ingenic,nemc-tSTRV = <100>;
+
+ ingenic,bch-controller = <&bch>;
+ ingenic,ecc-size = <1024>;
+ ingenic,ecc-strength = <24>;
+
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x0 0x0 0x80>;
+ };
+
+ partition@0x80 {
+ label = "u-boot";
+ reg = <0x0 0x80 0x0 0x20>;
+ };
+
+ partition@0xa0 {
+ label = "u-boot-env";
+ reg = <0x0 0xa0 0x0 0x20>;
+ };
+
+ partition@0xc0 {
+ label = "boot";
+ reg = <0x0 0xc0 0x0 0x400>;
+ };
+
+ partition@0x8c0 {
+ label = "system";
+ reg = <0x0 0x4c0 0x1 0xfb40>;
+ };
+ };
+};
+
+&bch {
+ status = "okay";
+};
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index 65389f6..b868b42 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -108,4 +108,30 @@
status = "disabled";
};
+
+ nemc: nemc@1341 {
+ compatible = "ingenic,jz4780-nemc";
+ reg = <0x1341 0x1>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0x1b00 0x100
+ 2 0 0x1a00 0x100
+ 3 0 0x1900 0x100
+ 4 0 0x1800 0x100
+ 5 0 0x1700 0x100
+ 6 0 0x1600 0x100>;
+
+ clocks = <&cgu JZ4780_CLK_NEMC>;
+
+ status = "disabled";
+ };
+
+ bch: bch@134d {
+ compatible = "ingenic,jz4780-bch";
+ reg = <0x134d 0x1>;
+
+ clocks = <&cgu JZ4780_CLK_BCH>;
+
+ status = "disabled";
+ };
};
--
2.6.0
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RE: [PATCH v7,3/3] MIPS: dts: jz4780/ci20: Add NEMC, BCH and NAND device tree nodes
On 8 October 2015 at 22:23, Ezequiel Garcia < ezequ...@vanguardiasur.com.ar>
wrote:
>On 6 October 2015 at 13:27, Harvey Hunt wrote:
>> From: Alex Smith
>>
>> Add device tree nodes for the NEMC and BCH to the JZ4780 device tree,
>> and make use of them in the Ci20 device tree to add a node for the
>> board's NAND.
>>
>> Note that since the pinctrl driver is not yet upstream, this includes
>> neither pin configuration nor busy/write-protect GPIO pins for the
>> NAND. Use of the NAND relies on the boot loader to have left the pins
>> configured in a usable state, which should be the case when booted
>> from the NAND.
>>
>> Signed-off-by: Alex Smith
>> Cc: Zubair Lutfullah Kakakhel
>> Cc: David Woodhouse
>> Cc: Brian Norris
>> Cc: Paul Burton
>> Cc: linux-...@lists.infradead.org
>> Cc: devicet...@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Cc: linux-m...@linux-mips.org
>> Cc: Alex Smith
>> Signed-off-by: Harvey Hunt
>> ---
>> v6 -> v7:
>> - Add nand-ecc-mode to DT.
>> - Add nand-on-flash-bbt to DT.
>>
>> v4 -> v5:
>> - New patch adding DT nodes for the NAND so that the driver can be
>>tested.
>>
>> arch/mips/boot/dts/ingenic/ci20.dts| 54
>> ++
>> arch/mips/boot/dts/ingenic/jz4780.dtsi | 26
>> 2 files changed, 80 insertions(+)
>>
>> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
>> b/arch/mips/boot/dts/ingenic/ci20.dts
>> index 9fcb9e7..453f1d3 100644
>> --- a/arch/mips/boot/dts/ingenic/ci20.dts
>> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
>> @@ -42,3 +42,57 @@
>> &uart4 {
>> status = "okay";
>> };
>> +
>> +&nemc {
>> + status = "okay";
>> +
>> + nand: nand@1 {
>> + compatible = "ingenic,jz4780-nand";
>> + reg = <1 0 0x100>;
>> +
>
>Why is this in the ci20.dts instead of the SoC dtsi?
>
>Seems at least compatible and reg is not board-specific.
>
>Thanks,
>--
>Ezequiel García, VanguardiaSur
>www.vanguardiasur.com.ar
Hi Ezequiel,
The number of NAND nodes under the NEMC node is board specific - some devices
could have 2 NAND banks and others could have none. Including the compatible
property in jz4780.dtsi would imply that all JZ4780 boards have at least one
NAND bank.
The size in the reg property would be the same for all NAND devices (as it
refers to the
NAND registers), however the bank number would be different, so that can also
be seen
as board specific.
Thanks,
Harvey
[PATCH v2] clk: ingenic: Allow divider value to be divided
The JZ4780's MSC clock divider registers multiply the clock divider by 2.
This means that MMC devices run at half their expected speed. Add the
ability to divide the clock divider in order to solve this.
Signed-off-by: Harvey Hunt
Cc: Paul Burton
Cc: Ralf Baechle
Cc: linux-...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
v1 -> v2:
- Replace right shift with division
- Update commit title
- Correctly update HDMI CDR
v1 can be found here:
https://lkml.org/lkml/2015/12/24/68
drivers/clk/ingenic/cgu.c| 11 ++-
drivers/clk/ingenic/cgu.h| 6 +-
drivers/clk/ingenic/jz4740-cgu.c | 24
drivers/clk/ingenic/jz4780-cgu.c | 40
4 files changed, 47 insertions(+), 34 deletions(-)
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index 7cfb7b2..e8248f9 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -325,6 +325,7 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long
parent_rate)
div = (div_reg >> clk_info->div.shift) &
GENMASK(clk_info->div.bits - 1, 0);
div += 1;
+ div *= clk_info->div.div;
rate /= div;
}
@@ -345,6 +346,14 @@ ingenic_clk_calc_div(const struct ingenic_cgu_clk_info
*clk_info,
div = min_t(unsigned, div, 1 << clk_info->div.bits);
div = max_t(unsigned, div, 1);
+ /*
+* If the divider value itself must be divided before being written to
+* the divider register, we must ensure we don't have any bits set that
+* would be lost as a result of doing so.
+*/
+ div /= clk_info->div.div;
+ div *= clk_info->div.div;
+
return div;
}
@@ -395,7 +404,7 @@ ingenic_clk_set_rate(struct clk_hw *hw, unsigned long
req_rate,
/* update the divide */
mask = GENMASK(clk_info->div.bits - 1, 0);
reg &= ~(mask << clk_info->div.shift);
- reg |= (div - 1) << clk_info->div.shift;
+ reg |= ((div / clk_info->div.div) - 1) << clk_info->div.shift;
/* clear the stop bit */
if (clk_info->div.stop_bit != -1)
diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h
index 99347e2..09700b2 100644
--- a/drivers/clk/ingenic/cgu.h
+++ b/drivers/clk/ingenic/cgu.h
@@ -76,8 +76,11 @@ struct ingenic_cgu_mux_info {
/**
* struct ingenic_cgu_div_info - information about a divider
* @reg: offset of the divider control register within the CGU
- * @shift: number of bits to shift the divide value by (ie. the index of
+ * @shift: number of bits to left shift the divide value by (ie. the index of
* the lowest bit of the divide value within its control register)
+ * @div: number of bits to divide the divider value by (i.e. if the
+ * effective divider value is the value written to the register
+ * multiplied by some constant)
* @bits: the size of the divide value in bits
* @ce_bit: the index of the change enable bit within reg, or -1 if there
* isn't one
@@ -87,6 +90,7 @@ struct ingenic_cgu_mux_info {
struct ingenic_cgu_div_info {
unsigned reg;
u8 shift;
+ u8 div;
u8 bits;
s8 ce_bit;
s8 busy_bit;
diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index 305a26c2..510fe7e 100644
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -90,51 +90,51 @@ static const struct ingenic_cgu_clk_info
jz4740_cgu_clocks[] = {
[JZ4740_CLK_PLL_HALF] = {
"pll half", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
- .div = { CGU_REG_CPCCR, 21, 1, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 },
},
[JZ4740_CLK_CCLK] = {
"cclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
- .div = { CGU_REG_CPCCR, 0, 4, 22, -1, -1 },
+ .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
},
[JZ4740_CLK_HCLK] = {
"hclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
- .div = { CGU_REG_CPCCR, 4, 4, 22, -1, -1 },
+ .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
},
[JZ4740_CLK_PCLK] = {
"pclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
- .div = { CGU_REG_CPCCR, 8, 4, 22, -1, -1 },
+ .div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1 },
},
[JZ4740_CLK_MCLK] = {
"mclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
- .div = { CGU_REG_CPCCR, 12, 4
[PATCH net] drivers: net: Don't print unpopulated net_device name
For ethernet devices, net_device.name will be eth%d before
register_netdev() is called. Don't print the net_device name until
the format string is replaced.
Cc: Robert Jarzmik
Cc: Barry Song
Cc: Marcel Ziswiler
Cc: net...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Harvey Hunt
---
I've tested this patch on a board that has a DM9000, but haven't
tested the other two network devices.
drivers/net/ethernet/davicom/dm9000.c | 3 +--
drivers/net/ethernet/micrel/ks8695net.c | 3 +--
drivers/net/ethernet/netx-eth.c | 3 +--
3 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/davicom/dm9000.c
b/drivers/net/ethernet/davicom/dm9000.c
index 48d9194..89dcaa1 100644
--- a/drivers/net/ethernet/davicom/dm9000.c
+++ b/drivers/net/ethernet/davicom/dm9000.c
@@ -1686,8 +1686,7 @@ dm9000_probe(struct platform_device *pdev)
}
if (!is_valid_ether_addr(ndev->dev_addr)) {
- dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please "
-"set using ifconfig\n", ndev->name);
+ dev_warn(db->dev, "Invalid ethernet MAC address. Please set
using ifconfig\n");
eth_hw_addr_random(ndev);
mac_src = "random";
diff --git a/drivers/net/ethernet/micrel/ks8695net.c
b/drivers/net/ethernet/micrel/ks8695net.c
index a8522d8..2e2ea61 100644
--- a/drivers/net/ethernet/micrel/ks8695net.c
+++ b/drivers/net/ethernet/micrel/ks8695net.c
@@ -1456,8 +1456,7 @@ ks8695_probe(struct platform_device *pdev)
ndev->dev_addr[5] = maclow & 0xFF;
if (!is_valid_ether_addr(ndev->dev_addr))
- dev_warn(ksp->dev, "%s: Invalid ethernet MAC address. Please "
-"set using ifconfig\n", ndev->name);
+ dev_warn(ksp->dev, "Invalid ethernet MAC address. Please set
using ifconfig\n");
/* In order to be efficient memory-wise, we allocate both
* rings in one go.
diff --git a/drivers/net/ethernet/netx-eth.c b/drivers/net/ethernet/netx-eth.c
index 9fbc302..c2e2151 100644
--- a/drivers/net/ethernet/netx-eth.c
+++ b/drivers/net/ethernet/netx-eth.c
@@ -358,8 +358,7 @@ static int netx_eth_enable(struct net_device *ndev)
xc_start(priv->xc);
if (!is_valid_ether_addr(ndev->dev_addr))
- printk("%s: Invalid ethernet MAC address. Please "
- "set using ifconfig\n", ndev->name);
+ printk("Invalid ethernet MAC address. Please set using
ifconfig\n");
for (i=2; i<=18; i++)
pfifo_push(EMPTY_PTR_FIFO(priv->id),
--
2.8.0
Re: [PATCH net] drivers: net: Don't print unpopulated net_device name
Hi Stephen,
On 10/05/16 19:31, Stephen Hemminger wrote:
On Tue, 10 May 2016 17:43:21 +0100
Harvey Hunt wrote:
For ethernet devices, net_device.name will be eth%d before
register_netdev() is called. Don't print the net_device name until
the format string is replaced.
Cc: Robert Jarzmik
Cc: Barry Song
Cc: Marcel Ziswiler
Cc: net...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Harvey Hunt
---
I've tested this patch on a board that has a DM9000, but haven't
tested the other two network devices.
drivers/net/ethernet/davicom/dm9000.c | 3 +--
drivers/net/ethernet/micrel/ks8695net.c | 3 +--
drivers/net/ethernet/netx-eth.c | 3 +--
3 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/davicom/dm9000.c
b/drivers/net/ethernet/davicom/dm9000.c
index 48d9194..89dcaa1 100644
--- a/drivers/net/ethernet/davicom/dm9000.c
+++ b/drivers/net/ethernet/davicom/dm9000.c
@@ -1686,8 +1686,7 @@ dm9000_probe(struct platform_device *pdev)
}
if (!is_valid_ether_addr(ndev->dev_addr)) {
- dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please "
-"set using ifconfig\n", ndev->name);
+ dev_warn(db->dev, "Invalid ethernet MAC address. Please set using
ifconfig\n");
ifconfig is deprecated, therefore please don't tell users to use it.
I'll update it to print "Please set using ip".
Thanks,
Harvey
Re: [PATCH net] drivers: net: Don't print unpopulated net_device name
Hi David,
On 12/05/16 00:26, David Miller wrote:
From: Harvey Hunt
Date: Tue, 10 May 2016 17:43:21 +0100
@@ -1686,8 +1686,7 @@ dm9000_probe(struct platform_device *pdev)
}
if (!is_valid_ether_addr(ndev->dev_addr)) {
- dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please "
-"set using ifconfig\n", ndev->name);
+ dev_warn(db->dev, "Invalid ethernet MAC address. Please set using
ifconfig\n");
eth_hw_addr_random(ndev);
mac_src = "random";
If we don't print the netdev name, it's harder for the user to see which
adapter has the problem.
Therefore, it is better if you save some boolean state into a local variable
here, then print the warning right after register_netdev().
Likewise for the rest of your changes too.
Okay, I'll do that for v2.
Thanks,
Harvey
[PATCH] irqchip/mips-gic: Fix IRQs in gic_dev_domain
When allocating a new device IRQ, gic_dev_domain_alloc() correctly calls
irq_domain_set_hwirq_and_chip(), but gic_irq_domain_alloc() does not. This
means that gic_irq_domain believes all IRQs from the dev domain have an
hwirq of 0 and creates incorrect mappings in the linear_revmap. As
gic_irq_domain is a parent of the gic_dev_domain, this leads to an
inability to boot on devices with a GIC. Excerpt of the error:
[2.297649] irq 0: nobody cared (try booting with the "irqpoll" option)
...
[2.436963] handlers:
[2.439492] Disabling IRQ #0
Fix this by calling irq_domain_set_hwirq_and_chip() for both the dev and
irq domain.
Now that we are modifying the parent domain, be sure to clear it up in
case of an allocation error.
Fixes: c98c1822ee13 ("irqchip/mips-gic: Add device hierarchy domain")
Fixes: 2af70a962070 ("irqchip/mips-gic: Add a IPI hierarchy domain")
Signed-off-by: Harvey Hunt
Tested-by: Govindraj Raja # On Pistachio SoC
Reviewed-by: Matt Redfearn
Cc:
Cc:
Cc: Qais Yousef
---
drivers/irqchip/irq-mips-gic.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 4dffccf..40fb120 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -734,6 +734,12 @@ static int gic_irq_domain_alloc(struct irq_domain *d,
unsigned int virq,
/* verify that it doesn't conflict with an IPI irq */
if (test_bit(spec->hwirq, ipi_resrv))
return -EBUSY;
+
+ hwirq = GIC_SHARED_TO_HWIRQ(spec->hwirq);
+
+ return irq_domain_set_hwirq_and_chip(d, virq, hwirq,
+&gic_level_irq_controller,
+NULL);
} else {
base_hwirq = find_first_bit(ipi_resrv, gic_shared_intrs);
if (base_hwirq == gic_shared_intrs) {
@@ -855,10 +861,14 @@ static int gic_dev_domain_alloc(struct irq_domain *d,
unsigned int virq,
&gic_level_irq_controller,
NULL);
if (ret)
- return ret;
+ goto error;
}
return 0;
+
+error:
+ irq_domain_free_irqs_parent(d, virq, nr_irqs);
+ return ret;
}
void gic_dev_domain_free(struct irq_domain *d, unsigned int virq,
--
2.8.2
[PATCH] irqchip/mips-gic: Populate irq_domain names
Set the irq_domain names so that they don't default to an unhelpful
value.
Signed-off-by: Harvey Hunt
Reviewed-by: Matt Redfearn
Cc:
Cc:
Cc: Qais Yousef
---
drivers/irqchip/irq-mips-gic.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 40fb120..22a4a6d 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -1022,12 +1022,14 @@ static void __init __gic_init(unsigned long
gic_base_addr,
&gic_irq_domain_ops, NULL);
if (!gic_irq_domain)
panic("Failed to add GIC IRQ domain");
+ gic_irq_domain->name = "mips-gic-irq";
gic_dev_domain = irq_domain_add_hierarchy(gic_irq_domain, 0,
GIC_NUM_LOCAL_INTRS +
gic_shared_intrs,
node, &gic_dev_domain_ops,
NULL);
if (!gic_dev_domain)
panic("Failed to add GIC DEV domain");
+ gic_dev_domain->name = "mips-gic-dev";
gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
IRQ_DOMAIN_FLAG_IPI_PER_CPU,
@@ -1036,6 +1038,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
if (!gic_ipi_domain)
panic("Failed to add GIC IPI domain");
+ gic_ipi_domain->name = "mips-gic-ipi";
gic_ipi_domain->bus_token = DOMAIN_BUS_IPI;
if (node &&
--
2.8.2
[PATCH v2 net] drivers: net: Don't print unpopulated net_device name
For ethernet devices, net_device.name will be eth%d before
register_netdev() is called. Don't print the net_device name until
the format string is replaced.
Signed-off-by: Harvey Hunt
Cc: Marcel Ziswiler
Cc: Robert Jarzmik
Cc: Barry Song
Cc: net...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
v1 -> v2:
- Replace ifconfig with ip
- Delay printk until the netdev name is known
Tested on a board with a DM9000 and compile tested for the other two
platforms.
drivers/net/ethernet/davicom/dm9000.c | 11 +++
drivers/net/ethernet/micrel/ks8695net.c | 7 +--
drivers/net/ethernet/netx-eth.c | 12
3 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/davicom/dm9000.c
b/drivers/net/ethernet/davicom/dm9000.c
index 48d9194..161274b 100644
--- a/drivers/net/ethernet/davicom/dm9000.c
+++ b/drivers/net/ethernet/davicom/dm9000.c
@@ -1432,6 +1432,7 @@ dm9000_probe(struct platform_device *pdev)
int reset_gpios;
enum of_gpio_flags flags;
struct regulator *power;
+ bool inv_mac_addr = false;
power = devm_regulator_get(dev, "vcc");
if (IS_ERR(power)) {
@@ -1686,9 +1687,7 @@ dm9000_probe(struct platform_device *pdev)
}
if (!is_valid_ether_addr(ndev->dev_addr)) {
- dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please "
-"set using ifconfig\n", ndev->name);
-
+ inv_mac_addr = true;
eth_hw_addr_random(ndev);
mac_src = "random";
}
@@ -1697,11 +1696,15 @@ dm9000_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, ndev);
ret = register_netdev(ndev);
- if (ret == 0)
+ if (ret == 0) {
+ if (inv_mac_addr)
+ dev_warn(db->dev, "%s: Invalid ethernet MAC address.
Please set using ip\n",
+ndev->name);
printk(KERN_INFO "%s: dm9000%c at %p,%p IRQ %d MAC: %pM (%s)\n",
ndev->name, dm9000_type_to_char(db->type),
db->io_addr, db->io_data, ndev->irq,
ndev->dev_addr, mac_src);
+ }
return 0;
out:
diff --git a/drivers/net/ethernet/micrel/ks8695net.c
b/drivers/net/ethernet/micrel/ks8695net.c
index a8522d8..20cb85b 100644
--- a/drivers/net/ethernet/micrel/ks8695net.c
+++ b/drivers/net/ethernet/micrel/ks8695net.c
@@ -1354,6 +1354,7 @@ ks8695_probe(struct platform_device *pdev)
struct resource *rxirq_res, *txirq_res, *linkirq_res;
int ret = 0;
int buff_n;
+ bool inv_mac_addr = false;
u32 machigh, maclow;
/* Initialise a net_device */
@@ -1456,8 +1457,7 @@ ks8695_probe(struct platform_device *pdev)
ndev->dev_addr[5] = maclow & 0xFF;
if (!is_valid_ether_addr(ndev->dev_addr))
- dev_warn(ksp->dev, "%s: Invalid ethernet MAC address. Please "
-"set using ifconfig\n", ndev->name);
+ inv_mac_addr = true;
/* In order to be efficient memory-wise, we allocate both
* rings in one go.
@@ -1520,6 +1520,9 @@ ks8695_probe(struct platform_device *pdev)
ret = register_netdev(ndev);
if (ret == 0) {
+ if (inv_mac_addr)
+ dev_warn(ksp->dev, "%s: Invalid ethernet MAC address.
Please set using ip\n",
+ndev->name);
dev_info(ksp->dev, "ks8695 ethernet (%s) MAC: %pM\n",
ks8695_port_type(ksp), ndev->dev_addr);
} else {
diff --git a/drivers/net/ethernet/netx-eth.c b/drivers/net/ethernet/netx-eth.c
index 9fbc302..adbc47f 100644
--- a/drivers/net/ethernet/netx-eth.c
+++ b/drivers/net/ethernet/netx-eth.c
@@ -313,7 +313,8 @@ static int netx_eth_enable(struct net_device *ndev)
{
struct netx_eth_priv *priv = netdev_priv(ndev);
unsigned int mac4321, mac65;
- int running, i;
+ int running, i, ret;
+ bool inv_mac_addr = false;
ndev->netdev_ops = &netx_eth_netdev_ops;
ndev->watchdog_timeo = msecs_to_jiffies(5000);
@@ -358,15 +359,18 @@ static int netx_eth_enable(struct net_device *ndev)
xc_start(priv->xc);
if (!is_valid_ether_addr(ndev->dev_addr))
- printk("%s: Invalid ethernet MAC address. Please "
- "set using ifconfig\n", ndev->name);
+ inv_mac_addr = true;
for (i=2; i<=18; i++)
pfifo_push(EMPTY_PTR_FIFO(priv->id),
FIFO_PTR_FRAMENO(i) | FIFO_PTR_SEGMENT(priv->id));
- return register_netdev(ndev);
+ ret = register_netdev(ndev);
+ if (inv_mac_addr)
+ printk("%s: Invalid ethernet MAC address. Please set using
ip\n",
+ ndev->name);
+ return ret;
}
static int netx_eth_drv_probe(struct platform_device *pdev)
--
2.8.2
[PATCH] MIPS: lib: Mark intrinsics notrace
On certain MIPS32 devices, the ftrace tracer "function_graph" uses
__lshrdi3() during the capturing of trace data. ftrace then attempts to
trace __lshrdi3() which leads to infinite recursion and a stack overflow.
Fix this by marking __lshrdi3() as notrace. Mark the other compiler
intrinsics as notrace in case the compiler decides to use them in the
ftrace path.
Signed-off-by: Harvey Hunt
Cc:
Cc:
Cc: # 4.2.x-
---
I've only been able to test this patch as far back as 4.2, although
the issue could have existed before then.
arch/mips/lib/ashldi3.c | 2 +-
arch/mips/lib/ashrdi3.c | 2 +-
arch/mips/lib/bswapdi.c | 2 +-
arch/mips/lib/bswapsi.c | 2 +-
arch/mips/lib/cmpdi2.c | 2 +-
arch/mips/lib/lshrdi3.c | 2 +-
arch/mips/lib/ucmpdi2.c | 2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/mips/lib/ashldi3.c b/arch/mips/lib/ashldi3.c
index beb80f31..927dc94 100644
--- a/arch/mips/lib/ashldi3.c
+++ b/arch/mips/lib/ashldi3.c
@@ -2,7 +2,7 @@
#include "libgcc.h"
-long long __ashldi3(long long u, word_type b)
+long long notrace __ashldi3(long long u, word_type b)
{
DWunion uu, w;
word_type bm;
diff --git a/arch/mips/lib/ashrdi3.c b/arch/mips/lib/ashrdi3.c
index c884a91..9fdf1a5 100644
--- a/arch/mips/lib/ashrdi3.c
+++ b/arch/mips/lib/ashrdi3.c
@@ -2,7 +2,7 @@
#include "libgcc.h"
-long long __ashrdi3(long long u, word_type b)
+long long notrace __ashrdi3(long long u, word_type b)
{
DWunion uu, w;
word_type bm;
diff --git a/arch/mips/lib/bswapdi.c b/arch/mips/lib/bswapdi.c
index 77e5f9c..e3e77aa 100644
--- a/arch/mips/lib/bswapdi.c
+++ b/arch/mips/lib/bswapdi.c
@@ -1,6 +1,6 @@
#include
-unsigned long long __bswapdi2(unsigned long long u)
+unsigned long long notrace __bswapdi2(unsigned long long u)
{
return (((u) & 0xff00ull) >> 56) |
(((u) & 0x00ffull) >> 40) |
diff --git a/arch/mips/lib/bswapsi.c b/arch/mips/lib/bswapsi.c
index 2b302ff..530a8af 100644
--- a/arch/mips/lib/bswapsi.c
+++ b/arch/mips/lib/bswapsi.c
@@ -1,6 +1,6 @@
#include
-unsigned int __bswapsi2(unsigned int u)
+unsigned int notrace __bswapsi2(unsigned int u)
{
return (((u) & 0xff00) >> 24) |
(((u) & 0x00ff) >> 8) |
diff --git a/arch/mips/lib/cmpdi2.c b/arch/mips/lib/cmpdi2.c
index 8c13064..06857da 100644
--- a/arch/mips/lib/cmpdi2.c
+++ b/arch/mips/lib/cmpdi2.c
@@ -2,7 +2,7 @@
#include "libgcc.h"
-word_type __cmpdi2(long long a, long long b)
+word_type notrace __cmpdi2(long long a, long long b)
{
const DWunion au = {
.ll = a
diff --git a/arch/mips/lib/lshrdi3.c b/arch/mips/lib/lshrdi3.c
index dcf8d68..3645474 100644
--- a/arch/mips/lib/lshrdi3.c
+++ b/arch/mips/lib/lshrdi3.c
@@ -2,7 +2,7 @@
#include "libgcc.h"
-long long __lshrdi3(long long u, word_type b)
+long long notrace __lshrdi3(long long u, word_type b)
{
DWunion uu, w;
word_type bm;
diff --git a/arch/mips/lib/ucmpdi2.c b/arch/mips/lib/ucmpdi2.c
index bb4cb2f..bd599f5 100644
--- a/arch/mips/lib/ucmpdi2.c
+++ b/arch/mips/lib/ucmpdi2.c
@@ -2,7 +2,7 @@
#include "libgcc.h"
-word_type __ucmpdi2(unsigned long long a, unsigned long long b)
+word_type notrace __ucmpdi2(unsigned long long a, unsigned long long b)
{
const DWunion au = {.ll = a};
const DWunion bu = {.ll = b};
--
2.8.3
Re: [PATCH 03/11] MIPS: pic32mzda: fix getting timer clock rate.
Hi Purna,
On 17/05/16 06:05, Purna Chandra Mandal wrote:
PIC32 clock driver is now implemented as platform driver instead of
as part of of_clk_init(). It meants all the clock modules are available
quite late in the boot sequence. So request for CPU clock by clk_get_sys()
and clk_get_rate() to find c0_timer rate fails.
To fix this use PIC32 specific early clock functions implemented for early
console support.
Signed-off-by: Purna Chandra Mandal
---
Note: Please pull this complete series through the MIPS tree.
---
arch/mips/pic32/pic32mzda/time.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/mips/pic32/pic32mzda/time.c b/arch/mips/pic32/pic32mzda/time.c
index ca6a62b..62a0a78 100644
--- a/arch/mips/pic32/pic32mzda/time.c
+++ b/arch/mips/pic32/pic32mzda/time.c
@@ -11,13 +11,12 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
-#include
#include
#include
#include
+#include
#include
#include
-#include
#include
@@ -58,16 +57,12 @@ unsigned int get_c0_compare_int(void)
void __init plat_time_init(void)
{
- struct clk *clk;
+ unsigned long rate = pic32_get_pbclk(7);
pic32_get_pbclk() is defined in arch/mips/pic32/pic32mzda/early_clk.c.
When CONFIG_EARLY_PRINTK isn't set, early_clk.c isn't compiled and so a
linker error occurs.
Maybe it's best to always build the early_clk.c file, or perhaps there
is a better place to put pic32_get_pbclk()?
Thanks,
Harvey
Re: [PATCH v9 2/3] mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs
Hi Boris,
That's fine - I hope to get a new version ready soon.
Thanks,
Harvey
On 14/12/15 16:25, Boris Brezillon wrote:
Hi Harvey,
I'm currently reworking the NAND subsystem to simplify NAND controller
drivers (see this series [1]), and some of my patches have made it into
Brian's tree.
Would you mind adapting your driver as described below so that I don't
have to do it when it gets applied into l2-mtd/master?
On Thu, 3 Dec 2015 12:02:21 +
Harvey Hunt wrote:
From: Alex Smith
Add a driver for NAND devices connected to the NEMC on JZ4780 SoCs, as
well as the hardware BCH controller. DMA is not currently implemented.
While older 47xx SoCs also have a BCH controller, they are incompatible
with the one in the 4780 due to differing register/bit positions, which
would make implementing a common driver for them quite messy.
Signed-off-by: Alex Smith
Cc: Zubair Lutfullah Kakakhel
Cc: David Woodhouse
Cc: Brian Norris
Cc: linux-...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Harvey Hunt
---
v8 -> v9:
- No change.
v7 -> v8:
- Rebase to 4.4-rc3.
- Add _US suffixes to time constants.
- Add locking to BCH hardware accesses.
- Don't print ECC info if ECC is not being used.
- Default to No ECC.
- Let the NAND core handle ECC layout in certain cases.
- Use the gpio_desc consumer interface.
- Removed gpio active low flags.
- Check for the BCH controller before initialising a chip.
- Add a jz4780_nand_controller struct.
- Initialise chips by iterating over DT child nodes.
v6 -> v7:
- Add nand-ecc-mode to DT bindings.
- Add nand-on-flash-bbt to DT bindings.
v5 -> v6:
- No change.
v4 -> v5:
- Rename ingenic,bch-device to ingenic,bch-controller to fit with
existing convention.
v3 -> v4:
- No change
v2 -> v3:
- Rebase to 4.0-rc6
- Changed ingenic,ecc-size to common nand-ecc-step-size
- Changed ingenic,ecc-strength to common nand-ecc-strength
- Changed ingenic,busy-gpio to common rb-gpios
- Changed ingenic,wp-gpio to common wp-gpios
v1 -> v2:
- Rebase to 4.0-rc3
drivers/mtd/nand/Kconfig | 7 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/jz4780_bch.c | 361 +++
drivers/mtd/nand/jz4780_bch.h | 42 +
drivers/mtd/nand/jz4780_nand.c | 420 +
5 files changed, 831 insertions(+)
create mode 100644 drivers/mtd/nand/jz4780_bch.c
create mode 100644 drivers/mtd/nand/jz4780_bch.h
create mode 100644 drivers/mtd/nand/jz4780_nand.c
[...]
diff --git a/drivers/mtd/nand/jz4780_nand.c b/drivers/mtd/nand/jz4780_nand.c
new file mode 100644
index 000..b4d0acb
--- /dev/null
+++ b/drivers/mtd/nand/jz4780_nand.c
@@ -0,0 +1,420 @@
+/*
+ * JZ4780 NAND driver
+ *
+ * Copyright (c) 2015 Imagination Technologies
+ * Author: Alex Smith
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "jz4780_bch.h"
+
+#define DRV_NAME "jz4780-nand"
+
+#define OFFSET_DATA0x
+#define OFFSET_CMD 0x0040
+#define OFFSET_ADDR0x0080
+
+/* Command delay when there is no R/B pin. */
+#define RB_DELAY_US100
+
+struct jz4780_nand_cs {
+ unsigned int bank;
+ void __iomem *base;
+};
+
+struct jz4780_nand_controller {
+ struct device *dev;
+ struct device *bch;
+ struct nand_hw_control controller;
+ unsigned int num_banks;
+ struct list_head chips;
+ int selected;
+ struct jz4780_nand_cs cs[];
+};
+
+struct jz4780_nand_chip {
+ struct mtd_info mtd;
You can drop the mtd field, since nand_chip now embeds its own mtd
instance. This implies doing the following changes...
+ struct nand_chip chip;
+ struct list_head chip_list;
+
+ struct nand_ecclayout ecclayout;
+
+ struct gpio_desc *busy_gpio;
+ struct gpio_desc *wp_gpio;
+ unsigned int reading: 1;
+};
+
+static inline struct jz4780_nand_chip *to_jz4780_nand_chip(struct mtd_info
*mtd)
+{
+ return container_of(mtd, struct jz4780_nand_chip, mtd);
return container_of(mtd_to_nand(mtd), struct jz4780_nand_chip,
chip);
+}
+
[...]
+static int jz4780_nand_ecc_correct(struct mtd_info *mtd, uint8_t *dat,
+ uint8_t *read_ecc, uint8_t *calc_ecc)
+{
+ struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
+ struct jz4780_nand_controller *nfc =
to_jz4780_nand_controller(nand->chip.controller);
+ struct jz4780_bch_params params;
+
+ params.size = nand->chip.ecc.size;
+ params.byte
[PATCH v8 2/3] mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs
From: Alex Smith Add a driver for NAND devices connected to the NEMC on JZ4780 SoCs, as well as the hardware BCH controller. DMA is not currently implemented. While older 47xx SoCs also have a BCH controller, they are incompatible with the one in the 4780 due to differing register/bit positions, which would make implementing a common driver for them quite messy. Signed-off-by: Alex Smith Cc: Zubair Lutfullah Kakakhel Cc: David Woodhouse Cc: Brian Norris Cc: linux-...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: Alex Smith Signed-off-by: Harvey Hunt --- v7 -> v8: - Rebase to 4.4-rc3. - Add _US suffixes to time constants. - Add locking to BCH hardware accesses. - Don't print ECC info if ECC is not being used. - Default to No ECC. - Let the NAND core handle ECC layout in certain cases. - Use the gpio_desc consumer interface. - Removed gpio active low flags. - Check for the BCH controller before initialising a chip. - Add a jz4780_nand_controller struct. - Initialise chips by iterating over DT child nodes. v6 -> v7: - Add nand-ecc-mode to DT bindings. - Add nand-on-flash-bbt to DT bindings. v5 -> v6: - No change. v4 -> v5: - Rename ingenic,bch-device to ingenic,bch-controller to fit with existing convention. v3 -> v4: - No change v2 -> v3: - Rebase to 4.0-rc6 - Changed ingenic,ecc-size to common nand-ecc-step-size - Changed ingenic,ecc-strength to common nand-ecc-strength - Changed ingenic,busy-gpio to common rb-gpios - Changed ingenic,wp-gpio to common wp-gpios v1 -> v2: - Rebase to 4.0-rc3 drivers/mtd/nand/Kconfig | 7 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/jz4780_bch.c | 361 +++ drivers/mtd/nand/jz4780_bch.h | 42 + drivers/mtd/nand/jz4780_nand.c | 420 + 5 files changed, 831 insertions(+) create mode 100644 drivers/mtd/nand/jz4780_bch.c create mode 100644 drivers/mtd/nand/jz4780_bch.h create mode 100644 drivers/mtd/nand/jz4780_nand.c diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 2896640..b742adc 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -519,6 +519,13 @@ config MTD_NAND_JZ4740 help Enables support for NAND Flash on JZ4740 SoC based boards. +config MTD_NAND_JZ4780 + tristate "Support for NAND on JZ4780 SoC" + depends on MACH_JZ4780 && JZ4780_NEMC + help + Enables support for NAND Flash connected to the NEMC on JZ4780 SoC + based boards, using the BCH controller for hardware error correction. + config MTD_NAND_FSMC tristate "Support for NAND on ST Micros FSMC" depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300 diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 2c7f014..9e36233 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC)+= mpc5121_nfc.o obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o obj-$(CONFIG_MTD_NAND_RICOH) += r852.o obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o +obj-$(CONFIG_MTD_NAND_JZ4780) += jz4780_nand.o jz4780_bch.o obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ obj-$(CONFIG_MTD_NAND_XWAY)+= xway_nand.o obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ diff --git a/drivers/mtd/nand/jz4780_bch.c b/drivers/mtd/nand/jz4780_bch.c new file mode 100644 index 000..0c472f4 --- /dev/null +++ b/drivers/mtd/nand/jz4780_bch.c @@ -0,0 +1,361 @@ +/* + * JZ4780 BCH controller + * + * Copyright (c) 2015 Imagination Technologies + * Author: Alex Smith + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "jz4780_bch.h" + +#define BCH_BHCR 0x0 +#define BCH_BHCCR 0x8 +#define BCH_BHCNT 0xc +#define BCH_BHDR 0x10 +#define BCH_BHPAR0 0x14 +#define BCH_BHERR0 0x84 +#define BCH_BHINT 0x184 +#define BCH_BHINTES0x188 +#define BCH_BHINTEC0x18c +#define BCH_BHINTE 0x190 + +#define BCH_BHCR_BSEL_SHIFT4 +#define BCH_BHCR_BSEL_MASK (0x7f << BCH_BHCR_BSEL_SHIFT) +#define BCH_BHCR_ENCE BIT(2) +#define BCH_BHCR_INIT BIT(1) +#define BCH_BHCR_BCHE BIT(0) + +#define BCH_BHCNT_PARITYSIZE_SHIFT 16 +#define BCH_BHCNT_PARITYSIZE_MASK (0x7f << BCH_BHCNT_PARITYSIZE_SHIFT) +#define BCH
[PATCH v8 0/3] mtd: nand: jz4780: Add NAND and BCH drivers
Hi,
This series adds support for the BCH controller and NAND devices on
the Ingenic JZ4780 SoC.
Tested on the MIPS Creator Ci20 board. All dependencies are now in
mainline.
This version of the series is based on 4.4-rc3.
As suggested by Boris [0], refactoring work has been done to treat NAND
chips as children nodes of the NAND controller.
Review and feedback welcome.
Thanks,
Harvey
[0] https://patchwork.ozlabs.org/patch/526818/
Alex Smith (3):
dt-bindings: binding for jz4780-{nand,bch}
mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs
MIPS: dts: jz4780/ci20: Add NEMC, BCH and NAND device tree nodes
.../bindings/mtd/ingenic,jz4780-nand.txt | 81
arch/mips/boot/dts/ingenic/ci20.dts| 61 +++
arch/mips/boot/dts/ingenic/jz4780.dtsi | 26 ++
drivers/mtd/nand/Kconfig | 7 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/jz4780_bch.c | 361 ++
drivers/mtd/nand/jz4780_bch.h | 42 +++
drivers/mtd/nand/jz4780_nand.c | 420 +
8 files changed, 999 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
create mode 100644 drivers/mtd/nand/jz4780_bch.c
create mode 100644 drivers/mtd/nand/jz4780_bch.h
create mode 100644 drivers/mtd/nand/jz4780_nand.c
--
2.6.2
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[PATCH v8 1/3] dt-bindings: binding for jz4780-{nand,bch}
From: Alex Smith
Add DT bindings for NAND devices connected to the NEMC on JZ4780 SoCs,
as well as the hardware BCH controller, used by the jz4780_{nand,bch}
drivers.
Signed-off-by: Alex Smith
Cc: Zubair Lutfullah Kakakhel
Cc: David Woodhouse
Cc: Brian Norris
Cc: linux-...@lists.infradead.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Alex Smith
Signed-off-by: Harvey Hunt
---
v7 -> v8:
- Describe how NAND chips are now child nodes of the NAND controller.
v6 -> v7:
- Add nand-ecc-mode to DT bindings.
- Add nand-on-flash-bbt to DT bindings.
v5 -> v6:
- No change.
v4 -> v5:
- Rename ingenic,bch-device to ingenic,bch-controller to fit with
existing convention.
v3 -> v4:
- No change
v2 -> v3:
- Rebase to 4.0-rc6
- Changed ingenic,ecc-size to common nand-ecc-step-size
- Changed ingenic,ecc-strength to common nand-ecc-strength
- Changed ingenic,busy-gpio to common rb-gpios
- Changed ingenic,wp-gpio to common wp-gpios
v1 -> v2:
- Rebase to 4.0-rc3
.../bindings/mtd/ingenic,jz4780-nand.txt | 81 ++
1 file changed, 81 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
new file mode 100644
index 000..8151602
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
@@ -0,0 +1,81 @@
+* Ingenic JZ4780 NAND/BCH
+
+This file documents the device tree bindings for NAND flash devices on the
+JZ4780. NAND devices are connected to the NEMC controller (described in
+memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
+be children of the NEMC node.
+
+Required NAND controller device properties:
+- compatible: Should be set to "ingenic,jz4780-nand".
+- reg: For each bank with a NAND chip attached, should specify a bank number,
+ an offset of 0 and a size of 0x100 (i.e. the whole NEMC bank).
+
+Optional NAND controller device properties:
+- ingenic,bch-controller: To make use of the hardware BCH controller, this
+ property must contain a phandle for the BCH controller node. The required
+ properties for this node are described below. If this is not specified,
+ software BCH will be used instead.
+
+Optional children nodes:
+Individual NAND chips are children of the NAND controller node.
+
+Required children node properties:
+- reg: An integer ranging from 1 to 6 representing the CS line to use.
+- #address-cells: See partition.txt
+- #size-cells: See partition.txt
+
+Optional children node properties:
+- nand-ecc-step-size: ECC block size in bytes.
+- nand-ecc-strength: ECC strength (max number of correctable bits).
+- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default
+- nand-on-flash-bbt: boolean to enable on flash bbt option, if not present
false
+- rb-gpios: GPIO specifier for the busy pin.
+- wp-gpios: GPIO specifier for the write protect pin.
+
+Example:
+
+nemc: nemc@1341 {
+ ...
+
+ nandc: nand-controller@1 {
+ compatible = "ingenic,jz4780-nand";
+ reg = <1 0 0x100>; /* Bank 1 */
+
+#address-cells = <1>;
+#size-cells = <0>;
+
+ ingenic,bch-controller = <&bch>;
+
+nand@1 {
+reg = <1>;
+#address-cells = <2>;
+#size-cells = <2>;
+
+nand-ecc-step-size = <1024>;
+nand-ecc-strength = <24>;
+nand-ecc-mode = "hw";
+nand-on-flash-bbt;
+
+rb-gpios = <&gpa 20 GPIO_ACTIVE_LOW>;
+wp-gpios = <&gpf 22 GPIO_ACTIVE_LOW>;
+};
+ };
+};
+
+The BCH controller is a separate SoC component used for error correction on
+NAND devices. The following is a description of the device properties for a
+BCH controller.
+
+Required BCH properties:
+- compatible: Should be set to "ingenic,jz4780-bch".
+- reg: Should specify the BCH controller registers location and length.
+- clocks: Clock for the BCH controller.
+
+Example:
+
+bch: bch@134d {
+ compatible = "ingenic,jz4780-bch";
+ reg = <0x134d 0x1>;
+
+ clocks = <&cgu JZ4780_CLK_BCH>;
+};
--
2.6.2
--
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[PATCH v8 3/3] MIPS: dts: jz4780/ci20: Add NEMC, BCH and NAND device tree nodes
From: Alex Smith
Add device tree nodes for the NEMC and BCH to the JZ4780 device tree,
and make use of them in the Ci20 device tree to add a node for the
board's NAND.
Note that since the pinctrl driver is not yet upstream, this includes
neither pin configuration nor busy/write-protect GPIO pins for the
NAND. Use of the NAND relies on the boot loader to have left the pins
configured in a usable state, which should be the case when booted
from the NAND.
Signed-off-by: Alex Smith
Cc: Zubair Lutfullah Kakakhel
Cc: David Woodhouse
Cc: Brian Norris
Cc: Paul Burton
Cc: linux-...@lists.infradead.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-m...@linux-mips.org
Cc: Alex Smith
Signed-off-by: Harvey Hunt
---
v7 -> v8:
- Describe the NAND chips as children nodes of the NAND controller.
- Remove ingenic, prefix from ECC settings.
- Renamed some ECC settings.
v6 -> v7:
- Add nand-ecc-mode to DT.
- Add nand-on-flash-bbt to DT.
v4 -> v5:
- New patch adding DT nodes for the NAND so that the driver can be
tested.
arch/mips/boot/dts/ingenic/ci20.dts| 61 ++
arch/mips/boot/dts/ingenic/jz4780.dtsi | 26 +++
2 files changed, 87 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
b/arch/mips/boot/dts/ingenic/ci20.dts
index 9fcb9e7..46ed8d0 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -42,3 +42,64 @@
&uart4 {
status = "okay";
};
+
+&nemc {
+ status = "okay";
+
+ nandc: nand-controller@1 {
+ compatible = "ingenic,jz4780-nand";
+ reg = <1 0 0x100>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ingenic,bch-controller = <&bch>;
+
+ ingenic,nemc-tAS = <10>;
+ ingenic,nemc-tAH = <5>;
+ ingenic,nemc-tBP = <10>;
+ ingenic,nemc-tAW = <15>;
+ ingenic,nemc-tSTRV = <100>;
+
+ nand@1 {
+ reg = <1>;
+
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x0 0x0 0x80>;
+ };
+
+ partition@0x80 {
+ label = "u-boot";
+ reg = <0x0 0x80 0x0 0x20>;
+ };
+
+ partition@0xa0 {
+ label = "u-boot-env";
+ reg = <0x0 0xa0 0x0 0x20>;
+ };
+
+ partition@0xc0 {
+ label = "boot";
+ reg = <0x0 0xc0 0x0 0x400>;
+ };
+
+ partition@0x8c0 {
+ label = "system";
+ reg = <0x0 0x4c0 0x1 0xfb40>;
+ };
+ };
+ };
+};
+
+&bch {
+ status = "okay";
+};
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index 65389f6..b868b42 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -108,4 +108,30 @@
status = "disabled";
};
+
+ nemc: nemc@1341 {
+ compatible = "ingenic,jz4780-nemc";
+ reg = <0x1341 0x1>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0x1b00 0x100
+ 2 0 0x1a00 0x100
+ 3 0 0x1900 0x100
+ 4 0 0x1800 0x100
+ 5 0 0x1700 0x100
+ 6 0 0x1600 0x100>;
+
+ clocks = <&cgu JZ4780_CLK_NEMC>;
+
+ status = "disabled";
+ };
+
+ bch: bch@134d {
+ compatible = "ingenic,jz4780-bch";
+ reg = <0x134d 0x1>;
+
+ clocks = <&cgu JZ4780_CLK_BCH>;
+
+ status = "disabled";
+ };
};
--
2.6.2
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v9 0/3] mtd: nand: jz4780: Add NAND and BCH drivers
Hi,
This series adds support for the BCH controller and NAND devices on
the Ingenic JZ4780 SoC.
Tested on the MIPS Creator Ci20 board. All dependencies are now in
mainline.
This version of the series is based on 4.4-rc3.
As suggested by Boris [0], refactoring work has been done to treat NAND
chips as children nodes of the NAND controller.
Review and feedback welcome.
Thanks,
Harvey
[0] https://patchwork.ozlabs.org/patch/526818/
Cc: Brian Norris
Cc: David Woodhouse
Cc: Paul Burton
Cc: Zubair Lutfullah Kakakhel
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-m...@linux-mips.org
Cc: linux-...@lists.infradead.org
Alex Smith (3):
dt-bindings: binding for jz4780-{nand,bch}
mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs
MIPS: dts: jz4780/ci20: Add NEMC, BCH and NAND device tree nodes
.../bindings/mtd/ingenic,jz4780-nand.txt | 86 +
arch/mips/boot/dts/ingenic/ci20.dts| 63
arch/mips/boot/dts/ingenic/jz4780.dtsi | 26 ++
drivers/mtd/nand/Kconfig | 7 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/jz4780_bch.c | 361 ++
drivers/mtd/nand/jz4780_bch.h | 42 +++
drivers/mtd/nand/jz4780_nand.c | 420 +
8 files changed, 1006 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
create mode 100644 drivers/mtd/nand/jz4780_bch.c
create mode 100644 drivers/mtd/nand/jz4780_bch.h
create mode 100644 drivers/mtd/nand/jz4780_nand.c
--
2.6.2
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v9 1/3] dt-bindings: binding for jz4780-{nand,bch}
From: Alex Smith
Add DT bindings for NAND devices connected to the NEMC on JZ4780 SoCs,
as well as the hardware BCH controller, used by the jz4780_{nand,bch}
drivers.
Signed-off-by: Alex Smith
Cc: Zubair Lutfullah Kakakhel
Cc: David Woodhouse
Cc: Brian Norris
Cc: linux-...@lists.infradead.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Harvey Hunt
---
v8 -> v9:
- Document that partitions are represented as a child node of a NAND chip.
v7 -> v8:
- Describe how NAND chips are now child nodes of the NAND controller.
v6 -> v7:
- Add nand-ecc-mode to DT bindings.
- Add nand-on-flash-bbt to DT bindings.
v5 -> v6:
- No change.
v4 -> v5:
- Rename ingenic,bch-device to ingenic,bch-controller to fit with
existing convention.
v3 -> v4:
- No change
v2 -> v3:
- Rebase to 4.0-rc6
- Changed ingenic,ecc-size to common nand-ecc-step-size
- Changed ingenic,ecc-strength to common nand-ecc-strength
- Changed ingenic,busy-gpio to common rb-gpios
- Changed ingenic,wp-gpio to common wp-gpios
v1 -> v2:
- Rebase to 4.0-rc3
.../bindings/mtd/ingenic,jz4780-nand.txt | 86 ++
1 file changed, 86 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
new file mode 100644
index 000..29ea585
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
@@ -0,0 +1,86 @@
+* Ingenic JZ4780 NAND/BCH
+
+This file documents the device tree bindings for NAND flash devices on the
+JZ4780. NAND devices are connected to the NEMC controller (described in
+memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
+be children of the NEMC node.
+
+Required NAND controller device properties:
+- compatible: Should be set to "ingenic,jz4780-nand".
+- reg: For each bank with a NAND chip attached, should specify a bank number,
+ an offset of 0 and a size of 0x100 (i.e. the whole NEMC bank).
+
+Optional NAND controller device properties:
+- ingenic,bch-controller: To make use of the hardware BCH controller, this
+ property must contain a phandle for the BCH controller node. The required
+ properties for this node are described below. If this is not specified,
+ software BCH will be used instead.
+
+Optional children nodes:
+- Individual NAND chips are children of the NAND controller node.
+
+Required children node properties:
+- reg: An integer ranging from 1 to 6 representing the CS line to use.
+
+Optional children node properties:
+- nand-ecc-step-size: ECC block size in bytes.
+- nand-ecc-strength: ECC strength (max number of correctable bits).
+- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default
+- nand-on-flash-bbt: boolean to enable on flash bbt option, if not present
false
+- rb-gpios: GPIO specifier for the busy pin.
+- wp-gpios: GPIO specifier for the write protect pin.
+
+Optional child node of NAND chip nodes:
+- partitions: see Documentation/devicetree/bindings/mtd/partition.txt
+
+Example:
+
+nemc: nemc@1341 {
+ ...
+
+ nandc: nand-controller@1 {
+ compatible = "ingenic,jz4780-nand";
+ reg = <1 0 0x100>; /* Bank 1 */
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ingenic,bch-controller = <&bch>;
+
+ nand@1 {
+ reg = <1>;
+
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+
+ rb-gpios = <&gpa 20 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpf 22 GPIO_ACTIVE_LOW>;
+
+ partitions {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ...
+ }
+ };
+ };
+};
+
+The BCH controller is a separate SoC component used for error correction on
+NAND devices. The following is a description of the device properties for a
+BCH controller.
+
+Required BCH properties:
+- compatible: Should be set to "ingenic,jz4780-bch".
+- reg: Should specify the BCH controller registers location and length.
+- clocks: Clock for the BCH controller.
+
+Example:
+
+bch: bch@134d {
+ compatible = "ingenic,jz4780-bch";
+ reg = <0x134d 0x1>;
+
+ clocks = <&cgu JZ4780_CLK_BCH>;
+};
--
2.6.2
--
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the body of a message to majord...@vger.kernel.org
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[PATCH v9 3/3] MIPS: dts: jz4780/ci20: Add NEMC, BCH and NAND device tree nodes
From: Alex Smith
Add device tree nodes for the NEMC and BCH to the JZ4780 device tree,
and make use of them in the Ci20 device tree to add a node for the
board's NAND.
Note that since the pinctrl driver is not yet upstream, this includes
neither pin configuration nor busy/write-protect GPIO pins for the
NAND. Use of the NAND relies on the boot loader to have left the pins
configured in a usable state, which should be the case when booted
from the NAND.
Signed-off-by: Alex Smith
Cc: Zubair Lutfullah Kakakhel
Cc: David Woodhouse
Cc: Brian Norris
Cc: Paul Burton
Cc: linux-...@lists.infradead.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-m...@linux-mips.org
Signed-off-by: Harvey Hunt
---
v8 -> v9:
- Represent the partition table as a subnode of a NAND chip.
v7 -> v8:
- Describe the NAND chips as children nodes of the NAND controller.
- Remove ingenic, prefix from ECC settings.
- Renamed some ECC settings.
v6 -> v7:
- Add nand-ecc-mode to DT.
- Add nand-on-flash-bbt to DT.
v4 -> v5:
- New patch adding DT nodes for the NAND so that the driver can be
tested.
arch/mips/boot/dts/ingenic/ci20.dts| 63 ++
arch/mips/boot/dts/ingenic/jz4780.dtsi | 26 ++
2 files changed, 89 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
b/arch/mips/boot/dts/ingenic/ci20.dts
index 9fcb9e7..782258c 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -42,3 +42,66 @@
&uart4 {
status = "okay";
};
+
+&nemc {
+ status = "okay";
+
+ nandc: nand-controller@1 {
+ compatible = "ingenic,jz4780-nand";
+ reg = <1 0 0x100>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ingenic,bch-controller = <&bch>;
+
+ ingenic,nemc-tAS = <10>;
+ ingenic,nemc-tAH = <5>;
+ ingenic,nemc-tBP = <10>;
+ ingenic,nemc-tAW = <15>;
+ ingenic,nemc-tSTRV = <100>;
+
+ nand@1 {
+ reg = <1>;
+
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+
+ partitions {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x0 0x0 0x80>;
+ };
+
+ partition@0x80 {
+ label = "u-boot";
+ reg = <0x0 0x80 0x0 0x20>;
+ };
+
+ partition@0xa0 {
+ label = "u-boot-env";
+ reg = <0x0 0xa0 0x0 0x20>;
+ };
+
+ partition@0xc0 {
+ label = "boot";
+ reg = <0x0 0xc0 0x0 0x400>;
+ };
+
+ partition@0x8c0 {
+ label = "system";
+ reg = <0x0 0x4c0 0x1 0xfb40>;
+ };
+ };
+ };
+ };
+};
+
+&bch {
+ status = "okay";
+};
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index 65389f6..b868b42 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -108,4 +108,30 @@
status = "disabled";
};
+
+ nemc: nemc@1341 {
+ compatible = "ingenic,jz4780-nemc";
+ reg = <0x1341 0x1>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0x1b00 0x100
+ 2 0 0x1a00 0x100
+ 3 0 0x1900 0x100
+ 4 0 0x1800 0x100
+ 5 0 0x1700 0x100
+ 6 0 0x1600 0x100>;
+
+ clocks = <&cgu JZ4780_CLK_NEMC>;
+
+ status = "disabled";
+ };
+
+ bch: bch@134d {
+ compatible = "ingenic,jz4780-bch";
+ reg = &
[PATCH v9 2/3] mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs
From: Alex Smith Add a driver for NAND devices connected to the NEMC on JZ4780 SoCs, as well as the hardware BCH controller. DMA is not currently implemented. While older 47xx SoCs also have a BCH controller, they are incompatible with the one in the 4780 due to differing register/bit positions, which would make implementing a common driver for them quite messy. Signed-off-by: Alex Smith Cc: Zubair Lutfullah Kakakhel Cc: David Woodhouse Cc: Brian Norris Cc: linux-...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Harvey Hunt --- v8 -> v9: - No change. v7 -> v8: - Rebase to 4.4-rc3. - Add _US suffixes to time constants. - Add locking to BCH hardware accesses. - Don't print ECC info if ECC is not being used. - Default to No ECC. - Let the NAND core handle ECC layout in certain cases. - Use the gpio_desc consumer interface. - Removed gpio active low flags. - Check for the BCH controller before initialising a chip. - Add a jz4780_nand_controller struct. - Initialise chips by iterating over DT child nodes. v6 -> v7: - Add nand-ecc-mode to DT bindings. - Add nand-on-flash-bbt to DT bindings. v5 -> v6: - No change. v4 -> v5: - Rename ingenic,bch-device to ingenic,bch-controller to fit with existing convention. v3 -> v4: - No change v2 -> v3: - Rebase to 4.0-rc6 - Changed ingenic,ecc-size to common nand-ecc-step-size - Changed ingenic,ecc-strength to common nand-ecc-strength - Changed ingenic,busy-gpio to common rb-gpios - Changed ingenic,wp-gpio to common wp-gpios v1 -> v2: - Rebase to 4.0-rc3 drivers/mtd/nand/Kconfig | 7 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/jz4780_bch.c | 361 +++ drivers/mtd/nand/jz4780_bch.h | 42 + drivers/mtd/nand/jz4780_nand.c | 420 + 5 files changed, 831 insertions(+) create mode 100644 drivers/mtd/nand/jz4780_bch.c create mode 100644 drivers/mtd/nand/jz4780_bch.h create mode 100644 drivers/mtd/nand/jz4780_nand.c diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 2896640..b742adc 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -519,6 +519,13 @@ config MTD_NAND_JZ4740 help Enables support for NAND Flash on JZ4740 SoC based boards. +config MTD_NAND_JZ4780 + tristate "Support for NAND on JZ4780 SoC" + depends on MACH_JZ4780 && JZ4780_NEMC + help + Enables support for NAND Flash connected to the NEMC on JZ4780 SoC + based boards, using the BCH controller for hardware error correction. + config MTD_NAND_FSMC tristate "Support for NAND on ST Micros FSMC" depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300 diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 2c7f014..9e36233 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC)+= mpc5121_nfc.o obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o obj-$(CONFIG_MTD_NAND_RICOH) += r852.o obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o +obj-$(CONFIG_MTD_NAND_JZ4780) += jz4780_nand.o jz4780_bch.o obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ obj-$(CONFIG_MTD_NAND_XWAY)+= xway_nand.o obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ diff --git a/drivers/mtd/nand/jz4780_bch.c b/drivers/mtd/nand/jz4780_bch.c new file mode 100644 index 000..0c472f4 --- /dev/null +++ b/drivers/mtd/nand/jz4780_bch.c @@ -0,0 +1,361 @@ +/* + * JZ4780 BCH controller + * + * Copyright (c) 2015 Imagination Technologies + * Author: Alex Smith + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "jz4780_bch.h" + +#define BCH_BHCR 0x0 +#define BCH_BHCCR 0x8 +#define BCH_BHCNT 0xc +#define BCH_BHDR 0x10 +#define BCH_BHPAR0 0x14 +#define BCH_BHERR0 0x84 +#define BCH_BHINT 0x184 +#define BCH_BHINTES0x188 +#define BCH_BHINTEC0x18c +#define BCH_BHINTE 0x190 + +#define BCH_BHCR_BSEL_SHIFT4 +#define BCH_BHCR_BSEL_MASK (0x7f << BCH_BHCR_BSEL_SHIFT) +#define BCH_BHCR_ENCE BIT(2) +#define BCH_BHCR_INIT BIT(1) +#define BCH_BHCR_BCHE BIT(0) + +#define BCH_BHCNT_PARITYSIZE_SHIFT 16 +#define BCH_BHCNT_PARITYSIZE_MASK (0x7f << BCH_BHCNT_PARITYSIZE_SHIFT) +#define
Re: [PATCH 05/23] mtd: nand: jz4770: kill the ->ecc_layout field
Hi Boris,
On 07/12/15 22:26, Boris Brezillon wrote:
->ecc_layout is not used by any board file. Kill this field to avoid any
confusion. New boards are encouraged to use the default ECC layout defined
in NAND core.
Signed-off-by: Boris Brezillon
---
arch/mips/include/asm/mach-jz4740/jz4740_nand.h | 2 --
drivers/mtd/nand/jz4740_nand.c | 3 ---
2 files changed, 5 deletions(-)
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
index 79cff26..398733e 100644
--- a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
+++ b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
@@ -25,8 +25,6 @@ struct jz_nand_platform_data {
int num_partitions;
struct mtd_partition*partitions;
- struct nand_ecclayout *ecc_layout;
-
unsigned char banks[JZ_NAND_NUM_BANKS];
void (*ident_callback)(struct platform_device *, struct nand_chip *,
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
index 5a99a93..c4fe446 100644
--- a/drivers/mtd/nand/jz4740_nand.c
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -446,9 +446,6 @@ static int jz_nand_probe(struct platform_device *pdev)
chip->ecc.bytes = 9;
chip->ecc.strength = 4;
- if (pdata)
- chip->ecc.layout = pdata->ecc_layout;
-
chip->chip_delay = 50;
chip->cmd_ctrl = jz_nand_cmd_ctrl;
chip->select_chip = jz_nand_select_chip;
Is there a typo in this commit title? The JZ4740 and JZ4770 have quite
different NAND controller interfaces, so I don't think that the JZ4740
driver will support the JZ4770.
Thanks,
Harvey
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Re: [PATCH v9 2/3] mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs
Hi Boris, Thanks for the review. On 08/12/15 14:14, Boris Brezillon wrote: On Thu, 3 Dec 2015 12:02:21 + Harvey Hunt wrote: From: Alex Smith Add a driver for NAND devices connected to the NEMC on JZ4780 SoCs, as well as the hardware BCH controller. DMA is not currently implemented. While older 47xx SoCs also have a BCH controller, they are incompatible with the one in the 4780 due to differing register/bit positions, which would make implementing a common driver for them quite messy. Signed-off-by: Alex Smith Cc: Zubair Lutfullah Kakakhel Cc: David Woodhouse Cc: Brian Norris Cc: linux-...@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Harvey Hunt --- v8 -> v9: - No change. v7 -> v8: - Rebase to 4.4-rc3. - Add _US suffixes to time constants. - Add locking to BCH hardware accesses. - Don't print ECC info if ECC is not being used. - Default to No ECC. - Let the NAND core handle ECC layout in certain cases. - Use the gpio_desc consumer interface. - Removed gpio active low flags. - Check for the BCH controller before initialising a chip. - Add a jz4780_nand_controller struct. - Initialise chips by iterating over DT child nodes. v6 -> v7: - Add nand-ecc-mode to DT bindings. - Add nand-on-flash-bbt to DT bindings. v5 -> v6: - No change. v4 -> v5: - Rename ingenic,bch-device to ingenic,bch-controller to fit with existing convention. v3 -> v4: - No change v2 -> v3: - Rebase to 4.0-rc6 - Changed ingenic,ecc-size to common nand-ecc-step-size - Changed ingenic,ecc-strength to common nand-ecc-strength - Changed ingenic,busy-gpio to common rb-gpios - Changed ingenic,wp-gpio to common wp-gpios v1 -> v2: - Rebase to 4.0-rc3 drivers/mtd/nand/Kconfig | 7 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/jz4780_bch.c | 361 +++ drivers/mtd/nand/jz4780_bch.h | 42 + drivers/mtd/nand/jz4780_nand.c | 420 + 5 files changed, 831 insertions(+) create mode 100644 drivers/mtd/nand/jz4780_bch.c create mode 100644 drivers/mtd/nand/jz4780_bch.h create mode 100644 drivers/mtd/nand/jz4780_nand.c diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 2896640..b742adc 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -519,6 +519,13 @@ config MTD_NAND_JZ4740 help Enables support for NAND Flash on JZ4740 SoC based boards. +config MTD_NAND_JZ4780 + tristate "Support for NAND on JZ4780 SoC" + depends on MACH_JZ4780 && JZ4780_NEMC + help + Enables support for NAND Flash connected to the NEMC on JZ4780 SoC + based boards, using the BCH controller for hardware error correction. + config MTD_NAND_FSMC tristate "Support for NAND on ST Micros FSMC" depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300 diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 2c7f014..9e36233 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC)+= mpc5121_nfc.o obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o obj-$(CONFIG_MTD_NAND_RICOH) += r852.o obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o +obj-$(CONFIG_MTD_NAND_JZ4780) += jz4780_nand.o jz4780_bch.o obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ diff --git a/drivers/mtd/nand/jz4780_bch.c b/drivers/mtd/nand/jz4780_bch.c new file mode 100644 index 000..0c472f4 --- /dev/null +++ b/drivers/mtd/nand/jz4780_bch.c @@ -0,0 +1,361 @@ +/* + * JZ4780 BCH controller + * + * Copyright (c) 2015 Imagination Technologies + * Author: Alex Smith + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "jz4780_bch.h" + +#define BCH_BHCR 0x0 +#define BCH_BHCCR 0x8 +#define BCH_BHCNT 0xc +#define BCH_BHDR 0x10 +#define BCH_BHPAR0 0x14 +#define BCH_BHERR0 0x84 +#define BCH_BHINT 0x184 +#define BCH_BHINTES0x188 +#define BCH_BHINTEC0x18c +#define BCH_BHINTE 0x190 + +#define BCH_BHCR_BSEL_SHIFT4 +#define BCH_BHCR_BSEL_MASK (0x7f << BCH_BHCR_BSEL_SHIFT) +#define BCH_BHCR_ENCE BIT(2) +#define BCH_BHCR_INIT BIT(1) +#define BCH_BHCR_BCHE
Re: [PATCH v9 2/3] mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs
On 08/12/15 16:12, Boris Brezillon wrote:
On Tue, 8 Dec 2015 16:03:55 +
Harvey Hunt wrote:
static void jz4780_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
unsigned int ctrl)
{
struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
struct jz4780_nand_controller *nfc =
to_jz4780_nand_controller(nand->chip.controller);
struct jz4780_nand_cs *cs;
if (WARN_ON(nfc->selected < 0))
return;
cs = &nfc->cs[nfc->selected];
if (ctrl & NAND_CTRL_CHANGE) {
if (cmd != NAND_CMD_NONE) {
if (ctrl & NAND_ALE)
writeb(cmd, cs->base + OFFSET_ADDR);
else if (ctrl & NAND_CLE)
writeb(cmd, cs->base + OFFSET_CMD);
}
jz4780_nemc_assert(nfc->dev, cs->bank, ctrl & NAND_NCE);
}
}
Okay, I understand your point now. I would also have to implement the
read/write functions to replace the defaults, correct? If so, it feels
strange to add functions to reimplement the default ones.
I don't think you have to re-implement the {read,write}_{byte,buf,word}
functions, because you'll still assign the ->IO_ADDR_W and ->IO_ADDR_R
fields to cs->base + OFFSET_DATA in jz4780_nand_init_chip(), but maybe
I'm missing something.
You're right, I forgot about that.
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Re: [PATCH v9 2/3] mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs
On 08/12/15 16:26, Boris Brezillon wrote:
On Tue, 8 Dec 2015 16:03:55 +
Harvey Hunt wrote:
static void jz4780_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
unsigned int ctrl)
{
struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
struct jz4780_nand_controller *nfc =
to_jz4780_nand_controller(nand->chip.controller);
struct jz4780_nand_cs *cs;
if (WARN_ON(nfc->selected < 0))
return;
cs = &nfc->cs[nfc->selected];
if (ctrl & NAND_CTRL_CHANGE) {
if (cmd != NAND_CMD_NONE) {
if (ctrl & NAND_ALE)
writeb(cmd, cs->base + OFFSET_ADDR);
else if (ctrl & NAND_CLE)
writeb(cmd, cs->base + OFFSET_CMD);
}
jz4780_nemc_assert(nfc->dev, cs->bank, ctrl & NAND_NCE);
}
}
Okay, I understand your point now. I would also have to implement the
read/write functions to replace the defaults, correct? If so, it feels
strange to add functions to reimplement the default ones.
Actually it should be something like this, because NAND_CTRL_CHANGE is
cleared after the first address cycle.
static void jz4780_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
unsigned int ctrl)
{
struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
struct jz4780_nand_controller *nfc =
to_jz4780_nand_controller(nand->chip.controller);
struct jz4780_nand_cs *cs;
if (WARN_ON(nfc->selected < 0))
return;
cs = &nfc->cs[nfc->selected];
jz4780_nemc_assert(nfc->dev, cs->bank, ctrl & NAND_NCE);
if (cmd == NAND_CMD_NONE)
return;
if (ctrl & NAND_ALE)
writeb(cmd, cs->base + OFFSET_ADDR);
else if (ctrl & NAND_CLE)
writeb(cmd, cs->base + OFFSET_CMD);
}
Thanks for the example code, I'll try it out for the next version.
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Re: [PATCH v10 2/3] mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs
Hi Boris,
Happy New Year.
Thanks for the comments - I'll send out a new patchset today.
On 28/12/15 08:25, Boris Brezillon wrote:
Hi Harvey,
I found a few remaining issues. Once fixed you can add my
Reviewed-by: Boris Brezillon
On Thu, 24 Dec 2015 12:20:14 +
Harvey Hunt wrote:
From: Alex Smith
Add a driver for NAND devices connected to the NEMC on JZ4780 SoCs, as
well as the hardware BCH controller. DMA is not currently implemented.
While older 47xx SoCs also have a BCH controller, they are incompatible
with the one in the 4780 due to differing register/bit positions, which
would make implementing a common driver for them quite messy.
Signed-off-by: Alex Smith
Cc: Zubair Lutfullah Kakakhel
Cc: David Woodhouse
Cc: Brian Norris
Cc: linux-...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Harvey Hunt
---
v9 -> v10:
- Replace uint{8,32}_t with u{8,32}.
- Only set IO_ADDR_{R,W} during chip init.
- Check that ECC layout fits into OOB area.
- Rebase onto l2-mtd/master and use its new functions.
- Remove mtd field from jz4780_nand_chip.
- Tidied up jz4780_nand_cmd_ctrl.
- Corrected ECC mode print statement.
- Refactor BCH code.
- Implement of_jz4780_bch_get.
- Update Authorship.
- Use a mutex to protect accesses to BCH controller.
- Update code documentation.
- Checkpatch cleanup.
v8 -> v9:
- No change.
v7 -> v8:
- Rebase to 4.4-rc3.
- Add _US suffixes to time constants.
- Add locking to BCH hardware accesses.
- Don't print ECC info if ECC is not being used.
- Default to No ECC.
- Let the NAND core handle ECC layout in certain cases.
- Use the gpio_desc consumer interface.
- Removed gpio active low flags.
- Check for the BCH controller before initialising a chip.
- Add a jz4780_nand_controller struct.
- Initialise chips by iterating over DT child nodes.
v6 -> v7:
- Add nand-ecc-mode to DT bindings.
- Add nand-on-flash-bbt to DT bindings.
v5 -> v6:
- No change.
v4 -> v5:
- Rename ingenic,bch-device to ingenic,bch-controller to fit with
existing convention.
v3 -> v4:
- No change
v2 -> v3:
- Rebase to 4.0-rc6
- Changed ingenic,ecc-size to common nand-ecc-step-size
- Changed ingenic,ecc-strength to common nand-ecc-strength
- Changed ingenic,busy-gpio to common rb-gpios
- Changed ingenic,wp-gpio to common wp-gpios
v1 -> v2:
- Rebase to 4.0-rc3
drivers/mtd/nand/Kconfig | 7 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/jz4780_bch.c | 381 +
drivers/mtd/nand/jz4780_bch.h | 44 +
drivers/mtd/nand/jz4780_nand.c | 416 +
5 files changed, 849 insertions(+)
create mode 100644 drivers/mtd/nand/jz4780_bch.c
create mode 100644 drivers/mtd/nand/jz4780_bch.h
create mode 100644 drivers/mtd/nand/jz4780_nand.c
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 2896640..b742adc 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -519,6 +519,13 @@ config MTD_NAND_JZ4740
help
Enables support for NAND Flash on JZ4740 SoC based boards.
+config MTD_NAND_JZ4780
+ tristate "Support for NAND on JZ4780 SoC"
+ depends on MACH_JZ4780 && JZ4780_NEMC
+ help
+ Enables support for NAND Flash connected to the NEMC on JZ4780 SoC
+ based boards, using the BCH controller for hardware error correction.
+
config MTD_NAND_FSMC
tristate "Support for NAND on ST Micros FSMC"
depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 2c7f014..9e36233 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC)+= mpc5121_nfc.o
obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
+obj-$(CONFIG_MTD_NAND_JZ4780) += jz4780_nand.o jz4780_bch.o
obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
diff --git a/drivers/mtd/nand/jz4780_bch.c b/drivers/mtd/nand/jz4780_bch.c
new file mode 100644
index 000..22d3729
--- /dev/null
+++ b/drivers/mtd/nand/jz4780_bch.c
@@ -0,0 +1,381 @@
+/*
+ * JZ4780 BCH controller
+ *
+ * Copyright (c) 2015 Imagination Technologies
+ * Author: Alex Smith
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "jz4780_bch.h"
+
+#define BCH_BHCR
Re: [PATCH v10 2/3] mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs
Hi Boris,
On 04/01/16 11:47, Boris Brezillon wrote:
Hi Harvey,
On Mon, 4 Jan 2016 10:24:15 +
Harvey Hunt wrote:
+
+static void jz4780_bch_disable(struct jz4780_bch *bch)
+{
+ writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);
+ writel(BCH_BHCR_BCHE, bch->base + BCH_BHCCR);
Not sure what BCH_BHCR_BCHE means, but if BCHE stands for "BCH Enable",
do you really have to keep this bit set when disabling the engine?
The JZ4780 has the BHCR (BCH Control Register) as well as the BHCCR
(BCH Control Clear Register) and BHCSR (BCH Control Set Register).
Setting the bit BCH_BHCR_BCHE in BHCCR clears the corresponding bit in
BHCR, which disables the BCH controller.
Okay, thanks for the explanation. I guess BCHE stands for BCH Engine
then.
[...]
+
+static int jz4780_nand_init_ecc(struct jz4780_nand_chip *nand, struct device
*dev)
+{
+ struct nand_chip *chip = &nand->chip;
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ struct jz4780_nand_controller *nfc =
to_jz4780_nand_controller(chip->controller);
+ struct nand_ecclayout *layout = &nand->ecclayout;
+ u32 start, i;
+
+ chip->ecc.bytes = fls((1 + 8) * chip->ecc.size) *
+ (chip->ecc.strength / 8);
+
+ if (nfc->bch && chip->ecc.mode == NAND_ECC_HW) {
+ chip->ecc.hwctl = jz4780_nand_ecc_hwctl;
+ chip->ecc.calculate = jz4780_nand_ecc_calculate;
+ chip->ecc.correct = jz4780_nand_ecc_correct;
+ } else if (!nfc->bch && chip->ecc.mode == NAND_ECC_HW) {
+ dev_err(dev, "HW BCH selected, but BCH controller not found\n");
+ return -ENODEV;
+ }
+
+ if (chip->ecc.mode != NAND_ECC_NONE)
+ dev_info(dev, "using %s (strength %d, size %d, bytes %d)\n",
+ (nfc->bch) ? "hardware BCH" : "software hamming",
As said in my previous review, '!= NAND_ECC_HW' does not necessarily
imply '== NAND_ECC_SOFT' (i.e. hamming ECC), so I'd suggest printing
something like "software ECC".
Done.
+ chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
+ else
+ dev_info(dev, "not using ECC\n");
You should probably complain about the invalid NAND_ECC_HW_SYNDROME
value and return -EINVAL in this case.
Don't forget that aspect ^.
I forgot to mention it in my email, but I've not forgotten it in my
patchset. :-)
+
+ /* The NAND core will generate the ECC layout. */
+ if (chip->ecc.mode == NAND_ECC_SOFT || chip->ecc.mode ==
NAND_ECC_SOFT_BCH)
+ return 0;
+
+ /* Generate ECC layout. ECC codes are right aligned in the OOB area. */
+ layout->eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes;
+
+ if (layout->eccbytes > mtd->oobsize - 2) {
+ dev_err(dev,
+ "invalid ECC config: required %d ECC bytes, but only %d are
available",
+ layout->eccbytes, mtd->oobsize - 2);
+ return -EINVAL;
+ }
+
+ start = mtd->oobsize - layout->eccbytes;
+ for (i = 0; i < layout->eccbytes; i++)
+ layout->eccpos[i] = start + i;
+
+ layout->oobfree[0].offset = 2;
+ layout->oobfree[0].length = mtd->oobsize - layout->eccbytes - 2;
+
+ chip->ecc.layout = layout;
+ return 0;
+}
+
+static int jz4780_nand_init_chip(struct platform_device *pdev,
+ struct jz4780_nand_controller *nfc,
+ struct device_node *np,
+ unsigned int chipnr)
+{
+ struct device *dev = &pdev->dev;
+ struct jz4780_nand_chip *nand;
+ struct jz4780_nand_cs *cs;
+ struct resource *res;
+ struct nand_chip *chip;
+ struct mtd_info *mtd;
+ const __be32 *reg;
+ int ret = 0;
+
+ cs = &nfc->cs[chipnr];
+
+ reg = of_get_property(np, "reg", NULL);
+ if (!reg)
+ return -EINVAL;
+
+ cs->bank = be32_to_cpu(*reg);
+
+ jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, chipnr);
+ cs->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(cs->base))
+ return PTR_ERR(cs->base);
+
+ nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
+ if (!nand)
+ return -ENOMEM;
+
+ nand->busy_gpio = devm_gpiod_get_optional(dev, "rb", GPIOD_IN);
+
+ if (IS_ERR(nand->busy_gpio)) {
+ ret = PTR_ERR(nand->busy_gpio);
+ dev_err(dev, "failed to request busy GPIO: %d\n"
[PATCH v11 2/3] mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs
From: Alex Smith
Add a driver for NAND devices connected to the NEMC on JZ4780 SoCs, as
well as the hardware BCH controller. DMA is not currently implemented.
While older 47xx SoCs also have a BCH controller, they are incompatible
with the one in the 4780 due to differing register/bit positions, which
would make implementing a common driver for them quite messy.
Signed-off-by: Alex Smith
Cc: Zubair Lutfullah Kakakhel
Cc: David Woodhouse
Cc: Brian Norris
Cc: linux-...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Harvey Hunt
Reviewed-by: Boris Brezillon
---
v10 -> v11:
- Reordered mutex unlocking.
- Made jz4780_bch_get() private.
- Removed extern prefix from function prototype definitions.
- Removed a useless else.
- Changed ECC strength print statement.
- Implemented jz4780_nand_cleanup_chips().
- Add a NAND chip to the NFC's list after it has been initialised.
- Complain when NAND_ECC_HW_SYNDROME is selected.
- Call jz4780_bch_release() from jz4780_nand_probe().
- Added Boris Brezillon's Reviewed-By.
v9 -> v10:
- Replace uint{8,32}_t with u{8,32}.
- Only set IO_ADDR_{R,W} during chip init.
- Check that ECC layout fits into OOB area.
- Rebase onto l2-mtd/master and use its new functions.
- Remove mtd field from jz4780_nand_chip.
- Tidied up jz4780_nand_cmd_ctrl.
- Corrected ECC mode print statement.
- Refactor BCH code.
- Implement of_jz4780_bch_get.
- Update Authorship.
- Use a mutex to protect accesses to BCH controller.
- Update code documentation.
- Checkpatch cleanup.
v8 -> v9:
- No change.
v7 -> v8:
- Rebase to 4.4-rc3.
- Add _US suffixes to time constants.
- Add locking to BCH hardware accesses.
- Don't print ECC info if ECC is not being used.
- Default to No ECC.
- Let the NAND core handle ECC layout in certain cases.
- Use the gpio_desc consumer interface.
- Removed gpio active low flags.
- Check for the BCH controller before initialising a chip.
- Add a jz4780_nand_controller struct.
- Initialise chips by iterating over DT child nodes.
v6 -> v7:
- Add nand-ecc-mode to DT bindings.
- Add nand-on-flash-bbt to DT bindings.
v5 -> v6:
- No change.
v4 -> v5:
- Rename ingenic,bch-device to ingenic,bch-controller to fit with
existing convention.
v3 -> v4:
- No change
v2 -> v3:
- Rebase to 4.0-rc6
- Changed ingenic,ecc-size to common nand-ecc-step-size
- Changed ingenic,ecc-strength to common nand-ecc-strength
- Changed ingenic,busy-gpio to common rb-gpios
- Changed ingenic,wp-gpio to common wp-gpios
v1 -> v2:
- Rebase to 4.0-rc3
drivers/mtd/nand/Kconfig | 7 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/jz4780_bch.c | 380 +
drivers/mtd/nand/jz4780_bch.h | 43 +
drivers/mtd/nand/jz4780_nand.c | 422 +
5 files changed, 853 insertions(+)
create mode 100644 drivers/mtd/nand/jz4780_bch.c
create mode 100644 drivers/mtd/nand/jz4780_bch.h
create mode 100644 drivers/mtd/nand/jz4780_nand.c
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 2896640..b742adc 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -519,6 +519,13 @@ config MTD_NAND_JZ4740
help
Enables support for NAND Flash on JZ4740 SoC based boards.
+config MTD_NAND_JZ4780
+ tristate "Support for NAND on JZ4780 SoC"
+ depends on MACH_JZ4780 && JZ4780_NEMC
+ help
+ Enables support for NAND Flash connected to the NEMC on JZ4780 SoC
+ based boards, using the BCH controller for hardware error correction.
+
config MTD_NAND_FSMC
tristate "Support for NAND on ST Micros FSMC"
depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 2c7f014..9e36233 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC)+= mpc5121_nfc.o
obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
+obj-$(CONFIG_MTD_NAND_JZ4780) += jz4780_nand.o jz4780_bch.o
obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
obj-$(CONFIG_MTD_NAND_XWAY)+= xway_nand.o
obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
diff --git a/drivers/mtd/nand/jz4780_bch.c b/drivers/mtd/nand/jz4780_bch.c
new file mode 100644
index 000..53b2c06
--- /dev/null
+++ b/drivers/mtd/nand/jz4780_bch.c
@@ -0,0 +1,380 @@
+/*
+ * JZ4780 BCH controller
+ *
+ * Copyright (c) 2015 Imagination Technologies
+ * Author: Alex Smith
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include
+#include
+#
[PATCH v11 1/3] dt-bindings: binding for jz4780-{nand,bch}
From: Alex Smith
Add DT bindings for NAND devices connected to the NEMC on JZ4780 SoCs,
as well as the hardware BCH controller, used by the jz4780_{nand,bch}
drivers.
Signed-off-by: Alex Smith
Cc: Zubair Lutfullah Kakakhel
Cc: David Woodhouse
Cc: Brian Norris
Cc: linux-...@lists.infradead.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: r...@kernel.org
Signed-off-by: Harvey Hunt
Acked-by: Rob Herring
Reviewed-by: Boris Brezillon
---
v10 -> v11:
- Added Boris Brezillon's Reviewed-By.
v9 -> v10:
- Added Rob Herring's Acked-by.
v8 -> v9:
- Document that partitions are represented as a child node of a NAND chip.
v7 -> v8:
- Describe how NAND chips are now child nodes of the NAND controller.
v6 -> v7:
- Add nand-ecc-mode to DT bindings.
- Add nand-on-flash-bbt to DT bindings.
v5 -> v6:
- No change.
v4 -> v5:
- Rename ingenic,bch-device to ingenic,bch-controller to fit with
existing convention.
v3 -> v4:
- No change
v2 -> v3:
- Rebase to 4.0-rc6
- Changed ingenic,ecc-size to common nand-ecc-step-size
- Changed ingenic,ecc-strength to common nand-ecc-strength
- Changed ingenic,busy-gpio to common rb-gpios
- Changed ingenic,wp-gpio to common wp-gpios
v1 -> v2:
- Rebase to 4.0-rc3
.../bindings/mtd/ingenic,jz4780-nand.txt | 86 ++
1 file changed, 86 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
new file mode 100644
index 000..29ea585
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
@@ -0,0 +1,86 @@
+* Ingenic JZ4780 NAND/BCH
+
+This file documents the device tree bindings for NAND flash devices on the
+JZ4780. NAND devices are connected to the NEMC controller (described in
+memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
+be children of the NEMC node.
+
+Required NAND controller device properties:
+- compatible: Should be set to "ingenic,jz4780-nand".
+- reg: For each bank with a NAND chip attached, should specify a bank number,
+ an offset of 0 and a size of 0x100 (i.e. the whole NEMC bank).
+
+Optional NAND controller device properties:
+- ingenic,bch-controller: To make use of the hardware BCH controller, this
+ property must contain a phandle for the BCH controller node. The required
+ properties for this node are described below. If this is not specified,
+ software BCH will be used instead.
+
+Optional children nodes:
+- Individual NAND chips are children of the NAND controller node.
+
+Required children node properties:
+- reg: An integer ranging from 1 to 6 representing the CS line to use.
+
+Optional children node properties:
+- nand-ecc-step-size: ECC block size in bytes.
+- nand-ecc-strength: ECC strength (max number of correctable bits).
+- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default
+- nand-on-flash-bbt: boolean to enable on flash bbt option, if not present
false
+- rb-gpios: GPIO specifier for the busy pin.
+- wp-gpios: GPIO specifier for the write protect pin.
+
+Optional child node of NAND chip nodes:
+- partitions: see Documentation/devicetree/bindings/mtd/partition.txt
+
+Example:
+
+nemc: nemc@1341 {
+ ...
+
+ nandc: nand-controller@1 {
+ compatible = "ingenic,jz4780-nand";
+ reg = <1 0 0x100>; /* Bank 1 */
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ingenic,bch-controller = <&bch>;
+
+ nand@1 {
+ reg = <1>;
+
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+
+ rb-gpios = <&gpa 20 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpf 22 GPIO_ACTIVE_LOW>;
+
+ partitions {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ...
+ }
+ };
+ };
+};
+
+The BCH controller is a separate SoC component used for error correction on
+NAND devices. The following is a description of the device properties for a
+BCH controller.
+
+Required BCH properties:
+- compatible: Should be set to "ingenic,jz4780-bch".
+- reg: Should specify the BCH controller registers location and length.
+- clocks: Clock for the BCH controller.
+
+Example:
+
+bch: bch@134d {
+ compatible = "ingenic,jz4780-bch";
+ reg = <0x134d 0x1>;
+
+ clocks = <&cgu JZ4780_CLK_BCH>;
+};
--
2.6.4
-
[PATCH v11 3/3] MIPS: dts: jz4780/ci20: Add NEMC, BCH and NAND device tree nodes
From: Alex Smith
Add device tree nodes for the NEMC and BCH to the JZ4780 device tree,
and make use of them in the Ci20 device tree to add a node for the
board's NAND.
Note that since the pinctrl driver is not yet upstream, this includes
neither pin configuration nor busy/write-protect GPIO pins for the
NAND. Use of the NAND relies on the boot loader to have left the pins
configured in a usable state, which should be the case when booted
from the NAND.
Signed-off-by: Alex Smith
Cc: Zubair Lutfullah Kakakhel
Cc: David Woodhouse
Cc: Brian Norris
Cc: Paul Burton
Cc: linux-...@lists.infradead.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-m...@linux-mips.org
Cc: r...@kernel.org
Signed-off-by: Harvey Hunt
Reviewed-by: Boris Brezillon
---
v10 -> v11:
- Added Boris Brezillon's Reviewed-By.
v9 -> v10:
- No change.
v8 -> v9:
- Represent the partition table as a subnode of a NAND chip.
v7 -> v8:
- Describe the NAND chips as children nodes of the NAND controller.
- Remove ingenic, prefix from ECC settings.
- Renamed some ECC settings.
v6 -> v7:
- Add nand-ecc-mode to DT.
- Add nand-on-flash-bbt to DT.
v4 -> v5:
- New patch adding DT nodes for the NAND so that the driver can be
tested.
arch/mips/boot/dts/ingenic/ci20.dts| 63 ++
arch/mips/boot/dts/ingenic/jz4780.dtsi | 26 ++
2 files changed, 89 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
b/arch/mips/boot/dts/ingenic/ci20.dts
index 9fcb9e7..782258c 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -42,3 +42,66 @@
&uart4 {
status = "okay";
};
+
+&nemc {
+ status = "okay";
+
+ nandc: nand-controller@1 {
+ compatible = "ingenic,jz4780-nand";
+ reg = <1 0 0x100>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ingenic,bch-controller = <&bch>;
+
+ ingenic,nemc-tAS = <10>;
+ ingenic,nemc-tAH = <5>;
+ ingenic,nemc-tBP = <10>;
+ ingenic,nemc-tAW = <15>;
+ ingenic,nemc-tSTRV = <100>;
+
+ nand@1 {
+ reg = <1>;
+
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+
+ partitions {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x0 0x0 0x80>;
+ };
+
+ partition@0x80 {
+ label = "u-boot";
+ reg = <0x0 0x80 0x0 0x20>;
+ };
+
+ partition@0xa0 {
+ label = "u-boot-env";
+ reg = <0x0 0xa0 0x0 0x20>;
+ };
+
+ partition@0xc0 {
+ label = "boot";
+ reg = <0x0 0xc0 0x0 0x400>;
+ };
+
+ partition@0x8c0 {
+ label = "system";
+ reg = <0x0 0x4c0 0x1 0xfb40>;
+ };
+ };
+ };
+ };
+};
+
+&bch {
+ status = "okay";
+};
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index 65389f6..b868b42 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -108,4 +108,30 @@
status = "disabled";
};
+
+ nemc: nemc@1341 {
+ compatible = "ingenic,jz4780-nemc";
+ reg = <0x1341 0x1>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0x1b00 0x100
+ 2 0 0x1a00 0x100
+ 3 0 0x1900 0x100
+ 4 0 0x1800 0x100
+ 5 0 0x1700 0x100
+ 6 0 0x1600 0x100>;
+
+ clocks = <&cgu JZ4780_CLK_NEMC>;
+
+ status = "disab
[PATCH] MIPS: Always page align TASK_SIZE
STACK_TOP_MAX is aligned on a 32k boundary. When __bprm_mm_init() creates an initial stack for a process, it does so using STACK_TOP_MAX as the end of the vma. A process's arguments and environment information are placed on the stack and then the stack is relocated and aligned on a page boundary. When using a 32 bit kernel with 64k pages, the relocated stack has the process's args erroneously stored in the middle of the stack. This means that processes receive no arguments or environment variables, preventing them from running correctly. Fix this by aligning TASK_SIZE on a page boundary. Signed-off-by: Harvey Hunt Cc: David Daney Cc: Paul Burton Cc: James Hogan Cc: linux-kernel@vger.kernel.org --- arch/mips/include/asm/processor.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 3f832c3..b618b40 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -39,13 +39,13 @@ extern unsigned int vced_count, vcei_count; #ifdef CONFIG_32BIT #ifdef CONFIG_KVM_GUEST /* User space process size is limited to 1GB in KVM Guest Mode */ -#define TASK_SIZE 0x3fff8000UL +#define TASK_SIZE (0x4000UL - PAGE_SIZE) #else /* * User space process size: 2GB. This is hardcoded into a few places, * so don't change it unless you know what you are doing. */ -#define TASK_SIZE 0x7fff8000UL +#define TASK_SIZE (0x7fff8000UL & PAGE_SIZE) #endif #define STACK_TOP_MAX TASK_SIZE @@ -62,7 +62,7 @@ extern unsigned int vced_count, vcei_count; * support 16TB; the architectural reserve for future expansion is * 8192EB ... */ -#define TASK_SIZE320x7fff8000UL +#define TASK_SIZE32(0x7fff8000UL & PAGE_SIZE) #define TASK_SIZE640x100UL #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) #define STACK_TOP_MAX TASK_SIZE64 -- 2.7.1
Re: [PATCH] MIPS: Always page align TASK_SIZE
Hi David, On 02/08/2016 10:11 AM, David Daney wrote: On 02/08/2016 10:05 AM, Harvey Hunt wrote: STACK_TOP_MAX is aligned on a 32k boundary. When __bprm_mm_init() creates an initial stack for a process, it does so using STACK_TOP_MAX as the end of the vma. A process's arguments and environment information are placed on the stack and then the stack is relocated and aligned on a page boundary. When using a 32 bit kernel with 64k pages, the relocated stack has the process's args erroneously stored in the middle of the stack. This means that processes receive no arguments or environment variables, preventing them from running correctly. Fix this by aligning TASK_SIZE on a page boundary. Signed-off-by: Harvey Hunt Cc: David Daney Cc: Paul Burton Cc: James Hogan Cc: linux-kernel@vger.kernel.org --- arch/mips/include/asm/processor.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 3f832c3..b618b40 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -39,13 +39,13 @@ extern unsigned int vced_count, vcei_count; #ifdef CONFIG_32BIT #ifdef CONFIG_KVM_GUEST /* User space process size is limited to 1GB in KVM Guest Mode */ -#define TASK_SIZE0x3fff8000UL +#define TASK_SIZE(0x4000UL - PAGE_SIZE) #else /* * User space process size: 2GB. This is hardcoded into a few places, * so don't change it unless you know what you are doing. */ -#define TASK_SIZE0x7fff8000UL +#define TASK_SIZE(0x7fff8000UL & PAGE_SIZE) Can you check your math here. This doesn't seem correct. Thanks for spotting that - it should have been: (0x7fff8000UL & PAGE_MASK) I'll do a v2 now. #endif #define STACK_TOP_MAXTASK_SIZE @@ -62,7 +62,7 @@ extern unsigned int vced_count, vcei_count; * support 16TB; the architectural reserve for future expansion is * 8192EB ... */ -#define TASK_SIZE320x7fff8000UL +#define TASK_SIZE32(0x7fff8000UL & PAGE_SIZE) Same here. As above. #define TASK_SIZE640x100UL #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) #define STACK_TOP_MAXTASK_SIZE64 Thanks, Harvey
Re: [PATCH] MIPS: Always page align TASK_SIZE
Hi Joshua, On 02/08/2016 01:35 PM, Joshua Kinard wrote: On 02/08/2016 13:15, Harvey Hunt wrote: Hi David, On 02/08/2016 10:11 AM, David Daney wrote: On 02/08/2016 10:05 AM, Harvey Hunt wrote: STACK_TOP_MAX is aligned on a 32k boundary. When __bprm_mm_init() creates an initial stack for a process, it does so using STACK_TOP_MAX as the end of the vma. A process's arguments and environment information are placed on the stack and then the stack is relocated and aligned on a page boundary. When using a 32 bit kernel with 64k pages, the relocated stack has the process's args erroneously stored in the middle of the stack. This means that processes receive no arguments or environment variables, preventing them from running correctly. Fix this by aligning TASK_SIZE on a page boundary. Signed-off-by: Harvey Hunt Cc: David Daney Cc: Paul Burton Cc: James Hogan Cc: linux-kernel@vger.kernel.org --- arch/mips/include/asm/processor.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 3f832c3..b618b40 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -39,13 +39,13 @@ extern unsigned int vced_count, vcei_count; #ifdef CONFIG_32BIT #ifdef CONFIG_KVM_GUEST /* User space process size is limited to 1GB in KVM Guest Mode */ -#define TASK_SIZE0x3fff8000UL +#define TASK_SIZE(0x4000UL - PAGE_SIZE) #else /* * User space process size: 2GB. This is hardcoded into a few places, * so don't change it unless you know what you are doing. */ -#define TASK_SIZE0x7fff8000UL +#define TASK_SIZE(0x7fff8000UL & PAGE_SIZE) Can you check your math here. This doesn't seem correct. Thanks for spotting that - it should have been: (0x7fff8000UL & PAGE_MASK) I'll do a v2 now. FYI, TASK_SIZE was recently changed to 0x8000UL in commit 7f8ca9cb1ed3 on the linux-mips.org tree. Thanks, I'll rebase. #endif #define STACK_TOP_MAXTASK_SIZE @@ -62,7 +62,7 @@ extern unsigned int vced_count, vcei_count; * support 16TB; the architectural reserve for future expansion is * 8192EB ... */ -#define TASK_SIZE320x7fff8000UL +#define TASK_SIZE32(0x7fff8000UL & PAGE_SIZE) Same here. As above. #define TASK_SIZE640x100UL #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) #define STACK_TOP_MAXTASK_SIZE64 Thanks, Harvey
Re: [PATCH] MIPS: Always page align TASK_SIZE
On 02/08/2016 02:08 PM, David Daney wrote: On 02/08/2016 01:48 PM, Harvey Hunt wrote: Hi Joshua, On 02/08/2016 01:35 PM, Joshua Kinard wrote: On 02/08/2016 13:15, Harvey Hunt wrote: Hi David, On 02/08/2016 10:11 AM, David Daney wrote: On 02/08/2016 10:05 AM, Harvey Hunt wrote: STACK_TOP_MAX is aligned on a 32k boundary. When __bprm_mm_init() creates an initial stack for a process, it does so using STACK_TOP_MAX as the end of the vma. A process's arguments and environment information are placed on the stack and then the stack is relocated and aligned on a page boundary. When using a 32 bit kernel with 64k pages, the relocated stack has the process's args erroneously stored in the middle of the stack. This means that processes receive no arguments or environment variables, preventing them from running correctly. Fix this by aligning TASK_SIZE on a page boundary. Signed-off-by: Harvey Hunt Cc: David Daney Cc: Paul Burton Cc: James Hogan Cc: linux-kernel@vger.kernel.org --- arch/mips/include/asm/processor.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 3f832c3..b618b40 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -39,13 +39,13 @@ extern unsigned int vced_count, vcei_count; #ifdef CONFIG_32BIT #ifdef CONFIG_KVM_GUEST /* User space process size is limited to 1GB in KVM Guest Mode */ -#define TASK_SIZE0x3fff8000UL +#define TASK_SIZE(0x4000UL - PAGE_SIZE) #else /* * User space process size: 2GB. This is hardcoded into a few places, * so don't change it unless you know what you are doing. */ -#define TASK_SIZE0x7fff8000UL +#define TASK_SIZE(0x7fff8000UL & PAGE_SIZE) Can you check your math here. This doesn't seem correct. Thanks for spotting that - it should have been: (0x7fff8000UL & PAGE_MASK) I'll do a v2 now. FYI, TASK_SIZE was recently changed to 0x8000UL in commit 7f8ca9cb1ed3 on the linux-mips.org tree. Thanks, I'll rebase. You may find that in rebasing, suddenly you have a completely empty patch! Yeah, I noticed that. I'll just drop this patch... Thanks, Harvey #endif #define STACK_TOP_MAXTASK_SIZE @@ -62,7 +62,7 @@ extern unsigned int vced_count, vcei_count; * support 16TB; the architectural reserve for future expansion is * 8192EB ... */ -#define TASK_SIZE320x7fff8000UL +#define TASK_SIZE32(0x7fff8000UL & PAGE_SIZE) Same here. As above. #define TASK_SIZE640x100UL #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) #define STACK_TOP_MAXTASK_SIZE64 Thanks, Harvey
Re: [PATCH v3 07/52] mtd: nand: core: use mtd_ooblayout_xxx() helpers where appropriate
Hi Boris,
On 26/02/16 00:57, Boris Brezillon wrote:
The mtd_ooblayout_xxx() helper functions have been added to avoid direct
accesses to the ecclayout field, and thus ease for future reworks.
Use these helpers in all places where the oobfree[] and eccpos[] arrays
where directly accessed.
Signed-off-by: Boris Brezillon
---
drivers/mtd/nand/nand_base.c | 183 +++
drivers/mtd/nand/nand_bch.c | 3 +-
2 files changed, 82 insertions(+), 104 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 91672bf..17504f2 100644
[...]
I just pulled your nand/ecclayout branch from github and tested out your
latest patchset "mtd: rework ECC layout definition" on a Ci20
(jz4780_{nand,bch}) and noticed that my board was failing to boot.
I bisected to this patch, here is the kernel's output during boot:
479556d ("mtd: nand: core: use mtd_ooblayout_xxx() helpers where
appropriate"):
[ 0.256349] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x88
[ 0.262860] nand: Micron MT29F64G08CBAAAWP
[ 0.266970] nand: 8192 MiB, MLC, erase size: 2048 KiB, page size: 8192,
OOB size: 448
[ 0.274856] jz4780-nand 1b00.nand-controller: using hardware BCH
(strength 24, size 1024, bytes 42)
[ 0.288982] Bad block table not found for chip 0
[ 0.297673] Bad block table not found for chip 0
[ 0.302328] Scanning device for bad blocks
[ 0.320135] Bad eraseblock 90 at 0x0b40
[ 0.324829] Bad eraseblock 91 at 0x0b60
[ 0.931085] Bad eraseblock 4092 at 0x0001ff80
[ 0.935947] Bad eraseblock 4093 at 0x0001ffa0
[ 0.944878] nand_bbt: error while writing bad block table -34
[ 0.950666] jz4780-nand: probe of 1b00.nand-controller failed with
error -34
[ 0.958302] UBI error: cannot open mtd 3, error -19
[ 0.963002] UBI error: cannot open mtd 4, error -19[ 0.970419] clk: Not
disabling unused clocks
[ 0.975011] UBIFS error (pid: 1): cannot open "ubi1:root", error -19VFS:
Cannot open root device "ubi1:root" or unknown-block(0,0): error -19
[ 0.987810] Please append a correct "root=" boot option; here are the
available partitions:
[ 0.996210] Kernel panic - not syncing: VFS: Unable to mount root fs on
unknown-block(0,0)
[ 1.004498] Rebooting in 10 seconds..
6625d32 ("mtd: use mtd_ooblayout_xxx() helpers where appropriate"):
[ 0.256232] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x88
[ 0.262745] nand: Micron MT29F64G08CBAAAWP
[ 0.266854] nand: 8192 MiB, MLC, erase size: 2048 KiB, page size: 8192,
OOB size: 448
[ 0.274739] jz4780-nand 1b00.nand-controller: using hardware BCH
(strength 24, size 1024, bytes 42)
[ 0.285993] Bad block table found at page 1048320, version 0x01
[ 0.294353] Bad block table found at page 1048064, version 0x01
[ 0.301523] nand_read_bbt: bad block at 0x0b40
[ 0.306677] nand_read_bbt: bad block at 0x0b60
[ 0.312289] 5 ofpart partitions found on MTD device
1b00.nand-controller.1
[ 0.319553] Creating 5 MTD partitions on "1b00.nand-controller.1":
[ 0.326098] 0x-0x0080 : "u-boot-spl"
[ 0.331757] 0x0080-0x00a0 : "u-boot"
[ 0.337185] 0x00a0-0x00c0 : "u-boot-env"
[ 0.342903] 0x00c0-0x04c0 : "boot"
[ 0.348109] 0x04c0-0x0002 : "system"
[ 0.354284] ubi0 error: ubi_attach_mtd_dev: More than 64 PEBs are needed
for fastmap, sorry.
[...]
I'll look into this more later today, but wanted to run it by you in
case you have any thoughts.
Thanks,
Harvey
Re: [PATCH v3 07/52] mtd: nand: core: use mtd_ooblayout_xxx() helpers where appropriate
Hi Boris, On 26/02/16 15:10, Boris Brezillon wrote: Hi Harvey, On Fri, 26 Feb 2016 14:35:08 + Harvey Hunt wrote: [...] I'll look into this more later today, but wanted to run it by you in case you have any thoughts. Can you apply this patch [1], and let me know if you see the additional trace? I applied the patch, the following is the (unchanged) output: [0.256375] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x88 [0.262887] nand: Micron MT29F64G08CBAAAWP [0.266995] nand: 8192 MiB, MLC, erase size: 2048 KiB, page size: 8192, OOB size: 448 [0.274881] jz4780-nand 1b00.nand-controller: using hardware BCH (strength 24, size 1024, bytes 42) [0.289046] Bad block table not found for chip 0 [0.297769] Bad block table not found for chip 0 [0.302425] Scanning device for bad blocks [0.320239] Bad eraseblock 90 at 0x0b40 [0.324934] Bad eraseblock 91 at 0x0b60 [0.931054] Bad eraseblock 4092 at 0x0001ff80 [0.935917] Bad eraseblock 4093 at 0x0001ffa0 [0.944660] nand_bbt: error while writing bad block table -34 [0.950448] jz4780-nand: probe of 1b00.nand-controller failed with error -34 [0.958079] UBI error: cannot open mtd 3, error -19 [0.962788] UBI error: cannot open mtd 4, error -19[0.970229] clk: Not disabling unused clocks Thanks, Boris [1]http://code.bulix.org/l2hkl1-91947 Thanks, Harvey
[PATCH] MIPS: ci20_defconfig: Enable NAND and UBIFS support
Update the Ci20's defconfig to enable the JZ4780's NAND driver and therefore access to the UBIFS rootfs. Signed-off-by: Harvey Hunt Cc: Paul Burton Cc: linux-kernel@vger.kernel.org --- arch/mips/configs/ci20_defconfig | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index 4e36b6e..43e0ba2 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -17,13 +17,12 @@ CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_CGROUP_SCHED=y CONFIG_CGROUP_FREEZER=y -CONFIG_CGROUP_DEVICE=y CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y -CONFIG_MEMCG=y -CONFIG_MEMCG_KMEM=y -CONFIG_CGROUP_SCHED=y CONFIG_NAMESPACES=y CONFIG_USER_NS=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y @@ -52,6 +51,11 @@ CONFIG_DEVTMPFS=y # CONFIG_ALLOW_DEV_COREDUMP is not set CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_MTD=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_JZ4780=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_FASTMAP=y CONFIG_NETDEVICES=y # CONFIG_NET_VENDOR_ARC is not set # CONFIG_NET_CADENCE is not set @@ -103,7 +107,7 @@ CONFIG_PROC_KCORE=y # CONFIG_PROC_PAGE_MONITOR is not set CONFIG_TMPFS=y CONFIG_CONFIGFS_FS=y -# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_UBIFS_FS=y # CONFIG_NETWORK_FILESYSTEMS is not set CONFIG_NLS=y CONFIG_NLS_CODEPAGE_437=y -- 2.7.1
Re: [PATCH v3 07/52] mtd: nand: core: use mtd_ooblayout_xxx() helpers where appropriate
Hi Boris, On 26/02/16 18:33, Boris Brezillon wrote: Hi Harvey, On Fri, 26 Feb 2016 15:17:28 + Harvey Hunt wrote: Hi Boris, On 26/02/16 15:10, Boris Brezillon wrote: Hi Harvey, On Fri, 26 Feb 2016 14:35:08 + Harvey Hunt wrote: [...] I'll look into this more later today, but wanted to run it by you in case you have any thoughts. Can you apply this patch [1], and let me know if you see the additional trace? I applied the patch, the following is the (unchanged) output: [0.256375] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x88 [0.262887] nand: Micron MT29F64G08CBAAAWP [0.266995] nand: 8192 MiB, MLC, erase size: 2048 KiB, page size: 8192, OOB size: 448 [0.274881] jz4780-nand 1b00.nand-controller: using hardware BCH (strength 24, size 1024, bytes 42) [0.289046] Bad block table not found for chip 0 [0.297769] Bad block table not found for chip 0 [0.302425] Scanning device for bad blocks [0.320239] Bad eraseblock 90 at 0x0b40 [0.324934] Bad eraseblock 91 at 0x0b60 [0.931054] Bad eraseblock 4092 at 0x0001ff80 [0.935917] Bad eraseblock 4093 at 0x0001ffa0 [0.944660] nand_bbt: error while writing bad block table -34 [0.950448] jz4780-nand: probe of 1b00.nand-controller failed with error -34 [0.958079] UBI error: cannot open mtd 3, error -19 [0.962788] UBI error: cannot open mtd 4, error -19[0.970229] clk: Not disabling unused clocks Can you test with this one [1]? [1]http://code.bulix.org/36oytz-91960 With that patch applied, my Ci20 successfully boots again. Thanks for looking into it :-) Harvey
Re: [PATCH v3 39/52] mtd: nand: jz4780: switch to mtd_ooblayout_ops
Hi Boris,
On 26/02/16 00:57, Boris Brezillon wrote:
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon
---
drivers/mtd/nand/jz4780_nand.c | 19 +--
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git a/drivers/mtd/nand/jz4780_nand.c b/drivers/mtd/nand/jz4780_nand.c
index e1c016c..b86a579 100644
--- a/drivers/mtd/nand/jz4780_nand.c
+++ b/drivers/mtd/nand/jz4780_nand.c
@@ -56,8 +56,6 @@ struct jz4780_nand_chip {
struct nand_chip chip;
struct list_head chip_list;
- struct nand_ecclayout ecclayout;
-
struct gpio_desc *busy_gpio;
struct gpio_desc *wp_gpio;
unsigned int reading: 1;
@@ -165,8 +163,7 @@ static int jz4780_nand_init_ecc(struct jz4780_nand_chip
*nand, struct device *de
struct nand_chip *chip = &nand->chip;
struct mtd_info *mtd = nand_to_mtd(chip);
struct jz4780_nand_controller *nfc =
to_jz4780_nand_controller(chip->controller);
- struct nand_ecclayout *layout = &nand->ecclayout;
- u32 start, i;
+ int eccbytes;
chip->ecc.bytes = fls((1 + 8) * chip->ecc.size) *
(chip->ecc.strength / 8);
@@ -201,23 +198,17 @@ static int jz4780_nand_init_ecc(struct jz4780_nand_chip
*nand, struct device *de
return 0;
/* Generate ECC layout. ECC codes are right aligned in the OOB area. */
- layout->eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes;
+ eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes;
- if (layout->eccbytes > mtd->oobsize - 2) {
+ if (eccbytes > mtd->oobsize - 2) {
dev_err(dev,
"invalid ECC config: required %d ECC bytes, but only %d are
available",
- layout->eccbytes, mtd->oobsize - 2);
+ eccbytes, mtd->oobsize - 2);
return -EINVAL;
}
- start = mtd->oobsize - layout->eccbytes;
- for (i = 0; i < layout->eccbytes; i++)
- layout->eccpos[i] = start + i;
-
- layout->oobfree[0].offset = 2;
- layout->oobfree[0].length = mtd->oobsize - layout->eccbytes - 2;
+ mtd->ooblayout = &nand_ooblayout_lp_ops;
- chip->ecc.layout = layout;
return 0;
}
With your patch applied [0] that you gave me earlier in the patchset, I
am able to boot to userland on my Ci20 (jz4780_{nand,bch}) with a NAND
rootfs. So, dependant upon that patch (or equivalent) being added to
this patchset:
Tested-by: Harvey Hunt
Thanks,
Harvey
[0] http://code.bulix.org/36oytz-91960
[PATCH] libata: Align ata_device's id on a cacheline
The id buffer in ata_device is a DMA target, but it isn't explicitly
cacheline aligned. Due to this, adjacent fields can be overwritten with
stale data from memory on non coherent architectures. As a result, the
kernel is sometimes unable to communicate with an ATA device.
Fix this by ensuring that the id buffer is cacheline aligned.
This issue is similar to that fixed by Commit 84bda12af31f
("libata: align ap->sector_buf").
Signed-off-by: Harvey Hunt
Cc: linux-kernel@vger.kernel.org
Cc: # 2.6.18
---
This patch is based on libata/for-4.6
include/linux/libata.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/libata.h b/include/linux/libata.h
index bec2abb..2c4ebef 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -720,7 +720,7 @@ struct ata_device {
union {
u16 id[ATA_ID_WORDS]; /* IDENTIFY xxx DEVICE data */
u32 gscr[SATA_PMP_GSCR_DWORDS]; /* PMP GSCR block */
- };
+ } cacheline_aligned;
/* DEVSLP Timing Variables from Identify Device Data Log */
u8 devslp_timing[ATA_LOG_DEVSLP_SIZE];
--
2.7.1
Re: [PATCH v7] mtd: nand: increase ready wait timeout and report timeouts
Hi,
On 25/02/16 23:27, Richard Weinberger wrote:
Am 26.02.2016 um 00:23 schrieb Boris Brezillon:
Regardless, this timeout loop is wrong. Shouldn't it have something like
the following?
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index f2c8ff398d6c..596a9b0503da 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -566,8 +566,8 @@ void nand_wait_ready(struct mtd_info *mtd)
cond_resched();
} while (time_before(jiffies, timeo));
- pr_warn_ratelimited(
- "timeout while waiting for chip to become ready\n");
+ if (!chip->dev_ready(mtd))
+ pr_warn_ratelimited("timeout while waiting for chip to become
ready\n");
out:
led_trigger_event(nand_led_trigger, LED_OFF);
}
Looks good to me.
If you post the patch, you can add
Reviewed-by: Boris Brezillon
Same here.
Reviewed-by: Richard Weinberger
Thanks,
//richard
-cc IMG list (I left it in my gitconfig when I originally sent this
patch...).
Thanks for debugging and fixing this - proposed patch looks good to me:
Reviewed-by: Harvey Hunt
Thanks,
Harvey
Re: [PATCH] mtd: nand: jz4740: Remove unused local variable
Hi Maarten, On 18/04/16 17:04, Maarten ter Huurne wrote: Signed-off-by: Maarten ter Huurne --- drivers/mtd/nand/jz4740_nand.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c index 673ceb2..2f39ee1 100644 --- a/drivers/mtd/nand/jz4740_nand.c +++ b/drivers/mtd/nand/jz4740_nand.c @@ -221,7 +221,6 @@ static int jz_nand_correct_ecc_rs(struct mtd_info *mtd, uint8_t *dat, struct jz_nand *nand = mtd_to_jz_nand(mtd); int i, error_count, index; uint32_t reg, status, error; - uint32_t t; unsigned int timeout = 1000; for (i = 0; i < 9; ++i) Acked-by: Harvey Hunt Thanks, Harvey
Re: [PATCH] mtd: nand: document the NAND controller/NAND chip DT representation
Hi Boris,
On 31/03/16 14:57, Boris Brezillon wrote:
Standardize the NAND controller/NAND chip DT representation. Now, all new
NAND controller drivers should comply with this representation, even if
they are only supporting a single NAND chip.
Existing drivers can keep support for the old representation (where only
the NAND chip was described), but are encouraged to also support the new
one.
Signed-off-by: Boris Brezillon
---
Documentation/devicetree/bindings/mtd/nand.txt | 37 +-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt
b/Documentation/devicetree/bindings/mtd/nand.txt
index b53f92e..fbf5677 100644
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ b/Documentation/devicetree/bindings/mtd/nand.txt
@@ -1,4 +1,23 @@
-* MTD generic binding
+* NAND chip and NAND controller generic binding
+
+NAND controller/NAND chip representation:
+
+The NAND controller should be represented with it's own DT node, and all
s/it's/its/
+NAND chips attached to this controller should be defined as children nodes
+of the NAND controller. This representation should be enforced even for
+simple controllers supporting only one chip.
+
+Mandatory NAND controller properties:
+- #address-cells: depends on your controller. Should at least be 1 to
+ encode the CS line id.
+- #size-cells: depends on your controller. Put zero unless you need a
+ mapping between CS lines and dedicated memory regions
+
+Optional NAND controller properties
+- ranges: only needed if you need to define a mapping between CS lines and
+ memory regions
+
+Optional NAND chip properties:
- nand-ecc-mode : String, operation mode of the NAND ecc mode.
Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
@@ -19,3 +38,19 @@ errors per {size} bytes".
The interpretation of these parameters is implementation-defined, so not all
implementations must support all possible combinations. However,
implementations
are encouraged to further specify the value(s) they support.
+
+Example:
+
+ nand-controller {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* controller specific properties */
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-mode = "soft_bch";
+
+ /* controller specific properties */
Did you mean "chip specific properties"?
+ };
+ };
Thanks,
Harvey
Re: [PATCH] mtd: nand: document the NAND controller/NAND chip DT representation
Hi,
On 31/03/16 16:19, Boris Brezillon wrote:
On Thu, 31 Mar 2016 16:15:26 +0100
Harvey Hunt wrote:
Hi Boris,
On 31/03/16 14:57, Boris Brezillon wrote:
Standardize the NAND controller/NAND chip DT representation. Now, all new
NAND controller drivers should comply with this representation, even if
they are only supporting a single NAND chip.
Existing drivers can keep support for the old representation (where only
the NAND chip was described), but are encouraged to also support the new
one.
Signed-off-by: Boris Brezillon
---
Documentation/devicetree/bindings/mtd/nand.txt | 37
+-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt
b/Documentation/devicetree/bindings/mtd/nand.txt
index b53f92e..fbf5677 100644
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ b/Documentation/devicetree/bindings/mtd/nand.txt
@@ -1,4 +1,23 @@
-* MTD generic binding
+* NAND chip and NAND controller generic binding
+
+NAND controller/NAND chip representation:
+
+The NAND controller should be represented with it's own DT node, and all
s/it's/its/
Yep, I'll fix that.
+NAND chips attached to this controller should be defined as children nodes
+of the NAND controller. This representation should be enforced even for
+simple controllers supporting only one chip.
+
+Mandatory NAND controller properties:
+- #address-cells: depends on your controller. Should at least be 1 to
+ encode the CS line id.
+- #size-cells: depends on your controller. Put zero unless you need a
+ mapping between CS lines and dedicated memory regions
+
+Optional NAND controller properties
+- ranges: only needed if you need to define a mapping between CS lines and
+ memory regions
+
+Optional NAND chip properties:
- nand-ecc-mode : String, operation mode of the NAND ecc mode.
Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
@@ -19,3 +38,19 @@ errors per {size} bytes".
The interpretation of these parameters is implementation-defined, so not all
implementations must support all possible combinations. However,
implementations
are encouraged to further specify the value(s) they support.
+
+Example:
+
+ nand-controller {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* controller specific properties */
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-mode = "soft_bch";
+
+ /* controller specific properties */
Did you mean "chip specific properties"?
No, it's really "controller specific properties". Those are properties
prefixed by the controller vendor name (like 'allwinner,rb' which is
encoding the native ready/busy pin to be attached to this chip).
Okay, I see - I was somewhat confused by it being in the nand chip node,
but I understand what you mean now.
Thanks,
Harvey
Re: [PATCH 01/12] mtd: nand: remove unneeded of_mtd.h inclusions
Hi Boris, On 01/04/16 13:54, Boris Brezillon wrote: Some drivers are including linux/of_mtd.h even if they don't use any of the of_get_nand_xxx() helpers. Signed-off-by: Boris Brezillon --- drivers/mtd/nand/jz4780_nand.c | 1 - drivers/mtd/nand/lpc32xx_mlc.c | 1 - drivers/mtd/nand/qcom_nandc.c | 1 - drivers/mtd/nand/sunxi_nand.c | 1 - drivers/mtd/nand/vf610_nfc.c | 1 - 5 files changed, 5 deletions(-) diff --git a/drivers/mtd/nand/jz4780_nand.c b/drivers/mtd/nand/jz4780_nand.c index e1c016c..23a1999 100644 --- a/drivers/mtd/nand/jz4780_nand.c +++ b/drivers/mtd/nand/jz4780_nand.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include Looks good to me. Acked-by: Harvey Hunt Thanks, Harvey
Re: [PATCH v7,1/3] dt-bindings: binding for jz4780-{nand,bch}
Hi Boris,
On 04/11/15 07:57, Boris Brezillon wrote:
Hi Harvey,
On Tue, 6 Oct 2015 17:27:15 +0100
Harvey Hunt wrote:
From: Alex Smith
Add DT bindings for NAND devices connected to the NEMC on JZ4780 SoCs,
as well as the hardware BCH controller, used by the jz4780_{nand,bch}
drivers.
Patch 3 does not seem to follow this binding: it still uses the
ingenic,ecc-xxx properties and defines NAND timings.
I'll fix this for v8.
Also, as answered to patch 3, I think it would be clearer to separate
the nand controller and nand chip representation.
I agree - I'll implement this in the next version.
Best Regards,
Boris
Thanks,
Harvey Hunt
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Re: [PATCH v7,1/3] dt-bindings: binding for jz4780-{nand,bch}
Hi Boris,
On 04/11/15 07:57, Boris Brezillon wrote:
Hi Harvey,
On Tue, 6 Oct 2015 17:27:15 +0100
Harvey Hunt wrote:
From: Alex Smith
Add DT bindings for NAND devices connected to the NEMC on JZ4780 SoCs,
as well as the hardware BCH controller, used by the jz4780_{nand,bch}
drivers.
Patch 3 does not seem to follow this binding: it still uses the
ingenic,ecc-xxx properties and defines NAND timings.
Thanks, I'll fix that for v8.
Also, as answered to patch 3, I think it would be clearer to separate
the nand controller and nand chip representation.
That approach makes sense - I'll change it for the next series.
Best Regards,
Boris
Best regards,
Harvey Hunt
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Re: [PATCH v7,3/3] MIPS: dts: jz4780/ci20: Add NEMC, BCH and NAND device tree nodes
Hi Boris,
On 04/11/15 07:51, Boris Brezillon wrote:
Paul, Harvey,
On Fri, 16 Oct 2015 11:48:48 +0100
Paul Burton wrote:
On Fri, Oct 16, 2015 at 11:31:12AM +0100, James Hogan wrote:
+
+&nemc {
+ status = "okay";
+
+ nand: nand@1 {
+ compatible = "ingenic,jz4780-nand";
Isn't the NAND a micron part? This doesn't seem right. Is the device
driver and binding already accepted upstream with that compatible
string?
This is the compatible string for the JZ4780 NAND driver, this patch
is part of the series adding that. Detection of the NAND part is
handled by the MTD subsystem.
Right (didn't spot that it was part of a series).
The node appears to describe the NAND interface itself, i.e. a part of
the SoC, so should be in the SoC dtsi file, with overrides in the board
file if necessary for it to work with a particular NAND part
(potentially utilising status="disabled"). Would you agree?
Hi James,
The "nemc" node there is for the Nand & External Memory Controller which
is a hardware block inside the SoC. It has 6 banks (ie. 6 chip select
pins, each associated with a different address range, that connect to
different devices). NAND flash is one such possible device, but a board
could connect it to any of the 6 chip selects, or banks. To represent
that in the SoC dtsi you'd want to have 6 NAND nodes, each disabled by
default, which doesn't make a whole lot of sense to me. Other, non-NAND
devices can connect to the NEMC too - for example the ethernet
controller on the CI20 is connected to one bank.
The NAND device nodes are sort of a mix of describing the NAND flash
(ie. Micron part as you point out) and its connections & properties, the
way the NEMC should be used to interact with it alongside the BCH block,
and the configuration for the NEMC such as timing parameters.
I imagine the most semantically correct means of describing it would
probably be for the compatible string to reflect the Micron NAND part,
and the NEMC driver to pick up on the relevant properties of its child
nodes for configuring timings, whether the device is NAND etc. However
the handling of registering NAND devices with MTD would probably then
have to be part of the NEMC driver, which feels a bit off too.
Another solution would be to describe both the NAND controller and the
NAND chip in the DT (with the NAND chip being a chip of the NAND
controller).
Actually this is already what other binding are doing [1][2]. I know
those bindings are representing NAND controllers which can interface
with more than one NAND chip, but I think that even in the 1:1 case it
would make it clearer to represent both the NAND chip and the NAND
controller.
In your case this would give the following representation
+&nemc {
+ status = "okay";
+
+ nandc: nand-controller@1 {
+ compatible = "ingenic,jz4780-nand";
+ reg = <1 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ingenic,bch-controller = <&bch>;
+
+ nand@0 {
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ nand-ecc-size = <1024>;
+ nand-ecc-strength = <24>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x0 0x0 0x80>;
+ };
+ /* ... */
+
+ };
+ };
+};
I'll implement this in v8 - thanks for the example DT. :-)
Best Regards,
Boris
[1]http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt#L119
[2]http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/mtd/sunxi-nand.txt#L28
Thanks,
Paul
__
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
Best regards,
Harvey Hunt
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Re: [PATCH v7, 2/3] mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs
JZ4780_NEMC_BANK_NAND);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+ chip->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(chip->base))
+ return PTR_ERR(chip->base);
+
+ i++;
+ }
+
+ return 0;
+}
+
+static int jz4780_nand_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ unsigned int num_banks;
+ struct jz4780_nand *nand;
+ struct mtd_info *mtd;
+ struct nand_chip *chip;
+ enum of_gpio_flags flags;
+ struct mtd_part_parser_data ppdata;
+ int ret;
+
+ num_banks = jz4780_nemc_num_banks(dev);
+ if (num_banks == 0) {
+ dev_err(dev, "no banks found\n");
+ return -ENODEV;
+ }
+
+ nand = devm_kzalloc(dev,
+ sizeof(*nand) + (sizeof(nand->chips[0]) * num_banks),
+ GFP_KERNEL);
+ if (!nand)
+ return -ENOMEM;
+
+ nand->dev = dev;
+ nand->num_banks = num_banks;
+ nand->selected = -1;
+
+ mtd = &nand->mtd;
+ chip = &nand->chip;
+ mtd->priv = chip;
+ mtd->owner = THIS_MODULE;
+ mtd->name = DRV_NAME;
+ mtd->dev.parent = dev;
+
+ chip->dn = dev->of_node;
chip->dn has recently been renamed to chip->flash_node.
Thanks, I'll change this.
BTW, If you go for the nand_controller + nand_chip approach, you'll have
to initialize the nand_controller struct and link it with your
nand_chip by doing:
spin_lock_init(&jz4780_ctrl->controller.lock);
init_waitqueue_head(&jz4780_ctrl->controller.wq);
chip->controller = &jz4780_ctrl->controller;
Noted - thanks.
That's all I see for now.
Best Regards,
Boris
Thanks again for the thorough review.
Best regards,
Harvey Hunt
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Re: [PATCH] MIPS: pic32mzda: fix linker error for pic32_get_pbclk().
Hi Purna, On 02/06/16 06:20, Purna Chandra Mandal wrote: Early clock API pic32_get_pbclk() is defined in early_clk.c and used by time.c and early_console.c. When CONFIG_EARLY_PRINTK isn't set, early_clk.c isn't compiled and so a linker error is reported while referring the API from time.c. Maybe "early_clk.c isn't compiled and so time.c fails to link"? Fix it by compiling early_clk.c always. Also sort files in alphabetical order. Cc: Harvey Hunt Cc: Ralf Baechle Cc: linux-m...@linux-mips.org Cc: Joshua Henderson Signed-off-by: Purna Chandra Mandal --- arch/mips/pic32/pic32mzda/Makefile | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/mips/pic32/pic32mzda/Makefile b/arch/mips/pic32/pic32mzda/Makefile index 4a4c272..c286496 100644 --- a/arch/mips/pic32/pic32mzda/Makefile +++ b/arch/mips/pic32/pic32mzda/Makefile @@ -2,8 +2,7 @@ # Joshua Henderson, # Copyright (C) 2015 Microchip Technology, Inc. All rights reserved. # -obj-y := init.o time.o config.o +obj-y := config.o early_clk.o init.o time.o obj-$(CONFIG_EARLY_PRINTK) += early_console.o \ - early_pin.o \ - early_clk.o + early_pin.o Perhaps add: Reported-by: Harvey Hunt Thanks for fixing this, Reviewed-by: Harvey Hunt Thanks, Harvey
Re: [PATCH] MIPS: lib: Mark intrinsics notrace
Hi Ralf, On 29/05/16 22:03, Ralf Baechle wrote: On Wed, May 25, 2016 at 11:06:35AM +0100, Harvey Hunt wrote: On certain MIPS32 devices, the ftrace tracer "function_graph" uses __lshrdi3() during the capturing of trace data. ftrace then attempts to trace __lshrdi3() which leads to infinite recursion and a stack overflow. Fix this by marking __lshrdi3() as notrace. Mark the other compiler intrinsics as notrace in case the compiler decides to use them in the ftrace path. Makes perfect sense - but I'm wondering how you triggered it. Was this a build with the GCC option -Os that is CONFIG_CC_OPTIMIZE_FOR_SIZE? Usually people build with CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE that is -O2 which results in intrinsics being inlined. This is triggered by building with CONFIG_CC_OPTIMIZE_FOR_SIZE. This explains why I only saw it on certain MIPS32 devices - Malta's defconfigs don't have CONFIG_CC_OPTIMIZE_FOR_SIZE enabled, but the pistachio and Ci20 defconfigs do. Ralf Thanks, Harvey
[PATCH] MIPS: tools: Fix relocs tool compiler warnings
When using clang as HOSTCC, the following warnings appear:
In file included from arch/mips/boot/tools/relocs_64.c:27:0:
arch/mips/boot/tools/relocs.c: In function ‘read_relocs’:
arch/mips/boot/tools/relocs.c:397:4: warning: dereferencing type-punned pointer
will break strict-aliasing rules [-Wstrict-aliasing]
ELF_R_SYM(rel->r_info) = elf32_to_cpu(ELF_R_SYM(rel->r_info));
^
arch/mips/boot/tools/relocs.c:397:4: warning: dereferencing type-punned pointer
will break strict-aliasing rules [-Wstrict-aliasing]
arch/mips/boot/tools/relocs.c: In function ‘walk_relocs’:
arch/mips/boot/tools/relocs.c:491:4: warning: dereferencing type-punned pointer
will break strict-aliasing rules [-Wstrict-aliasing]
Elf_Sym *sym = &sh_symtab[ELF_R_SYM(rel->r_info)];
^~~
arch/mips/boot/tools/relocs.c: In function ‘do_reloc’:
arch/mips/boot/tools/relocs.c:502:2: warning: dereferencing type-punned pointer
will break strict-aliasing rules [-Wstrict-aliasing]
unsigned r_type = ELF_R_TYPE(rel->r_info);
^~~~
arch/mips/boot/tools/relocs.c: In function ‘do_reloc_info’:
arch/mips/boot/tools/relocs.c:641:3: warning: dereferencing type-punned pointer
will break strict-aliasing rules [-Wstrict-aliasing]
rel_type(ELF_R_TYPE(rel->r_info)),
^~~~
Fix them by making Elf64_Mips_Rela a union
Signed-off-by: Harvey Hunt
Cc: Matt Redfearn
Cc: linux-m...@linux-mips.org
Cc: linux-kernel@vger.kernel.org
---
arch/mips/boot/tools/relocs_64.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/arch/mips/boot/tools/relocs_64.c b/arch/mips/boot/tools/relocs_64.c
index b671b5e..06066e6a 100644
--- a/arch/mips/boot/tools/relocs_64.c
+++ b/arch/mips/boot/tools/relocs_64.c
@@ -9,17 +9,20 @@
typedef uint8_t Elf64_Byte;
-typedef struct {
- Elf64_Word r_sym; /* Symbol index. */
- Elf64_Byte r_ssym; /* Special symbol. */
- Elf64_Byte r_type3; /* Third relocation. */
- Elf64_Byte r_type2; /* Second relocation. */
- Elf64_Byte r_type; /* First relocation. */
+typedef union {
+ struct {
+ Elf64_Word r_sym; /* Symbol index. */
+ Elf64_Byte r_ssym; /* Special symbol. */
+ Elf64_Byte r_type3; /* Third relocation. */
+ Elf64_Byte r_type2; /* Second relocation. */
+ Elf64_Byte r_type; /* First relocation. */
+ } fields;
+ Elf64_Xword unused;
} Elf64_Mips_Rela;
#define ELF_CLASS ELFCLASS64
-#define ELF_R_SYM(val) (((Elf64_Mips_Rela *)(&val))->r_sym)
-#define ELF_R_TYPE(val) (((Elf64_Mips_Rela *)(&val))->r_type)
+#define ELF_R_SYM(val) (((Elf64_Mips_Rela *)(&val))->fields.r_sym)
+#define ELF_R_TYPE(val) (((Elf64_Mips_Rela *)(&val))->fields.r_type)
#define ELF_ST_TYPE(o) ELF64_ST_TYPE(o)
#define ELF_ST_BIND(o) ELF64_ST_BIND(o)
#define ELF_ST_VISIBILITY(o)ELF64_ST_VISIBILITY(o)
--
2.8.3
[PATCH] MIPS: Factor o32 specific code into signal_o32.c
The commit ebb5e78cc634 ("MIPS: Initial implementation of a VDSO")
caused building a 64 bit kernel with support for n32 and not o32
to produce a build error:
arch/mips/kernel/signal32.c:415:11: error: ‘vdso_image_o32’ undeclared here
(not in a function)
.vdso = &vdso_image_o32,
Fix this by moving the o32 specific code into signal_o32.c and
updating the Makefile accordingly.
Signed-off-by: Harvey Hunt
Cc: Leonid Yegoshin
Cc: Alex Smith
Cc: linux-m...@linux-mips.org
Cc: linux-kernel@vger.kernel.org
---
arch/mips/include/asm/signal.h | 2 +-
arch/mips/kernel/Makefile | 2 +-
arch/mips/kernel/signal32.c| 288 +
arch/mips/kernel/signal_o32.c | 285
4 files changed, 293 insertions(+), 284 deletions(-)
create mode 100644 arch/mips/kernel/signal_o32.c
diff --git a/arch/mips/include/asm/signal.h b/arch/mips/include/asm/signal.h
index 2292373..77b3b95 100644
--- a/arch/mips/include/asm/signal.h
+++ b/arch/mips/include/asm/signal.h
@@ -11,7 +11,7 @@
#include
-#ifdef CONFIG_MIPS32_COMPAT
+#ifdef CONFIG_MIPS32_O32
extern struct mips_abi mips_abi_32;
#define sig_uses_siginfo(ka, abi) \
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index e6053d0..4a603a3 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -71,7 +71,7 @@ obj-$(CONFIG_32BIT) += scall32-o32.o
obj-$(CONFIG_64BIT)+= scall64-64.o
obj-$(CONFIG_MIPS32_COMPAT)+= linux32.o ptrace32.o signal32.o
obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o
-obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o
+obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o signal_o32.o
obj-$(CONFIG_KGDB) += kgdb.o
obj-$(CONFIG_PROC_FS) += proc.o
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 78c8349..97b7c51 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -6,129 +6,26 @@
* Copyright (C) 1991, 1992 Linus Torvalds
* Copyright (C) 1994 - 2000, 2006 Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2016, Imagination Technologies Ltd.
*/
-#include
-#include
-#include
-#include
-#include
+#include
+#include
#include
#include
#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
+#include
#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
+#include
+#include
#include "signal-common.h"
-/*
- * Including would give use the 64-bit syscall numbers ...
- */
-#define __NR_O32_restart_syscall 4253
-
/* 32-bit compatibility types */
typedef unsigned int __sighandler32_t;
typedef void (*vfptr_t)(void);
-struct ucontext32 {
- u32 uc_flags;
- s32 uc_link;
- compat_stack_t uc_stack;
- struct sigcontext32 uc_mcontext;
- compat_sigset_t uc_sigmask; /* mask last for extensibility */
-};
-
-struct sigframe32 {
- u32 sf_ass[4]; /* argument save space for o32 */
- u32 sf_pad[2]; /* Was: signal trampoline */
- struct sigcontext32 sf_sc;
- compat_sigset_t sf_mask;
-};
-
-struct rt_sigframe32 {
- u32 rs_ass[4]; /* argument save space for o32 */
- u32 rs_pad[2]; /* Was: signal trampoline */
- compat_siginfo_t rs_info;
- struct ucontext32 rs_uc;
-};
-
-static int setup_sigcontext32(struct pt_regs *regs,
- struct sigcontext32 __user *sc)
-{
- int err = 0;
- int i;
-
- err |= __put_user(regs->cp0_epc, &sc->sc_pc);
-
- err |= __put_user(0, &sc->sc_regs[0]);
- for (i = 1; i < 32; i++)
- err |= __put_user(regs->regs[i], &sc->sc_regs[i]);
-
- err |= __put_user(regs->hi, &sc->sc_mdhi);
- err |= __put_user(regs->lo, &sc->sc_mdlo);
- if (cpu_has_dsp) {
- err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp);
- err |= __put_user(mfhi1(), &sc->sc_hi1);
- err |= __put_user(mflo1(), &sc->sc_lo1);
- err |= __put_user(mfhi2(), &sc->sc_hi2);
- err |= __put_user(mflo2(), &sc->sc_lo2);
- err |= __put_user(mfhi3(), &sc->sc_hi3);
- err |= __put_user(mflo3(), &sc->sc_lo3);
- }
-
- /*
-* Save FPU state to signal context. Signal handler
-* will "inherit" current FPU state.
-*/
- err |= protected_save_fp_context(sc);
-
- return err;
-}
-
-static int restore_sigcontext32(struct pt_regs *regs,
- struct sigcontext32 __user *sc)
-{
- int err = 0;
- s3
[PATCH] MAINTAINERS: Add maintainer entry for Ingenic JZ4780 NAND driver
Signed-off-by: Harvey Hunt Cc: Zubair Lutfullah Kakakhel Cc: linux-...@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 71aa5da..28d2d5f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5992,6 +5992,12 @@ M: Zubair Lutfullah Kakakhel S: Maintained F: drivers/dma/dma-jz4780.c +INGENIC JZ4780 NAND DRIVER +M: Harvey Hunt +L: linux-...@lists.infradead.org +S: Maintained +F: drivers/mtd/nand/jz4780_* + INTEGRITY MEASUREMENT ARCHITECTURE (IMA) M: Mimi Zohar M: Dmitry Kasatkin -- 2.9.3
[PATCH] mtd: nand: jz4780: Update MODULE_AUTHOR email address
Emails will bounce from my imgtec address, so update it to a new one.
Signed-off-by: Harvey Hunt
Cc: Harvey Hunt
Cc: linux-...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
drivers/mtd/nand/jz4780_bch.c | 2 +-
drivers/mtd/nand/jz4780_nand.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/jz4780_bch.c b/drivers/mtd/nand/jz4780_bch.c
index d74f4ba..731c605 100644
--- a/drivers/mtd/nand/jz4780_bch.c
+++ b/drivers/mtd/nand/jz4780_bch.c
@@ -375,6 +375,6 @@ static struct platform_driver jz4780_bch_driver = {
module_platform_driver(jz4780_bch_driver);
MODULE_AUTHOR("Alex Smith ");
-MODULE_AUTHOR("Harvey Hunt ");
+MODULE_AUTHOR("Harvey Hunt ");
MODULE_DESCRIPTION("Ingenic JZ4780 BCH error correction driver");
MODULE_LICENSE("GPL v2");
diff --git a/drivers/mtd/nand/jz4780_nand.c b/drivers/mtd/nand/jz4780_nand.c
index daf3c42..175f67d 100644
--- a/drivers/mtd/nand/jz4780_nand.c
+++ b/drivers/mtd/nand/jz4780_nand.c
@@ -412,6 +412,6 @@ static struct platform_driver jz4780_nand_driver = {
module_platform_driver(jz4780_nand_driver);
MODULE_AUTHOR("Alex Smith ");
-MODULE_AUTHOR("Harvey Hunt ");
+MODULE_AUTHOR("Harvey Hunt ");
MODULE_DESCRIPTION("Ingenic JZ4780 NAND driver");
MODULE_LICENSE("GPL v2");
--
2.9.0
Re: [PATCH 3/5] rtc: rtc-jz4740: Add support for devicetree
Hi Alexandre,
On 17/03/16 12:08, Alexandre Belloni wrote:
On 05/03/2016 at 23:38:49 +0100, Paul Cercueil wrote :
Signed-off-by: Paul Cercueil
---
drivers/rtc/rtc-jz4740.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c
index 47617bd..3914b1c 100644
--- a/drivers/rtc/rtc-jz4740.c
+++ b/drivers/rtc/rtc-jz4740.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -245,6 +246,13 @@ void jz4740_rtc_poweroff(struct device *dev)
}
EXPORT_SYMBOL_GPL(jz4740_rtc_poweroff);
+static const struct of_device_id jz4740_rtc_of_match[] = {
+ { .compatible = "ingenic,jz4740-rtc", .data = (void *) ID_JZ4740 },
+ { .compatible = "ingenic,jz4780-rtc", .data = (void *) ID_JZ4780 },
ingenic is not in Documentation/devicetree/bindings/vendor-prefixes.txt,
you have to add it there before using it.
Ingenic is in vendor-prefixes.txt - it was added by Commit f289cc7
("devicetree/bindings: add Ingenic Semiconductor vendor prefix").
Thanks,
Harvey
[PATCH] clk: ingenic: Allow divider value to be right shifted
The JZ4780's MSC clock divider registers multiply the clock divider
by 2. This means that MSC devices run at half their expected speed.
Shift the clock divider for the affected registers to solve this.
Signed-off-by: Harvey Hunt
---
drivers/clk/ingenic/cgu.c| 11 ++-
drivers/clk/ingenic/cgu.h| 6 +-
drivers/clk/ingenic/jz4740-cgu.c | 24
drivers/clk/ingenic/jz4780-cgu.c | 38 +++---
4 files changed, 46 insertions(+), 33 deletions(-)
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index 7cfb7b2..8333bd0 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -325,6 +325,7 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long
parent_rate)
div = (div_reg >> clk_info->div.shift) &
GENMASK(clk_info->div.bits - 1, 0);
div += 1;
+ div <<= clk_info->div.div;
rate /= div;
}
@@ -345,6 +346,14 @@ ingenic_clk_calc_div(const struct ingenic_cgu_clk_info
*clk_info,
div = min_t(unsigned, div, 1 << clk_info->div.bits);
div = max_t(unsigned, div, 1);
+ /*
+* If the divider value itself must be divided before being written to
+* the divider register, we must ensure we don't have any bits set that
+* would be lost as a result of doing so.
+*/
+ div >>= clk_info->div.div;
+ div <<= clk_info->div.div;
+
return div;
}
@@ -395,7 +404,7 @@ ingenic_clk_set_rate(struct clk_hw *hw, unsigned long
req_rate,
/* update the divide */
mask = GENMASK(clk_info->div.bits - 1, 0);
reg &= ~(mask << clk_info->div.shift);
- reg |= (div - 1) << clk_info->div.shift;
+ reg |= ((div >> clk_info->div.div) - 1) << clk_info->div.shift;
/* clear the stop bit */
if (clk_info->div.stop_bit != -1)
diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h
index 99347e2..bdeac6c 100644
--- a/drivers/clk/ingenic/cgu.h
+++ b/drivers/clk/ingenic/cgu.h
@@ -76,8 +76,11 @@ struct ingenic_cgu_mux_info {
/**
* struct ingenic_cgu_div_info - information about a divider
* @reg: offset of the divider control register within the CGU
- * @shift: number of bits to shift the divide value by (ie. the index of
+ * @shift: number of bits to left shift the divide value by (ie. the index of
* the lowest bit of the divide value within its control register)
+ * @div: number of bits to right shift the divide value by (i.e. if the
+ * effective divider value is the value written to the register
+ * multiplied by some constant)
* @bits: the size of the divide value in bits
* @ce_bit: the index of the change enable bit within reg, or -1 if there
* isn't one
@@ -87,6 +90,7 @@ struct ingenic_cgu_mux_info {
struct ingenic_cgu_div_info {
unsigned reg;
u8 shift;
+ u8 div;
u8 bits;
s8 ce_bit;
s8 busy_bit;
diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index 305a26c2..8d0ebad 100644
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -90,51 +90,51 @@ static const struct ingenic_cgu_clk_info
jz4740_cgu_clocks[] = {
[JZ4740_CLK_PLL_HALF] = {
"pll half", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
- .div = { CGU_REG_CPCCR, 21, 1, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 21, 0, 1, -1, -1, -1 },
},
[JZ4740_CLK_CCLK] = {
"cclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
- .div = { CGU_REG_CPCCR, 0, 4, 22, -1, -1 },
+ .div = { CGU_REG_CPCCR, 0, 0, 4, 22, -1, -1 },
},
[JZ4740_CLK_HCLK] = {
"hclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
- .div = { CGU_REG_CPCCR, 4, 4, 22, -1, -1 },
+ .div = { CGU_REG_CPCCR, 4, 0, 4, 22, -1, -1 },
},
[JZ4740_CLK_PCLK] = {
"pclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
- .div = { CGU_REG_CPCCR, 8, 4, 22, -1, -1 },
+ .div = { CGU_REG_CPCCR, 8, 0, 4, 22, -1, -1 },
},
[JZ4740_CLK_MCLK] = {
"mclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
- .div = { CGU_REG_CPCCR, 12, 4, 22, -1, -1 },
+ .div = { CGU_REG_CPCCR, 12, 0, 4, 22, -1, -1 },
},
[JZ4740_CLK_LCD] = {
"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -
[PATCH v10 1/3] dt-bindings: binding for jz4780-{nand,bch}
From: Alex Smith
Add DT bindings for NAND devices connected to the NEMC on JZ4780 SoCs,
as well as the hardware BCH controller, used by the jz4780_{nand,bch}
drivers.
Signed-off-by: Alex Smith
Cc: Zubair Lutfullah Kakakhel
Cc: David Woodhouse
Cc: Brian Norris
Cc: linux-...@lists.infradead.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: r...@kernel.org
Signed-off-by: Harvey Hunt
Acked-by: Rob Herring
---
v9 -> v10:
- Added Rob Herring's Acked-by.
v8 -> v9:
- Document that partitions are represented as a child node of a NAND chip.
v7 -> v8:
- Describe how NAND chips are now child nodes of the NAND controller.
v6 -> v7:
- Add nand-ecc-mode to DT bindings.
- Add nand-on-flash-bbt to DT bindings.
v5 -> v6:
- No change.
v4 -> v5:
- Rename ingenic,bch-device to ingenic,bch-controller to fit with
existing convention.
v3 -> v4:
- No change
v2 -> v3:
- Rebase to 4.0-rc6
- Changed ingenic,ecc-size to common nand-ecc-step-size
- Changed ingenic,ecc-strength to common nand-ecc-strength
- Changed ingenic,busy-gpio to common rb-gpios
- Changed ingenic,wp-gpio to common wp-gpios
v1 -> v2:
- Rebase to 4.0-rc3
.../bindings/mtd/ingenic,jz4780-nand.txt | 86 ++
1 file changed, 86 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
new file mode 100644
index 000..29ea585
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
@@ -0,0 +1,86 @@
+* Ingenic JZ4780 NAND/BCH
+
+This file documents the device tree bindings for NAND flash devices on the
+JZ4780. NAND devices are connected to the NEMC controller (described in
+memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
+be children of the NEMC node.
+
+Required NAND controller device properties:
+- compatible: Should be set to "ingenic,jz4780-nand".
+- reg: For each bank with a NAND chip attached, should specify a bank number,
+ an offset of 0 and a size of 0x100 (i.e. the whole NEMC bank).
+
+Optional NAND controller device properties:
+- ingenic,bch-controller: To make use of the hardware BCH controller, this
+ property must contain a phandle for the BCH controller node. The required
+ properties for this node are described below. If this is not specified,
+ software BCH will be used instead.
+
+Optional children nodes:
+- Individual NAND chips are children of the NAND controller node.
+
+Required children node properties:
+- reg: An integer ranging from 1 to 6 representing the CS line to use.
+
+Optional children node properties:
+- nand-ecc-step-size: ECC block size in bytes.
+- nand-ecc-strength: ECC strength (max number of correctable bits).
+- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default
+- nand-on-flash-bbt: boolean to enable on flash bbt option, if not present
false
+- rb-gpios: GPIO specifier for the busy pin.
+- wp-gpios: GPIO specifier for the write protect pin.
+
+Optional child node of NAND chip nodes:
+- partitions: see Documentation/devicetree/bindings/mtd/partition.txt
+
+Example:
+
+nemc: nemc@1341 {
+ ...
+
+ nandc: nand-controller@1 {
+ compatible = "ingenic,jz4780-nand";
+ reg = <1 0 0x100>; /* Bank 1 */
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ingenic,bch-controller = <&bch>;
+
+ nand@1 {
+ reg = <1>;
+
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+
+ rb-gpios = <&gpa 20 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpf 22 GPIO_ACTIVE_LOW>;
+
+ partitions {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ...
+ }
+ };
+ };
+};
+
+The BCH controller is a separate SoC component used for error correction on
+NAND devices. The following is a description of the device properties for a
+BCH controller.
+
+Required BCH properties:
+- compatible: Should be set to "ingenic,jz4780-bch".
+- reg: Should specify the BCH controller registers location and length.
+- clocks: Clock for the BCH controller.
+
+Example:
+
+bch: bch@134d {
+ compatible = "ingenic,jz4780-bch";
+ reg = <0x134d 0x1>;
+
+ clocks = <&cgu JZ4780_CLK_BCH>;
+};
--
2.6.4
--
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[PATCH v10 3/3] MIPS: dts: jz4780/ci20: Add NEMC, BCH and NAND device tree nodes
From: Alex Smith
Add device tree nodes for the NEMC and BCH to the JZ4780 device tree,
and make use of them in the Ci20 device tree to add a node for the
board's NAND.
Note that since the pinctrl driver is not yet upstream, this includes
neither pin configuration nor busy/write-protect GPIO pins for the
NAND. Use of the NAND relies on the boot loader to have left the pins
configured in a usable state, which should be the case when booted
from the NAND.
Signed-off-by: Alex Smith
Cc: Zubair Lutfullah Kakakhel
Cc: David Woodhouse
Cc: Brian Norris
Cc: Paul Burton
Cc: linux-...@lists.infradead.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-m...@linux-mips.org
Cc: r...@kernel.org
Signed-off-by: Harvey Hunt
---
v9 -> v10:
- No change.
v8 -> v9:
- Represent the partition table as a subnode of a NAND chip.
v7 -> v8:
- Describe the NAND chips as children nodes of the NAND controller.
- Remove ingenic, prefix from ECC settings.
- Renamed some ECC settings.
v6 -> v7:
- Add nand-ecc-mode to DT.
- Add nand-on-flash-bbt to DT.
v4 -> v5:
- New patch adding DT nodes for the NAND so that the driver can be
tested.
arch/mips/boot/dts/ingenic/ci20.dts| 63 ++
arch/mips/boot/dts/ingenic/jz4780.dtsi | 26 ++
2 files changed, 89 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
b/arch/mips/boot/dts/ingenic/ci20.dts
index 9fcb9e7..782258c 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -42,3 +42,66 @@
&uart4 {
status = "okay";
};
+
+&nemc {
+ status = "okay";
+
+ nandc: nand-controller@1 {
+ compatible = "ingenic,jz4780-nand";
+ reg = <1 0 0x100>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ingenic,bch-controller = <&bch>;
+
+ ingenic,nemc-tAS = <10>;
+ ingenic,nemc-tAH = <5>;
+ ingenic,nemc-tBP = <10>;
+ ingenic,nemc-tAW = <15>;
+ ingenic,nemc-tSTRV = <100>;
+
+ nand@1 {
+ reg = <1>;
+
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+
+ partitions {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x0 0x0 0x80>;
+ };
+
+ partition@0x80 {
+ label = "u-boot";
+ reg = <0x0 0x80 0x0 0x20>;
+ };
+
+ partition@0xa0 {
+ label = "u-boot-env";
+ reg = <0x0 0xa0 0x0 0x20>;
+ };
+
+ partition@0xc0 {
+ label = "boot";
+ reg = <0x0 0xc0 0x0 0x400>;
+ };
+
+ partition@0x8c0 {
+ label = "system";
+ reg = <0x0 0x4c0 0x1 0xfb40>;
+ };
+ };
+ };
+ };
+};
+
+&bch {
+ status = "okay";
+};
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index 65389f6..b868b42 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -108,4 +108,30 @@
status = "disabled";
};
+
+ nemc: nemc@1341 {
+ compatible = "ingenic,jz4780-nemc";
+ reg = <0x1341 0x1>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0x1b00 0x100
+ 2 0 0x1a00 0x100
+ 3 0 0x1900 0x100
+ 4 0 0x1800 0x100
+ 5 0 0x1700 0x100
+ 6 0 0x1600 0x100>;
+
+ clocks = <&cgu JZ4780_CLK_NEMC>;
+
+ status = "disabled";
+ };
+
+ bch: bch@134d {
+ compatible = "inge
[PATCH v10 2/3] mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs
From: Alex Smith
Add a driver for NAND devices connected to the NEMC on JZ4780 SoCs, as
well as the hardware BCH controller. DMA is not currently implemented.
While older 47xx SoCs also have a BCH controller, they are incompatible
with the one in the 4780 due to differing register/bit positions, which
would make implementing a common driver for them quite messy.
Signed-off-by: Alex Smith
Cc: Zubair Lutfullah Kakakhel
Cc: David Woodhouse
Cc: Brian Norris
Cc: linux-...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Harvey Hunt
---
v9 -> v10:
- Replace uint{8,32}_t with u{8,32}.
- Only set IO_ADDR_{R,W} during chip init.
- Check that ECC layout fits into OOB area.
- Rebase onto l2-mtd/master and use its new functions.
- Remove mtd field from jz4780_nand_chip.
- Tidied up jz4780_nand_cmd_ctrl.
- Corrected ECC mode print statement.
- Refactor BCH code.
- Implement of_jz4780_bch_get.
- Update Authorship.
- Use a mutex to protect accesses to BCH controller.
- Update code documentation.
- Checkpatch cleanup.
v8 -> v9:
- No change.
v7 -> v8:
- Rebase to 4.4-rc3.
- Add _US suffixes to time constants.
- Add locking to BCH hardware accesses.
- Don't print ECC info if ECC is not being used.
- Default to No ECC.
- Let the NAND core handle ECC layout in certain cases.
- Use the gpio_desc consumer interface.
- Removed gpio active low flags.
- Check for the BCH controller before initialising a chip.
- Add a jz4780_nand_controller struct.
- Initialise chips by iterating over DT child nodes.
v6 -> v7:
- Add nand-ecc-mode to DT bindings.
- Add nand-on-flash-bbt to DT bindings.
v5 -> v6:
- No change.
v4 -> v5:
- Rename ingenic,bch-device to ingenic,bch-controller to fit with
existing convention.
v3 -> v4:
- No change
v2 -> v3:
- Rebase to 4.0-rc6
- Changed ingenic,ecc-size to common nand-ecc-step-size
- Changed ingenic,ecc-strength to common nand-ecc-strength
- Changed ingenic,busy-gpio to common rb-gpios
- Changed ingenic,wp-gpio to common wp-gpios
v1 -> v2:
- Rebase to 4.0-rc3
drivers/mtd/nand/Kconfig | 7 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/jz4780_bch.c | 381 +
drivers/mtd/nand/jz4780_bch.h | 44 +
drivers/mtd/nand/jz4780_nand.c | 416 +
5 files changed, 849 insertions(+)
create mode 100644 drivers/mtd/nand/jz4780_bch.c
create mode 100644 drivers/mtd/nand/jz4780_bch.h
create mode 100644 drivers/mtd/nand/jz4780_nand.c
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 2896640..b742adc 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -519,6 +519,13 @@ config MTD_NAND_JZ4740
help
Enables support for NAND Flash on JZ4740 SoC based boards.
+config MTD_NAND_JZ4780
+ tristate "Support for NAND on JZ4780 SoC"
+ depends on MACH_JZ4780 && JZ4780_NEMC
+ help
+ Enables support for NAND Flash connected to the NEMC on JZ4780 SoC
+ based boards, using the BCH controller for hardware error correction.
+
config MTD_NAND_FSMC
tristate "Support for NAND on ST Micros FSMC"
depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 2c7f014..9e36233 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC)+= mpc5121_nfc.o
obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
+obj-$(CONFIG_MTD_NAND_JZ4780) += jz4780_nand.o jz4780_bch.o
obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
obj-$(CONFIG_MTD_NAND_XWAY)+= xway_nand.o
obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
diff --git a/drivers/mtd/nand/jz4780_bch.c b/drivers/mtd/nand/jz4780_bch.c
new file mode 100644
index 000..22d3729
--- /dev/null
+++ b/drivers/mtd/nand/jz4780_bch.c
@@ -0,0 +1,381 @@
+/*
+ * JZ4780 BCH controller
+ *
+ * Copyright (c) 2015 Imagination Technologies
+ * Author: Alex Smith
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "jz4780_bch.h"
+
+#define BCH_BHCR 0x0
+#define BCH_BHCCR 0x8
+#define BCH_BHCNT 0xc
+#define BCH_BHDR 0x10
+#define BCH_BHPAR0 0x14
+#define BCH_BHERR0 0x84
+#define BCH_BHINT 0x184
+#define BCH_BHINTES0
[PATCH 1/2] MIPS: Ci20: Enable GPIO driver
Update the Ci20's defconfig to enable the JZ4780's GPIO driver. Signed-off-by: Harvey Hunt Cc: linux-m...@linux-mips.org Cc: linux-kernel@vger.kernel.org --- Ralf, both of these patches rely on Paul Cercueil's pinctrl and gpio patches from Linus Walleij's 4.13 pinctrl pull request. arch/mips/configs/ci20_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index 43e0ba2..ce317ff 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -92,6 +92,7 @@ CONFIG_SERIAL_OF_PLATFORM=y CONFIG_I2C=y CONFIG_I2C_JZ4780=y CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_INGENIC=y # CONFIG_HWMON is not set CONFIG_REGULATOR=y CONFIG_REGULATOR_DEBUG=y -- 2.7.4
[PATCH 2/2] MIPS: dts: Ci20: Add ethernet and fixed-regulator nodes
Add devicetree nodes for the DM9000 and the ethernet power regulator.
Additionally, add a new pinctrl node for the ethernet chip's pins.
Signed-off-by: Harvey Hunt
Cc: Zubair Lutfullah Kakakhel
Cc: Paul Burton
Cc: Rob Herring
Cc: Mark Rutland
Cc: Paul Cercueil
Cc: Linus Walleij
Cc: devicet...@vger.kernel.org
Cc: linux-m...@linux-mips.org
Cc: linux-kernel@vger.kernel.org
---
Ralf, both of these patches rely on Paul Cercueil's pinctrl
and gpio patches from Linus Walleij's 4.13 pinctrl pull request.
arch/mips/boot/dts/ingenic/ci20.dts | 37 +
1 file changed, 37 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
b/arch/mips/boot/dts/ingenic/ci20.dts
index fd138d99..6c38184 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -1,6 +1,7 @@
/dts-v1/;
#include "jz4780.dtsi"
+#include
/ {
compatible = "img,ci20", "ingenic,jz4780";
@@ -21,6 +22,13 @@
reg = <0x0 0x1000
0x3000 0x3000>;
};
+
+ eth0_power: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "eth0_power";
+ gpio = <&gpb 25 GPIO_ACTIVE_LOW>;
+ enable-active-high;
+ };
};
&ext {
@@ -123,6 +131,29 @@
};
};
};
+
+ dm9000@6 {
+ compatible = "davicom,dm9000";
+ davicom,no-eeprom;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc_cs6>;
+
+ reg = <6 0 1 /* addr */
+ 6 2 1>; /* data */
+
+ ingenic,nemc-tAS = <15>;
+ ingenic,nemc-tAH = <10>;
+ ingenic,nemc-tBP = <20>;
+ ingenic,nemc-tAW = <50>;
+ ingenic,nemc-tSTRV = <100>;
+
+ reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>;
+ vcc-supply = <ð0_power>;
+
+ interrupt-parent = <&gpe>;
+ interrupts = <19 4>;
+ };
};
&bch {
@@ -165,4 +196,10 @@
groups = "nemc-cs1";
bias-disable;
};
+
+ pins_nemc_cs6: nemc-cs6 {
+ function = "nemc-cs6";
+ groups = "nemc-cs6";
+ bias-disable;
+ };
};
--
2.7.4
[PATCH 1/2] MIPS: ralink: Fix build error due to missing header
Previously, was included before ralink_regs.h in all
ralink files - leading to being implicitly included.
After commit 26dd3e4ff9ac ("MIPS: Audit and remove any unnecessary
uses of module.h") removed the inclusion of module.h from multiple
places, some ralink platforms failed to build with the following error:
In file included from arch/mips/ralink/mt7620.c:17:0:
./arch/mips/include/asm/mach-ralink/ralink_regs.h: In function ‘rt_sysc_w32’:
./arch/mips/include/asm/mach-ralink/ralink_regs.h:38:2: error: implicit
declaration of function ‘__raw_writel’ [-Werror=implicit-function-declaration]
__raw_writel(val, rt_sysc_membase + reg);
^
./arch/mips/include/asm/mach-ralink/ralink_regs.h: In function ‘rt_sysc_r32’:
./arch/mips/include/asm/mach-ralink/ralink_regs.h:43:2: error: implicit
declaration of function ‘__raw_readl’ [-Werror=implicit-function-declaration]
return __raw_readl(rt_sysc_membase + reg);
Fix this by including .
Signed-off-by: Harvey Hunt
Fixes: 26dd3e4ff9ac ("MIPS: Audit and remove any unnecessary uses of module.h")
Cc: #4.11+
Cc: John Crispin
Cc: linux-m...@linux-mips.org
Cc: linux-kernel@vger.kernel.org
---
arch/mips/include/asm/mach-ralink/ralink_regs.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h
b/arch/mips/include/asm/mach-ralink/ralink_regs.h
index 9df1a53..b4e7dfa 100644
--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
@@ -13,6 +13,8 @@
#ifndef _RALINK_REGS_H_
#define _RALINK_REGS_H_
+#include
+
enum ralink_soc_type {
RALINK_UNKNOWN = 0,
RT2880_SOC,
--
2.7.4
[PATCH 2/2] MIPS: ralink: mt7620: Add missing header
Fix a build error caused by not including . The following compilation errors are caused by the missing header: arch/mips/ralink/mt7620.c: In function ‘mt7620_get_cpu_pll_rate’: arch/mips/ralink/mt7620.c:431:2: error: implicit declaration of function ‘WARN_ON’ [-Werror=implicit-function-declaration] WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider)); ^ arch/mips/ralink/mt7620.c: In function ‘mt7620_get_sys_rate’: arch/mips/ralink/mt7620.c:500:2: error: implicit declaration of function ‘WARN’ [-Werror=implicit-function-declaration] if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio)) ^ arch/mips/ralink/mt7620.c: In function ‘mt7620_dram_init’: arch/mips/ralink/mt7620.c:619:3: error: implicit declaration of function ‘BUG’ [-Werror=implicit-function-declaration] BUG(); ^ cc1: some warnings being treated as errors scripts/Makefile.build:302: recipe for target 'arch/mips/ralink/mt7620.o' failed Signed-off-by: Harvey Hunt Cc: John Crispin Cc: linux-m...@linux-mips.org Cc: linux-kernel@vger.kernel.org --- arch/mips/ralink/mt7620.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 094a0ee..9be8b08 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -12,6 +12,7 @@ #include #include +#include #include #include -- 2.7.4
[PATCH] Documentation/devicetree: Update links to PCI DT bindings
Update links to the PDFs of PCI and interrupt mapping bindings, as the previous links are broken. Signed-off-by: Harvey Hunt Cc: Bjorn Helgaas Cc: linux-...@vger.kernel.org Cc: devicet...@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- Documentation/devicetree/bindings/pci/pci.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index 50f9e2c..13a73b4 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -1,12 +1,12 @@ PCI bus bridges have standardized Device Tree bindings: PCI Bus Binding to: IEEE Std 1275-1994 -http://www.firmware.org/1275/bindings/pci/pci2_1.pdf +https://www.openfirmware.info/data/docs/bus.pci.pdf And for the interrupt mapping part: Open Firmware Recommended Practice: Interrupt Mapping -http://www.firmware.org/1275/practice/imap/imap0_9d.pdf +https://www.openfirmware.info/data/docs/rec.intmap.d09.pdf Additionally to the properties specified in the above standards a host bridge driver implementation may support the following properties: -- 2.7.4
Re: [PATCH 1/2] MIPS: ralink: Fix build error due to missing header
Hi Ralf,
On 18/07/17 23:01, Ralf Baechle wrote:
On Tue, Jul 18, 2017 at 02:25:45PM +0100, Harvey Hunt wrote:
Previously, was included before ralink_regs.h in all
ralink files - leading to being implicitly included.
After commit 26dd3e4ff9ac ("MIPS: Audit and remove any unnecessary
uses of module.h") removed the inclusion of module.h from multiple
places, some ralink platforms failed to build with the following error:
In file included from arch/mips/ralink/mt7620.c:17:0:
./arch/mips/include/asm/mach-ralink/ralink_regs.h: In function ‘rt_sysc_w32’:
./arch/mips/include/asm/mach-ralink/ralink_regs.h:38:2: error: implicit
declaration of function ‘__raw_writel’ [-Werror=implicit-function-declaration]
__raw_writel(val, rt_sysc_membase + reg);
^
./arch/mips/include/asm/mach-ralink/ralink_regs.h: In function ‘rt_sysc_r32’:
./arch/mips/include/asm/mach-ralink/ralink_regs.h:43:2: error: implicit
declaration of function ‘__raw_readl’ [-Werror=implicit-function-declaration]
return __raw_readl(rt_sysc_membase + reg);
Fix this by including .
Looks sensible, applied. But I'm wondering why I don't see this in my
test builds.
Thanks for merging them. There isn't currently a defconfig for this
platform, but I am working on adding one.
Ralf
Thanks,
Harvey
Re: [V4 1/2] phy: ralink-usb: add driver for Mediatek/Ralink
Hi James, On 09/08/17 23:23, James Hogan wrote: On 9 August 2017 10:35:39 BST, Harvey Hunt wrote: From: John Crispin Add a driver to setup the USB phy on Mediatek/Ralink SoCs. The driver is trivial and only sets up power and host mode. Signed-off-by: John Crispin Signed-off-by: Harvey Hunt Cc: linux-kernel@vger.kernel.org Cc: linux-media...@lists.infradead.org --- Changes in V4 * Remove Allwinner from comment * Depend on COMPILE_TEST Changes in V3 * Separate DT bindings * Update Kconfig text * Modify John's email address * Rebase onto v4.13-rc3 Changes in V2 * remove refcounting * drop empty functions * dont use static globals * use explicit compatible strings drivers/phy/Kconfig | 8 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-ralink-usb.c | 173 +++ 3 files changed, 182 insertions(+) create mode 100644 drivers/phy/phy-ralink-usb.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index c1807d4..8fb5260 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -41,6 +41,14 @@ config PHY_PISTACHIO_USB help Enable this to support the USB2.0 PHY on the IMG Pistachio SoC. +config PHY_RALINK_USB + tristate "Ralink USB PHY driver" + select GENERIC_PHY + depends on RALINK || COMPILE_TEST given that the driver includes a asm/mach-ralink header, the COMPILE_TEST bit may break x86 allmodconfig? maybe the header should be moved out of arch/mips or it should depend on MIPS only (so a mips allmodconfig catches it, but cant be enabled on x86 even with COMPILE_TEST=y) cheers James [...] Well spotted - the build does indeed fail for ARCH=x86 allmodconfig. I could either use: depends on RALINK || (COMPILE_TEST && MIPS) or just drop the COMPILE_TEST altogether, as I don't know how many people are running compile test only on MIPS. Thanks, Harvey
[V5 2/2] dt-bindings: phy: Add bindings for ralink-usb PHY
From: John Crispin
Add a binding for the USB phy on Mediatek/Ralink SoCs.
Signed-off-by: John Crispin
Signed-off-by: Harvey Hunt
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-media...@lists.infradead.org
---
Changes in V5:
* None
Changes in V4:
* None
Changes in V3:
* Split out from first patch
.../devicetree/bindings/phy/ralink-usb-phy.txt | 17 +
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
new file mode 100644
index 000..5b27cad
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
@@ -0,0 +1,17 @@
+Mediatek/Ralink USB PHY
+
+Required properties:
+ - compatible: ralink,rt3352-usbphy or mediatek,mt7620-usbphy
+ - #phy-cells: should be 0
+ - resets: the two reset controllers for host and device
+ - reset-names: the names of the 2 reset controllers
+
+Example:
+
+usbphy: phy {
+ compatible = "mediatek,mt7620-usbphy";
+ #phy-cells = <0>;
+
+ resets = <&rstctrl 22 &rstctrl 25>;
+ reset-names = "host", "device";
+};
--
2.7.4
[V5 1/2] phy: ralink-usb: add driver for Mediatek/Ralink
From: John Crispin
Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
The driver is trivial and only sets up power and host mode.
Signed-off-by: John Crispin
Signed-off-by: Harvey Hunt
Cc: linux-kernel@vger.kernel.org
Cc: linux-media...@lists.infradead.org
---
Changes in V5
* Depend on MIPS
Changes in V4
* Remove Allwinner from comment
* Depend on COMPILE_TEST
Changes in V3
* Separate DT bindings
* Update Kconfig text
* Modify John's email address
* Rebase onto v4.13-rc3
Changes in V2
* remove refcounting
* drop empty functions
* dont use static globals
* use explicit compatible strings
drivers/phy/Kconfig | 9 +++
drivers/phy/Makefile | 1 +
drivers/phy/phy-ralink-usb.c | 173 +++
3 files changed, 183 insertions(+)
create mode 100644 drivers/phy/phy-ralink-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index c1807d4..112a146 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -41,6 +41,15 @@ config PHY_PISTACHIO_USB
help
Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.
+config PHY_RALINK_USB
+ tristate "Ralink USB PHY driver"
+ depends on RALINK || COMPILE_TEST
+ depends on MIPS
+ select GENERIC_PHY
+ help
+ This option enables support for the Ralink USB PHY found inside
+ RT3352, MT7620, MT7628 and MT7688.
+
config PHY_XGENE
tristate "APM X-Gene 15Gbps PHY support"
depends on HAS_IOMEM && OF && (ARM64 || COMPILE_TEST)
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f252201..60ed30b 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
obj-$(CONFIG_PHY_MT65XX_USB3) += phy-mt65xx-usb3.o
obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
obj-$(CONFIG_PHY_PISTACHIO_USB)+= phy-pistachio-usb.o
+obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
obj-$(CONFIG_ARCH_SUNXI) += allwinner/
obj-$(CONFIG_ARCH_MESON) += amlogic/
diff --git a/drivers/phy/phy-ralink-usb.c b/drivers/phy/phy-ralink-usb.c
new file mode 100644
index 000..14a254a
--- /dev/null
+++ b/drivers/phy/phy-ralink-usb.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2016 John Crispin
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define RT_SYSC_REG_SYSCFG10x014
+#define RT_SYSC_REG_CLKCFG10x030
+#define RT_SYSC_REG_USB_PHY_CFG0x05c
+
+#define RT_RSTCTRL_UDEVBIT(25)
+#define RT_RSTCTRL_UHSTBIT(22)
+#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
+
+#define MT7620_CLKCFG1_UPHY0_CLK_ENBIT(25)
+#define MT7620_CLKCFG1_UPHY1_CLK_ENBIT(22)
+#define RT_CLKCFG1_UPHY1_CLK_ENBIT(20)
+#define RT_CLKCFG1_UPHY0_CLK_ENBIT(18)
+
+#define USB_PHY_UTMI_8B60M BIT(1)
+#define UDEV_WAKEUPBIT(0)
+
+struct ralink_usb_phy {
+ struct reset_control*rstdev;
+ struct reset_control*rsthost;
+ u32 clk;
+ struct phy *phy;
+};
+
+static int ralink_usb_phy_power_on(struct phy *_phy)
+{
+ struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
+ u32 t;
+
+ /* enable the phy */
+ rt_sysc_m32(0, phy->clk, RT_SYSC_REG_CLKCFG1);
+
+ /* setup host mode */
+ rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
+
+ /* deassert the reset lines */
+ reset_control_deassert(phy->rsthost);
+ reset_control_deassert(phy->rstdev);
+
+ /*
+* The SDK kernel had a delay of 100ms. however on device
+* testing showed that 10ms is enough
+*/
+ mdelay(10);
+
+ /* print some status info */
+ t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
+ dev_info(&phy->phy->dev, "remote usb device wakeup %s\n",
+ (t & UDEV_WAKEUP) ? ("enabled") : ("disabled"));
+ if (t & USB_PHY_UTMI_8B60M)
+ dev_info(&phy->phy->dev, "UTMI 8bit 60MHz\n");
+ else
+ dev_info(&phy->phy->dev, "U
Re: [PATCH] phy: ralink: fix 64-bit build warning
Hi Arnd,
On 23/08/17 14:39, Arnd Bergmann wrote:
Casting between an 'int' and a pointer causes a warning on
64-bit architectures in compile-testing this driver:
drivers/phy/ralink/phy-ralink-usb.c: In function 'ralink_usb_phy_probe':
drivers/phy/ralink/phy-ralink-usb.c:195:13: error: cast from pointer to integer
of different size [-Werror=pointer-to-int-cast]
This changes the code to cast to uintptr_t instead. This is
guaranteed to do what we want on all architectures and avoids
the warning.
Fixes: 2411a736ff09 ("phy: ralink-usb: add driver for Mediatek/Ralink")
Signed-off-by: Arnd Bergmann
---
drivers/phy/ralink/phy-ralink-usb.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
[...]
Thanks for fixing this - it was on my TODO list.
Tested-by Harvey Hunt
Reviewed-by Harvey Hunt
Thanks,
Harvey
[PATCH] MIPS: mt7620: Rename uartlite to serial
Previously, mt7620.c defined the clocks for uarts with the names
uartlite, uart1 and uart2. Rename them to serial{0,1,2} and update
the devicetree node names.
Signed-off-by: Harvey Hunt
Cc: devicet...@vger.kernel.org
Cc: linux-m...@linux-mips.org
Cc: linux-kernel@vger.kernel.org
---
arch/mips/boot/dts/ralink/mt7620a.dtsi | 2 +-
arch/mips/boot/dts/ralink/mt7628a.dtsi | 6 +++---
arch/mips/ralink/mt7620.c | 14 +++---
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi
b/arch/mips/boot/dts/ralink/mt7620a.dtsi
index 793c0c7..58bd002 100644
--- a/arch/mips/boot/dts/ralink/mt7620a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
@@ -45,7 +45,7 @@
reg = <0x300 0x100>;
};
- uartlite@c00 {
+ serial0@c00 {
compatible = "ralink,mt7620a-uart",
"ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi
b/arch/mips/boot/dts/ralink/mt7628a.dtsi
index 9ff7e8f..fe3fe9a 100644
--- a/arch/mips/boot/dts/ralink/mt7628a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -62,7 +62,7 @@
reg = <0x300 0x100>;
};
- uart0: uartlite@c00 {
+ uart0: serial0@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
@@ -75,7 +75,7 @@
reg-shift = <2>;
};
- uart1: uart1@d00 {
+ uart1: serial1@d00 {
compatible = "ns16550a";
reg = <0xd00 0x100>;
@@ -88,7 +88,7 @@
reg-shift = <2>;
};
- uart2: uart2@e00 {
+ uart2: serial2@e00 {
compatible = "ns16550a";
reg = <0xe00 0x100>;
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 9be8b08..f623ceb 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -54,7 +54,7 @@ static int dram_type;
static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
-static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
+static struct rt2880_pmx_func serial_grp[] = { FUNC("serial", 0, 15, 2) };
static struct rt2880_pmx_func mdio_grp[] = {
FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
@@ -92,7 +92,7 @@ static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
MT7620_GPIO_MODE_UART0_SHIFT),
GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
- GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
+ GRP("serial", serial_grp, 1, MT7620_GPIO_MODE_UART1),
GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
@@ -530,8 +530,8 @@ void __init ralink_clk_init(void)
periph_rate = MHZ(40);
pcmi2s_rate = MHZ(480);
- ralink_clk_add("1d00.uartlite", periph_rate);
- ralink_clk_add("1e00.uartlite", periph_rate);
+ ralink_clk_add("1d00.serial0", periph_rate);
+ ralink_clk_add("1e00.serial0", periph_rate);
} else {
cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
@@ -566,9 +566,9 @@ void __init ralink_clk_init(void)
ralink_clk_add("1a00.i2s", pcmi2s_rate);
ralink_clk_add("1b00.spi", sys_rate);
ralink_clk_add("1b40.spi", sys_rate);
- ralink_clk_add("1c00.uartlite", periph_rate);
- ralink_clk_add("1d00.uart1", periph_rate);
- ralink_clk_add("1e00.uart2", periph_rate);
+ ralink_clk_add("1c00.serial0", periph_rate);
+ ralink_clk_add("1d00.serial1", periph_rate);
+ ralink_clk_add("1e00.serial2", periph_rate);
ralink_clk_add("1018.wmac", xtal_rate);
if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
--
2.7.4
Re: [PATCH 2/3] MIPS: dts: Add VoCore2 board
Hi Rob,
Thanks for the review.
On 17/08/17 22:36, Rob Herring wrote:
On Tue, Aug 15, 2017 at 05:32:52PM +0100, Harvey Hunt wrote:
The VoCore2 board is a low cost MT7628A based board with 128MB RAM, 16MB
flash and multiple external peripherals.
This initial DTS provides enough support to get to userland and use the USB
port.
Signed-off-by: Harvey Hunt
Cc: linux-kernel@vger.kernel.org
Cc: devicet...@vger.kernel.org
Cc: linux-m...@linux-mips.org
---
MAINTAINERS | 6 ++
arch/mips/boot/dts/ralink/Makefile| 1 +
arch/mips/boot/dts/ralink/vocore2.dts | 18 ++
arch/mips/ralink/Kconfig | 5 +
4 files changed, 30 insertions(+)
create mode 100644 arch/mips/boot/dts/ralink/vocore2.dts
diff --git a/MAINTAINERS b/MAINTAINERS
index 6f7721d..82dcc6f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14127,6 +14127,12 @@ L: net...@vger.kernel.org
S:Maintained
F:drivers/net/vmxnet3/
+VOCORE VOCORE2 BOARD
+M: Harvey Hunt
+L: linux-m...@linux-mips.org
+S: Maintained
+F: arch/mips/boot/dts/ralink/vocore2.dts
+
VOLTAGE AND CURRENT REGULATOR FRAMEWORK
M:Liam Girdwood
M:Mark Brown
diff --git a/arch/mips/boot/dts/ralink/Makefile
b/arch/mips/boot/dts/ralink/Makefile
index 2a72259..a191788 100644
--- a/arch/mips/boot/dts/ralink/Makefile
+++ b/arch/mips/boot/dts/ralink/Makefile
@@ -2,6 +2,7 @@ dtb-$(CONFIG_DTB_RT2880_EVAL) += rt2880_eval.dtb
dtb-$(CONFIG_DTB_RT305X_EVAL) += rt3052_eval.dtb
dtb-$(CONFIG_DTB_RT3883_EVAL) += rt3883_eval.dtb
dtb-$(CONFIG_DTB_MT7620A_EVAL)+= mt7620a_eval.dtb
+dtb-$(CONFIG_DTB_VOCORE2) += vocore2.dtb
obj-y+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
diff --git a/arch/mips/boot/dts/ralink/vocore2.dts b/arch/mips/boot/dts/ralink/vocore2.dts
new file mode 100644
index 000..7591340
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/vocore2.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+#include "mt7628a.dtsi"
+
+/ {
+ compatible = "vocore,vocore2", "ralink,mt7628a-soc";
Is vocore,vocore2 documented?
It's not, do you want me to add a file in
Documentation/devicetree/bindings/mips?
If so, shall I just create a vocore.txt file or create a "vocore"
directory with vocore2.txt in it?
Thanks,
Harvey
+ model = "VoCore2";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x800>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS2,115200";
+ stdout-path = "serial2:115200";
+ };
+};
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 710b04c..c2b2c2d 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -82,6 +82,11 @@ choice
depends on SOC_MT7620
select BUILTIN_DTB
+ config DTB_VOCORE2
+ bool "VoCore2"
+ depends on SOC_MT7620
+ select BUILTIN_DTB
+
endchoice
endif
--
2.7.4
Re: [PATCH] MIPS: dts: ralink: Add Mediatek MT7628A SoC
Hi Rob,
On 18/08/17 15:04, Rob Herring wrote:
On Fri, Aug 18, 2017 at 4:42 AM, Harvey Hunt wrote:
Hi Rob,
Thanks for the review.
On 17/08/17 22:34, Rob Herring wrote:
On Tue, Aug 15, 2017 at 05:28:50PM +0100, Harvey Hunt wrote:
The MT7628A is the successor to the MT7620 and pin compatible with the
MT7688A, although the latter supports only a 1T1R antenna rather than
a 2T2R antenna.
[...]
+ uartlite@c00 {
serial@c00
And so on. IOW, use standard, generic node names as defined in the DT
spec.
The clocks for the UARTs are using the device names "uartlite", "uart1" and
"uart2" (as defined in arch/mips/ralink/mt7620.c).
You can't add clocks to the DT? Looks like mt76x8 at least should be
pretty easy with some fixed clocks.
Depending if backwards compatibility (old dtb working on new kernel)
is a concern on these platforms, you could just change all the names
both in the kernel and dts.
I don't think backwards compatibility will matter - the bootloaders I've
come across don't ship DTBs with them and I don't think there are any
ralink devices using the upstream MT7620 DT.
John might have some thoughts on backwards compat though.
Changing the name of the DT nodes causes the serial driver to bail as it
can't find the clock for the device.
arch/mips/boot/dts/ralink/mt7620a.dtsi is already using the uartlite name,
although it hasn't been documented...
Generally the kernel shouldn't care what the names are (though you can
match by name, it's not widely used).
In any case, I guess fixing this can be done later.
Rob
Shall I respin this patch with the earlier nodes (intc etc) renamed and
then send a patch later to rename the serial ports in the DT and kernel
(assuming there are no backwards compatibility issues)?
Thanks,
Harvey
[V2 2/4] dt-bindings: vendors: Add VoCore as a vendor
VoCore are a manufacturer of devices such as the VoCore2. Signed-off-by: Harvey Hunt Acked-by: Rob Herring Cc: linux-kernel@vger.kernel.org Cc: devicet...@vger.kernel.org Cc: linux-m...@linux-mips.org --- Changes in V2: - None Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index daf465be..f6e3716 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -353,6 +353,7 @@ variscite Variscite Ltd. viaVIA Technologies, Inc. virtio Virtual I/O Device Specification, developed by the OASIS consortium vivanteVivante Corporation +vocore VoCore Studio voipac Voipac Technologies s.r.o. wd Western Digital Corp. wetek WeTek Electronics, limited. -- 2.7.4
[V2 1/4] MIPS: dts: ralink: Add Mediatek MT7628A SoC
The MT7628A is the successor to the MT7620 and pin compatible with the
MT7688A, although the latter supports only a 1T1R antenna rather than
a 2T2R antenna.
This commit adds support for the following features:
- UART
- USB PHY
- EHCI
- Interrupt controller
- System controller
- Memory controller
- Reset controller
Signed-off-by: Harvey Hunt
Cc: linux-m...@linux-mips.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-media...@lists.infradead.org
---
Ralf: I've added this patch to both my vocore2 and omega2+
patchsets for ease of review, please only merge it once :-)
Changes in V2:
- Add MT7628 to patchset to keep kbuild happy and retain context
- Rename multiple DT nodes to standard names
- Add labels for uarts
- Rename USB PHY handle
Documentation/devicetree/bindings/mips/ralink.txt | 1 +
arch/mips/boot/dts/ralink/mt7628a.dtsi| 126 ++
2 files changed, 127 insertions(+)
create mode 100644 arch/mips/boot/dts/ralink/mt7628a.dtsi
diff --git a/Documentation/devicetree/bindings/mips/ralink.txt
b/Documentation/devicetree/bindings/mips/ralink.txt
index b35a8d0..a16e8d7 100644
--- a/Documentation/devicetree/bindings/mips/ralink.txt
+++ b/Documentation/devicetree/bindings/mips/ralink.txt
@@ -15,3 +15,4 @@ value must be one of the following values:
ralink,rt5350-soc
ralink,mt7620a-soc
ralink,mt7620n-soc
+ ralink,mt7628a-soc
diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi
b/arch/mips/boot/dts/ralink/mt7628a.dtsi
new file mode 100644
index 000..9ff7e8f
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -0,0 +1,126 @@
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,mt7628a-soc";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mti,mips24KEc";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ resetc: reset-controller {
+ compatible = "ralink,rt2880-reset";
+ #reset-cells = <1>;
+ };
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ palmbus@1000 {
+ compatible = "palmbus";
+ reg = <0x1000 0x20>;
+ ranges = <0x0 0x1000 0x1F>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysc: system-controller@0 {
+ compatible = "ralink,mt7620a-sysc", "syscon";
+ reg = <0x0 0x100>;
+ };
+
+ intc: interrupt-controller@200 {
+ compatible = "ralink,rt2880-intc";
+ reg = <0x200 0x100>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ resets = <&resetc 9>;
+ reset-names = "intc";
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+
+ ralink,intc-registers = <0x9c 0xa0
+0x6c 0xa4
+0x80 0x78>;
+ };
+
+ memory-controller@300 {
+ compatible = "ralink,mt7620a-memc";
+ reg = <0x300 0x100>;
+ };
+
+ uart0: uartlite@c00 {
+ compatible = "ns16550a";
+ reg = <0xc00 0x100>;
+
+ resets = <&resetc 12>;
+ reset-names = "uart0";
+
+ interrupt-parent = <&intc>;
+ interrupts = <20>;
+
+ reg-shift = <2>;
+ };
+
+ uart1: uart1@d00 {
+ compatible = "ns16550a";
+ reg = <0xd00 0x100>;
+
+ resets = <&resetc 19>;
+ reset-names = "uart1";
+
+ interrupt-parent = <&intc>;
+ interrupts = <21>;
+
+ reg-shift = <2>;
+ };
+
+ uart2: uart2@e00 {
+ compatible = "ns16550a";
+ reg = <0xe00 0x100>;
+
+ resets = <&resetc 20>;
+ reset-names
[V2 2/3] MIPS: Add Onion Omega2+ board
The Onion Omega2+ is an MT7688A based board that has 128MB RAM and
multiple peripherals.
The MT7688A is pin compatible with the MT7628A, although the former
supports a 1T1R antenna whereas the MT7628A supports a 2R2T antenna.
Signed-off-by: Harvey Hunt
Cc: linux-kernel@vger.kernel.org
Cc: devicet...@vger.kernel.org
Cc: linux-m...@linux-mips.org
---
Changes in V2:
- Use uart0 phandle for stdout-path
- Add MT7628 compatible string
MAINTAINERS | 6 ++
arch/mips/boot/dts/ralink/Makefile| 1 +
arch/mips/boot/dts/ralink/omega2p.dts | 18 ++
arch/mips/ralink/Kconfig | 5 +
4 files changed, 30 insertions(+)
create mode 100644 arch/mips/boot/dts/ralink/omega2p.dts
diff --git a/MAINTAINERS b/MAINTAINERS
index 6f7721d..33b6bd2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9675,6 +9675,12 @@ F: drivers/regulator/twl-regulator.c
F: drivers/regulator/twl6030-regulator.c
F: include/linux/i2c-omap.h
+ONION OMEGA2+ BOARD
+M: Harvey Hunt
+L: linux-m...@linux-mips.org
+S: Maintained
+F: arch/mips/boot/dts/ralink/omega2p.dts
+
OMFS FILESYSTEM
M: Bob Copeland
L: linux-karma-de...@lists.sourceforge.net
diff --git a/arch/mips/boot/dts/ralink/Makefile
b/arch/mips/boot/dts/ralink/Makefile
index 2a72259..88da019 100644
--- a/arch/mips/boot/dts/ralink/Makefile
+++ b/arch/mips/boot/dts/ralink/Makefile
@@ -2,6 +2,7 @@ dtb-$(CONFIG_DTB_RT2880_EVAL) += rt2880_eval.dtb
dtb-$(CONFIG_DTB_RT305X_EVAL) += rt3052_eval.dtb
dtb-$(CONFIG_DTB_RT3883_EVAL) += rt3883_eval.dtb
dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb
+dtb-$(CONFIG_DTB_OMEGA2P) += omega2p.dtb
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
diff --git a/arch/mips/boot/dts/ralink/omega2p.dts
b/arch/mips/boot/dts/ralink/omega2p.dts
new file mode 100644
index 000..5884fd4
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/omega2p.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+/include/ "mt7628a.dtsi"
+
+/ {
+ compatible = "onion,omega2+", "ralink,mt7688a-soc",
"ralink,mt7628a-soc";
+ model = "Onion Omega2+";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x800>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = &uart0;
+ };
+};
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 710b04c..6ee52bc 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -82,6 +82,11 @@ choice
depends on SOC_MT7620
select BUILTIN_DTB
+ config DTB_OMEGA2P
+ bool "Onion Omega2+"
+ depends on SOC_MT7620
+ select BUILTIN_DTB
+
endchoice
endif
--
2.7.4
[V2 3/3] MIPS: configs: Add Onion Omega2+ defconfig
Create a defconfig for the Omega2+ that reaches userspace and allows use of the USB port. Signed-off-by: Harvey Hunt Cc: linux-kernel@vger.kernel.org Cc: linux-m...@linux-mips.org --- Changes in V2: - Remove CONFIG_PANIC_ON_OOPS arch/mips/configs/omega2p_defconfig | 129 1 file changed, 129 insertions(+) create mode 100644 arch/mips/configs/omega2p_defconfig diff --git a/arch/mips/configs/omega2p_defconfig b/arch/mips/configs/omega2p_defconfig new file mode 100644 index 000..e2731c3 --- /dev/null +++ b/arch/mips/configs/omega2p_defconfig @@ -0,0 +1,129 @@ +CONFIG_RALINK=y +CONFIG_SOC_MT7620=y +CONFIG_DTB_OMEGA2P=y +CONFIG_CPU_MIPS32_R2=y +# CONFIG_COMPACTION is not set +CONFIG_HZ_100=y +CONFIG_PREEMPT=y +# CONFIG_SECCOMP is not set +CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +# CONFIG_FW_LOADER is not set +# CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_NETDEVICES=y +# CONFIG_ETHERNET is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_LEGACY_PTY_COUNT=2 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_VGA_CONSOLE is not set +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_MMC=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_MEMORY=y +CONFIG_PHY_RALINK_USB=y +# CONFIG_DNOTIFY is not set +CONFIG_PROC_KCORE=y +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_TMPFS=y +CONFIG_CONFIGFS_FS=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=y +CONFIG_NLS_CODEPAGE_775=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +CONFIG_NLS_CODEPAGE_855=y +CONFIG_NLS_CODEPAGE_857=y +CONFIG_NLS_CODEPAGE_860=y +CONFIG_NLS_CODEPAGE_861=y +CONFIG_NLS_CODEPAGE_862=y +CONFIG_NLS_CODEPAGE_863=y +CONFIG_NLS_CODEPAGE_864=y +CONFIG_NLS_CODEPAGE_865=y +CONFIG_NLS_CODEPAGE_866=y +CONFIG_NLS_CODEPAGE_869=y +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_NLS_CODEPAGE_949=y +CONFIG_NLS_CODEPAGE_874=y +CONFIG_NLS_ISO8859_8=y +CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_CODEPAGE_1251=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_ISO8859_3=y +CONFIG_NLS_ISO8859_4=y +CONFIG_NLS_ISO8859_5=y +CONFIG_NLS_ISO8859_6=y +CONFIG_NLS_ISO8859_7=y +CONFIG_NLS_ISO8859_9=y +CONFIG_NLS_ISO8859_13=y +CONFIG_NLS_ISO8859_14=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_KOI8_R=y +CONFIG_NLS_KOI8_U=y +CONFIG_NLS_UTF8=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_PANIC_TIMEOUT=10 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_STACKTRACE=y +# CONFIG_FTRACE is not set +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRC16=y +CONFIG_XZ_DEC=y -- 2.7.4
[V2 4/4] MIPS: configs: Add VoCore2 defconfig
Enabled supported drivers, including: - USB PHY - EHCI - UART Signed-off-by: Harvey Hunt Cc: linux-kernel@vger.kernel.org Cc: linux-m...@linux-mips.org --- Changes in V2: - Remove CONFIG_PANIC_ON_OOPS arch/mips/configs/vocore2_defconfig | 129 1 file changed, 129 insertions(+) create mode 100644 arch/mips/configs/vocore2_defconfig diff --git a/arch/mips/configs/vocore2_defconfig b/arch/mips/configs/vocore2_defconfig new file mode 100644 index 000..9121e41 --- /dev/null +++ b/arch/mips/configs/vocore2_defconfig @@ -0,0 +1,129 @@ +CONFIG_RALINK=y +CONFIG_SOC_MT7620=y +CONFIG_DTB_VOCORE2=y +CONFIG_CPU_MIPS32_R2=y +# CONFIG_COMPACTION is not set +CONFIG_HZ_100=y +CONFIG_PREEMPT=y +# CONFIG_SECCOMP is not set +CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +# CONFIG_FW_LOADER is not set +# CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_NETDEVICES=y +# CONFIG_ETHERNET is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_LEGACY_PTY_COUNT=2 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_VGA_CONSOLE is not set +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_MMC=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_MEMORY=y +CONFIG_PHY_RALINK_USB=y +# CONFIG_DNOTIFY is not set +CONFIG_PROC_KCORE=y +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_TMPFS=y +CONFIG_CONFIGFS_FS=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=y +CONFIG_NLS_CODEPAGE_775=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +CONFIG_NLS_CODEPAGE_855=y +CONFIG_NLS_CODEPAGE_857=y +CONFIG_NLS_CODEPAGE_860=y +CONFIG_NLS_CODEPAGE_861=y +CONFIG_NLS_CODEPAGE_862=y +CONFIG_NLS_CODEPAGE_863=y +CONFIG_NLS_CODEPAGE_864=y +CONFIG_NLS_CODEPAGE_865=y +CONFIG_NLS_CODEPAGE_866=y +CONFIG_NLS_CODEPAGE_869=y +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_NLS_CODEPAGE_949=y +CONFIG_NLS_CODEPAGE_874=y +CONFIG_NLS_ISO8859_8=y +CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_CODEPAGE_1251=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_ISO8859_3=y +CONFIG_NLS_ISO8859_4=y +CONFIG_NLS_ISO8859_5=y +CONFIG_NLS_ISO8859_6=y +CONFIG_NLS_ISO8859_7=y +CONFIG_NLS_ISO8859_9=y +CONFIG_NLS_ISO8859_13=y +CONFIG_NLS_ISO8859_14=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_KOI8_R=y +CONFIG_NLS_KOI8_U=y +CONFIG_NLS_UTF8=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_PANIC_TIMEOUT=10 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_STACKTRACE=y +# CONFIG_FTRACE is not set +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRC16=y +CONFIG_XZ_DEC=y -- 2.7.4
[V2 1/4] MIPS: dts: ralink: Add Mediatek MT7628A SoC
The MT7628A is the successor to the MT7620 and pin compatible with the
MT7688A, although the latter supports only a 1T1R antenna rather than
a 2T2R antenna.
This commit adds support for the following features:
- UART
- USB PHY
- EHCI
- Interrupt controller
- System controller
- Memory controller
- Reset controller
Signed-off-by: Harvey Hunt
Cc: linux-m...@linux-mips.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-media...@lists.infradead.org
---
Ralf: I've added this patch to both my vocore2 and omega2+
patchsets for ease of review, please only merge it once :-)
Changes in V2:
- Add MT7628 to patchset to keep kbuild happy and retain context
- Rename multiple DT nodes to standard names
- Add labels for uarts
- Rename USB PHY handle
Documentation/devicetree/bindings/mips/ralink.txt | 1 +
arch/mips/boot/dts/ralink/mt7628a.dtsi| 126 ++
2 files changed, 127 insertions(+)
create mode 100644 arch/mips/boot/dts/ralink/mt7628a.dtsi
diff --git a/Documentation/devicetree/bindings/mips/ralink.txt
b/Documentation/devicetree/bindings/mips/ralink.txt
index b35a8d0..a16e8d7 100644
--- a/Documentation/devicetree/bindings/mips/ralink.txt
+++ b/Documentation/devicetree/bindings/mips/ralink.txt
@@ -15,3 +15,4 @@ value must be one of the following values:
ralink,rt5350-soc
ralink,mt7620a-soc
ralink,mt7620n-soc
+ ralink,mt7628a-soc
diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi
b/arch/mips/boot/dts/ralink/mt7628a.dtsi
new file mode 100644
index 000..9ff7e8f
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -0,0 +1,126 @@
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,mt7628a-soc";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mti,mips24KEc";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ resetc: reset-controller {
+ compatible = "ralink,rt2880-reset";
+ #reset-cells = <1>;
+ };
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ palmbus@1000 {
+ compatible = "palmbus";
+ reg = <0x1000 0x20>;
+ ranges = <0x0 0x1000 0x1F>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysc: system-controller@0 {
+ compatible = "ralink,mt7620a-sysc", "syscon";
+ reg = <0x0 0x100>;
+ };
+
+ intc: interrupt-controller@200 {
+ compatible = "ralink,rt2880-intc";
+ reg = <0x200 0x100>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ resets = <&resetc 9>;
+ reset-names = "intc";
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+
+ ralink,intc-registers = <0x9c 0xa0
+0x6c 0xa4
+0x80 0x78>;
+ };
+
+ memory-controller@300 {
+ compatible = "ralink,mt7620a-memc";
+ reg = <0x300 0x100>;
+ };
+
+ uart0: uartlite@c00 {
+ compatible = "ns16550a";
+ reg = <0xc00 0x100>;
+
+ resets = <&resetc 12>;
+ reset-names = "uart0";
+
+ interrupt-parent = <&intc>;
+ interrupts = <20>;
+
+ reg-shift = <2>;
+ };
+
+ uart1: uart1@d00 {
+ compatible = "ns16550a";
+ reg = <0xd00 0x100>;
+
+ resets = <&resetc 19>;
+ reset-names = "uart1";
+
+ interrupt-parent = <&intc>;
+ interrupts = <21>;
+
+ reg-shift = <2>;
+ };
+
+ uart2: uart2@e00 {
+ compatible = "ns16550a";
+ reg = <0xe00 0x100>;
+
+ resets = <&resetc 20>;
+ reset-names
[V2 3/4] MIPS: dts: Add Vocore2 board
The VoCore2 board is a low cost MT7628A based board with 128MB RAM, 16MB
flash and multiple external peripherals.
This initial DTS provides enough support to get to userland and use the USB
port.
Signed-off-by: Harvey Hunt
Cc: linux-kernel@vger.kernel.org
Cc: devicet...@vger.kernel.org
Cc: linux-m...@linux-mips.org
---
Changes in V2:
- Use uart2 phandle for stdout-path
MAINTAINERS | 6 ++
arch/mips/boot/dts/ralink/Makefile| 1 +
arch/mips/boot/dts/ralink/vocore2.dts | 18 ++
arch/mips/ralink/Kconfig | 5 +
4 files changed, 30 insertions(+)
create mode 100644 arch/mips/boot/dts/ralink/vocore2.dts
diff --git a/MAINTAINERS b/MAINTAINERS
index 6f7721d..82dcc6f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14127,6 +14127,12 @@ L: net...@vger.kernel.org
S: Maintained
F: drivers/net/vmxnet3/
+VOCORE VOCORE2 BOARD
+M: Harvey Hunt
+L: linux-m...@linux-mips.org
+S: Maintained
+F: arch/mips/boot/dts/ralink/vocore2.dts
+
VOLTAGE AND CURRENT REGULATOR FRAMEWORK
M: Liam Girdwood
M: Mark Brown
diff --git a/arch/mips/boot/dts/ralink/Makefile
b/arch/mips/boot/dts/ralink/Makefile
index 2a72259..a191788 100644
--- a/arch/mips/boot/dts/ralink/Makefile
+++ b/arch/mips/boot/dts/ralink/Makefile
@@ -2,6 +2,7 @@ dtb-$(CONFIG_DTB_RT2880_EVAL) += rt2880_eval.dtb
dtb-$(CONFIG_DTB_RT305X_EVAL) += rt3052_eval.dtb
dtb-$(CONFIG_DTB_RT3883_EVAL) += rt3883_eval.dtb
dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb
+dtb-$(CONFIG_DTB_VOCORE2) += vocore2.dtb
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
diff --git a/arch/mips/boot/dts/ralink/vocore2.dts
b/arch/mips/boot/dts/ralink/vocore2.dts
new file mode 100644
index 000..fa8a5f8
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/vocore2.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+#include "mt7628a.dtsi"
+
+/ {
+ compatible = "vocore,vocore2", "ralink,mt7628a-soc";
+ model = "VoCore2";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x800>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS2,115200";
+ stdout-path = &uart2;
+ };
+};
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 710b04c..c2b2c2d 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -82,6 +82,11 @@ choice
depends on SOC_MT7620
select BUILTIN_DTB
+ config DTB_VOCORE2
+ bool "VoCore2"
+ depends on SOC_MT7620
+ select BUILTIN_DTB
+
endchoice
endif
--
2.7.4
[V3 1/2] phy: ralink-usb: add driver for Mediatek/Ralink
From: John Crispin
Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
The driver is trivial and only sets up power and host mode.
Signed-off-by: John Crispin
Signed-off-by: Harvey Hunt
Cc: linux-kernel@vger.kernel.org
Cc: linux-media...@lists.infradead.org
---
Changes in V3
* Separate DT bindings
* Update Kconfig text
* Modify John's email address
* Rebase onto v4.13-rc3
Changes in V2
* remove refcounting
* drop empty functions
* dont use static globals
* use explicit compatible strings
drivers/phy/Kconfig | 8 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-ralink-usb.c | 175 +++
3 files changed, 184 insertions(+)
create mode 100644 drivers/phy/phy-ralink-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index c1807d4..79f966a 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -41,6 +41,14 @@ config PHY_PISTACHIO_USB
help
Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.
+config PHY_RALINK_USB
+ tristate "Ralink USB PHY driver"
+ select GENERIC_PHY
+ depends on RALINK
+ help
+ This option enables support for the Ralink USB PHY found inside
+ RT3352, MT7620, MT7628 and MT7688.
+
config PHY_XGENE
tristate "APM X-Gene 15Gbps PHY support"
depends on HAS_IOMEM && OF && (ARM64 || COMPILE_TEST)
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f252201..60ed30b 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
obj-$(CONFIG_PHY_MT65XX_USB3) += phy-mt65xx-usb3.o
obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
obj-$(CONFIG_PHY_PISTACHIO_USB)+= phy-pistachio-usb.o
+obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
obj-$(CONFIG_ARCH_SUNXI) += allwinner/
obj-$(CONFIG_ARCH_MESON) += amlogic/
diff --git a/drivers/phy/phy-ralink-usb.c b/drivers/phy/phy-ralink-usb.c
new file mode 100644
index 000..c693fb1
--- /dev/null
+++ b/drivers/phy/phy-ralink-usb.c
@@ -0,0 +1,175 @@
+/*
+ * Allwinner ralink USB phy driver
+ *
+ * Copyright (C) 2016 John Crispin
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define RT_SYSC_REG_SYSCFG10x014
+#define RT_SYSC_REG_CLKCFG10x030
+#define RT_SYSC_REG_USB_PHY_CFG0x05c
+
+#define RT_RSTCTRL_UDEVBIT(25)
+#define RT_RSTCTRL_UHSTBIT(22)
+#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
+
+#define MT7620_CLKCFG1_UPHY0_CLK_ENBIT(25)
+#define MT7620_CLKCFG1_UPHY1_CLK_ENBIT(22)
+#define RT_CLKCFG1_UPHY1_CLK_ENBIT(20)
+#define RT_CLKCFG1_UPHY0_CLK_ENBIT(18)
+
+#define USB_PHY_UTMI_8B60M BIT(1)
+#define UDEV_WAKEUPBIT(0)
+
+struct ralink_usb_phy {
+ struct reset_control*rstdev;
+ struct reset_control*rsthost;
+ u32 clk;
+ struct phy *phy;
+};
+
+static int ralink_usb_phy_power_on(struct phy *_phy)
+{
+ struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
+ u32 t;
+
+ /* enable the phy */
+ rt_sysc_m32(0, phy->clk, RT_SYSC_REG_CLKCFG1);
+
+ /* setup host mode */
+ rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
+
+ /* deassert the reset lines */
+ reset_control_deassert(phy->rsthost);
+ reset_control_deassert(phy->rstdev);
+
+ /*
+* The SDK kernel had a delay of 100ms. however on device
+* testing showed that 10ms is enough
+*/
+ mdelay(10);
+
+ /* print some status info */
+ t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
+ dev_info(&phy->phy->dev, "remote usb device wakeup %s\n",
+ (t & UDEV_WAKEUP) ? ("enabled") : ("disabled"));
+ if (t & USB_PHY_UTMI_8B60M)
+ dev_info(&phy->phy->dev, "UTMI 8bit 60MHz\n");
+ else
+ dev_info(&phy->phy->dev, "UTMI 16bit 30MHz\n");
+
+ return 0;
+}
+
+static int ralink_usb_phy_power_off(struct
[V3 2/2] dt-bindings: phy: Add bindings for ralink-usb PHY
From: John Crispin
Add a binding for the USB phy on Mediatek/Ralink SoCs.
Signed-off-by: John Crispin
Signed-off-by: Harvey Hunt
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-media...@lists.infradead.org
---
Changes in V3:
* Split out from first patch
.../devicetree/bindings/phy/ralink-usb-phy.txt | 17 +
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
new file mode 100644
index 000..5b27cad
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
@@ -0,0 +1,17 @@
+Mediatek/Ralink USB PHY
+
+Required properties:
+ - compatible: ralink,rt3352-usbphy or mediatek,mt7620-usbphy
+ - #phy-cells: should be 0
+ - resets: the two reset controllers for host and device
+ - reset-names: the names of the 2 reset controllers
+
+Example:
+
+usbphy: phy {
+ compatible = "mediatek,mt7620-usbphy";
+ #phy-cells = <0>;
+
+ resets = <&rstctrl 22 &rstctrl 25>;
+ reset-names = "host", "device";
+};
--
2.7.4
[V4 2/2] dt-bindings: phy: Add bindings for ralink-usb PHY
From: John Crispin
Add a binding for the USB phy on Mediatek/Ralink SoCs.
Signed-off-by: John Crispin
Signed-off-by: Harvey Hunt
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-media...@lists.infradead.org
---
Changes in V4:
* None
Changes in V3:
* Split out from first patch
.../devicetree/bindings/phy/ralink-usb-phy.txt | 17 +
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
new file mode 100644
index 000..5b27cad
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
@@ -0,0 +1,17 @@
+Mediatek/Ralink USB PHY
+
+Required properties:
+ - compatible: ralink,rt3352-usbphy or mediatek,mt7620-usbphy
+ - #phy-cells: should be 0
+ - resets: the two reset controllers for host and device
+ - reset-names: the names of the 2 reset controllers
+
+Example:
+
+usbphy: phy {
+ compatible = "mediatek,mt7620-usbphy";
+ #phy-cells = <0>;
+
+ resets = <&rstctrl 22 &rstctrl 25>;
+ reset-names = "host", "device";
+};
--
2.7.4
[V4 1/2] phy: ralink-usb: add driver for Mediatek/Ralink
From: John Crispin
Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
The driver is trivial and only sets up power and host mode.
Signed-off-by: John Crispin
Signed-off-by: Harvey Hunt
Cc: linux-kernel@vger.kernel.org
Cc: linux-media...@lists.infradead.org
---
Changes in V4
* Remove Allwinner from comment
* Depend on COMPILE_TEST
Changes in V3
* Separate DT bindings
* Update Kconfig text
* Modify John's email address
* Rebase onto v4.13-rc3
Changes in V2
* remove refcounting
* drop empty functions
* dont use static globals
* use explicit compatible strings
drivers/phy/Kconfig | 8 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-ralink-usb.c | 173 +++
3 files changed, 182 insertions(+)
create mode 100644 drivers/phy/phy-ralink-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index c1807d4..8fb5260 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -41,6 +41,14 @@ config PHY_PISTACHIO_USB
help
Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.
+config PHY_RALINK_USB
+ tristate "Ralink USB PHY driver"
+ select GENERIC_PHY
+ depends on RALINK || COMPILE_TEST
+ help
+ This option enables support for the Ralink USB PHY found inside
+ RT3352, MT7620, MT7628 and MT7688.
+
config PHY_XGENE
tristate "APM X-Gene 15Gbps PHY support"
depends on HAS_IOMEM && OF && (ARM64 || COMPILE_TEST)
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f252201..60ed30b 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
obj-$(CONFIG_PHY_MT65XX_USB3) += phy-mt65xx-usb3.o
obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
obj-$(CONFIG_PHY_PISTACHIO_USB)+= phy-pistachio-usb.o
+obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
obj-$(CONFIG_ARCH_SUNXI) += allwinner/
obj-$(CONFIG_ARCH_MESON) += amlogic/
diff --git a/drivers/phy/phy-ralink-usb.c b/drivers/phy/phy-ralink-usb.c
new file mode 100644
index 000..14a254a
--- /dev/null
+++ b/drivers/phy/phy-ralink-usb.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2016 John Crispin
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define RT_SYSC_REG_SYSCFG10x014
+#define RT_SYSC_REG_CLKCFG10x030
+#define RT_SYSC_REG_USB_PHY_CFG0x05c
+
+#define RT_RSTCTRL_UDEVBIT(25)
+#define RT_RSTCTRL_UHSTBIT(22)
+#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
+
+#define MT7620_CLKCFG1_UPHY0_CLK_ENBIT(25)
+#define MT7620_CLKCFG1_UPHY1_CLK_ENBIT(22)
+#define RT_CLKCFG1_UPHY1_CLK_ENBIT(20)
+#define RT_CLKCFG1_UPHY0_CLK_ENBIT(18)
+
+#define USB_PHY_UTMI_8B60M BIT(1)
+#define UDEV_WAKEUPBIT(0)
+
+struct ralink_usb_phy {
+ struct reset_control*rstdev;
+ struct reset_control*rsthost;
+ u32 clk;
+ struct phy *phy;
+};
+
+static int ralink_usb_phy_power_on(struct phy *_phy)
+{
+ struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
+ u32 t;
+
+ /* enable the phy */
+ rt_sysc_m32(0, phy->clk, RT_SYSC_REG_CLKCFG1);
+
+ /* setup host mode */
+ rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
+
+ /* deassert the reset lines */
+ reset_control_deassert(phy->rsthost);
+ reset_control_deassert(phy->rstdev);
+
+ /*
+* The SDK kernel had a delay of 100ms. however on device
+* testing showed that 10ms is enough
+*/
+ mdelay(10);
+
+ /* print some status info */
+ t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
+ dev_info(&phy->phy->dev, "remote usb device wakeup %s\n",
+ (t & UDEV_WAKEUP) ? ("enabled") : ("disabled"));
+ if (t & USB_PHY_UTMI_8B60M)
+ dev_info(&phy->phy->dev, "UTMI 8bit 60MHz\n");
+ else
+ dev_info(&phy->phy->dev, "UTMI 16bit 30MHz\n");
+
+ return 0;
+}
+
+static
[V6 2/2] dt-bindings: phy: Add bindings for ralink-usb PHY
From: John Crispin
Add a binding for the USB phy on Mediatek/Ralink SoCs.
Signed-off-by: John Crispin
Signed-off-by: Harvey Hunt
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-media...@lists.infradead.org
---
Changes in V6:
* Add MT7628 binding
* Add optional reg property
Changes in V5:
* None
Changes in V4:
* None
Changes in V3:
* Split out from first patch
.../devicetree/bindings/phy/ralink-usb-phy.txt | 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
new file mode 100644
index 000..80cd24d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
@@ -0,0 +1,21 @@
+Mediatek/Ralink USB PHY
+
+Required properties:
+ - compatible: "ralink,rt3352-usbphy"
+ "mediatek,mt7620-usbphy"
+ "mediatek,mt7628-usbphy"
+ - reg: required for "mediatek,mt7628-usbphy"
+ - #phy-cells: should be 0
+ - resets: the two reset controllers for host and device
+ - reset-names: the names of the 2 reset controllers
+
+Example:
+
+usbphy: phy {
+ compatible = "mediatek,mt7628-usbphy";
+ reg = <0x1012 0x1000>;
+ #phy-cells = <0>;
+
+ resets = <&rstctrl 22 &rstctrl 25>;
+ reset-names = "host", "device";
+};
--
2.7.4
[V6 1/2] phy: ralink-usb: add driver for Mediatek/Ralink
From: John Crispin
Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
The driver sets up power and host mode, but also needs to
configure PHY registers for the MT7628 and MT7688.
Signed-off-by: John Crispin
Signed-off-by: Harvey Hunt
Cc: linux-kernel@vger.kernel.org
Cc: linux-media...@lists.infradead.org
---
Changes in V6
* Add binding for MT7628
* Configure PHY registers for MT76{2,8}8
Changes in V5
* Depend on MIPS
Changes in V4
* Remove Allwinner from comment
* Depend on COMPILE_TEST
Changes in V3
* Separate DT bindings
* Update Kconfig text
* Modify John's email address
* Rebase onto v4.13-rc3
Changes in V2
* remove refcounting
* drop empty functions
* dont use static globals
* use explicit compatible strings
drivers/phy/Kconfig | 9 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-ralink-usb.c | 238 +++
3 files changed, 248 insertions(+)
create mode 100644 drivers/phy/phy-ralink-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index c1807d4..a95394b 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -41,6 +41,15 @@ config PHY_PISTACHIO_USB
help
Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.
+config PHY_RALINK_USB
+ tristate "Ralink USB PHY driver"
+ depends on RALINK || COMPILE_TEST
+ depends on MIPS
+ select GENERIC_PHY
+ help
+ This option enables support for the Ralink USB PHY found inside
+ RT3352, MT7620, MT7628 and MT7688.
+
config PHY_XGENE
tristate "APM X-Gene 15Gbps PHY support"
depends on HAS_IOMEM && OF && (ARM64 || COMPILE_TEST)
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f252201..60ed30b 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
obj-$(CONFIG_PHY_MT65XX_USB3) += phy-mt65xx-usb3.o
obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
obj-$(CONFIG_PHY_PISTACHIO_USB)+= phy-pistachio-usb.o
+obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
obj-$(CONFIG_ARCH_SUNXI) += allwinner/
obj-$(CONFIG_ARCH_MESON) += amlogic/
diff --git a/drivers/phy/phy-ralink-usb.c b/drivers/phy/phy-ralink-usb.c
new file mode 100644
index 000..d027c43
--- /dev/null
+++ b/drivers/phy/phy-ralink-usb.c
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2016 John Crispin
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define RT_SYSC_REG_SYSCFG10x014
+#define RT_SYSC_REG_CLKCFG10x030
+#define RT_SYSC_REG_USB_PHY_CFG0x05c
+
+#define OFS_U2_PHY_AC0 0x800
+#define OFS_U2_PHY_AC1 0x804
+#define OFS_U2_PHY_AC2 0x808
+#define OFS_U2_PHY_ACR00x810
+#define OFS_U2_PHY_ACR10x814
+#define OFS_U2_PHY_ACR20x818
+#define OFS_U2_PHY_ACR30x81C
+#define OFS_U2_PHY_ACR40x820
+#define OFS_U2_PHY_AMON0 0x824
+#define OFS_U2_PHY_DCR00x860
+#define OFS_U2_PHY_DCR10x864
+#define OFS_U2_PHY_DTM00x868
+#define OFS_U2_PHY_DTM10x86C
+
+#define RT_RSTCTRL_UDEVBIT(25)
+#define RT_RSTCTRL_UHSTBIT(22)
+#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
+
+#define MT7620_CLKCFG1_UPHY0_CLK_ENBIT(25)
+#define MT7620_CLKCFG1_UPHY1_CLK_ENBIT(22)
+#define RT_CLKCFG1_UPHY1_CLK_ENBIT(20)
+#define RT_CLKCFG1_UPHY0_CLK_ENBIT(18)
+
+#define USB_PHY_UTMI_8B60M BIT(1)
+#define UDEV_WAKEUPBIT(0)
+
+struct ralink_usb_phy {
+ struct reset_control*rstdev;
+ struct reset_control*rsthost;
+ u32 clk;
+ struct phy *phy;
+ void __iomem*base;
+};
+
+static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg)
+{
+ iowrite32(val, phy->base + reg);
+}
+
+static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg)
+{
+ return ioread32(phy->base + reg);
+}
+
+static void
[PATCH] MIPS: dts: ralink: Add Mediatek MT7628A SoC
The MT7628A is the successor to the MT7620 and pin compatible with the
MT7688A, although the latter supports only a 1T1R antenna rather than
a 2T2R antenna.
This commit adds support for the following features:
- UART
- USB PHY
- EHCI
- Interrupt controller
- System controller
- Memory controller
- Reset controller
Signed-off-by: Harvey Hunt
Cc: John Crispin
Cc: linux-m...@linux-mips.org
Cc: devicet...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-media...@lists.infradead.org
---
Documentation/devicetree/bindings/mips/ralink.txt | 1 +
arch/mips/boot/dts/ralink/mt7628a.dtsi| 125 ++
2 files changed, 126 insertions(+)
create mode 100644 arch/mips/boot/dts/ralink/mt7628a.dtsi
diff --git a/Documentation/devicetree/bindings/mips/ralink.txt
b/Documentation/devicetree/bindings/mips/ralink.txt
index b35a8d0..a16e8d7 100644
--- a/Documentation/devicetree/bindings/mips/ralink.txt
+++ b/Documentation/devicetree/bindings/mips/ralink.txt
@@ -15,3 +15,4 @@ value must be one of the following values:
ralink,rt5350-soc
ralink,mt7620a-soc
ralink,mt7620n-soc
+ ralink,mt7628a-soc
diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi
b/arch/mips/boot/dts/ralink/mt7628a.dtsi
new file mode 100644
index 000..8461fe9
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -0,0 +1,125 @@
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,mt7628a-soc";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mti,mips24KEc";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ resetctrl: resetctrl {
+ compatible = "ralink,rt2880-reset";
+ #reset-cells = <1>;
+ };
+
+ cpuintc: cpuintc {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ palmbus@1000 {
+ compatible = "palmbus";
+ reg = <0x1000 0x20>;
+ ranges = <0x0 0x1000 0x1F>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysc@0 {
+ compatible = "ralink,mt7620a-sysc";
+ reg = <0x0 0x100>;
+ };
+
+ intc: intc@200 {
+ compatible = "ralink,rt2880-intc";
+ reg = <0x200 0x100>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ resets = <&resetctrl 9>;
+ reset-names = "intc";
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+
+ ralink,intc-registers = <0x9c 0xa0
+0x6c 0xa4
+0x80 0x78>;
+ };
+
+ memc@300 {
+ compatible = "ralink,mt7620a-memc";
+ reg = <0x300 0x100>;
+ };
+
+ uartlite@c00 {
+ compatible = "ns16550a";
+ reg = <0xc00 0x100>;
+
+ resets = <&resetctrl 12>;
+ reset-names = "uart0";
+
+ interrupt-parent = <&intc>;
+ interrupts = <20>;
+
+ reg-shift = <2>;
+ };
+
+ uart1@d00 {
+ compatible = "ns16550a";
+ reg = <0xd00 0x100>;
+
+ resets = <&resetctrl 19>;
+ reset-names = "uart1";
+
+ interrupt-parent = <&intc>;
+ interrupts = <21>;
+
+ reg-shift = <2>;
+ };
+
+ uart2@e00 {
+ compatible = "ns16550a";
+ reg = <0xe00 0x100>;
+
+ resets = <&resetctrl 20>;
+ reset-names = "uart2";
+
+ interrupt-parent = <&intc>;
+ interrupts = <22>;
+
+ reg-shift = <2>;
+ };
+ };
+
+ usbphy: uphy@1012 {
+ compatible = "mediatek,mt7628-usbphy";
+ reg = <0x1012 0x1000>
[PATCH 1/3] dt-bindings: vendors: Add VoCore as a vendor
VoCore are a manufacturer of devices such as the VoCore2. Signed-off-by: Harvey Hunt Cc: linux-kernel@vger.kernel.org Cc: devicet...@vger.kernel.org Cc: linux-m...@linux-mips.org --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index daf465be..f6e3716 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -353,6 +353,7 @@ variscite Variscite Ltd. viaVIA Technologies, Inc. virtio Virtual I/O Device Specification, developed by the OASIS consortium vivanteVivante Corporation +vocore VoCore Studio voipac Voipac Technologies s.r.o. wd Western Digital Corp. wetek WeTek Electronics, limited. -- 2.7.4
[PATCH 2/3] MIPS: dts: Add VoCore2 board
The VoCore2 board is a low cost MT7628A based board with 128MB RAM, 16MB
flash and multiple external peripherals.
This initial DTS provides enough support to get to userland and use the USB
port.
Signed-off-by: Harvey Hunt
Cc: linux-kernel@vger.kernel.org
Cc: devicet...@vger.kernel.org
Cc: linux-m...@linux-mips.org
---
MAINTAINERS | 6 ++
arch/mips/boot/dts/ralink/Makefile| 1 +
arch/mips/boot/dts/ralink/vocore2.dts | 18 ++
arch/mips/ralink/Kconfig | 5 +
4 files changed, 30 insertions(+)
create mode 100644 arch/mips/boot/dts/ralink/vocore2.dts
diff --git a/MAINTAINERS b/MAINTAINERS
index 6f7721d..82dcc6f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14127,6 +14127,12 @@ L: net...@vger.kernel.org
S: Maintained
F: drivers/net/vmxnet3/
+VOCORE VOCORE2 BOARD
+M: Harvey Hunt
+L: linux-m...@linux-mips.org
+S: Maintained
+F: arch/mips/boot/dts/ralink/vocore2.dts
+
VOLTAGE AND CURRENT REGULATOR FRAMEWORK
M: Liam Girdwood
M: Mark Brown
diff --git a/arch/mips/boot/dts/ralink/Makefile
b/arch/mips/boot/dts/ralink/Makefile
index 2a72259..a191788 100644
--- a/arch/mips/boot/dts/ralink/Makefile
+++ b/arch/mips/boot/dts/ralink/Makefile
@@ -2,6 +2,7 @@ dtb-$(CONFIG_DTB_RT2880_EVAL) += rt2880_eval.dtb
dtb-$(CONFIG_DTB_RT305X_EVAL) += rt3052_eval.dtb
dtb-$(CONFIG_DTB_RT3883_EVAL) += rt3883_eval.dtb
dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb
+dtb-$(CONFIG_DTB_VOCORE2) += vocore2.dtb
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
diff --git a/arch/mips/boot/dts/ralink/vocore2.dts
b/arch/mips/boot/dts/ralink/vocore2.dts
new file mode 100644
index 000..7591340
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/vocore2.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+#include "mt7628a.dtsi"
+
+/ {
+ compatible = "vocore,vocore2", "ralink,mt7628a-soc";
+ model = "VoCore2";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x800>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS2,115200";
+ stdout-path = "serial2:115200";
+ };
+};
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 710b04c..c2b2c2d 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -82,6 +82,11 @@ choice
depends on SOC_MT7620
select BUILTIN_DTB
+ config DTB_VOCORE2
+ bool "VoCore2"
+ depends on SOC_MT7620
+ select BUILTIN_DTB
+
endchoice
endif
--
2.7.4
[PATCH 3/3] MIPS: configs: Add VoCore2 defconfig
Enabled supported drivers, including: - USB PHY - EHCI - UART Signed-off-by: Harvey Hunt Cc: linux-kernel@vger.kernel.org Cc: linux-m...@linux-mips.org --- arch/mips/configs/vocore2_defconfig | 130 1 file changed, 130 insertions(+) create mode 100644 arch/mips/configs/vocore2_defconfig diff --git a/arch/mips/configs/vocore2_defconfig b/arch/mips/configs/vocore2_defconfig new file mode 100644 index 000..c5e0b2e --- /dev/null +++ b/arch/mips/configs/vocore2_defconfig @@ -0,0 +1,130 @@ +CONFIG_RALINK=y +CONFIG_SOC_MT7620=y +CONFIG_DTB_VOCORE2=y +CONFIG_CPU_MIPS32_R2=y +# CONFIG_COMPACTION is not set +CONFIG_HZ_100=y +CONFIG_PREEMPT=y +# CONFIG_SECCOMP is not set +CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +# CONFIG_FW_LOADER is not set +# CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_NETDEVICES=y +# CONFIG_ETHERNET is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_LEGACY_PTY_COUNT=2 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_VGA_CONSOLE is not set +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_MMC=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_MEMORY=y +CONFIG_PHY_RALINK_USB=y +# CONFIG_DNOTIFY is not set +CONFIG_PROC_KCORE=y +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_TMPFS=y +CONFIG_CONFIGFS_FS=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=y +CONFIG_NLS_CODEPAGE_775=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +CONFIG_NLS_CODEPAGE_855=y +CONFIG_NLS_CODEPAGE_857=y +CONFIG_NLS_CODEPAGE_860=y +CONFIG_NLS_CODEPAGE_861=y +CONFIG_NLS_CODEPAGE_862=y +CONFIG_NLS_CODEPAGE_863=y +CONFIG_NLS_CODEPAGE_864=y +CONFIG_NLS_CODEPAGE_865=y +CONFIG_NLS_CODEPAGE_866=y +CONFIG_NLS_CODEPAGE_869=y +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_NLS_CODEPAGE_949=y +CONFIG_NLS_CODEPAGE_874=y +CONFIG_NLS_ISO8859_8=y +CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_CODEPAGE_1251=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_ISO8859_3=y +CONFIG_NLS_ISO8859_4=y +CONFIG_NLS_ISO8859_5=y +CONFIG_NLS_ISO8859_6=y +CONFIG_NLS_ISO8859_7=y +CONFIG_NLS_ISO8859_9=y +CONFIG_NLS_ISO8859_13=y +CONFIG_NLS_ISO8859_14=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_KOI8_R=y +CONFIG_NLS_KOI8_U=y +CONFIG_NLS_UTF8=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_PANIC_ON_OOPS=y +CONFIG_PANIC_TIMEOUT=10 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_STACKTRACE=y +# CONFIG_FTRACE is not set +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRC16=y +CONFIG_XZ_DEC=y -- 2.7.4
[PATCH 1/2] MIPS: Add Onion Omega2+ board
The Onion Omega2+ is an MT7688A based board that has 128MB RAM and
multiple peripherals.
The MT7688A is pin compatible with the MT7628A, although the former
supports a 1T1R antenna whereas the MT7628A supports a 2R2T antenna.
Signed-off-by: Harvey Hunt
Cc: linux-kernel@vger.kernel.org
Cc: devicet...@vger.kernel.org
Cc: linux-m...@linux-mips.org
---
MAINTAINERS | 6 ++
arch/mips/boot/dts/ralink/Makefile| 1 +
arch/mips/boot/dts/ralink/omega2p.dts | 18 ++
arch/mips/ralink/Kconfig | 5 +
4 files changed, 30 insertions(+)
create mode 100644 arch/mips/boot/dts/ralink/omega2p.dts
diff --git a/MAINTAINERS b/MAINTAINERS
index 6f7721d..33b6bd2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9675,6 +9675,12 @@ F: drivers/regulator/twl-regulator.c
F: drivers/regulator/twl6030-regulator.c
F: include/linux/i2c-omap.h
+ONION OMEGA2+ BOARD
+M: Harvey Hunt
+L: linux-m...@linux-mips.org
+S: Maintained
+F: arch/mips/boot/dts/ralink/omega2p.dts
+
OMFS FILESYSTEM
M: Bob Copeland
L: linux-karma-de...@lists.sourceforge.net
diff --git a/arch/mips/boot/dts/ralink/Makefile
b/arch/mips/boot/dts/ralink/Makefile
index 2a72259..88da019 100644
--- a/arch/mips/boot/dts/ralink/Makefile
+++ b/arch/mips/boot/dts/ralink/Makefile
@@ -2,6 +2,7 @@ dtb-$(CONFIG_DTB_RT2880_EVAL) += rt2880_eval.dtb
dtb-$(CONFIG_DTB_RT305X_EVAL) += rt3052_eval.dtb
dtb-$(CONFIG_DTB_RT3883_EVAL) += rt3883_eval.dtb
dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb
+dtb-$(CONFIG_DTB_OMEGA2P) += omega2p.dtb
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
diff --git a/arch/mips/boot/dts/ralink/omega2p.dts
b/arch/mips/boot/dts/ralink/omega2p.dts
new file mode 100644
index 000..e44dba3
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/omega2p.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+/include/ "mt7628a.dtsi"
+
+/ {
+ compatible = "onion,omega2+", "ralink,mt7688a-soc";
+ model = "Onion Omega2+";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x800>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200";
+ };
+};
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 710b04c..6ee52bc 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -82,6 +82,11 @@ choice
depends on SOC_MT7620
select BUILTIN_DTB
+ config DTB_OMEGA2P
+ bool "Onion Omega2+"
+ depends on SOC_MT7620
+ select BUILTIN_DTB
+
endchoice
endif
--
2.7.4
[PATCH 2/2] MIPS: configs: Add Onion Omega2+ defconfig
Create a defconfig for the Omega2+ that reaches userspace and allows use of the USB port. Signed-off-by: Harvey Hunt Cc: linux-kernel@vger.kernel.org Cc: linux-m...@linux-mips.org --- arch/mips/configs/omega2p_defconfig | 130 1 file changed, 130 insertions(+) create mode 100644 arch/mips/configs/omega2p_defconfig diff --git a/arch/mips/configs/omega2p_defconfig b/arch/mips/configs/omega2p_defconfig new file mode 100644 index 000..1199daf --- /dev/null +++ b/arch/mips/configs/omega2p_defconfig @@ -0,0 +1,130 @@ +CONFIG_RALINK=y +CONFIG_SOC_MT7620=y +CONFIG_DTB_OMEGA2P=y +CONFIG_CPU_MIPS32_R2=y +# CONFIG_COMPACTION is not set +CONFIG_HZ_100=y +CONFIG_PREEMPT=y +# CONFIG_SECCOMP is not set +CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +# CONFIG_FW_LOADER is not set +# CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_NETDEVICES=y +# CONFIG_ETHERNET is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_LEGACY_PTY_COUNT=2 +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_VGA_CONSOLE is not set +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_MMC=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_MEMORY=y +CONFIG_PHY_RALINK_USB=y +# CONFIG_DNOTIFY is not set +CONFIG_PROC_KCORE=y +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_TMPFS=y +CONFIG_CONFIGFS_FS=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=y +CONFIG_NLS_CODEPAGE_775=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +CONFIG_NLS_CODEPAGE_855=y +CONFIG_NLS_CODEPAGE_857=y +CONFIG_NLS_CODEPAGE_860=y +CONFIG_NLS_CODEPAGE_861=y +CONFIG_NLS_CODEPAGE_862=y +CONFIG_NLS_CODEPAGE_863=y +CONFIG_NLS_CODEPAGE_864=y +CONFIG_NLS_CODEPAGE_865=y +CONFIG_NLS_CODEPAGE_866=y +CONFIG_NLS_CODEPAGE_869=y +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_NLS_CODEPAGE_949=y +CONFIG_NLS_CODEPAGE_874=y +CONFIG_NLS_ISO8859_8=y +CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_CODEPAGE_1251=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_ISO8859_3=y +CONFIG_NLS_ISO8859_4=y +CONFIG_NLS_ISO8859_5=y +CONFIG_NLS_ISO8859_6=y +CONFIG_NLS_ISO8859_7=y +CONFIG_NLS_ISO8859_9=y +CONFIG_NLS_ISO8859_13=y +CONFIG_NLS_ISO8859_14=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_KOI8_R=y +CONFIG_NLS_KOI8_U=y +CONFIG_NLS_UTF8=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_PANIC_ON_OOPS=y +CONFIG_PANIC_TIMEOUT=10 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_STACKTRACE=y +# CONFIG_FTRACE is not set +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRC16=y +CONFIG_XZ_DEC=y -- 2.7.4
Re: [PATCH] dt-bindings: update OpenFirmware document links to devicetree.org
Hi Rob, On 01/08/17 17:03, Rob Herring wrote: The mirrors for old, but still referenced OF documents have disappeared. A new mirror has been setup on devicetree.org at: http://devicetree.org/open-firmware/home.html [...] Thanks for finding a new mirror. Reviewed-by: Harvey Hunt Cheers, Harvey
[tip:irq/urgent] irqchip/mips-gic: Fix IRQs in gic_dev_domain
Commit-ID: 4b2312bd0592708c85ed94368c874819e7013309
Gitweb: http://git.kernel.org/tip/4b2312bd0592708c85ed94368c874819e7013309
Author: Harvey Hunt
AuthorDate: Mon, 23 May 2016 12:05:52 +0100
Committer: Thomas Gleixner
CommitDate: Tue, 14 Jun 2016 11:41:57 +0200
irqchip/mips-gic: Fix IRQs in gic_dev_domain
When allocating a new device IRQ, gic_dev_domain_alloc() correctly calls
irq_domain_set_hwirq_and_chip(), but gic_irq_domain_alloc() does not. This
means that gic_irq_domain believes all IRQs from the dev domain have an
hwirq of 0 and creates incorrect mappings in the linear_revmap. As
gic_irq_domain is a parent of the gic_dev_domain, this leads to an
inability to boot on devices with a GIC. Excerpt of the error:
[2.297649] irq 0: nobody cared (try booting with the "irqpoll" option)
...
[2.436963] handlers:
[2.439492] Disabling IRQ #0
Fix this by calling irq_domain_set_hwirq_and_chip() for both the dev and
irq domain.
Now that we are modifying the parent domain, be sure to clear it up in
case of an allocation error.
Fixes: c98c1822ee13 ("irqchip/mips-gic: Add device hierarchy domain")
Fixes: 2af70a962070 ("irqchip/mips-gic: Add a IPI hierarchy domain")
Signed-off-by: Harvey Hunt
Tested-by: Govindraj Raja # On Pistachio SoC
Reviewed-by: Matt Redfearn
Cc: linux-m...@linux-mips.org
Cc: Qais Yousef
Cc: ja...@lakedaemon.net
Cc: marc.zyng...@arm.com
Cc: sta...@vger.kernel.org
Link:
http://lkml.kernel.org/r/1464001552-31174-1-git-send-email-harvey.h...@imgtec.com
Signed-off-by: Thomas Gleixner
---
drivers/irqchip/irq-mips-gic.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 3b5e10a..8a4adbeb 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -746,6 +746,12 @@ static int gic_irq_domain_alloc(struct irq_domain *d,
unsigned int virq,
/* verify that it doesn't conflict with an IPI irq */
if (test_bit(spec->hwirq, ipi_resrv))
return -EBUSY;
+
+ hwirq = GIC_SHARED_TO_HWIRQ(spec->hwirq);
+
+ return irq_domain_set_hwirq_and_chip(d, virq, hwirq,
+&gic_level_irq_controller,
+NULL);
} else {
base_hwirq = find_first_bit(ipi_resrv, gic_shared_intrs);
if (base_hwirq == gic_shared_intrs) {
@@ -867,10 +873,14 @@ static int gic_dev_domain_alloc(struct irq_domain *d,
unsigned int virq,
&gic_level_irq_controller,
NULL);
if (ret)
- return ret;
+ goto error;
}
return 0;
+
+error:
+ irq_domain_free_irqs_parent(d, virq, nr_irqs);
+ return ret;
}
void gic_dev_domain_free(struct irq_domain *d, unsigned int virq,
