[Intel-gfx] [PATCH] drm/i915/rkl: Add DP vswing programming tables
The bspec has been updated with new vswing programming for RKL DP. No
data is provided for HDMI or eDP, so for now we'll continue to assume
that those are the same as TGL.
Bspec: 49291
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 42 ++--
1 file changed, 39 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6863236df1d0..7fb168c52c58 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -766,6 +766,34 @@ static const struct cnl_ddi_buf_trans
tgl_combo_phy_ddi_translations_edp_hbr2_ho
{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 21 */
};
+static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr[]
= {
+ /* NT mV Trans mV db*/
+ { 0xA, 0x2F, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
+ { 0xA, 0x4F, 0x37, 0x00, 0x08 },/* 350 500 3.1 */
+ { 0xC, 0x63, 0x2F, 0x00, 0x10 },/* 350 700 6.0 */
+ { 0x6, 0x7D, 0x2A, 0x00, 0x15 },/* 350 900 8.2 */
+ { 0xA, 0x4C, 0x3F, 0x00, 0x00 },/* 500 500 0.0 */
+ { 0xC, 0x73, 0x34, 0x00, 0x0B },/* 500 700 2.9 */
+ { 0x6, 0x7F, 0x2F, 0x00, 0x10 },/* 500 900 5.1 */
+ { 0xC, 0x6E, 0x3E, 0x00, 0x01 },/* 650 700 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A },/* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */
+};
+
+static const struct cnl_ddi_buf_trans
rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
+ /* NT mV Trans mV db*/
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
+ { 0xA, 0x50, 0x38, 0x00, 0x07 },/* 350 500 3.1 */
+ { 0xC, 0x61, 0x33, 0x00, 0x0C },/* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2E, 0x00, 0x11 },/* 350 900 8.2 */
+ { 0xA, 0x47, 0x3F, 0x00, 0x00 },/* 500 500 0.0 */
+ { 0xC, 0x5F, 0x38, 0x00, 0x07 },/* 500 700 2.9 */
+ { 0x6, 0x7F, 0x2F, 0x00, 0x10 },/* 500 900 5.1 */
+ { 0xC, 0x5F, 0x3F, 0x00, 0x00 },/* 650 700 0.6 */
+ { 0x6, 0x7E, 0x36, 0x00, 0x09 },/* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */
+};
+
static bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
{
return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
@@ -1259,7 +1287,10 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
if (crtc_state->port_clock > 27) {
- if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
+ if (IS_ROCKETLAKE(dev_priv)) {
+ *n_entries =
ARRAY_SIZE(rkl_combo_phy_ddi_translations_dp_hbr2_hbr3);
+ return rkl_combo_phy_ddi_translations_dp_hbr2_hbr3;
+ } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
*n_entries =
ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
} else {
@@ -1267,8 +1298,13 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
return tgl_combo_phy_ddi_translations_dp_hbr2;
}
} else {
- *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
- return tgl_combo_phy_ddi_translations_dp_hbr;
+ if (IS_ROCKETLAKE(dev_priv)) {
+ *n_entries =
ARRAY_SIZE(rkl_combo_phy_ddi_translations_dp_hbr);
+ return rkl_combo_phy_ddi_translations_dp_hbr;
+ } else {
+ *n_entries =
ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
+ return tgl_combo_phy_ddi_translations_dp_hbr;
+ }
}
}
--
2.24.1
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Re: [Intel-gfx] [PATCH V2] drm/i915/cml : Add TGP PCH support
On Mon, Dec 28, 2020 at 11:42:35AM +0530, Tejas Upadhyay wrote:
> We have TGP PCH support for Tigerlake and Rocketlake. Similarly
> now TGP PCH can be used with Cometlake CPU.
Based on the 'compatibility' section of bspec 49181, I think the TGP PCH
can technically be compatible with any gen9bc platform, not just CML.
Although it seems unlikely that anyone is going to go back and create
new products with a SKL+TGP pairing or something at this point, it's
still probably best to write this patch based on GEN9_BC rather than
CML.
>
> Changes since V1 :
> - Matched HPD Pin mapping for PORT C and PORT D of CML CPU.
>
> Cc : Matt Roper
> Cc : Ville Syrjälä
> Signed-off-by: Tejas Upadhyay
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 7 +--
> drivers/gpu/drm/i915/display/intel_display.c | 5 +
> drivers/gpu/drm/i915/display/intel_hdmi.c| 3 ++-
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 17eaa56c5a99..181d60a5e145 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -5301,7 +5301,9 @@ static enum hpd_pin dg1_hpd_pin(struct drm_i915_private
> *dev_priv,
> static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
> enum port port)
> {
> - if (port >= PORT_TC1)
> + if (IS_COMETLAKE(dev_priv) && port >= PORT_C)
> + return HPD_PORT_TC1 + port + 1 - PORT_TC1;
> + else if (port >= PORT_TC1)
> return HPD_PORT_TC1 + port - PORT_TC1;
> else
> return HPD_PORT_A + port - PORT_A;
> @@ -5455,7 +5457,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
>
> if (IS_DG1(dev_priv))
> encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
> - else if (IS_ROCKETLAKE(dev_priv))
> + else if (IS_ROCKETLAKE(dev_priv) || (IS_COMETLAKE(dev_priv) &&
> + HAS_PCH_TGP(dev_priv)))
> encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
> else if (INTEL_GEN(dev_priv) >= 12)
I'd suggest leaving the RKL condition alone since nothing here has
anything to do with RKL. Instead change the gen12+ condition to
HAS_PCH_TGP() and update the TGP-specific handler to do the port mapping
described on bspec 49181.
Plus I don't think what you have here would map the ports correctly
anyway. gen9 PORT_C/PORT_D would map to HPD_PORT_C/HPD_PORT_TC1 with
the logic here, whereas the bspec says they should map to
HPD_PORT_TC1/HPD_PORT_TC2.
> encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f2c48e5cdb43..47014471658f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16163,6 +16163,11 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> intel_ddi_init(dev_priv, PORT_F);
>
> icl_dsi_init(dev_priv);
> + } else if (IS_COMETLAKE(dev_priv) && HAS_PCH_TGP(dev_priv)) {
> + intel_ddi_init(dev_priv, PORT_A);
> + intel_ddi_init(dev_priv, PORT_B);
> + intel_ddi_init(dev_priv, PORT_C);
> + intel_ddi_init(dev_priv, PORT_D);
As noted before, this relates to gen9bc in general, not just CML.
Is the only reason for this block because TGP's instance of SFUSE_STRAP
doesn't have output presence bits anymore? If you want, you could keep
using the existing gen9bc block for consistency, but make the
SFUSE_STRAP checks themselves conditional on a platform that has the
presence bits. E.g.,
/* ICP+ no longer has port presence bits */
found = INTEL_PCH_TYPE(dev_priv) >= PCH_ICP ?
~0 : intel_de_read(dev_priv, SFUSE_STRAP);
> } else if (IS_GEN9_LP(dev_priv)) {
> /*
>* FIXME: Broxton doesn't support port detection via the
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index c5959590562b..540c9d54b595 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3174,7 +3174,8 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder
> *encoder)
>
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
> - else if (IS_ROCKETLAKE(dev_priv))
> + else if (IS_ROCKETLAKE(dev_priv) || (IS_COMETLAKE(dev_priv) &&
> +
Re: [Intel-gfx] [PATCH] drm/i915/dp: Remove aux xfer timeout debug message
On Wed, Dec 30, 2020 at 10:37:42AM +, Chris Wilson wrote:
> The timeouts are frequent and expected. We will complain if we retry so
> often as to lose patience and give up, so the cacophony from individual
> complaints is redundant.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8ae769b18879..704e4cebf7f3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1613,8 +1613,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> /* Timeouts occur when the device isn't connected, so they're
>* "normal" -- don't fill the kernel log with these */
> if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
> - drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
> - intel_dp->aux.name, status);
> ret = -ETIMEDOUT;
> goto out;
> }
> --
> 2.20.1
>
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[Intel-gfx] [PATCH] drm/i915: Clarify error message on failed workaround
Let's modify the "workaround lost" error message slightly to make it
more clear what the various numbers represent. Also, the 'expected'
value needs to be &'d with wa->read so that it doesn't include the mask
bits for masked registers (those bits are write-only in the hardware and
will usually always read out as 0's).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 42d320e68b60..b0e3a5ba0320 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1383,9 +1383,9 @@ static bool
wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char
*from)
{
if ((cur ^ wa->set) & wa->read) {
- DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x)\n",
+ DRM_ERROR("%s workaround lost on %s! (reg[%x]=0x%x, relevant
bits were 0x%x vs expected 0x%x)\n",
name, from, i915_mmio_reg_offset(wa->reg),
- cur, cur & wa->read, wa->set);
+ cur, cur & wa->read, wa->set & wa->read);
return false;
}
--
2.24.1
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Re: [Intel-gfx] [PATCH V2] drm/i915/cml : Add TGP PCH support
On Thu, Dec 31, 2020 at 12:48:06AM -0800, Surendrakumar Upadhyay, TejaskumarX
wrote:
>
>
> > -Original Message-
> > From: Matt Roper
> > Sent: 31 December 2020 05:31
> > To: Surendrakumar Upadhyay, TejaskumarX
> >
> > Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
> >
> > Subject: Re: [Intel-gfx] [PATCH V2] drm/i915/cml : Add TGP PCH support
> >
> > On Mon, Dec 28, 2020 at 11:42:35AM +0530, Tejas Upadhyay wrote:
> > > We have TGP PCH support for Tigerlake and Rocketlake. Similarly now
> > > TGP PCH can be used with Cometlake CPU.
> >
> > Based on the 'compatibility' section of bspec 49181, I think the TGP PCH can
> > technically be compatible with any gen9bc platform, not just CML.
> > Although it seems unlikely that anyone is going to go back and create new
> > products with a SKL+TGP pairing or something at this point, it's still
> > probably
> > best to write this patch based on GEN9_BC rather than CML.
> >
>
>
> Tejas : This patch is generated to support DELL's requirement where they are
> using CML CPU + TGP PCH. But I agree if we want to change CML with GEN9_BC.
> Please have a look at https://gitlab.freedesktop.org/drm/intel/-/issues/2742
> and this patch has been verified by DELL as working for all of their
> platforms with CML CPU + TGP PCH (Off course it worked after I gave local
> workaround of Lee Shawn's patch
> https://patchwork.freedesktop.org/patch/401301/?series=83154&rev=5). Also
> this patch +
> https://patchwork.freedesktop.org/patch/401301/?series=83154&rev=5 (Lee
> Shawn's patch reviewed by you) + Adding IS_COMETLAKE check to Lee Shawn's
> patch needs to be merged by Jan 4th to complete upstreaming for CML CPU + TGP
> PCH. DELL is having critical requirement to finish upstreaming by Jan 4th.
The changes from Shawn are to make RKL (a gen12 platform) work with the
older gen9-style CMP PCH. What you're doing here is making a gen9
platform work with a newer gen12-style TGP PCH. Although those are
converses of each other, I don't think the driver changes should depend
on each other. Shawn's series shouldn't be necessary for your work or
vice versa. I'm not sure when Shawn plans to merge his series; I had
some further changes suggested, so he might be working on those before
merging his work.
I'm not sure what leads to the Jan 4th date, but assuming "finish
upstreaming" means that you want the patch to land in a final release
kernel by that date, there's pretty much no way that would be possible
at this point. Getting patches like this reviewed and applied to an
Intel tree is only the first step along the maintainer chain that
eventually leads to a release from Linus or a stable kernel maintainer.
Plus when a customer says they want something upstream, one of the most
important things for them is that the patch has been fully reviewed and
tested and has a relatively high chance of being correct. We can't rush
patches in to meet deadlines if we think they're only going to work in
certain situations and cause problems for other ones.
One other thing that I don't see addressed anywhere in this patch is
that the driver doesn't consider gen9 + TGP to be a valid combination
and will throw a warning in intel_pch_type() if detected.
>
> > >
> > > Changes since V1 :
> > > - Matched HPD Pin mapping for PORT C and PORT D of CML CPU.
> > >
> > > Cc : Matt Roper Cc : Ville Syrjälä
> > >
> > > Signed-off-by: Tejas Upadhyay
> > >
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 7 +--
> > > drivers/gpu/drm/i915/display/intel_display.c | 5 +
> > > drivers/gpu/drm/i915/display/intel_hdmi.c| 3 ++-
> > > 3 files changed, 12 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index 17eaa56c5a99..181d60a5e145 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -5301,7 +5301,9 @@ static enum hpd_pin dg1_hpd_pin(struct
> > > drm_i915_private *dev_priv, static enum hpd_pin tgl_hpd_pin(struct
> > drm_i915_private *dev_priv,
> > > enum port port)
> > > {
> > > -if (port >= PORT_TC1)
> > > +if (IS_COMETLAKE(dev_priv) && port >= PORT_C)
> > > +return HPD_PORT_TC1 + port + 1 - PORT_TC1;
Why is the offset written as "port + 1 - PORT_TC1?" This platform
doesn't have TC ports as inputs, so it's completely unintuitive how
Re: [Intel-gfx] [PATCH] drm/i915: Fix HTI port checking
On Fri, Jan 08, 2021 at 05:48:02AM -0800, José Roberto de Souza wrote:
> There was some misinterpretation of specification, when DDIX_USED is
> set, the next bit means 0 for DP and 1 for HDMI.
>
> Anyways this misinterpretation is not causing any issues, this change
> is just to comply with specification.
> Also as for us it do not matters if it is HDMI or DP, not checking the
> port type that HTI is using.
>
> Cc: Anusha Srivatsa
> Cc: Matt Roper
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +--
> drivers/gpu/drm/i915/i915_reg.h | 3 +--
> 2 files changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3df6913369bc..e90d1af1a54d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -5321,8 +5321,7 @@ intel_ddi_max_lanes(struct intel_digital_port *dig_port)
> static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
> {
> return i915->hti_state & HDPORT_ENABLED &&
> - (i915->hti_state & HDPORT_PHY_USED_DP(phy) ||
> - i915->hti_state & HDPORT_PHY_USED_HDMI(phy));
> +i915->hti_state & HDPORT_DDI_USED(phy);
> }
>
> static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0023c023f472..1d8ba10847ca 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2928,8 +2928,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>
> #define HDPORT_STATE _MMIO(0x45050)
> #define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12)
> -#define HDPORT_PHY_USED_DP(phy)REG_BIT(2 * (phy) + 2)
> -#define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1)
> +#define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1)
> #define HDPORT_ENABLED REG_BIT(0)
>
> /* Make render/texture TLB fetches lower priorty than associated data
> --
> 2.30.0
>
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Re: [Intel-gfx] [PATCH] drm/i915/gt: Prevent use of engine->wa_ctx after error
On Fri, Jan 08, 2021 at 03:09:24PM +, Chris Wilson wrote:
> On error we unpin and free the wa_ctx.vma, but do not clear any of the
> derived flags. During lrc_init, we look at the flags and attempt to
> dereference the wa_ctx.vma if they are set. To protect the error path
> where we try to limp along without the wa_ctx, make sure we clear those
> flags!
>
> Reported-by: Matt Roper
> Fixes: 604a8f6f1e33 ("drm/i915/lrc: Only enable per-context and per-bb
> buffers if set")
> Signed-off-by: Chris Wilson
> Cc: Matt Roper
> Cc: Tvrtko Ursulin
> Cc: Mika Kuoppala
> Cc: # v4.15+
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 4e856947fb13..703d9ecc3f7e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1453,6 +1453,9 @@ static int lrc_setup_wa_ctx(struct intel_engine_cs
> *engine)
> void lrc_fini_wa_ctx(struct intel_engine_cs *engine)
> {
> i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);
> +
> + /* Called on error unwind, clear all flags to prevent further use */
> + memset(&engine->wa_ctx, 0, sizeof(engine->wa_ctx));
> }
>
> typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
> --
> 2.20.1
>
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[Intel-gfx] [PATCH v2] drm/i915/dg1: Update voltage swing tables for DP
DG1's vswing tables are the same for eDP and HDMI but have slight
differences from ICL/TGL for DP.
v2:
- Use a "_hbr2_hbr3" suffix on the table name to make it more clear
that the same table is used for both HBR2 and HBR3 link rates.
(Swathi)
Bspec: 49291
Cc: Clinton Taylor
Cc: José Roberto de Souza
Cc: Radhakrishna Sripada
Cc: Swathi Dhanavanthri
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 34
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3df6913369bc..a047fd81e433 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -611,6 +611,34 @@ static const struct cnl_ddi_buf_trans
jsl_combo_phy_ddi_translations_edp_hbr2[]
{ 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
};
+static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr[]
= {
+ /* NT mV Trans mV db*/
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
+ { 0xA, 0x48, 0x35, 0x00, 0x0A },/* 350 500 3.1 */
+ { 0xC, 0x63, 0x2F, 0x00, 0x10 },/* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2C, 0x00, 0x13 },/* 350 900 8.2 */
+ { 0xA, 0x43, 0x3F, 0x00, 0x00 },/* 500 500 0.0 */
+ { 0xC, 0x60, 0x36, 0x00, 0x09 },/* 500 700 2.9 */
+ { 0x6, 0x7F, 0x30, 0x00, 0x0F },/* 500 900 5.1 */
+ { 0xC, 0x60, 0x3F, 0x00, 0x00 },/* 650 700 0.6 */
+ { 0x6, 0x7F, 0x37, 0x00, 0x08 },/* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */
+};
+
+static const struct cnl_ddi_buf_trans
dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
+ /* NT mV Trans mV db*/
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
+ { 0xA, 0x48, 0x35, 0x00, 0x0A },/* 350 500 3.1 */
+ { 0xC, 0x63, 0x2F, 0x00, 0x10 },/* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2C, 0x00, 0x13 },/* 350 900 8.2 */
+ { 0xA, 0x43, 0x3F, 0x00, 0x00 },/* 500 500 0.0 */
+ { 0xC, 0x60, 0x36, 0x00, 0x09 },/* 500 700 2.9 */
+ { 0x6, 0x7F, 0x30, 0x00, 0x0F },/* 500 900 5.1 */
+ { 0xC, 0x58, 0x3F, 0x00, 0x00 },/* 650 700 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A },/* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */
+};
+
struct icl_mg_phy_ddi_buf_trans {
u32 cri_txdeemph_override_11_6;
u32 cri_txdeemph_override_5_0;
@@ -1121,6 +1149,12 @@ icl_get_combo_buf_trans_edp(struct intel_encoder
*encoder,
} else if (dev_priv->vbt.edp.low_vswing) {
*n_entries =
ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
return icl_combo_phy_ddi_translations_edp_hbr2;
+ } else if (IS_DG1(dev_priv) && crtc_state->port_clock > 27) {
+ *n_entries =
ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2_hbr3);
+ return dg1_combo_phy_ddi_translations_dp_hbr2_hbr3;
+ } else if (IS_DG1(dev_priv)) {
+ *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr);
+ return dg1_combo_phy_ddi_translations_dp_hbr;
}
return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
--
2.24.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gt: Exercise lrc_wa_ctx initialisation failure
On Fri, Jan 08, 2021 at 08:51:14PM +, Chris Wilson wrote: > Inject a fault into lrc_init_wa_ctx() to ensure that we can tolerate a > failure to construct the workarounds. > > Signed-off-by: Chris Wilson > Cc: Matt Roper Reviewed-by: Matt Roper > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c > b/drivers/gpu/drm/i915/gt/intel_lrc.c > index 703d9ecc3f7e..f0de3f661042 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -1525,6 +1525,9 @@ int lrc_init_wa_ctx(struct intel_engine_cs *engine) > > __i915_gem_object_flush_map(wa_ctx->vma->obj, 0, batch_ptr - batch); > __i915_gem_object_release_map(wa_ctx->vma->obj); > + > + if (i915_inject_probe_error(engine->i915, -ENODEV)) > + ret = -ENODEV; > if (ret) > lrc_fini_wa_ctx(engine); > > -- > 2.20.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
On Fri, Jan 08, 2021 at 03:18:52PM -0800, Aditya Swarup wrote:
> TGL adds another level of indirection for applying WA based on stepping
> information rather than PCI REVID. So change TGL_REVID enum into
> stepping enum and use PCI REVID as index into revid to stepping table to
> fetch correct display and GT stepping for application of WAs as
> suggested by Matt Roper.
So to clarify the goal is to rename "revid" -> "stepping" because the
values like "A1," "C0," etc. are't the actual PCI revision ID, but
rather descriptions of the stepping of a given IP block; the enum values
we use to represent those are arbitrary and don't matter as long as
they're monotonically increasing for comparisons. The PCI revision ID
is just the input we use today to deduce what the IP steppings are, and
there's talk that we could determine the IP steppings in a different way
at some point in the future.
Furthermore, since the same scheme will be used at least for ADL-S, we
should drop the "TGL" prefix since there's no need to name these general
enum values in a platform-specific manner.
Reviewed-by: Matt Roper
We should probably make the same kind of change to KBL (and use the same
stepping enum) too since it has the same kind of extra indirection as
TGL/ADL-S, but we can do that as a followup patch.
Matt
>
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Cc: José Roberto de Souza
> Signed-off-by: Aditya Swarup
> ---
> .../drm/i915/display/intel_display_power.c| 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 4 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 +-
> drivers/gpu/drm/i915/i915_drv.h | 50 +--
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 6 files changed, 43 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index d52374f01316..bb04b502a442 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5340,7 +5340,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private
> *dev_priv)
> int config, i;
>
> if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> - IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> + IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
> /* Wa_1409767108:tgl,dg1 */
> table = wa_1409767108_buddy_page_masks;
> else
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index c24ae69426cf..a93717178957 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>
> if (dev_priv->psr.psr2_sel_fetch_enabled) {
> /* WA 1408330847 */
> - if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> + if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
> IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
>
> /* WA 1408330847 */
> if (dev_priv->psr.psr2_sel_fetch_enabled &&
> - (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> + (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index cf3589fd0ddb..4ce32df3855f 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -3033,7 +3033,7 @@ static bool gen12_plane_supports_mc_ccs(struct
> drm_i915_private *dev_priv,
> {
> /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
> if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
> - IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
> + IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
> return false;
>
> return plane_id < PLANE_SPRITE4;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index c21a9726326a..111d01e2f81e 100644
>
Re: [Intel-gfx] [PATCH 2/2] drm/i915/adl_s: Add ADL-S platform info and PCI ids
On Fri, Jan 08, 2021 at 03:18:53PM -0800, Aditya Swarup wrote:
> From: Caz Yokoyama
>
> - Add the initial platform information for Alderlake-S.
> - Specify ppgtt_size value
> - Add dma_mask_size
> - Add ADLS REVIDs
> - HW tracking(Selective Update Tracking Enable) has been
> removed from ADLS. Disable PSR2 till we enable software/
> manual tracking.
>
> v2:
> - Add support for different ADLS SOC steppings to select
> correct GT/DISP stepping based on Bspec 53655 based on
> feedback from Matt Roper.(aswarup)
>
> v3:
> - Make display/gt steppings info generic for reuse with TGL and ADLS.
> - Modify the macros to reuse tgl_revids_get()
> - Add HTI support to adls device info.(mdroper)
>
> v4:
> - Rebase on TGL patch for applying WAs based on stepping info from
> Matt Roper's feedback.(aswarup)
>
> Bspec: 53597
> Bspec: 53648
> Bspec: 53655
> Bspec: 48028
> Bspec: 53650
> BSpec: 50422
>
> Cc: José Roberto de Souza
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Cc: Anusha Srivatsa
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Signed-off-by: Caz Yokoyama
> Signed-off-by: Aditya Swarup
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++
> drivers/gpu/drm/i915/i915_drv.h | 27 -
> drivers/gpu/drm/i915/i915_pci.c | 13 ++
> drivers/gpu/drm/i915/intel_device_info.c| 1 +
> drivers/gpu/drm/i915/intel_device_info.h| 1 +
> include/drm/i915_pciids.h | 11 +
> 6 files changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 111d01e2f81e..c89bd653af17 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -84,6 +84,14 @@ const struct i915_rev_steppings tgl_revid_step_tbl[] = {
> [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
> };
>
> +const struct i915_rev_steppings adls_revid_step_tbl[] = {
> + [ADLS_REVID_A0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
> + [ADLS_REVID_A2] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 },
> + [ADLS_REVID_B0] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 },
> + [ADLS_REVID_G0] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 },
> + [ADLS_REVID_C0] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 },
> +};
Now that we've disassociated IP steppings from revision ID, I don't
think we should use stepping terminology for the constant inputs to the
array anymore. The terms you're using seem to roughly correspond to
what the bspec refers to as "SOC stepping" but even that's not terribly
accurate since, for example, PCI revision ID 0xC is used for SoC
steppings C0, C1, D0, and H0. I'd just use the exact numeric PCI ID as
documented in the bspec to remove any ambiguity:
const struct i915_rev_steppings adls_revid_step_tbl[] = {
[0x0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
[0x1] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 },
[0x4] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 },
[0x8] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 },
[0xC] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 },
};
That also matches how we're indexing into the TGL arrays.
Matt
> +
> static void wa_init_start(struct i915_wa_list *wal, const char *name, const
> char *engine_name)
> {
> wal->name = name;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 11d6e8abde46..8d8a046a7b0c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1417,6 +1417,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
> #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
> #define IS_DG1(dev_priv)IS_PLATFORM(dev_priv, INTEL_DG1)
> +#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) \
> @@ -1560,6 +1561,7 @@ extern const struct i915_rev_steppings kbl_revids[];
>
> enum {
> STEP_A0,
> + STEP_A2,
> STEP_B0,
> STEP_B1,
> STEP_C0,
> @@ -1568,9 +1570,11 @@ enum {
>
> #define TGL_UY_REVID_STEP_TBL_SIZE 4
> #define TGL_REVID_STEP_TBL_SIZE 2
> +#define AD
Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
On Mon, Jan 11, 2021 at 10:18:45PM +0200, Jani Nikula wrote: > On Mon, 11 Jan 2021, Jani Nikula wrote: > > On Fri, 08 Jan 2021, Matt Roper wrote: > >> On Fri, Jan 08, 2021 at 03:18:52PM -0800, Aditya Swarup wrote: > >>> TGL adds another level of indirection for applying WA based on stepping > >>> information rather than PCI REVID. So change TGL_REVID enum into > >>> stepping enum and use PCI REVID as index into revid to stepping table to > >>> fetch correct display and GT stepping for application of WAs as > >>> suggested by Matt Roper. > >> > >> So to clarify the goal is to rename "revid" -> "stepping" because the > >> values like "A1," "C0," etc. are't the actual PCI revision ID, but > >> rather descriptions of the stepping of a given IP block; the enum values > >> we use to represent those are arbitrary and don't matter as long as > >> they're monotonically increasing for comparisons. The PCI revision ID > >> is just the input we use today to deduce what the IP steppings are, and > >> there's talk that we could determine the IP steppings in a different way > >> at some point in the future. > >> > >> Furthermore, since the same scheme will be used at least for ADL-S, we > >> should drop the "TGL" prefix since there's no need to name these general > >> enum values in a platform-specific manner. > >> > >> Reviewed-by: Matt Roper > >> > >> We should probably make the same kind of change to KBL (and use the same > >> stepping enum) too since it has the same kind of extra indirection as > >> TGL/ADL-S, but we can do that as a followup patch. > > > > FWIW I have a wip series changing the whole thing to abstract steppings > > enums that are shared between platforms, but it's in a bit of limbo > > because the previous revid changes were applied to drm-intel-gt-next, > > and it's fallen pretty far out of sync with drm-intel-next. All of this > > really belongs to drm-intel-next, but can't do that until the branches > > sync up again. > > Btw this series doesn't apply to drm-intel-next either, for the same > reason, and the ADL-S platform definition and PCI IDs must *not* be > applied to drm-intel-gt-next. So to clarify, it looks like we have a bunch of revid changes to the display code that got merged to the gt-next tree but not to the intel-next tree? Should we be going back and also merging / cherry-picking those over to intel-next since that's where the display changes are supposed to go, or is it too late to do that cleanly at this point? Going forward, what should the general strategy be for stuff like platform definitions and such? Merge such enablement patches to both intel-next and gt-next at the same time so that the basic definitions are available to both trees? It seems like the whole split into two trees really isn't working well and is just leading to more mistakes and bottlenecks. What benefit are we supposed to be getting from this split? Matt > > BR, > Jani. > > > > > My series also completely hides the arrays into a separate .c file, > > because the externs with direct array access are turning into > > nightmare. The ARRAY_SIZE() checks rely on the extern declaration and > > the actual array definition to have the sizes in sync, but the compiler > > does not check that. Really. > > > > IDK, feels like this merging this series is going to be extra churn. > > > > > > BR, > > Jani. > > > > > >> > >> > >> Matt > >> > >>> > >>> Cc: Matt Roper > >>> Cc: Lucas De Marchi > >>> Cc: José Roberto de Souza > >>> Signed-off-by: Aditya Swarup > >>> --- > >>> .../drm/i915/display/intel_display_power.c| 2 +- > >>> drivers/gpu/drm/i915/display/intel_psr.c | 4 +- > >>> drivers/gpu/drm/i915/display/intel_sprite.c | 2 +- > >>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 +- > >>> drivers/gpu/drm/i915/i915_drv.h | 50 +-- > >>> drivers/gpu/drm/i915/intel_pm.c | 2 +- > >>> 6 files changed, 43 insertions(+), 43 deletions(-) > >>> > >>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c > >>> b/drivers/gpu/drm/i915/display/intel_display_power.c > >>> index d52374f01316..bb04b502a442 100644 > >>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c > &
Re: [Intel-gfx] [PATCH V4] drm/i915/gen9_bc : Add TGP PCH support
On Mon, Jan 11, 2021 at 07:21:55PM -0500, Rodrigo Vivi wrote:
> On Fri, Jan 08, 2021 at 05:39:22PM +0530, Tejas Upadhyay wrote:
> > We have TGP PCH support for Tigerlake and Rocketlake. Similarly
> > now TGP PCH can be used with Cometlake CPU.
> >
> > Changes since V3 :
> > - Rebased to top drm-tip commit
> > - dev_priv replaced with i915 for new API
> > - Enable default Port B,C,D detection for TGP && GEN9_BC
> > Changes since V2 :
> > - IS_COMETLAKE replaced with IS_GEN9_BC
> > - VBT ddc pin remapping added
> > - Added dedicated HPD pin and DDC pin handling API
> > Changes since V1 :
> > - Matched HPD Pin mapping for PORT C and PORT D of CML CPU.
> >
> > Cc: Matt Roper
> > Cc: Jani Nikula
> > Signed-off-by: Tejas Upadhyay
> > ---
> > drivers/gpu/drm/i915/display/intel_bios.c| 9 +
> > drivers/gpu/drm/i915/display/intel_ddi.c | 7 +--
> > drivers/gpu/drm/i915/display/intel_display.c | 9 -
> > drivers/gpu/drm/i915/display/intel_hdmi.c| 20
> > drivers/gpu/drm/i915/intel_pch.c | 3 ++-
> > 5 files changed, 44 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index 987cf509337f..730b7f45e5d4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -1630,6 +1630,12 @@ static const u8 rkl_pch_tgp_ddc_pin_map[] = {
> > [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP,
> > };
> >
> > +static const u8 gen9bc_tgp_ddc_pin_map[] = {
> > + [DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
> > + [DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,
> > + [DDC_BUS_DDI_D] = GMBUS_PIN_10_TC2_ICP,
> > +};
>
> Could you please point out the spec you are using here?
>
> VBT's spec at BSpec - at Block 2
> I can see the TGP table is same as ICP.
>
> So I'm kind of confused now.
It's a weird place to document it, but bspec 49181 has a compatibility
section that describes how to map the TGP pins when paired with a gen9bc
CPU.
>
> > +
> > static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
> > {
> > const u8 *ddc_pin_map;
> > @@ -1640,6 +1646,9 @@ static u8 map_ddc_pin(struct drm_i915_private
> > *dev_priv, u8 vbt_pin)
> > } else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) ==
> > PCH_TGP) {
> > ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
> > n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
> > + } else if (HAS_PCH_TGP(dev_priv) && IS_GEN9_BC(dev_priv)) {
> > + ddc_pin_map = gen9bc_tgp_ddc_pin_map;
> > + n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map);
> > } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
> > ddc_pin_map = icp_ddc_pin_map;
> > n_entries = ARRAY_SIZE(icp_ddc_pin_map);
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 3df6913369bc..13f1268e2cff 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -5337,7 +5337,9 @@ static enum hpd_pin dg1_hpd_pin(struct
> > drm_i915_private *dev_priv,
> > static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
> > enum port port)
> > {
> > - if (port >= PORT_TC1)
> > + if (IS_GEN9_BC(dev_priv) && port >= PORT_C)
>
> gen9 in tgl function?!
> please, no!
We should probably rename this function to tgp since it ultimately gets
called on every possible TGP platform (TGL+TGP, RKL+TGP, gen9+TGP). If
it weren't for RKL+CMP, I'd say that all these functions should just be
named after the PCH, but I guess the TC ports on RKL+CMP break the
pattern.
I think the real plan once we get some free time is to kill off a bunch
of these output-based functions and define DDI/port/phy/VBT/HPD/DDC
mapping for outputs declaratively in a table since all the special cases
we're running into on recent platforms are turning the logic-based
approach into a mess.
>
> > + return HPD_PORT_TC1 + port - PORT_C;
> > + else if (port >= PORT_TC1)
> > return HPD_PORT_TC1 + port - PORT_TC1;
> > else
> > return HPD_PORT_A + port - PORT_A;
> > @@ -5493,7 +5495,8 @@ void intel_ddi_init(struct drm_i915_private
> > *dev_priv, enum port port)
> > encoder->hpd_pin =
Re: [Intel-gfx] [PATCH 07/22] drm/i915/adl_s: Add PHYs for Alderlake S
On Fri, Dec 04, 2020 at 05:08:29PM -0800, Aditya Swarup wrote:
> From: Anusha Srivatsa
>
> Alderlake-S has 5 combo phys, add reg definitions for
> combo phys and update the port to phy helper for ADL-S.
>
> v2:
> - Change IS_GEN() >= 12 to IS_TIGERLAKE() in intel_phy_is_tc()
> and return false for platforms RKL,DG1 and ADLS.(mdroper)
>
> Cc: Lucas De Marchi
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Cc: Matt Roper
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Aditya Swarup
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 ++
> drivers/gpu/drm/i915/i915_reg.h | 5 -
> 2 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 9187a20a8aca..2d1c5bfe4032 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7397,6 +7397,8 @@ bool intel_phy_is_combo(struct drm_i915_private
> *dev_priv, enum phy phy)
> {
> if (phy == PHY_NONE)
> return false;
> + else if (IS_ALDERLAKE_S(dev_priv))
> + return phy <= PHY_E;
> else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> return phy <= PHY_D;
> else if (IS_JSL_EHL(dev_priv))
> @@ -7409,9 +7411,7 @@ bool intel_phy_is_combo(struct drm_i915_private
> *dev_priv, enum phy phy)
>
> bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> {
> - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> - return false;
> - else if (INTEL_GEN(dev_priv) >= 12)
> + if (IS_TIGERLAKE(dev_priv))
> return phy >= PHY_D && phy <= PHY_I;
> else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv))
> return phy >= PHY_C && phy <= PHY_F;
> @@ -7421,7 +7421,9 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv,
> enum phy phy)
>
> enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
> {
> - if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
> + if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
> + return PHY_B + port - PORT_TC1;
> + else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
> return PHY_C + port - PORT_TC1;
> else if (IS_JSL_EHL(i915) && port == PORT_D)
> return PHY_A;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cdc67f583a9c..60a0d4c35cae 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1874,10 +1874,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define _ICL_COMBOPHY_B 0x6C000
> #define _EHL_COMBOPHY_C 0x16
> #define _RKL_COMBOPHY_D 0x161000
> +#define _ADL_COMBOPHY_E 0x16B000
> +
> #define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
> _ICL_COMBOPHY_B, \
> _EHL_COMBOPHY_C, \
> - _RKL_COMBOPHY_D)
> + _RKL_COMBOPHY_D, \
> + _ADL_COMBOPHY_E)
>
> /* CNL/ICL Port CL_DW registers */
> #define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
> --
> 2.27.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 08/22] drm/i915/adl_s: Configure DPLL for ADL-S
On Fri, Dec 04, 2020 at 05:08:30PM -0800, Aditya Swarup wrote: > Add changes for configuring DPLL for ADL-S > - Reusing DG1 DPLL 2 & DPLL 3 for ADL-S > - Extend CNL macro to choose DPLL_ENABLE > for ADL-S. > - Select CFGCR0 and CFGCR1 for ADL-S plls. > > On BSpec: 53720 PLL arrangement dig for adls: > DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1) > DPLL3 cfgcr is programmed using _ADLS_DPLL4_CFGCR(0/1) 53720 shows DPLL's 0/1/2/3 in the diagram but the registers are named as DPLL 0/1/3/4 (no #2). I don't see anywhere on 53720 that it explicitly gives the mapping you mention here, but on page 53723 I see a note: Due to current BSpec filtering limitations, the DPLL4_CRCFG0/1 (164294h/164298h) are used to control the DPLL2. Assuming that's correct, the patch below has the registers for the last two DPLL's swapped. ... > + > +#define _ADLS_DPLL3_CFGCR1 0x1642C4 > +#define _ADLS_DPLL4_CFGCR1 0x164298 > +#define ADLS_DPLL_CFGCR1(pll)_MMIO_PLL3(pll, > _TGL_DPLL0_CFGCR1, \ > +_TGL_DPLL1_CFGCR1, \ > +_ADLS_DPLL3_CFGCR1, \ > +_ADLS_DPLL4_CFGCR1) I.e., this should be #define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ _TGL_DPLL1_CFGCR1, \ _ADLS_DPLL4_CFGCR1, \ _ADLS_DPLL3_CFGCR1) Given the strange spec naming, I think this calls for a comment in the code as well to clarify that yes, we really do want 4 before 3 and that there's no 2. Matt > + > #define _DKL_PHY1_BASE 0x168000 > #define _DKL_PHY2_BASE 0x169000 > #define _DKL_PHY3_BASE 0x16A000 > -- > 2.27.0 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/22] drm/i915/adl_s: Initialize display for ADL-S
On Fri, Dec 04, 2020 at 05:08:32PM -0800, Aditya Swarup wrote:
> Initialize display outputs for ADL-S. ADL-S has 5 display
> outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs.
>
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Signed-off-by: Aditya Swarup
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 0ff0eeabab8c..19ed51e6c647 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17627,7 +17627,13 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
> + if (IS_ALDERLAKE_S(dev_priv)) {
> + intel_ddi_init(dev_priv, PORT_A);
> + intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
It all comes out the same in the end, but we should just pass PORT_TC1
and such for these outputs since that's the formal name in the bspec
(and matches how we handle RKL/DG1 that also have "TC" DDIs that are
actually combo PHYs).
Matt
> + intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
> + intel_ddi_init(dev_priv, PORT_F); /* DDI TC3 */
> + intel_ddi_init(dev_priv, PORT_G); /* DDI TC4 */
> + } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> intel_ddi_init(dev_priv, PORT_TC1);
> --
> 2.27.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 12/22] drm/i915/adl_s: Add vbt port and aux channel settings for adls
On Fri, Dec 04, 2020 at 05:08:34PM -0800, Aditya Swarup wrote:
> - ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D
> and E.
> - Add ADLS specific port mappings for vbt port dvo settings.
> - Select appropriate AUX CH specific to ADLS based on port mapping.
The aux stuff is getting really messy; we're definitely going to have to
move to a table-based approach for some of this stuff soon to keep it
from getting too out of hand.
The changes here look correct for the current style though.
Reviewed-by: Matt Roper
>
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Signed-off-by: Aditya Swarup
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 57 ++-
> 1 file changed, 46 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 9dc67c03ffc0..8f166f49b6cc 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1709,8 +1709,26 @@ static enum port dvo_port_to_port(struct
> drm_i915_private *dev_priv,
> [PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
> [PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
> };
> + /*
> + * Alderlake S ports used in the driver are PORT_A, PORT_D, PORT_E,
> + * PORT_F and PORT_G, we need to map that to correct VBT sections.
> + */
> + static const int adls_port_mapping[][3] = {
> + [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
> + [PORT_B] = { -1 },
> + [PORT_C] = { -1 },
> + [PORT_TC1] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
> + [PORT_TC2] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
> + [PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
> + [PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
> + };
>
> - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> + if (IS_ALDERLAKE_S(dev_priv))
> + return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping),
> + ARRAY_SIZE(adls_port_mapping[0]),
> + adls_port_mapping,
> + dvo_port);
> + else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
> ARRAY_SIZE(rkl_port_mapping[0]),
> rkl_port_mapping,
> @@ -2667,27 +2685,44 @@ enum aux_ch intel_bios_port_aux_ch(struct
> drm_i915_private *dev_priv,
> return aux_ch;
> }
>
> + /*
> + * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
> + * map to DDI A,B,TC1,TC2 respectively.
> + *
> + * ADL-S VBT uses PHY based mapping. Combo PHYs A,B,C,D,E
> + * map to DDI A,TC1,TC2,TC3,TC4 respectively.
> + */
> switch (info->alternate_aux_channel) {
> case DP_AUX_A:
> aux_ch = AUX_CH_A;
> break;
> case DP_AUX_B:
> - aux_ch = AUX_CH_B;
> + if (IS_ALDERLAKE_S(dev_priv))
> + aux_ch = AUX_CH_USBC1;
> + else
> + aux_ch = AUX_CH_B;
> break;
> case DP_AUX_C:
> - /*
> - * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
> - * map to DDI A,B,TC1,TC2 respectively.
> - */
> - aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
> - AUX_CH_USBC1 : AUX_CH_C;
> + if (IS_ALDERLAKE_S(dev_priv))
> + aux_ch = AUX_CH_USBC2;
> + else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> + aux_ch = AUX_CH_USBC1;
> + else
> + aux_ch = AUX_CH_C;
> break;
> case DP_AUX_D:
> - aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
> - AUX_CH_USBC2 : AUX_CH_D;
> + if (IS_ALDERLAKE_S(dev_priv))
> + aux_ch = AUX_CH_USBC3;
> + else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> + aux_ch = AUX_CH_USBC2;
> + else
> + aux_ch = AUX_CH_D;
> break;
> case DP_AUX_E:
> - aux_ch = AUX_CH_E;
> + if (IS_ALDERLAKE_S(dev_priv))
> + aux_ch = AUX_CH_USBC4;
> + else
> + aux_ch = AUX_CH_E;
> break;
> case DP_AUX_F:
> aux_ch = AUX_CH_F;
> --
> 2.27.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
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Re: [Intel-gfx] [PATCH 11/22] drm/i915/adl_s: Add adl-s ddc pin mapping
On Fri, Dec 04, 2020 at 05:08:33PM -0800, Aditya Swarup wrote:
> ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E.
> Combo PHY A still uses the old ddc pin mapping.
>
> From VBT, ddc pin info suggests the following mapping:
> VBT DRIVER
> DDI B->ddc_pin=2 should translate to PORT_D->0x9
> DDI C->ddc_pin=3 should translate to PORT_E->0xa
> DDI D->ddc_pin=4 should translate to PORT_F->0xb
> DDI E->ddc_pin=5 should translate to PORT_G->0xc
>
> Adding pin map to facilitate this translation as we cannot use existing
> icl ddc pin map due to conflict with DDI B and DDI C info.
>
> Bspec:20124
>
> v2: Replace IS_ALDERLAKE_S() with HAS_PCH_ADP() as the pin map pairing
> depends on the PCH being used rather than the platform.(mdroper)
>
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Signed-off-by: Aditya Swarup
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 13 +++-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++-
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4
> 3 files changed, 35 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 4cc949b228f2..9dc67c03ffc0 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1623,12 +1623,23 @@ static const u8 icp_ddc_pin_map[] = {
> [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
> };
>
> +static const u8 adls_ddc_pin_map[] = {
> + [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
> + [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP,
> + [ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP,
> + [ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP,
> + [ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP,
> +};
Can't we use icp_ddc_pin_map[] since it's a superset of this? The ICP
table has some extra entries that we'll never map through, but that's
true for other platforms as well. E.g., ICP itself can never have a
DDI_C or TC5/TC6, but it doesn't hurt anything to have those outputs as
extra entries in the table that never get looked up.
> +
> static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
> {
> const u8 *ddc_pin_map;
> int n_entries;
>
> - if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
> + if (HAS_PCH_ADP(dev_priv)) {
> + ddc_pin_map = adls_ddc_pin_map;
> + n_entries = ARRAY_SIZE(adls_ddc_pin_map);
> + } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
> return vbt_pin;
> } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
> ddc_pin_map = icp_ddc_pin_map;
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index e10fdb369daa..060a13b63aa9 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3135,6 +3135,22 @@ static u8 dg1_port_to_ddc_pin(struct drm_i915_private
> *dev_priv, enum port port)
> return intel_port_to_phy(dev_priv, port) + 1;
> }
>
> +static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
> port)
> +{
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> +
> + WARN_ON(port == PORT_B || port == PORT_C);
> +
> + /*
> + * Pin mapping for ADL-S requires TC pins for all combo phy outputs
> + * except first combo output.
> + */
> + if (IS_ALDERLAKE_S(dev_priv) && phy >= PHY_B)
The IS_ADLS test here is redundant since we only call this function on
ADL-S, right?
> + return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
> +
> + return GMBUS_PIN_1_BXT + phy;
There's only one possible output that can get to this return
(PORT_A/PHY_A), so the generic "+ phy" seems unnecessary.
Actually it might more more sensible to make PHY_A the special case we
test for in the 'if' condition and then make the PHY_B+ case the
function's regular return.
> +}
> +
> static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
> enum port port)
> {
> @@ -3172,7 +3188,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder
> *encoder)
> return ddc_pin;
> }
>
> - if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> + if (IS_ALDERLAKE_S(dev_priv))
This should probably be a PCH check instead of a platform check too.
Matt
> + ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
> + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
>
Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
On Tue, Jan 12, 2021 at 06:24:50PM +0200, Jani Nikula wrote: > On Mon, 11 Jan 2021, Lucas De Marchi wrote: > > On Mon, Jan 11, 2021 at 12:57:43PM -0800, Matt Roper wrote: > >>On Mon, Jan 11, 2021 at 10:18:45PM +0200, Jani Nikula wrote: > >>So to clarify, it looks like we have a bunch of revid changes to the > >>display code that got merged to the gt-next tree but not to the > >>intel-next tree? Should we be going back and also merging / > >>cherry-picking those over to intel-next since that's where the display > >>changes are supposed to go, or is it too late to do that cleanly at this > >>point? > > > > it was my mistake to merge them to drm-intel-gt-next. They should have > > been in drm-intel-next. > > That's not the problem though. The branches generally being too far > apart atm is. The single cherry-pick won't solve that. Applying these > patches to one tree just adds a dependency that will not be around in > the topic branch baseline, creating a new problem for merging the topic > branch. I still don't understand what the original goal of splitting the driver into two different trees was. It's clear that this approach is going to cause extra mistakes and bugs if we continue down this path and it's not clear to me what the expected benefit was to justify the additional complexity? When are the two branches supposed to be brought back in sync? Is it just a single backmerge to each branch immediately after new mainline kernel releases or is there some other strategy to handle this? Matt > > >>Going forward, what should the general strategy be for stuff like > >>platform definitions and such? Merge such enablement patches to both > > > > last time we talked about this was regarding dg1 AFAIR and the consensus > > was to create a topic branch and that topic branch to be merged in both > > branches. That would avoid having 2 commits in different branches. > > Agreed. > > > Not sure if it would work out nicely for getting test on CI though. > > Since the changes are spread through the codebase, we could very easily > > hit a situation that this topic branch creates conflicts for other > > patches getting merged on either drm-intel-next or drm-intel-gt-next. > > The cycle in review -> apply to topic branch -> merge topic branch just > needs to be short enough. We can't have the topic branch laying around > for more than maybe a few days, or we'll have problems. > > > BR, > Jani. > > -- > Jani Nikula, Intel Open Source Graphics Center -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 09/22] drm/i915/adl_s: Configure Port clock registers for ADL-S
On Fri, Dec 04, 2020 at 05:08:31PM -0800, Aditya Swarup wrote:
> Add changes to configure port clock registers for ADL-S. Combo phy port
> clocks are configured by DPCLKA_CFGCR0 and DPCLKA_CFGCR1 registers.
>
> The DDI to internal clock mappings in DPCLKA_CFGCR0 register for ADL-S
> translates to
> DDI A -> DDIA
> DDI B -> USBC1
> DDI I -> USBC2
>
> For DPCLKA_CFGCR1
> DDI J -> USBC3
> DDI K -> USBC4
>
> Bspec: 50287
> Bspec: 53812
> Bspec: 53723
>
> v2: Replace I915_READ() with intel_de_read().(Jani)
>
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Signed-off-by: Aditya Swarup
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 64 +---
> drivers/gpu/drm/i915/display/intel_display.c | 18 +-
> drivers/gpu/drm/i915/i915_reg.h | 23 ++-
> 3 files changed, 82 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 76e975b4765b..fdf692be2bc3 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3088,25 +3088,30 @@ static void icl_map_plls_to_ports(struct
> intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> - u32 val;
> + u32 val, mask, sel;
> + i915_reg_t reg;
> +
> + if (IS_ALDERLAKE_S(dev_priv)) {
> + reg = ADLS_DPCLKA_CFGCR(phy);
> + mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
> + sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
> + } else if (IS_ROCKETLAKE(dev_priv)) {
> + reg = ICL_DPCLKA_CFGCR0;
> + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> + } else {
> + reg = ICL_DPCLKA_CFGCR0;
> + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> + }
>
> mutex_lock(&dev_priv->dpll.lock);
>
> - val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> + val = intel_de_read(dev_priv, reg);
> drm_WARN_ON(&dev_priv->drm,
> (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
>
> if (intel_phy_is_combo(dev_priv, phy)) {
> - u32 mask, sel;
> -
> - if (IS_ROCKETLAKE(dev_priv)) {
> - mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> - sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> - } else {
> - mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> - sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> - }
> -
> /*
>* Even though this register references DDIs, note that we
>* want to pass the PHY rather than the port (DDI). For
> @@ -3119,12 +3124,12 @@ static void icl_map_plls_to_ports(struct
> intel_encoder *encoder,
>*/
> val &= ~mask;
> val |= sel;
> - intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
> - intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
> + intel_de_write(dev_priv, reg, val);
> + intel_de_posting_read(dev_priv, reg);
> }
>
> val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
> - intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
> + intel_de_write(dev_priv, reg, val);
>
> mutex_unlock(&dev_priv->dpll.lock);
> }
> @@ -3150,9 +3155,17 @@ static void icl_unmap_plls_to_ports(struct
> intel_encoder *encoder)
>
> mutex_lock(&dev_priv->dpll.lock);
>
> - val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> + if (IS_ALDERLAKE_S(dev_priv))
> + val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy));
> + else
> + val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> +
> val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
> - intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
> +
> + if (IS_ALDERLAKE_S(dev_priv))
> + intel_de_write(dev_priv, ADLS_DPCLKA_CFGCR(phy), val);
> + else
> + intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
We could potentially assign the register to a local at the top of the
function like we did in icl_map_plls_to_ports() to
Re: [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER
On Thu, May 27, 2021 at 11:16:54AM -0700, Lucas De Marchi wrote:
> This was done by the following semantic patch:
Is the commit message here out-of-date? The cocci doesn't appear to
match the diff anymore. IS_GRAPHICS_VER() is the range macro now and
IS_GEN is being replaced with a direct "==" comparison.
Matt
>
> @@ expression dev_priv, E; @@
> - INTEL_GEN(dev_priv) == E
> + IS_GRAPHICS_VER(dev_priv, E)
>
> @@ expression dev_priv; @@
> - INTEL_GEN(dev_priv)
> + GRAPHICS_VER(dev_priv)
>
> @@ expression dev_priv; expression E; @@
> - IS_GEN(dev_priv, E)
> + IS_GRAPHICS_VER(dev_priv, E)
>
> @@
> expression dev_priv;
> expression from, until;
> @@
> - IS_GEN_RANGE(dev_priv, from, until)
> + IS_GRAPHICS_RANGE(dev_priv, from, until)
>
> @def@
> expression E;
> identifier id =~ "^gen$";
> @@
> - id = GRAPHICS_VER(E)
> + ver = GRAPHICS_VER(E)
>
> @@
> identifier def.id;
> @@
> - id
> + ver
>
> It also takes care of renaming the variable we assign to GRAPHICS_VER()
> so to use "ver" rather than "gen".
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 38 +--
> drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 54 +++
> .../drm/i915/gt/intel_execlists_submission.c | 18 ++---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 18 ++---
> drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 34 +-
> drivers/gpu/drm/i915/gt/intel_gt.c| 27
> .../gpu/drm/i915/gt/intel_gt_clock_utils.c| 12 ++--
> drivers/gpu/drm/i915/gt/intel_gt_irq.c| 6 +-
> drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 10 +--
> drivers/gpu/drm/i915/gt/intel_gtt.c | 14 ++--
> drivers/gpu/drm/i915/gt/intel_llc.c | 6 +-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 46 ++---
> drivers/gpu/drm/i915/gt/intel_mocs.c | 8 +--
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 6 +-
> drivers/gpu/drm/i915/gt/intel_rc6.c | 16 ++---
> drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_reset.c | 12 ++--
> .../gpu/drm/i915/gt/intel_ring_submission.c | 64 +-
> drivers/gpu/drm/i915/gt/intel_rps.c | 60 -
> drivers/gpu/drm/i915/gt/intel_sseu.c | 14 ++--
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +--
> drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 6 +-
> drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_execlists.c | 4 +-
> drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 8 +--
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8 +--
> drivers/gpu/drm/i915/gt/selftest_llc.c| 4 +-
> drivers/gpu/drm/i915/gt/selftest_lrc.c| 8 +--
> drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_rc6.c| 4 +-
> .../drm/i915/gt/selftest_ring_submission.c| 6 +-
> drivers/gpu/drm/i915/gt/selftest_rps.c| 16 ++---
> drivers/gpu/drm/i915/gt/selftest_timeline.c | 6 +-
> .../gpu/drm/i915/gt/selftest_workarounds.c| 8 +--
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 4 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +--
> drivers/gpu/drm/i915/gt/uc/intel_huc.c| 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
> 44 files changed, 323 insertions(+), 322 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> index d4f4452ce5ed..0389bceebd06 100644
> --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> @@ -85,14 +85,14 @@ static int gen6_drpc(struct seq_file *m)
> gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
>
> rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
> - if (INTEL_GEN(i915) >= 9) {
> + if (GRAPHICS_VER(i915) >= 9) {
> gen9_powergate_enable =
> intel_uncore_read(uncore, GEN9_PG_ENABLE);
> gen9_powergate_status =
> intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS);
> }
>
> - if (INTEL_GEN(i915) <= 7)
> + if (GRAPHICS_VER(i915) <= 7)
> sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
> &rc6vids, NULL);
>
> @@ -100,7 +100,7 @@ static int gen6_drpc(struct seq_file *m)
> yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
>
Re: [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL
eset on all pipes
> @@ -2475,7 +2528,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
> *state)
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> const struct intel_cdclk_state *old_cdclk_state;
> struct intel_cdclk_state *new_cdclk_state;
> - enum pipe pipe;
> + enum pipe pipe = INVALID_PIPE;
> int ret;
>
> new_cdclk_state = intel_atomic_get_cdclk_state(state);
> @@ -2527,15 +2580,18 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
>
> if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> pipe = INVALID_PIPE;
> - } else {
> - pipe = INVALID_PIPE;
> }
>
> - if (pipe != INVALID_PIPE) {
> + if (intel_cdclk_can_crawl(dev_priv,
> + &old_cdclk_state->actual,
> + &new_cdclk_state->actual)) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Can change cdclk via crawl\n");
> + } else if (pipe != INVALID_PIPE) {
> new_cdclk_state->pipe = pipe;
>
> drm_dbg_kms(&dev_priv->drm,
> - "Can change cdclk with pipe %c active\n",
> + "Can change cdclk cd2x divider with pipe %c
> active\n",
> pipe_name(pipe));
> } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
>&new_cdclk_state->actual)) {
> @@ -2544,8 +2600,6 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
> *state)
> if (ret)
> return ret;
>
> - new_cdclk_state->pipe = INVALID_PIPE;
> -
> drm_dbg_kms(&dev_priv->drm,
> "Modeset required for cdclk change\n");
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3b58067a873c..1d1176d1799d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11157,6 +11157,8 @@ enum skl_power_gate {
> #define BXT_DE_PLL_ENABLE_MMIO(0x46070)
> #define BXT_DE_PLL_PLL_ENABLE (1 << 31)
> #define BXT_DE_PLL_LOCK(1 << 30)
> +#define BXT_DE_PLL_FREQ_REQ(1 << 23)
> +#define BXT_DE_PLL_FREQ_REQ_ACK(1 << 22)
> #define CNL_CDCLK_PLL_RATIO(x) (x)
> #define CNL_CDCLK_PLL_RATIO_MASK 0xff
>
> --
> 2.24.1.485.gad05a3d8e5
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
___
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Re: [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER
On Tue, Jun 01, 2021 at 11:34:39PM -0700, Lucas De Marchi wrote: > On Tue, Jun 01, 2021 at 01:39:25PM -0700, Matt Roper wrote: > > On Tue, Jun 01, 2021 at 12:13:17PM -0700, Lucas De Marchi wrote: > > > On Tue, Jun 01, 2021 at 10:30:55AM -0700, Matt Roper wrote: > > > > On Tue, Jun 01, 2021 at 10:15:14AM -0700, Lucas De Marchi wrote: > > > > > On Tue, Jun 01, 2021 at 09:58:34AM -0700, Matt Roper wrote: > > > > > > On Thu, May 27, 2021 at 11:16:54AM -0700, Lucas De Marchi wrote: > > > > > > > This was done by the following semantic patch: > > > > > > > > > > > > Is the commit message here out-of-date? The cocci doesn't appear to > > > > > > match the diff anymore. IS_GRAPHICS_VER() is the range macro now > > > > > > and > > > > > > IS_GEN is being replaced with a direct "==" comparison. > > > > > > > > > > not necessarily, it's included in "and friends...". Maybe rewording to > > > > > something like "replace gen-based macros with new ver-based ones" > > > > > would > > > > > make it clearer? > > > > > > > > I mean that running the coccinelle rules below through spatch won't > > > > generate the code diff here; it would generate a completely different > > > > patch (that I don't think would build properly either). > > > > > > oh, ok. I fixed the issues in the .cocci and forgot to update the commit > > > message. Thanks. > > > > > > Lucas De Marchi > > > > Aside from the commit messages needing updated Coccinelle rules, the > > code deltas look correct to me. > > > > Reviewed-by: Matt Roper > > humn... is that to the series or only this commit? Sorry, that was meant for the whole series. Matt > > Lucas De Marchi -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/adl_p: Extend Wa_1606931601 for ADL-P
On Fri, Jun 04, 2021 at 03:14:25PM -0700, Nataraj Deshpande wrote:
> Helps to fixe skia test failures on adl_p platform.
>
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Signed-off-by: Nataraj Deshpande
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 62cb9ee5bfc3..38efc1e0ccfa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1633,9 +1633,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> GEN7_DISABLE_SAMPLER_PREFETCH);
> }
>
> - if (IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> + if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> - /* Wa_1606931601:tgl,rkl,dg1,adl-s */
> + /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
> wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
>
> /*
> --
> 2.29.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH] drm/i915/adl_p: Add initial ADL_P Workarounds
On Mon, Jun 07, 2021 at 05:20:56PM -0700, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> Most of the context WA are already implemented.
> Adding adl_p platform tag to reflect so.
>
> BSpec: 54369
> Cc: Matt Roper
> Cc: Aditya Swarup
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Madhumitha Tolakanahalli Pradeep
>
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Swathi Dhanavanthri
> Signed-off-by: Clint Taylor
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 39 ++-
> drivers/gpu/drm/i915/intel_pm.c | 8 ++--
> 4 files changed, 28 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 71ac57670043..79746d5c1378 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2675,7 +2675,7 @@ ehl_combo_pll_div_frac_wa_needed(struct
> drm_i915_private *i915)
> {
> return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
>IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) ||
> - IS_TIGERLAKE(i915)) &&
> + IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
There's a comment above this function that lists the platforms; we
should add adl-p to that list so it doesn't become stale.
I notice that we're also missing this workaround on ADL-S; we should
probably follow up with a separate patch to add that too.
>i915->dpll.ref_clks.nssc == 38400;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 94e0a5669f90..87b06572fd2e 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -208,7 +208,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32
> mode)
> flags |= PIPE_CONTROL_FLUSH_L3;
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> - /* Wa_1409600907:tgl */
> + /* Wa_1409600907:tgl,adl-p */
> flags |= PIPE_CONTROL_DEPTH_STALL;
> flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index b62d1e31a645..e62cadb3fcd8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -640,15 +640,16 @@ static void gen12_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> gen12_ctx_gt_tuning_init(engine, wal);
>
> /*
> - * Wa_1409142259:tgl
> - * Wa_1409347922:tgl
> - * Wa_1409252684:tgl
> - * Wa_1409217633:tgl
> - * Wa_1409207793:tgl
> - * Wa_1409178076:tgl
> - * Wa_1408979724:tgl
> - * Wa_14010443199:rkl
> - * Wa_14010698770:rkl
> + * Wa_1409142259:tgl,adl-p
> + * Wa_1409347922:tgl,adl-p
> + * Wa_1409252684:tgl,adl-p
> + * Wa_1409217633:tgl,adl-p
> + * Wa_1409207793:tgl,adl-p
> + * Wa_1409178076:tgl,adl-p
> + * Wa_1408979724:tgl,adl-p
Since we're updating the comments anyway, it looks like all of the ones
listed above should actually be "tgl,dg1,adl-p" for completeness and
grep-ability.
> + * Wa_14010443199:rkl,adl-p
This one is tgl,rkl,dg1,adl-p
> + * Wa_14010698770:rkl,adl-p
> + * Wa_1409342910:adl-p
These two are tgl,rkl,dg1,adl-s,adl-p
Aside from the comment tweaks, all of the workarounds look correct to
me.
Reviewed-by: Matt Roper
>*/
> wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
>GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> @@ -1113,7 +1114,7 @@ gen12_gt_workarounds_init(struct drm_i915_private *i915,
> {
> wa_init_mcr(i915, wal);
>
> - /* Wa_14011060649:tgl,rkl,dg1,adls */
> + /* Wa_14011060649:tgl,rkl,dg1,adls,adl-p */
> wa_14011060649(i915, wal);
> }
>
> @@ -1633,38 +1634,40 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> GEN7_DISABLE_SAMPLER_PREFETCH);
> }
>
> - if (IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> + if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> - /* Wa_1606931601:tgl,rkl,dg1,
Re: [Intel-gfx] [PATCH] Revert "drm/i915: Apply Wa_1406680159:icl, ehl as an engine workaround"
On Thu, Jun 10, 2021 at 03:16:58PM +0530, Tejas Upadhyay wrote:
> This reverts commit fb899dd8ea9c4ac5928b86946e6536790981adae.
>
> w/a on mentioned platforms not working as expected and causing
> more harm on the RC6 flow.
>
> Fixes: fb899dd8ea9c ("drm/i915: Apply Wa_1406680159:icl,ehl as an engine
> workaround")
> Cc: Mika Kuoppala
> Cc: Matt Roper
> Signed-off-by: Tejas Upadhyay
NAK. This patch does not do what it claims (it deletes the workaround
completely rather than reverting the original patch) and also doesn't
address the real issue here.
As we've discussed before, this workaround is working properly. We've
already confirmed that the register write does go through, the bit is
set in hardware, and the relevant clock gating is disabled at the
hardware level. The *only* thing that isn't working is the readback
verification of the register bit, and this is a multicast steering issue
rather than anything to do with this specific workaround (due to "luck"
this just happens to be the only documented workaround that updates a
register in the affected multicast region on this platform, but you'd
see the same type of warnings if other workarounds in the future start
touching the same general multicast region).
When we write to a multicast register like this, all instances of the
register that live behind the same MMIO address get updated. But when
we read back those multicast registers, the value we get back always
comes from one specific instance. For workarounds, all of the instances
will have the same value, so it doesn't matter which instance we read
back, as long as we don't read back from an instance that is fused off
(if we do, we'll read back a 0). During driver init, we pick a register
steering configuration that will make sure reads of multicase registers
hit a non-fused-off instance and return a proper value.
However on some platforms (including EHL/JSL), there's one more thing to
consider. On these platforms, Render Power Gating (RPG) will modify the
behavior when the hardware exits RC6 --- instead of all registers being
powered back up and accessible when forcewake is grabbed, only a single
slice/subslice will be powered up initially if there's no workload to be
run (the hardware architects refer to this as the "minconfig"). This
means that when reading from multicast registers while RPG is enabled,
we need to not only steer toward a slice/subslice that isn't fused off,
but we also need to steer toward the specific slice/subslice that is
used as the minconfig (which I believe is always the lowest numbered
one).
At the point we apply and verify workarounds, RPG is not supposed to be
active (i.e., we're not at the point of GT setup where we (re)enable it
yet). However there seems to be some hardware misbehavior where in
certain circumstances a previous write to the A210 control register to
disable Render Power Gating did not take effect --- the A210 register
value indicates that RPG should be off, but the hardware continues to
operate as if it is on, and only minconfig instances of MCR registers
get powered up to return valid values. We encounter this problem during
certain reset or suspend/resume operations, and that's what causes the
workaround warning message here. We're steering our read to a valid
(non-fused-off) instance of the multicast register, but since it isn't
the specific minconfig slice/subslice we still fail to read back the
proper value.
If we just want to fix the workaround warning message here, it should be
a simple matter of making sure our default steering always targets the
minconfig slice/subslice. I believe switching wa_init_mcr() from using
fls() to ffs() would be sufficient --- we'd always pick the lowest
possible slice/subslice in that case (i.e., the minconfig) instead of
the highest.
The real question to be answered is why the hardware continues to behave
as if RPG is on, even after its been disabled via the POWERGATE_ENABLE
register. This may be a hardware bug, or (more likely), there's some
step that wasn't properly documented in the bspec so our driver isn't
following it (the GT power management documentation in the bspec
definitely isn't as clear and complete as we'd like it to be).
Matt
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index b62d1e31a645..fea7fde30d4a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1774,11 +1774,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> PS
Re: [Intel-gfx] [PATCH] drm/i915: Fix parenthesis and dbuf condition
On Thu, Jun 10, 2021 at 10:02:13AM +0300, Stanislav Lisovskiy wrote: > Removed excessive parenthesis and placed && on > previous line in DBUF state checker. > > Signed-off-by: Stanislav Lisovskiy Reviewed-by: Matt Roper Minor nit: you probably want "parentheses" in the subject and commit message as the plural form of the word "parenthesis." > --- > drivers/gpu/drm/i915/intel_pm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 97d9cde64e26..ded0fb8ed817 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -8324,8 +8324,8 @@ void intel_dbuf_post_plane_update(struct > intel_atomic_state *state) > intel_atomic_get_old_dbuf_state(state); > > if (!new_dbuf_state || > - ((new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices) > - && (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))) > + (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices && > + new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus)) > return; > > WARN_ON(!new_dbuf_state->base.changed); > -- > 2.24.1.485.gad05a3d8e5 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Steer MCR reads to lowest potential slice/subslice
When determining the slice/subslice to use for steering multicast
register reads we need to not only consider the fusing (to avoid
steering to a fused off instance), but also the "minconfig" that the
hardware uses to wake from RC6 when render power gating is enabled on
some platforms. Although it isn't well-documented, certain platforms
(e.g., EHL/JSL) will initially only power up a single instance of
multicast registers when forcewake is grabbed if the GPU isn't actually
busy. In these cases, only the minconfig slice/subslice will return
valid, non-zero reads so we need to ensure that we steer to the
minconfig specifically. The minconfig should always be the lowest
slice/subslice that isn't fused off; as such, we should pick our
steering target with ffs() instead of fls() during initialization.
This steering change is especially important on EHL/JSL since there are
cases where the hardware appears to not honor the driver's attempts to
disable render powergating via the POWERGATE_ENABLE (0xA210) register
and will continue to only wake the minconfig's slice/subslice in
response to forcewake. We can see this in certain reset or
suspend/resume cases where i915 tries to disable render powergating and
then re-applies workarounds before re-enabling powergating; the
workarounds apply successfully, but the readback verification will fail
if we aren't steering to the minconfig register instance.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/1222
Cc: Tejas Upadhyay
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b62d1e31a645..0c973678bf03 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -991,13 +991,13 @@ wa_init_mcr(struct drm_i915_private *i915, struct
i915_wa_list *wal)
l3_en = ~0;
}
- slice = fls(sseu->slice_mask) - 1;
- subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
+ slice = ffs(sseu->slice_mask) - 1;
+ subslice = ffs(l3_en & intel_sseu_get_subslices(sseu, slice));
if (!subslice) {
drm_warn(&i915->drm,
"No common index found between subslice mask %x and L3
bank mask %x!\n",
intel_sseu_get_subslices(sseu, slice), l3_en);
- subslice = fls(l3_en);
+ subslice = ffs(l3_en);
drm_WARN_ON(&i915->drm, !subslice);
}
subslice--;
--
2.25.4
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Steer MCR reads to lowest potential slice/subslice
fx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html >[119]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20340/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html > > * igt@kms_psr@psr2_suspend: > - shard-iclb: [SKIP][120] ([fdo#109441]) -> [PASS][121] +1 > similar issue >[120]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-iclb8/igt@kms_psr@psr2_suspend.html >[121]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20340/shard-iclb2/igt@kms_psr@psr2_suspend.html > > * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend: > - shard-tglb: [INCOMPLETE][122] ([i915#456]) -> [PASS][123] >[122]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-tglb1/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html >[123]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20340/shard-tglb3/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html > > * igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend: > - shard-tglb: [DMESG-WARN][124] ([i915#2411] / [i915#2868]) -> > [PASS][125] >[124]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-tglb5/igt@kms_vbl...@pipe-d-ts-continuation-dpms-suspend.html >[125]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20340/shard-tglb8/igt@kms_vbl...@pipe-d-ts-continuation-dpms-suspend.html > > * igt@perf@polling-parameterized: > - shard-iclb: [FAIL][126] ([i915#1542]) -> [PASS][127] >[126]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-iclb1/igt@p...@polling-parameterized.html >[127]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20340/shard-iclb6/igt@p...@polling-parameterized.html > > > Warnings > > * igt@gem_exec_fair@basic-throttle@rcs0: > - shard-iclb: [FAIL][128] ([i915#2842]) -> [FAIL][129] > ([i915#2849]) >[128]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html >[129]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20340/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html > > * igt@i915_pm_rc6_residency@rc6-fence: > - shard-iclb: [WARN][130] ([i915#1804] / [i915#2684]) -> > [WARN][131] ([i915#2684]) +1 similar issue >[130]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-iclb4/igt@i915_pm_rc6_reside...@rc6-fence.html >[131]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20340/shard-iclb8/igt@i915_pm_rc6_reside...@rc6-fence.html > > * igt@i915_selftest@live@execlists: > - shard-skl: [INCOMPLETE][132] -> [INCOMPLETE][133] ([i915#2782] > / [i915#3462]) >[132]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-skl7/igt@i915_selftest@l...@execlists.html >[133]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20340/shard-skl4/igt@i915_selftest@l...@execlists.html > - shard-iclb: [INCOMPLETE][134] ([i915#2782] / [i915#3462]) -> > [DMESG-FAIL][135] ([i915#3462]) >[134]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-iclb1/igt@i915_selftest@l...@execlists.html >[135]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20340/shard-iclb5/igt@i915_selftest@l...@execlists.html > > * igt@kms_psr2_sf@cursor-plane-update-sf: > - shard-iclb: [SKIP][136] ([i915#2920]) -> [SKIP][137] > ([i915#658]) >[136]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-iclb2/igt@kms_psr2...@cursor-plane-update-sf.html >[137]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20340/shard-iclb5/igt@kms_psr2...@cursor-plane-update-sf.html > > * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1: > - shard-iclb: [SKIP][138] ([i915#658]) -> [SKIP][139] > ([i915#2920]) +2 similar issues >[138]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-iclb3/igt@kms_psr2...@primary-plane-update-sf-dmg-area-1.html >[139]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20340/shard-iclb2/igt@kms_psr2...@primary-plane-update-sf-dmg-area-1.html > > * igt@runner@aborted: > - shard-kbl: ([FAIL][140], [FAIL][141], [FAIL][142], > [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], > [FAIL][149]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2505] / > [i915#3002] / [i915#3363] / [i915#92]) -> ([FAIL][150], [FAIL][151], > [FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155]) ([i915#1436] / [i915#180] > / [i915#1814] / [i915#3002] / [i915#3363] / [i915#92]) >[140]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-kbl3/igt@run...@aborted.html >[141]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-kbl1/igt@run...@aborted.html >[142]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-kbl1/igt@run...@aborted.html >[143]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-kbl6/igt@run...@aborted.html >[144]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-kbl7/igt@run...@aborted.html >[145]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10206/shard-kbl6/igt@run...@aborted.html >[ > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20340/index.html -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/xelpd: break feature inheritance
On Fri, Jun 11, 2021 at 10:35:31PM -0700, Lucas De Marchi wrote:
> It's becoming pretty cumbersome to track the features enabled going back
> to GEN7. Gather the XE_LPD display features together in XE_LPD_FEATURES
> macro so they are sufficient to describe the display features.
>
> In ADL-P's device_info we set has_psr_hw_tracking to 0 as it would
> otherwise be enabled since it is inheriting from GEN12_FEATURES.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_pci.c | 50 +++--
> 1 file changed, 42 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 83b500bb170c..5e8348f506b8 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -939,15 +939,48 @@ static const struct intel_device_info adl_s_info = {
> .dma_mask_size = 46,
> };
>
> +#define XE_LPD_CURSOR_OFFSETS \
> + .cursor_offsets = { \
> + [PIPE_A] = CURSOR_A_OFFSET, \
> + [PIPE_B] = IVB_CURSOR_B_OFFSET, \
> + [PIPE_C] = IVB_CURSOR_C_OFFSET, \
> + [PIPE_D] = TGL_CURSOR_D_OFFSET, \
> + }
> +
> #define XE_LPD_FEATURES \
> - .display.ver = 13, \
> - .display.has_psr_hw_tracking = 0, \
> - .abox_mask = GENMASK(1, 0), \
> - .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> - .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> - BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
> - .dbuf.size = 4096, \
> - .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |
> BIT(DBUF_S4)
> + .abox_mask = GENMASK(1, 0),
> \
> + .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 },
> \
> + .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> \
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> \
> + .dbuf.size = 4096,
> \
> + .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |
> \
> + BIT(DBUF_S4),
> \
> + .display.has_ddi = 1,
> \
> + .display.has_dmc = 1,
> \
> + .display.has_dp_mst = 1,
> \
> + .display.has_dsb = 1,
> \
> + .display.has_dsc = 1,
> \
> + .display.has_fbc = 1,
> \
> + .display.has_fpga_dbg = 1,
> \
> + .display.has_hdcp = 1,
> \
> + .display.has_hotplug = 1,
> \
> + .display.has_ipc = 1,
> \
> + .display.has_psr = 1,
> \
> + .display.ver = 13,
> \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> \
> + .pipe_offsets = {
> \
> + [TRANSCODER_A] = PIPE_A_OFFSET,
> \
> + [TRANSCODER_B] = PIPE_B_OFFSET,
> \
> + [TRANSCODER_C] = PIPE_C_OFFSET,
> \
> + [TRANSCODER_D] = PIPE_D_OFFSET,
> \
> + },
> \
> + .trans_offsets = {
> \
> + [TRANSCODER_A] = TRANSCODER_A_OFFSET,
> \
> + [TRANSCODER_B] = TRANSCODER_B_OFFSET,
> \
> + [TRANSCODER_C] = TRANSCODER_C_OFFSET,
> \
> + [TRANSCODER_D] = TRANSCODER_D_OFFSET,
> \
> + },
> \
> + XE_LPD_CURSOR_OFFSETS
>
> static const struct intel_device_info adl_p_info = {
>
Re: [Intel-gfx] [PATCH] drm/i915/gen11: use ffs for minconfig slice/subslice
On Sat, Jun 12, 2021 at 09:55:02AM +, Surendrakumar Upadhyay, TejaskumarX
wrote:
>
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: 11 June 2021 23:36
> > To: Surendrakumar Upadhyay, TejaskumarX
> >
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/gen11: use ffs for minconfig
> > slice/subslice
> >
> > On Fri, Jun 11, 2021 at 08:04:09PM +0530, Tejas Upadhyay wrote:
> > > w/a on gen11 platforms not working as expected and causing more harm
> > > on the RC6 flow. Because of subslice steering disturbance w/a read is
> > > failing. By using ffs we can default steering of slice/sublice to
> > > minconfig hence w/a will pass and any warns will go away.
> > >
> > > Fixes: fb899dd8ea9c ("drm/i915: Apply Wa_1406680159:icl,ehl as an
> > > engine workaround")
> > > Cc: Mika Kuoppala
> > > Cc: Matt Roper
> > > Signed-off-by: Tejas Upadhyay
> > >
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 +++---
> > > drivers/gpu/drm/i915/intel_pm.c | 10 +++---
> > > 2 files changed, 18 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index b62d1e31a645..68b14141088a 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -991,13 +991,21 @@ wa_init_mcr(struct drm_i915_private *i915,
> > struct i915_wa_list *wal)
> > > l3_en = ~0;
> > > }
> > >
> > > - slice = fls(sseu->slice_mask) - 1;
> > > - subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
> > > + if (GRAPHICS_VER(i915) == 11) {
> > > + slice = ffs(sseu->slice_mask) - 1;
> > > + subslice = ffs(l3_en & intel_sseu_get_subslices(sseu, slice));
> > > + } else {
> > > + slice = fls(sseu->slice_mask) - 1;
> > > + subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
> > > + }
> > > if (!subslice) {
> > > drm_warn(&i915->drm,
> > >"No common index found between subslice mask %x
> > and L3 bank mask %x!\n",
> > >intel_sseu_get_subslices(sseu, slice), l3_en);
> > > - subslice = fls(l3_en);
> > > + if (GRAPHICS_VER(i915) == 11)
> > > + subslice = ffs(l3_en);
> > > + else
> > > + subslice = fls(l3_en);
> > > drm_WARN_ON(&i915->drm, !subslice);
> > > }
> > > subslice--;
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c index 45fefa0ed160..d1352ec3546a
> > > 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4049,9 +4049,13 @@ skl_ddb_entry_for_slices(struct
> > drm_i915_private *dev_priv, u8 slice_mask,
> > > ddb->end = 0;
> > > return;
> > > }
> > > -
> > > - ddb->start = (ffs(slice_mask) - 1) * slice_size;
> > > - ddb->end = fls(slice_mask) * slice_size;
> > > + if (GRAPHICS_VER(dev_priv) == 11) {
> > > + ddb->start = (fls(slice_mask) - 1) * slice_size;
> > > + ddb->end = ffs(slice_mask) * slice_size;
> > > + } else {
> > > + ddb->start = (ffs(slice_mask) - 1) * slice_size;
> > > + ddb->end = fls(slice_mask) * slice_size;
> > > + }
> >
> > This code has nothing to do with GT slices.
>
> Without this change we are observing "gem_exec_suspend (basic-s0)
> Starting subtest: basic-S0" test hangs and crash eventually. Thus
> change identified and added. Would you please help reviewing?
>
> Also I am seeing ICL igt@kms_frontbuffer_tracking@fbc-suspend is
> seeing workaround(0x9524) lost warning after this patch while EHL and
> JSL are working fine. does someone has insight why that should be
> the case?
See the patch I sent last week:
https://patchwork.freedesktop.org/series/91367/
and my response to the CI results here that explains the ICL behavior:
https://lists.freedesktop.org/archives/intel-gfx/2021-June/269097.html
Basically the fact that we're trying to combine subslice steering and
l3bank steering into a single value prevents us from using the
minconfig, e
[Intel-gfx] [PATCH 0/3] Explicity steer l3bank multicast reads when necessary
We've recently learned that when steering reads of multicast registers that use 'subslice' replication, it's not only important to steer to a subslice that isn't fused off, but also to steer to the lowest-numbered subslice. This is because when Render Power Gating is enabled, grabbing forcewake will only cause the hardware to power up a single subslice (referred to as the "minconfig") until/unless a real workload is being run on the EUs. If we try to read back a value from a register instance other than the minconfig subslice, the read operation will either return 0 or random garbage. Unfortunately this extra requirement to steer to the minconfig means that the steering target we use for subslice-replicated registers may not select a valid instance for l3bank-replicated registers. In cases where the two types of multicast registers do not have compatible steering targets, we'll initialize the steering control register to the proper subslice target at driver load, and then explicitly re-steer individual reads of l3bank registers as they occur at runtime. This series sets up an infrastructure to handle explicit resteering of multiple multicast register types, and then applies it to l3bank registers. Our next upcoming platform (which we'll probably start upstreaming soon) will bring several more types of multicast registers, each with their own steering criteria, so the infrastructure here is partially in preparation for those extra multicast types that will be arriving soon. Cc: Daniele Ceraolo Spurio Cc: Tvrtko Ursulin Cc: Tejas Upadhyay Daniele Ceraolo Spurio (1): drm/i915: extract steered reg access to common function Matt Roper (2): drm/i915: Add GT support for multiple types of multicast steering drm/i915: Add support for explicit L3BANK steering drivers/gpu/drm/i915/gt/intel_engine_cs.c | 41 +-- drivers/gpu/drm/i915/gt/intel_gt.c| 102 drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++ drivers/gpu/drm/i915/gt/intel_gt_types.h | 26 drivers/gpu/drm/i915/gt/intel_workarounds.c | 112 +++--- .../gpu/drm/i915/gt/selftest_workarounds.c| 2 +- drivers/gpu/drm/i915/intel_uncore.c | 55 + drivers/gpu/drm/i915/intel_uncore.h | 6 + 8 files changed, 240 insertions(+), 112 deletions(-) -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915: extract steered reg access to common function
From: Daniele Ceraolo Spurio
New steering cases will be added in the follow-up patches, so prepare a
common helper to avoid code duplication.
Cc: Tvrtko Ursulin
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 41 +
drivers/gpu/drm/i915/intel_uncore.c | 55 +++
drivers/gpu/drm/i915/intel_uncore.h | 6 +++
3 files changed, 63 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 9ceddfbb1687..8b913c6961c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1105,45 +1105,8 @@ static u32
read_subslice_reg(const struct intel_engine_cs *engine,
int slice, int subslice, i915_reg_t reg)
{
- struct drm_i915_private *i915 = engine->i915;
- struct intel_uncore *uncore = engine->uncore;
- u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
- enum forcewake_domains fw_domains;
-
- if (GRAPHICS_VER(i915) >= 11) {
- mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
- mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
- } else {
- mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
- mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
- }
-
- fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
- FW_REG_READ);
- fw_domains |= intel_uncore_forcewake_for_reg(uncore,
-GEN8_MCR_SELECTOR,
-FW_REG_READ |
FW_REG_WRITE);
-
- spin_lock_irq(&uncore->lock);
- intel_uncore_forcewake_get__locked(uncore, fw_domains);
-
- old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
-
- mcr &= ~mcr_mask;
- mcr |= mcr_ss;
- intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
-
- val = intel_uncore_read_fw(uncore, reg);
-
- mcr &= ~mcr_mask;
- mcr |= old_mcr & mcr_mask;
-
- intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
-
- intel_uncore_forcewake_put__locked(uncore, fw_domains);
- spin_unlock_irq(&uncore->lock);
-
- return val;
+ return intel_uncore_read_with_mcr_steering(engine->uncore, reg,
+ slice, subslice);
}
/* NB: please notice the memset */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 1bed8f666048..d067524f9162 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2277,6 +2277,61 @@ intel_uncore_forcewake_for_reg(struct intel_uncore
*uncore,
return fw_domains;
}
+u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore,
+ i915_reg_t reg,
+ int slice, int subslice)
+{
+ u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
+
+ lockdep_assert_held(&uncore->lock);
+
+ if (GRAPHICS_VER(uncore->i915) >= 11) {
+ mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
+ mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
+ } else {
+ mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
+ mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+ }
+
+ old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
+
+ mcr &= ~mcr_mask;
+ mcr |= mcr_ss;
+ intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
+
+ val = intel_uncore_read_fw(uncore, reg);
+
+ mcr &= ~mcr_mask;
+ mcr |= old_mcr & mcr_mask;
+
+ intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
+
+ return val;
+}
+
+u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore,
+ i915_reg_t reg, int slice, int subslice)
+{
+ enum forcewake_domains fw_domains;
+ u32 val;
+
+ fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
+ FW_REG_READ);
+ fw_domains |= intel_uncore_forcewake_for_reg(uncore,
+GEN8_MCR_SELECTOR,
+FW_REG_READ |
FW_REG_WRITE);
+
+ spin_lock_irq(&uncore->lock);
+ intel_uncore_forcewake_get__locked(uncore, fw_domains);
+
+ val = intel_uncore_read_with_mcr_steering_fw(uncore, reg, slice,
subslice);
+
+ intel_uncore_forcewake_put__locked(uncore, fw_domains);
+ spin_unlock_irq(&uncore->lock);
+
+ return val;
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#includ
[Intel-gfx] [PATCH 2/3] drm/i915: Add GT support for multiple types of multicast steering
Although most of our multicast registers are replicated per-subslice, we
also have a small number of multicast registers that are replicated
per-l3 bank instead. For both types of multicast registers we need to
make sure we steer reads of these registers to a valid instance.
Ideally we'd like to find a specific instance ID that would steer reads
of either type of multicast register to a valid instance (i.e., not
fused off and not powered down), but sometimes the combination of
part-specific fusing and the additional restrictions imposed by Render
Power Gating make it impossible to find any overlap between the set of
valid subslices and valid l3 banks. This problem will become even more
noticeable on our upcoming platforms since they will be adding
additional types of multicast registers with new types of replication
and rules for finding valid instances for reads.
To handle this we'll continue to pick a suitable subslice instance at
driver startup and program this as the default (sliceid,subsliceid)
setting in the steering control register (0xFDC). In cases where we
need to read another type of multicast GT register, but the default
subslice steering would not correspond to a valid instance, we'll
explicitly re-steer the single read to a valid value, perform the read,
and then reset the steering to it's "subslice" default.
This patch adds the general functionality to prepare for this explicit
steering of other multicast register types. We'll plug L3 bank steering
into this in the next patch, and then add additional types of multicast
registers when the support for our next upcoming platform arrives.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c| 84 +++
drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 22 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 28 ---
.../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
5 files changed, 131 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 2161bf01ef8b..f2bea1c20d56 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -697,6 +697,90 @@ void intel_gt_driver_late_release(struct intel_gt *gt)
intel_engines_free(gt);
}
+/**
+ * intel_gt_reg_needs_read_steering - determine whether a register read
+ * requires explicit steering
+ * @gt: GT structure
+ * @reg: the register to check steering requirements for
+ * @type: type of multicast steering to check
+ *
+ * Determines whether @reg needs explicit steering of a specific type for
+ * reads.
+ *
+ * Returns false if @reg does not belong to a register range of the given
+ * steering type, or if the default (subslice-based) steering IDs are suitable
+ * for @type steering too.
+ */
+static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
+i915_reg_t reg,
+enum intel_steering_type type)
+{
+ const u32 offset = i915_mmio_reg_offset(reg);
+ const struct intel_mmio_range *entry;
+
+ if (likely(!intel_gt_needs_read_steering(gt, type)))
+ return false;
+
+ for (entry = gt->steering_table[type]; entry->start < 0xFF;
entry++) {
+ if (offset >= entry->start && offset <= entry->end)
+ return true;
+ }
+
+ return false;
+}
+
+/**
+ * intel_gt_get_valid_steering - determines valid IDs for a class of MCR
steering
+ * @gt: GT structure
+ * @type: multicast register type
+ * @sliceid: Slice ID returned
+ * @subsliceid: Subslice ID returned
+ *
+ * Determines sliceid and subsliceid values that will steer reads
+ * of a specific multicast register class to a valid value.
+ */
+static void intel_gt_get_valid_steering(struct intel_gt *gt,
+ enum intel_steering_type type,
+ u8 *sliceid, u8 *subsliceid)
+{
+ switch (type) {
+ default:
+ MISSING_CASE(type);
+ *sliceid = 0;
+ *subsliceid = 0;
+ }
+}
+
+/**
+ * intel_gt_read_register_fw - reads a GT register with support for multicast
+ * @gt: GT structure
+ * @reg: register to read
+ *
+ * This function will read a GT register. If the register is a multicast
+ * register, the read will be steered to a valid instance (i.e., one that
+ * isn't fused off or powered down by power gating).
+ *
+ * Returns the value from a valid instance of @reg.
+ */
+u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg)
+{
+ int type;
+ u8 sliceid, subsliceid;
+
+ for (type = 0; type < NUM_STEERING_TYPES; type++) {
+ if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
+ intel_gt_get_valid_steering(gt, type, &
[Intel-gfx] [PATCH 3/3] drm/i915: Add support for explicit L3BANK steering
Because Render Power Gating restricts us to just a single subslice as a
valid steering target for reads of multicast registers in a SUBSLICE
range, the default steering we setup at init may not lead to a suitable
target for L3BANK multicast register. In cases where it does not, use
explicit runtime steering whenever an L3BANK multicast register is read.
While we're at it, let's simplify the function a little bit and drop its
support for gen10/CNL since no such platforms ever materialized for real
use. Multicast register steering is already an area that causes enough
confusion; no need to complicate it with what's effectively dead code.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 18 +
drivers/gpu/drm/i915/gt/intel_gt_types.h| 4 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 84 ++---
3 files changed, 46 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f2bea1c20d56..2c9cc34b0cbd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -83,6 +83,11 @@ void intel_gt_init_hw_early(struct intel_gt *gt, struct
i915_ggtt *ggtt)
gt->ggtt = ggtt;
}
+static const struct intel_mmio_range icl_l3bank_steering_table[] = {
+ { 0x00B100, 0x00B3FF },
+ { 0xFF, 0xFF }, /* terminating entry */
+};
+
int intel_gt_init_mmio(struct intel_gt *gt)
{
intel_gt_init_clock_frequency(gt);
@@ -90,6 +95,13 @@ int intel_gt_init_mmio(struct intel_gt *gt)
intel_uc_init_mmio(>->uc);
intel_sseu_info_init(gt);
+ if (GRAPHICS_VER(gt->i915) >= 11) {
+ gt->steering_table[L3BANK] = icl_l3bank_steering_table;
+ gt->info.l3bank_mask =
+ intel_uncore_read(>->i915->uncore,
GEN10_MIRROR_FUSE3) &
+ GEN10_L3BANK_MASK;
+ }
+
return intel_engines_init_mmio(gt);
}
@@ -744,6 +756,12 @@ static void intel_gt_get_valid_steering(struct intel_gt
*gt,
u8 *sliceid, u8 *subsliceid)
{
switch (type) {
+ case L3BANK:
+ GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be
impossible! */
+
+ *sliceid = __ffs(gt->info.l3bank_mask);
+ *subsliceid = 0;/* unused */
+ break;
default:
MISSING_CASE(type);
*sliceid = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 47957837c8c0..5ecad25de6ed 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -48,6 +48,8 @@ struct intel_mmio_range {
* need to explicitly re-steer reads of registers of the other type.
*/
enum intel_steering_type {
+ L3BANK,
+
NUM_STEERING_TYPES
};
@@ -174,6 +176,8 @@ struct intel_gt {
/* Media engine access to SFC per instance */
u8 vdbox_sfc_access;
+ u32 l3bank_mask;
+
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 689045d3752b..a0be3c09a7f9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -944,71 +944,37 @@ cfl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
}
static void
-wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
+icl_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
unsigned int slice, subslice;
- u32 l3_en, mcr, mcr_mask;
+ u32 mcr, mcr_mask;
- GEM_BUG_ON(GRAPHICS_VER(i915) < 10);
+ GEM_BUG_ON(GRAPHICS_VER(i915) < 11);
+ GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
+ slice = 0;
/*
-* WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
-* L3Banks could be fused off in single slice scenario. If that is
-* the case, we might need to program MCR select to a valid L3Bank
-* by default, to make sure we correctly read certain registers
-* later on (in the range 0xB100 - 0xB3FF).
-*
-* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
-* Before any MMIO read into slice/subslice specific registers, MCR
-* packet control register needs to be programmed to point to any
-* enabled s/ss pair. Otherwise, incorrect values will be returned.
-* This means each subsequent MMIO read will be forwarded to an
-* specific s/ss combination, but this is OK since these registers
-* are consistent across s/ss in almost all cases. In the rare
-* occasions, such as
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Add GT support for multiple types of multicast steering
On Tue, Jun 15, 2021 at 05:11:04AM -0400, Rodrigo Vivi wrote:
> On Tue, Jun 15, 2021 at 05:08:20AM -0400, Rodrigo Vivi wrote:
> > On Mon, Jun 14, 2021 at 08:34:32PM -0700, Matt Roper wrote:
> > > Although most of our multicast registers are replicated per-subslice, we
> > > also have a small number of multicast registers that are replicated
> > > per-l3 bank instead. For both types of multicast registers we need to
> > > make sure we steer reads of these registers to a valid instance.
> > > Ideally we'd like to find a specific instance ID that would steer reads
> > > of either type of multicast register to a valid instance (i.e., not
> > > fused off and not powered down), but sometimes the combination of
> > > part-specific fusing and the additional restrictions imposed by Render
> > > Power Gating make it impossible to find any overlap between the set of
> > > valid subslices and valid l3 banks. This problem will become even more
> > > noticeable on our upcoming platforms since they will be adding
> > > additional types of multicast registers with new types of replication
> > > and rules for finding valid instances for reads.
> > >
> > > To handle this we'll continue to pick a suitable subslice instance at
> > > driver startup and program this as the default (sliceid,subsliceid)
> > > setting in the steering control register (0xFDC). In cases where we
> > > need to read another type of multicast GT register, but the default
> > > subslice steering would not correspond to a valid instance, we'll
> > > explicitly re-steer the single read to a valid value, perform the read,
> > > and then reset the steering to it's "subslice" default.
> > >
> > > This patch adds the general functionality to prepare for this explicit
> > > steering of other multicast register types. We'll plug L3 bank steering
> > > into this in the next patch, and then add additional types of multicast
> > > registers when the support for our next upcoming platform arrives.
> > >
> > > Signed-off-by: Matt Roper
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_gt.c| 84 +++
> > > drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++
> > > drivers/gpu/drm/i915/gt/intel_gt_types.h | 22 +
> > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 28 ---
> > > .../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
> > > 5 files changed, 131 insertions(+), 13 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> > > b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > index 2161bf01ef8b..f2bea1c20d56 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > @@ -697,6 +697,90 @@ void intel_gt_driver_late_release(struct intel_gt
> > > *gt)
> > > intel_engines_free(gt);
> > > }
> > >
> > > +/**
> > > + * intel_gt_reg_needs_read_steering - determine whether a register read
> > > + * requires explicit steering
> > > + * @gt: GT structure
> > > + * @reg: the register to check steering requirements for
> > > + * @type: type of multicast steering to check
> > > + *
> > > + * Determines whether @reg needs explicit steering of a specific type for
> > > + * reads.
> > > + *
> > > + * Returns false if @reg does not belong to a register range of the given
> > > + * steering type, or if the default (subslice-based) steering IDs are
> > > suitable
> > > + * for @type steering too.
> > > + */
> > > +static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
> > > + i915_reg_t reg,
> > > + enum intel_steering_type type)
> > > +{
> > > + const u32 offset = i915_mmio_reg_offset(reg);
> > > + const struct intel_mmio_range *entry;
> > > +
> > > + if (likely(!intel_gt_needs_read_steering(gt, type)))
> > > + return false;
> > > +
> > > + for (entry = gt->steering_table[type]; entry->start < 0xFF;
> > > entry++) {
> >
> > I'm not comfortable with this stop condition...
Is your worry that we'll someday have registers going more than 16MB
into the MMIO BAR? Or just that we use a terminator entry in general?
We have lots of other places in the driver where we use this pattern
already (cdclk tables, dbuf tables, etc.). We're soon goi
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Add GT support for multiple types of multicast steering
On Tue, Jun 15, 2021 at 03:48:32PM -0400, Rodrigo Vivi wrote: > On Tue, Jun 15, 2021 at 08:30:23AM -0700, Matt Roper wrote: > > On Tue, Jun 15, 2021 at 05:11:04AM -0400, Rodrigo Vivi wrote: > > > On Tue, Jun 15, 2021 at 05:08:20AM -0400, Rodrigo Vivi wrote: > > > > On Mon, Jun 14, 2021 at 08:34:32PM -0700, Matt Roper wrote: > > > > > Although most of our multicast registers are replicated per-subslice, > > > > > we > > > > > also have a small number of multicast registers that are replicated > > > > > per-l3 bank instead. For both types of multicast registers we need to > > > > > make sure we steer reads of these registers to a valid instance. > > > > > Ideally we'd like to find a specific instance ID that would steer > > > > > reads > > > > > of either type of multicast register to a valid instance (i.e., not > > > > > fused off and not powered down), but sometimes the combination of > > > > > part-specific fusing and the additional restrictions imposed by Render > > > > > Power Gating make it impossible to find any overlap between the set of > > > > > valid subslices and valid l3 banks. This problem will become even > > > > > more > > > > > noticeable on our upcoming platforms since they will be adding > > > > > additional types of multicast registers with new types of replication > > > > > and rules for finding valid instances for reads. > > > > > > > > > > To handle this we'll continue to pick a suitable subslice instance at > > > > > driver startup and program this as the default (sliceid,subsliceid) > > > > > setting in the steering control register (0xFDC). In cases where we > > > > > need to read another type of multicast GT register, but the default > > > > > subslice steering would not correspond to a valid instance, we'll > > > > > explicitly re-steer the single read to a valid value, perform the > > > > > read, > > > > > and then reset the steering to it's "subslice" default. > > > > > > > > > > This patch adds the general functionality to prepare for this explicit > > > > > steering of other multicast register types. We'll plug L3 bank > > > > > steering > > > > > into this in the next patch, and then add additional types of > > > > > multicast > > > > > registers when the support for our next upcoming platform arrives. > > > > > > > > > > Signed-off-by: Matt Roper > > > > > --- > > > > > drivers/gpu/drm/i915/gt/intel_gt.c| 84 > > > > > +++ > > > > > drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++ > > > > > drivers/gpu/drm/i915/gt/intel_gt_types.h | 22 + > > > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 28 --- > > > > > .../gpu/drm/i915/gt/selftest_workarounds.c| 2 +- > > > > > 5 files changed, 131 insertions(+), 13 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c > > > > > b/drivers/gpu/drm/i915/gt/intel_gt.c > > > > > index 2161bf01ef8b..f2bea1c20d56 100644 > > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > > > > > @@ -697,6 +697,90 @@ void intel_gt_driver_late_release(struct > > > > > intel_gt *gt) > > > > > intel_engines_free(gt); > > > > > } > > > > > > > > > > +/** > > > > > + * intel_gt_reg_needs_read_steering - determine whether a register > > > > > read > > > > > + * requires explicit steering > > > > > + * @gt: GT structure > > > > > + * @reg: the register to check steering requirements for > > > > > + * @type: type of multicast steering to check > > > > > + * > > > > > + * Determines whether @reg needs explicit steering of a specific > > > > > type for > > > > > + * reads. > > > > > + * > > > > > + * Returns false if @reg does not belong to a register range of the > > > > > given > > > > > + * steering type, or if the default (subslice-based) steering IDs > > > > > are suitable > > > > > + * for @type stee
[Intel-gfx] [PATCH v2 0/3] Explicity steer l3bank multicast reads when necessary
We've recently learned that when steering reads of multicast registers
that use 'subslice' replication, it's not only important to steer to a
subslice that isn't fused off, but also to steer to the lowest-numbered
subslice. This is because when Render Power Gating is enabled, grabbing
forcewake will only cause the hardware to power up a single subslice
(referred to as the "minconfig") until/unless a real workload is being
run on the EUs. If we try to read back a value from a register instance
other than the minconfig subslice, the read operation will either return
0 or random garbage.
Unfortunately this extra requirement to steer to the minconfig means
that the steering target we use for subslice-replicated registers may
not select a valid instance for l3bank-replicated registers. In cases
where the two types of multicast registers do not have compatible
steering targets, we'll initialize the steering control register to the
proper subslice target at driver load, and then explicitly re-steer
individual reads of l3bank registers as they occur at runtime.
This series sets up an infrastructure to handle explicit resteering of
multiple multicast register types, and then applies it to l3bank
registers. Our next upcoming platform (which we'll probably start
upstreaming soon) will bring several more types of multicast registers,
each with their own steering criteria, so the infrastructure here is
partially in preparation for those extra multicast types that will be
arriving soon.
v2:
- Use {} as table terminator and check for end==0 instead of 0xFF
on loop iteration. (Rodrigo)
- Use gt->uncore instead of gt->i915->uncore. (Tvrtko)
- Now that wa_list_verify() uses _fw accessors we need to explicitly
grab forcewake.
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Tejas Upadhyay
Cc: Rodrigo Vivi
Daniele Ceraolo Spurio (1):
drm/i915: extract steered reg access to common function
Matt Roper (2):
drm/i915: Add GT support for multiple types of multicast steering
drm/i915: Add support for explicit L3BANK steering
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 41 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 102 +++
drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 26
drivers/gpu/drm/i915/gt/intel_workarounds.c | 123 --
.../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 55
drivers/gpu/drm/i915/intel_uncore.h | 6 +
8 files changed, 251 insertions(+), 112 deletions(-)
--
2.25.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 3/3] drm/i915: Add support for explicit L3BANK steering
Because Render Power Gating restricts us to just a single subslice as a
valid steering target for reads of multicast registers in a SUBSLICE
range, the default steering we setup at init may not lead to a suitable
target for L3BANK multicast register. In cases where it does not, use
explicit runtime steering whenever an L3BANK multicast register is read.
While we're at it, let's simplify the function a little bit and drop its
support for gen10/CNL since no such platforms ever materialized for real
use. Multicast register steering is already an area that causes enough
confusion; no need to complicate it with what's effectively dead code.
v2:
- Use gt->uncore instead of gt->i915->uncore. (Tvrtko)
- Use {} as table terminator. (Rodrigo)
Cc: Tvrtko Ursulin
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 18 +
drivers/gpu/drm/i915/gt/intel_gt_types.h| 4 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 84 ++---
3 files changed, 46 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 66299105da66..25a3ecf9892a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -83,6 +83,11 @@ void intel_gt_init_hw_early(struct intel_gt *gt, struct
i915_ggtt *ggtt)
gt->ggtt = ggtt;
}
+static const struct intel_mmio_range icl_l3bank_steering_table[] = {
+ { 0x00B100, 0x00B3FF },
+ {},
+};
+
int intel_gt_init_mmio(struct intel_gt *gt)
{
intel_gt_init_clock_frequency(gt);
@@ -90,6 +95,13 @@ int intel_gt_init_mmio(struct intel_gt *gt)
intel_uc_init_mmio(>->uc);
intel_sseu_info_init(gt);
+ if (GRAPHICS_VER(gt->i915) >= 11) {
+ gt->steering_table[L3BANK] = icl_l3bank_steering_table;
+ gt->info.l3bank_mask =
+ intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
+ GEN10_L3BANK_MASK;
+ }
+
return intel_engines_init_mmio(gt);
}
@@ -744,6 +756,12 @@ static void intel_gt_get_valid_steering(struct intel_gt
*gt,
u8 *sliceid, u8 *subsliceid)
{
switch (type) {
+ case L3BANK:
+ GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be
impossible! */
+
+ *sliceid = __ffs(gt->info.l3bank_mask);
+ *subsliceid = 0;/* unused */
+ break;
default:
MISSING_CASE(type);
*sliceid = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index f2c274eee1e6..80dc131e862f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -48,6 +48,8 @@ struct intel_mmio_range {
* need to explicitly re-steer reads of registers of the other type.
*/
enum intel_steering_type {
+ L3BANK,
+
NUM_STEERING_TYPES
};
@@ -174,6 +176,8 @@ struct intel_gt {
/* Media engine access to SFC per instance */
u8 vdbox_sfc_access;
+ u32 l3bank_mask;
+
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index df63baad254e..a8294eb4c9ab 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -944,71 +944,37 @@ cfl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
}
static void
-wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
+icl_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
unsigned int slice, subslice;
- u32 l3_en, mcr, mcr_mask;
+ u32 mcr, mcr_mask;
- GEM_BUG_ON(GRAPHICS_VER(i915) < 10);
+ GEM_BUG_ON(GRAPHICS_VER(i915) < 11);
+ GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
+ slice = 0;
/*
-* WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
-* L3Banks could be fused off in single slice scenario. If that is
-* the case, we might need to program MCR select to a valid L3Bank
-* by default, to make sure we correctly read certain registers
-* later on (in the range 0xB100 - 0xB3FF).
-*
-* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
-* Before any MMIO read into slice/subslice specific registers, MCR
-* packet control register needs to be programmed to point to any
-* enabled s/ss pair. Otherwise, incorrect values will be returned.
-* This means each subsequent MMIO read will be forwarded to an
-* specific s/ss combination, but this is OK since these reg
[Intel-gfx] [PATCH v2 2/3] drm/i915: Add GT support for multiple types of multicast steering
Although most of our multicast registers are replicated per-subslice, we
also have a small number of multicast registers that are replicated
per-l3 bank instead. For both types of multicast registers we need to
make sure we steer reads of these registers to a valid instance.
Ideally we'd like to find a specific instance ID that would steer reads
of either type of multicast register to a valid instance (i.e., not
fused off and not powered down), but sometimes the combination of
part-specific fusing and the additional restrictions imposed by Render
Power Gating make it impossible to find any overlap between the set of
valid subslices and valid l3 banks. This problem will become even more
noticeable on our upcoming platforms since they will be adding
additional types of multicast registers with new types of replication
and rules for finding valid instances for reads.
To handle this we'll continue to pick a suitable subslice instance at
driver startup and program this as the default (sliceid,subsliceid)
setting in the steering control register (0xFDC). In cases where we
need to read another type of multicast GT register, but the default
subslice steering would not correspond to a valid instance, we'll
explicitly re-steer the single read to a valid value, perform the read,
and then reset the steering to it's "subslice" default.
This patch adds the general functionality to prepare for this explicit
steering of other multicast register types. We'll plug L3 bank steering
into this in the next patch, and then add additional types of multicast
registers when the support for our next upcoming platform arrives.
v2:
- Use entry->end==0 as table terminator. (Rodrigo)
- Grab forcewake in wa_list_verify() now that we're using accessors
that assume forcewake is already held.
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c| 84 +++
drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 22 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 39 ++---
.../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
5 files changed, 142 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 2161bf01ef8b..66299105da66 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -697,6 +697,90 @@ void intel_gt_driver_late_release(struct intel_gt *gt)
intel_engines_free(gt);
}
+/**
+ * intel_gt_reg_needs_read_steering - determine whether a register read
+ * requires explicit steering
+ * @gt: GT structure
+ * @reg: the register to check steering requirements for
+ * @type: type of multicast steering to check
+ *
+ * Determines whether @reg needs explicit steering of a specific type for
+ * reads.
+ *
+ * Returns false if @reg does not belong to a register range of the given
+ * steering type, or if the default (subslice-based) steering IDs are suitable
+ * for @type steering too.
+ */
+static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
+i915_reg_t reg,
+enum intel_steering_type type)
+{
+ const u32 offset = i915_mmio_reg_offset(reg);
+ const struct intel_mmio_range *entry;
+
+ if (likely(!intel_gt_needs_read_steering(gt, type)))
+ return false;
+
+ for (entry = gt->steering_table[type]; !entry->end; entry++) {
+ if (offset >= entry->start && offset <= entry->end)
+ return true;
+ }
+
+ return false;
+}
+
+/**
+ * intel_gt_get_valid_steering - determines valid IDs for a class of MCR
steering
+ * @gt: GT structure
+ * @type: multicast register type
+ * @sliceid: Slice ID returned
+ * @subsliceid: Subslice ID returned
+ *
+ * Determines sliceid and subsliceid values that will steer reads
+ * of a specific multicast register class to a valid value.
+ */
+static void intel_gt_get_valid_steering(struct intel_gt *gt,
+ enum intel_steering_type type,
+ u8 *sliceid, u8 *subsliceid)
+{
+ switch (type) {
+ default:
+ MISSING_CASE(type);
+ *sliceid = 0;
+ *subsliceid = 0;
+ }
+}
+
+/**
+ * intel_gt_read_register_fw - reads a GT register with support for multicast
+ * @gt: GT structure
+ * @reg: register to read
+ *
+ * This function will read a GT register. If the register is a multicast
+ * register, the read will be steered to a valid instance (i.e., one that
+ * isn't fused off or powered down by power gating).
+ *
+ * Returns the value from a valid instance of @reg.
+ */
+u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg)
+{
+ int type;
+ u8 sliceid, subsliceid;
+
+
[Intel-gfx] [PATCH v2 1/3] drm/i915: extract steered reg access to common function
From: Daniele Ceraolo Spurio
New steering cases will be added in the follow-up patches, so prepare a
common helper to avoid code duplication.
Cc: Tvrtko Ursulin
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 41 +
drivers/gpu/drm/i915/intel_uncore.c | 55 +++
drivers/gpu/drm/i915/intel_uncore.h | 6 +++
3 files changed, 63 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 9ceddfbb1687..8b913c6961c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1105,45 +1105,8 @@ static u32
read_subslice_reg(const struct intel_engine_cs *engine,
int slice, int subslice, i915_reg_t reg)
{
- struct drm_i915_private *i915 = engine->i915;
- struct intel_uncore *uncore = engine->uncore;
- u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
- enum forcewake_domains fw_domains;
-
- if (GRAPHICS_VER(i915) >= 11) {
- mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
- mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
- } else {
- mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
- mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
- }
-
- fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
- FW_REG_READ);
- fw_domains |= intel_uncore_forcewake_for_reg(uncore,
-GEN8_MCR_SELECTOR,
-FW_REG_READ |
FW_REG_WRITE);
-
- spin_lock_irq(&uncore->lock);
- intel_uncore_forcewake_get__locked(uncore, fw_domains);
-
- old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
-
- mcr &= ~mcr_mask;
- mcr |= mcr_ss;
- intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
-
- val = intel_uncore_read_fw(uncore, reg);
-
- mcr &= ~mcr_mask;
- mcr |= old_mcr & mcr_mask;
-
- intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
-
- intel_uncore_forcewake_put__locked(uncore, fw_domains);
- spin_unlock_irq(&uncore->lock);
-
- return val;
+ return intel_uncore_read_with_mcr_steering(engine->uncore, reg,
+ slice, subslice);
}
/* NB: please notice the memset */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 1bed8f666048..d067524f9162 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2277,6 +2277,61 @@ intel_uncore_forcewake_for_reg(struct intel_uncore
*uncore,
return fw_domains;
}
+u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore,
+ i915_reg_t reg,
+ int slice, int subslice)
+{
+ u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
+
+ lockdep_assert_held(&uncore->lock);
+
+ if (GRAPHICS_VER(uncore->i915) >= 11) {
+ mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
+ mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
+ } else {
+ mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
+ mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+ }
+
+ old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
+
+ mcr &= ~mcr_mask;
+ mcr |= mcr_ss;
+ intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
+
+ val = intel_uncore_read_fw(uncore, reg);
+
+ mcr &= ~mcr_mask;
+ mcr |= old_mcr & mcr_mask;
+
+ intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
+
+ return val;
+}
+
+u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore,
+ i915_reg_t reg, int slice, int subslice)
+{
+ enum forcewake_domains fw_domains;
+ u32 val;
+
+ fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
+ FW_REG_READ);
+ fw_domains |= intel_uncore_forcewake_for_reg(uncore,
+GEN8_MCR_SELECTOR,
+FW_REG_READ |
FW_REG_WRITE);
+
+ spin_lock_irq(&uncore->lock);
+ intel_uncore_forcewake_get__locked(uncore, fw_domains);
+
+ val = intel_uncore_read_with_mcr_steering_fw(uncore, reg, slice,
subslice);
+
+ intel_uncore_forcewake_put__locked(uncore, fw_domains);
+ spin_unlock_irq(&uncore->lock);
+
+ return val;
+}
+
#if IS_ENABLED(CONFI
[Intel-gfx] [PATCH v2.1 2/3] drm/i915: Add GT support for multiple types of multicast steering
Although most of our multicast registers are replicated per-subslice, we
also have a small number of multicast registers that are replicated
per-l3 bank instead. For both types of multicast registers we need to
make sure we steer reads of these registers to a valid instance.
Ideally we'd like to find a specific instance ID that would steer reads
of either type of multicast register to a valid instance (i.e., not
fused off and not powered down), but sometimes the combination of
part-specific fusing and the additional restrictions imposed by Render
Power Gating make it impossible to find any overlap between the set of
valid subslices and valid l3 banks. This problem will become even more
noticeable on our upcoming platforms since they will be adding
additional types of multicast registers with new types of replication
and rules for finding valid instances for reads.
To handle this we'll continue to pick a suitable subslice instance at
driver startup and program this as the default (sliceid,subsliceid)
setting in the steering control register (0xFDC). In cases where we
need to read another type of multicast GT register, but the default
subslice steering would not correspond to a valid instance, we'll
explicitly re-steer the single read to a valid value, perform the read,
and then reset the steering to it's "subslice" default.
This patch adds the general functionality to prepare for this explicit
steering of other multicast register types. We'll plug L3 bank steering
into this in the next patch, and then add additional types of multicast
registers when the support for our next upcoming platform arrives.
v2:
- Use entry->end==0 as table terminator. (Rodrigo)
- Grab forcewake in wa_list_verify() now that we're using accessors
that assume forcewake is already held.
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c| 84 +++
drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 22 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 39 ++---
.../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
5 files changed, 142 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 2161bf01ef8b..66299105da66 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -697,6 +697,90 @@ void intel_gt_driver_late_release(struct intel_gt *gt)
intel_engines_free(gt);
}
+/**
+ * intel_gt_reg_needs_read_steering - determine whether a register read
+ * requires explicit steering
+ * @gt: GT structure
+ * @reg: the register to check steering requirements for
+ * @type: type of multicast steering to check
+ *
+ * Determines whether @reg needs explicit steering of a specific type for
+ * reads.
+ *
+ * Returns false if @reg does not belong to a register range of the given
+ * steering type, or if the default (subslice-based) steering IDs are suitable
+ * for @type steering too.
+ */
+static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
+i915_reg_t reg,
+enum intel_steering_type type)
+{
+ const u32 offset = i915_mmio_reg_offset(reg);
+ const struct intel_mmio_range *entry;
+
+ if (likely(!intel_gt_needs_read_steering(gt, type)))
+ return false;
+
+ for (entry = gt->steering_table[type]; !entry->end; entry++) {
+ if (offset >= entry->start && offset <= entry->end)
+ return true;
+ }
+
+ return false;
+}
+
+/**
+ * intel_gt_get_valid_steering - determines valid IDs for a class of MCR
steering
+ * @gt: GT structure
+ * @type: multicast register type
+ * @sliceid: Slice ID returned
+ * @subsliceid: Subslice ID returned
+ *
+ * Determines sliceid and subsliceid values that will steer reads
+ * of a specific multicast register class to a valid value.
+ */
+static void intel_gt_get_valid_steering(struct intel_gt *gt,
+ enum intel_steering_type type,
+ u8 *sliceid, u8 *subsliceid)
+{
+ switch (type) {
+ default:
+ MISSING_CASE(type);
+ *sliceid = 0;
+ *subsliceid = 0;
+ }
+}
+
+/**
+ * intel_gt_read_register_fw - reads a GT register with support for multicast
+ * @gt: GT structure
+ * @reg: register to read
+ *
+ * This function will read a GT register. If the register is a multicast
+ * register, the read will be steered to a valid instance (i.e., one that
+ * isn't fused off or powered down by power gating).
+ *
+ * Returns the value from a valid instance of @reg.
+ */
+u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg)
+{
+ int type;
+ u8 sliceid, subsliceid;
+
+
[Intel-gfx] [PATCH v2.1 1/3] drm/i915: extract steered reg access to common function
From: Daniele Ceraolo Spurio
New steering cases will be added in the follow-up patches, so prepare a
common helper to avoid code duplication.
Cc: Tvrtko Ursulin
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 41 +
drivers/gpu/drm/i915/intel_uncore.c | 55 +++
drivers/gpu/drm/i915/intel_uncore.h | 6 +++
3 files changed, 63 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 9ceddfbb1687..8b913c6961c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1105,45 +1105,8 @@ static u32
read_subslice_reg(const struct intel_engine_cs *engine,
int slice, int subslice, i915_reg_t reg)
{
- struct drm_i915_private *i915 = engine->i915;
- struct intel_uncore *uncore = engine->uncore;
- u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
- enum forcewake_domains fw_domains;
-
- if (GRAPHICS_VER(i915) >= 11) {
- mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
- mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
- } else {
- mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
- mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
- }
-
- fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
- FW_REG_READ);
- fw_domains |= intel_uncore_forcewake_for_reg(uncore,
-GEN8_MCR_SELECTOR,
-FW_REG_READ |
FW_REG_WRITE);
-
- spin_lock_irq(&uncore->lock);
- intel_uncore_forcewake_get__locked(uncore, fw_domains);
-
- old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
-
- mcr &= ~mcr_mask;
- mcr |= mcr_ss;
- intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
-
- val = intel_uncore_read_fw(uncore, reg);
-
- mcr &= ~mcr_mask;
- mcr |= old_mcr & mcr_mask;
-
- intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
-
- intel_uncore_forcewake_put__locked(uncore, fw_domains);
- spin_unlock_irq(&uncore->lock);
-
- return val;
+ return intel_uncore_read_with_mcr_steering(engine->uncore, reg,
+ slice, subslice);
}
/* NB: please notice the memset */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 1bed8f666048..d067524f9162 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2277,6 +2277,61 @@ intel_uncore_forcewake_for_reg(struct intel_uncore
*uncore,
return fw_domains;
}
+u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore,
+ i915_reg_t reg,
+ int slice, int subslice)
+{
+ u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
+
+ lockdep_assert_held(&uncore->lock);
+
+ if (GRAPHICS_VER(uncore->i915) >= 11) {
+ mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
+ mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
+ } else {
+ mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
+ mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+ }
+
+ old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
+
+ mcr &= ~mcr_mask;
+ mcr |= mcr_ss;
+ intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
+
+ val = intel_uncore_read_fw(uncore, reg);
+
+ mcr &= ~mcr_mask;
+ mcr |= old_mcr & mcr_mask;
+
+ intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
+
+ return val;
+}
+
+u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore,
+ i915_reg_t reg, int slice, int subslice)
+{
+ enum forcewake_domains fw_domains;
+ u32 val;
+
+ fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
+ FW_REG_READ);
+ fw_domains |= intel_uncore_forcewake_for_reg(uncore,
+GEN8_MCR_SELECTOR,
+FW_REG_READ |
FW_REG_WRITE);
+
+ spin_lock_irq(&uncore->lock);
+ intel_uncore_forcewake_get__locked(uncore, fw_domains);
+
+ val = intel_uncore_read_with_mcr_steering_fw(uncore, reg, slice,
subslice);
+
+ intel_uncore_forcewake_put__locked(uncore, fw_domains);
+ spin_unlock_irq(&uncore->lock);
+
+ return val;
+}
+
#if IS_ENABLED(CONFI
[Intel-gfx] [PATCH v2.1 0/3] Explicity steer l3bank multicast reads when necessary
We've recently learned that when steering reads of multicast registers
that use 'subslice' replication, it's not only important to steer to a
subslice that isn't fused off, but also to steer to the lowest-numbered
subslice. This is because when Render Power Gating is enabled, grabbing
forcewake will only cause the hardware to power up a single subslice
(referred to as the "minconfig") until/unless a real workload is being
run on the EUs. If we try to read back a value from a register instance
other than the minconfig subslice, the read operation will either return
0 or random garbage.
Unfortunately this extra requirement to steer to the minconfig means
that the steering target we use for subslice-replicated registers may
not select a valid instance for l3bank-replicated registers. In cases
where the two types of multicast registers do not have compatible
steering targets, we'll initialize the steering control register to the
proper subslice target at driver load, and then explicitly re-steer
individual reads of l3bank registers as they occur at runtime.
This series sets up an infrastructure to handle explicit resteering of
multiple multicast register types, and then applies it to l3bank
registers. Our next upcoming platform (which we'll probably start
upstreaming soon) will bring several more types of multicast registers,
each with their own steering criteria, so the infrastructure here is
partially in preparation for those extra multicast types that will be
arriving soon.
v2:
- Use {} as table terminator and check for end==0 instead of 0xFF
on loop iteration. (Rodrigo)
- Use gt->uncore instead of gt->i915->uncore. (Tvrtko)
- Now that wa_list_verify() uses _fw accessors we need to explicitly
grab forcewake.
v2.1:
- Rebase
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Tejas Upadhyay
Cc: Rodrigo Vivi
Daniele Ceraolo Spurio (1):
drm/i915: extract steered reg access to common function
Matt Roper (2):
drm/i915: Add GT support for multiple types of multicast steering
drm/i915: Add support for explicit L3BANK steering
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 41 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 102 +++
drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 26
drivers/gpu/drm/i915/gt/intel_workarounds.c | 123 --
.../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 55
drivers/gpu/drm/i915/intel_uncore.h | 6 +
8 files changed, 251 insertions(+), 112 deletions(-)
--
2.25.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2.1 3/3] drm/i915: Add support for explicit L3BANK steering
Because Render Power Gating restricts us to just a single subslice as a
valid steering target for reads of multicast registers in a SUBSLICE
range, the default steering we setup at init may not lead to a suitable
target for L3BANK multicast register. In cases where it does not, use
explicit runtime steering whenever an L3BANK multicast register is read.
While we're at it, let's simplify the function a little bit and drop its
support for gen10/CNL since no such platforms ever materialized for real
use. Multicast register steering is already an area that causes enough
confusion; no need to complicate it with what's effectively dead code.
v2:
- Use gt->uncore instead of gt->i915->uncore. (Tvrtko)
- Use {} as table terminator. (Rodrigo)
Cc: Tvrtko Ursulin
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 18 +
drivers/gpu/drm/i915/gt/intel_gt_types.h| 4 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 84 ++---
3 files changed, 46 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 66299105da66..25a3ecf9892a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -83,6 +83,11 @@ void intel_gt_init_hw_early(struct intel_gt *gt, struct
i915_ggtt *ggtt)
gt->ggtt = ggtt;
}
+static const struct intel_mmio_range icl_l3bank_steering_table[] = {
+ { 0x00B100, 0x00B3FF },
+ {},
+};
+
int intel_gt_init_mmio(struct intel_gt *gt)
{
intel_gt_init_clock_frequency(gt);
@@ -90,6 +95,13 @@ int intel_gt_init_mmio(struct intel_gt *gt)
intel_uc_init_mmio(>->uc);
intel_sseu_info_init(gt);
+ if (GRAPHICS_VER(gt->i915) >= 11) {
+ gt->steering_table[L3BANK] = icl_l3bank_steering_table;
+ gt->info.l3bank_mask =
+ intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
+ GEN10_L3BANK_MASK;
+ }
+
return intel_engines_init_mmio(gt);
}
@@ -744,6 +756,12 @@ static void intel_gt_get_valid_steering(struct intel_gt
*gt,
u8 *sliceid, u8 *subsliceid)
{
switch (type) {
+ case L3BANK:
+ GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be
impossible! */
+
+ *sliceid = __ffs(gt->info.l3bank_mask);
+ *subsliceid = 0;/* unused */
+ break;
default:
MISSING_CASE(type);
*sliceid = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index f2c274eee1e6..80dc131e862f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -48,6 +48,8 @@ struct intel_mmio_range {
* need to explicitly re-steer reads of registers of the other type.
*/
enum intel_steering_type {
+ L3BANK,
+
NUM_STEERING_TYPES
};
@@ -174,6 +176,8 @@ struct intel_gt {
/* Media engine access to SFC per instance */
u8 vdbox_sfc_access;
+ u32 l3bank_mask;
+
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 93c74d4cae02..d9a5a445ceec 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -945,71 +945,37 @@ cfl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
}
static void
-wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
+icl_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
unsigned int slice, subslice;
- u32 l3_en, mcr, mcr_mask;
+ u32 mcr, mcr_mask;
- GEM_BUG_ON(GRAPHICS_VER(i915) < 10);
+ GEM_BUG_ON(GRAPHICS_VER(i915) < 11);
+ GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
+ slice = 0;
/*
-* WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
-* L3Banks could be fused off in single slice scenario. If that is
-* the case, we might need to program MCR select to a valid L3Bank
-* by default, to make sure we correctly read certain registers
-* later on (in the range 0xB100 - 0xB3FF).
-*
-* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
-* Before any MMIO read into slice/subslice specific registers, MCR
-* packet control register needs to be programmed to point to any
-* enabled s/ss pair. Otherwise, incorrect values will be returned.
-* This means each subsequent MMIO read will be forwarded to an
-* specific s/ss combination, but this is OK since these reg
Re: [Intel-gfx] [PATCH v2.1 2/3] drm/i915: Add GT support for multiple types of multicast steering
On Wed, Jun 16, 2021 at 10:24:48AM -0400, Rodrigo Vivi wrote:
> On Tue, Jun 15, 2021 at 05:42:12PM -0700, Matt Roper wrote:
> > Although most of our multicast registers are replicated per-subslice, we
> > also have a small number of multicast registers that are replicated
> > per-l3 bank instead. For both types of multicast registers we need to
> > make sure we steer reads of these registers to a valid instance.
> > Ideally we'd like to find a specific instance ID that would steer reads
> > of either type of multicast register to a valid instance (i.e., not
> > fused off and not powered down), but sometimes the combination of
> > part-specific fusing and the additional restrictions imposed by Render
> > Power Gating make it impossible to find any overlap between the set of
> > valid subslices and valid l3 banks. This problem will become even more
> > noticeable on our upcoming platforms since they will be adding
> > additional types of multicast registers with new types of replication
> > and rules for finding valid instances for reads.
> >
> > To handle this we'll continue to pick a suitable subslice instance at
> > driver startup and program this as the default (sliceid,subsliceid)
> > setting in the steering control register (0xFDC). In cases where we
> > need to read another type of multicast GT register, but the default
> > subslice steering would not correspond to a valid instance, we'll
> > explicitly re-steer the single read to a valid value, perform the read,
> > and then reset the steering to it's "subslice" default.
> >
> > This patch adds the general functionality to prepare for this explicit
> > steering of other multicast register types. We'll plug L3 bank steering
> > into this in the next patch, and then add additional types of multicast
> > registers when the support for our next upcoming platform arrives.
> >
> > v2:
> > - Use entry->end==0 as table terminator. (Rodrigo)
> > - Grab forcewake in wa_list_verify() now that we're using accessors
> >that assume forcewake is already held.
> >
> > Cc: Rodrigo Vivi
> > Signed-off-by: Matt Roper
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt.c| 84 +++
> > drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++
> > drivers/gpu/drm/i915/gt/intel_gt_types.h | 22 +
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 39 ++---
> > .../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
> > 5 files changed, 142 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> > b/drivers/gpu/drm/i915/gt/intel_gt.c
> > index 2161bf01ef8b..66299105da66 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > @@ -697,6 +697,90 @@ void intel_gt_driver_late_release(struct intel_gt *gt)
> > intel_engines_free(gt);
> > }
> >
> > +/**
> > + * intel_gt_reg_needs_read_steering - determine whether a register read
> > + * requires explicit steering
> > + * @gt: GT structure
> > + * @reg: the register to check steering requirements for
> > + * @type: type of multicast steering to check
> > + *
> > + * Determines whether @reg needs explicit steering of a specific type for
> > + * reads.
> > + *
> > + * Returns false if @reg does not belong to a register range of the given
> > + * steering type, or if the default (subslice-based) steering IDs are
> > suitable
> > + * for @type steering too.
> > + */
> > +static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
> > +i915_reg_t reg,
> > +enum intel_steering_type type)
> > +{
> > + const u32 offset = i915_mmio_reg_offset(reg);
> > + const struct intel_mmio_range *entry;
> > +
> > + if (likely(!intel_gt_needs_read_steering(gt, type)))
> > + return false;
> > +
> > + for (entry = gt->steering_table[type]; !entry->end; entry++) {
>
> shouldn't it be:
> for (entry = gt->steering_table[type]; entry->end; entry++) {
> ?!
Yep, good catch. I'll fix this.
Matt
>
> or maybe this is just the proof that the 0x terminator
> is less confusing?! :)
>
> with this fixed:
>
> Reviewed-by: Rodrigo Vivi
>
> > + if (offset >= entry->start && offset <= entry->end)
> > + return true;
> > + }
> > +
> > + return false;
> > +}
> > +
&g
[Intel-gfx] [PATCH v3 2/3] drm/i915: Add GT support for multiple types of multicast steering
Although most of our multicast registers are replicated per-subslice, we
also have a small number of multicast registers that are replicated
per-l3 bank instead. For both types of multicast registers we need to
make sure we steer reads of these registers to a valid instance.
Ideally we'd like to find a specific instance ID that would steer reads
of either type of multicast register to a valid instance (i.e., not
fused off and not powered down), but sometimes the combination of
part-specific fusing and the additional restrictions imposed by Render
Power Gating make it impossible to find any overlap between the set of
valid subslices and valid l3 banks. This problem will become even more
noticeable on our upcoming platforms since they will be adding
additional types of multicast registers with new types of replication
and rules for finding valid instances for reads.
To handle this we'll continue to pick a suitable subslice instance at
driver startup and program this as the default (sliceid,subsliceid)
setting in the steering control register (0xFDC). In cases where we
need to read another type of multicast GT register, but the default
subslice steering would not correspond to a valid instance, we'll
explicitly re-steer the single read to a valid value, perform the read,
and then reset the steering to it's "subslice" default.
This patch adds the general functionality to prepare for this explicit
steering of other multicast register types. We'll plug L3 bank steering
into this in the next patch, and then add additional types of multicast
registers when the support for our next upcoming platform arrives.
v2:
- Use entry->end==0 as table terminator. (Rodrigo)
- Grab forcewake in wa_list_verify() now that we're using accessors
that assume forcewake is already held.
v3:
- Fix loop condition when iterating over steering range tables.
(Rodrigo)
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt.c| 84 +++
drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 22 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 39 ++---
.../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
5 files changed, 142 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 2161bf01ef8b..80badc54b19d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -697,6 +697,90 @@ void intel_gt_driver_late_release(struct intel_gt *gt)
intel_engines_free(gt);
}
+/**
+ * intel_gt_reg_needs_read_steering - determine whether a register read
+ * requires explicit steering
+ * @gt: GT structure
+ * @reg: the register to check steering requirements for
+ * @type: type of multicast steering to check
+ *
+ * Determines whether @reg needs explicit steering of a specific type for
+ * reads.
+ *
+ * Returns false if @reg does not belong to a register range of the given
+ * steering type, or if the default (subslice-based) steering IDs are suitable
+ * for @type steering too.
+ */
+static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
+i915_reg_t reg,
+enum intel_steering_type type)
+{
+ const u32 offset = i915_mmio_reg_offset(reg);
+ const struct intel_mmio_range *entry;
+
+ if (likely(!intel_gt_needs_read_steering(gt, type)))
+ return false;
+
+ for (entry = gt->steering_table[type]; entry->end; entry++) {
+ if (offset >= entry->start && offset <= entry->end)
+ return true;
+ }
+
+ return false;
+}
+
+/**
+ * intel_gt_get_valid_steering - determines valid IDs for a class of MCR
steering
+ * @gt: GT structure
+ * @type: multicast register type
+ * @sliceid: Slice ID returned
+ * @subsliceid: Subslice ID returned
+ *
+ * Determines sliceid and subsliceid values that will steer reads
+ * of a specific multicast register class to a valid value.
+ */
+static void intel_gt_get_valid_steering(struct intel_gt *gt,
+ enum intel_steering_type type,
+ u8 *sliceid, u8 *subsliceid)
+{
+ switch (type) {
+ default:
+ MISSING_CASE(type);
+ *sliceid = 0;
+ *subsliceid = 0;
+ }
+}
+
+/**
+ * intel_gt_read_register_fw - reads a GT register with support for multicast
+ * @gt: GT structure
+ * @reg: register to read
+ *
+ * This function will read a GT register. If the register is a multicast
+ * register, the read will be steered to a valid instance (i.e., one that
+ * isn't fused off or powered down by power gating).
+ *
+ * Returns the value from a valid instance of @reg.
+ */
+u32 intel_gt_read_regist
[Intel-gfx] [PATCH v3 3/3] drm/i915: Add support for explicit L3BANK steering
Because Render Power Gating restricts us to just a single subslice as a
valid steering target for reads of multicast registers in a SUBSLICE
range, the default steering we setup at init may not lead to a suitable
target for L3BANK multicast register. In cases where it does not, use
explicit runtime steering whenever an L3BANK multicast register is read.
While we're at it, let's simplify the function a little bit and drop its
support for gen10/CNL since no such platforms ever materialized for real
use. Multicast register steering is already an area that causes enough
confusion; no need to complicate it with what's effectively dead code.
v2:
- Use gt->uncore instead of gt->i915->uncore. (Tvrtko)
- Use {} as table terminator. (Rodrigo)
v3:
- L3bank fuse register is a disable mask rather than an enable mask.
We need to invert it before use. (CI)
Cc: Tvrtko Ursulin
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt.c | 18 +
drivers/gpu/drm/i915/gt/intel_gt_types.h| 4 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 84 ++---
3 files changed, 46 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 80badc54b19d..3128ea476a98 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -83,6 +83,11 @@ void intel_gt_init_hw_early(struct intel_gt *gt, struct
i915_ggtt *ggtt)
gt->ggtt = ggtt;
}
+static const struct intel_mmio_range icl_l3bank_steering_table[] = {
+ { 0x00B100, 0x00B3FF },
+ {},
+};
+
int intel_gt_init_mmio(struct intel_gt *gt)
{
intel_gt_init_clock_frequency(gt);
@@ -90,6 +95,13 @@ int intel_gt_init_mmio(struct intel_gt *gt)
intel_uc_init_mmio(>->uc);
intel_sseu_info_init(gt);
+ if (GRAPHICS_VER(gt->i915) >= 11) {
+ gt->steering_table[L3BANK] = icl_l3bank_steering_table;
+ gt->info.l3bank_mask =
+ ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
+ GEN10_L3BANK_MASK;
+ }
+
return intel_engines_init_mmio(gt);
}
@@ -744,6 +756,12 @@ static void intel_gt_get_valid_steering(struct intel_gt
*gt,
u8 *sliceid, u8 *subsliceid)
{
switch (type) {
+ case L3BANK:
+ GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be
impossible! */
+
+ *sliceid = __ffs(gt->info.l3bank_mask);
+ *subsliceid = 0;/* unused */
+ break;
default:
MISSING_CASE(type);
*sliceid = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index f2c274eee1e6..80dc131e862f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -48,6 +48,8 @@ struct intel_mmio_range {
* need to explicitly re-steer reads of registers of the other type.
*/
enum intel_steering_type {
+ L3BANK,
+
NUM_STEERING_TYPES
};
@@ -174,6 +176,8 @@ struct intel_gt {
/* Media engine access to SFC per instance */
u8 vdbox_sfc_access;
+ u32 l3bank_mask;
+
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 93c74d4cae02..d9a5a445ceec 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -945,71 +945,37 @@ cfl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
}
static void
-wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
+icl_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
unsigned int slice, subslice;
- u32 l3_en, mcr, mcr_mask;
+ u32 mcr, mcr_mask;
- GEM_BUG_ON(GRAPHICS_VER(i915) < 10);
+ GEM_BUG_ON(GRAPHICS_VER(i915) < 11);
+ GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
+ slice = 0;
/*
-* WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
-* L3Banks could be fused off in single slice scenario. If that is
-* the case, we might need to program MCR select to a valid L3Bank
-* by default, to make sure we correctly read certain registers
-* later on (in the range 0xB100 - 0xB3FF).
-*
-* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
-* Before any MMIO read into slice/subslice specific registers, MCR
-* packet control register needs to be programmed to point to any
-* enabled s/ss pair. Otherwise, incorrect values will be retu
[Intel-gfx] [PATCH v4 3/3] drm/i915: Add support for explicit L3BANK steering
Because Render Power Gating restricts us to just a single subslice as a
valid steering target for reads of multicast registers in a SUBSLICE
range, the default steering we setup at init may not lead to a suitable
target for L3BANK multicast register. In cases where it does not, use
explicit runtime steering whenever an L3BANK multicast register is read.
While we're at it, let's simplify the function a little bit and drop its
support for gen10/CNL since no such platforms ever materialized for real
use. Multicast register steering is already an area that causes enough
confusion; no need to complicate it with what's effectively dead code.
v2:
- Use gt->uncore instead of gt->i915->uncore. (Tvrtko)
- Use {} as table terminator. (Rodrigo)
v3:
- L3bank fuse register is a disable mask rather than an enable mask.
We need to invert it before use. (CI)
v4:
- L3bank ID goes in the subslice field, not the slice field. (CI)
Cc: Tvrtko Ursulin
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt.c | 18 +
drivers/gpu/drm/i915/gt/intel_gt_types.h| 4 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 84 ++---
3 files changed, 46 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 80badc54b19d..a668f6670ce0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -83,6 +83,11 @@ void intel_gt_init_hw_early(struct intel_gt *gt, struct
i915_ggtt *ggtt)
gt->ggtt = ggtt;
}
+static const struct intel_mmio_range icl_l3bank_steering_table[] = {
+ { 0x00B100, 0x00B3FF },
+ {},
+};
+
int intel_gt_init_mmio(struct intel_gt *gt)
{
intel_gt_init_clock_frequency(gt);
@@ -90,6 +95,13 @@ int intel_gt_init_mmio(struct intel_gt *gt)
intel_uc_init_mmio(>->uc);
intel_sseu_info_init(gt);
+ if (GRAPHICS_VER(gt->i915) >= 11) {
+ gt->steering_table[L3BANK] = icl_l3bank_steering_table;
+ gt->info.l3bank_mask =
+ ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
+ GEN10_L3BANK_MASK;
+ }
+
return intel_engines_init_mmio(gt);
}
@@ -744,6 +756,12 @@ static void intel_gt_get_valid_steering(struct intel_gt
*gt,
u8 *sliceid, u8 *subsliceid)
{
switch (type) {
+ case L3BANK:
+ GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be
impossible! */
+
+ *sliceid = 0; /* unused */
+ *subsliceid = __ffs(gt->info.l3bank_mask);
+ break;
default:
MISSING_CASE(type);
*sliceid = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index f2c274eee1e6..80dc131e862f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -48,6 +48,8 @@ struct intel_mmio_range {
* need to explicitly re-steer reads of registers of the other type.
*/
enum intel_steering_type {
+ L3BANK,
+
NUM_STEERING_TYPES
};
@@ -174,6 +176,8 @@ struct intel_gt {
/* Media engine access to SFC per instance */
u8 vdbox_sfc_access;
+ u32 l3bank_mask;
+
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 93c74d4cae02..d9a5a445ceec 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -945,71 +945,37 @@ cfl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
}
static void
-wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
+icl_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
unsigned int slice, subslice;
- u32 l3_en, mcr, mcr_mask;
+ u32 mcr, mcr_mask;
- GEM_BUG_ON(GRAPHICS_VER(i915) < 10);
+ GEM_BUG_ON(GRAPHICS_VER(i915) < 11);
+ GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
+ slice = 0;
/*
-* WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
-* L3Banks could be fused off in single slice scenario. If that is
-* the case, we might need to program MCR select to a valid L3Bank
-* by default, to make sure we correctly read certain registers
-* later on (in the range 0xB100 - 0xB3FF).
-*
-* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
-* Before any MMIO read into slice/subslice specific registers, MCR
-* packet control register needs to be programmed to point to a
[Intel-gfx] [CI 0/3] Explicity steer l3bank multicast reads when necessary
We've recently learned that when steering reads of multicast registers
that use 'subslice' replication, it's not only important to steer to a
subslice that isn't fused off, but also to steer to the lowest-numbered
subslice. This is because when Render Power Gating is enabled, grabbing
forcewake will only cause the hardware to power up a single subslice
(referred to as the "minconfig") until/unless a real workload is being
run on the EUs. If we try to read back a value from a register instance
other than the minconfig subslice, the read operation will either return
0 or random garbage.
Unfortunately this extra requirement to steer to the minconfig means
that the steering target we use for subslice-replicated registers may
not select a valid instance for l3bank-replicated registers. In cases
where the two types of multicast registers do not have compatible
steering targets, we'll initialize the steering control register to the
proper subslice target at driver load, and then explicitly re-steer
individual reads of l3bank registers as they occur at runtime.
This series sets up an infrastructure to handle explicit resteering of
multiple multicast register types, and then applies it to l3bank
registers. Our next upcoming platform (which we'll probably start
upstreaming soon) will bring several more types of multicast registers,
each with their own steering criteria, so the infrastructure here is
partially in preparation for those extra multicast types that will be
arriving soon.
v2:
- Use {} as table terminator and check for end==0 instead of 0xFF
on loop iteration. (Rodrigo)
- Use gt->uncore instead of gt->i915->uncore. (Tvrtko)
- Now that wa_list_verify() uses _fw accessors we need to explicitly
grab forcewake.
v2.1:
- Rebase
v3:
- The L3BANK fuse value is a disable mask rather than an enable mask.
We need to invert it before applying ffs() to select a valid
instance.
v4:
- The selected L3BANK ID goes in the subslice field of the steering
register, not the slice field.
v4.1:
- Rebase
Cc: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Tejas Upadhyay
Cc: Rodrigo Vivi
Daniele Ceraolo Spurio (1):
drm/i915: extract steered reg access to common function
Matt Roper (2):
drm/i915: Add GT support for multiple types of multicast steering
drm/i915: Add support for explicit L3BANK steering
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 41 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 102 +++
drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 26
drivers/gpu/drm/i915/gt/intel_workarounds.c | 123 --
.../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 55
drivers/gpu/drm/i915/intel_uncore.h | 6 +
8 files changed, 251 insertions(+), 112 deletions(-)
--
2.25.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/3] drm/i915: Add GT support for multiple types of multicast steering
Although most of our multicast registers are replicated per-subslice, we
also have a small number of multicast registers that are replicated
per-l3 bank instead. For both types of multicast registers we need to
make sure we steer reads of these registers to a valid instance.
Ideally we'd like to find a specific instance ID that would steer reads
of either type of multicast register to a valid instance (i.e., not
fused off and not powered down), but sometimes the combination of
part-specific fusing and the additional restrictions imposed by Render
Power Gating make it impossible to find any overlap between the set of
valid subslices and valid l3 banks. This problem will become even more
noticeable on our upcoming platforms since they will be adding
additional types of multicast registers with new types of replication
and rules for finding valid instances for reads.
To handle this we'll continue to pick a suitable subslice instance at
driver startup and program this as the default (sliceid,subsliceid)
setting in the steering control register (0xFDC). In cases where we
need to read another type of multicast GT register, but the default
subslice steering would not correspond to a valid instance, we'll
explicitly re-steer the single read to a valid value, perform the read,
and then reset the steering to it's "subslice" default.
This patch adds the general functionality to prepare for this explicit
steering of other multicast register types. We'll plug L3 bank steering
into this in the next patch, and then add additional types of multicast
registers when the support for our next upcoming platform arrives.
v2:
- Use entry->end==0 as table terminator. (Rodrigo)
- Grab forcewake in wa_list_verify() now that we're using accessors
that assume forcewake is already held.
v3:
- Fix loop condition when iterating over steering range tables.
(Rodrigo)
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt.c| 84 +++
drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 22 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 39 ++---
.../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
5 files changed, 142 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 67ef057ae918..1c7ca7a090ab 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -701,6 +701,90 @@ void intel_gt_driver_late_release(struct intel_gt *gt)
intel_engines_free(gt);
}
+/**
+ * intel_gt_reg_needs_read_steering - determine whether a register read
+ * requires explicit steering
+ * @gt: GT structure
+ * @reg: the register to check steering requirements for
+ * @type: type of multicast steering to check
+ *
+ * Determines whether @reg needs explicit steering of a specific type for
+ * reads.
+ *
+ * Returns false if @reg does not belong to a register range of the given
+ * steering type, or if the default (subslice-based) steering IDs are suitable
+ * for @type steering too.
+ */
+static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
+i915_reg_t reg,
+enum intel_steering_type type)
+{
+ const u32 offset = i915_mmio_reg_offset(reg);
+ const struct intel_mmio_range *entry;
+
+ if (likely(!intel_gt_needs_read_steering(gt, type)))
+ return false;
+
+ for (entry = gt->steering_table[type]; entry->end; entry++) {
+ if (offset >= entry->start && offset <= entry->end)
+ return true;
+ }
+
+ return false;
+}
+
+/**
+ * intel_gt_get_valid_steering - determines valid IDs for a class of MCR
steering
+ * @gt: GT structure
+ * @type: multicast register type
+ * @sliceid: Slice ID returned
+ * @subsliceid: Subslice ID returned
+ *
+ * Determines sliceid and subsliceid values that will steer reads
+ * of a specific multicast register class to a valid value.
+ */
+static void intel_gt_get_valid_steering(struct intel_gt *gt,
+ enum intel_steering_type type,
+ u8 *sliceid, u8 *subsliceid)
+{
+ switch (type) {
+ default:
+ MISSING_CASE(type);
+ *sliceid = 0;
+ *subsliceid = 0;
+ }
+}
+
+/**
+ * intel_gt_read_register_fw - reads a GT register with support for multicast
+ * @gt: GT structure
+ * @reg: register to read
+ *
+ * This function will read a GT register. If the register is a multicast
+ * register, the read will be steered to a valid instance (i.e., one that
+ * isn't fused off or powered down by power gating).
+ *
+ * Returns the value from a valid instance of @reg.
+ */
+u32 intel_gt_read_regist
[Intel-gfx] [CI 3/3] drm/i915: Add support for explicit L3BANK steering
Because Render Power Gating restricts us to just a single subslice as a
valid steering target for reads of multicast registers in a SUBSLICE
range, the default steering we setup at init may not lead to a suitable
target for L3BANK multicast register. In cases where it does not, use
explicit runtime steering whenever an L3BANK multicast register is read.
While we're at it, let's simplify the function a little bit and drop its
support for gen10/CNL since no such platforms ever materialized for real
use. Multicast register steering is already an area that causes enough
confusion; no need to complicate it with what's effectively dead code.
v2:
- Use gt->uncore instead of gt->i915->uncore. (Tvrtko)
- Use {} as table terminator. (Rodrigo)
v3:
- L3bank fuse register is a disable mask rather than an enable mask.
We need to invert it before use. (CI)
v4:
- L3bank ID goes in the subslice field, not the slice field. (CI)
Cc: Tvrtko Ursulin
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_gt.c | 18 +
drivers/gpu/drm/i915/gt/intel_gt_types.h| 4 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 84 ++---
3 files changed, 46 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 1c7ca7a090ab..e714e21c0a4d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -84,6 +84,11 @@ void intel_gt_init_hw_early(struct intel_gt *gt, struct
i915_ggtt *ggtt)
gt->ggtt = ggtt;
}
+static const struct intel_mmio_range icl_l3bank_steering_table[] = {
+ { 0x00B100, 0x00B3FF },
+ {},
+};
+
int intel_gt_init_mmio(struct intel_gt *gt)
{
intel_gt_init_clock_frequency(gt);
@@ -91,6 +96,13 @@ int intel_gt_init_mmio(struct intel_gt *gt)
intel_uc_init_mmio(>->uc);
intel_sseu_info_init(gt);
+ if (GRAPHICS_VER(gt->i915) >= 11) {
+ gt->steering_table[L3BANK] = icl_l3bank_steering_table;
+ gt->info.l3bank_mask =
+ ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
+ GEN10_L3BANK_MASK;
+ }
+
return intel_engines_init_mmio(gt);
}
@@ -748,6 +760,12 @@ static void intel_gt_get_valid_steering(struct intel_gt
*gt,
u8 *sliceid, u8 *subsliceid)
{
switch (type) {
+ case L3BANK:
+ GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be
impossible! */
+
+ *sliceid = 0; /* unused */
+ *subsliceid = __ffs(gt->info.l3bank_mask);
+ break;
default:
MISSING_CASE(type);
*sliceid = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index cabea1966b4e..d93d578a4105 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -49,6 +49,8 @@ struct intel_mmio_range {
* need to explicitly re-steer reads of registers of the other type.
*/
enum intel_steering_type {
+ L3BANK,
+
NUM_STEERING_TYPES
};
@@ -177,6 +179,8 @@ struct intel_gt {
/* Media engine access to SFC per instance */
u8 vdbox_sfc_access;
+ u32 l3bank_mask;
+
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 93c74d4cae02..d9a5a445ceec 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -945,71 +945,37 @@ cfl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
}
static void
-wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
+icl_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
unsigned int slice, subslice;
- u32 l3_en, mcr, mcr_mask;
+ u32 mcr, mcr_mask;
- GEM_BUG_ON(GRAPHICS_VER(i915) < 10);
+ GEM_BUG_ON(GRAPHICS_VER(i915) < 11);
+ GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
+ slice = 0;
/*
-* WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
-* L3Banks could be fused off in single slice scenario. If that is
-* the case, we might need to program MCR select to a valid L3Bank
-* by default, to make sure we correctly read certain registers
-* later on (in the range 0xB100 - 0xB3FF).
-*
-* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
-* Before any MMIO read into slice/subslice specific registers, MCR
-* packet control register needs to be programmed to point to a
[Intel-gfx] [CI 1/3] drm/i915: extract steered reg access to common function
From: Daniele Ceraolo Spurio
New steering cases will be added in the follow-up patches, so prepare a
common helper to avoid code duplication.
Cc: Tvrtko Ursulin
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 41 +
drivers/gpu/drm/i915/intel_uncore.c | 55 +++
drivers/gpu/drm/i915/intel_uncore.h | 6 +++
3 files changed, 63 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index fcbaad18ac91..04c1f5b9ce71 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1112,45 +1112,8 @@ static u32
read_subslice_reg(const struct intel_engine_cs *engine,
int slice, int subslice, i915_reg_t reg)
{
- struct drm_i915_private *i915 = engine->i915;
- struct intel_uncore *uncore = engine->uncore;
- u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
- enum forcewake_domains fw_domains;
-
- if (GRAPHICS_VER(i915) >= 11) {
- mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
- mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
- } else {
- mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
- mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
- }
-
- fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
- FW_REG_READ);
- fw_domains |= intel_uncore_forcewake_for_reg(uncore,
-GEN8_MCR_SELECTOR,
-FW_REG_READ |
FW_REG_WRITE);
-
- spin_lock_irq(&uncore->lock);
- intel_uncore_forcewake_get__locked(uncore, fw_domains);
-
- old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
-
- mcr &= ~mcr_mask;
- mcr |= mcr_ss;
- intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
-
- val = intel_uncore_read_fw(uncore, reg);
-
- mcr &= ~mcr_mask;
- mcr |= old_mcr & mcr_mask;
-
- intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
-
- intel_uncore_forcewake_put__locked(uncore, fw_domains);
- spin_unlock_irq(&uncore->lock);
-
- return val;
+ return intel_uncore_read_with_mcr_steering(engine->uncore, reg,
+ slice, subslice);
}
/* NB: please notice the memset */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 1bed8f666048..d067524f9162 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2277,6 +2277,61 @@ intel_uncore_forcewake_for_reg(struct intel_uncore
*uncore,
return fw_domains;
}
+u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore,
+ i915_reg_t reg,
+ int slice, int subslice)
+{
+ u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
+
+ lockdep_assert_held(&uncore->lock);
+
+ if (GRAPHICS_VER(uncore->i915) >= 11) {
+ mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
+ mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
+ } else {
+ mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
+ mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+ }
+
+ old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
+
+ mcr &= ~mcr_mask;
+ mcr |= mcr_ss;
+ intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
+
+ val = intel_uncore_read_fw(uncore, reg);
+
+ mcr &= ~mcr_mask;
+ mcr |= old_mcr & mcr_mask;
+
+ intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
+
+ return val;
+}
+
+u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore,
+ i915_reg_t reg, int slice, int subslice)
+{
+ enum forcewake_domains fw_domains;
+ u32 val;
+
+ fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
+ FW_REG_READ);
+ fw_domains |= intel_uncore_forcewake_for_reg(uncore,
+GEN8_MCR_SELECTOR,
+FW_REG_READ |
FW_REG_WRITE);
+
+ spin_lock_irq(&uncore->lock);
+ intel_uncore_forcewake_get__locked(uncore, fw_domains);
+
+ val = intel_uncore_read_with_mcr_steering_fw(uncore, reg, slice,
subslice);
+
+ intel_uncore_forcewake_put__locked(uncore, fw_domains);
+ spin_unlock_irq(&uncore->lock);
+
+ return val;
+}
+
#if IS_ENABLED(CONFI
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Explicity steer l3bank multicast reads when necessary (rev7)
pipe-c-coverage-7efc.html >[121]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20404/shard-skl10/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html > > * igt@kms_psr@psr2_cursor_blt: > - shard-iclb: [SKIP][122] ([fdo#109441]) -> [PASS][123] +1 > similar issue >[122]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10239/shard-iclb3/igt@kms_psr@psr2_cursor_blt.html >[123]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20404/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html > > * igt@kms_vblank@pipe-a-ts-continuation-suspend: > - shard-apl: [DMESG-WARN][124] ([i915#180] / [i915#295]) -> > [PASS][125] >[124]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10239/shard-apl7/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html >[125]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20404/shard-apl3/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html > > * igt@kms_vblank@pipe-b-ts-continuation-suspend: > - shard-kbl: [DMESG-WARN][126] ([i915#180]) -> [PASS][127] +2 > similar issues >[126]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10239/shard-kbl4/igt@kms_vbl...@pipe-b-ts-continuation-suspend.html >[127]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20404/shard-kbl2/igt@kms_vbl...@pipe-b-ts-continuation-suspend.html > > * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend: > - shard-skl: [INCOMPLETE][128] ([i915#198] / [i915#2405]) -> > [PASS][129] >[128]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10239/shard-skl8/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html >[129]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20404/shard-skl5/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html > > * igt@prime_vgem@sync@vcs0: > - shard-skl: [INCOMPLETE][130] ([i915#409]) -> [PASS][131] >[130]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10239/shard-skl6/igt@prime_vgem@s...@vcs0.html >[131]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20404/shard-skl9/igt@prime_vgem@s...@vcs0.html > > > Warnings > > * igt@gem_exec_fair@basic-pace@vcs0: > - shard-kbl: [SKIP][132] ([fdo#109271]) -> [FAIL][133] > ([i915#2842]) >[132]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10239/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs0.html >[133]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20404/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs0.html > > * igt@i915_pm_rc6_residency@rc6-fence: > - shard-iclb: [WARN][134] ([i915#1804] / [i915#2684]) -> > [WARN][135] ([i915#2684]) >[134]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10239/shard-iclb7/igt@i915_pm_rc6_reside...@rc6-fence.html >[135]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20404/shard-iclb8/igt@i915_pm_rc6_reside...@rc6-fence.html > > * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4: > - shard-iclb: [SKIP][136] ([i915#658]) -> [SKIP][137] > ([i915#2920]) +2 similar issues >[136]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10239/shard-iclb3/igt@kms_psr2...@overlay-primary-update-sf-dmg-area-4.html >[137]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20404/shard-iclb2/igt@kms_psr2...@overlay-primary-update-sf-dmg-area-4.html > > * igt@kms_psr2_sf@plane-move-sf-dmg-area-1: > - shard-iclb: [SKIP][138] ([i915#2920]) -> [SKIP][139] > ([i915#658]) +1 similar issue >[138]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10239/shard-iclb2/igt@kms_psr2...@plane-move-sf-dmg-area-1.html >[139]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20404/shard-iclb1/igt@kms_psr2...@plane-move-sf-dmg-area-1.html > > * igt@runner@aborted: > - shard-kbl: ([FAIL][140], [FAIL][141], [FAIL][142], > [FAIL][143], [FAIL][144], [FAIL][145]) ([i915#180] / [i915#1814] / > [i915#3002] / [i915 > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20404/index.html -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce i915_sched_engine object (rev6)
-ci.01.org/tree/drm-tip/CI_DRM_10240/shard-iclb3/igt@run...@aborted.html >[128]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20406/shard-iclb1/igt@run...@aborted.html >[129]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20406/shard-iclb6/igt@run...@aborted.html >[130]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20406/shard-iclb7/igt@run...@aborted.html > - shard-apl: ([FAIL][131], [FAIL][132], [FAIL][133], > [FAIL][134], [FAIL][135]) ([i915#180] / [i915#1814] / [i915#3002] / > [i915#3363]) -> ([FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], > [FAIL][140]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / > [i915#3363]) >[131]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10240/shard-apl1/igt@run...@aborted.html >[132]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10240/shard-apl3/igt@run...@aborted.html >[133]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10240/shard-apl7/igt@run...@aborted.html >[134]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10240/shard-apl6/igt@run...@aborted.html >[135]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10240/shard-apl6/igt@run...@aborted.html >[136]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20406/shard-apl6/igt@run...@aborted.html >[137]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20406/shard-apl1/igt@run...@aborted.html >[138]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20406/shard-apl2/igt@run...@aborted.html >[139]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20406/shard-apl3/igt@run...@aborted.html >[140]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20406/shard-apl1/igt@run...@aborted.html > - shard-skl: ([FAIL][141], [FAIL][142]) ([i915#3002] / > [i915#3363]) -> ([FAIL][143], [FAIL][144], [FAIL][145]) ([i915#1436] / > [i915#3002] / [i915#3363]) >[141]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10240/shard-skl10/igt@run...@aborted.html >[142]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10240/shard-skl10/igt@run...@aborted.html >[143]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20406/shard-skl6/igt@run...@aborted.html >[144]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20406/shard-skl3/igt@run...@aborted.html >[145]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20406/shard-skl4/igt@run...@aborted.html > > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 > [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 > [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 > [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 > [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 > [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 > [fdo#110892]: https://bugs.freedesktop.org/show_bug.cgi?id=110892 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [fdo#112306]: https://bugs.freedesktop.org/show_bug.cgi?id=112306 > [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 > [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1804]: https:/ > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20406/index.html > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Update firmware to v62.0.0 (rev4)
: [SKIP][125] ([i915#2920]) -> [SKIP][126] > ([i915#658]) >[125]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10226/shard-iclb2/igt@kms_psr2...@plane-move-sf-dmg-area-2.html >[126]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20379/shard-iclb4/igt@kms_psr2...@plane-move-sf-dmg-area-2.html > > * igt@runner@aborted: > - shard-kbl: ([FAIL][127], [FAIL][128], [FAIL][129], > [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134]) ([i915#1436] > / [i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#3363]) -> > ([FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139]) > ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / > [i915#92]) >[127]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10226/shard-kbl7/igt@run...@aborted.html >[128]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10226/shard-kbl4/igt@run...@aborted.html >[129]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10226/shard-kbl4/igt@run...@aborted.html >[130]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10226/shard-kbl4/igt@run...@aborted.html >[131]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10226/shard-kbl7/igt@run...@aborted.html >[132]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10226/shard-kbl7/igt@run...@aborted.html >[133]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10226/shard-kbl4/igt@run...@aborted.html >[134]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10226/shard-kbl6/igt@run...@aborted.html >[135]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20379/shard-kbl2/igt@run...@aborted.html >[136]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20379/shard-kbl4/igt@run...@aborted.html >[137]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20379/shard-kbl4/igt@run...@aborted.html >[138]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20379/shard-kbl4/igt@run...@aborted.html >[139]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20379/shard-kbl7/igt@run...@aborted.html > - shard-iclb: ([FAIL][140], [FAIL][141], [FAIL][142]) > ([i915#2426] / [i915#3002] / [i915#409]) -> ([FAIL][143], [FAIL][144], > [FAIL][145], [FAIL][146]) ([i915#1814] / [i915#3002]) >[140]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10226/shard-iclb3/igt@run...@aborted.html >[141]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10226/shard-iclb7/igt@run...@aborted.html >[142]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10226/shard-iclb5/igt@run...@aborted.html >[143]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20379/shard-iclb6/igt@run...@aborted.html >[144]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20379/shard-iclb2/igt@run...@aborted.html >[145]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20379/shard-iclb1/igt@run...@aborted.html >[146]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20379/shard-iclb1/igt@run...@aborted.html > - shard-apl: ([FAIL][147], [FAIL][148], [FAIL][149], > [FAIL][150]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> > ([FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155], > [FAIL][156], [FAIL][157], [FAIL][158], [FAIL][159]) ([fdo#109271] / > [i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) >[147]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10226/shard-apl3/igt@run...@aborted.html >[148]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10226/shard-apl6/igt@run...@aborted.html >[149]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10226/shard-apl2/igt@run...@aborted.html >[150]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10226/shard-apl3/igt@run...@aborted.html >[151]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20379/shard-apl8/igt@run...@aborted.html >[152]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20379/shard-apl8/igt@run...@aborted.html >[153]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20379/shard-apl8/igt@run...@aborted.html > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20379/index.html > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 00/11] i915: Initial multi-tile support
Some of our upcoming platforms, including the Xe_HP SDV, support a "multi-tile" design. A multi-tile platform is effectively a platform with multiple GT instances and local memory regions, all behind a single PCI device. From an i915 perspective, this translates to multiple intel_gt structures per drm_i915_private. This series provides the initial refactoring to support multiple independent GTs per card, but further work (especially related to local memory) will be required to fully enable a multi-tile platform. Note that the presence of multiple GTs is largely transparent to userspace. A multi-tile platform will advertise a larger list of engines to userspace, but the concept of "tile" is not something userspace has to worry about directly. There will be some uapi implications later due to the devices having multiple local memory regions, but that aspect of multi-tile is not covered by this patch series and will show up in future work. Daniele Ceraolo Spurio (2): drm/i915: split general MMIO setup from per-GT uncore init drm/i915: Initial support for per-tile uncore Matt Roper (1): drm/i915: Restructure probe to handle multi-tile platforms Michal Wajdeczko (1): drm/i915/guc: Update CT debug macro for multi-tile Michał Winiarski (1): drm/i915: Store backpointer to GT in uncore Paulo Zanoni (3): drm/i915: rework some irq functions to take intel_gt as argument drm/i915/xehp: Determine which tile raised an interrupt drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware Tvrtko Ursulin (2): drm/i915: Prepare for multiple gts drm/i915/xehpsdv: Initialize multi-tiles Venkata Sandeep Dhanalakota (1): drm/i915: Release per-gt resources allocated drivers/gpu/drm/i915/gt/intel_gt.c| 180 +- drivers/gpu/drm/i915/gt/intel_gt.h| 11 +- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 + drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +- drivers/gpu/drm/i915/i915_debugfs.c | 5 +- drivers/gpu/drm/i915/i915_drv.c | 80 ++-- drivers/gpu/drm/i915/i915_drv.h | 9 + drivers/gpu/drm/i915/i915_irq.c | 71 --- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 4 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_memory_region.h| 3 + drivers/gpu/drm/i915/intel_uncore.c | 36 ++-- drivers/gpu/drm/i915/intel_uncore.h | 6 +- .../gpu/drm/i915/selftests/mock_gem_device.c | 3 +- drivers/gpu/drm/i915/selftests/mock_uncore.c | 2 +- 17 files changed, 345 insertions(+), 89 deletions(-) -- 2.33.0
[Intel-gfx] [PATCH 02/11] drm/i915: split general MMIO setup from per-GT uncore init
From: Daniele Ceraolo Spurio
In coming patches we'll be doing the actual tile initialization between
these two uncore init phases.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.c | 9 -
drivers/gpu/drm/i915/intel_uncore.c | 17 +++--
drivers/gpu/drm/i915/intel_uncore.h | 2 ++
3 files changed, 13 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c65c3742887a..7f96d26c012a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -415,10 +415,14 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
if (ret < 0)
return ret;
- ret = intel_uncore_init_mmio(&dev_priv->uncore);
+ ret = intel_uncore_setup_mmio(&dev_priv->uncore);
if (ret < 0)
goto err_bridge;
+ ret = intel_uncore_init_mmio(&dev_priv->uncore);
+ if (ret)
+ goto err_mmio;
+
/* Try to make sure MCHBAR is enabled before poking at it */
intel_setup_mchbar(dev_priv);
intel_device_info_runtime_init(dev_priv);
@@ -435,6 +439,8 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
err_uncore:
intel_teardown_mchbar(dev_priv);
intel_uncore_fini_mmio(&dev_priv->uncore);
+err_mmio:
+ intel_uncore_cleanup_mmio(&dev_priv->uncore);
err_bridge:
pci_dev_put(dev_priv->bridge_dev);
@@ -449,6 +455,7 @@ static void i915_driver_mmio_release(struct
drm_i915_private *dev_priv)
{
intel_teardown_mchbar(dev_priv);
intel_uncore_fini_mmio(&dev_priv->uncore);
+ intel_uncore_cleanup_mmio(&dev_priv->uncore);
pci_dev_put(dev_priv->bridge_dev);
}
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index e072054adac5..a308e86c9d9f 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2020,7 +2020,7 @@ static int i915_pmic_bus_access_notifier(struct
notifier_block *nb,
return NOTIFY_OK;
}
-static int uncore_mmio_setup(struct intel_uncore *uncore)
+int intel_uncore_setup_mmio(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore->i915;
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
@@ -2053,7 +2053,7 @@ static int uncore_mmio_setup(struct intel_uncore *uncore)
return 0;
}
-static void uncore_mmio_cleanup(struct intel_uncore *uncore)
+void intel_uncore_cleanup_mmio(struct intel_uncore *uncore)
{
struct pci_dev *pdev = to_pci_dev(uncore->i915->drm.dev);
@@ -2146,10 +2146,6 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
struct drm_i915_private *i915 = uncore->i915;
int ret;
- ret = uncore_mmio_setup(uncore);
- if (ret)
- return ret;
-
/*
* The boot firmware initializes local memory and assesses its health.
* If memory training fails, the punit will have been instructed to
@@ -2170,7 +2166,7 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
} else {
ret = uncore_forcewake_init(uncore);
if (ret)
- goto out_mmio_cleanup;
+ return ret;
}
/* make sure fw funcs are set if and only if we have fw*/
@@ -2192,11 +2188,6 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init,
clearing\n");
return 0;
-
-out_mmio_cleanup:
- uncore_mmio_cleanup(uncore);
-
- return ret;
}
/*
@@ -2261,8 +2252,6 @@ void intel_uncore_fini_mmio(struct intel_uncore *uncore)
intel_uncore_fw_domains_fini(uncore);
iosf_mbi_punit_release();
}
-
- uncore_mmio_cleanup(uncore);
}
static const struct reg_whitelist {
diff --git a/drivers/gpu/drm/i915/intel_uncore.h
b/drivers/gpu/drm/i915/intel_uncore.h
index 3248e4e2c540..d1d17b04e29f 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -218,11 +218,13 @@ void
intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
void intel_uncore_init_early(struct intel_uncore *uncore,
struct drm_i915_private *i915);
+int intel_uncore_setup_mmio(struct intel_uncore *uncore);
int intel_uncore_init_mmio(struct intel_uncore *uncore);
void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
struct intel_gt *gt);
bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
+void intel_uncore_cleanup_mmio(struct intel_uncore *uncore);
void intel_uncore_fini_mmio(struct intel_uncore *uncore
[Intel-gfx] [PATCH 05/11] drm/i915: Prepare for multiple gts
From: Tvrtko Ursulin
Add some basic plumbing to support more than one dynamically allocated
struct intel_gt. Up to four gts are supported in i915->gts[], with slot
zero shadowing the existing i915->gt to enable source compatibility with
legacy driver paths. A for_each_gt macro is added to iterate over the
GTs and will be used by upcoming patches that convert various parts of
the driver to be multi-gt aware.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 74 --
drivers/gpu/drm/i915/gt/intel_gt.h | 8 ++-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +
drivers/gpu/drm/i915/i915_drv.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h| 6 ++
drivers/gpu/drm/i915/intel_memory_region.h | 3 +
6 files changed, 86 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 863039d56cba..736725411f51 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -23,10 +23,13 @@
#include "shmem_utils.h"
#include "pxp/intel_pxp.h"
-void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
+static void
+__intel_gt_init_early(struct intel_gt *gt,
+ struct intel_uncore *uncore,
+ struct drm_i915_private *i915)
{
gt->i915 = i915;
- gt->uncore = &i915->uncore;
+ gt->uncore = uncore;
spin_lock_init(>->irq_lock);
@@ -46,13 +49,18 @@ void intel_gt_init_early(struct intel_gt *gt, struct
drm_i915_private *i915)
intel_rps_init_early(>->rps);
}
-int intel_gt_probe_lmem(struct intel_gt *gt)
+static int intel_gt_probe_lmem(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
+ unsigned int instance = gt->info.id;
struct intel_memory_region *mem;
int id;
int err;
+ id = INTEL_REGION_LMEM + instance;
+ if (drm_WARN_ON(&i915->drm, id >= INTEL_REGION_STOLEN_SMEM))
+ return -ENODEV;
+
mem = intel_gt_setup_lmem(gt);
if (mem == ERR_PTR(-ENODEV))
mem = intel_gt_setup_fake_lmem(gt);
@@ -67,9 +75,8 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
return err;
}
- id = INTEL_REGION_LMEM;
-
mem->id = id;
+ mem->instance = instance;
intel_memory_region_set_name(mem, "local%u", mem->instance);
@@ -80,6 +87,11 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
return 0;
}
+void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
+{
+ __intel_gt_init_early(gt, &i915->uncore, i915);
+}
+
void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
{
gt->ggtt = ggtt;
@@ -903,9 +915,29 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt,
i915_reg_t reg)
static int
tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t phys_addr)
{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore;
+ struct intel_uncore_mmio_debug *mmio_debug;
int ret;
- intel_uncore_init_early(gt->uncore, gt);
+ if (id) {
+ uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
+ if (!uncore)
+ return -ENOMEM;
+
+ mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
+ if (!mmio_debug) {
+ kfree(uncore);
+ return -ENOMEM;
+ }
+
+ __intel_gt_init_early(gt, uncore, i915);
+ } else {
+ uncore = &i915->uncore;
+ mmio_debug = &i915->mmio_debug;
+ }
+
+ intel_uncore_init_early(uncore, gt);
ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
if (ret)
@@ -919,6 +951,11 @@ tile_setup(struct intel_gt *gt, unsigned int id,
phys_addr_t phys_addr)
static void tile_cleanup(struct intel_gt *gt)
{
intel_uncore_cleanup_mmio(gt->uncore);
+
+ if (gt->info.id) {
+ kfree(gt->uncore);
+ kfree(gt);
+ }
}
int intel_probe_gts(struct drm_i915_private *i915)
@@ -936,13 +973,36 @@ int intel_probe_gts(struct drm_i915_private *i915)
if (ret)
return ret;
+ i915->gts[0] = &i915->gt;
+
/* TODO: add more tiles */
return 0;
}
+int intel_gt_tiles_init(struct drm_i915_private *i915)
+{
+ struct intel_gt *gt;
+ unsigned int id;
+ int ret;
+
+ for_each_gt(i915, id, gt) {
+ ret = intel_gt_probe_lmem(gt);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
void intel_gts_release(struct drm_i915_private *i915)
{
- tile_cleanup(&i915->gt);
+ struct intel_gt *gt;
+
[Intel-gfx] [PATCH 04/11] drm/i915: Store backpointer to GT in uncore
From: Michał Winiarski
We now support a per-gt uncore, yet we're not able to infer which GT
we're operating upon. Let's store a backpointer for now.
Signed-off-by: Michał Winiarski
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 9 +
drivers/gpu/drm/i915/intel_uncore.h | 3 ++-
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 +--
drivers/gpu/drm/i915/selftests/mock_uncore.c | 2 +-
5 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f4bea1f1de77..863039d56cba 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -905,7 +905,7 @@ tile_setup(struct intel_gt *gt, unsigned int id,
phys_addr_t phys_addr)
{
int ret;
- intel_uncore_init_early(gt->uncore, gt->i915);
+ intel_uncore_init_early(gt->uncore, gt);
ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
if (ret)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 8a0a0676d67a..2c449836f537 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2057,12 +2057,13 @@ void intel_uncore_cleanup_mmio(struct intel_uncore
*uncore)
}
void intel_uncore_init_early(struct intel_uncore *uncore,
-struct drm_i915_private *i915)
+struct intel_gt *gt)
{
spin_lock_init(&uncore->lock);
- uncore->i915 = i915;
- uncore->rpm = &i915->runtime_pm;
- uncore->debug = &i915->mmio_debug;
+ uncore->i915 = gt->i915;
+ uncore->gt = gt;
+ uncore->rpm = >->i915->runtime_pm;
+ uncore->debug = >->i915->mmio_debug;
}
static void uncore_raw_init(struct intel_uncore *uncore)
diff --git a/drivers/gpu/drm/i915/intel_uncore.h
b/drivers/gpu/drm/i915/intel_uncore.h
index 83a455aa8374..2989032b580b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -130,6 +130,7 @@ struct intel_uncore {
void __iomem *regs;
struct drm_i915_private *i915;
+ struct intel_gt *gt;
struct intel_runtime_pm *rpm;
spinlock_t lock; /** lock is also taken in irq contexts. */
@@ -218,7 +219,7 @@ u32 intel_uncore_read_with_mcr_steering(struct intel_uncore
*uncore,
void
intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
void intel_uncore_init_early(struct intel_uncore *uncore,
-struct drm_i915_private *i915);
+struct intel_gt *gt);
int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t
phys_addr);
int intel_uncore_init_mmio(struct intel_uncore *uncore);
void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 4f8180146888..bd21bb7d104e 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -175,10 +175,9 @@ struct drm_i915_private *mock_gem_device(void)
mkwrite_device_info(i915)->memory_regions = REGION_SMEM;
intel_memory_regions_hw_probe(i915);
- mock_uncore_init(&i915->uncore, i915);
-
i915_gem_init__mm(i915);
intel_gt_init_early(&i915->gt, i915);
+ mock_uncore_init(&i915->uncore, i915);
atomic_inc(&i915->gt.wakeref.count); /* disable; no hw support */
i915->gt.awake = -ENODEV;
diff --git a/drivers/gpu/drm/i915/selftests/mock_uncore.c
b/drivers/gpu/drm/i915/selftests/mock_uncore.c
index ca57e4008701..b3790ef137e4 100644
--- a/drivers/gpu/drm/i915/selftests/mock_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/mock_uncore.c
@@ -42,7 +42,7 @@ __nop_read(64)
void mock_uncore_init(struct intel_uncore *uncore,
struct drm_i915_private *i915)
{
- intel_uncore_init_early(uncore, i915);
+ intel_uncore_init_early(uncore, &i915->gt);
ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, nop);
ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, nop);
--
2.33.0
[Intel-gfx] [PATCH 01/11] drm/i915: rework some irq functions to take intel_gt as argument
From: Paulo Zanoni
We'll be adding multi-tile support soon; on multi-tile platforms
interrupts are per-tile and every tile has the full set of
interrupt registers.
In this commit we start passing intel_gt instead of dev_priv for the
functions that are related to Xe_HP irq handling. Right now we're still
passing tile 0 everywhere, but in later patches we'll start actually
passing the correct tile.
Signed-off-by: Paulo Zanoni
Co-authored-by: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 77680bca46ee..038a9ec563c1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2772,7 +2772,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
{
struct drm_i915_private * const i915 = arg;
struct intel_gt *gt = &i915->gt;
- void __iomem * const regs = i915->uncore.regs;
+ void __iomem * const regs = gt->uncore->regs;
u32 master_tile_ctl, master_ctl;
u32 gu_misc_iir;
@@ -3173,11 +3173,12 @@ static void gen11_display_irq_reset(struct
drm_i915_private *dev_priv)
static void gen11_irq_reset(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_gt *gt = &dev_priv->gt;
+ struct intel_uncore *uncore = gt->uncore;
gen11_master_intr_disable(dev_priv->uncore.regs);
- gen11_gt_irq_reset(&dev_priv->gt);
+ gen11_gt_irq_reset(gt);
gen11_display_irq_reset(dev_priv);
GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
@@ -3186,11 +3187,12 @@ static void gen11_irq_reset(struct drm_i915_private
*dev_priv)
static void dg1_irq_reset(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_gt *gt = &dev_priv->gt;
+ struct intel_uncore *uncore = gt->uncore;
dg1_master_intr_disable(dev_priv->uncore.regs);
- gen11_gt_irq_reset(&dev_priv->gt);
+ gen11_gt_irq_reset(gt);
gen11_display_irq_reset(dev_priv);
GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
@@ -3869,13 +3871,14 @@ static void gen11_de_irq_postinstall(struct
drm_i915_private *dev_priv)
static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_gt *gt = &dev_priv->gt;
+ struct intel_uncore *uncore = gt->uncore;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
icp_irq_postinstall(dev_priv);
- gen11_gt_irq_postinstall(&dev_priv->gt);
+ gen11_gt_irq_postinstall(gt);
gen11_de_irq_postinstall(dev_priv);
GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
@@ -3886,10 +3889,11 @@ static void gen11_irq_postinstall(struct
drm_i915_private *dev_priv)
static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_gt *gt = &dev_priv->gt;
+ struct intel_uncore *uncore = gt->uncore;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
- gen11_gt_irq_postinstall(&dev_priv->gt);
+ gen11_gt_irq_postinstall(gt);
GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
@@ -3900,8 +3904,8 @@ static void dg1_irq_postinstall(struct drm_i915_private
*dev_priv)
GEN11_DISPLAY_IRQ_ENABLE);
}
- dg1_master_intr_enable(dev_priv->uncore.regs);
- intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_TILE_INTR);
+ dg1_master_intr_enable(uncore->regs);
+ intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
}
static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
--
2.33.0
[Intel-gfx] [PATCH 10/11] drm/i915: Release per-gt resources allocated
From: Venkata Sandeep Dhanalakota
Iterate for_each_gt during release to support multi-tile
devices.
Cc: Tvrtko Ursulin
Signed-off-by: Venkata Sandeep Dhanalakota
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 36b6e6f2cebf..da574f422084 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -381,10 +381,14 @@ static int i915_driver_early_probe(struct
drm_i915_private *dev_priv)
*/
static void i915_driver_late_release(struct drm_i915_private *dev_priv)
{
+ struct intel_gt *gt;
+ unsigned int id;
+
intel_irq_fini(dev_priv);
intel_power_domains_cleanup(dev_priv);
i915_gem_cleanup_early(dev_priv);
- intel_gt_driver_late_release(&dev_priv->gt);
+ for_each_gt(dev_priv, id, gt)
+ intel_gt_driver_late_release(gt);
intel_region_ttm_device_fini(dev_priv);
vlv_suspend_cleanup(dev_priv);
i915_workqueues_cleanup(dev_priv);
--
2.33.0
[Intel-gfx] [PATCH 06/11] drm/i915: Initial support for per-tile uncore
From: Daniele Ceraolo Spurio
Initialization and suspend/resume is replicated per-tile.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++-
drivers/gpu/drm/i915/i915_drv.c | 61 ++---
3 files changed, 51 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 736725411f51..6528d21e68eb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1008,6 +1008,7 @@ void intel_gts_release(struct drm_i915_private *i915)
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p)
{
+ drm_printf(p, "GT %u info:\n", info->id);
drm_printf(p, "available engines: %x\n", info->engine_mask);
intel_sseu_dump(&info->sseu, p);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index fdbd46ff59e0..34fefdfb6661 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -60,12 +60,15 @@ static int i915_capabilities(struct seq_file *m, void *data)
{
struct drm_i915_private *i915 = node_to_i915(m->private);
struct drm_printer p = drm_seq_file_printer(m);
+ struct intel_gt *gt;
+ unsigned int id;
seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
intel_device_info_print_static(INTEL_INFO(i915), &p);
intel_device_info_print_runtime(RUNTIME_INFO(i915), &p);
- intel_gt_info_print(&i915->gt.info, &p);
+ for_each_gt(i915, id, gt)
+ intel_gt_info_print(>->info, &p);
intel_driver_caps_print(&i915->caps, &p);
kernel_param_lock(THIS_MODULE);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 44ccf0078ac4..36b6e6f2cebf 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -406,6 +406,8 @@ static void i915_driver_late_release(struct
drm_i915_private *dev_priv)
*/
static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
{
+ struct intel_gt *gt;
+ unsigned int i, j;
int ret;
if (i915_inject_probe_failure(dev_priv))
@@ -415,26 +417,35 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
if (ret < 0)
return ret;
- ret = intel_uncore_init_mmio(&dev_priv->uncore);
- if (ret)
- return ret;
+ for_each_gt(dev_priv, i, gt) {
+ ret = intel_uncore_init_mmio(gt->uncore);
+ if (ret)
+ goto err_uncore;
+ }
/* Try to make sure MCHBAR is enabled before poking at it */
intel_setup_mchbar(dev_priv);
intel_device_info_runtime_init(dev_priv);
- ret = intel_gt_init_mmio(&dev_priv->gt);
- if (ret)
- goto err_uncore;
+ for_each_gt(dev_priv, j, gt) {
+ ret = intel_gt_init_mmio(gt);
+ if (ret)
+ goto err_mchbar;
+ }
/* As early as possible, scrub existing GPU state before clobbering */
sanitize_gpu(dev_priv);
return 0;
-err_uncore:
+err_mchbar:
intel_teardown_mchbar(dev_priv);
- intel_uncore_fini_mmio(&dev_priv->uncore);
+err_uncore:
+ for_each_gt(dev_priv, j, gt) {
+ if (j >= i)
+ break;
+ intel_uncore_fini_mmio(gt->uncore);
+ }
pci_dev_put(dev_priv->bridge_dev);
return ret;
@@ -446,8 +457,12 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
*/
static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
{
+ struct intel_gt *gt;
+ unsigned int i;
+
intel_teardown_mchbar(dev_priv);
- intel_uncore_fini_mmio(&dev_priv->uncore);
+ for_each_gt(dev_priv, i, gt)
+ intel_uncore_fini_mmio(gt->uncore);
pci_dev_put(dev_priv->bridge_dev);
}
@@ -734,6 +749,8 @@ static void i915_welcome_messages(struct drm_i915_private
*dev_priv)
{
if (drm_debug_enabled(DRM_UT_DRIVER)) {
struct drm_printer p = drm_debug_printer("i915 device info:");
+ struct intel_gt *gt;
+ unsigned int id;
drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s
(subplatform=0x%x) gen=%i\n",
INTEL_DEVID(dev_priv),
@@ -745,7 +762,8 @@ static void i915_welcome_messages(struct drm_i915_private
*dev_priv)
intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
- inte
[Intel-gfx] [PATCH 07/11] drm/i915/xehp: Determine which tile raised an interrupt
From: Paulo Zanoni
The first step of interrupt handling is to read a tile0 register that
tells us in which tile the interrupt happened; we can then we read the
usual interrupt registers from the appropriate tile.
Note that this is just the first step of handling interrupts properly on
multi-tile platforms. Subsequent patches will convert other parts of
the interrupt handling flow.
Cc: Stuart Summers
Signed-off-by: Paulo Zanoni
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 31 ---
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 038a9ec563c1..9f99ad56cde6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2772,37 +2772,38 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
{
struct drm_i915_private * const i915 = arg;
struct intel_gt *gt = &i915->gt;
- void __iomem * const regs = gt->uncore->regs;
+ void __iomem * const t0_regs = gt->uncore->regs;
u32 master_tile_ctl, master_ctl;
- u32 gu_misc_iir;
+ u32 gu_misc_iir = 0;
+ unsigned int i;
if (!intel_irqs_enabled(i915))
return IRQ_NONE;
- master_tile_ctl = dg1_master_intr_disable(regs);
+ master_tile_ctl = dg1_master_intr_disable(t0_regs);
if (!master_tile_ctl) {
- dg1_master_intr_enable(regs);
+ dg1_master_intr_enable(t0_regs);
return IRQ_NONE;
}
- /* FIXME: we only support tile 0 for now. */
- if (master_tile_ctl & DG1_MSTR_TILE(0)) {
+ for_each_gt(i915, i, gt) {
+ void __iomem *const regs = gt->uncore->regs;
+
+ if ((master_tile_ctl & DG1_MSTR_TILE(i)) == 0)
+ continue;
+
master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl);
- } else {
- DRM_ERROR("Tile not supported: 0x%08x\n", master_tile_ctl);
- dg1_master_intr_enable(regs);
- return IRQ_NONE;
- }
- gen11_gt_irq_handler(gt, master_ctl);
+ gen11_gt_irq_handler(gt, master_ctl);
+
+ gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
+ }
if (master_ctl & GEN11_DISPLAY_IRQ)
gen11_display_irq_handler(i915);
- gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
-
- dg1_master_intr_enable(regs);
+ dg1_master_intr_enable(t0_regs);
gen11_gu_misc_irq_handler(gt, gu_misc_iir);
--
2.33.0
[Intel-gfx] [PATCH 09/11] drm/i915/guc: Update CT debug macro for multi-tile
From: Michal Wajdeczko
Update CT debug macros by including tile ID in all messages.
Cc: Michał Winiarski
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 0a3504bc0b61..013ad85cc7f6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -33,15 +33,15 @@ static inline struct drm_device *ct_to_drm(struct
intel_guc_ct *ct)
}
#define CT_ERROR(_ct, _fmt, ...) \
- drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+ drm_err(ct_to_drm(_ct), "CT%u: " _fmt, ct_to_gt(_ct)->info.id,
##__VA_ARGS__)
#ifdef CONFIG_DRM_I915_DEBUG_GUC
#define CT_DEBUG(_ct, _fmt, ...) \
- drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+ drm_dbg(ct_to_drm(_ct), "CT%u: " _fmt, ct_to_gt(_ct)->info.id,
##__VA_ARGS__)
#else
#define CT_DEBUG(...) do { } while (0)
#endif
#define CT_PROBE_ERROR(_ct, _fmt, ...) \
- i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
+ i915_probe_error(ct_to_i915(ct), "CT%u: " _fmt, ct_to_gt(_ct)->info.id,
##__VA_ARGS__)
/**
* DOC: CTB Blob
--
2.33.0
[Intel-gfx] [PATCH 11/11] drm/i915/xehpsdv: Initialize multi-tiles
From: Tvrtko Ursulin
Check how many extra GT tiles are available on the system and setup
register access for all of them. We can detect how may GT tiles are
available by reading a register on the root tile. The same register
returns the tile ID on all tiles.
Bspec: 33407
Original-author: Abdiel Janulgue
Signed-off-by: Tvrtko Ursulin
Cc: Matthew Auld
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Paulo Zanoni
Signed-off-by: Paulo Zanoni
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_gt.c | 66 +++-
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 4 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
5 files changed, 74 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 6528d21e68eb..d7efaef9ade7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -943,6 +943,17 @@ tile_setup(struct intel_gt *gt, unsigned int id,
phys_addr_t phys_addr)
if (ret)
return ret;
+ /* Which tile am I? default to zero on single tile systems */
+ if (HAS_REMOTE_TILES(i915)) {
+ u32 instance =
+ __raw_uncore_read32(gt->uncore, XEHPSDV_MTCFG_ADDR) &
+ TILE_NUMBER;
+
+ if (GEM_WARN_ON(instance != id))
+ return -ENXIO;
+ }
+
+ gt->info.id = id;
gt->phys_addr = phys_addr;
return 0;
@@ -958,11 +969,25 @@ static void tile_cleanup(struct intel_gt *gt)
}
}
+static unsigned int tile_count(struct drm_i915_private *i915)
+{
+ u32 mtcfg;
+
+ /*
+* We use raw MMIO reads at this point since the
+* MMIO vfuncs are not setup yet
+*/
+ mtcfg = __raw_uncore_read32(&i915->uncore, XEHPSDV_MTCFG_ADDR);
+ return REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
+}
+
int intel_probe_gts(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct intel_gt *gt;
phys_addr_t phys_addr;
unsigned int mmio_bar;
+ unsigned int i, tiles;
int ret;
mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
@@ -975,8 +1000,47 @@ int intel_probe_gts(struct drm_i915_private *i915)
i915->gts[0] = &i915->gt;
- /* TODO: add more tiles */
+ if (!HAS_REMOTE_TILES(i915))
+ return 0;
+
+ /* Setup other tiles */
+ tiles = tile_count(i915);
+ drm_dbg(&i915->drm, "Tile count: %u\n", tiles);
+
+ if (GEM_WARN_ON(tiles > I915_MAX_TILES))
+ return -EINVAL;
+
+ /* For multi-tile platforms, size of GTTMMADR is 16MB per tile */
+ if (GEM_WARN_ON(pci_resource_len(pdev, 0) / tiles != SZ_16M))
+ return -EINVAL;
+
+ for (i = 1; i < tiles; i++) {
+ gt = kzalloc(sizeof(*gt), GFP_KERNEL);
+ if (!gt) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ ret = tile_setup(gt, i, phys_addr + SZ_16M * i);
+ if (ret)
+ goto err;
+
+ i915->gts[i] = gt;
+ }
+
+ i915->remote_tiles = tiles - 1;
+
return 0;
+
+err:
+ drm_err(&i915->drm, "Failed to initialize tile %u! (%d)\n", i, ret);
+
+ for_each_gt(i915, i, gt) {
+ tile_cleanup(gt);
+ i915->gts[i] = NULL;
+ }
+
+ return ret;
}
int intel_gt_tiles_init(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3a26a21ffb3a..342c42e5aa96 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -865,6 +865,8 @@ struct drm_i915_private {
*/
resource_size_t stolen_usable_size; /* Total size minus reserved
ranges */
+ unsigned int remote_tiles;
+
struct intel_uncore uncore;
struct intel_uncore_mmio_debug mmio_debug;
@@ -1724,6 +1726,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
+#define HAS_REMOTE_TILES(dev_priv) (INTEL_INFO(dev_priv)->has_remote_tiles)
#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 169837de395d..95870c2e366e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1015,6 +1015,7 @@ static const struct intel_device_info xehpsdv_info = {
DGFX_FEATURES,
PLATFORM(INTEL_XEHPSDV),
.display = { },
+ .has_remote_tiles = 1,
.pipe_mask = 0,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
diff --git
[Intel-gfx] [PATCH 03/11] drm/i915: Restructure probe to handle multi-tile platforms
On a multi-tile platform, each tile has its own registers + GGTT space,
and BAR 0 is extended to cover all of them. Upcoming patches will start
exposing the tiles as multiple GTs within a single PCI device. In
preparation for supporting such setups, restructure the driver's probe
code a bit.
Only the primary/root tile is initialized for now; the other tiles will
be detected and plugged in by future patches once the necessary
infrastructure is in place to handle them.
Original-author: Abdiel Janulgue
Cc: Daniele Ceraolo Spurio
Cc: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 45
drivers/gpu/drm/i915/gt/intel_gt.h | 3 ++
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 9 -
drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 +++
drivers/gpu/drm/i915/i915_drv.c | 20 +--
drivers/gpu/drm/i915/intel_uncore.c | 12 +++
drivers/gpu/drm/i915/intel_uncore.h | 3 +-
7 files changed, 76 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 1cb1948ac959..f4bea1f1de77 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -900,6 +900,51 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt,
i915_reg_t reg)
return intel_uncore_read_fw(gt->uncore, reg);
}
+static int
+tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t phys_addr)
+{
+ int ret;
+
+ intel_uncore_init_early(gt->uncore, gt->i915);
+
+ ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
+ if (ret)
+ return ret;
+
+ gt->phys_addr = phys_addr;
+
+ return 0;
+}
+
+static void tile_cleanup(struct intel_gt *gt)
+{
+ intel_uncore_cleanup_mmio(gt->uncore);
+}
+
+int intel_probe_gts(struct drm_i915_private *i915)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ phys_addr_t phys_addr;
+ unsigned int mmio_bar;
+ int ret;
+
+ mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
+ phys_addr = pci_resource_start(pdev, mmio_bar);
+
+ /* We always have at least one primary GT on any device */
+ ret = tile_setup(&i915->gt, 0, phys_addr);
+ if (ret)
+ return ret;
+
+ /* TODO: add more tiles */
+ return 0;
+}
+
+void intel_gts_release(struct drm_i915_private *i915)
+{
+ tile_cleanup(&i915->gt);
+}
+
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 74e771871a9b..f4f35a70cbe4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -85,6 +85,9 @@ static inline bool intel_gt_needs_read_steering(struct
intel_gt *gt,
u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg);
+int intel_probe_gts(struct drm_i915_private *i915);
+void intel_gts_release(struct drm_i915_private *i915);
+
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 524eaf678790..76f498edb0d5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -126,7 +126,14 @@ static const struct intel_wakeref_ops wf_ops = {
void intel_gt_pm_init_early(struct intel_gt *gt)
{
- intel_wakeref_init(>->wakeref, gt->uncore->rpm, &wf_ops);
+ /*
+* We access the runtime_pm structure via gt->i915 here rather than
+* gt->uncore as we do elsewhere in the file because gt->uncore is not
+* yet initialized for all tiles at this point in the driver startup.
+* runtime_pm is per-device rather than per-tile, so this is still the
+* correct structure.
+*/
+ intel_wakeref_init(>->wakeref, >->i915->runtime_pm, &wf_ops);
seqcount_mutex_init(>->stats.lock, >->wakeref.mutex);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 14216cc471b1..66143316d92e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -180,6 +180,11 @@ struct intel_gt {
const struct intel_mmio_range *steering_table[NUM_STEERING_TYPES];
+ /*
+* Base of per-tile GTTMMADR where we can derive the MMIO and the GGTT.
+*/
+ phys_addr_t phys_addr;
+
struct intel_gt_info {
intel_engine_mask_t engine_mask;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7f96d26c012a..51234fd1349b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/dr
[Intel-gfx] [PATCH 08/11] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware
From: Paulo Zanoni
Loop through all the tiles when initializing and resetting interrupts.
Signed-off-by: Paulo Zanoni
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 28 ++--
1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9f99ad56cde6..e788e283d4a8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3190,14 +3190,19 @@ static void dg1_irq_reset(struct drm_i915_private
*dev_priv)
{
struct intel_gt *gt = &dev_priv->gt;
struct intel_uncore *uncore = gt->uncore;
+ unsigned int i;
dg1_master_intr_disable(dev_priv->uncore.regs);
- gen11_gt_irq_reset(gt);
- gen11_display_irq_reset(dev_priv);
+ for_each_gt(dev_priv, i, gt) {
+ gen11_gt_irq_reset(gt);
- GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
- GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+ uncore = gt->uncore;
+ GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
+ GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+ }
+
+ gen11_display_irq_reset(dev_priv);
}
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -3890,13 +3895,16 @@ static void gen11_irq_postinstall(struct
drm_i915_private *dev_priv)
static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_gt *gt = &dev_priv->gt;
- struct intel_uncore *uncore = gt->uncore;
+ struct intel_gt *gt;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
+ unsigned int i;
- gen11_gt_irq_postinstall(gt);
+ for_each_gt(dev_priv, i, gt) {
+ gen11_gt_irq_postinstall(gt);
- GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
+ GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked,
+ gu_misc_masked);
+ }
if (HAS_DISPLAY(dev_priv)) {
icp_irq_postinstall(dev_priv);
@@ -3905,8 +3913,8 @@ static void dg1_irq_postinstall(struct drm_i915_private
*dev_priv)
GEN11_DISPLAY_IRQ_ENABLE);
}
- dg1_master_intr_enable(uncore->regs);
- intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
+ dg1_master_intr_enable(dev_priv->gt.uncore->regs);
+ intel_uncore_posting_read(dev_priv->gt.uncore, DG1_MSTR_TILE_INTR);
}
static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
--
2.33.0
[Intel-gfx] [PATCH v2 11/11] drm/i915/xehpsdv: Initialize multi-tiles
From: Tvrtko Ursulin
Check how many extra GT tiles are available on the system and setup
register access for all of them. We can detect how may GT tiles are
available by reading a register on the root tile. The same register
returns the tile ID on all tiles.
v2:
- Include some additional refactor that didn't get squashed in properly
on v1.
Bspec: 33407
Original-author: Abdiel Janulgue
Signed-off-by: Tvrtko Ursulin
Cc: Matthew Auld
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Paulo Zanoni
Cc: Andi Shyti
Signed-off-by: Paulo Zanoni
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 83 +--
drivers/gpu/drm/i915/gt/intel_gt.h| 4 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 7 +-
drivers/gpu/drm/i915/i915_pci.c | 40 +--
drivers/gpu/drm/i915/i915_reg.h | 4 ++
drivers/gpu/drm/i915/intel_device_info.h | 15
8 files changed, 145 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 2ae57e4656a3..1d9fcf9572ca 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -525,7 +525,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt
*gt)
u16 vdbox_mask;
u16 vebox_mask;
- info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
+ GEM_BUG_ON(!info->engine_mask);
if (GRAPHICS_VER(i915) < 11)
return info->engine_mask;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 6528d21e68eb..0879e30ace7c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -912,14 +912,17 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt,
i915_reg_t reg)
return intel_uncore_read_fw(gt->uncore, reg);
}
-static int
-tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t phys_addr)
+int intel_tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t
phys_addr)
{
struct drm_i915_private *i915 = gt->i915;
struct intel_uncore *uncore;
struct intel_uncore_mmio_debug *mmio_debug;
int ret;
+ /* For Modern GENs size of GTTMMADR is 16MB (for each tile) */
+ if (GEM_WARN_ON(pci_resource_len(to_pci_dev(i915->drm.dev), 0) < (id +
1) * SZ_16M))
+ return -EINVAL;
+
if (id) {
uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
if (!uncore)
@@ -943,6 +946,16 @@ tile_setup(struct intel_gt *gt, unsigned int id,
phys_addr_t phys_addr)
if (ret)
return ret;
+ /* Which tile am I? default to zero on single tile systems */
+ if (HAS_REMOTE_TILES(i915)) {
+ u32 instance =
+ __raw_uncore_read32(gt->uncore, XEHPSDV_MTCFG_ADDR) &
+ TILE_NUMBER;
+
+ if (GEM_WARN_ON(instance != id))
+ return -ENXIO;
+ }
+
gt->phys_addr = phys_addr;
return 0;
@@ -958,25 +971,87 @@ static void tile_cleanup(struct intel_gt *gt)
}
}
+static unsigned int tile_count(struct drm_i915_private *i915)
+{
+ u32 mtcfg;
+
+ /*
+* We use raw MMIO reads at this point since the
+* MMIO vfuncs are not setup yet
+*/
+ mtcfg = __raw_uncore_read32(&i915->uncore, XEHPSDV_MTCFG_ADDR);
+ return REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
+}
+
int intel_probe_gts(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ const struct intel_gt_definition *gtdef;
+ struct intel_gt *gt;
phys_addr_t phys_addr;
unsigned int mmio_bar;
+ unsigned int i, tiles;
int ret;
mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
phys_addr = pci_resource_start(pdev, mmio_bar);
/* We always have at least one primary GT on any device */
- ret = tile_setup(&i915->gt, 0, phys_addr);
+ gt = &i915->gt;
+ gt->name = "Primary GT";
+ gt->info.engine_mask = INTEL_INFO(i915)->platform_engine_mask;
+
+ drm_dbg(&i915->drm, "Setting up %s %u\n", gt->name, gt->info.id);
+ ret = intel_tile_setup(gt, 0, phys_addr);
if (ret)
return ret;
i915->gts[0] = &i915->gt;
- /* TODO: add more tiles */
+ tiles = tile_count(i915);
+ drm_dbg(&i915->drm, "Tile count: %u\n", tiles);
+
+ for (gtdef = INTEL_INFO(i915)->extra_gts, i = 1;
+gtdef && i < tiles;
+gtdef++, i++) {
+ if (GEM_WARN_ON(i >= I915_MAX_GTS)) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ gt = kzalloc(sizeof(*gt), GFP_KERNEL);
+ if (!gt) {
Re: [Intel-gfx] [PATCH 07/11] drm/i915/xehp: Determine which tile raised an interrupt
On Fri, Oct 08, 2021 at 02:56:31PM -0700, Matt Roper wrote:
> From: Paulo Zanoni
>
> The first step of interrupt handling is to read a tile0 register that
> tells us in which tile the interrupt happened; we can then we read the
> usual interrupt registers from the appropriate tile.
>
> Note that this is just the first step of handling interrupts properly on
> multi-tile platforms. Subsequent patches will convert other parts of
> the interrupt handling flow.
>
> Cc: Stuart Summers
> Signed-off-by: Paulo Zanoni
> Signed-off-by: Tvrtko Ursulin
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_irq.c | 31 ---
> 1 file changed, 16 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 038a9ec563c1..9f99ad56cde6 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2772,37 +2772,38 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> {
> struct drm_i915_private * const i915 = arg;
> struct intel_gt *gt = &i915->gt;
> - void __iomem * const regs = gt->uncore->regs;
> + void __iomem * const t0_regs = gt->uncore->regs;
> u32 master_tile_ctl, master_ctl;
> - u32 gu_misc_iir;
> + u32 gu_misc_iir = 0;
> + unsigned int i;
>
> if (!intel_irqs_enabled(i915))
> return IRQ_NONE;
>
> - master_tile_ctl = dg1_master_intr_disable(regs);
> + master_tile_ctl = dg1_master_intr_disable(t0_regs);
> if (!master_tile_ctl) {
> - dg1_master_intr_enable(regs);
> + dg1_master_intr_enable(t0_regs);
> return IRQ_NONE;
> }
>
> - /* FIXME: we only support tile 0 for now. */
> - if (master_tile_ctl & DG1_MSTR_TILE(0)) {
> + for_each_gt(i915, i, gt) {
> + void __iomem *const regs = gt->uncore->regs;
> +
> + if ((master_tile_ctl & DG1_MSTR_TILE(i)) == 0)
> + continue;
> +
> master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
> raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl);
> - } else {
> - DRM_ERROR("Tile not supported: 0x%08x\n", master_tile_ctl);
> - dg1_master_intr_enable(regs);
> - return IRQ_NONE;
> - }
>
> - gen11_gt_irq_handler(gt, master_ctl);
> + gen11_gt_irq_handler(gt, master_ctl);
> +
> + gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
Hmm, I missed it before sending the series, but this doesn't look right.
We ack every tile's gu_misc_irq separately, but...
> + }
>
> if (master_ctl & GEN11_DISPLAY_IRQ)
> gen11_display_irq_handler(i915);
>
> - gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
> -
> - dg1_master_intr_enable(regs);
> + dg1_master_intr_enable(t0_regs);
>
> gen11_gu_misc_irq_handler(gt, gu_misc_iir);
...only handle the value from the final tile? Looks like this was
intended to move inside the loop as well.
Matt
>
> --
> 2.33.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix read of memory frequency
On Fri, Oct 08, 2021 at 01:58:55PM -0700, José Roberto de Souza wrote:
> All display 9 and display 10 platforms has only 4 bits for the memory
> frequency but display 11 platforms it changes to 8 bits.
>
> Display 9 platforms has another register in bits 7:4 that prevents us
> to have a single mask.
> Also adding new mask with the current name in CRWebViewer, not
> sure why current mask is named like this.
>
> Fixes: f8112cb9574b ("drm/i915/gen11+: Only load DRAM information from pcode")
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_dram.c | 7 +--
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a897f4abea0c3..041f7dc9e0d94 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11148,6 +11148,7 @@ enum skl_power_gate {
> #define SKL_MEMORY_FREQ_MULTIPLIER_HZ2
> #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU_MMIO(MCHBAR_MIRROR_BASE_SNB +
> 0x5E04)
> #define SKL_REQ_DATA_MASK (0xF << 0)
> +#define ICL_FREQ_MASK (0xFF << 0)
We might as well take this opportunity to switch over to REG_GENMASK
notation while we're here.
> #define DG1_GEAR_TYPE REG_BIT(16)
>
> #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN
> _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
> diff --git a/drivers/gpu/drm/i915/intel_dram.c
> b/drivers/gpu/drm/i915/intel_dram.c
> index 30a0cab5eff46..558589b1202d6 100644
> --- a/drivers/gpu/drm/i915/intel_dram.c
> +++ b/drivers/gpu/drm/i915/intel_dram.c
> @@ -257,8 +257,11 @@ skl_get_dram_info(struct drm_i915_private *i915)
>
> val = intel_uncore_read(&i915->uncore,
> SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
> - mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
> - SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
> + if (DISPLAY_VER(i915) == 11)
> + val &= ICL_FREQ_MASK;
> + else
> + val &= SKL_REQ_DATA_MASK;
> + mem_freq_khz = DIV_ROUND_UP(val * SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
I'm not sure SKL_MEMORY_FREQ_MULTIPLIER_HZ is correct anymore either.
If I'm reading the register description correctly, it appears the value
is now given in units of 133.33 MHz instead of the old 266.66.
Matt
>
> if (dram_info->num_channels * mem_freq_khz == 0) {
> drm_info(&i915->drm,
> --
> 2.33.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix read of memory frequency
On Tue, Oct 12, 2021 at 02:23:27PM -0700, Souza, Jose wrote:
> On Tue, 2021-10-12 at 14:20 -0700, Matt Roper wrote:
> > On Fri, Oct 08, 2021 at 01:58:55PM -0700, José Roberto de Souza wrote:
> > > All display 9 and display 10 platforms has only 4 bits for the memory
> > > frequency but display 11 platforms it changes to 8 bits.
> > >
> > > Display 9 platforms has another register in bits 7:4 that prevents us
> > > to have a single mask.
> > > Also adding new mask with the current name in CRWebViewer, not
> > > sure why current mask is named like this.
> > >
> > > Fixes: f8112cb9574b ("drm/i915/gen11+: Only load DRAM information from
> > > pcode")
> > > Signed-off-by: José Roberto de Souza
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > drivers/gpu/drm/i915/intel_dram.c | 7 +--
> > > 2 files changed, 6 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index a897f4abea0c3..041f7dc9e0d94 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -11148,6 +11148,7 @@ enum skl_power_gate {
> > > #define SKL_MEMORY_FREQ_MULTIPLIER_HZ2
> > > #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU
> > > _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
> > > #define SKL_REQ_DATA_MASK (0xF << 0)
> > > +#define ICL_FREQ_MASK (0xFF << 0)
> >
> > We might as well take this opportunity to switch over to REG_GENMASK
> > notation while we're here.
>
> Will do.
>
> >
> > > #define DG1_GEAR_TYPE REG_BIT(16)
> > >
> > > #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN
> > > _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
> > > diff --git a/drivers/gpu/drm/i915/intel_dram.c
> > > b/drivers/gpu/drm/i915/intel_dram.c
> > > index 30a0cab5eff46..558589b1202d6 100644
> > > --- a/drivers/gpu/drm/i915/intel_dram.c
> > > +++ b/drivers/gpu/drm/i915/intel_dram.c
> > > @@ -257,8 +257,11 @@ skl_get_dram_info(struct drm_i915_private *i915)
> > >
> > > val = intel_uncore_read(&i915->uncore,
> > > SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
> > > - mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
> > > - SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
> > > + if (DISPLAY_VER(i915) == 11)
> > > + val &= ICL_FREQ_MASK;
> > > + else
> > > + val &= SKL_REQ_DATA_MASK;
> > > + mem_freq_khz = DIV_ROUND_UP(val * SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
> >
> > I'm not sure SKL_MEMORY_FREQ_MULTIPLIER_HZ is correct anymore either.
> > If I'm reading the register description correctly, it appears the value
> > is now given in units of 133.33 MHz instead of the old 266.66.
>
> Thought about that but as the calculated memory frequency here is not used
> for anything besides check if is not zero, I left as is.
Hmm, good point. Although in that case do we really need to read this
register at all? It seems like after
commit f0b29707baa9e6f3d7b90090fcce62d2f1023fa1
Author: José Roberto de Souza
AuthorDate: Thu Jan 28 08:43:10 2021 -0800
Commit: José Roberto de Souza
CommitDate: Fri Jan 29 05:50:48 2021 -0800
drm/i915: Nuke not needed members of dram_info
we're not calculating bandwidth_kbps, so checking if the register is
valid doesn't really gain us anything and could just be removed? A
simple check for
if (dram_info->num_channels == 0) {
...error...
}
might be sufficient?
Matt
>
> >
> >
> > Matt
> >
> > >
> > > if (dram_info->num_channels * mem_freq_khz == 0) {
> > > drm_info(&i915->drm,
> > > --
> > > 2.33.0
> > >
> >
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
Re: [Intel-gfx] [PATCH] drm/i915: Stop using I915_TILING_* in client blit selftest
On Fri, Oct 08, 2021 at 12:49:57PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 30, 2021 at 05:58:16PM -0700, Matt Roper wrote:
> > The I915_TILING_* definitions in the uapi header are intended solely for
> > tiling modes that are visible to the old de-tiling fence ioctls. Since
> > modern hardware does not support de-tiling fences, we should not add new
> > definitions for new tiling types going forward. However we do want the
> > client blit selftest to eventually cover other new tiling modes (such as
> > Tile4), so switch it to using its own enum of tiling modes.
> >
> > Cc: Ville Syrjälä
> > Cc: Stanislav Lisovskiy
> > Signed-off-by: Matt Roper
> > ---
> > .../i915/gem/selftests/i915_gem_client_blt.c | 29 ---
> > include/uapi/drm/i915_drm.h | 6
> > 2 files changed, 24 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> > b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> > index ecbcbb86ae1e..8402ed925a69 100644
> > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> > @@ -17,13 +17,20 @@
> > #include "huge_gem_object.h"
> > #include "mock_context.h"
> >
> > +enum client_tiling {
> > + CLIENT_TILING_LINEAR,
> > + CLIENT_TILING_X,
> > + CLIENT_TILING_Y,
> > + CLIENT_NUM_TILING_TYPES
> > +};
> > +
> > #define WIDTH 512
> > #define HEIGHT 32
> >
> > struct blit_buffer {
> > struct i915_vma *vma;
> > u32 start_val;
> > - u32 tiling;
> > + enum client_tiling tiling;
> > };
> >
> > struct tiled_blits {
> > @@ -53,9 +60,9 @@ static int prepare_blit(const struct tiled_blits *t,
> > *cs++ = MI_LOAD_REGISTER_IMM(1);
> > *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
> > cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
> > - if (src->tiling == I915_TILING_Y)
> > + if (src->tiling == CLIENT_TILING_Y)
> > cmd |= BCS_SRC_Y;
> > - if (dst->tiling == I915_TILING_Y)
> > + if (dst->tiling == CLIENT_TILING_Y)
> > cmd |= BCS_DST_Y;
> > *cs++ = cmd;
> >
> > @@ -172,7 +179,7 @@ static int tiled_blits_create_buffers(struct
> > tiled_blits *t,
> >
> > t->buffers[i].vma = vma;
> > t->buffers[i].tiling =
> > - i915_prandom_u32_max_state(I915_TILING_Y + 1, prng);
> > + i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng);
> > }
> >
> > return 0;
> > @@ -197,17 +204,17 @@ static u64 swizzle_bit(unsigned int bit, u64 offset)
> > static u64 tiled_offset(const struct intel_gt *gt,
> > u64 v,
> > unsigned int stride,
> > - unsigned int tiling)
> > + enum client_tiling tiling)
> > {
> > unsigned int swizzle;
> > u64 x, y;
> >
> > - if (tiling == I915_TILING_NONE)
> > + if (tiling == CLIENT_TILING_LINEAR)
> > return v;
> >
> > y = div64_u64_rem(v, stride, &x);
> >
> > - if (tiling == I915_TILING_X) {
> > + if (tiling == CLIENT_TILING_X) {
> > v = div64_u64_rem(y, 8, &y) * stride * 8;
> > v += y * 512;
> > v += div64_u64_rem(x, 512, &x) << 12;
> > @@ -244,12 +251,12 @@ static u64 tiled_offset(const struct intel_gt *gt,
> > return v;
> > }
> >
> > -static const char *repr_tiling(int tiling)
> > +static const char *repr_tiling(enum client_tiling tiling)
> > {
> > switch (tiling) {
> > - case I915_TILING_NONE: return "linear";
> > - case I915_TILING_X: return "X";
> > - case I915_TILING_Y: return "Y";
> > + case CLIENT_TILING_LINEAR: return "linear";
> > + case CLIENT_TILING_X: return "X";
> > + case CLIENT_TILING_Y: return "Y";
> > default: return "unknown";
> > }
> > }
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index bde5860b3686..00311a63068e 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -1522,6 +1522,12 @@ struct drm_i915_gem_caching {
> > #define I915_TILING_NONE 0
> > #define I915_TILING_X 1
> > #define I915_TILING_Y 2
> > +/
[Intel-gfx] [PATCH] drm/i915/uapi: Add comment clarifying purpose of I915_TILING_* values
The I915_TILING_* values in our uapi header are intended solely for use
with the old get_tiling/set_tiling ioctls that operate on hardware
de-tiling fences; all other uapi communication about tiling types is
done via framebuffer modifiers rather than with these old values.
On newer Intel platforms detiling fences no longer exist so the old
get_tiling/set_tiling ioctls are no longer usable and will always return
-EOPNOTSUPP. This means there's no reason to add new tiling types (such
as the Tile4 format introduced by Xe_HP) to the uapi header here. Any
kernel-internal code that needs to represent tiling format should either
rely on framebuffer modifiers (as the display code does) or use some
kind of non-uapi enum (as the GEM blt selftest now does).
References: https://patchwork.freedesktop.org/patch/456656/?series=95308
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
include/uapi/drm/i915_drm.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index aa2a7eccfb94..9b8e61163c39 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1522,6 +1522,12 @@ struct drm_i915_gem_caching {
#define I915_TILING_NONE 0
#define I915_TILING_X 1
#define I915_TILING_Y 2
+/*
+ * Do not add new tiling types here. The I915_TILING_* values are for
+ * de-tiling fence registers that no longer exist on modern platforms.
Although
+ * the hardware may support new types of tiling in general (e.g., Tile4), we
+ * do not need to add them to the uapi that is specific to now-defunct ioctls.
+ */
#define I915_TILING_LAST I915_TILING_Y
#define I915_BIT_6_SWIZZLE_NONE0
--
2.33.0
Re: [Intel-gfx] [PATCH] drm/i915: Remove memory frequency calculation
On Tue, Oct 12, 2021 at 05:24:55PM -0700, José Roberto de Souza wrote:
> This memory frequency calculated is only used to check if it is zero,
> what is not useful as it will never actually be zero.
>
> Also the calculation is wrong, we should be checking other bit to
> select the appropriate frequency multiplier while this code is stuck
> with a fixed multiplier.
>
> So here dropping it as whole.
I think we can do similar cleanup in bxt_get_dram_info() too. The value
of BXT_P_CR_MC_BIOS_REQ_0_0_0 that we read is used to obtain
mem_freq_khz and dram_channels/num_active_channels, but none of those
variables are ever used for anything except a needless zero-check.
Matt
> Cc: Yakui Zhao
> Cc: Matt Roper
> Fixes: f8112cb9574b ("drm/i915/gen11+: Only load DRAM information from pcode")
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 --
> drivers/gpu/drm/i915/intel_dram.c | 12
> 2 files changed, 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a897f4abea0c3..03b6c505249dc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11145,9 +11145,7 @@ enum skl_power_gate {
> #define BXT_DRAM_TYPE_LPDDR4(0x2 << 22)
> #define BXT_DRAM_TYPE_DDR4 (0x4 << 22)
>
> -#define SKL_MEMORY_FREQ_MULTIPLIER_HZ2
> #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU_MMIO(MCHBAR_MIRROR_BASE_SNB +
> 0x5E04)
> -#define SKL_REQ_DATA_MASK (0xF << 0)
> #define DG1_GEAR_TYPE REG_BIT(16)
>
> #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN
> _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
> diff --git a/drivers/gpu/drm/i915/intel_dram.c
> b/drivers/gpu/drm/i915/intel_dram.c
> index 30a0cab5eff46..31933b1e7277b 100644
> --- a/drivers/gpu/drm/i915/intel_dram.c
> +++ b/drivers/gpu/drm/i915/intel_dram.c
> @@ -244,7 +244,6 @@ static int
> skl_get_dram_info(struct drm_i915_private *i915)
> {
> struct dram_info *dram_info = &i915->dram_info;
> - u32 mem_freq_khz, val;
> int ret;
>
> dram_info->type = skl_get_dram_type(i915);
> @@ -255,17 +254,6 @@ skl_get_dram_info(struct drm_i915_private *i915)
> if (ret)
> return ret;
>
> - val = intel_uncore_read(&i915->uncore,
> - SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
> - mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
> - SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
> -
> - if (dram_info->num_channels * mem_freq_khz == 0) {
> - drm_info(&i915->drm,
> - "Couldn't get system memory bandwidth\n");
> - return -EINVAL;
> - }
> -
> return 0;
> }
>
> --
> 2.33.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
Re: [Intel-gfx] [PATCH v2] drm/i915: Remove memory frequency calculation
On Tue, Oct 12, 2021 at 06:00:46PM -0700, José Roberto de Souza wrote:
> This memory frequency calculated is only used to check if it is zero,
> what is not useful as it will never actually be zero.
>
> Also the calculation is wrong, we should be checking other bit to
> select the appropriate frequency multiplier while this code is stuck
> with a fixed multiplier.
>
> So here dropping it as whole.
>
> v2:
> - Also remove memory frequency calculation for gen9 LP platforms
>
> Cc: Yakui Zhao
> Cc: Matt Roper
> Fixes: f8112cb9574b ("drm/i915/gen11+: Only load DRAM information from pcode")
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8
> drivers/gpu/drm/i915/intel_dram.c | 30 ++
> 2 files changed, 2 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a897f4abea0c3..8825f7ac477b6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11109,12 +11109,6 @@ enum skl_power_gate {
> #define DC_STATE_DEBUG_MASK_CORES (1 << 0)
> #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
>
> -#define BXT_P_CR_MC_BIOS_REQ_0_0_0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)
> -#define BXT_REQ_DATA_MASK 0x3F
> -#define BXT_DRAM_CHANNEL_ACTIVE_SHIFT 12
> -#define BXT_DRAM_CHANNEL_ACTIVE_MASK(0xF << 12)
> -#define BXT_MEMORY_FREQ_MULTIPLIER_HZ 1
> -
> #define BXT_D_CR_DRP0_DUNIT8 0x1000
> #define BXT_D_CR_DRP0_DUNIT9 0x1200
> #define BXT_D_CR_DRP0_DUNIT_START 8
> @@ -11145,9 +11139,7 @@ enum skl_power_gate {
> #define BXT_DRAM_TYPE_LPDDR4(0x2 << 22)
> #define BXT_DRAM_TYPE_DDR4 (0x4 << 22)
>
> -#define SKL_MEMORY_FREQ_MULTIPLIER_HZ2
> #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU_MMIO(MCHBAR_MIRROR_BASE_SNB +
> 0x5E04)
> -#define SKL_REQ_DATA_MASK (0xF << 0)
> #define DG1_GEAR_TYPE REG_BIT(16)
>
> #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN
> _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
> diff --git a/drivers/gpu/drm/i915/intel_dram.c
> b/drivers/gpu/drm/i915/intel_dram.c
> index 30a0cab5eff46..0adadfd9528aa 100644
> --- a/drivers/gpu/drm/i915/intel_dram.c
> +++ b/drivers/gpu/drm/i915/intel_dram.c
> @@ -244,7 +244,6 @@ static int
> skl_get_dram_info(struct drm_i915_private *i915)
> {
> struct dram_info *dram_info = &i915->dram_info;
> - u32 mem_freq_khz, val;
> int ret;
>
> dram_info->type = skl_get_dram_type(i915);
> @@ -255,17 +254,6 @@ skl_get_dram_info(struct drm_i915_private *i915)
> if (ret)
> return ret;
>
> - val = intel_uncore_read(&i915->uncore,
> - SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
> - mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
> - SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
> -
> - if (dram_info->num_channels * mem_freq_khz == 0) {
> - drm_info(&i915->drm,
> - "Couldn't get system memory bandwidth\n");
> - return -EINVAL;
> - }
> -
> return 0;
> }
>
> @@ -350,24 +338,10 @@ static void bxt_get_dimm_info(struct dram_dimm_info
> *dimm, u32 val)
> static int bxt_get_dram_info(struct drm_i915_private *i915)
> {
> struct dram_info *dram_info = &i915->dram_info;
> - u32 dram_channels;
> - u32 mem_freq_khz, val;
> - u8 num_active_channels, valid_ranks = 0;
> + u32 val;
> + u8 valid_ranks = 0;
> int i;
>
> - val = intel_uncore_read(&i915->uncore, BXT_P_CR_MC_BIOS_REQ_0_0_0);
> - mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
> - BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
> -
> - dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
> - num_active_channels = hweight32(dram_channels);
> -
> - if (mem_freq_khz * num_active_channels == 0) {
> - drm_info(&i915->drm,
> - "Couldn't get system memory bandwidth\n");
> - return -EINVAL;
> - }
> -
> /*
>* Now read each DUNIT8/9/10/11 to check the rank of each dimms.
>*/
> --
> 2.33.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
Re: [Intel-gfx] [PATCH 08/11] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware
On Thu, Oct 28, 2021 at 06:30:09PM +0200, Andi Shyti wrote: > Hi Paulo and Matt, > > [...] > > > @@ -3190,14 +3190,19 @@ static void dg1_irq_reset(struct drm_i915_private > > *dev_priv) > > mmmhhh... bad naming :/ Even though dg1 wasn't a multi-tile platform, it was the platform that introduced the singleton "master tile interrupt" register that is responsible for telling us which tile(s) had interrupts; we then proceed to read the per-tile master register to find out what those interrupts are. So I think the name is accurate since the hardware introduced the extra level of indirection, and we do need to use this handler on DG1 (we'll just never have more than a single GT to loop over in that case). > > [...] > > > - dg1_master_intr_enable(uncore->regs); > > - intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR); > > + dg1_master_intr_enable(dev_priv->gt.uncore->regs); > > + intel_uncore_posting_read(dev_priv->gt.uncore, DG1_MSTR_TILE_INTR); > > I guess this should also go under a for_each_gt() DG1_MSTR_TILE_INTR (0x190008) is the top-level, one-per-PCI device interrupt register; we always access it via tile0's MMIO . So in this case we do want to do this outside the loop since it's not a per-tile operation. We could probably simplify the dev_priv->gt.uncore parameter to just dev_priv->uncore to make this more obvious. Matt > > Andi -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795
[Intel-gfx] [PATCH v3 03/10] drm/i915: Restructure probe to handle multi-tile platforms
On a multi-tile platform, each tile has its own registers + GGTT space,
and BAR 0 is extended to cover all of them. Upcoming patches will start
exposing the tiles as multiple GTs within a single PCI device. In
preparation for supporting such setups, restructure the driver's probe
code a bit.
Only the primary/root tile is initialized for now; the other tiles will
be detected and plugged in by future patches once the necessary
infrastructure is in place to handle them.
v2:
- Rename for naming prefix consistency. (Jani, Lucas)
Original-author: Abdiel Janulgue
Cc: Daniele Ceraolo Spurio
Cc: Matthew Auld
Cc: Joonas Lahtinen
Cc: Lucas De Marchi
Cc: Jani Nikula
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 46
drivers/gpu/drm/i915/gt/intel_gt.h | 3 ++
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 9 -
drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 +++
drivers/gpu/drm/i915/i915_drv.c | 20 +--
drivers/gpu/drm/i915/intel_uncore.c | 12 +++
drivers/gpu/drm/i915/intel_uncore.h | 3 +-
7 files changed, 77 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 1cb1948ac959..083c1bacc8bc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -900,6 +900,52 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt,
i915_reg_t reg)
return intel_uncore_read_fw(gt->uncore, reg);
}
+static int
+intel_gt_tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t
phys_addr)
+{
+ int ret;
+
+ intel_uncore_init_early(gt->uncore, gt->i915);
+
+ ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
+ if (ret)
+ return ret;
+
+ gt->phys_addr = phys_addr;
+
+ return 0;
+}
+
+static void
+intel_gt_tile_cleanup(struct intel_gt *gt)
+{
+ intel_uncore_cleanup_mmio(gt->uncore);
+}
+
+int intel_gt_probe_all(struct drm_i915_private *i915)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ phys_addr_t phys_addr;
+ unsigned int mmio_bar;
+ int ret;
+
+ mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
+ phys_addr = pci_resource_start(pdev, mmio_bar);
+
+ /* We always have at least one primary GT on any device */
+ ret = intel_gt_tile_setup(&i915->gt, 0, phys_addr);
+ if (ret)
+ return ret;
+
+ /* TODO: add more tiles */
+ return 0;
+}
+
+void intel_gt_release_all(struct drm_i915_private *i915)
+{
+ intel_gt_tile_cleanup(&i915->gt);
+}
+
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 74e771871a9b..68cdf042ad88 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -85,6 +85,9 @@ static inline bool intel_gt_needs_read_steering(struct
intel_gt *gt,
u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg);
+int intel_gt_probe_all(struct drm_i915_private *i915);
+void intel_gt_release_all(struct drm_i915_private *i915);
+
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index b4a8594bc46c..e1d5495cee58 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -128,7 +128,14 @@ static const struct intel_wakeref_ops wf_ops = {
void intel_gt_pm_init_early(struct intel_gt *gt)
{
- intel_wakeref_init(>->wakeref, gt->uncore->rpm, &wf_ops);
+ /*
+* We access the runtime_pm structure via gt->i915 here rather than
+* gt->uncore as we do elsewhere in the file because gt->uncore is not
+* yet initialized for all tiles at this point in the driver startup.
+* runtime_pm is per-device rather than per-tile, so this is still the
+* correct structure.
+*/
+ intel_wakeref_init(>->wakeref, >->i915->runtime_pm, &wf_ops);
seqcount_mutex_init(>->stats.lock, >->wakeref.mutex);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 14216cc471b1..66143316d92e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -180,6 +180,11 @@ struct intel_gt {
const struct intel_mmio_range *steering_table[NUM_STEERING_TYPES];
+ /*
+* Base of per-tile GTTMMADR where we can derive the MMIO and the GGTT.
+*/
+ phys_addr_t phys_addr;
+
struct intel_gt_info {
intel_engine_mask_t engine_mask;
diff --git a/drivers/gpu/drm/i915/i9
[Intel-gfx] [PATCH v3 01/10] drm/i915: rework some irq functions to take intel_gt as argument
From: Paulo Zanoni
We'll be adding multi-tile support soon; on multi-tile platforms
interrupts are per-tile and every tile has the full set of
interrupt registers.
In this commit we start passing intel_gt instead of dev_priv for the
functions that are related to Xe_HP irq handling. Right now we're still
passing tile 0 everywhere, but in later patches we'll start actually
passing the correct tile.
Signed-off-by: Paulo Zanoni
Co-authored-by: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/i915_irq.c | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 77680bca46ee..038a9ec563c1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2772,7 +2772,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
{
struct drm_i915_private * const i915 = arg;
struct intel_gt *gt = &i915->gt;
- void __iomem * const regs = i915->uncore.regs;
+ void __iomem * const regs = gt->uncore->regs;
u32 master_tile_ctl, master_ctl;
u32 gu_misc_iir;
@@ -3173,11 +3173,12 @@ static void gen11_display_irq_reset(struct
drm_i915_private *dev_priv)
static void gen11_irq_reset(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_gt *gt = &dev_priv->gt;
+ struct intel_uncore *uncore = gt->uncore;
gen11_master_intr_disable(dev_priv->uncore.regs);
- gen11_gt_irq_reset(&dev_priv->gt);
+ gen11_gt_irq_reset(gt);
gen11_display_irq_reset(dev_priv);
GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
@@ -3186,11 +3187,12 @@ static void gen11_irq_reset(struct drm_i915_private
*dev_priv)
static void dg1_irq_reset(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_gt *gt = &dev_priv->gt;
+ struct intel_uncore *uncore = gt->uncore;
dg1_master_intr_disable(dev_priv->uncore.regs);
- gen11_gt_irq_reset(&dev_priv->gt);
+ gen11_gt_irq_reset(gt);
gen11_display_irq_reset(dev_priv);
GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
@@ -3869,13 +3871,14 @@ static void gen11_de_irq_postinstall(struct
drm_i915_private *dev_priv)
static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_gt *gt = &dev_priv->gt;
+ struct intel_uncore *uncore = gt->uncore;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
icp_irq_postinstall(dev_priv);
- gen11_gt_irq_postinstall(&dev_priv->gt);
+ gen11_gt_irq_postinstall(gt);
gen11_de_irq_postinstall(dev_priv);
GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
@@ -3886,10 +3889,11 @@ static void gen11_irq_postinstall(struct
drm_i915_private *dev_priv)
static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_gt *gt = &dev_priv->gt;
+ struct intel_uncore *uncore = gt->uncore;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
- gen11_gt_irq_postinstall(&dev_priv->gt);
+ gen11_gt_irq_postinstall(gt);
GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
@@ -3900,8 +3904,8 @@ static void dg1_irq_postinstall(struct drm_i915_private
*dev_priv)
GEN11_DISPLAY_IRQ_ENABLE);
}
- dg1_master_intr_enable(dev_priv->uncore.regs);
- intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_TILE_INTR);
+ dg1_master_intr_enable(uncore->regs);
+ intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
}
static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
--
2.33.0
[Intel-gfx] [PATCH v3 07/10] drm/i915/xehp: Determine which tile raised an interrupt
From: Paulo Zanoni
The first step of interrupt handling is to read a tile0 register that
tells us in which tile the interrupt happened; we can then read the
usual interrupt registers from the appropriate tile.
Note that this is just the first step of handling interrupts properly on
multi-tile platforms. Subsequent patches will convert other parts of
the interrupt handling flow.
v2:
- Simplify init of t0_regs. (Lucas)
- Fix handling of display and GSE interrupts. Although we only expect
to receive these on tile 0, we should still process them inside the
gt loop to ensure the proper tile's master_ctl value is used.
Cc: Stuart Summers
Cc: Lucas De Marchi
Signed-off-by: Paulo Zanoni
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 41 ++---
1 file changed, 23 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 038a9ec563c1..57a58151eaae 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2771,40 +2771,45 @@ static inline void dg1_master_intr_enable(void __iomem
* const regs)
static irqreturn_t dg1_irq_handler(int irq, void *arg)
{
struct drm_i915_private * const i915 = arg;
+ void __iomem * const t0_regs = i915->gt.uncore->regs;
struct intel_gt *gt = &i915->gt;
- void __iomem * const regs = gt->uncore->regs;
u32 master_tile_ctl, master_ctl;
- u32 gu_misc_iir;
+ u32 gu_misc_iir = 0;
+ unsigned int i;
if (!intel_irqs_enabled(i915))
return IRQ_NONE;
- master_tile_ctl = dg1_master_intr_disable(regs);
+ master_tile_ctl = dg1_master_intr_disable(t0_regs);
if (!master_tile_ctl) {
- dg1_master_intr_enable(regs);
+ dg1_master_intr_enable(t0_regs);
return IRQ_NONE;
}
- /* FIXME: we only support tile 0 for now. */
- if (master_tile_ctl & DG1_MSTR_TILE(0)) {
+ for_each_gt(i915, i, gt) {
+ void __iomem *const regs = gt->uncore->regs;
+
+ if ((master_tile_ctl & DG1_MSTR_TILE(i)) == 0)
+ continue;
+
master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl);
- } else {
- DRM_ERROR("Tile not supported: 0x%08x\n", master_tile_ctl);
- dg1_master_intr_enable(regs);
- return IRQ_NONE;
- }
- gen11_gt_irq_handler(gt, master_ctl);
+ gen11_gt_irq_handler(gt, master_ctl);
- if (master_ctl & GEN11_DISPLAY_IRQ)
- gen11_display_irq_handler(i915);
-
- gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
+ /*
+* In practice we'll only get display and gu_misc interrupts
+* for the GSE on tile0, but it's still simplest to process
+* them inside the loop.
+*/
+ if (master_ctl & GEN11_DISPLAY_IRQ)
+ gen11_display_irq_handler(i915);
- dg1_master_intr_enable(regs);
+ gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
+ gen11_gu_misc_irq_handler(gt, gu_misc_iir);
+ }
- gen11_gu_misc_irq_handler(gt, gu_misc_iir);
+ dg1_master_intr_enable(t0_regs);
pmu_irq_stats(i915, IRQ_HANDLED);
--
2.33.0
[Intel-gfx] [PATCH v3 05/10] drm/i915: Prepare for multiple gts
From: Tvrtko Ursulin
Add some basic plumbing to support more than one dynamically allocated
struct intel_gt. Up to four gts are supported in i915->gts[], with slot
zero shadowing the existing i915->gt to enable source compatibility with
legacy driver paths. A for_each_gt macro is added to iterate over the
GTs and will be used by upcoming patches that convert various parts of
the driver to be multi-gt aware.
v2:
- Rename init function to i915_init_tile_memory() and move it to
i915_drv.c. (Lucas)
- Squash in patch from Sandeep to release the per-gt resources during
driver teardown.
Cc: Lucas De Marchi
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Venkata Sandeep Dhanalakota
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 57 +++---
drivers/gpu/drm/i915/gt/intel_gt.h | 6 +++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +
drivers/gpu/drm/i915/i915_drv.c| 30 +++-
drivers/gpu/drm/i915/i915_drv.h| 6 +++
drivers/gpu/drm/i915/intel_memory_region.h | 3 ++
6 files changed, 96 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 098cd8843c38..d02a09653033 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -23,10 +23,13 @@
#include "shmem_utils.h"
#include "pxp/intel_pxp.h"
-void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
+static void
+__intel_gt_init_early(struct intel_gt *gt,
+ struct intel_uncore *uncore,
+ struct drm_i915_private *i915)
{
gt->i915 = i915;
- gt->uncore = &i915->uncore;
+ gt->uncore = uncore;
spin_lock_init(>->irq_lock);
@@ -49,10 +52,15 @@ void intel_gt_init_early(struct intel_gt *gt, struct
drm_i915_private *i915)
int intel_gt_probe_lmem(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
+ unsigned int instance = gt->info.id;
struct intel_memory_region *mem;
int id;
int err;
+ id = INTEL_REGION_LMEM + instance;
+ if (drm_WARN_ON(&i915->drm, id >= INTEL_REGION_STOLEN_SMEM))
+ return -ENODEV;
+
mem = intel_gt_setup_lmem(gt);
if (mem == ERR_PTR(-ENODEV))
mem = intel_gt_setup_fake_lmem(gt);
@@ -67,9 +75,8 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
return err;
}
- id = INTEL_REGION_LMEM;
-
mem->id = id;
+ mem->instance = instance;
intel_memory_region_set_name(mem, "local%u", mem->instance);
@@ -80,6 +87,11 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
return 0;
}
+void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
+{
+ __intel_gt_init_early(gt, &i915->uncore, i915);
+}
+
void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
{
gt->ggtt = ggtt;
@@ -903,9 +915,29 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt,
i915_reg_t reg)
static int
intel_gt_tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t
phys_addr)
{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore;
+ struct intel_uncore_mmio_debug *mmio_debug;
int ret;
- intel_uncore_init_early(gt->uncore, gt);
+ if (id) {
+ uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
+ if (!uncore)
+ return -ENOMEM;
+
+ mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
+ if (!mmio_debug) {
+ kfree(uncore);
+ return -ENOMEM;
+ }
+
+ __intel_gt_init_early(gt, uncore, i915);
+ } else {
+ uncore = &i915->uncore;
+ mmio_debug = &i915->mmio_debug;
+ }
+
+ intel_uncore_init_early(uncore, gt);
ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
if (ret)
@@ -920,6 +952,11 @@ static void
intel_gt_tile_cleanup(struct intel_gt *gt)
{
intel_uncore_cleanup_mmio(gt->uncore);
+
+ if (gt->info.id) {
+ kfree(gt->uncore);
+ kfree(gt);
+ }
}
int intel_gt_probe_all(struct drm_i915_private *i915)
@@ -937,13 +974,21 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
if (ret)
return ret;
+ i915->gts[0] = &i915->gt;
+
/* TODO: add more tiles */
return 0;
}
void intel_gt_release_all(struct drm_i915_private *i915)
{
- intel_gt_tile_cleanup(&i915->gt);
+ struct intel_gt *gt;
+ unsigned int id;
+
+ for_each_gt(i915, id, gt) {
+ intel_gt_tile_cleanup(gt);
+ i915->gts[id] = NULL;
+ }
}
void intel_gt_info_print(const s
[Intel-gfx] [PATCH v3 06/10] drm/i915: Initial support for per-tile uncore
From: Daniele Ceraolo Spurio
Initialization and suspend/resume is replicated per-tile.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++-
drivers/gpu/drm/i915/i915_drv.c | 61 ++---
3 files changed, 51 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index d02a09653033..ade698d47c34 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -994,6 +994,7 @@ void intel_gt_release_all(struct drm_i915_private *i915)
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p)
{
+ drm_printf(p, "GT %u info:\n", info->id);
drm_printf(p, "available engines: %x\n", info->engine_mask);
intel_sseu_dump(&info->sseu, p);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index fe638b5da7c0..ac7e031b3b0a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -60,12 +60,15 @@ static int i915_capabilities(struct seq_file *m, void *data)
{
struct drm_i915_private *i915 = node_to_i915(m->private);
struct drm_printer p = drm_seq_file_printer(m);
+ struct intel_gt *gt;
+ unsigned int id;
seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
intel_device_info_print_static(INTEL_INFO(i915), &p);
intel_device_info_print_runtime(RUNTIME_INFO(i915), &p);
- intel_gt_info_print(&i915->gt.info, &p);
+ for_each_gt(i915, id, gt)
+ intel_gt_info_print(>->info, &p);
intel_driver_caps_print(&i915->caps, &p);
kernel_param_lock(THIS_MODULE);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fde148d6777e..220d059ca50c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -411,6 +411,8 @@ static void i915_driver_late_release(struct
drm_i915_private *dev_priv)
*/
static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
{
+ struct intel_gt *gt;
+ unsigned int i, j;
int ret;
if (i915_inject_probe_failure(dev_priv))
@@ -420,26 +422,35 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
if (ret < 0)
return ret;
- ret = intel_uncore_init_mmio(&dev_priv->uncore);
- if (ret)
- return ret;
+ for_each_gt(dev_priv, i, gt) {
+ ret = intel_uncore_init_mmio(gt->uncore);
+ if (ret)
+ goto err_uncore;
+ }
/* Try to make sure MCHBAR is enabled before poking at it */
intel_setup_mchbar(dev_priv);
intel_device_info_runtime_init(dev_priv);
- ret = intel_gt_init_mmio(&dev_priv->gt);
- if (ret)
- goto err_uncore;
+ for_each_gt(dev_priv, j, gt) {
+ ret = intel_gt_init_mmio(gt);
+ if (ret)
+ goto err_mchbar;
+ }
/* As early as possible, scrub existing GPU state before clobbering */
sanitize_gpu(dev_priv);
return 0;
-err_uncore:
+err_mchbar:
intel_teardown_mchbar(dev_priv);
- intel_uncore_fini_mmio(&dev_priv->uncore);
+err_uncore:
+ for_each_gt(dev_priv, j, gt) {
+ if (j >= i)
+ break;
+ intel_uncore_fini_mmio(gt->uncore);
+ }
pci_dev_put(dev_priv->bridge_dev);
return ret;
@@ -451,8 +462,12 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
*/
static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
{
+ struct intel_gt *gt;
+ unsigned int i;
+
intel_teardown_mchbar(dev_priv);
- intel_uncore_fini_mmio(&dev_priv->uncore);
+ for_each_gt(dev_priv, i, gt)
+ intel_uncore_fini_mmio(gt->uncore);
pci_dev_put(dev_priv->bridge_dev);
}
@@ -761,6 +776,8 @@ static void i915_welcome_messages(struct drm_i915_private
*dev_priv)
{
if (drm_debug_enabled(DRM_UT_DRIVER)) {
struct drm_printer p = drm_debug_printer("i915 device info:");
+ struct intel_gt *gt;
+ unsigned int id;
drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s
(subplatform=0x%x) gen=%i\n",
INTEL_DEVID(dev_priv),
@@ -772,7 +789,8 @@ static void i915_welcome_messages(struct drm_i915_private
*dev_priv)
intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &
[Intel-gfx] [PATCH v3 02/10] drm/i915: split general MMIO setup from per-GT uncore init
From: Daniele Ceraolo Spurio
In coming patches we'll be doing the actual tile initialization between
these two uncore init phases.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/i915_drv.c | 9 -
drivers/gpu/drm/i915/intel_uncore.c | 17 +++--
drivers/gpu/drm/i915/intel_uncore.h | 2 ++
3 files changed, 13 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1e5b75ae9932..b9fed62806f8 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -416,10 +416,14 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
if (ret < 0)
return ret;
- ret = intel_uncore_init_mmio(&dev_priv->uncore);
+ ret = intel_uncore_setup_mmio(&dev_priv->uncore);
if (ret < 0)
goto err_bridge;
+ ret = intel_uncore_init_mmio(&dev_priv->uncore);
+ if (ret)
+ goto err_mmio;
+
/* Try to make sure MCHBAR is enabled before poking at it */
intel_setup_mchbar(dev_priv);
intel_device_info_runtime_init(dev_priv);
@@ -436,6 +440,8 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
err_uncore:
intel_teardown_mchbar(dev_priv);
intel_uncore_fini_mmio(&dev_priv->uncore);
+err_mmio:
+ intel_uncore_cleanup_mmio(&dev_priv->uncore);
err_bridge:
pci_dev_put(dev_priv->bridge_dev);
@@ -450,6 +456,7 @@ static void i915_driver_mmio_release(struct
drm_i915_private *dev_priv)
{
intel_teardown_mchbar(dev_priv);
intel_uncore_fini_mmio(&dev_priv->uncore);
+ intel_uncore_cleanup_mmio(&dev_priv->uncore);
pci_dev_put(dev_priv->bridge_dev);
}
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 722910d02b5f..abdac78d3976 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2020,7 +2020,7 @@ static int i915_pmic_bus_access_notifier(struct
notifier_block *nb,
return NOTIFY_OK;
}
-static int uncore_mmio_setup(struct intel_uncore *uncore)
+int intel_uncore_setup_mmio(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore->i915;
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
@@ -2053,7 +2053,7 @@ static int uncore_mmio_setup(struct intel_uncore *uncore)
return 0;
}
-static void uncore_mmio_cleanup(struct intel_uncore *uncore)
+void intel_uncore_cleanup_mmio(struct intel_uncore *uncore)
{
struct pci_dev *pdev = to_pci_dev(uncore->i915->drm.dev);
@@ -2146,10 +2146,6 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
struct drm_i915_private *i915 = uncore->i915;
int ret;
- ret = uncore_mmio_setup(uncore);
- if (ret)
- return ret;
-
/*
* The boot firmware initializes local memory and assesses its health.
* If memory training fails, the punit will have been instructed to
@@ -2170,7 +2166,7 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
} else {
ret = uncore_forcewake_init(uncore);
if (ret)
- goto out_mmio_cleanup;
+ return ret;
}
/* make sure fw funcs are set if and only if we have fw*/
@@ -2192,11 +2188,6 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init,
clearing\n");
return 0;
-
-out_mmio_cleanup:
- uncore_mmio_cleanup(uncore);
-
- return ret;
}
/*
@@ -2261,8 +2252,6 @@ void intel_uncore_fini_mmio(struct intel_uncore *uncore)
intel_uncore_fw_domains_fini(uncore);
iosf_mbi_punit_release();
}
-
- uncore_mmio_cleanup(uncore);
}
static const struct reg_whitelist {
diff --git a/drivers/gpu/drm/i915/intel_uncore.h
b/drivers/gpu/drm/i915/intel_uncore.h
index 3248e4e2c540..d1d17b04e29f 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -218,11 +218,13 @@ void
intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
void intel_uncore_init_early(struct intel_uncore *uncore,
struct drm_i915_private *i915);
+int intel_uncore_setup_mmio(struct intel_uncore *uncore);
int intel_uncore_init_mmio(struct intel_uncore *uncore);
void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
struct intel_gt *gt);
bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
+void intel_uncore_cleanup_mmio(struct intel_uncore *unc
[Intel-gfx] [PATCH v3 00/10] i915: Initial multi-tile support
Some of our upcoming platforms, including the Xe_HP SDV, support a "multi-tile" design. A multi-tile platform is effectively a platform with multiple GT instances and local memory regions, all behind a single PCI device. From an i915 perspective, this translates to multiple intel_gt structures per drm_i915_private. This series provides the initial refactoring to support multiple independent GTs per card, but further work (especially related to local memory) will be required to fully enable a multi-tile platform. Note that the presence of multiple GTs is largely transparent to userspace. A multi-tile platform will advertise a larger list of engines to userspace, but the concept of "tile" is not something userspace has to worry about directly. There will be some uapi implications later due to the devices having multiple local memory regions, but that aspect of multi-tile is not covered by this patch series and will show up in future work. v2: - Include some additional tile setup refactoring that got missed in v1. v3: - Fix GEM_BUG_ON() assertion on pre-gen9 platforms; the assertion was only meant for multi-tile platforms and will always fail on old platforms that have a BAR0 smaller than 16MB. - Rename some of the gt/tile initialization functions. (Lucas/Jani) - Move top-level tile memory init to i915_drv.c since it isn't directly related to the GT. (Lucas) - Squash per-gt cleanup into the patch that introduces the per-gt setup. - Fix handling of display and GSE interrupts (our current multi-tile platforms don't have display, but we can't count on that being true in the future). Daniele Ceraolo Spurio (2): drm/i915: split general MMIO setup from per-GT uncore init drm/i915: Initial support for per-tile uncore Matt Roper (1): drm/i915: Restructure probe to handle multi-tile platforms Michal Wajdeczko (1): drm/i915/guc: Update CT debug macro for multi-tile Michał Winiarski (1): drm/i915: Store backpointer to GT in uncore Paulo Zanoni (3): drm/i915: rework some irq functions to take intel_gt as argument drm/i915/xehp: Determine which tile raised an interrupt drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware Tvrtko Ursulin (2): drm/i915: Prepare for multiple gts drm/i915/xehpsdv: Initialize multi-tiles drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c| 177 +- drivers/gpu/drm/i915/gt/intel_gt.h| 11 ++ drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 10 + drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +- drivers/gpu/drm/i915/i915_debugfs.c | 5 +- drivers/gpu/drm/i915/i915_drv.c | 102 -- drivers/gpu/drm/i915/i915_drv.h | 9 + drivers/gpu/drm/i915/i915_irq.c | 77 +--- drivers/gpu/drm/i915/i915_pci.c | 40 +++- drivers/gpu/drm/i915/i915_reg.h | 4 + drivers/gpu/drm/i915/intel_device_info.h | 15 ++ drivers/gpu/drm/i915/intel_memory_region.h| 3 + drivers/gpu/drm/i915/intel_uncore.c | 36 ++-- drivers/gpu/drm/i915/intel_uncore.h | 6 +- .../gpu/drm/i915/selftests/mock_gem_device.c | 3 +- drivers/gpu/drm/i915/selftests/mock_uncore.c | 2 +- 18 files changed, 423 insertions(+), 94 deletions(-) -- 2.33.0
[Intel-gfx] [PATCH v3 04/10] drm/i915: Store backpointer to GT in uncore
From: Michał Winiarski
We now support a per-gt uncore, yet we're not able to infer which GT
we're operating upon. Let's store a backpointer for now.
Signed-off-by: Michał Winiarski
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 9 +
drivers/gpu/drm/i915/intel_uncore.h | 3 ++-
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 +--
drivers/gpu/drm/i915/selftests/mock_uncore.c | 2 +-
5 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 083c1bacc8bc..098cd8843c38 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -905,7 +905,7 @@ intel_gt_tile_setup(struct intel_gt *gt, unsigned int id,
phys_addr_t phys_addr)
{
int ret;
- intel_uncore_init_early(gt->uncore, gt->i915);
+ intel_uncore_init_early(gt->uncore, gt);
ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
if (ret)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 86399bb21987..6ea23b306530 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2057,12 +2057,13 @@ void intel_uncore_cleanup_mmio(struct intel_uncore
*uncore)
}
void intel_uncore_init_early(struct intel_uncore *uncore,
-struct drm_i915_private *i915)
+struct intel_gt *gt)
{
spin_lock_init(&uncore->lock);
- uncore->i915 = i915;
- uncore->rpm = &i915->runtime_pm;
- uncore->debug = &i915->mmio_debug;
+ uncore->i915 = gt->i915;
+ uncore->gt = gt;
+ uncore->rpm = >->i915->runtime_pm;
+ uncore->debug = >->i915->mmio_debug;
}
static void uncore_raw_init(struct intel_uncore *uncore)
diff --git a/drivers/gpu/drm/i915/intel_uncore.h
b/drivers/gpu/drm/i915/intel_uncore.h
index 83a455aa8374..2989032b580b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -130,6 +130,7 @@ struct intel_uncore {
void __iomem *regs;
struct drm_i915_private *i915;
+ struct intel_gt *gt;
struct intel_runtime_pm *rpm;
spinlock_t lock; /** lock is also taken in irq contexts. */
@@ -218,7 +219,7 @@ u32 intel_uncore_read_with_mcr_steering(struct intel_uncore
*uncore,
void
intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
void intel_uncore_init_early(struct intel_uncore *uncore,
-struct drm_i915_private *i915);
+struct intel_gt *gt);
int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t
phys_addr);
int intel_uncore_init_mmio(struct intel_uncore *uncore);
void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 4f8180146888..bd21bb7d104e 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -175,10 +175,9 @@ struct drm_i915_private *mock_gem_device(void)
mkwrite_device_info(i915)->memory_regions = REGION_SMEM;
intel_memory_regions_hw_probe(i915);
- mock_uncore_init(&i915->uncore, i915);
-
i915_gem_init__mm(i915);
intel_gt_init_early(&i915->gt, i915);
+ mock_uncore_init(&i915->uncore, i915);
atomic_inc(&i915->gt.wakeref.count); /* disable; no hw support */
i915->gt.awake = -ENODEV;
diff --git a/drivers/gpu/drm/i915/selftests/mock_uncore.c
b/drivers/gpu/drm/i915/selftests/mock_uncore.c
index ca57e4008701..b3790ef137e4 100644
--- a/drivers/gpu/drm/i915/selftests/mock_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/mock_uncore.c
@@ -42,7 +42,7 @@ __nop_read(64)
void mock_uncore_init(struct intel_uncore *uncore,
struct drm_i915_private *i915)
{
- intel_uncore_init_early(uncore, i915);
+ intel_uncore_init_early(uncore, &i915->gt);
ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, nop);
ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, nop);
--
2.33.0
[Intel-gfx] [PATCH v3 09/10] drm/i915/guc: Update CT debug macro for multi-tile
From: Michal Wajdeczko
Update CT debug macros by including tile ID in all messages.
Cc: Michał Winiarski
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index a0cc34be7b56..8ca8dd0566fe 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -33,15 +33,15 @@ static inline struct drm_device *ct_to_drm(struct
intel_guc_ct *ct)
}
#define CT_ERROR(_ct, _fmt, ...) \
- drm_err(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+ drm_err(ct_to_drm(_ct), "CT%u: " _fmt, ct_to_gt(_ct)->info.id,
##__VA_ARGS__)
#ifdef CONFIG_DRM_I915_DEBUG_GUC
#define CT_DEBUG(_ct, _fmt, ...) \
- drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
+ drm_dbg(ct_to_drm(_ct), "CT%u: " _fmt, ct_to_gt(_ct)->info.id,
##__VA_ARGS__)
#else
#define CT_DEBUG(...) do { } while (0)
#endif
#define CT_PROBE_ERROR(_ct, _fmt, ...) \
- i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
+ i915_probe_error(ct_to_i915(ct), "CT%u: " _fmt, ct_to_gt(_ct)->info.id,
##__VA_ARGS__)
/**
* DOC: CTB Blob
--
2.33.0
[Intel-gfx] [PATCH v3 08/10] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware
From: Paulo Zanoni
Loop through all the tiles when initializing and resetting interrupts.
v2:
- Access tile0 registers through dev_priv->uncore rather than
dev_priv->gt.uncore for clarity.
Signed-off-by: Paulo Zanoni
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/i915_irq.c | 28 ++--
1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 57a58151eaae..c2955916e0fe 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3194,14 +3194,19 @@ static void dg1_irq_reset(struct drm_i915_private
*dev_priv)
{
struct intel_gt *gt = &dev_priv->gt;
struct intel_uncore *uncore = gt->uncore;
+ unsigned int i;
dg1_master_intr_disable(dev_priv->uncore.regs);
- gen11_gt_irq_reset(gt);
- gen11_display_irq_reset(dev_priv);
+ for_each_gt(dev_priv, i, gt) {
+ gen11_gt_irq_reset(gt);
- GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
- GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+ uncore = gt->uncore;
+ GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
+ GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+ }
+
+ gen11_display_irq_reset(dev_priv);
}
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -3894,13 +3899,16 @@ static void gen11_irq_postinstall(struct
drm_i915_private *dev_priv)
static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_gt *gt = &dev_priv->gt;
- struct intel_uncore *uncore = gt->uncore;
+ struct intel_gt *gt;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
+ unsigned int i;
- gen11_gt_irq_postinstall(gt);
+ for_each_gt(dev_priv, i, gt) {
+ gen11_gt_irq_postinstall(gt);
- GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
+ GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked,
+ gu_misc_masked);
+ }
if (HAS_DISPLAY(dev_priv)) {
icp_irq_postinstall(dev_priv);
@@ -3909,8 +3917,8 @@ static void dg1_irq_postinstall(struct drm_i915_private
*dev_priv)
GEN11_DISPLAY_IRQ_ENABLE);
}
- dg1_master_intr_enable(uncore->regs);
- intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
+ dg1_master_intr_enable(dev_priv->uncore.regs);
+ intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_TILE_INTR);
}
static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
--
2.33.0
[Intel-gfx] [PATCH v3 10/10] drm/i915/xehpsdv: Initialize multi-tiles
From: Tvrtko Ursulin
Check how many extra GT tiles are available on the system and setup
register access for all of them. We can detect how may GT tiles are
available by reading a register on the root tile. The same register
returns the tile ID on all tiles.
v2:
- Include some additional refactor that didn't get squashed in properly
on v1.
v3:
- Move the PCI BAR size assertion into the non-gt0 code since we're
only really trying to check it on multi-tile platforms (and on old
pre-gen9 platforms the BAR size is less than 16MB so the assertion
would have failed there).
Bspec: 33407
Original-author: Abdiel Janulgue
Signed-off-by: Tvrtko Ursulin
Co-authored-by: Matt Roper
Signed-off-by: Matt Roper
Cc: Matthew Auld
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Paulo Zanoni
Cc: Andi Shyti
Signed-off-by: Paulo Zanoni
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 83 ++-
drivers/gpu/drm/i915/gt/intel_gt.h| 4 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 7 +-
drivers/gpu/drm/i915/i915_pci.c | 40 +--
drivers/gpu/drm/i915/i915_reg.h | 4 ++
drivers/gpu/drm/i915/intel_device_info.h | 15
8 files changed, 146 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 332756036007..b50520bf3445 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -527,7 +527,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt
*gt)
u16 vdbox_mask;
u16 vebox_mask;
- info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
+ GEM_BUG_ON(!info->engine_mask);
if (GRAPHICS_VER(i915) < 11)
return info->engine_mask;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index ade698d47c34..54154715a14e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -912,7 +912,7 @@ u32 intel_gt_read_register_fw(struct intel_gt *gt,
i915_reg_t reg)
return intel_uncore_read_fw(gt->uncore, reg);
}
-static int
+int
intel_gt_tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t
phys_addr)
{
struct drm_i915_private *i915 = gt->i915;
@@ -921,6 +921,11 @@ intel_gt_tile_setup(struct intel_gt *gt, unsigned int id,
phys_addr_t phys_addr)
int ret;
if (id) {
+ /* For multi-tile platforms BAR0 must have at least 16MB per
tile */
+ if (GEM_WARN_ON(pci_resource_len(to_pci_dev(i915->drm.dev), 0) <
+ (id + 1) * SZ_16M))
+ return -EINVAL;
+
uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
if (!uncore)
return -ENOMEM;
@@ -943,6 +948,16 @@ intel_gt_tile_setup(struct intel_gt *gt, unsigned int id,
phys_addr_t phys_addr)
if (ret)
return ret;
+ /* Which tile am I? default to zero on single tile systems */
+ if (HAS_REMOTE_TILES(i915)) {
+ u32 instance =
+ __raw_uncore_read32(gt->uncore, XEHPSDV_MTCFG_ADDR) &
+ TILE_NUMBER;
+
+ if (GEM_WARN_ON(instance != id))
+ return -ENXIO;
+ }
+
gt->phys_addr = phys_addr;
return 0;
@@ -959,25 +974,87 @@ intel_gt_tile_cleanup(struct intel_gt *gt)
}
}
+static unsigned int tile_count(struct drm_i915_private *i915)
+{
+ u32 mtcfg;
+
+ /*
+* We use raw MMIO reads at this point since the
+* MMIO vfuncs are not setup yet
+*/
+ mtcfg = __raw_uncore_read32(&i915->uncore, XEHPSDV_MTCFG_ADDR);
+ return REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
+}
+
int intel_gt_probe_all(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ const struct intel_gt_definition *gtdef;
+ struct intel_gt *gt;
phys_addr_t phys_addr;
unsigned int mmio_bar;
+ unsigned int i, tiles;
int ret;
mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
phys_addr = pci_resource_start(pdev, mmio_bar);
/* We always have at least one primary GT on any device */
- ret = intel_gt_tile_setup(&i915->gt, 0, phys_addr);
+ gt = &i915->gt;
+ gt->name = "Primary GT";
+ gt->info.engine_mask = INTEL_INFO(i915)->platform_engine_mask;
+
+ drm_dbg(&i915->drm, "Setting up %s %u\n", gt->name, gt->info.id);
+ ret = intel_gt_tile_setup(gt, 0, phys_addr);
if (ret)
return ret;
i915->gts[0] = &
Re: [Intel-gfx] [PATCH] drm/i915/dg1: Add new PCI id
On Mon, Sep 13, 2021 at 11:19:09AM -0700, José Roberto de Souza wrote: > New DG1 PCI id. > > BSpec: 44463 > Cc: Caz Yokoyama > Cc: Matt Roper > Signed-off-by: José Roberto de Souza Reviewed-by: Matt Roper > --- > include/drm/i915_pciids.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h > index cb45af9f2c44f..c00ac54692d70 100644 > --- a/include/drm/i915_pciids.h > +++ b/include/drm/i915_pciids.h > @@ -632,7 +632,8 @@ > INTEL_VGA_DEVICE(0x4905, info), \ > INTEL_VGA_DEVICE(0x4906, info), \ > INTEL_VGA_DEVICE(0x4907, info), \ > - INTEL_VGA_DEVICE(0x4908, info) > + INTEL_VGA_DEVICE(0x4908, info), \ > + INTEL_VGA_DEVICE(0x4909, info) > > /* ADL-S */ > #define INTEL_ADLS_IDS(info) \ > -- > 2.33.0 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795
Re: [Intel-gfx] [PATCH] drm/i915: Update memory bandwidth parameters
On Mon, Sep 13, 2021 at 10:42:54AM -0700, Radhakrishna Sripada wrote:
> Earlier while calculating derated bw we would use 90% of the calculated
> bw. Starting ADL-P we use a non standard derating. Updating the formulae
> to reflect the same.
>
> Bspec: 64631
>
> Fixes: 4d32fe2f14a7 ("drm/i915/adl_p: Update memory bandwidth parameters")
> Cc: Matt Roper
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index e91e0e0191fb..23121ddd2580 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -222,31 +222,35 @@ static int icl_sagv_max_dclk(const struct
> intel_qgv_info *qi)
>
> struct intel_sa_info {
> u16 displayrtids;
> - u8 deburst, deprogbwlimit;
> + u8 deburst, deprogbwlimit, derating;
> };
>
> static const struct intel_sa_info icl_sa_info = {
> .deburst = 8,
> .deprogbwlimit = 25, /* GB/s */
> .displayrtids = 128,
> + .derating = 10,
> };
>
> static const struct intel_sa_info tgl_sa_info = {
> .deburst = 16,
> .deprogbwlimit = 34, /* GB/s */
> .displayrtids = 256,
> + .derating = 10,
> };
>
> static const struct intel_sa_info rkl_sa_info = {
> .deburst = 16,
> .deprogbwlimit = 20, /* GB/s */
> .displayrtids = 128,
> + .derating = 10,
> };
>
> static const struct intel_sa_info adls_sa_info = {
> .deburst = 16,
> .deprogbwlimit = 38, /* GB/s */
> .displayrtids = 256,
> + .derating = 20,
This is changing the derating for both ADL-S and ADL-P, but the bspec
says that ADL-S still uses a derating of 10.
Matt
> };
>
> static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct
> intel_sa_info *sa)
> @@ -302,7 +306,7 @@ static int icl_get_bw_info(struct drm_i915_private
> *dev_priv, const struct intel
> bw = icl_calc_bw(sp->dclk, clpchgroup * 32 *
> num_channels, ct);
>
> bi->deratedbw[j] = min(maxdebw,
> -bw * 9 / 10); /* 90% */
> + bw * (100 - sa->derating) / 100);
>
> drm_dbg_kms(&dev_priv->drm,
> "BW%d / QGV %d: num_planes=%d
> deratedbw=%u\n",
> --
> 2.20.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
Re: [Intel-gfx] [v2] drm/i915: Update memory bandwidth parameters
On Tue, Sep 14, 2021 at 03:07:44PM -0700, Radhakrishna Sripada wrote:
> Earlier while calculating derated bw we would use 90% of the calculated
> bw. Starting ADL-P we use a non standard derating. Updating the formulae
> to reflect the same.
>
> Bspec: 64631
>
> v2: Use the new derating value only for ADL-P(MattR)
>
> Fixes: 4d32fe2f14a7 ("drm/i915/adl_p: Update memory bandwidth parameters")
> Cc: Matt Roper
> Signed-off-by: Radhakrishna Sripada
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 19 ---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index e91e0e0191fb..4b94256d7319 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -222,31 +222,42 @@ static int icl_sagv_max_dclk(const struct
> intel_qgv_info *qi)
>
> struct intel_sa_info {
> u16 displayrtids;
> - u8 deburst, deprogbwlimit;
> + u8 deburst, deprogbwlimit, derating;
> };
>
> static const struct intel_sa_info icl_sa_info = {
> .deburst = 8,
> .deprogbwlimit = 25, /* GB/s */
> .displayrtids = 128,
> + .derating = 10,
> };
>
> static const struct intel_sa_info tgl_sa_info = {
> .deburst = 16,
> .deprogbwlimit = 34, /* GB/s */
> .displayrtids = 256,
> + .derating = 10,
> };
>
> static const struct intel_sa_info rkl_sa_info = {
> .deburst = 16,
> .deprogbwlimit = 20, /* GB/s */
> .displayrtids = 128,
> + .derating = 10,
> };
>
> static const struct intel_sa_info adls_sa_info = {
> .deburst = 16,
> .deprogbwlimit = 38, /* GB/s */
> .displayrtids = 256,
> + .derating = 10,
> +};
> +
> +static const struct intel_sa_info adlp_sa_info = {
> + .deburst = 16,
> + .deprogbwlimit = 38, /* GB/s */
> + .displayrtids = 256,
> + .derating = 20,
> };
>
> static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct
> intel_sa_info *sa)
> @@ -302,7 +313,7 @@ static int icl_get_bw_info(struct drm_i915_private
> *dev_priv, const struct intel
> bw = icl_calc_bw(sp->dclk, clpchgroup * 32 *
> num_channels, ct);
>
> bi->deratedbw[j] = min(maxdebw,
> -bw * 9 / 10); /* 90% */
> +bw * (100 - sa->derating) / 100);
>
> drm_dbg_kms(&dev_priv->drm,
> "BW%d / QGV %d: num_planes=%d
> deratedbw=%u\n",
> @@ -400,7 +411,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
>
> if (IS_DG2(dev_priv))
> dg2_get_bw_info(dev_priv);
> - else if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
> + else if (IS_ALDERLAKE_P(dev_priv))
> + icl_get_bw_info(dev_priv, &adlp_sa_info);
> + else if (IS_ALDERLAKE_S(dev_priv))
> icl_get_bw_info(dev_priv, &adls_sa_info);
> else if (IS_ROCKETLAKE(dev_priv))
> icl_get_bw_info(dev_priv, &rkl_sa_info);
> --
> 2.20.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Add MOCS tables for XeHP SDV and DG2 (rev3)
.@flip-vs-cursor-atomic-transitions.html
>
> * igt@kms_dp_aux_dev:
> - {shard-rkl}:[SKIP][125] ([i915#1257]) -> [PASS][126]
>[125]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10557/shard-rkl-2/igt@kms_dp_aux_dev.html
>[126]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20977/shard-rkl-6/igt@kms_dp_aux_dev.html
>
> * igt@kms_draw_crc@draw-method-xrgb-blt-xtiled:
> - {shard-rkl}:[SKIP][127] ([fdo#111314]) -> [PASS][128] +12
> similar issues
>[127]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10557/shard-rkl-2/igt@kms_draw_...@draw-method-xrgb-blt-xtiled.html
>[128]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20977/shard-rkl-6/igt@kms_draw_...@draw-method-xrgb-blt-xtiled.html
>
> * igt@kms_fbcon_fbt@psr-suspend:
> - {shard-rkl}:[SKIP][129] ([fdo#110189] / [i915#3955]) ->
> [PASS][130] +1 similar issue
>[129]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10557/shard-rkl-2/igt@kms_fbcon_...@psr-suspend.html
>[130]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20977/shard-rkl-6/igt@kms_fbcon_...@psr-suspend.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
> - shard-skl: [FAIL][131] ([i915#79]) -> [PASS][132]
>[131]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10557/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-edp1.html
>[132]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20977/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-edp1.html
>
> * igt@kms_flip@flip-vs-suspend@b-dp1:
> - shard-apl: [DMESG-WARN][133] ([i915#180]) -> [PASS][134]
>[133]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10557/shard-apl7/igt@kms_flip@flip-vs-susp...@b-dp1.html
>[134]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20977/shard-apl7/igt@kms_flip@flip-vs-susp...@b-dp1.html
>
> * igt@kms_flip@flip-vs-suspend@c-dp1:
> - shard-kbl: [INCOMPLETE][135] ([i915#636]) -> [PASS][136]
>[135]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10557/shard-kbl2/igt@kms_flip@flip-vs-susp...@c-dp1.html
>[136]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20977/shard-kbl4/igt@kms_flip@flip-vs-susp...@c-dp1.html
>
> * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
> - shard-skl: [FAIL][137] ([i915#2122]) -> [PASS][138]
>[137]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10557/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interrupti...@a-edp1.html
>[138]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20977/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interrupti...@a-edp1.html
>
> * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
> - shard-iclb: [SKIP][139] -> [PASS][140]
>[139]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10557/shard-iclb2/igt@kms_flip_scaled_...@flip-32bpp-ytileccs-to-64bpp-ytile.html
>[140]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20977/shard-iclb6/igt@kms_flip_scaled_...@flip-32bpp-ytileccs-to-64bpp-ytile.html
>
> * igt@kms_frontbuffer_tracking@basic:
> - {shard-rkl}:[SKIP][141] ([i915#1849]) -> [PASS][142] +50
> similar issues
>[141]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10557/shard-rkl-1/igt@kms_frontbuffer_track...@basic.html
>[142]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20977/shard-rkl-6/igt@kms_frontbuffer_track...@basic.html
>
> * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
> - {shard-rkl}:[SKIP][143] ([i915#3558]) -> [PASS][144] +5 similar
> issues
>[143]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10557/shard-rkl-2/igt@kms_plane@plane-panning-bottom-ri
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20977/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
Re: [Intel-gfx] [PATCH 3/4] drm/i915: rename debugfs_gt_pm files
On Fri, Sep 10, 2021 at 10:52:57AM -0700, Lucas De Marchi wrote:
> On Wed, Sep 08, 2021 at 05:49:40PM -0700, Lucas De Marchi wrote:
> > We shouldn't be using debugfs_ namespace for this functionality. Rename
> > debugfs_gt_pm.[ch] to intel_gt_pm_debugfs.[ch] and then make
> > functions, defines and structs follow suit.
> >
> > Signed-off-by: Lucas De Marchi
> > ---
> > drivers/gpu/drm/i915/Makefile | 2 +-
> > drivers/gpu/drm/i915/gt/debugfs_gt_pm.h| 14 --
> > drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 4 ++--
> > .../gt/{debugfs_gt_pm.c => intel_gt_pm_debugfs.c} | 4 ++--
> > drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h | 14 ++
> > 5 files changed, 19 insertions(+), 19 deletions(-)
> > delete mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt_pm.h
> > rename drivers/gpu/drm/i915/gt/{debugfs_gt_pm.c => intel_gt_pm_debugfs.c}
> > (99%)
> > create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > index 232c9673a2e5..dd656f2d7721 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -79,7 +79,6 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
> >
> > # "Graphics Technology" (aka we talk to the gpu)
> > gt-y += \
> > - gt/debugfs_gt_pm.o \
> > gt/gen2_engine_cs.o \
> > gt/gen6_engine_cs.o \
> > gt/gen6_ppgtt.o \
> > @@ -103,6 +102,7 @@ gt-y += \
> > gt/intel_gt_engines_debugfs.o \
> > gt/intel_gt_irq.o \
> > gt/intel_gt_pm.o \
> > + gt/intel_gt_pm_debugfs.o \
> > gt/intel_gt_pm_irq.o \
> > gt/intel_gt_requests.o \
> > gt/intel_gtt.o \
> > diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.h
> > b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.h
> > deleted file mode 100644
> > index 4cf5f5c9da7d..
> > --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.h
> > +++ /dev/null
> > @@ -1,14 +0,0 @@
> > -/* SPDX-License-Identifier: MIT */
> > -/*
> > - * Copyright © 2019 Intel Corporation
> > - */
> > -
> > -#ifndef DEBUGFS_GT_PM_H
> > -#define DEBUGFS_GT_PM_H
> > -
> > -struct intel_gt;
> > -struct dentry;
> > -
> > -void debugfs_gt_pm_register(struct intel_gt *gt, struct dentry *root);
> > -
> > -#endif /* DEBUGFS_GT_PM_H */
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> > b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> > index e5d173c235a3..4096ee893b69 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> > @@ -5,10 +5,10 @@
> >
> > #include
> >
> > -#include "debugfs_gt_pm.h"
> > #include "i915_drv.h"
> > #include "intel_gt_debugfs.h"
> > #include "intel_gt_engines_debugfs.h"
> > +#include "intel_gt_pm_debugfs.h"
> > #include "intel_sseu_debugfs.h"
> > #include "uc/intel_uc_debugfs.h"
> >
> > @@ -24,7 +24,7 @@ void intel_gt_register_debugfs(struct intel_gt *gt)
> > return;
> >
> > intel_gt_engines_register_debugfs(gt, root);
> > - debugfs_gt_pm_register(gt, root);
> > + intel_gt_pm_register_debugfs(gt, root);
>
> This is one case I usually don't know what convention to follow since it
> changes in different places.
>
> I did it like _register_debugfs because of calls like
> intel_gt_init_scratch(), xxx_init_hw, etc. However here I see that just
> below we have intel_sseu_debugfs_register(), so maybe I should consider
> debugfs as part of the namespace?
I like *_debugfs_register slightly better than *_register_debugfs
because to me we're not registering debugfs itself, we're performing
debugfs' register operation on some files. But I don't really have a
strong feeling either way. Whichever way you decide,
Reviewed-by: Matt Roper
for the series.
Matt
>
> Lucas De Marchi
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
Re: [Intel-gfx] [PATCH V5 1/5] drm/i915/gt: Add support of mocs propagation
On Fri, Sep 03, 2021 at 02:51:49PM +0530, Ayaz A Siddiqui wrote:
> Now there are lots of Command and registers that require mocs index
> programming.
> So propagating mocs_index from mocs to gt so that it can be
> used directly without having platform-specific checks.
>
> V2:
> Changed 'i915_mocs_index_gt' to anonymous structure.
>
> Cc: CQ Tang
> Reviewed-by: Matt Roper
> Signed-off-by: Ayaz A Siddiqui
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 2 ++
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 4
> drivers/gpu/drm/i915/gt/intel_mocs.c | 13 +
> drivers/gpu/drm/i915/gt/intel_mocs.h | 1 +
> 4 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 62d40c9866427..2aeaae036a6f8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -682,6 +682,8 @@ int intel_gt_init(struct intel_gt *gt)
> goto err_pm;
> }
>
> + set_mocs_index(gt);
> +
> err = intel_engines_init(gt);
> if (err)
> goto err_engines;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index a81e21bf1bd1a..6fdcde64c1800 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -192,6 +192,10 @@ struct intel_gt {
>
> unsigned long mslice_mask;
> } info;
> +
> + struct {
> + u8 uc_index;
> + } mocs;
> };
>
> enum intel_gt_scratch_field {
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 582c4423b95d6..7ccac15d9a331 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -22,6 +22,7 @@ struct drm_i915_mocs_table {
> unsigned int size;
> unsigned int n_entries;
> const struct drm_i915_mocs_entry *table;
> + u8 uc_index;
> };
>
> /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
> @@ -340,14 +341,18 @@ static unsigned int get_mocs_settings(const struct
> drm_i915_private *i915,
> {
> unsigned int flags;
>
> + memset(table, 0, sizeof(struct drm_i915_mocs_table));
> +
> if (IS_DG1(i915)) {
> table->size = ARRAY_SIZE(dg1_mocs_table);
> table->table = dg1_mocs_table;
> + table->uc_index = 1;
> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> } else if (GRAPHICS_VER(i915) >= 12) {
> table->size = ARRAY_SIZE(tgl_mocs_table);
> table->table = tgl_mocs_table;
> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> + table->uc_index = 3;
> } else if (GRAPHICS_VER(i915) == 11) {
> table->size = ARRAY_SIZE(icl_mocs_table);
> table->table = icl_mocs_table;
> @@ -504,6 +509,14 @@ static u32 global_mocs_offset(void)
> return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
> }
>
> +void set_mocs_index(struct intel_gt *gt)
Hi Ayaz,
I overlooked it when doing my review before, but for non-static
functions like this we should have a proper function name prefix
(intel_* in this case).
Would you mind writing a small patch to rename this?
Thanks.
Matt
> +{
> + struct drm_i915_mocs_table table;
> +
> + get_mocs_settings(gt->i915, &table);
> + gt->mocs.uc_index = table.uc_index;
> +}
> +
> void intel_mocs_init(struct intel_gt *gt)
> {
> struct drm_i915_mocs_table table;
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h
> b/drivers/gpu/drm/i915/gt/intel_mocs.h
> index d83274f5163bd..8a09d64b115f7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
> @@ -36,5 +36,6 @@ struct intel_gt;
>
> void intel_mocs_init(struct intel_gt *gt);
> void intel_mocs_init_engine(struct intel_engine_cs *engine);
> +void set_mocs_index(struct intel_gt *gt);
>
> #endif
> --
> 2.26.2
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Mark GPU wedging on driver unregister unrecoverable (rev2)
ard-rkl}:[SKIP][122] ([i915#3721]) -> [PASS][123] +1 similar
> issue
>[122]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10550/shard-rkl-2/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
>[123]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20953/shard-rkl-6/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
>
> * igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
> - shard-iclb: [DMESG-WARN][124] ([i915#3621]) -> [PASS][125]
>[124]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10550/shard-iclb1/igt@kms_big...@yf-tiled-32bpp-rotate-0.html
>[125]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20953/shard-iclb8/igt@kms_big...@yf-tiled-32bpp-rotate-0.html
>
> * igt@kms_color@pipe-a-legacy-gamma-reset:
> - {shard-rkl}:[SKIP][126] ([i915#1849] / [i915#4070]) ->
> [PASS][127] +5 similar issues
>[126]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10550/shard-rkl-2/igt@kms_co...@pipe-a-legacy-gamma-reset.html
>[127]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20953/shard-rkl-6/igt@kms_co...@pipe-a-legacy-gamma-reset.html
>
> * igt@kms_color@pipe-b-ctm-0-5:
> - {shard-rkl}:[SKIP][128] ([i915#1149] / [i915#1849] /
> [i915#4070]) -> [PASS][129] +3 similar issues
>[128]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10550/shard-rkl-2/igt@kms_co...@pipe-b-ctm-0-5.html
>[129]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20953/shard-rkl-6/igt@kms_co...@pipe-b-ctm-0-5.html
>
> * igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding:
> - {shard-rkl}:[SKIP][130] ([fdo#112022] / [i915#4070]) ->
> [PASS][131] +10 similar issues
>[130]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10550/shard-rkl-2/igt@kms_cursor_...@pipe-b-cursor-128x128-sliding.html
>[131]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20953/shard-rkl-6/igt@kms_cursor_...@pipe-b-cursor-128x128-sliding.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-suspend:
> - shard-skl: [INCOMPLETE][132] ([i915#300]) -> [PASS][133]
>[132]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10550/shard-skl3/igt@kms_cursor_...@pipe-c-cursor-suspend.html
>[133]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20953/shard-skl3/igt@kms_cursor_...@pipe-c-cursor-suspend.html
> - shard-kbl: [DMESG-WARN][134] ([i915#180]) -> [PASS][135] +5
> similar issues
>[134]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10550/shard-kbl4/igt@kms_cursor_...@pipe-c-cursor-suspend.html
>[135]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20953/shard-kbl7/igt@kms_cursor_...@pipe-c-cursor-suspend.html
>
> * igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
> - {shard-rkl}:[SKIP][136] ([fdo#111825] / [i915#4070]) ->
> [PASS][137] +3 similar issues
>[136]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10550/shard-rkl-2/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
>[137]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20953/shard-rkl-6/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
> - shard-skl: [FAIL][138] ([i915#2346] / [i915#533]) ->
> [PASS][139]
>[138]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10550/shard-skl5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
>[139]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20953/shard-skl8/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
>
> * igt@kms_draw_crc@draw-method-xrgb-blt-ytiled:
> - {shard-rkl}:[SKIP][140] ([fdo#111314]) -> [PA
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20953/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Update memory bandwidth parameters (rev2)
5]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 > [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 > [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279 > [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 > [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 > [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 > [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#109502]: https://bugs.freedesktop.org/show_bug.cgi?id=109502 > [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 > [fdo#110892]: https://bugs.freedesktop.org/show_bug.cgi?id=110892 > [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 > [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 > [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656 > [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054 > [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132 > [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 > [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 > [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 > [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 > [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 > [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 > [i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369 > [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 > [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 > [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 > [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 > [i915#2828]: https://gitlab.freedesktop.org/drm/intel/issues/2828 > [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 > [i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849 > [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 > [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 > [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 > [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063 > [i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070 > [i915#3288]: https://gitlab.freedesktop.org/drm/intel/issues/3288 > [i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319 > [i915#3343]: https://gitlab.freedesktop.org/drm/intel/issues/3343 > [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 > [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 > [i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467 > [i915#3648]: https://gitlab.freedesktop.org/drm/intel/issues/3648 > [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 > [i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778 > [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 > [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 > [i915#456]: https://gitlab.freedeskt > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21051/index.html -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795
Re: [Intel-gfx] [PATCH] drm/i915/gt: Add "intel_" as prefix in set_mocs_index()
On Thu, Sep 16, 2021 at 11:57:36AM +0530, Ayaz A Siddiqui wrote:
> Adding missing "intel_" prefix in set_mocs_index().
>
> Fixes: b62aa57e3c78 ("drm/i915/gt: Add support of mocs propagation")
> Cc: Matt Roper
> Signed-off-by: Ayaz A Siddiqui
Thanks for fixing this up.
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_mocs.h | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 55e87aff51d2..04b83c9578d5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -682,7 +682,7 @@ int intel_gt_init(struct intel_gt *gt)
> goto err_pm;
> }
>
> - set_mocs_index(gt);
> + intel_set_mocs_index(gt);
>
> err = intel_engines_init(gt);
> if (err)
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index e4b97cd14cf9..15f9ada28a7a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -616,7 +616,7 @@ static u32 global_mocs_offset(void)
> return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
> }
>
> -void set_mocs_index(struct intel_gt *gt)
> +void intel_set_mocs_index(struct intel_gt *gt)
> {
> struct drm_i915_mocs_table table;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h
> b/drivers/gpu/drm/i915/gt/intel_mocs.h
> index 8a09d64b115f..76db827210c0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
> @@ -36,6 +36,6 @@ struct intel_gt;
>
> void intel_mocs_init(struct intel_gt *gt);
> void intel_mocs_init_engine(struct intel_engine_cs *engine);
> -void set_mocs_index(struct intel_gt *gt);
> +void intel_set_mocs_index(struct intel_gt *gt);
>
> #endif
> --
> 2.26.2
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Add "intel_" as prefix in set_mocs_index() (rev2)
tree/drm-tip/Patchwork_21077/fi-kbl-soraka/igt@i915_module_l...@reload.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
> [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
> [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
> [i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
> [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
> [i915#3690]: https://gitlab.freedesktop.org/drm/intel/issues/3690
> [i915#4130]: https://gitlab.freedesktop.org/drm/intel/issues/4130
> [i915#4136]: https://gitlab.freedesktop.org/drm/intel/issues/4136
>
>
> Participating hosts (38 -> 35)
> --
>
> Missing(3): fi-bdw-samus fi-bsw-cyan bat-dg1-6
>
>
> Build changes
> -
>
> * Linux: CI_DRM_10599 -> Patchwork_21077
>
> CI-20190529: 20190529
> CI_DRM_10599: 7517e1f3124126ca9f24627f9494330d155e5ff6 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6211: 7b275b3eb17ddf6e7c5b7b9ba359b7f5345a5311 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_21077: 09f1c5e7cc42089c657204d67f37e60b0375a6c9 @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> == Linux commits ==
>
> 09f1c5e7cc42 drm/i915/gt: Add "intel_" as prefix in set_mocs_index()
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21077/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
[Intel-gfx] [PATCH 0/2] Check SFC fusing on Xe_HP
Xe_HP adds some new fuse bits to indicate whether an SFC unit is fused off. We should utilize these when initializing VD/VE SFC access and also when capturing/dumping SFC_DONE for the error state. Matt Roper (2): drm/i915/xehp: Check new fuse bits for SFC availability drm/i915: Check SFC fusing before recording/dumping SFC_DONE drivers/gpu/drm/i915/gt/intel_engine_cs.c | 25 ++- drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++ drivers/gpu/drm/i915/gt/intel_sseu.c | 5 ++--- drivers/gpu/drm/i915/i915_gpu_error.c | 6 -- drivers/gpu/drm/i915/i915_reg.h | 4 ++-- 5 files changed, 31 insertions(+), 12 deletions(-) -- 2.33.0
[Intel-gfx] [PATCH 2/2] drm/i915: Check SFC fusing before recording/dumping SFC_DONE
On Xe_HP and beyond the SFC unit may be fused off, even if the corresponding media engines are present. Check the SFC-specific fusing before trying to dump the SFC_DONE instances. Cc: José Roberto de Souza Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/i915_gpu_error.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index b9f66dbd46bb..2a2d7643b551 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -753,7 +753,8 @@ static void err_print_gt(struct drm_i915_error_state_buf *m, * only exists if the corresponding VCS engine is * present. */ - if (!HAS_ENGINE(gt->_gt, _VCS(i * 2))) + if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || + !HAS_ENGINE(gt->_gt, _VCS(i * 2))) continue; err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, @@ -1632,7 +1633,8 @@ static void gt_record_regs(struct intel_gt_coredump *gt) * only exists if the corresponding VCS engine is * present. */ - if (!HAS_ENGINE(gt->_gt, _VCS(i * 2))) + if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || + !HAS_ENGINE(gt->_gt, _VCS(i * 2))) continue; gt->sfc_done[i] = -- 2.33.0
