[Intel-gfx] ✓ Fi.CI.IGT: success for i915/display: split and constify vtable

[Patchwork]

== Series Details ==

Series: i915/display: split and constify vtable
URL   : https://patchwork.freedesktop.org/series/94459/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10560_full -> Patchwork_20985_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_20985_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@psr2:
- shard-iclb: [PASS][1] -> [SKIP][2] ([i915#658])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-iclb2/igt@feature_discov...@psr2.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb7/igt@feature_discov...@psr2.html

  * igt@gem_ctx_persistence@engines-hostile:
- shard-snb:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +4 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-snb5/igt@gem_ctx_persiste...@engines-hostile.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][4] -> [FAIL][5] ([i915#2846])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-glk2/igt@gem_exec_f...@basic-deadline.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-glk3/igt@gem_exec_f...@basic-deadline.html
- shard-apl:  NOTRUN -> [FAIL][6] ([i915#2846])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl3/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: NOTRUN -> [FAIL][7] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk:  [PASS][8] -> [FAIL][9] ([i915#2842]) +2 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-glk7/igt@gem_exec_fair@basic-none-r...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-glk4/igt@gem_exec_fair@basic-none-r...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-iclb7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][12] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-tglb1/igt@gem_exec_fair@basic-p...@vcs1.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb1/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_params@no-vebox:
- shard-tglb: NOTRUN -> [SKIP][15] ([fdo#109283])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb1/igt@gem_exec_par...@no-vebox.html

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][16] -> [SKIP][17] ([i915#2190])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-tglb2/igt@gem_huc_c...@huc-copy.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb6/igt@gem_huc_c...@huc-copy.html

  * igt@gem_mmap_gtt@cpuset-big-copy-xy:
- shard-iclb: [PASS][18] -> [FAIL][19] ([i915#2428])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-iclb5/igt@gem_mmap_...@cpuset-big-copy-xy.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb8/igt@gem_mmap_...@cpuset-big-copy-xy.html

  * igt@gem_pread@exhaustion:
- shard-tglb: NOTRUN -> [WARN][20] ([i915#2658])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb1/igt@gem_pr...@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-apl:  NOTRUN -> [WARN][21] ([i915#2658])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl1/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_userptr_blits@coherency-sync:
- shard-tglb: NOTRUN -> [SKIP][22] ([fdo#110542])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb1/igt@gem_userptr_bl...@coherency-sync.html

  * igt@gem_userptr_blits@input-checking:
- shard-skl:  NOTRUN -> [DMESG-WARN][23] ([i915#3002])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl9/igt@gem_userptr_bl...@input-checking.html

  * igt@gem_userptr_blits@vma-merge:
- shard-apl:  NOTRUN -> [FAIL][24] ([i915#3318])
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl8/igt@gem_userptr_bl...@vma-merge.html

  * igt@gem_workaroun

[Intel-gfx] ✓ Fi.CI.IGT: success for Enable GuC submission by default on DG1 (rev3)

[Patchwork]

== Series Details ==

Series: Enable GuC submission by default on DG1 (rev3)
URL   : https://patchwork.freedesktop.org/series/93325/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10560_full -> Patchwork_20986_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_20986_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@psr2:
- shard-iclb: [PASS][1] -> [SKIP][2] ([i915#658])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-iclb2/igt@feature_discov...@psr2.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20986/shard-iclb3/igt@feature_discov...@psr2.html

  * igt@gem_ctx_persistence@engines-hostile:
- shard-snb:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +4 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20986/shard-snb2/igt@gem_ctx_persiste...@engines-hostile.html

  * igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][4] -> [TIMEOUT][5] ([i915#2369] / [i915#2481] 
/ [i915#3070])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-iclb4/igt@gem_...@unwedge-stress.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20986/shard-iclb7/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
- shard-apl:  NOTRUN -> [FAIL][6] ([i915#2846])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20986/shard-apl2/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk:  [PASS][7] -> [FAIL][8] ([i915#2842]) +2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-glk7/igt@gem_exec_fair@basic-none-r...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20986/shard-glk8/igt@gem_exec_fair@basic-none-r...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-iclb7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20986/shard-iclb4/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl:  [PASS][11] -> [FAIL][12] ([i915#2842]) +2 similar 
issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-kbl2/igt@gem_exec_fair@basic-p...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20986/shard-kbl1/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-tglb1/igt@gem_exec_fair@basic-p...@vcs1.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20986/shard-tglb6/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_params@no-vebox:
- shard-tglb: NOTRUN -> [SKIP][15] ([fdo#109283])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20986/shard-tglb1/igt@gem_exec_par...@no-vebox.html

  * igt@gem_pread@exhaustion:
- shard-tglb: NOTRUN -> [WARN][16] ([i915#2658])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20986/shard-tglb1/igt@gem_pr...@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-apl:  NOTRUN -> [WARN][17] ([i915#2658])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20986/shard-apl7/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_userptr_blits@coherency-sync:
- shard-tglb: NOTRUN -> [SKIP][18] ([fdo#110542])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20986/shard-tglb1/igt@gem_userptr_bl...@coherency-sync.html

  * igt@gem_userptr_blits@input-checking:
- shard-skl:  NOTRUN -> [DMESG-WARN][19] ([i915#3002])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20986/shard-skl5/igt@gem_userptr_bl...@input-checking.html

  * igt@gem_userptr_blits@vma-merge:
- shard-apl:  NOTRUN -> [FAIL][20] ([i915#3318])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20986/shard-apl6/igt@gem_userptr_bl...@vma-merge.html

  * igt@gen7_exec_parse@basic-offset:
- shard-apl:  NOTRUN -> [SKIP][21] ([fdo#109271]) +310 similar 
issues
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20986/shard-apl2/igt@gen7_exec_pa...@basic-offset.html

  * igt@gen7_exec_parse@basic-rejected:
- shard-tglb: NOTRUN -> [SKIP][22] ([fdo#109289]) +2 similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20986/shard-tglb2/igt@gen7_exec_pa...@basic-rejected.html

  * igt@gen9_exec_parse@allowed-all:
- shard-glk:  [PASS][23] -> [DMESG-WARN][24] ([i915#1436] / 
[i915#716])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10

Re: [Intel-gfx] [PATCH v2 3/6] drm/i915 Implement LMEM backup and restore for suspend / resume

[Thomas Hellström]

Hi, Matt,

Thanks for reviewing.

On 9/7/21 7:37 PM, Matthew Auld wrote:



+    i915_gem_ww_unlock_single(backup);
+    i915_gem_object_put(backup);


I assume we need to set ttm.backup = NULL somewhere here on the 
failure path, or don't drop the ref? Or at least it looks like 
potential uaf later?


Yes, I think on failure, we just don't drop the ref here in case 
something at some point decides to retry.


I'll fix up this and other comments.

/Thomas





+
+    return err;
+}
+

Re: [Intel-gfx] [PATCH v4] drm/i915: Use Transparent Hugepages when IOMMU is enabled

[Tvrtko Ursulin]

On 07/09/2021 12:13, Eero Tamminen wrote:

Hi,

For completeness sake, it might be worth mentioning specifically what 
(synthetic) test-cases regress with THP patch.


* Skylake GT4e:
   20-25% SynMark TexMem*
   (whereas all MemBW GPU tests either improve or are not affected)

* Broxton J4205:
   7% MemBW GPU texture
   2-3% SynMark TexMem*

* Tigerlake-H:
   7% MemBW GPU blend


Ah right that makes sense. All the entries marker with asterisk under 
the "with patch" list. Okay if I just add an explanation on what does 
the asterisk mean for them at a single place?


And about the Broxton one. In the bug you put "15-20% MemBW GPU texture" 
and "10% SynMark TexMem*" so from where are these numbers now?




I have no idea why on GEN9 texture accesses regress, but on GEN12 TGL 
it's render buffer blend that regresses.


Blend (read+write) regressing is especially odd, as neither render 
buffer read nor write regresses.


Maybe that is a GEN12 specific driver bug similar to Mesa/i965 bug from 
few years back in how its shaders access render buffer, that had caused 
SIMD32 accesses to regress memory BW bound test-cases perf a bit 
compared to SIMD16?


(Blend test is likely to run nowadays as SIMD32.)


No idea on this one from me, leaving to more qualified people to comment.

Regards,

Tvrtko




 - Eero

On 7.9.2021 13.34, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

Usage of Transparent Hugepages was disabled in 9987da4b5dcf
("drm/i915: Disable THP until we have a GPU read BW W/A"), but since it
appears majority of performance regressions reported with an enabled 
IOMMU

can be almost eliminated by turning them on, lets just do that.

To err on the side of safety we keep the current default in cases where
IOMMU is not active, and only when it is default to the 
"huge=within_size"

mode. Although there probably would be wins to enable them throughout,
more extensive testing across benchmarks and platforms would need to be
done.

With the patch and IOMMU enabled my local testing on a small Skylake part
shows OglVSTangent regression being reduced from ~14% (IOMMU on versus
IOMMU off) to ~2% (same comparison but with THP on).

More detailed testing done in the below referenced Gitlab issue by Eero:

Skylake GT4e:

Performance drops from enabling IOMMU:

 30-35% SynMark CSDof
 20-25% Unigine Heaven, MemBW GPU write, SynMark VSTangent
 ~20% GLB Egypt  (1/2 screen window)
 10-15% GLB T-Rex (1/2 screen window)
 8-10% GfxBench T-Rex, MemBW GPU blit
 7-8% SynMark DeferredAA + TerrainFly* + ZBuffer
 6-7% GfxBench Manhattan 3.0 + 3.1, SynMark TexMem128 & CSCloth
 5-6% GfxBench CarChase, Unigine Valley
 3-5% GfxBench Vulkan & GL AztecRuins + ALU2, MemBW GPU texture,
  SynMark Fill*, Deferred, TerrainPan*
 1-2% Most of the other tests

With the patch drops become:

 20-25% SynMark TexMem*
 15-20% GLB Egypt (1/2 screen window)
 10-15% GLB T-Rex (1/2 screen window)
 4-7% GfxBench T-Rex, GpuTest Triangle
 1-8% GfxBench ALU2 (offscreen 1%, onscreen 8%)
 3% GfxBench Manhattan 3.0, SynMark CSDof
 2-3% Unigine Heaven + Valley, MemBW GPU texture
 1-3 GfxBench Manhattan 3.1 + CarChase + Vulkan & GL AztecRuins

Broxton:

Performance drops from IOMMU, without patch:

 30% MemBW GPU write
 25% SynMark ZBuffer + Fill*
 20% MemBW GPU blit
 15% MemBW GPU blend, GpuTest Triangle
 10-15% MemBW GPU texture
 10% GLB Egypt, Unigine Heaven (had hangs), SynMark TerrainFly*
 7-9% GLB T-Rex, GfxBench Manhattan 3.0 + T-Rex,
  SynMark Deferred* + TexMem*
 6-8% GfxBench CarChase, Unigine Valley,
  SynMark CSCloth + ShMapVsm + TerrainPan*
 5-6% GfxBench Manhattan 3.1 + GL AztecRuins,
  SynMark CSDof + TexFilterTri
 2-4% GfxBench ALU2, SynMark DrvRes + GSCloth + ShMapPcf + 
Batch[0-5] +

  TexFilterAniso, GpuTest GiMark + 32-bit Julia

And with patch:

 15-20% MemBW GPU texture
 10% SynMark TexMem*
 8-9% GLB Egypt (1/2 screen window)
 4-5% GLB T-Rex (1/2 screen window)
 3-6% GfxBench Manhattan 3.0, GpuTest FurMark,
  SynMark Deferred + TexFilterTri
 3-4% GfxBench Manhattan 3.1 + T-Rex, SynMark VSInstancing
 2-4% GpuTest Triangle, SynMark DeferredAA
 2-3% Unigine Heaven + Valley
 1-3% SynMark Terrain*
 1-2% GfxBench CarChase, SynMark TexFilterAniso + ZBuffer

Tigerlake-H:

 20-25% MemBW GPU texture
 15-20% GpuTest Triangle
 13-15% SynMark TerrainFly* + DeferredAA + HdrBloom
 8-10% GfxBench Manhattan 3.1, SynMark TerrainPan* + DrvRes
 6-7% GfxBench Manhattan 3.0, SynMark TexMem*
 4-8% GLB onscreen Fill + T-Rex + Egypt (more in onscreen than
  offscreen versions of T-Rex/Egypt)
 4-6% GfxBench CarChase + GLES AztecRuins + ALU2, GpuTest 32-bit 
Julia,

  SynMark CSDof + DrvState
 3-5% GfxBench T-Rex + Egypt, Unigine Heaven + Valley, GpuTest Plot3D
 1-7% Media tests
 2-3% MemBW GPU blit
 1-3% 

Re: [Intel-gfx] [PATCH] drm/i915: deduplicate frequency dump on debugfs

[Jani Nikula]

On Tue, 07 Sep 2021, Lucas De Marchi  wrote:
> Although commit 9dd4b065446a ("drm/i915/gt: Move pm debug files into a
> gt aware debugfs") says it was moving debug files to gt/, the
> i915_frequency_info file was left behind and its implementation copied
> into drivers/gpu/drm/i915/gt/debugfs_gt_pm.c. Over time we had several
> patches having to change both places to keep them in sync (and some
> patches failing to do so). The initial idea was to remove i915_frequency_info,
> but there are user space tools using it. From a quick code search there
> are other scripts and test tools besides igt, so it's not simply
> updating igt to get rid of the older file.
>
> Here we export a function using drm_printer as parameter and make
> both show() implementations to call this same function. Aside from a few
> variable name differences, for i915_frequency_info this brings a few
> lines that were not previously printed: RP UP EI, RP UP THRESHOLD, RP
> DOWN THRESHOLD and RP DOWN EI.  These came in as part of
> commit 9c878557b1eb ("drm/i915/gt: Use the RPM config register to
> determine clk frequencies"), which didn't change both places.
>
> Signed-off-by: Lucas De Marchi 
> ---
>  drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 127 ++---
>  drivers/gpu/drm/i915/gt/debugfs_gt_pm.h |   2 +
>  drivers/gpu/drm/i915/i915_debugfs.c | 227 +---
>  3 files changed, 74 insertions(+), 282 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c 
> b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> index f6733f279890..6a27c011d0ff 100644
> --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> @@ -240,9 +240,8 @@ static int drpc_show(struct seq_file *m, void *unused)
>  }
>  DEFINE_GT_DEBUGFS_ATTRIBUTE(drpc);
>  
> -static int frequency_show(struct seq_file *m, void *unused)
> +void debugfs_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)

The debugfs prefix belongs to debugfs, and I don't think we should have
non-static functions with that prefix.

I know it's in line with what's currently in the file, and I've
complained about it before, but apparently that hasn't been enough.

BR,
Jani.



>  {
> - struct intel_gt *gt = m->private;
>   struct drm_i915_private *i915 = gt->i915;
>   struct intel_uncore *uncore = gt->uncore;
>   struct intel_rps *rps = >->rps;
> @@ -254,21 +253,21 @@ static int frequency_show(struct seq_file *m, void 
> *unused)
>   u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
>   u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
>  
> - seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
> - seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
> - seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) 
> >>
> + drm_printf(p, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
> + drm_printf(p, "Requested VID: %d\n", rgvswctl & 0x3f);
> + drm_printf(p, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) 
> >>
>  MEMSTAT_VID_SHIFT);
> - seq_printf(m, "Current P-state: %d\n",
> + drm_printf(p, "Current P-state: %d\n",
>  (rgvstat & MEMSTAT_PSTATE_MASK) >> 
> MEMSTAT_PSTATE_SHIFT);
>   } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
>   u32 rpmodectl, freq_sts;
>  
>   rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
> - seq_printf(m, "Video Turbo Mode: %s\n",
> + drm_printf(p, "Video Turbo Mode: %s\n",
>  yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
> - seq_printf(m, "HW control enabled: %s\n",
> + drm_printf(p, "HW control enabled: %s\n",
>  yesno(rpmodectl & GEN6_RP_ENABLE));
> - seq_printf(m, "SW control enabled: %s\n",
> + drm_printf(p, "SW control enabled: %s\n",
>  yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
>GEN6_RP_MEDIA_SW_MODE));
>  
> @@ -276,25 +275,25 @@ static int frequency_show(struct seq_file *m, void 
> *unused)
>   freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
>   vlv_punit_put(i915);
>  
> - seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
> - seq_printf(m, "DDR freq: %d MHz\n", i915->mem_freq);
> + drm_printf(p, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
> + drm_printf(p, "DDR freq: %d MHz\n", i915->mem_freq);
>  
> - seq_printf(m, "actual GPU freq: %d MHz\n",
> + drm_printf(p, "actual GPU freq: %d MHz\n",
>  intel_gpu_freq(rps, (freq_sts >> 8) & 0xff));
>  
> - seq_printf(m, "current GPU freq: %d MHz\n",
> + drm_printf(p, "current GPU freq: %d MHz\n",
>  intel_gpu_freq(rps, rps->cur_f

Re: [Intel-gfx] linux-next: build failure after merge of the drm tree

[Daniel Vetter]

On Wed, Sep 8, 2021 at 5:14 AM Masahiro Yamada  wrote:
>
> On Mon, Sep 6, 2021 at 4:34 PM Daniel Vetter  wrote:
> >
> > On Mon, Sep 6, 2021 at 12:49 AM Stephen Rothwell  
> > wrote:
> > > Hi all,
> > >
> > > On Thu, 2 Sep 2021 07:50:38 +1000 Stephen Rothwell 
> > >  wrote:
> > > >
> > > > On Fri, 20 Aug 2021 15:23:34 +0900 Masahiro Yamada 
> > > >  wrote:
> > > > >
> > > > > On Fri, Aug 20, 2021 at 11:33 AM Stephen Rothwell 
> > > > >  wrote:
> > > > > >
> > >  > > After merging the drm tree, today's linux-next build (x86_64 
> > > allmodconfig)
> > > > > > failed like this:
> > > > > >
> > > > > > In file included from drivers/gpu/drm/i915/i915_debugfs.c:39:
> > > > > > drivers/gpu/drm/i915/gt/intel_gt_requests.h:9:10: fatal error: 
> > > > > > stddef.h: No such file or directory
> > > > > > 9 | #include 
> > > > > >   |  ^~
> > > > > >
> > > > > > Caused by commit
> > > > > >
> > > > > >   564f963eabd1 ("isystem: delete global -isystem compile option")
> > > > > >
> > > > > > from the kbuild tree interacting with commit
> > > > > >
> > > > > >   b97060a99b01 ("drm/i915/guc: Update intel_gt_wait_for_idle to 
> > > > > > work with GuC")
> > > > > >
> > > > > > I have applied the following patch for today.
> > > > >
> > > > >
> > > > > Thanks.
> > > > >
> > > > > This fix-up does not depend on my kbuild tree in any way.
> > > > >
> > > > > So, the drm maintainer can apply it to his tree.
> > > > >
> > > > > Perhaps with
> > > > >
> > > > > Fixes: b97060a99b01 ("drm/i915/guc: Update intel_gt_wait_for_idle to
> > > > > work with GuC")
> > > >
> > > > OK, so that didn't happen so I will now apply the merge fix up to the
> > > > merge of the kbuild tree.
> > > >
> > > > > > From: Stephen Rothwell 
> > > > > > Date: Fri, 20 Aug 2021 12:24:19 +1000
> > > > > > Subject: [PATCH] drm/i915: use linux/stddef.h due to "isystem: 
> > > > > > trim/fixup stdarg.h and other headers"
> > > > > >
> > > > > > Signed-off-by: Stephen Rothwell 
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/gt/intel_gt_requests.h | 2 +-
> > > > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.h 
> > > > > > b/drivers/gpu/drm/i915/gt/intel_gt_requests.h
> > > > > > index 51dbe0e3294e..d2969f68dd64 100644
> > > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt_requests.h
> > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.h
> > > > > > @@ -6,7 +6,7 @@
> > > > > >  #ifndef INTEL_GT_REQUESTS_H
> > > > > >  #define INTEL_GT_REQUESTS_H
> > > > > >
> > > > > > -#include 
> > > > > > +#include 
> > > > > >
> > > > > >  struct intel_engine_cs;
> > > > > >  struct intel_gt;
> > > > > > --
> > > > > > 2.32.0
> > >
> > > Ping?  I am still applying this ...
> >
> > Apologies, this fell through a lot of cracks. I applied this to drm-next 
> > now.
>
>
>
> Rather, I was planning to apply this fix to my kbuild tree.
>
> Since you guys did not fix the issue in time,
> I ended up with dropping [1] from my pull request.
>
> I want to get [1] merged in this MW.
>
> If I postponed it, somebody would add new
>  or  inclusion in the next development
> cycle, I will never make it in the mainline.
>
> [1] 
> https://lore.kernel.org/linux-kernel/YQhY40teUJcTc5H4@localhost.localdomain/

Yeah no problem if you apply it too. For that:

Acked-by: Daniel Vetter 

I just figured I make sure this is at least not lost.
-Daniel

>
>
>
>
>
> > Matt/John, as author/committer it's your job to make sure issues and
> > fixes for the stuff you're pushing don't get lost. I'd have expected
> > John to apply this to at least drm-intel-gt-next (it's not even
> > there).
> >
> > Joonas, I think this is the 2nd or 3rd or so issue this release cycle
> > where some compile fix got stuck a bit because drm-intel-gt-next isn't
> > in linux-next. Can we please fix that? It probably needs some changes
> > to the dim script.
> >
> > Cheers, Daniel
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
>
>
>
> --
> Best Regards
> Masahiro Yamada



-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

Re: [Intel-gfx] [PATCH 2/2] drm/i915/uncore: constify the register vtables.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> This reworks the uncore function vtable so that it's constant.

There's a bug in there, see comment inline, with that fixed,

Reviewed-by: Jani Nikula 


>
> Signed-off-by: Dave Airlie 
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 139 +---
>  drivers/gpu/drm/i915/intel_uncore.h |   8 +-
>  2 files changed, 89 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
> b/drivers/gpu/drm/i915/intel_uncore.c
> index d0bbfc320604..0bc6e16fc4e3 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1756,32 +1756,24 @@ __vgpu_write(8)
>  __vgpu_write(16)
>  __vgpu_write(32)
>  
> -#define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \
> -do { \
> - (uncore)->funcs.mmio_writeb = x##_write8; \
> - (uncore)->funcs.mmio_writew = x##_write16; \
> - (uncore)->funcs.mmio_writel = x##_write32; \
> -} while (0)
> -
> -#define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \
> -do { \
> - (uncore)->funcs.mmio_readb = x##_read8; \
> - (uncore)->funcs.mmio_readw = x##_read16; \
> - (uncore)->funcs.mmio_readl = x##_read32; \
> - (uncore)->funcs.mmio_readq = x##_read64; \
> -} while (0)
> -
> -#define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
> -do { \
> - ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \
> - (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \
> -} while (0)
> -
> -#define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
> -do { \
> - ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \
> - (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
> -} while (0)
> +#define MMIO_RAW_WRITE_VFUNCS(x) \
> + .mmio_writeb = x##_write8,   \
> + .mmio_writew = x##_write16,  \
> + .mmio_writel = x##_write32
> +
> +#define MMIO_RAW_READ_VFUNCS(x)\
> + .mmio_readb = x##_read8,  \
> + .mmio_readw = x##_read16, \
> + .mmio_readl = x##_read32, \
> + .mmio_readq = x##_read64
> +
> +#define MMIO_WRITE_FW_VFUNCS(x)  \
> + MMIO_RAW_WRITE_VFUNCS(x),   \
> + .write_fw_domains = x##_reg_write_fw_domains
> +
> +#define MMIO_READ_FW_VFUNCS(x)   \
> + MMIO_RAW_READ_VFUNCS(x),\
> + .read_fw_domains = x##_reg_read_fw_domains
>  
>  static int __fw_domain_init(struct intel_uncore *uncore,
>   enum forcewake_domain_id domain_id,
> @@ -2086,22 +2078,70 @@ void intel_uncore_init_early(struct intel_uncore 
> *uncore,
>   uncore->debug = &i915->mmio_debug;
>  }
>  
> +static const struct intel_uncore_funcs vgpu_funcs = {
> + MMIO_RAW_WRITE_VFUNCS(vgpu),
> + MMIO_RAW_READ_VFUNCS(vgpu),
> +};
> +
> +static const struct intel_uncore_funcs gen5_funcs = {
> + MMIO_RAW_WRITE_VFUNCS(gen5),
> + MMIO_RAW_READ_VFUNCS(gen5),
> +};
> +
> +static const struct intel_uncore_funcs gen2_funcs = {
> + MMIO_RAW_WRITE_VFUNCS(gen2),
> + MMIO_RAW_READ_VFUNCS(gen2),
> +};
> +
> +
>  static void uncore_raw_init(struct intel_uncore *uncore)
>  {
>   GEM_BUG_ON(intel_uncore_has_forcewake(uncore));
>  
>   if (intel_vgpu_active(uncore->i915)) {
> - ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu);
> - ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu);
> + uncore->funcs = &vgpu_funcs;
>   } else if (GRAPHICS_VER(uncore->i915) == 5) {
> - ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
> - ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
> + uncore->funcs = &gen5_funcs;
>   } else {
> - ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2);
> - ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2);
> + uncore->funcs = &gen2_funcs;
>   }
>  }
>  
> +static const struct intel_uncore_funcs xehp_funcs = {
> + MMIO_WRITE_FW_VFUNCS(xehp_fwtable),
> + MMIO_READ_FW_VFUNCS(gen11_fwtable)
> +};
> +
> +static const struct intel_uncore_funcs gen12_funcs = {
> + MMIO_WRITE_FW_VFUNCS(gen12_fwtable),
> + MMIO_READ_FW_VFUNCS(gen12_fwtable)
> +};
> +
> +static const struct intel_uncore_funcs gen11_funcs = {
> + MMIO_WRITE_FW_VFUNCS(gen11_fwtable),
> + MMIO_READ_FW_VFUNCS(gen11_fwtable)
> +};
> +
> +static const struct intel_uncore_funcs gen9_funcs = {
> + MMIO_WRITE_FW_VFUNCS(fwtable),
> + MMIO_READ_FW_VFUNCS(fwtable)
> +};
> +
> +static const struct intel_uncore_funcs gen8_funcs = {
> + MMIO_WRITE_FW_VFUNCS(gen8),
> + MMIO_READ_FW_VFUNCS(gen6)
> +};
> +
> +static const struct intel_uncore_funcs vlv_funcs = {
> + MMIO_WRITE_FW_VFUNCS(gen8),

Should be gen6.

> + MMIO_READ_FW_VFUNCS(fwtable)
> +};
> +
> +static const struct intel_uncore_funcs gen6_funcs = {
> + MMIO_WRITE_FW_VFUNCS(gen6),
> + MMIO_READ_FW_VFUNCS(gen6)
> +};
> +
>  static int uncore_forcewake_init(struct intel_uncore *uncore)
>  {
>   struct drm_i915_private *i915 = uncore->i915;
> @@ -2116,38 +2156,29 @

Re: [Intel-gfx] [PATCH] drm/i915: Get PM ref before accessing HW register

[Tvrtko Ursulin]

On 08/09/2021 00:27, Vinay Belgaumkar wrote:

Seeing these errors when GT is likely in suspend state-
"RPM wakelock ref not held during HW access"

Ensure GT is awake before trying to access HW registers. Avoid
reading the register if that is not the case.

Signed-off-by: Vinay Belgaumkar 


Fixes: 41e5c17ebfc2 ("drm/i915/guc/slpc: Sysfs hooks for SLPC")
Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko


---
  drivers/gpu/drm/i915/gt/intel_rps.c | 8 +++-
  1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 3489f5f0cac1..e1a198bbd135 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1969,8 +1969,14 @@ u32 intel_rps_read_actual_frequency(struct intel_rps 
*rps)
  u32 intel_rps_read_punit_req(struct intel_rps *rps)
  {
struct intel_uncore *uncore = rps_to_uncore(rps);
+   struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm;
+   intel_wakeref_t wakeref;
+   u32 freq = 0;
  
-	return intel_uncore_read(uncore, GEN6_RPNSWREQ);

+   with_intel_runtime_pm_if_in_use(rpm, wakeref)
+   freq = intel_uncore_read(uncore, GEN6_RPNSWREQ);
+
+   return freq;
  }
  
  static u32 intel_rps_get_req(u32 pureq)

Re: [Intel-gfx] [PATCH 1/2] drm/i915/uncore: split the fw get function into separate vfunc

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> constify it while here. drop the put function since it was never
> overloaded and always has done the same thing, no point in
> indirecting it for show.
>
> Signed-off-by: Dave Airlie 
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 62 +++--
>  drivers/gpu/drm/i915/intel_uncore.h |  7 ++--
>  2 files changed, 36 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 6b38bc2811c1..d0bbfc320604 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -396,7 +396,7 @@ intel_uncore_fw_release_timer(struct hrtimer *timer)
>  
>   GEM_BUG_ON(!domain->wake_count);
>   if (--domain->wake_count == 0)
> - uncore->funcs.force_wake_put(uncore, domain->mask);
> + fw_domains_put(uncore, domain->mask);
>  
>   spin_unlock_irqrestore(&uncore->lock, irqflags);
>  
> @@ -454,7 +454,7 @@ intel_uncore_forcewake_reset(struct intel_uncore *uncore)
>  
>   fw = uncore->fw_domains_active;
>   if (fw)
> - uncore->funcs.force_wake_put(uncore, fw);
> + fw_domains_put(uncore, fw);

I kind of dislike the asymmetry of get remaining a vfunc and put being
called directly in code.

How about making fw_domains_get() a thin wrapper that calls the
appropriate vfunc? Something like this, incorporated into your series:

--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -248,7 +248,7 @@ fw_domain_put(const struct intel_uncore_forcewake_domain *d)
 }
 
 static void
-fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
+fw_domains_get_normal(struct intel_uncore *uncore, enum forcewake_domains 
fw_domains)
 {
struct intel_uncore_forcewake_domain *d;
unsigned int tmp;
@@ -266,6 +266,12 @@ fw_domains_get(struct intel_uncore *uncore, enum 
forcewake_domains fw_domains)
uncore->fw_domains_active |= fw_domains;
 }
 
+static void
+fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
+{
+   uncore->funcs.force_wake_get(uncore, fw_domains);
+}
+
 static void
 fw_domains_get_with_fallback(struct intel_uncore *uncore,
 enum forcewake_domains fw_domains)
@@ -340,7 +346,7 @@ static void __gen6_gt_wait_for_thread_c0(struct 
intel_uncore *uncore)
 static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
  enum forcewake_domains fw_domains)
 {
-   fw_domains_get(uncore, fw_domains);
+   fw_domains_get_normal(uncore, fw_domains);
 
/* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
__gen6_gt_wait_for_thread_c0(uncore);
@@ -1893,7 +1899,7 @@ static int intel_uncore_fw_domains_init(struct 
intel_uncore *uncore)
fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
   FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
-   uncore->funcs.force_wake_get = fw_domains_get;
+   uncore->funcs.force_wake_get = fw_domains_get_normal;
uncore->funcs.force_wake_put = fw_domains_put;
fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
   FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);

The call sites will look nice and symmetrical, and the compiler will
inline the call away.

Other than that, and the fact that this fails to apply and thus doesn't
give us CI results,


Reviewed-by: Jani Nikula 


>  
>   fw_domains_reset(uncore, uncore->fw_domains);
>   assert_forcewakes_inactive(uncore);
> @@ -562,7 +562,7 @@ static void forcewake_early_sanitize(struct intel_uncore 
> *uncore,
>   intel_uncore_forcewake_reset(uncore);
>   if (restore_forcewake) {
>   spin_lock_irq(&uncore->lock);
> - uncore->funcs.force_wake_get(uncore, restore_forcewake);
> + uncore->fw_get_funcs->force_wake_get(uncore, restore_forcewake);
>  
>   if (intel_uncore_has_fifo(uncore))
>   uncore->fifo_count = fifo_free_entries(uncore);
> @@ -623,7 +623,7 @@ static void __intel_uncore_forcewake_get(struct 
> intel_uncore *uncore,
>   }
>  
>   if (fw_domains)
> - uncore->funcs.force_wake_get(uncore, fw_domains);
> + uncore->fw_get_funcs->force_wake_get(uncore, fw_domains);
>  }
>  
>  /**
> @@ -644,7 +644,7 @@ void intel_uncore_forcewake_get(struct intel_uncore 
> *uncore,
>  {
>   unsigned long irqflags;
>  
> - if (!uncore->funcs.force_wake_get)
> + if (!uncore->fw_get_funcs)
>   return;
>  
>   assert_rpm_wakelock_held(uncore->rpm);
> @@ -711,7 +711,7 @@ void intel_uncore_forcewake_get__locked(struct 
> intel_uncore *uncore,
>  {
>   lockdep_assert_held(&uncore->lock);
>  
> - if (!uncore->funcs.force_wake_get)

Re: [Intel-gfx] [PATCH 03/21] drm/i915/wm: move the update watermark wrapper to display side.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> A vague goal is to have the vfunc table be the api between
> wm and display, not having direction function calls cross
> the boundary.
>
> This aligns the legacy update_wm with the newer vfuncs.
>
> The comment probably needs to live somewhere else, it seems
> like it should live in the pm side though not the display side,
> but I brought it along for the ride.
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 40 
>  drivers/gpu/drm/i915/intel_pm.c  | 39 ---
>  drivers/gpu/drm/i915/intel_pm.h  |  1 -
>  3 files changed, 40 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d95283bf2631..b495371c1889 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c

We haven't been axing stuff out of intel_display.c so we could add
somethign else back! ;)

A new file for watermarks or display pm? Ville?

BR,
Jani.



> @@ -125,6 +125,46 @@ static void ilk_pfit_enable(const struct 
> intel_crtc_state *crtc_state);
>  static void intel_modeset_setup_hw_state(struct drm_device *dev,
>struct drm_modeset_acquire_ctx *ctx);
>  
> +
> +/**
> + * intel_update_watermarks - update FIFO watermark values based on current 
> modes
> + * @crtc: the #intel_crtc on which to compute the WM
> + *
> + * Calculate watermark values for the various WM regs based on current mode
> + * and plane configuration.
> + *
> + * There are several cases to deal with here:
> + *   - normal (i.e. non-self-refresh)
> + *   - self-refresh (SR) mode
> + *   - lines are large relative to FIFO size (buffer can hold up to 2)
> + *   - lines are small relative to FIFO size (buffer can hold more than 2
> + * lines), so need to account for TLB latency
> + *
> + *   The normal calculation is:
> + * watermark = dotclock * bytes per pixel * latency
> + *   where latency is platform & configuration dependent (we assume pessimal
> + *   values here).
> + *
> + *   The SR calculation is:
> + * watermark = (trunc(latency/line time)+1) * surface width *
> + *   bytes per pixel
> + *   where
> + * line time = htotal / dotclock
> + * surface width = hdisplay for normal plane and 64 for cursor
> + *   and latency is assumed to be high, as above.
> + *
> + * The final value programmed to the register should always be rounded up,
> + * and include an extra 2 entries to account for clock crossings.
> + *
> + * We don't use the sprite, so we can ignore that.  And on Crestline we have
> + * to set the non-SR watermarks to 8.
> + */
> +static void intel_update_watermarks(struct drm_i915_private *dev_priv)
> +{
> + if (dev_priv->display.update_wm)
> + dev_priv->display.update_wm(dev_priv);
> +}
> +
>  /* returns HPLL frequency in kHz */
>  int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
>  {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 406baa49e6ad..4054c6f7a2f9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7132,45 +7132,6 @@ void ilk_wm_get_hw_state(struct drm_i915_private 
> *dev_priv)
>   !(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & 
> DISP_FBC_WM_DIS);
>  }
>  
> -/**
> - * intel_update_watermarks - update FIFO watermark values based on current 
> modes
> - * @crtc: the #intel_crtc on which to compute the WM
> - *
> - * Calculate watermark values for the various WM regs based on current mode
> - * and plane configuration.
> - *
> - * There are several cases to deal with here:
> - *   - normal (i.e. non-self-refresh)
> - *   - self-refresh (SR) mode
> - *   - lines are large relative to FIFO size (buffer can hold up to 2)
> - *   - lines are small relative to FIFO size (buffer can hold more than 2
> - * lines), so need to account for TLB latency
> - *
> - *   The normal calculation is:
> - * watermark = dotclock * bytes per pixel * latency
> - *   where latency is platform & configuration dependent (we assume pessimal
> - *   values here).
> - *
> - *   The SR calculation is:
> - * watermark = (trunc(latency/line time)+1) * surface width *
> - *   bytes per pixel
> - *   where
> - * line time = htotal / dotclock
> - * surface width = hdisplay for normal plane and 64 for cursor
> - *   and latency is assumed to be high, as above.
> - *
> - * The final value programmed to the register should always be rounded up,
> - * and include an extra 2 entries to account for clock crossings.
> - *
> - * We don't use the sprite, so we can ignore that.  And on Crestline we have
> - * to set the non-SR watermarks to 8.
> - */
> -void intel_update_watermarks(struct drm_i915_private *dev_priv)
> -{
> - if (dev_priv->display.update_wm)
> - dev_priv->display.update_wm(dev_p

[Intel-gfx] [RFC 0/5] Panel replay phase1 implementation

[Animesh Manna]

Panel Replay is a power saving feature for DP 2.0 monitor and similar
to PSR on EDP.

These patches are basic enablement patches and reused psr
framework to add panel replay related new changes which
may need further fine tuning to fill the gap if there is any.

Note: The patches are not tested due to unavailability of monitor

Animesh Manna (5):
  drm/i915/panelreplay: update plane selective fetch register definition
  drm/i915/panelreplay: Feature flag added for panel replay
  drm/i915/panelreplay: Initializaton and compute config for panel
replay
  drm/i915/panelreplay: enable/disable panel replay
  drm/i915/panelreplay: Added state checker for panel replay state

 drivers/gpu/drm/i915/display/intel_display.c  |  1 +
 .../drm/i915/display/intel_display_types.h|  4 +
 drivers/gpu/drm/i915/display/intel_dp.c   | 47 +--
 drivers/gpu/drm/i915/display/intel_psr.c  | 82 +--
 drivers/gpu/drm/i915/display/intel_psr.h  |  3 +
 drivers/gpu/drm/i915/i915_drv.h   |  1 +
 drivers/gpu/drm/i915/i915_pci.c   |  1 +
 drivers/gpu/drm/i915/i915_reg.h   | 33 
 drivers/gpu/drm/i915/intel_device_info.h  |  1 +
 include/drm/drm_dp_helper.h   |  6 ++
 10 files changed, 147 insertions(+), 32 deletions(-)

-- 
2.29.0

[Intel-gfx] [RFC 1/5] drm/i915/panelreplay: update plane selective fetch register definition

[Animesh Manna]

Panel replay can be enabled for all pipes driving DP 2.0 monitor,
so updated the plane selective fetch register difinition accordingly.

Signed-off-by: Animesh Manna 
---
 drivers/gpu/drm/i915/display/intel_psr.c |  8 +++---
 drivers/gpu/drm/i915/i915_reg.h  | 32 +---
 2 files changed, 22 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 3f6fb7d67f84..5fa76b148f6d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1445,7 +1445,7 @@ void intel_psr2_program_plane_sel_fetch(struct 
intel_plane *plane,
 
val = plane_state ? plane_state->ctl : 0;
val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE;
-   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val);
+   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(dev_priv, pipe, 
plane->id), val);
if (!val || plane->id == PLANE_CURSOR)
return;
 
@@ -1453,19 +1453,19 @@ void intel_psr2_program_plane_sel_fetch(struct 
intel_plane *plane,
 
val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
val |= plane_state->uapi.dst.x1;
-   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
+   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(dev_priv, pipe, 
plane->id), val);
 
/* TODO: consider auxiliary surfaces */
x = plane_state->uapi.src.x1 >> 16;
y = (plane_state->uapi.src.y1 >> 16) + clip->y1;
val = y << 16 | x;
-   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
+   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(dev_priv, pipe, 
plane->id),
  val);
 
/* Sizes are 0 based */
val = (drm_rect_height(clip) - 1) << 16;
val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
-   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
+   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(dev_priv, pipe, 
plane->id), val);
 }
 
 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state 
*crtc_state)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2853cc005ee..5bc8f22fa9a8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7471,6 +7471,7 @@ enum {
 #define _SEL_FETCH_PLANE_BASE_7_A  0x70960
 #define _SEL_FETCH_PLANE_BASE_CUR_A0x70880
 #define _SEL_FETCH_PLANE_BASE_1_B  0x70990
+#define _DG2_SEL_FETCH_PLANE_BASE_1_B  0x71890
 
 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
 _SEL_FETCH_PLANE_BASE_1_A, \
@@ -7481,31 +7482,34 @@ enum {
 _SEL_FETCH_PLANE_BASE_6_A, \
 _SEL_FETCH_PLANE_BASE_7_A, \
 _SEL_FETCH_PLANE_BASE_CUR_A)
-#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, 
_SEL_FETCH_PLANE_BASE_1_B)
-#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
-   _SEL_FETCH_PLANE_BASE_1_A + \
-   _SEL_FETCH_PLANE_BASE_A(plane))
+#define _SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) _PIPE(pipe, 
_SEL_FETCH_PLANE_BASE_1_A, \
+ DISPLAY_VER(dev_priv) > 
12 ? \
+ 
_DG2_SEL_FETCH_PLANE_BASE_1_B : \
+ _SEL_FETCH_PLANE_BASE_1_B)
+#define _SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) 
(_SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) - \
+ _SEL_FETCH_PLANE_BASE_1_A 
+ \
+ 
_SEL_FETCH_PLANE_BASE_A(plane))
 
 #define _SEL_FETCH_PLANE_CTL_1_A   0x70890
-#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, 
plane) + \
+#define PLANE_SEL_FETCH_CTL(dev_priv, pipe, plane) 
_MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
   _SEL_FETCH_PLANE_CTL_1_A - \
   _SEL_FETCH_PLANE_BASE_1_A)
 #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31)
 
 #define _SEL_FETCH_PLANE_POS_1_A   0x70894
-#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, 
plane) + \
-  _SEL_FETCH_PLANE_POS_1_A - \
-  _SEL_FETCH_PLANE_BASE_1_A)
+#define PLANE_SEL_FETCH_POS(dev_priv, pipe, plane) 
_MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
+
_SEL_FETCH_PLANE_POS_1_A - \
+

[Intel-gfx] [RFC 2/5] drm/i915/panelreplay: Feature flag added for panel replay

[Animesh Manna]

Platforms having Display 13 and above will support panel
replay feature of DP 2.0 monitor. Added a feature flag
for panel replay.

Signed-off-by: Animesh Manna 
---
 drivers/gpu/drm/i915/i915_drv.h  | 1 +
 drivers/gpu/drm/i915/i915_pci.c  | 1 +
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1fd3040b6771..5b26d7c09b2d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1645,6 +1645,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_DDI(dev_priv)   (INTEL_INFO(dev_priv)->display.has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) 
(INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 #define HAS_PSR(dev_priv)   (INTEL_INFO(dev_priv)->display.has_psr)
+#define HAS_PR(dev_priv)(INTEL_INFO(dev_priv)->display.has_pr)
 #define HAS_PSR_HW_TRACKING(dev_priv) \
(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 #define HAS_PSR2_SEL_FETCH(dev_priv)(GRAPHICS_VER(dev_priv) >= 12)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d4a6a9dcf182..c58bd19b5bdf 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -946,6 +946,7 @@ static const struct intel_device_info adl_s_info = {
.display.has_hotplug = 1,   
\
.display.has_ipc = 1,   
\
.display.has_psr = 1,   
\
+   .display.has_pr = 1,\
.display.ver = 13,  
\
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 
\
.pipe_offsets = {   
\
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index d328bb95c49b..4552a1f88568 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -161,6 +161,7 @@ enum intel_ppgtt_type {
func(has_modular_fia); \
func(has_overlay); \
func(has_psr); \
+   func(has_pr); \
func(has_psr_hw_tracking); \
func(overlay_needs_physical); \
func(supports_tv);
-- 
2.29.0

[Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay

[Animesh Manna]

As panel replay feature similar to PSR feature of EDP panel, so currently
utilized existing psr framework for panel replay.

Signed-off-by: Animesh Manna 
---
 .../drm/i915/display/intel_display_types.h|  4 ++
 drivers/gpu/drm/i915/display/intel_dp.c   | 47 +++
 drivers/gpu/drm/i915/display/intel_psr.c  | 43 +
 drivers/gpu/drm/i915/display/intel_psr.h  |  3 ++
 include/drm/drm_dp_helper.h   |  3 ++
 5 files changed, 91 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index c7bcf9183447..6ca9fabb9333 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1066,6 +1066,7 @@ struct intel_crtc_state {
bool req_psr2_sdp_prior_scanline;
u32 dc3co_exitline;
u16 su_y_granularity;
+   bool has_panel_replay;
 
/*
 * Frequence the dpll for the port should run at. Differs from the
@@ -1526,6 +1527,8 @@ struct intel_psr {
bool irq_aux_error;
u16 su_w_granularity;
u16 su_y_granularity;
+   bool sink_pr_support;
+   bool pr_enabled;
u32 dc3co_exitline;
u32 dc3co_exit_delay;
struct delayed_work dc3co_work;
@@ -1552,6 +1555,7 @@ struct intel_dp {
u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
u8 fec_capable;
u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
+   u8 pr_dpcd;
/* source rates */
int num_source_rates;
const int *source_rates;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index d28bd8c4a8a5..90c708548811 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1560,12 +1560,22 @@ static void intel_dp_compute_vsc_colorimetry(const 
struct intel_crtc_state *crtc
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-   /*
-* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
-* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
-* Colorimetry Format indication.
-*/
-   vsc->revision = 0x5;
+   if (crtc_state->has_panel_replay) {
+   /*
+* Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+* VSC SDP supporting 3D stereo, Panel Replay, and Pixel
+* Encoding/Colorimetry Format indication.
+*/
+   vsc->revision = 0x7;
+   } else {
+   /*
+* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+* Colorimetry Format indication.
+*/
+   vsc->revision = 0x5;
+   }
+
vsc->length = 0x13;
 
/* DP 1.4a spec, Table 2-120 */
@@ -1674,6 +1684,22 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp 
*intel_dp,
vsc->revision = 0x4;
vsc->length = 0xe;
}
+   } else if (intel_dp->psr.pr_enabled) {
+   if (intel_dp->psr.colorimetry_support &&
+   intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+   /* [PR, +Colorimetry] */
+   intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+vsc);
+   } else {
+   /*
+* [PR, -Colorimetry]
+* Prepare VSC Header for SU as per DP 2.0 spec, Table 
2-223
+* VSC SDP supporting 3D stereo + PR (applies to eDP 
v1.3 or
+* higher).
+*/
+   vsc->revision = 0x6;
+   vsc->length = 0x10;
+   }
} else {
/*
 * [PSR1]
@@ -1814,6 +1840,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
intel_vrr_compute_config(pipe_config, conn_state);
intel_psr_compute_config(intel_dp, pipe_config);
+   intel_panel_replay_compute_config(intel_dp, pipe_config);
intel_drrs_compute_config(intel_dp, pipe_config, output_bpp,
  constant_n);
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
@@ -2719,10 +2746,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct 
drm_dp_vsc_sdp *vsc,
sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
 
/*
-* Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
-* per DP 1.4a spec.
+* Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
+* per DP 1.4a spec and DP 2.0 spec respectively.
 */
-  

[Intel-gfx] [RFC 4/5] drm/i915/panelreplay: enable/disable panel replay

[Animesh Manna]

TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.

Signed-off-by: Animesh Manna 
---
 drivers/gpu/drm/i915/display/intel_psr.c | 30 
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 include/drm/drm_dp_helper.h  |  3 +++
 3 files changed, 29 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 660e19c10aa8..1dc6b340d745 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -369,8 +369,12 @@ static void intel_psr_enable_sink(struct intel_dp 
*intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u8 dpcd_val = DP_PSR_ENABLE;
 
-   /* Enable ALPM at sink for psr2 */
-   if (intel_dp->psr.psr2_enabled) {
+   if (intel_dp->psr.pr_enabled) {
+   drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
+  PANEL_REPLAY_ENABLE);
+   return;
+   } else if (intel_dp->psr.psr2_enabled) {
+   /* Enable ALPM at sink for psr2 */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
   DP_ALPM_ENABLE |
   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
@@ -497,6 +501,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp 
*intel_dp)
return val;
 }
 
+static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
+{
+   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+   intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
+  ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE);
+
+   intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
+TRANS_DP2_PANEL_REPLAY_ENABLE);
+}
+
 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 {
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1077,8 +1092,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
lockdep_assert_held(&intel_dp->psr.lock);
 
-   /* psr1 and psr2 are mutually exclusive.*/
-   if (intel_dp->psr.psr2_enabled)
+   /* psr1, psr2 and panel-replay are mutually exclusive.*/
+   if (intel_dp->psr.pr_enabled)
+   dg2_activate_panel_replay(intel_dp);
+   else if (intel_dp->psr.psr2_enabled)
hsw_activate_psr2(intel_dp);
else
hsw_activate_psr1(intel_dp);
@@ -1267,7 +1284,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
return;
}
 
-   if (intel_dp->psr.psr2_enabled) {
+   if (intel_dp->psr.pr_enabled) {
+   intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
+TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
+   } else if (intel_dp->psr.psr2_enabled) {
tgl_disallow_dc3co_on_psr2_exit(intel_dp);
val = intel_de_read(dev_priv,
EDP_PSR2_CTL(intel_dp->psr.transcoder));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5bc8f22fa9a8..9effbc6e5539 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4720,6 +4720,7 @@ enum {
 #define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
 #define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME  REG_BIT(2)
 #define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE  REG_BIT(1)
+#define  ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)
 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK   REG_GENMASK(28, 
16)
 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)   
REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 
0)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1b4dcee3b281..63face4e4f6f 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -707,6 +707,9 @@ struct drm_panel;
 #define DP_BRANCH_DEVICE_CTRL  0x1a1
 # define DP_BRANCH_DEVICE_IRQ_HPD  (1 << 0)
 
+#define PANEL_REPLAY_CONFIG 0x1b0
+# define PANEL_REPLAY_ENABLE(1 << 0)
+
 #define DP_PAYLOAD_ALLOCATE_SET0x1c0
 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
-- 
2.29.0

[Intel-gfx] [RFC 5/5] drm/i915/panelreplay: Added state checker for panel replay state

[Animesh Manna]

has_panel_replay flag is used to check panel replay state
which is part of crtc_state structure.

Signed-off-by: Animesh Manna 
---
 drivers/gpu/drm/i915/display/intel_display.c | 1 +
 drivers/gpu/drm/i915/display/intel_psr.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 134c792e1dbd..0dcfee8b459d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8090,6 +8090,7 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
PIPE_CONF_CHECK_BOOL(has_psr);
PIPE_CONF_CHECK_BOOL(has_psr2);
PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
+   PIPE_CONF_CHECK_BOOL(has_panel_replay);
PIPE_CONF_CHECK_I(dc3co_exitline);
}
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 1dc6b340d745..b5eb78e9397e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1058,6 +1058,7 @@ void intel_psr_get_config(struct intel_encoder *encoder,
 */
pipe_config->has_psr = true;
pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
+   pipe_config->has_panel_replay = intel_dp->psr.pr_enabled;
pipe_config->infoframes.enable |= 
intel_hdmi_infoframe_enable(DP_SDP_VSC);
 
if (!intel_dp->psr.psr2_enabled)
-- 
2.29.0

Re: [Intel-gfx] [PATCH 05/21] drm/i915: split watermark vfuncs from display vtable.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> These are the watermark api between display and pm.
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 54 ++--
>  drivers/gpu/drm/i915/i915_drv.h  | 24 ++---
>  drivers/gpu/drm/i915/intel_pm.c  | 40 +++
>  3 files changed, 63 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b495371c1889..b1202ede3fb0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -161,8 +161,8 @@ static void intel_modeset_setup_hw_state(struct 
> drm_device *dev,
>   */
>  static void intel_update_watermarks(struct drm_i915_private *dev_priv)
>  {
> - if (dev_priv->display.update_wm)
> - dev_priv->display.update_wm(dev_priv);
> + if (dev_priv->wm_disp.update_wm)
> + dev_priv->wm_disp.update_wm(dev_priv);
>  }
>  
>  /* returns HPLL frequency in kHz */
> @@ -2566,8 +2566,8 @@ static void intel_pre_plane_update(struct 
> intel_atomic_state *state,
>* we'll continue to update watermarks the old way, if flags 
> tell
>* us to.
>*/
> - if (dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state, crtc);
> + if (dev_priv->wm_disp.initial_watermarks)
> + dev_priv->wm_disp.initial_watermarks(state, crtc);
>   else if (new_crtc_state->update_wm_pre)
>   intel_update_watermarks(dev_priv);

Having an intel_initial_watermarks() wrapper similar to
intel_update_watermarks() to do the vfunc call would make this patch
nice and tidy.


>   }
> @@ -2941,8 +2941,8 @@ static void ilk_crtc_enable(struct intel_atomic_state 
> *state,
>   /* update DSPCNTR to configure gamma for pipe bottom color */
>   intel_disable_primary_plane(new_crtc_state);
>  
> - if (dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state, crtc);
> + if (dev_priv->wm_disp.initial_watermarks)
> + dev_priv->wm_disp.initial_watermarks(state, crtc);
>   intel_enable_pipe(new_crtc_state);
>  
>   if (new_crtc_state->has_pch_encoder)
> @@ -3152,8 +3152,8 @@ static void hsw_crtc_enable(struct intel_atomic_state 
> *state,
>   if (DISPLAY_VER(dev_priv) >= 11)
>   icl_set_pipe_chicken(new_crtc_state);
>  
> - if (dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state, crtc);
> + if (dev_priv->wm_disp.initial_watermarks)
> + dev_priv->wm_disp.initial_watermarks(state, crtc);
>  
>   if (DISPLAY_VER(dev_priv) >= 11) {
>   const struct intel_dbuf_state *dbuf_state =
> @@ -3570,7 +3570,7 @@ static void valleyview_crtc_enable(struct 
> intel_atomic_state *state,
>   /* update DSPCNTR to configure gamma for pipe bottom color */
>   intel_disable_primary_plane(new_crtc_state);
>  
> - dev_priv->display.initial_watermarks(state, crtc);
> + dev_priv->wm_disp.initial_watermarks(state, crtc);
>   intel_enable_pipe(new_crtc_state);
>  
>   intel_crtc_vblank_on(new_crtc_state);
> @@ -3613,8 +3613,8 @@ static void i9xx_crtc_enable(struct intel_atomic_state 
> *state,
>   /* update DSPCNTR to configure gamma for pipe bottom color */
>   intel_disable_primary_plane(new_crtc_state);
>  
> - if (dev_priv->display.initial_watermarks)
> - dev_priv->display.initial_watermarks(state, crtc);
> + if (dev_priv->wm_disp.initial_watermarks)
> + dev_priv->wm_disp.initial_watermarks(state, crtc);
>   else
>   intel_update_watermarks(dev_priv);
>   intel_enable_pipe(new_crtc_state);
> @@ -3682,7 +3682,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state 
> *state,
>   if (DISPLAY_VER(dev_priv) != 2)
>   intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>  
> - if (!dev_priv->display.initial_watermarks)
> + if (!dev_priv->wm_disp.initial_watermarks)
>   intel_update_watermarks(dev_priv);
>  
>   /* clock the pipe down to 640x480@60 to potentially save power */
> @@ -6790,8 +6790,8 @@ static int intel_crtc_atomic_check(struct 
> intel_atomic_state *state,
>   return ret;
>   }
>  
> - if (dev_priv->display.compute_pipe_wm) {
> - ret = dev_priv->display.compute_pipe_wm(state, crtc);
> + if (dev_priv->wm_disp.compute_pipe_wm) {
> + ret = dev_priv->wm_disp.compute_pipe_wm(state, crtc);
>   if (ret) {
>   drm_dbg_kms(&dev_priv->drm,
>   "Target pipe watermarks are invalid\n");
> @@ -6800,9 +6800,9 @@ static int intel_crtc_atomic_check(struct 
> intel_atomic_state *state,
>  
>   }
>  
> - if (dev_p

Re: [Intel-gfx] [PATCH 06/21] drm/i915: split color functions from display vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> These are only used internally in the color module

I think this patch is a testament to my comment on wrappers for calling
vfuncs. It's all intel_color.c implementation details.

Reviewed-by: Jani Nikula 

I might nitpick on the choice of naming for the struct
drm_i915_display_color_funcs; generally display stuff (for whatever
historical reasons) uses intel_ prefix all over the place. And in this
case, I don't think there's any need to emphasize display, so I'd just
make it struct intel_color_funcs.

*shrug*


BR,
Jani.

> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 64 +++---
>  drivers/gpu/drm/i915/i915_drv.h| 39 +++--
>  2 files changed, 54 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c 
> b/drivers/gpu/drm/i915/display/intel_color.c
> index afcb4bf3826c..ed79075158dd 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct 
> intel_crtc_state *crtc_state)
>  {
>   struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
> - dev_priv->display.load_luts(crtc_state);
> + dev_priv->color_funcs.load_luts(crtc_state);
>  }
>  
>  void intel_color_commit(const struct intel_crtc_state *crtc_state)
>  {
>   struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
> - dev_priv->display.color_commit(crtc_state);
> + dev_priv->color_funcs.color_commit(crtc_state);
>  }
>  
>  static bool intel_can_preload_luts(const struct intel_crtc_state 
> *new_crtc_state)
> @@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state 
> *crtc_state)
>  {
>   struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
> - return dev_priv->display.color_check(crtc_state);
> + return dev_priv->color_funcs.color_check(crtc_state);
>  }
>  
>  void intel_color_get_config(struct intel_crtc_state *crtc_state)
>  {
>   struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
> - if (dev_priv->display.read_luts)
> - dev_priv->display.read_luts(crtc_state);
> + if (dev_priv->color_funcs.read_luts)
> + dev_priv->color_funcs.read_luts(crtc_state);
>  }
>  
>  static bool need_plane_update(struct intel_plane *plane,
> @@ -2101,51 +2101,51 @@ void intel_color_init(struct intel_crtc *crtc)
>  
>   if (HAS_GMCH(dev_priv)) {
>   if (IS_CHERRYVIEW(dev_priv)) {
> - dev_priv->display.color_check = chv_color_check;
> - dev_priv->display.color_commit = i9xx_color_commit;
> - dev_priv->display.load_luts = chv_load_luts;
> - dev_priv->display.read_luts = chv_read_luts;
> + dev_priv->color_funcs.color_check = chv_color_check;
> + dev_priv->color_funcs.color_commit = i9xx_color_commit;
> + dev_priv->color_funcs.load_luts = chv_load_luts;
> + dev_priv->color_funcs.read_luts = chv_read_luts;
>   } else if (DISPLAY_VER(dev_priv) >= 4) {
> - dev_priv->display.color_check = i9xx_color_check;
> - dev_priv->display.color_commit = i9xx_color_commit;
> - dev_priv->display.load_luts = i965_load_luts;
> - dev_priv->display.read_luts = i965_read_luts;
> + dev_priv->color_funcs.color_check = i9xx_color_check;
> + dev_priv->color_funcs.color_commit = i9xx_color_commit;
> + dev_priv->color_funcs.load_luts = i965_load_luts;
> + dev_priv->color_funcs.read_luts = i965_read_luts;
>   } else {
> - dev_priv->display.color_check = i9xx_color_check;
> - dev_priv->display.color_commit = i9xx_color_commit;
> - dev_priv->display.load_luts = i9xx_load_luts;
> - dev_priv->display.read_luts = i9xx_read_luts;
> + dev_priv->color_funcs.color_check = i9xx_color_check;
> + dev_priv->color_funcs.color_commit = i9xx_color_commit;
> + dev_priv->color_funcs.load_luts = i9xx_load_luts;
> + dev_priv->color_funcs.read_luts = i9xx_read_luts;
>   }
>   } else {
>   if (DISPLAY_VER(dev_priv) >= 11)
> - dev_priv->display.color_check = icl_color_check;
> + dev_priv->color_funcs.color_check = icl_color_check;
>   else if (DISPLAY_VER(dev_priv) >= 10)
> - dev_priv->display.color_check = glk_color_check;
> + dev_priv->color_funcs.color_check = glk_color_check;
>   else if (DISPLAY_VER(dev_priv) >= 7)
> - dev_priv->disp

Re: [Intel-gfx] [PATCH 1/8] drm/i915/xehp: Define compute class and engine

[Tvrtko Ursulin]

On 07/09/2021 18:19, Matt Roper wrote:

Introduce a Compute Command Streamer (CCS), which has access to
the media and GPGPU pipelines (but not the 3D pipeline).

To begin with, define the compute class/engine common functions, based
on the existing render ones.

Bspec: 46167, 45544
Original-patch-by: Michel Thierry
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Vinay Belgaumkar 
Cc: Szymon Morek 
UMD (compute): https://github.com/intel/compute-runtime/pull/451
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Daniele Ceraolo Spurio 
Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Matt Roper 
---
  drivers/gpu/drm/i915/gt/intel_engine_cs.c| 28 
  drivers/gpu/drm/i915/gt/intel_engine_types.h |  9 ++-
  drivers/gpu/drm/i915/gt/intel_engine_user.c  |  5 +++-
  drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h  | 13 +
  drivers/gpu/drm/i915/i915_reg.h  |  8 ++
  include/uapi/drm/i915_drm.h  |  1 +
  6 files changed, 57 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 332efea696a5..69944bd8c19d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -153,6 +153,34 @@ static const struct engine_info intel_engines[] = {
{ .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
},
},
+   [CCS0] = {
+   .class = COMPUTE_CLASS,
+   .instance = 0,
+   .mmio_bases = {
+   { .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE }
+   }
+   },
+   [CCS1] = {
+   .class = COMPUTE_CLASS,
+   .instance = 1,
+   .mmio_bases = {
+   { .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE }
+   }
+   },
+   [CCS2] = {
+   .class = COMPUTE_CLASS,
+   .instance = 2,
+   .mmio_bases = {
+   { .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE }
+   }
+   },
+   [CCS3] = {
+   .class = COMPUTE_CLASS,
+   .instance = 3,
+   .mmio_bases = {
+   { .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
+   }
+   },
  };
  
  /**

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h 
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index bfbfe53c23dd..dcb9d8b2362a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -33,7 +33,8 @@
  #define VIDEO_ENHANCEMENT_CLASS   2
  #define COPY_ENGINE_CLASS 3
  #define OTHER_CLASS   4
-#define MAX_ENGINE_CLASS   4
+#define COMPUTE_CLASS  5
+#define MAX_ENGINE_CLASS   5
  #define MAX_ENGINE_INSTANCE   7
  
  #define I915_MAX_SLICES	3

@@ -95,6 +96,7 @@ struct i915_ctx_workarounds {
  
  #define I915_MAX_VCS	8

  #define I915_MAX_VECS 4
+#define I915_MAX_CCS   4
  
  /*

   * Engine IDs definitions.
@@ -117,6 +119,11 @@ enum intel_engine_id {
VECS2,
VECS3,
  #define _VECS(n) (VECS0 + (n))
+   CCS0,
+   CCS1,
+   CCS2,
+   CCS3,
+#define _CCS(n) (CCS0 + (n))
I915_NUM_ENGINES
  #define INVALID_ENGINE ((enum intel_engine_id)-1)
  };
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c 
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 8f8bea08e734..d981621a7c30 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -47,6 +47,7 @@ static const u8 uabi_classes[] = {
[COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
[VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
[VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
+   [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
  };
  
  static int engine_cmp(void *priv, const struct list_head *A,

@@ -139,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
[COPY_ENGINE_CLASS] = "bcs",
[VIDEO_DECODE_CLASS] = "vcs",
[VIDEO_ENHANCEMENT_CLASS] = "vecs",
+   [COMPUTE_CLASS] = "ccs",
};
  
  	if (class >= ARRAY_SIZE(uabi_names) || !uabi_names[class])

@@ -162,6 +164,7 @@ static int legacy_ring_idx(const struct legacy_ring *ring)
[COPY_ENGINE_CLASS] = { BCS0, 1 },
[VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS },
[VIDEO_ENHANCEMENT_CLASS] = { VECS0, I915_MAX_VECS },
+   [COMPUTE_CLASS] = { CCS0, I915_MAX_CCS },
};
  
  	if (GEM_DEBUG_WARN_ON(ring->class >= ARRAY_SIZE(map)))

@@ -190,7 +193,7 @@ static void add_legacy_ring(struct legacy_ring *ring,
  void intel_engines_driver_register(struct drm_i915_private *i915)
  {
struct legacy_ring ring = {};
-   u8 uabi_instances[4] = {};
+   u8 uabi_instances[5] = {};
struct list_head *it, *next;
struct 

Re: [Intel-gfx] [PATCH 07/21] drm/i915: split audio functions from display vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> These are only used internally in the audio code
> ---
>  drivers/gpu/drm/i915/display/intel_audio.c | 24 +++---
>  drivers/gpu/drm/i915/i915_drv.h| 19 +++--
>  2 files changed, 25 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index 532237588511..f539826c0424 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -848,8 +848,8 @@ void intel_audio_codec_enable(struct intel_encoder 
> *encoder,
>  
>   connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
>  
> - if (dev_priv->display.audio_codec_enable)
> - dev_priv->display.audio_codec_enable(encoder,
> + if (dev_priv->audio_funcs.audio_codec_enable)
> + dev_priv->audio_funcs.audio_codec_enable(encoder,
>crtc_state,
>conn_state);
>  
> @@ -893,8 +893,8 @@ void intel_audio_codec_disable(struct intel_encoder 
> *encoder,
>   enum port port = encoder->port;
>   enum pipe pipe = crtc->pipe;
>  
> - if (dev_priv->display.audio_codec_disable)
> - dev_priv->display.audio_codec_disable(encoder,
> + if (dev_priv->audio_funcs.audio_codec_disable)
> + dev_priv->audio_funcs.audio_codec_disable(encoder,
> old_crtc_state,
> old_conn_state);

Again, nice isolation here. :)

>  
> @@ -922,17 +922,17 @@ void intel_audio_codec_disable(struct intel_encoder 
> *encoder,
>  void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
>  {
>   if (IS_G4X(dev_priv)) {
> - dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
> - dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
> + dev_priv->audio_funcs.audio_codec_enable = 
> g4x_audio_codec_enable;
> + dev_priv->audio_funcs.audio_codec_disable = 
> g4x_audio_codec_disable;
>   } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> - dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
> - dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
> + dev_priv->audio_funcs.audio_codec_enable = 
> ilk_audio_codec_enable;
> + dev_priv->audio_funcs.audio_codec_disable = 
> ilk_audio_codec_disable;
>   } else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
> - dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
> - dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
> + dev_priv->audio_funcs.audio_codec_enable = 
> hsw_audio_codec_enable;
> + dev_priv->audio_funcs.audio_codec_disable = 
> hsw_audio_codec_disable;
>   } else if (HAS_PCH_SPLIT(dev_priv)) {
> - dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
> - dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
> + dev_priv->audio_funcs.audio_codec_enable = 
> ilk_audio_codec_enable;
> + dev_priv->audio_funcs.audio_codec_disable = 
> ilk_audio_codec_disable;
>   }
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7e5a8b1bbdd8..3e60bf8182e3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -364,6 +364,15 @@ struct drm_i915_display_color_funcs {
>   void (*read_luts)(struct intel_crtc_state *crtc_state);
>  };
>  
> +struct drm_i915_display_audio_funcs {

Nitpick, I'd make it struct intel_audio_funcs.

Reviewed-by: Jani Nikula 

> + void (*audio_codec_enable)(struct intel_encoder *encoder,
> +const struct intel_crtc_state *crtc_state,
> +const struct drm_connector_state 
> *conn_state);
> + void (*audio_codec_disable)(struct intel_encoder *encoder,
> + const struct intel_crtc_state 
> *old_crtc_state,
> + const struct drm_connector_state 
> *old_conn_state);
> +};
> +
>  struct drm_i915_display_funcs {
>   void (*get_cdclk)(struct drm_i915_private *dev_priv,
> struct intel_cdclk_config *cdclk_config);
> @@ -386,12 +395,7 @@ struct drm_i915_display_funcs {
>struct intel_crtc *crtc);
>   void (*commit_modeset_enables)(struct intel_atomic_state *state);
>   void (*commit_modeset_disables)(struct intel_atomic_state *state);
> - void (*audio_codec_enable)(struct intel_encoder *encoder,
> -const struct intel_crtc_state *crtc_state,
> -const struct drm_connector_stat

Re: [Intel-gfx] [PATCH 08/21] drm/i915: split cdclk functions from display vtable.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 

Commit message.

>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c| 148 +-
>  drivers/gpu/drm/i915/display/intel_display.c  |   2 +-
>  .../drm/i915/display/intel_display_power.c|   2 +-
>  drivers/gpu/drm/i915/i915_drv.h   |   8 +-
>  4 files changed, 83 insertions(+), 77 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 34fa4130d5c4..c12b4e6bf5f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1466,7 +1466,7 @@ static void bxt_get_cdclk(struct drm_i915_private 
> *dev_priv,
>* at least what the CDCLK frequency requires.
>*/
>   cdclk_config->voltage_level =
> - dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
> + dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config->cdclk);
>  }
>  
>  static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
> @@ -1777,7 +1777,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private 
> *dev_priv)
>   cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
>   cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
>   cdclk_config.voltage_level =
> - dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
> + dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config.cdclk);
>  
>   bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
>  }
> @@ -1789,7 +1789,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private 
> *dev_priv)
>   cdclk_config.cdclk = cdclk_config.bypass;
>   cdclk_config.vco = 0;
>   cdclk_config.voltage_level =
> - dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
> + dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config.cdclk);
>  
>   bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
>  }
> @@ -1932,7 +1932,7 @@ static void intel_set_cdclk(struct drm_i915_private 
> *dev_priv,
>   if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
>   return;
>  
> - if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk))
> + if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
>   return;
>  
>   intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
> @@ -1956,7 +1956,7 @@ static void intel_set_cdclk(struct drm_i915_private 
> *dev_priv,
>&dev_priv->gmbus_mutex);
>   }
>  
> - dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
> + dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
>  
>   for_each_intel_dp(&dev_priv->drm, encoder) {
>   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> @@ -2414,7 +2414,7 @@ static int bxt_modeset_calc_cdclk(struct 
> intel_cdclk_state *cdclk_state)
>   cdclk_state->logical.cdclk = cdclk;
>   cdclk_state->logical.voltage_level =
>   max_t(int, min_voltage_level,
> -   dev_priv->display.calc_voltage_level(cdclk));
> +   dev_priv->cdclk_funcs.calc_voltage_level(cdclk));
>  
>   if (!cdclk_state->active_pipes) {
>   cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
> @@ -2423,7 +2423,7 @@ static int bxt_modeset_calc_cdclk(struct 
> intel_cdclk_state *cdclk_state)
>   cdclk_state->actual.vco = vco;
>   cdclk_state->actual.cdclk = cdclk;
>   cdclk_state->actual.voltage_level =
> - dev_priv->display.calc_voltage_level(cdclk);
> + dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
>   } else {
>   cdclk_state->actual = cdclk_state->logical;
>   }
> @@ -2515,7 +2515,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state 
> *state)
>   new_cdclk_state->active_pipes =
>   intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
>  
> - ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
> + ret = dev_priv->cdclk_funcs.modeset_calc_cdclk(new_cdclk_state);
>   if (ret)
>   return ret;
>  
> @@ -2695,7 +2695,7 @@ void intel_update_max_cdclk(struct drm_i915_private 
> *dev_priv)
>   */
>  void intel_update_cdclk(struct drm_i915_private *dev_priv)
>  {
> - dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
> + dev_priv->cdclk_funcs.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
>  
>   /*
>* 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
> @@ -2852,119 +2852,119 @@ u32 intel_read_rawclk(struct drm_i915_private 
> *dev_priv)
>  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  {
>   if (IS_DG2(dev_priv)) {
> - dev_priv->display.set_cdclk = bxt_set_cdclk;
> - dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> - dev_priv->display.modeset_calc_cdclk

Re: [Intel-gfx] [PATCH 09/21] drm/i915: split irq hotplug function from display vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> This provide a service from irq to display, so make it separate
> ---
>  drivers/gpu/drm/i915/display/intel_hotplug.c |  4 ++--
>  drivers/gpu/drm/i915/i915_drv.h  |  9 -
>  drivers/gpu/drm/i915/i915_irq.c  | 14 +++---
>  3 files changed, 17 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c 
> b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index 47c85ac97c87..a06e1e1b33e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct 
> drm_i915_private *dev_priv)
>  
>  static void intel_hpd_irq_setup(struct drm_i915_private *i915)
>  {
> - if (i915->display_irqs_enabled && i915->display.hpd_irq_setup)
> - i915->display.hpd_irq_setup(i915);
> + if (i915->display_irqs_enabled && i915->irq_funcs.hpd_irq_setup)
> + i915->irq_funcs.hpd_irq_setup(i915);
>  }
>  
>  static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fbe92f248d05..ece23401cb46 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -384,6 +384,10 @@ struct drm_i915_display_cdclk_funcs {
>   u8 (*calc_voltage_level)(int cdclk);
>  };
>  
> +struct drm_i915_irq_funcs {

Here, I'm a bit divided with the naming, irqs being more of i915 core,
even if serving display. I could go with intel_hotplug_funcs. *shrug*.

Reviewed-by: Jani Nikula 


> + void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
> +};
> +
>  struct drm_i915_display_funcs {
>   /* Returns the active state of the crtc, and if the crtc is active,
>* fills out the pipe-config with the hw state. */
> @@ -401,7 +405,7 @@ struct drm_i915_display_funcs {
>  
>   void (*fdi_link_train)(struct intel_crtc *crtc,
>  const struct intel_crtc_state *crtc_state);
> - void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
> +
>   /* clock updates for mode set */
>   /* cursor updates */
>   /* render clock increase/decrease */
> @@ -993,6 +997,9 @@ struct drm_i915_private {
>   /* pm display functions */
>   struct drm_i915_wm_disp_funcs wm_disp;
>  
> + /* irq display functions */
> + struct drm_i915_irq_funcs irq_funcs;
> +
>   /* Display functions */
>   struct drm_i915_display_funcs display;
>  
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 0a1681384c84..f515a3a76a8e 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4395,20 +4395,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  
>   if (HAS_GMCH(dev_priv)) {
>   if (I915_HAS_HOTPLUG(dev_priv))
> - dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> + dev_priv->irq_funcs.hpd_irq_setup = i915_hpd_irq_setup;
>   } else {
>   if (HAS_PCH_DG1(dev_priv))
> - dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
> + dev_priv->irq_funcs.hpd_irq_setup = dg1_hpd_irq_setup;
>   else if (DISPLAY_VER(dev_priv) >= 11)
> - dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
> + dev_priv->irq_funcs.hpd_irq_setup = gen11_hpd_irq_setup;
>   else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> - dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> + dev_priv->irq_funcs.hpd_irq_setup = bxt_hpd_irq_setup;
>   else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> - dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
> + dev_priv->irq_funcs.hpd_irq_setup = icp_hpd_irq_setup;
>   else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> - dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> + dev_priv->irq_funcs.hpd_irq_setup = spt_hpd_irq_setup;
>   else
> - dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
> + dev_priv->irq_funcs.hpd_irq_setup = ilk_hpd_irq_setup;
>   }
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 10/21] drm/i915: split fdi link training from display vtable.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> It may make sense to merge this with display again later,
> however the fdi use of the vtable is limited to only a
> few generations.
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_fdi.c |  6 +++---
>  drivers/gpu/drm/i915/i915_drv.h  | 11 ---
>  3 files changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index ccd0332e7945..b981a923cc2f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2100,7 +2100,7 @@ static void ilk_pch_enable(const struct 
> intel_atomic_state *state,
>   assert_pch_transcoder_disabled(dev_priv, pipe);
>  
>   /* For PCH output, training FDI link */
> - dev_priv->display.fdi_link_train(crtc, crtc_state);
> + dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);

Nitpick, I'd add a wrapper intel_fdi_link_train to call this.

>  
>   /* We need to program the right clock selection before writing the pixel
>* mutliplier into the DPLL. */
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c 
> b/drivers/gpu/drm/i915/display/intel_fdi.c
> index fc09b781f15f..d9f952e0c67f 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -1009,11 +1009,11 @@ void
>  intel_fdi_init_hook(struct drm_i915_private *dev_priv)
>  {
>   if (IS_IRONLAKE(dev_priv)) {
> - dev_priv->display.fdi_link_train = ilk_fdi_link_train;
> + dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
>   } else if (IS_SANDYBRIDGE(dev_priv)) {
> - dev_priv->display.fdi_link_train = gen6_fdi_link_train;
> + dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
>   } else if (IS_IVYBRIDGE(dev_priv)) {
>   /* FIXME: detect B0+ stepping and use auto training */
> - dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
> + dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
>   }
>  }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ece23401cb46..49b23ea46475 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -388,6 +388,11 @@ struct drm_i915_irq_funcs {
>   void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
>  };
>  
> +struct drm_i915_fdi_link_train_funcs {

Nitpick, intel_fdi_funcs.

Reviewed-by: Jani Nikula 

> + void (*fdi_link_train)(struct intel_crtc *crtc,
> +const struct intel_crtc_state *crtc_state);
> +};
> +
>  struct drm_i915_display_funcs {
>   /* Returns the active state of the crtc, and if the crtc is active,
>* fills out the pipe-config with the hw state. */
> @@ -403,9 +408,6 @@ struct drm_i915_display_funcs {
>   void (*commit_modeset_enables)(struct intel_atomic_state *state);
>   void (*commit_modeset_disables)(struct intel_atomic_state *state);
>  
> - void (*fdi_link_train)(struct intel_crtc *crtc,
> -const struct intel_crtc_state *crtc_state);
> -
>   /* clock updates for mode set */
>   /* cursor updates */
>   /* render clock increase/decrease */
> @@ -1000,6 +1002,9 @@ struct drm_i915_private {
>   /* irq display functions */
>   struct drm_i915_irq_funcs irq_funcs;
>  
> + /* fdi display functions */
> + struct drm_i915_fdi_link_train_funcs fdi_funcs;
> +
>   /* Display functions */
>   struct drm_i915_display_funcs display;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain

[Tvrtko Ursulin]

On 07/09/2021 18:19, Matt Roper wrote:

The reset domain is shared between render and all compute engines,
so resetting one will affect the others.

Note:  Before performing a reset on an RCS or CCS engine, the GuC will
attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid
impacting other clients (since some shared modules will be reset).  If
other engines are executing non-preemptable workloads, the impact is
unavoidable and some work may be lost.


Since here it talks about engine reset, should this patch add warning if 
 same is attempted by i915 on a GuC platform - to document it is not 
implemented/supported? Or perhaps later in the series, or future series 
works better.


Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko


Bspec: 52549
Original-patch-by: Michel Thierry
Cc: Tvrtko Ursulin 
Cc: Vinay Belgaumkar 
Signed-off-by: Daniele Ceraolo Spurio 
Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Matt Roper 
---
  drivers/gpu/drm/i915/gt/intel_reset.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 91200c43951f..30598c1d070c 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -507,6 +507,10 @@ static int gen11_reset_engines(struct intel_gt *gt,
[VECS1] = GEN11_GRDOM_VECS2,
[VECS2] = GEN11_GRDOM_VECS3,
[VECS3] = GEN11_GRDOM_VECS4,
+   [CCS0] = GEN11_GRDOM_RENDER,
+   [CCS1] = GEN11_GRDOM_RENDER,
+   [CCS2] = GEN11_GRDOM_RENDER,
+   [CCS3] = GEN11_GRDOM_RENDER,
};
struct intel_engine_cs *engine;
intel_engine_mask_t tmp;

Re: [Intel-gfx] [PATCH 3/8] drm/i915/xehp: Add Compute CS IRQ handlers

[Tvrtko Ursulin]

On 07/09/2021 18:19, Matt Roper wrote:

Add execlists and GuC interrupts for compute CS into existing IRQ handlers.

All compute command streamers belong to the same compute class, so the
only change needed to enable their interrupts is to program their GT engine
interrupt mask registers.

CCS0 shares the register with CCS1, while CCS2 and CCS3 are in a new one.

BSpec: 50844, 54029, 54030, 53223, 53224.
Original-patch-by: Michel Thierry
Cc: Tvrtko Ursulin 
Cc: Vinay Belgaumkar 
Signed-off-by: Daniele Ceraolo Spurio 
Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Matt Roper 
---
  drivers/gpu/drm/i915/gt/intel_gt_irq.c | 15 ++-
  drivers/gpu/drm/i915/i915_drv.h|  2 ++
  drivers/gpu/drm/i915/i915_reg.h|  3 +++
  3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c 
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index b2de83be4d97..612281d47513 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -96,7 +96,7 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 
identity)
if (unlikely(!intr))
return;
  
-	if (class <= COPY_ENGINE_CLASS)

+   if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
return gen11_engine_irq_handler(gt, class, instance, intr);
  
  	if (class == OTHER_CLASS)

@@ -178,6 +178,8 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
/* Disable RCS, BCS, VCS and VECS class engines. */
intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0);
intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE,0);
+   if (CCS_MASK(gt))
+   intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
  
  	/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */

intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK,   ~0);
@@ -191,6 +193,10 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0);
if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0);
+   if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))
+   intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
+   if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
+   intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
  
  	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);

intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK,  ~0);
@@ -218,6 +224,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
/* Enable RCS, BCS, VCS and VECS class interrupts. */
intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask);
intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
+   if (CCS_MASK(gt))
+   intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
  
  	/* Unmask irqs on RCS, BCS, VCS and VECS engines. */

intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
@@ -231,6 +239,11 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask);
if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask);
+   if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1))
+   intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
+   if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
+   intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
+
/*
 * RPS interrupts will get enabled/disabled on demand when RPS itself
 * is enabled/disabled.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1fd3040b6771..5b6eee5d8ade 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1573,6 +1573,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
  #define VEBOX_MASK(gt) \
ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
+#define CCS_MASK(gt) \
+   ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
  
  /*

   * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 33d6aa0b07c1..31e9c2cc4c0c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8139,6 +8139,7 @@ enum {
  #define GEN11_GPM_WGBOXPERF_INTR_ENABLE   _MMIO(0x19003c)
  #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
  #define GEN11_GUNIT_CSME_INTR_ENABLE  _MMIO(0x190044)
+#define GEN12_CCS_RSVD_INTR_ENABLE _MMIO(0x190048)
  
  #define GEN11_RCS0_RSVD_INTR_MASK	_MMIO(0x190090)

  #define GEN11_BCS_RSVD_INTR_MASK  _MMIO(0x1900a0)
@@ -8152,6 +8153,8 @@ enum {
  #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
  #define GEN11_

Re: [Intel-gfx] [PATCH 11/21] drm/i915: split the dpll clock compute out from display vtable.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> this could be merged later but for now it's simple to split it out.
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  6 +++---
>  drivers/gpu/drm/i915/display/intel_dpll.c| 16 
>  drivers/gpu/drm/i915/i915_drv.h  |  8 +++-
>  3 files changed, 18 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b981a923cc2f..87950202f4ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6768,10 +6768,10 @@ static int intel_crtc_atomic_check(struct 
> intel_atomic_state *state,
>   crtc_state->update_wm_post = true;
>  
>   if (mode_changed && crtc_state->hw.enable &&
> - dev_priv->display.crtc_compute_clock &&
> + dev_priv->dpll_funcs.crtc_compute_clock &&
>   !crtc_state->bigjoiner_slave &&
>   !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
> - ret = dev_priv->display.crtc_compute_clock(crtc_state);
> + ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
>   if (ret)
>   return ret;

It was there before, but yuck. Conditions like this with checks on the
existence of a vfunc are really ugly. Could benefit from a wrapper - but
that requires figuring out what the condition actually is. *facepalm*.

>   }
> @@ -8807,7 +8807,7 @@ static void intel_modeset_clear_plls(struct 
> intel_atomic_state *state)
>   struct intel_crtc *crtc;
>   int i;
>  
> - if (!dev_priv->display.crtc_compute_clock)
> + if (!dev_priv->dpll_funcs.crtc_compute_clock)
>   return;
>  
>   for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 210f91f4a576..9326c7cbb05c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1367,21 +1367,21 @@ void
>  intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
>  {
>   if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
> - dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
> + dev_priv->dpll_funcs.crtc_compute_clock = 
> hsw_crtc_compute_clock;
>   else if (HAS_PCH_SPLIT(dev_priv))
> - dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock;
> + dev_priv->dpll_funcs.crtc_compute_clock = 
> ilk_crtc_compute_clock;
>   else if (IS_CHERRYVIEW(dev_priv))
> - dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
> + dev_priv->dpll_funcs.crtc_compute_clock = 
> chv_crtc_compute_clock;
>   else if (IS_VALLEYVIEW(dev_priv))
> - dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
> + dev_priv->dpll_funcs.crtc_compute_clock = 
> vlv_crtc_compute_clock;
>   else if (IS_G4X(dev_priv))
> - dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
> + dev_priv->dpll_funcs.crtc_compute_clock = 
> g4x_crtc_compute_clock;
>   else if (IS_PINEVIEW(dev_priv))
> - dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
> + dev_priv->dpll_funcs.crtc_compute_clock = 
> pnv_crtc_compute_clock;
>   else if (DISPLAY_VER(dev_priv) != 2)
> - dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
> + dev_priv->dpll_funcs.crtc_compute_clock = 
> i9xx_crtc_compute_clock;
>   else
> - dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
> + dev_priv->dpll_funcs.crtc_compute_clock = 
> i8xx_crtc_compute_clock;
>  }
>  
>  static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 49b23ea46475..461ab0a0f088 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -393,6 +393,10 @@ struct drm_i915_fdi_link_train_funcs {
>  const struct intel_crtc_state *crtc_state);
>  };
>  
> +struct drm_i915_dpll_funcs {

Nitpick, intel_dpll_funcs. Starting to spot the pattern? ;D

Part of the point is that I think these may eventually move to their own
headers, and I like to drive naming structs and functions after the file
name. So, you'd find intel_dpll_* stuff in intel_dpll.[ch]. Or if they
stay in i915_drv.h, at least that's the chrystal clear context.

Reviewed-by: Jani Nikula 


> + int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
> +};
> +
>  struct drm_i915_display_funcs {
>   /* Returns the active state of the crtc, and if the crtc is active,
>* fills out the pipe-config with the hw state. */
> @@ -400,7 +404,6 @@ struct drm_i915_display_funcs {
>  

Re: [Intel-gfx] [PATCH 12/21] drm/i915: constify fdi link training vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> Avoid having writeable function pointers.

Would benefit from the call wrapper and naming.

Reviewed-by: Jani Nikula 


> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_fdi.c | 18 +++---
>  drivers/gpu/drm/i915/i915_drv.h  |  2 +-
>  3 files changed, 17 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 87950202f4ce..0ad577aceb9d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2100,7 +2100,7 @@ static void ilk_pch_enable(const struct 
> intel_atomic_state *state,
>   assert_pch_transcoder_disabled(dev_priv, pipe);
>  
>   /* For PCH output, training FDI link */
> - dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
> + dev_priv->fdi_funcs->fdi_link_train(crtc, crtc_state);
>  
>   /* We need to program the right clock selection before writing the pixel
>* mutliplier into the DPLL. */
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c 
> b/drivers/gpu/drm/i915/display/intel_fdi.c
> index d9f952e0c67f..68aa9c7b18ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -1005,15 +1005,27 @@ void lpt_fdi_program_mphy(struct drm_i915_private 
> *dev_priv)
>   intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
>  }
>  
> +static const struct drm_i915_fdi_link_train_funcs ilk_funcs = {
> + .fdi_link_train = ilk_fdi_link_train
> +};
> +
> +static const struct drm_i915_fdi_link_train_funcs gen6_funcs = {
> + .fdi_link_train = gen6_fdi_link_train
> +};
> +
> +static const struct drm_i915_fdi_link_train_funcs ivb_funcs = {
> + .fdi_link_train = ivb_manual_fdi_link_train
> +};
> +
>  void
>  intel_fdi_init_hook(struct drm_i915_private *dev_priv)
>  {
>   if (IS_IRONLAKE(dev_priv)) {
> - dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
> + dev_priv->fdi_funcs = &ilk_funcs;
>   } else if (IS_SANDYBRIDGE(dev_priv)) {
> - dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
> + dev_priv->fdi_funcs = &gen6_funcs;
>   } else if (IS_IVYBRIDGE(dev_priv)) {
>   /* FIXME: detect B0+ stepping and use auto training */
> - dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
> + dev_priv->fdi_funcs = &ivb_funcs;
>   }
>  }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 461ab0a0f088..b3765222e717 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1006,7 +1006,7 @@ struct drm_i915_private {
>   struct drm_i915_irq_funcs irq_funcs;
>  
>   /* fdi display functions */
> - struct drm_i915_fdi_link_train_funcs fdi_funcs;
> + const struct drm_i915_fdi_link_train_funcs *fdi_funcs;
>  
>   /* display pll funcs */
>   struct drm_i915_dpll_funcs dpll_funcs;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 13/21] drm/i915: constify irq function vtable.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> Use a macro to avoid mistakes, this type of macro is only used
> in a couple of places.
> ---
>  drivers/gpu/drm/i915/display/intel_hotplug.c |  4 +--
>  drivers/gpu/drm/i915/i915_drv.h  |  2 +-
>  drivers/gpu/drm/i915/i915_irq.c  | 27 +++-
>  3 files changed, 23 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c 
> b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index a06e1e1b33e1..97df40107213 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct 
> drm_i915_private *dev_priv)
>  
>  static void intel_hpd_irq_setup(struct drm_i915_private *i915)
>  {
> - if (i915->display_irqs_enabled && i915->irq_funcs.hpd_irq_setup)
> - i915->irq_funcs.hpd_irq_setup(i915);
> + if (i915->display_irqs_enabled && i915->irq_funcs)
> + i915->irq_funcs->hpd_irq_setup(i915);
>  }
>  
>  static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b3765222e717..6050bb519b18 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1003,7 +1003,7 @@ struct drm_i915_private {
>   struct drm_i915_wm_disp_funcs wm_disp;
>  
>   /* irq display functions */
> - struct drm_i915_irq_funcs irq_funcs;
> + const struct drm_i915_irq_funcs *irq_funcs;
>  
>   /* fdi display functions */
>   const struct drm_i915_fdi_link_train_funcs *fdi_funcs;
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index f515a3a76a8e..29231daf6057 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4345,6 +4345,19 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
>   return ret;
>  }
>  
> +#define HPD_FUNCS(platform)  \
> +static const struct drm_i915_irq_funcs platform##_hpd_funcs = { \
> + .hpd_irq_setup = platform##_hpd_irq_setup   \
> +}
> +
> +HPD_FUNCS(i915);
> +HPD_FUNCS(dg1);
> +HPD_FUNCS(gen11);
> +HPD_FUNCS(bxt);
> +HPD_FUNCS(icp);
> +HPD_FUNCS(spt);
> +HPD_FUNCS(ilk);
> +

#undef HPD_FUNCS

Reviewed-by: Jani Nikula 


>  /**
>   * intel_irq_init - initializes irq support
>   * @dev_priv: i915 device instance
> @@ -4395,20 +4408,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  
>   if (HAS_GMCH(dev_priv)) {
>   if (I915_HAS_HOTPLUG(dev_priv))
> - dev_priv->irq_funcs.hpd_irq_setup = i915_hpd_irq_setup;
> + dev_priv->irq_funcs = &i915_hpd_funcs;
>   } else {
>   if (HAS_PCH_DG1(dev_priv))
> - dev_priv->irq_funcs.hpd_irq_setup = dg1_hpd_irq_setup;
> + dev_priv->irq_funcs = &dg1_hpd_funcs;
>   else if (DISPLAY_VER(dev_priv) >= 11)
> - dev_priv->irq_funcs.hpd_irq_setup = gen11_hpd_irq_setup;
> + dev_priv->irq_funcs = &gen11_hpd_funcs;
>   else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> - dev_priv->irq_funcs.hpd_irq_setup = bxt_hpd_irq_setup;
> + dev_priv->irq_funcs = &bxt_hpd_funcs;
>   else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> - dev_priv->irq_funcs.hpd_irq_setup = icp_hpd_irq_setup;
> + dev_priv->irq_funcs = &icp_hpd_funcs;
>   else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> - dev_priv->irq_funcs.hpd_irq_setup = spt_hpd_irq_setup;
> + dev_priv->irq_funcs = &spt_hpd_funcs;
>   else
> - dev_priv->irq_funcs.hpd_irq_setup = ilk_hpd_irq_setup;
> + dev_priv->irq_funcs = &ilk_hpd_funcs;
>   }
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 4/8] drm/i915/xehp: CCS should use RCS setup functions

[Tvrtko Ursulin]

On 07/09/2021 18:19, Matt Roper wrote:

The compute engine handles the same commands the render engine can
(except 3D pipeline), so it makes sense that CCS is more similar to RCS
than non-render engines.

The CCS context state (lrc) is also similar to the render one, so reuse
it. Note that the compute engine has its own CTX_R_PWR_CLK_STATE
register.

In order to avoid having multiple RCS && CCS checks, add the following
engine flag:
  - I915_ENGINE_HAS_RCS_REG_STATE - use the render (larger) reg state ctx.

BSpec: 46260
Original-patch-by: Michel Thierry
Cc: Tvrtko Ursulin 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Matt Roper 
---
  drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 8 +---
  drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 ++
  drivers/gpu/drm/i915/gt/intel_engine_types.h  | 1 +
  drivers/gpu/drm/i915/gt/intel_execlists_submission.c  | 2 +-
  drivers/gpu/drm/i915/gt/intel_lrc.c   | 4 ++--
  drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
  drivers/gpu/drm/i915/i915_perf.c  | 4 ++--
  drivers/gpu/drm/i915/i915_reg.h   | 2 +-
  8 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index b32f7fed2d9c..fbe10783628b 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -883,7 +883,9 @@ static int igt_shared_ctx_exec(void *arg)
return err;
  }
  
-static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *vma)

+static int rpcs_query_batch(struct drm_i915_gem_object *rpcs,
+   struct i915_vma *vma,
+   struct intel_engine_cs *engine)
  {
u32 *cmd;
  
@@ -894,7 +896,7 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v

return PTR_ERR(cmd);
  
  	*cmd++ = MI_STORE_REGISTER_MEM_GEN8;

-   *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
+   *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(engine->mmio_base));
*cmd++ = lower_32_bits(vma->node.start);
*cmd++ = upper_32_bits(vma->node.start);
*cmd = MI_BATCH_BUFFER_END;
@@ -955,7 +957,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
if (err)
goto err_vma;
  
-	err = rpcs_query_batch(rpcs, vma);

+   err = rpcs_query_batch(rpcs, vma, ce->engine);
if (err)
goto err_batch;
  
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c

index 69944bd8c19d..b346b946602d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -205,6 +205,8 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
  
  	switch (class) {

+   case COMPUTE_CLASS:
+   fallthrough;
case RENDER_CLASS:
switch (GRAPHICS_VER(gt->i915)) {
default:
@@ -379,6 +381,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum 
intel_engine_id id)
if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
engine->props.preempt_timeout_ms = 0;
  
+	/* features common between engines sharing EUs */

+   if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS)
+   engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
+
engine->defaults = engine->props; /* never to change again */
  
  	engine->context_size = intel_engine_context_size(gt, engine->class);

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h 
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index dcb9d8b2362a..30a0c69c36c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -454,6 +454,7 @@ struct intel_engine_cs {
  #define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
  #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
  #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
+#define I915_ENGINE_HAS_RCS_REG_STATE  BIT(9)
unsigned int flags;
  
  	/*

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index de5f9c86b9a4..4c600c46414d 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3406,7 +3406,7 @@ int intel_execlists_submission_setup(struct 
intel_engine_cs *engine)
logical_ring_default_vfuncs(engine);
logical_ring_default_irqs(engine);
  
-	if (engine->class == RENDER_CLASS)

+   if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
rcs_submission_override(engine);


Hm, what do pipe control flushes which relate to 3d pipeline end up 
doing on CCS engines?


Regards,

Tvrtko

 

[Intel-gfx] ✗ Fi.CI.BUILD: failure for i915/uncore: constify the uncore vtables. (rev2)

[Patchwork]

== Series Details ==

Series: i915/uncore: constify the uncore vtables. (rev2)
URL   : https://patchwork.freedesktop.org/series/94465/
State : failure

== Summary ==

Applying: drm/i915/uncore: split the fw get function into separate vfunc
Applying: drm/i915/uncore: constify the register vtables.
error: sha1 information is lacking or useless 
(drivers/gpu/drm/i915/intel_uncore.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0002 drm/i915/uncore: constify the register vtables.
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

Re: [Intel-gfx] [PATCH 14/21] drm/i915: constify color function vtable.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 

The commit message could contain some words about how ugly this used to
be and how beautiful it is now. Awesome.

One bug, comment inline.

>
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 138 ++---
>  drivers/gpu/drm/i915/i915_drv.h|   2 +-
>  2 files changed, 93 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c 
> b/drivers/gpu/drm/i915/display/intel_color.c
> index ed79075158dd..b4e010c7e29d 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct 
> intel_crtc_state *crtc_state)
>  {
>   struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
> - dev_priv->color_funcs.load_luts(crtc_state);
> + dev_priv->color_funcs->load_luts(crtc_state);
>  }
>  
>  void intel_color_commit(const struct intel_crtc_state *crtc_state)
>  {
>   struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
> - dev_priv->color_funcs.color_commit(crtc_state);
> + dev_priv->color_funcs->color_commit(crtc_state);
>  }
>  
>  static bool intel_can_preload_luts(const struct intel_crtc_state 
> *new_crtc_state)
> @@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state 
> *crtc_state)
>  {
>   struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
> - return dev_priv->color_funcs.color_check(crtc_state);
> + return dev_priv->color_funcs->color_check(crtc_state);
>  }
>  
>  void intel_color_get_config(struct intel_crtc_state *crtc_state)
>  {
>   struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
> - if (dev_priv->color_funcs.read_luts)
> - dev_priv->color_funcs.read_luts(crtc_state);
> + if (dev_priv->color_funcs->read_luts)
> + dev_priv->color_funcs->read_luts(crtc_state);
>  }
>  
>  static bool need_plane_update(struct intel_plane *plane,
> @@ -2092,6 +2092,76 @@ static void icl_read_luts(struct intel_crtc_state 
> *crtc_state)
>   }
>  }
>  
> +static const struct drm_i915_display_color_funcs chv_color_funcs = {
> + .color_check = chv_color_check,
> + .color_commit = i9xx_color_commit,
> + .load_luts = chv_load_luts,
> + .read_luts = chv_read_luts,
> +};
> +
> +static const struct drm_i915_display_color_funcs i965_color_funcs = {
> + .color_check = i9xx_color_check,
> + .color_commit = i9xx_color_commit,
> + .load_luts = i965_load_luts,
> + .read_luts = i965_read_luts,
> +};
> +
> +static const struct drm_i915_display_color_funcs i9xx_color_funcs = {
> + .color_check = i9xx_color_check,
> + .color_commit = i9xx_color_commit,
> + .load_luts = i9xx_load_luts,
> + .read_luts = i9xx_read_luts,
> +};
> +
> +static const struct drm_i915_display_color_funcs icl_color_funcs = {
> + .color_check = icl_color_check,
> + .color_commit = skl_color_commit,
> + .load_luts = icl_load_luts,
> + .read_luts = icl_read_luts,
> +};
> +
> +static const struct drm_i915_display_color_funcs glk_color_funcs = {
> + .color_check = glk_color_check,
> + .color_commit = skl_color_commit,
> + .load_luts = glk_load_luts,
> + .read_luts = glk_read_luts,
> +};
> +
> +static const struct drm_i915_display_color_funcs skl_color_funcs = {
> + .color_check = ivb_color_check,
> + .color_commit = skl_color_commit,
> + .load_luts = bdw_load_luts,
> + .read_luts = NULL,
> +};
> +
> +static const struct drm_i915_display_color_funcs bdw_color_funcs = {
> + .color_check = ivb_color_check,
> + .color_commit = hsw_color_commit,
> + .load_luts = bdw_load_luts,
> + .read_luts = NULL,
> +};
> +
> +static const struct drm_i915_display_color_funcs hsw_color_funcs = {
> + .color_check = ivb_color_check,
> + .color_commit = hsw_color_commit,
> + .load_luts = ivb_load_luts,
> + .read_luts = NULL,
> +};
> +
> +static const struct drm_i915_display_color_funcs ivb_color_funcs = {
> + .color_check = ivb_color_check,
> + .color_commit = ilk_color_commit,
> + .load_luts = ilk_load_luts,

Should be ivb_load_luts.

> + .read_luts = ilk_read_luts,

Should be NULL.

Old code for ivb i.e. non-hsw gen 7 was:

 -  } else if (DISPLAY_VER(dev_priv) >= 7) {
 -  dev_priv->color_funcs.load_luts = ivb_load_luts;
 -  } else {

Right? It's a nightmare to review this because the old code was a
nightmare to read.

I think with that fixed this is good, and,

Reviewed-by: Jani Nikula 


> +};
> +
> +static const struct drm_i915_display_color_funcs ilk_color_funcs = {
> + .color_check = ilk_color_check,
> + .color_commit = ilk_color_commit,
> + .load_luts = ilk_load_luts,
> + .read_luts = ilk_read_luts,
> +};
> +
>  void intel_color_init(struct intel_crtc *crtc)
>  {
>   struct 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Panel replay phase1 implementation

[Patchwork]

== Series Details ==

Series: Panel replay phase1 implementation
URL   : https://patchwork.freedesktop.org/series/94470/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
c7704eae2ab0 drm/i915/panelreplay: update plane selective fetch register 
definition
-:8: WARNING:TYPO_SPELLING: 'difinition' may be misspelled - perhaps 
'definition'?
#8: 
so updated the plane selective fetch register difinition accordingly.
  ^^

-:78: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#78: FILE: drivers/gpu/drm/i915/i915_reg.h:7494:
+#define PLANE_SEL_FETCH_CTL(dev_priv, pipe, plane) 
_MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \

-:87: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#87: FILE: drivers/gpu/drm/i915/i915_reg.h:7500:
+#define PLANE_SEL_FETCH_POS(dev_priv, pipe, plane) 
_MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \

-:95: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#95: FILE: drivers/gpu/drm/i915/i915_reg.h:7505:
+#define PLANE_SEL_FETCH_SIZE(dev_priv, pipe, plane) 
_MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \

-:103: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#103: FILE: drivers/gpu/drm/i915/i915_reg.h:7510:
+#define PLANE_SEL_FETCH_OFFSET(dev_priv, pipe, plane) 
_MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \

total: 0 errors, 5 warnings, 0 checks, 85 lines checked
03948896e7b6 drm/i915/panelreplay: Feature flag added for panel replay
7d7858afd7c3 drm/i915/panelreplay: Initializaton and compute config for panel 
replay
9432d1630bf8 drm/i915/panelreplay: enable/disable panel replay
959cdcb164d3 drm/i915/panelreplay: Added state checker for panel replay state

Re: [Intel-gfx] [PATCH] kernel/locking: Add context to ww_mutex_trylock.

[Peter Zijlstra]

On Tue, Sep 07, 2021 at 03:20:44PM +0200, Maarten Lankhorst wrote:
> i915 will soon gain an eviction path that trylock a whole lot of locks
> for eviction, getting dmesg failures like below:
> 
> BUG: MAX_LOCK_DEPTH too low!
> turning off the locking correctness validator.
> depth: 48  max: 48!
> 48 locks held by i915_selftest/5776:
>  #0: 888101a79240 (&dev->mutex){}-{3:3}, at: 
> __driver_attach+0x88/0x160
>  #1: c99778c0 (reservation_ww_class_acquire){+.+.}-{0:0}, at: 
> i915_vma_pin.constprop.63+0x39/0x1b0 [i915]
>  #2: 88800cf74de8 (reservation_ww_class_mutex){+.+.}-{3:3}, at: 
> i915_vma_pin.constprop.63+0x5f/0x1b0 [i915]
>  #3: 88810c7f9e38 (&vm->mutex/1){+.+.}-{3:3}, at: 
> i915_vma_pin_ww+0x1c4/0x9d0 [i915]
>  #4: 88810bad5768 (reservation_ww_class_mutex){+.+.}-{3:3}, at: 
> i915_gem_evict_something+0x110/0x860 [i915]
>  #5: 88810bad60e8 (reservation_ww_class_mutex){+.+.}-{3:3}, at: 
> i915_gem_evict_something+0x110/0x860 [i915]
> ...
>  #46: 88811964d768 (reservation_ww_class_mutex){+.+.}-{3:3}, at: 
> i915_gem_evict_something+0x110/0x860 [i915]
>  #47: 88811964e0e8 (reservation_ww_class_mutex){+.+.}-{3:3}, at: 
> i915_gem_evict_something+0x110/0x860 [i915]
> INFO: lockdep is turned off.

> As an intermediate solution, add an acquire context to ww_mutex_trylock,
> which allows us to do proper nesting annotations on the trylocks, making
> the above lockdep splat disappear.

Fair enough I suppose.

> +/**
> + * ww_mutex_trylock - tries to acquire the w/w mutex with optional acquire 
> context
> + * @lock: mutex to lock
> + * @ctx: optional w/w acquire context
> + *
> + * Trylocks a mutex with the optional acquire context; no deadlock detection 
> is
> + * possible. Returns 1 if the mutex has been acquired successfully, 0 
> otherwise.
> + *
> + * Unlike ww_mutex_lock, no deadlock handling is performed. However, if a 
> @ctx is
> + * specified, -EALREADY and -EDEADLK handling may happen in calls to 
> ww_mutex_lock.
> + *
> + * A mutex acquired with this function must be released with ww_mutex_unlock.
> + */
> +int __sched
> +ww_mutex_trylock(struct ww_mutex *ww, struct ww_acquire_ctx *ctx)
> +{
> + bool locked;
> +
> + if (!ctx)
> + return mutex_trylock(&ww->base);
> +
> +#ifdef CONFIG_DEBUG_MUTEXES
> + DEBUG_LOCKS_WARN_ON(ww->base.magic != &ww->base);
> +#endif
> +
> + preempt_disable();
> + locked = __mutex_trylock(&ww->base);
> +
> + if (locked) {
> + ww_mutex_set_context_fastpath(ww, ctx);
> + mutex_acquire_nest(&ww->base.dep_map, 0, 1, &ctx->dep_map, 
> _RET_IP_);
> + }
> + preempt_enable();
> +
> + return locked;
> +}
> +EXPORT_SYMBOL(ww_mutex_trylock);

You'll need a similar hunk in ww_rt_mutex.c

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Panel replay phase1 implementation

[Patchwork]

== Series Details ==

Series: Panel replay phase1 implementation
URL   : https://patchwork.freedesktop.org/series/94470/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdg

Re: [Intel-gfx] [PATCH 15/21] drm/i915: constify the audio function vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>

Reviewed-by: Jani Nikula 


> ---
>  drivers/gpu/drm/i915/display/intel_audio.c | 43 ++
>  drivers/gpu/drm/i915/i915_drv.h|  2 +-
>  2 files changed, 28 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index f539826c0424..4707e1beb763 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -848,10 +848,10 @@ void intel_audio_codec_enable(struct intel_encoder 
> *encoder,
>  
>   connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
>  
> - if (dev_priv->audio_funcs.audio_codec_enable)
> - dev_priv->audio_funcs.audio_codec_enable(encoder,
> -  crtc_state,
> -  conn_state);
> + if (dev_priv->audio_funcs)
> + dev_priv->audio_funcs->audio_codec_enable(encoder,
> +   crtc_state,
> +   conn_state);
>  
>   mutex_lock(&dev_priv->av_mutex);
>   encoder->audio_connector = connector;
> @@ -893,10 +893,10 @@ void intel_audio_codec_disable(struct intel_encoder 
> *encoder,
>   enum port port = encoder->port;
>   enum pipe pipe = crtc->pipe;
>  
> - if (dev_priv->audio_funcs.audio_codec_disable)
> - dev_priv->audio_funcs.audio_codec_disable(encoder,
> -   old_crtc_state,
> -   old_conn_state);
> + if (dev_priv->audio_funcs)
> + dev_priv->audio_funcs->audio_codec_disable(encoder,
> +old_crtc_state,
> +old_conn_state);
>  
>   mutex_lock(&dev_priv->av_mutex);
>   encoder->audio_connector = NULL;
> @@ -915,6 +915,21 @@ void intel_audio_codec_disable(struct intel_encoder 
> *encoder,
>   intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
>  }
>  
> +static const struct drm_i915_display_audio_funcs g4x_audio_funcs = {
> + .audio_codec_enable = g4x_audio_codec_enable,
> + .audio_codec_disable = g4x_audio_codec_disable,
> +};
> +
> +static const struct drm_i915_display_audio_funcs ilk_audio_funcs = {
> + .audio_codec_enable = ilk_audio_codec_enable,
> + .audio_codec_disable = ilk_audio_codec_disable,
> +};
> +
> +static const struct drm_i915_display_audio_funcs hsw_audio_funcs = {
> + .audio_codec_enable = hsw_audio_codec_enable,
> + .audio_codec_disable = hsw_audio_codec_disable,
> +};
> +
>  /**
>   * intel_init_audio_hooks - Set up chip specific audio hooks
>   * @dev_priv: device private
> @@ -922,17 +937,13 @@ void intel_audio_codec_disable(struct intel_encoder 
> *encoder,
>  void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
>  {
>   if (IS_G4X(dev_priv)) {
> - dev_priv->audio_funcs.audio_codec_enable = 
> g4x_audio_codec_enable;
> - dev_priv->audio_funcs.audio_codec_disable = 
> g4x_audio_codec_disable;
> + dev_priv->audio_funcs = &g4x_audio_funcs;
>   } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> - dev_priv->audio_funcs.audio_codec_enable = 
> ilk_audio_codec_enable;
> - dev_priv->audio_funcs.audio_codec_disable = 
> ilk_audio_codec_disable;
> + dev_priv->audio_funcs = &ilk_audio_funcs;
>   } else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
> - dev_priv->audio_funcs.audio_codec_enable = 
> hsw_audio_codec_enable;
> - dev_priv->audio_funcs.audio_codec_disable = 
> hsw_audio_codec_disable;
> + dev_priv->audio_funcs = &hsw_audio_funcs;
>   } else if (HAS_PCH_SPLIT(dev_priv)) {
> - dev_priv->audio_funcs.audio_codec_enable = 
> ilk_audio_codec_enable;
> - dev_priv->audio_funcs.audio_codec_disable = 
> ilk_audio_codec_disable;
> + dev_priv->audio_funcs = &ilk_audio_funcs;
>   }
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e82df3bf493b..8d14318c5708 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1018,7 +1018,7 @@ struct drm_i915_private {
>   const struct drm_i915_display_color_funcs *color_funcs;
>  
>   /* Display internal audio functions */
> - struct drm_i915_display_audio_funcs audio_funcs;
> + const struct drm_i915_display_audio_funcs *audio_funcs;
>  
>   /* Display CDCLK functions */
>   struct drm_i915_display_cdclk_funcs cdclk_funcs;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 16/21] drm/i915: constify the dpll clock vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 

Reviewed-by: Jani Nikula 


>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  6 +--
>  drivers/gpu/drm/i915/display/intel_dpll.c| 49 
>  drivers/gpu/drm/i915/i915_drv.h  |  2 +-
>  3 files changed, 45 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 0ad577aceb9d..d8a576d1435e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6768,10 +6768,10 @@ static int intel_crtc_atomic_check(struct 
> intel_atomic_state *state,
>   crtc_state->update_wm_post = true;
>  
>   if (mode_changed && crtc_state->hw.enable &&
> - dev_priv->dpll_funcs.crtc_compute_clock &&
> + dev_priv->dpll_funcs &&
>   !crtc_state->bigjoiner_slave &&
>   !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
> - ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
> + ret = dev_priv->dpll_funcs->crtc_compute_clock(crtc_state);
>   if (ret)
>   return ret;
>   }
> @@ -8807,7 +8807,7 @@ static void intel_modeset_clear_plls(struct 
> intel_atomic_state *state)
>   struct intel_crtc *crtc;
>   int i;
>  
> - if (!dev_priv->dpll_funcs.crtc_compute_clock)
> + if (!dev_priv->dpll_funcs)
>   return;
>  
>   for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c 
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 9326c7cbb05c..3df10b88e69f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1363,25 +1363,58 @@ static int i8xx_crtc_compute_clock(struct 
> intel_crtc_state *crtc_state)
>   return 0;
>  }
>  
> +static const struct drm_i915_dpll_funcs hsw_dpll_funcs = {
> + .crtc_compute_clock = hsw_crtc_compute_clock
> +};
> +
> +static const struct drm_i915_dpll_funcs ilk_dpll_funcs = {
> + .crtc_compute_clock = ilk_crtc_compute_clock
> +};
> +
> +static const struct drm_i915_dpll_funcs chv_dpll_funcs = {
> + .crtc_compute_clock = chv_crtc_compute_clock
> +};
> +
> +static const struct drm_i915_dpll_funcs vlv_dpll_funcs = {
> + .crtc_compute_clock = vlv_crtc_compute_clock
> +};
> +
> +static const struct drm_i915_dpll_funcs g4x_dpll_funcs = {
> + .crtc_compute_clock = g4x_crtc_compute_clock
> +};
> +
> +static const struct drm_i915_dpll_funcs pnv_dpll_funcs = {
> + .crtc_compute_clock = pnv_crtc_compute_clock
> +};
> +
> +static const struct drm_i915_dpll_funcs i9xx_dpll_funcs = {
> + .crtc_compute_clock = i9xx_crtc_compute_clock
> +};
> +
> +static const struct drm_i915_dpll_funcs i8xx_dpll_funcs = {
> + .crtc_compute_clock = i8xx_crtc_compute_clock
> +};
> +
> +
>  void
>  intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
>  {
>   if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
> - dev_priv->dpll_funcs.crtc_compute_clock = 
> hsw_crtc_compute_clock;
> + dev_priv->dpll_funcs = &hsw_dpll_funcs;
>   else if (HAS_PCH_SPLIT(dev_priv))
> - dev_priv->dpll_funcs.crtc_compute_clock = 
> ilk_crtc_compute_clock;
> + dev_priv->dpll_funcs = &ilk_dpll_funcs;
>   else if (IS_CHERRYVIEW(dev_priv))
> - dev_priv->dpll_funcs.crtc_compute_clock = 
> chv_crtc_compute_clock;
> + dev_priv->dpll_funcs = &chv_dpll_funcs;
>   else if (IS_VALLEYVIEW(dev_priv))
> - dev_priv->dpll_funcs.crtc_compute_clock = 
> vlv_crtc_compute_clock;
> + dev_priv->dpll_funcs = &vlv_dpll_funcs;
>   else if (IS_G4X(dev_priv))
> - dev_priv->dpll_funcs.crtc_compute_clock = 
> g4x_crtc_compute_clock;
> + dev_priv->dpll_funcs = &g4x_dpll_funcs;
>   else if (IS_PINEVIEW(dev_priv))
> - dev_priv->dpll_funcs.crtc_compute_clock = 
> pnv_crtc_compute_clock;
> + dev_priv->dpll_funcs = &pnv_dpll_funcs;
>   else if (DISPLAY_VER(dev_priv) != 2)
> - dev_priv->dpll_funcs.crtc_compute_clock = 
> i9xx_crtc_compute_clock;
> + dev_priv->dpll_funcs = &i9xx_dpll_funcs;
>   else
> - dev_priv->dpll_funcs.crtc_compute_clock = 
> i8xx_crtc_compute_clock;
> + dev_priv->dpll_funcs = &i8xx_dpll_funcs;
>  }
>  
>  static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8d14318c5708..a9563730aad5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1009,7 +1009,7 @@ struct drm_i915_private {
>   const struct drm_i915_fdi_link_train_funcs *fdi_funcs;
>  
>   /* display pll funcs */
> - struct drm_i915_dpll_funcs dpll_funcs;
> + const struct drm_i915_dpll_funcs *

Re: [Intel-gfx] [PATCH v2 5/6] drm/i915: Don't back up pinned LMEM context images and rings during suspend

[Matthew Auld]

On 06/09/2021 17:55, Thomas Hellström wrote:

Pinned context images are now reset during resume. Don't back them up,
and assuming that rings can be assumed empty at suspend, don't back them
up either.

Introduce a new object flag, I915_BO_ALLOC_PM_VOLATILE meaning that an
object is allowed to lose its content on suspend.

Signed-off-by: Thomas Hellström 
---
  .../gpu/drm/i915/gem/i915_gem_object_types.h| 17 ++---
  drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c  |  3 +++
  drivers/gpu/drm/i915/gt/intel_lrc.c |  3 ++-
  drivers/gpu/drm/i915/gt/intel_ring.c|  3 ++-
  4 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 734cc8e16481..66123ba46247 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -288,16 +288,19 @@ struct drm_i915_gem_object {
I915_SELFTEST_DECLARE(struct list_head st_link);
  
  	unsigned long flags;

-#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
-#define I915_BO_ALLOC_VOLATILE   BIT(1)
-#define I915_BO_ALLOC_CPU_CLEAR  BIT(2)
-#define I915_BO_ALLOC_USER   BIT(3)
+#define I915_BO_ALLOC_CONTIGUOUS  BIT(0)
+#define I915_BO_ALLOC_VOLATILEBIT(1)
+#define I915_BO_ALLOC_CPU_CLEAR   BIT(2)
+#define I915_BO_ALLOC_USERBIT(3)
+/* Object may lose its contents on suspend / resume */


+ if we can't evict it?


+#define I915_BO_ALLOC_PM_VOLATILE BIT(4)
  #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
 I915_BO_ALLOC_VOLATILE | \
 I915_BO_ALLOC_CPU_CLEAR | \
-I915_BO_ALLOC_USER)
-#define I915_BO_READONLY BIT(4)
-#define I915_TILING_QUIRK_BIT5 /* unknown swizzling; do not release! */
+I915_BO_ALLOC_USER | \
+I915_BO_ALLOC_PM_VOLATILE)
+#define I915_BO_READONLY  BIT(5)
+#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not release! */
  
  	/**

 * @mem_flags - Mutable placement-related flags
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
index 3884bf45dab8..eaceecfc3f19 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
@@ -61,6 +61,9 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region 
*apply,
if (!pm_apply->backup_pinned)
return 0;
  
+	if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)

+   return 0;
+
sys_region = i915->mm.regions[INTEL_REGION_SMEM];
backup = i915_gem_object_create_region(sys_region,
   obj->base.size,
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6ba8daea2f56..3ef9eaf8c50e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -942,7 +942,8 @@ __lrc_alloc_state(struct intel_context *ce, struct 
intel_engine_cs *engine)
context_size += PAGE_SIZE;
}
  
-	obj = i915_gem_object_create_lmem(engine->i915, context_size, 0);

+   obj = i915_gem_object_create_lmem(engine->i915, context_size,
+ I915_BO_ALLOC_PM_VOLATILE);
if (IS_ERR(obj))
obj = i915_gem_object_create_shmem(engine->i915, context_size);
if (IS_ERR(obj))
diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c 
b/drivers/gpu/drm/i915/gt/intel_ring.c
index 7c4d5158e03b..2fdd52b62092 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring.c
@@ -112,7 +112,8 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt 
*ggtt, int size)
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
  
-	obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE);

+   obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE |
+ I915_BO_ALLOC_PM_VOLATILE);
if (IS_ERR(obj) && i915_ggtt_has_aperture(ggtt))
obj = i915_gem_object_create_stolen(i915, size);
if (IS_ERR(obj))

[Intel-gfx] ✓ Fi.CI.BAT: success for Panel replay phase1 implementation

[Patchwork]

== Series Details ==

Series: Panel replay phase1 implementation
URL   : https://patchwork.freedesktop.org/series/94470/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10562 -> Patchwork_20989


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/index.html

Known issues


  Here are the changes found in Patchwork_20989 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4:  [PASS][2] -> [FAIL][3] ([i915#1888])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-n3050:   [PASS][4] -> [INCOMPLETE][5] ([i915#2940])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@gt_timelines:
- fi-rkl-guc: [PASS][6] -> [INCOMPLETE][7] ([i915#4034])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/fi-rkl-guc/igt@i915_selftest@live@gt_timelines.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/fi-rkl-guc/igt@i915_selftest@live@gt_timelines.html

  * igt@runner@aborted:
- fi-rkl-guc: NOTRUN -> [FAIL][8] ([i915#3928])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/fi-rkl-guc/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][9] ([i915#3921]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928
  [i915#4034]: https://gitlab.freedesktop.org/drm/intel/issues/4034


Participating hosts (47 -> 39)
--

  Missing(8): fi-ilk-m540 bat-adls-5 bat-dg1-6 fi-bsw-cyan bat-adlp-4 
fi-ctg-p8600 fi-bdw-samus bat-jsl-1 


Build changes
-

  * Linux: CI_DRM_10562 -> Patchwork_20989

  CI-20190529: 20190529
  CI_DRM_10562: d38c3e456e48f3cc74f454615dedc5a82e258402 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6200: 3a6585c472dff11ece952b745244f05e4c93ede5 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20989: 959cdcb164d3097c83def2762b1c4e25f7faf66d @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

959cdcb164d3 drm/i915/panelreplay: Added state checker for panel replay state
9432d1630bf8 drm/i915/panelreplay: enable/disable panel replay
7d7858afd7c3 drm/i915/panelreplay: Initializaton and compute config for panel 
replay
03948896e7b6 drm/i915/panelreplay: Feature flag added for panel replay
c7704eae2ab0 drm/i915/panelreplay: update plane selective fetch register 
definition

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/index.html

Re: [Intel-gfx] [PATCH v2 5/6] drm/i915: Don't back up pinned LMEM context images and rings during suspend

[Matthew Auld]

On 06/09/2021 17:55, Thomas Hellström wrote:

Pinned context images are now reset during resume. Don't back them up,
and assuming that rings can be assumed empty at suspend, don't back them
up either.

Introduce a new object flag, I915_BO_ALLOC_PM_VOLATILE meaning that an
object is allowed to lose its content on suspend.

Signed-off-by: Thomas Hellström 
---
  .../gpu/drm/i915/gem/i915_gem_object_types.h| 17 ++---
  drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c  |  3 +++
  drivers/gpu/drm/i915/gt/intel_lrc.c |  3 ++-
  drivers/gpu/drm/i915/gt/intel_ring.c|  3 ++-
  4 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 734cc8e16481..66123ba46247 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -288,16 +288,19 @@ struct drm_i915_gem_object {
I915_SELFTEST_DECLARE(struct list_head st_link);
  
  	unsigned long flags;

-#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
-#define I915_BO_ALLOC_VOLATILE   BIT(1)
-#define I915_BO_ALLOC_CPU_CLEAR  BIT(2)
-#define I915_BO_ALLOC_USER   BIT(3)
+#define I915_BO_ALLOC_CONTIGUOUS  BIT(0)
+#define I915_BO_ALLOC_VOLATILEBIT(1)
+#define I915_BO_ALLOC_CPU_CLEAR   BIT(2)
+#define I915_BO_ALLOC_USERBIT(3)
+/* Object may lose its contents on suspend / resume */
+#define I915_BO_ALLOC_PM_VOLATILE BIT(4)


PM_SKIP_PINNED? Not sure if that is better.



  #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
 I915_BO_ALLOC_VOLATILE | \
 I915_BO_ALLOC_CPU_CLEAR | \
-I915_BO_ALLOC_USER)
-#define I915_BO_READONLY BIT(4)
-#define I915_TILING_QUIRK_BIT5 /* unknown swizzling; do not release! */
+I915_BO_ALLOC_USER | \
+I915_BO_ALLOC_PM_VOLATILE)
+#define I915_BO_READONLY  BIT(5)
+#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not release! */
  
  	/**

 * @mem_flags - Mutable placement-related flags
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
index 3884bf45dab8..eaceecfc3f19 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
@@ -61,6 +61,9 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region 
*apply,
if (!pm_apply->backup_pinned)
return 0;
  
+	if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)

+   return 0;
+
sys_region = i915->mm.regions[INTEL_REGION_SMEM];
backup = i915_gem_object_create_region(sys_region,
   obj->base.size,
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6ba8daea2f56..3ef9eaf8c50e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -942,7 +942,8 @@ __lrc_alloc_state(struct intel_context *ce, struct 
intel_engine_cs *engine)
context_size += PAGE_SIZE;
}
  
-	obj = i915_gem_object_create_lmem(engine->i915, context_size, 0);

+   obj = i915_gem_object_create_lmem(engine->i915, context_size,
+ I915_BO_ALLOC_PM_VOLATILE);
if (IS_ERR(obj))
obj = i915_gem_object_create_shmem(engine->i915, context_size);
if (IS_ERR(obj))
diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c 
b/drivers/gpu/drm/i915/gt/intel_ring.c
index 7c4d5158e03b..2fdd52b62092 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring.c
@@ -112,7 +112,8 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt 
*ggtt, int size)
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
  
-	obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE);

+   obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE |
+ I915_BO_ALLOC_PM_VOLATILE);
if (IS_ERR(obj) && i915_ggtt_has_aperture(ggtt))
obj = i915_gem_object_create_stolen(i915, size);
if (IS_ERR(obj))

Re: [Intel-gfx] [v3 4/5] drm/i915/dsi: Retrieve max brightness level from VBT

[Jani Nikula]

On Thu, 02 Sep 2021, Lee Shawn C  wrote:
> So far, DCS backlight driver hardcode (0xFF) for max brightness level.
> MIPI DCS spec allow max 0x for set_display_brightness (51h) command.
> And VBT brightness precision bits can support 8 ~ 16 bits.
>
> We should set correct precision bits in VBT that meet panel's request.
> Driver can refer to this setting then configure max brightness level
> in DCS backlight driver properly.
>
> v2: modify variable name brightness_precision_bits instead of
> max_brightness_level.
> v3: fix checkpatch warning.
>
> Cc: Ville Syrjala 
> Cc: Jani Nikula 
> Cc: Vandita Kulkarni 
> Cc: Cooper Chiou 
> Cc: William Tseng 
> Signed-off-by: Lee Shawn C 

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/display/intel_bios.c  |  3 +++
>  drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c | 10 --
>  drivers/gpu/drm/i915/i915_drv.h|  1 +
>  3 files changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index e86e6ed2d3bf..ccaf0a3100f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -483,6 +483,9 @@ parse_lfp_backlight(struct drm_i915_private *i915,
>   level = 255;
>   }
>   i915->vbt.backlight.min_brightness = min_level;
> +
> + i915->vbt.backlight.brightness_precision_bits =
> + backlight_data->brightness_precision_bits[panel_type];
>   } else {
>   level = backlight_data->level[panel_type];
>   i915->vbt.backlight.min_brightness = entry->min_brightness;
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c 
> b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
> index 584c14c4cbd0..567c086602d5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
> @@ -147,10 +147,16 @@ static void dcs_enable_backlight(const struct 
> intel_crtc_state *crtc_state,
>  static int dcs_setup_backlight(struct intel_connector *connector,
>  enum pipe unused)
>  {
> + struct drm_device *dev = connector->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
>   struct intel_panel *panel = &connector->panel;
>  
> - panel->backlight.max = PANEL_PWM_MAX_VALUE;
> - panel->backlight.level = PANEL_PWM_MAX_VALUE;
> + if (dev_priv->vbt.backlight.brightness_precision_bits > 8)
> + panel->backlight.max = (1 << 
> dev_priv->vbt.backlight.brightness_precision_bits) - 1;
> + else
> + panel->backlight.max = PANEL_PWM_MAX_VALUE;
> +
> + panel->backlight.level = panel->backlight.max;
>  
>   return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index be2392bbcecc..99a2d308b24d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -705,6 +705,7 @@ struct intel_vbt_data {
>  
>   struct {
>   u16 pwm_freq_hz;
> + u16 brightness_precision_bits;
>   bool present;
>   bool active_low_pwm;
>   u8 min_brightness;  /* min_brightness/255 of max */

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [v3 3/5] drm/i915: Get proper min cdclk if vDSC enabled

[Jani Nikula]

On Thu, 02 Sep 2021, Lee Shawn C  wrote:
> VDSC engine can process only 1 pixel per Cd clock. In case
> VDSC is used and max slice count == 1, max supported pixel
> clock should be 100% of CD clock. Then do min_cdclk and
> pixel clock comparison to get proper min cdclk.
>
> v2:
> - Check for dsc enable and slice count ==1 then allow to
>   double confirm min cdclk value.
>
> Cc: Ville Syrjala 
> Cc: Jani Nikula 
> Cc: Vandita Kulkarni 
> Cc: Cooper Chiou 
> Cc: William Tseng 
> Signed-off-by: Lee Shawn C 
> Reviewed-by: Vandita Kulkarni 
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++
>  1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 34fa4130d5c4..9aec17b33819 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2139,6 +2139,16 @@ int intel_crtc_compute_min_cdclk(const struct 
> intel_crtc_state *crtc_state)
>   /* Account for additional needs from the planes */
>   min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
>  
> + /*
> +  * VDSC engine can process only 1 pixel per Cd clock.
> +  * In case VDSC is used and max slice count == 1,
> +  * max supported pixel clock should be 100% of CD clock.
> +  * Then do min_cdclk and pixel clock comparison to get cdclk.
> +  */

To elaborate, we can't use two VDSC engines to reach an effective 2 ppc
when the slice count is 1, and are thus limited to 1 ppc.

> + if (crtc_state->dsc.compression_enable &&
> + crtc_state->dsc.slice_count == 1)
> + min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);

Acked-by: Jani Nikula 

This is the immediate fix, but I think we'll need to improve this later
on. In some cases, especially with DP and maybe not so much with DSI, we
may have cases where the min_cdclk will now exceed the max_cdclk and
fail the compute config. In that case, we should do a better job of
pruning the mode up front instead of letting userspace think it's okay,
only to fail it at this stage.

We should probably also abstract the ppc limitations in the DSC code
better, instead of having them leak here.

BR,
Jani.


> +
>   /*
>* HACK. Currently for TGL platforms we calculate
>* min_cdclk initially based on pixel_rate divided

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 01/21] drm/i915/pm: drop get_fifo_size vfunc.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> The i845_update_wm code was always calling the i845 variant,
> and the i9xx_update_wm had only a choice between i830 and i9xx
> paths, hardly worth the vfunc overhead.
>
> Signed-off-by: Dave Airlie 

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/i915_drv.h |  2 --
>  drivers/gpu/drm/i915/intel_pm.c | 20 +++-
>  2 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index be2392bbcecc..6511ec674c23 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -330,8 +330,6 @@ struct drm_i915_display_funcs {
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe);
>   int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
> - int (*get_fifo_size)(struct drm_i915_private *dev_priv,
> -  enum i9xx_plane_id i9xx_plane);
>   int (*compute_pipe_wm)(struct intel_atomic_state *state,
>  struct intel_crtc *crtc);
>   int (*compute_intermediate_wm)(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index cfc41f8fa74a..d9993eb3730d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2347,7 +2347,10 @@ static void i9xx_update_wm(struct intel_crtc 
> *unused_crtc)
>   else
>   wm_info = &i830_a_wm_info;
>  
> - fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
> + if (DISPLAY_VER(dev_priv) == 2)
> + fifo_size = i830_get_fifo_size(dev_priv, PLANE_A);
> + else
> + fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_A);
>   crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
>   if (intel_crtc_active(crtc)) {
>   const struct drm_display_mode *pipe_mode =
> @@ -2374,7 +2377,10 @@ static void i9xx_update_wm(struct intel_crtc 
> *unused_crtc)
>   if (DISPLAY_VER(dev_priv) == 2)
>   wm_info = &i830_bc_wm_info;
>  
> - fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
> + if (DISPLAY_VER(dev_priv) == 2)
> + fifo_size = i830_get_fifo_size(dev_priv, PLANE_B);
> + else
> + fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_B);
>   crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
>   if (intel_crtc_active(crtc)) {
>   const struct drm_display_mode *pipe_mode =
> @@ -2490,7 +2496,7 @@ static void i845_update_wm(struct intel_crtc 
> *unused_crtc)
>   pipe_mode = &crtc->config->hw.pipe_mode;
>   planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
>  &i845_wm_info,
> -
> dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
> +i845_get_fifo_size(dev_priv, PLANE_A),
>  4, pessimal_latency_ns);
>   fwater_lo = intel_uncore_read(&dev_priv->uncore, FW_BLC) & ~0xfff;
>   fwater_lo |= (3<<8) | planea_wm;
> @@ -8054,15 +8060,11 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
>   dev_priv->display.update_wm = i965_update_wm;
>   } else if (DISPLAY_VER(dev_priv) == 3) {
>   dev_priv->display.update_wm = i9xx_update_wm;
> - dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
>   } else if (DISPLAY_VER(dev_priv) == 2) {
> - if (INTEL_NUM_PIPES(dev_priv) == 1) {
> + if (INTEL_NUM_PIPES(dev_priv) == 1)
>   dev_priv->display.update_wm = i845_update_wm;
> - dev_priv->display.get_fifo_size = i845_get_fifo_size;
> - } else {
> + else
>   dev_priv->display.update_wm = i9xx_update_wm;
> - dev_priv->display.get_fifo_size = i830_get_fifo_size;
> - }
>   } else {
>   drm_err(&dev_priv->drm,
>   "unexpected fall-through in %s\n", __func__);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 02/21] drm/i915: make update_wm take a dev_priv.

[Jani Nikula]

On Wed, 08 Sep 2021, David Airlie  wrote:
> On Wed, Sep 8, 2021 at 10:39 AM Dave Airlie  wrote:
>>
>> From: Dave Airlie 
>>
>> The crtc was never being used here.
>
> /me realises I've noobed up the Sob on these,
>
> I've added them to my tree locally and in the branch I posted to the
> other thread., if there are comments/no comments I'll add them in a
> respin tomorrow.

Please also add commit messages to the ones that lack one.

Thanks,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 02/21] drm/i915: make update_wm take a dev_priv.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> The crtc was never being used here.

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 10 +-
>  drivers/gpu/drm/i915/i915_drv.h  |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c  | 18 ++
>  drivers/gpu/drm/i915/intel_pm.h  |  2 +-
>  4 files changed, 13 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 1f447ba776c7..d95283bf2631 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2373,7 +2373,7 @@ static void intel_post_plane_update(struct 
> intel_atomic_state *state,
>   intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
>  
>   if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
> - intel_update_watermarks(crtc);
> + intel_update_watermarks(dev_priv);
>  
>   if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
>   hsw_enable_ips(new_crtc_state);
> @@ -2529,7 +2529,7 @@ static void intel_pre_plane_update(struct 
> intel_atomic_state *state,
>   if (dev_priv->display.initial_watermarks)
>   dev_priv->display.initial_watermarks(state, crtc);
>   else if (new_crtc_state->update_wm_pre)
> - intel_update_watermarks(crtc);
> + intel_update_watermarks(dev_priv);
>   }
>  
>   /*
> @@ -3576,7 +3576,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state 
> *state,
>   if (dev_priv->display.initial_watermarks)
>   dev_priv->display.initial_watermarks(state, crtc);
>   else
> - intel_update_watermarks(crtc);
> + intel_update_watermarks(dev_priv);
>   intel_enable_pipe(new_crtc_state);
>  
>   intel_crtc_vblank_on(new_crtc_state);
> @@ -3643,7 +3643,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state 
> *state,
>   intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>  
>   if (!dev_priv->display.initial_watermarks)
> - intel_update_watermarks(crtc);
> + intel_update_watermarks(dev_priv);
>  
>   /* clock the pipe down to 640x480@60 to potentially save power */
>   if (IS_I830(dev_priv))
> @@ -3719,7 +3719,7 @@ static void intel_crtc_disable_noatomic(struct 
> intel_crtc *crtc,
>   encoder->base.crtc = NULL;
>  
>   intel_fbc_disable(crtc);
> - intel_update_watermarks(crtc);
> + intel_update_watermarks(dev_priv);
>   intel_disable_shared_dpll(crtc_state);
>  
>   intel_display_power_put_all_in_set(dev_priv, 
> &crtc->enabled_power_domains);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6511ec674c23..ef903d70ab0b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -341,7 +341,7 @@ struct drm_i915_display_funcs {
>   void (*optimize_watermarks)(struct intel_atomic_state *state,
>   struct intel_crtc *crtc);
>   int (*compute_global_watermarks)(struct intel_atomic_state *state);
> - void (*update_wm)(struct intel_crtc *crtc);
> + void (*update_wm)(struct drm_i915_private *dev_priv);
>   int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
>   u8 (*calc_voltage_level)(int cdclk);
>   /* Returns the active state of the crtc, and if the crtc is active,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d9993eb3730d..406baa49e6ad 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -881,9 +881,8 @@ static struct intel_crtc *single_enabled_crtc(struct 
> drm_i915_private *dev_priv)
>   return enabled;
>  }
>  
> -static void pnv_update_wm(struct intel_crtc *unused_crtc)
> +static void pnv_update_wm(struct drm_i915_private *dev_priv)
>  {
> - struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
>   struct intel_crtc *crtc;
>   const struct cxsr_latency *latency;
>   u32 reg;
> @@ -2253,9 +2252,8 @@ static void vlv_optimize_watermarks(struct 
> intel_atomic_state *state,
>   mutex_unlock(&dev_priv->wm.wm_mutex);
>  }
>  
> -static void i965_update_wm(struct intel_crtc *unused_crtc)
> +static void i965_update_wm(struct drm_i915_private *dev_priv)
>  {
> - struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
>   struct intel_crtc *crtc;
>   int srwm = 1;
>   int cursor_sr = 16;
> @@ -2329,9 +2327,8 @@ static void i965_update_wm(struct intel_crtc 
> *unused_crtc)
>  
>  #undef FW_WM
>  
> -static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> +static void i9xx_update_wm(struct drm_i915_private *dev_priv)
>  {
> - struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
>   c

Re: [Intel-gfx] [PATCH 04/21] drm/i915: split clock gating init from display vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> This function is only used inside intel_pm.c
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  9 ++-
>  drivers/gpu/drm/i915/intel_pm.c | 48 -
>  2 files changed, 32 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ef903d70ab0b..b93fa19892b5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -323,6 +323,11 @@ struct intel_crtc;
>  struct intel_limit;
>  struct dpll;
>  
> +/* functions used internal in intel_pm.c */
> +struct drm_i915_cg_funcs {

Nitpick, cg here is a bit terse.

Reviewed-by: Jani Nikula 


> + void (*init_clock_gating)(struct drm_i915_private *dev_priv);
> +};
> +
>  struct drm_i915_display_funcs {
>   void (*get_cdclk)(struct drm_i915_private *dev_priv,
> struct intel_cdclk_config *cdclk_config);
> @@ -365,7 +370,6 @@ struct drm_i915_display_funcs {
>   const struct drm_connector_state 
> *old_conn_state);
>   void (*fdi_link_train)(struct intel_crtc *crtc,
>  const struct intel_crtc_state *crtc_state);
> - void (*init_clock_gating)(struct drm_i915_private *dev_priv);
>   void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
>   /* clock updates for mode set */
>   /* cursor updates */
> @@ -969,6 +973,9 @@ struct drm_i915_private {
>   /* unbound hipri wq for page flips/plane updates */
>   struct workqueue_struct *flip_wq;
>  
> + /* pm private clock gating functions */
> + struct drm_i915_cg_funcs cg_funcs;
> +
>   /* Display functions */
>   struct drm_i915_display_funcs display;
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4054c6f7a2f9..73549e774881 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct 
> drm_i915_private *dev_priv)
>  
>  void intel_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
> - dev_priv->display.init_clock_gating(dev_priv);
> + dev_priv->cg_funcs.init_clock_gating(dev_priv);
>  }
>  
>  void intel_suspend_hw(struct drm_i915_private *dev_priv)
> @@ -7898,52 +7898,52 @@ static void nop_init_clock_gating(struct 
> drm_i915_private *dev_priv)
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  {
>   if (IS_ALDERLAKE_P(dev_priv))
> - dev_priv->display.init_clock_gating = adlp_init_clock_gating;
> + dev_priv->cg_funcs.init_clock_gating = adlp_init_clock_gating;
>   else if (IS_DG1(dev_priv))
> - dev_priv->display.init_clock_gating = dg1_init_clock_gating;
> + dev_priv->cg_funcs.init_clock_gating = dg1_init_clock_gating;
>   else if (GRAPHICS_VER(dev_priv) == 12)
> - dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
> + dev_priv->cg_funcs.init_clock_gating = 
> gen12lp_init_clock_gating;
>   else if (GRAPHICS_VER(dev_priv) == 11)
> - dev_priv->display.init_clock_gating = icl_init_clock_gating;
> + dev_priv->cg_funcs.init_clock_gating = icl_init_clock_gating;
>   else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
> - dev_priv->display.init_clock_gating = cfl_init_clock_gating;
> + dev_priv->cg_funcs.init_clock_gating = cfl_init_clock_gating;
>   else if (IS_SKYLAKE(dev_priv))
> - dev_priv->display.init_clock_gating = skl_init_clock_gating;
> + dev_priv->cg_funcs.init_clock_gating = skl_init_clock_gating;
>   else if (IS_KABYLAKE(dev_priv))
> - dev_priv->display.init_clock_gating = kbl_init_clock_gating;
> + dev_priv->cg_funcs.init_clock_gating = kbl_init_clock_gating;
>   else if (IS_BROXTON(dev_priv))
> - dev_priv->display.init_clock_gating = bxt_init_clock_gating;
> + dev_priv->cg_funcs.init_clock_gating = bxt_init_clock_gating;
>   else if (IS_GEMINILAKE(dev_priv))
> - dev_priv->display.init_clock_gating = glk_init_clock_gating;
> + dev_priv->cg_funcs.init_clock_gating = glk_init_clock_gating;
>   else if (IS_BROADWELL(dev_priv))
> - dev_priv->display.init_clock_gating = bdw_init_clock_gating;
> + dev_priv->cg_funcs.init_clock_gating = bdw_init_clock_gating;
>   else if (IS_CHERRYVIEW(dev_priv))
> - dev_priv->display.init_clock_gating = chv_init_clock_gating;
> + dev_priv->cg_funcs.init_clock_gating = chv_init_clock_gating;
>   else if (IS_HASWELL(dev_priv))
> - dev_priv->display.init_clock_gating = hsw_init_clock_gating;
> + dev_priv->cg_funcs.init_clock_gating = hsw_init_clock_gating;
>   else if (IS_IVYBRIDGE(dev_priv))
> - dev_priv->display.init_clock_gating = iv

Re: [Intel-gfx] [PATCH 18/21] drm/i915: drop unused function ptr and comments.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> There was some excess comments and an unused vtbl ptr.

Reviewed-by: Jani Nikula 


> ---
>  drivers/gpu/drm/i915/i915_drv.h | 7 ---
>  1 file changed, 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 085012727549..2231b93c2111 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -409,13 +409,6 @@ struct drm_i915_display_funcs {
>   void (*crtc_disable)(struct intel_atomic_state *state,
>struct intel_crtc *crtc);
>   void (*commit_modeset_enables)(struct intel_atomic_state *state);
> - void (*commit_modeset_disables)(struct intel_atomic_state *state);
> -
> - /* clock updates for mode set */
> - /* cursor updates */
> - /* render clock increase/decrease */
> - /* display clock increase/decrease */
> - /* pll clock increase/decrease */
>  };

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [v4 0/5] DSI driver improvement

[Lee Shawn C]

v2: Get data length of brightness value more easily while driver try to
read/write MIPI_DCS_DISPLAY_BRIGHTNESS command.
v3: fix checkpatch warning.

Signed-off-by: Lee Shawn C 

Lee Shawn C (5):
  drm/i915/dsi: wait for header and payload credit available
  drm/i915/dsi: refine send MIPI DCS command sequence
  drm/i915: Get proper min cdclk if vDSC enabled
  drm/i915/dsi: Retrieve max brightness level from VBT
  drm/i915/dsi: Read/write proper brightness value via MIPI DCS command

 drivers/gpu/drm/i915/display/icl_dsi.c| 50 +--
 drivers/gpu/drm/i915/display/intel_bios.c |  3 ++
 drivers/gpu/drm/i915/display/intel_cdclk.c| 10 
 .../i915/display/intel_dsi_dcs_backlight.c| 33 
 drivers/gpu/drm/i915/i915_drv.h   |  1 +
 5 files changed, 62 insertions(+), 35 deletions(-)

-- 
2.17.1

[Intel-gfx] [v4 1/5] drm/i915/dsi: wait for header and payload credit available

[Lee Shawn C]

Driver should wait for free header or payload buffer in FIFO.
It would be good to wait a while for HW to release credit before
give it up to write to HW. Without sending initailize command
sets completely. It would caused MIPI display can't light up properly.

Cc: Ville Syrjala 
Cc: Jani Nikula 
Cc: Vandita Kulkarni 
Cc: Cooper Chiou 
Cc: William Tseng 
Signed-off-by: Lee Shawn C 
Reviewed-by: Vandita Kulkarni 
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 40 --
 1 file changed, 19 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c 
b/drivers/gpu/drm/i915/display/icl_dsi.c
index a1e35180d5dd..44289003b709 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -55,20 +55,28 @@ static int payload_credits_available(struct 
drm_i915_private *dev_priv,
>> FREE_PLOAD_CREDIT_SHIFT;
 }
 
-static void wait_for_header_credits(struct drm_i915_private *dev_priv,
-   enum transcoder dsi_trans)
+static bool wait_for_header_credits(struct drm_i915_private *dev_priv,
+   enum transcoder dsi_trans, int hdr_credit)
 {
if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
-   MAX_HEADER_CREDIT, 100))
+   hdr_credit, 100)) {
drm_err(&dev_priv->drm, "DSI header credits not released\n");
+   return false;
+   }
+
+   return true;
 }
 
-static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
-enum transcoder dsi_trans)
+static bool wait_for_payload_credits(struct drm_i915_private *dev_priv,
+enum transcoder dsi_trans, int 
payld_credit)
 {
if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
-   MAX_PLOAD_CREDIT, 100))
+   payld_credit, 100)) {
drm_err(&dev_priv->drm, "DSI payload credits not released\n");
+   return false;
+   }
+
+   return true;
 }
 
 static enum transcoder dsi_port_to_transcoder(enum port port)
@@ -91,8 +99,8 @@ static void wait_for_cmds_dispatched_to_panel(struct 
intel_encoder *encoder)
/* wait for header/payload credits to be released */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
-   wait_for_header_credits(dev_priv, dsi_trans);
-   wait_for_payload_credits(dev_priv, dsi_trans);
+   wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
+   wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT);
}
 
/* send nop DCS command */
@@ -109,7 +117,7 @@ static void wait_for_cmds_dispatched_to_panel(struct 
intel_encoder *encoder)
/* wait for header credits to be released */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
-   wait_for_header_credits(dev_priv, dsi_trans);
+   wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
}
 
/* wait for LP TX in progress bit to be cleared */
@@ -127,18 +135,13 @@ static bool add_payld_to_queue(struct intel_dsi_host 
*host, const u8 *data,
struct intel_dsi *intel_dsi = host->intel_dsi;
struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
-   int free_credits;
int i, j;
 
for (i = 0; i < len; i += 4) {
u32 tmp = 0;
 
-   free_credits = payload_credits_available(dev_priv, dsi_trans);
-   if (free_credits < 1) {
-   drm_err(&dev_priv->drm,
-   "Payload credit not available\n");
+   if (!wait_for_payload_credits(dev_priv, dsi_trans, 1))
return false;
-   }
 
for (j = 0; j < min_t(u32, len - i, 4); j++)
tmp |= *data++ << 8 * j;
@@ -156,15 +159,10 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
u32 tmp;
-   int free_credits;
 
/* check if header credit available */
-   free_credits = header_credits_available(dev_priv, dsi_trans);
-   if (free_credits < 1) {
-   drm_err(&dev_priv->drm,
-   "send pkt header failed, not enough hdr credits\n");
+   if (!wait_for_header_credits(dev_priv, dsi_trans, 1))
return -1;
-   }
 
tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans));
 
-- 
2.17.1

[Intel-gfx] [v4 3/5] drm/i915: Get proper min cdclk if vDSC enabled

[Lee Shawn C]

VDSC engine can process only 1 pixel per Cd clock. In case
VDSC is used and max slice count == 1, max supported pixel
clock should be 100% of CD clock. Then do min_cdclk and
pixel clock comparison to get proper min cdclk.

v2:
- Check for dsc enable and slice count ==1 then allow to
  double confirm min cdclk value.

Cc: Ville Syrjala 
Cc: Jani Nikula 
Cc: Vandita Kulkarni 
Cc: Cooper Chiou 
Cc: William Tseng 
Signed-off-by: Lee Shawn C 
Reviewed-by: Vandita Kulkarni 
Acked-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 34fa4130d5c4..9aec17b33819 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2139,6 +2139,16 @@ int intel_crtc_compute_min_cdclk(const struct 
intel_crtc_state *crtc_state)
/* Account for additional needs from the planes */
min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
 
+   /*
+* VDSC engine can process only 1 pixel per Cd clock.
+* In case VDSC is used and max slice count == 1,
+* max supported pixel clock should be 100% of CD clock.
+* Then do min_cdclk and pixel clock comparison to get cdclk.
+*/
+   if (crtc_state->dsc.compression_enable &&
+   crtc_state->dsc.slice_count == 1)
+   min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
+
/*
 * HACK. Currently for TGL platforms we calculate
 * min_cdclk initially based on pixel_rate divided
-- 
2.17.1

[Intel-gfx] [v4 2/5] drm/i915/dsi: refine send MIPI DCS command sequence

[Lee Shawn C]

According to chapter "Sending Commands to the Panel" in bspec #29738
and #49188. If driver try to send DCS long pakcet, we have to program
TX payload register at first. And configure TX header HW register later.
DSC long packet would not be sent properly if we don't follow this
sequence.

Cc: Ville Syrjala 
Cc: Jani Nikula 
Cc: Vandita Kulkarni 
Cc: Cooper Chiou 
Cc: William Tseng 
Signed-off-by: Lee Shawn C 
Reviewed-by: Vandita Kulkarni 
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c 
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 44289003b709..060bc8fb0d30 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1831,11 +1831,6 @@ static ssize_t gen11_dsi_host_transfer(struct 
mipi_dsi_host *host,
if (msg->flags & MIPI_DSI_MSG_USE_LPM)
enable_lpdt = true;
 
-   /* send packet header */
-   ret  = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
-   if (ret < 0)
-   return ret;
-
/* only long packet contains payload */
if (mipi_dsi_packet_format_is_long(msg->type)) {
ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt);
@@ -1843,6 +1838,11 @@ static ssize_t gen11_dsi_host_transfer(struct 
mipi_dsi_host *host,
return ret;
}
 
+   /* send packet header */
+   ret  = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
+   if (ret < 0)
+   return ret;
+
//TODO: add payload receive code if needed
 
ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
-- 
2.17.1

[Intel-gfx] [v4 4/5] drm/i915/dsi: Retrieve max brightness level from VBT

[Lee Shawn C]

So far, DCS backlight driver hardcode (0xFF) for max brightness level.
MIPI DCS spec allow max 0x for set_display_brightness (51h) command.
And VBT brightness precision bits can support 8 ~ 16 bits.

We should set correct precision bits in VBT that meet panel's request.
Driver can refer to this setting then configure max brightness level
in DCS backlight driver properly.

v2: modify variable name brightness_precision_bits instead of
max_brightness_level.
v3: fix checkpatch warning.

Cc: Ville Syrjala 
Cc: Jani Nikula 
Cc: Vandita Kulkarni 
Cc: Cooper Chiou 
Cc: William Tseng 
Signed-off-by: Lee Shawn C 
Reviewed-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_bios.c  |  3 +++
 drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c | 10 --
 drivers/gpu/drm/i915/i915_drv.h|  1 +
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index e86e6ed2d3bf..ccaf0a3100f7 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -483,6 +483,9 @@ parse_lfp_backlight(struct drm_i915_private *i915,
level = 255;
}
i915->vbt.backlight.min_brightness = min_level;
+
+   i915->vbt.backlight.brightness_precision_bits =
+   backlight_data->brightness_precision_bits[panel_type];
} else {
level = backlight_data->level[panel_type];
i915->vbt.backlight.min_brightness = entry->min_brightness;
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c 
b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
index 584c14c4cbd0..567c086602d5 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
@@ -147,10 +147,16 @@ static void dcs_enable_backlight(const struct 
intel_crtc_state *crtc_state,
 static int dcs_setup_backlight(struct intel_connector *connector,
   enum pipe unused)
 {
+   struct drm_device *dev = connector->base.dev;
+   struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_panel *panel = &connector->panel;
 
-   panel->backlight.max = PANEL_PWM_MAX_VALUE;
-   panel->backlight.level = PANEL_PWM_MAX_VALUE;
+   if (dev_priv->vbt.backlight.brightness_precision_bits > 8)
+   panel->backlight.max = (1 << 
dev_priv->vbt.backlight.brightness_precision_bits) - 1;
+   else
+   panel->backlight.max = PANEL_PWM_MAX_VALUE;
+
+   panel->backlight.level = panel->backlight.max;
 
return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index be2392bbcecc..99a2d308b24d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -705,6 +705,7 @@ struct intel_vbt_data {
 
struct {
u16 pwm_freq_hz;
+   u16 brightness_precision_bits;
bool present;
bool active_low_pwm;
u8 min_brightness;  /* min_brightness/255 of max */
-- 
2.17.1

[Intel-gfx] [v4 5/5] drm/i915/dsi: Read/write proper brightness value via MIPI DCS command

[Lee Shawn C]

Driver has to swap the endian before send brightness level value
to tcon.

v2: Use __be16 instead of u16 to fix sparse warning.
v3: Send one or two bytes brightness value depend on the precision.
v4: get data length of brightness value more easily.

Reported-by: kernel test robot 
Cc: Ville Syrjala 
Cc: Jani Nikula 
Cc: Vandita Kulkarni 
Cc: Cooper Chiou 
Cc: William Tseng 
Signed-off-by: Lee Shawn C 
Reviewed-by: Jani Nikula 
---
 .../i915/display/intel_dsi_dcs_backlight.c| 23 +--
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c 
b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
index 567c086602d5..f61ed82e8867 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
@@ -47,33 +47,42 @@ static u32 dcs_get_backlight(struct intel_connector 
*connector, enum pipe unused
 {
struct intel_encoder *encoder = intel_attached_encoder(connector);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+   struct intel_panel *panel = &connector->panel;
struct mipi_dsi_device *dsi_device;
-   u8 data = 0;
+   u8 data[2] = {};
enum port port;
+   size_t len = panel->backlight.max > U8_MAX ? 2 : 1;
 
-   /* FIXME: Need to take care of 16 bit brightness level */
for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
dsi_device = intel_dsi->dsi_hosts[port]->device;
mipi_dsi_dcs_read(dsi_device, MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
- &data, sizeof(data));
+ &data, len);
break;
}
 
-   return data;
+   return (data[1] << 8) | data[0];
 }
 
 static void dcs_set_backlight(const struct drm_connector_state *conn_state, 
u32 level)
 {
struct intel_dsi *intel_dsi = 
enc_to_intel_dsi(to_intel_encoder(conn_state->best_encoder));
+   struct intel_panel *panel = 
&to_intel_connector(conn_state->connector)->panel;
struct mipi_dsi_device *dsi_device;
-   u8 data = level;
+   u8 data[2] = {};
enum port port;
+   size_t len = panel->backlight.max > U8_MAX ? 2 : 1;
+
+   if (len == 1) {
+   data[0] = level;
+   } else {
+   data[0] = level >> 8;
+   data[1] = level;
+   }
 
-   /* FIXME: Need to take care of 16 bit brightness level */
for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
dsi_device = intel_dsi->dsi_hosts[port]->device;
mipi_dsi_dcs_write(dsi_device, MIPI_DCS_SET_DISPLAY_BRIGHTNESS,
-  &data, sizeof(data));
+  &data, len);
}
 }
 
-- 
2.17.1

Re: [Intel-gfx] [PATCH 17/21] drm/i915: constify the cdclk vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> This is a bit of a twisty one since each platform is slightly
> different, so might take some more review care.

Yes, it was a PITA to review. But the end result is good.

Reviewed-by: Jani Nikula 


> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c| 306 --
>  drivers/gpu/drm/i915/display/intel_display.c  |   2 +-
>  .../drm/i915/display/intel_display_power.c|   2 +-
>  drivers/gpu/drm/i915/i915_drv.h   |   2 +-
>  4 files changed, 211 insertions(+), 101 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index c12b4e6bf5f5..9ce053bea022 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1466,7 +1466,7 @@ static void bxt_get_cdclk(struct drm_i915_private 
> *dev_priv,
>* at least what the CDCLK frequency requires.
>*/
>   cdclk_config->voltage_level =
> - dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config->cdclk);
> + dev_priv->cdclk_funcs->calc_voltage_level(cdclk_config->cdclk);
>  }
>  
>  static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
> @@ -1777,7 +1777,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private 
> *dev_priv)
>   cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
>   cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
>   cdclk_config.voltage_level =
> - dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config.cdclk);
> + dev_priv->cdclk_funcs->calc_voltage_level(cdclk_config.cdclk);
>  
>   bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
>  }
> @@ -1789,7 +1789,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private 
> *dev_priv)
>   cdclk_config.cdclk = cdclk_config.bypass;
>   cdclk_config.vco = 0;
>   cdclk_config.voltage_level =
> - dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config.cdclk);
> + dev_priv->cdclk_funcs->calc_voltage_level(cdclk_config.cdclk);
>  
>   bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
>  }
> @@ -1932,7 +1932,7 @@ static void intel_set_cdclk(struct drm_i915_private 
> *dev_priv,
>   if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
>   return;
>  
> - if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
> + if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))
>   return;
>  
>   intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
> @@ -1956,7 +1956,7 @@ static void intel_set_cdclk(struct drm_i915_private 
> *dev_priv,
>&dev_priv->gmbus_mutex);
>   }
>  
> - dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
> + dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe);
>  
>   for_each_intel_dp(&dev_priv->drm, encoder) {
>   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> @@ -2414,7 +2414,7 @@ static int bxt_modeset_calc_cdclk(struct 
> intel_cdclk_state *cdclk_state)
>   cdclk_state->logical.cdclk = cdclk;
>   cdclk_state->logical.voltage_level =
>   max_t(int, min_voltage_level,
> -   dev_priv->cdclk_funcs.calc_voltage_level(cdclk));
> +   dev_priv->cdclk_funcs->calc_voltage_level(cdclk));
>  
>   if (!cdclk_state->active_pipes) {
>   cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
> @@ -2423,7 +2423,7 @@ static int bxt_modeset_calc_cdclk(struct 
> intel_cdclk_state *cdclk_state)
>   cdclk_state->actual.vco = vco;
>   cdclk_state->actual.cdclk = cdclk;
>   cdclk_state->actual.voltage_level =
> - dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
> + dev_priv->cdclk_funcs->calc_voltage_level(cdclk);
>   } else {
>   cdclk_state->actual = cdclk_state->logical;
>   }
> @@ -2515,7 +2515,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state 
> *state)
>   new_cdclk_state->active_pipes =
>   intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
>  
> - ret = dev_priv->cdclk_funcs.modeset_calc_cdclk(new_cdclk_state);
> + ret = dev_priv->cdclk_funcs->modeset_calc_cdclk(new_cdclk_state);
>   if (ret)
>   return ret;
>  
> @@ -2695,7 +2695,7 @@ void intel_update_max_cdclk(struct drm_i915_private 
> *dev_priv)
>   */
>  void intel_update_cdclk(struct drm_i915_private *dev_priv)
>  {
> - dev_priv->cdclk_funcs.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
> + dev_priv->cdclk_funcs->get_cdclk(dev_priv, &dev_priv->cdclk.hw);
>  
>   /*
>* 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
> @@ -2845,6 +2845,157 @@ u32 intel_read_rawclk(struct drm_i915_private 
> *dev_priv)
>   return freq;
>  }
>  
> +static struct drm_i915_display_

Re: [Intel-gfx] [PATCH 19/21] drm/i915: constify display function vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 

Reviewed-by: Jani Nikula 


>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 81 
>  drivers/gpu/drm/i915/i915_drv.h  |  2 +-
>  2 files changed, 52 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 09c9dc741026..20fd35c6858c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3736,7 +3736,7 @@ static void intel_crtc_disable_noatomic(struct 
> intel_crtc *crtc,
>  
>   drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
>  
> - dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
> + dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);
>  
>   drm_atomic_state_put(state);
>  
> @@ -5941,7 +5941,7 @@ static bool intel_crtc_get_pipe_config(struct 
> intel_crtc_state *crtc_state)
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>  
> - if (!i915->display.get_pipe_config(crtc, crtc_state))
> + if (!i915->display->get_pipe_config(crtc, crtc_state))
>   return false;
>  
>   crtc_state->hw.active = true;
> @@ -9778,7 +9778,7 @@ static void intel_enable_crtc(struct intel_atomic_state 
> *state,
>  
>   intel_crtc_update_active_timings(new_crtc_state);
>  
> - dev_priv->display.crtc_enable(state, crtc);
> + dev_priv->display->crtc_enable(state, crtc);
>  
>   if (new_crtc_state->bigjoiner_slave)
>   return;
> @@ -9866,7 +9866,7 @@ static void intel_old_crtc_state_disables(struct 
> intel_atomic_state *state,
>*/
>   intel_crtc_disable_pipe_crc(crtc);
>  
> - dev_priv->display.crtc_disable(state, crtc);
> + dev_priv->display->crtc_disable(state, crtc);
>   crtc->active = false;
>   intel_fbc_disable(crtc);
>   intel_disable_shared_dpll(old_crtc_state);
> @@ -10246,7 +10246,7 @@ static void intel_atomic_commit_tail(struct 
> intel_atomic_state *state)
>   }
>  
>   /* Now enable the clocks, plane, pipe, and connectors that we set up. */
> - dev_priv->display.commit_modeset_enables(state);
> + dev_priv->display->commit_modeset_enables(state);
>  
>   if (state->modeset) {
>   intel_encoders_update_complete(state);
> @@ -11250,6 +11250,46 @@ static const struct drm_mode_config_funcs 
> intel_mode_funcs = {
>   .atomic_state_free = intel_atomic_state_free,
>  };
>  
> +static const struct drm_i915_display_funcs skl_display_funcs = {
> + .get_pipe_config = hsw_get_pipe_config,
> + .crtc_enable = hsw_crtc_enable,
> + .crtc_disable = hsw_crtc_disable,
> + .commit_modeset_enables = skl_commit_modeset_enables,
> + .get_initial_plane_config = skl_get_initial_plane_config,
> +};
> +
> +static const struct drm_i915_display_funcs ddi_display_funcs = {
> + .get_pipe_config = hsw_get_pipe_config,
> + .crtc_enable = hsw_crtc_enable,
> + .crtc_disable = hsw_crtc_disable,
> + .commit_modeset_enables = intel_commit_modeset_enables,
> + .get_initial_plane_config = i9xx_get_initial_plane_config,
> +};
> +
> +static const struct drm_i915_display_funcs pch_split_display_funcs = {
> + .get_pipe_config = ilk_get_pipe_config,
> + .crtc_enable = ilk_crtc_enable,
> + .crtc_disable = ilk_crtc_disable,
> + .commit_modeset_enables = intel_commit_modeset_enables,
> + .get_initial_plane_config = i9xx_get_initial_plane_config,
> +};
> +
> +static const struct drm_i915_display_funcs vlv_display_funcs = {
> + .get_pipe_config = i9xx_get_pipe_config,
> + .crtc_enable = valleyview_crtc_enable,
> + .crtc_disable = i9xx_crtc_disable,
> + .commit_modeset_enables = intel_commit_modeset_enables,
> + .get_initial_plane_config = i9xx_get_initial_plane_config,
> +};
> +
> +static const struct drm_i915_display_funcs i9xx_display_funcs = {
> + .get_pipe_config = i9xx_get_pipe_config,
> + .crtc_enable = i9xx_crtc_enable,
> + .crtc_disable = i9xx_crtc_disable,
> + .commit_modeset_enables = intel_commit_modeset_enables,
> + .get_initial_plane_config = i9xx_get_initial_plane_config,
> +};
> +
>  /**
>   * intel_init_display_hooks - initialize the display modesetting hooks
>   * @dev_priv: device private
> @@ -11265,38 +11305,19 @@ void intel_init_display_hooks(struct 
> drm_i915_private *dev_priv)
>   intel_dpll_init_clock_hook(dev_priv);
>  
>   if (DISPLAY_VER(dev_priv) >= 9) {
> - dev_priv->display.get_pipe_config = hsw_get_pipe_config;
> - dev_priv->display.crtc_enable = hsw_crtc_enable;
> - dev_priv->display.crtc_disable = hsw_crtc_disable;
> + dev_priv->display = &skl_display_funcs;
>   } else if (HAS_DDI(dev_priv)) {
> - dev_priv->display.get_pipe_config = hsw_get_p

Re: [Intel-gfx] linux-next: build failure after merge of the drm tree

[Masahiro Yamada]

On Mon, Sep 6, 2021 at 4:34 PM Daniel Vetter  wrote:
>
> On Mon, Sep 6, 2021 at 12:49 AM Stephen Rothwell  
> wrote:
> > Hi all,
> >
> > On Thu, 2 Sep 2021 07:50:38 +1000 Stephen Rothwell  
> > wrote:
> > >
> > > On Fri, 20 Aug 2021 15:23:34 +0900 Masahiro Yamada  
> > > wrote:
> > > >
> > > > On Fri, Aug 20, 2021 at 11:33 AM Stephen Rothwell 
> > > >  wrote:
> > > > >
> >  > > After merging the drm tree, today's linux-next build (x86_64 
> > allmodconfig)
> > > > > failed like this:
> > > > >
> > > > > In file included from drivers/gpu/drm/i915/i915_debugfs.c:39:
> > > > > drivers/gpu/drm/i915/gt/intel_gt_requests.h:9:10: fatal error: 
> > > > > stddef.h: No such file or directory
> > > > > 9 | #include 
> > > > >   |  ^~
> > > > >
> > > > > Caused by commit
> > > > >
> > > > >   564f963eabd1 ("isystem: delete global -isystem compile option")
> > > > >
> > > > > from the kbuild tree interacting with commit
> > > > >
> > > > >   b97060a99b01 ("drm/i915/guc: Update intel_gt_wait_for_idle to work 
> > > > > with GuC")
> > > > >
> > > > > I have applied the following patch for today.
> > > >
> > > >
> > > > Thanks.
> > > >
> > > > This fix-up does not depend on my kbuild tree in any way.
> > > >
> > > > So, the drm maintainer can apply it to his tree.
> > > >
> > > > Perhaps with
> > > >
> > > > Fixes: b97060a99b01 ("drm/i915/guc: Update intel_gt_wait_for_idle to
> > > > work with GuC")
> > >
> > > OK, so that didn't happen so I will now apply the merge fix up to the
> > > merge of the kbuild tree.
> > >
> > > > > From: Stephen Rothwell 
> > > > > Date: Fri, 20 Aug 2021 12:24:19 +1000
> > > > > Subject: [PATCH] drm/i915: use linux/stddef.h due to "isystem: 
> > > > > trim/fixup stdarg.h and other headers"
> > > > >
> > > > > Signed-off-by: Stephen Rothwell 
> > > > > ---
> > > > >  drivers/gpu/drm/i915/gt/intel_gt_requests.h | 2 +-
> > > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.h 
> > > > > b/drivers/gpu/drm/i915/gt/intel_gt_requests.h
> > > > > index 51dbe0e3294e..d2969f68dd64 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt_requests.h
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.h
> > > > > @@ -6,7 +6,7 @@
> > > > >  #ifndef INTEL_GT_REQUESTS_H
> > > > >  #define INTEL_GT_REQUESTS_H
> > > > >
> > > > > -#include 
> > > > > +#include 
> > > > >
> > > > >  struct intel_engine_cs;
> > > > >  struct intel_gt;
> > > > > --
> > > > > 2.32.0
> >
> > Ping?  I am still applying this ...
>
> Apologies, this fell through a lot of cracks. I applied this to drm-next now.



Rather, I was planning to apply this fix to my kbuild tree.

Since you guys did not fix the issue in time,
I ended up with dropping [1] from my pull request.

I want to get [1] merged in this MW.

If I postponed it, somebody would add new
 or  inclusion in the next development
cycle, I will never make it in the mainline.

[1] https://lore.kernel.org/linux-kernel/YQhY40teUJcTc5H4@localhost.localdomain/





> Matt/John, as author/committer it's your job to make sure issues and
> fixes for the stuff you're pushing don't get lost. I'd have expected
> John to apply this to at least drm-intel-gt-next (it's not even
> there).
>
> Joonas, I think this is the 2nd or 3rd or so issue this release cycle
> where some compile fix got stuck a bit because drm-intel-gt-next isn't
> in linux-next. Can we please fix that? It probably needs some changes
> to the dim script.
>
> Cheers, Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch



-- 
Best Regards
Masahiro Yamada

Re: [Intel-gfx] [PATCH 20/21] drm/i915: constify clock gating init vtable.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> I used a macro to avoid making any really silly mistakes here.
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c | 77 +++--
>  2 files changed, 54 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fbcafc7cc075..44094a25a110 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -990,7 +990,7 @@ struct drm_i915_private {
>   struct workqueue_struct *flip_wq;
>  
>   /* pm private clock gating functions */
> - struct drm_i915_cg_funcs cg_funcs;
> + const struct drm_i915_cg_funcs *cg_funcs;
>  
>   /* pm display functions */
>   struct drm_i915_wm_disp_funcs wm_disp;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7a457646fb84..44f5582531ac 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct 
> drm_i915_private *dev_priv)
>  
>  void intel_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
> - dev_priv->cg_funcs.init_clock_gating(dev_priv);
> + dev_priv->cg_funcs->init_clock_gating(dev_priv);
>  }
>  
>  void intel_suspend_hw(struct drm_i915_private *dev_priv)
> @@ -7886,6 +7886,35 @@ static void nop_init_clock_gating(struct 
> drm_i915_private *dev_priv)
>   "No clock gating settings or workarounds applied.\n");
>  }
>  
> +#define CG_FUNCS(platform) \
> +static const struct drm_i915_cg_funcs platform##_cg_funcs = { \
> + .init_clock_gating = platform##_init_clock_gating \
> +}
> +
> +CG_FUNCS(adlp);
> +CG_FUNCS(dg1);
> +CG_FUNCS(gen12lp);
> +CG_FUNCS(icl);
> +CG_FUNCS(cfl);
> +CG_FUNCS(skl);
> +CG_FUNCS(kbl);
> +CG_FUNCS(bxt);
> +CG_FUNCS(glk);
> +CG_FUNCS(bdw);
> +CG_FUNCS(chv);
> +CG_FUNCS(hsw);
> +CG_FUNCS(ivb);
> +CG_FUNCS(vlv);
> +CG_FUNCS(gen6);
> +CG_FUNCS(ilk);
> +CG_FUNCS(g4x);
> +CG_FUNCS(i965gm);
> +CG_FUNCS(i965g);
> +CG_FUNCS(gen3);
> +CG_FUNCS(i85x);
> +CG_FUNCS(i830);
> +CG_FUNCS(nop);

#undef CF_FUNCS

Reviewed-by: Jani Nikula 


> +
>  /**
>   * intel_init_clock_gating_hooks - setup the clock gating hooks
>   * @dev_priv: device private
> @@ -7898,52 +7927,52 @@ static void nop_init_clock_gating(struct 
> drm_i915_private *dev_priv)
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  {
>   if (IS_ALDERLAKE_P(dev_priv))
> - dev_priv->cg_funcs.init_clock_gating = adlp_init_clock_gating;
> + dev_priv->cg_funcs = &adlp_cg_funcs;
>   else if (IS_DG1(dev_priv))
> - dev_priv->cg_funcs.init_clock_gating = dg1_init_clock_gating;
> + dev_priv->cg_funcs = &dg1_cg_funcs;
>   else if (GRAPHICS_VER(dev_priv) == 12)
> - dev_priv->cg_funcs.init_clock_gating = 
> gen12lp_init_clock_gating;
> + dev_priv->cg_funcs = &gen12lp_cg_funcs;
>   else if (GRAPHICS_VER(dev_priv) == 11)
> - dev_priv->cg_funcs.init_clock_gating = icl_init_clock_gating;
> + dev_priv->cg_funcs = &icl_cg_funcs;
>   else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
> - dev_priv->cg_funcs.init_clock_gating = cfl_init_clock_gating;
> + dev_priv->cg_funcs = &cfl_cg_funcs;
>   else if (IS_SKYLAKE(dev_priv))
> - dev_priv->cg_funcs.init_clock_gating = skl_init_clock_gating;
> + dev_priv->cg_funcs = &skl_cg_funcs;
>   else if (IS_KABYLAKE(dev_priv))
> - dev_priv->cg_funcs.init_clock_gating = kbl_init_clock_gating;
> + dev_priv->cg_funcs = &kbl_cg_funcs;
>   else if (IS_BROXTON(dev_priv))
> - dev_priv->cg_funcs.init_clock_gating = bxt_init_clock_gating;
> + dev_priv->cg_funcs = &bxt_cg_funcs;
>   else if (IS_GEMINILAKE(dev_priv))
> - dev_priv->cg_funcs.init_clock_gating = glk_init_clock_gating;
> + dev_priv->cg_funcs = &glk_cg_funcs;
>   else if (IS_BROADWELL(dev_priv))
> - dev_priv->cg_funcs.init_clock_gating = bdw_init_clock_gating;
> + dev_priv->cg_funcs = &bdw_cg_funcs;
>   else if (IS_CHERRYVIEW(dev_priv))
> - dev_priv->cg_funcs.init_clock_gating = chv_init_clock_gating;
> + dev_priv->cg_funcs = &chv_cg_funcs;
>   else if (IS_HASWELL(dev_priv))
> - dev_priv->cg_funcs.init_clock_gating = hsw_init_clock_gating;
> + dev_priv->cg_funcs = &hsw_cg_funcs;
>   else if (IS_IVYBRIDGE(dev_priv))
> - dev_priv->cg_funcs.init_clock_gating = ivb_init_clock_gating;
> + dev_priv->cg_funcs = &ivb_cg_funcs;
>   else if (IS_VALLEYVIEW(dev_priv))
> - dev_priv->cg_funcs.init_clock_gating = vlv_init_clock_gating;
> + dev_priv->cg_funcs = &vlv_cg_funcs;
>   else if (GRAPHICS_VER(dev_priv) == 6)
> - d

Re: [Intel-gfx] [PATCH 20/21] drm/i915: constify clock gating init vtable.

[Jani Nikula]

On Wed, 08 Sep 2021, Jani Nikula  wrote:
> On Wed, 08 Sep 2021, Dave Airlie  wrote:
>> From: Dave Airlie 
>>
>> I used a macro to avoid making any really silly mistakes here.
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h |  2 +-
>>  drivers/gpu/drm/i915/intel_pm.c | 77 +++--
>>  2 files changed, 54 insertions(+), 25 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index fbcafc7cc075..44094a25a110 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -990,7 +990,7 @@ struct drm_i915_private {
>>  struct workqueue_struct *flip_wq;
>>  
>>  /* pm private clock gating functions */
>> -struct drm_i915_cg_funcs cg_funcs;
>> +const struct drm_i915_cg_funcs *cg_funcs;
>>  
>>  /* pm display functions */
>>  struct drm_i915_wm_disp_funcs wm_disp;
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c 
>> b/drivers/gpu/drm/i915/intel_pm.c
>> index 7a457646fb84..44f5582531ac 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct 
>> drm_i915_private *dev_priv)
>>  
>>  void intel_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>> -dev_priv->cg_funcs.init_clock_gating(dev_priv);
>> +dev_priv->cg_funcs->init_clock_gating(dev_priv);
>>  }
>>  
>>  void intel_suspend_hw(struct drm_i915_private *dev_priv)
>> @@ -7886,6 +7886,35 @@ static void nop_init_clock_gating(struct 
>> drm_i915_private *dev_priv)
>>  "No clock gating settings or workarounds applied.\n");
>>  }
>>  
>> +#define CG_FUNCS(platform) \
>> +static const struct drm_i915_cg_funcs platform##_cg_funcs = { \
>> +.init_clock_gating = platform##_init_clock_gating \
>> +}
>> +
>> +CG_FUNCS(adlp);
>> +CG_FUNCS(dg1);
>> +CG_FUNCS(gen12lp);
>> +CG_FUNCS(icl);
>> +CG_FUNCS(cfl);
>> +CG_FUNCS(skl);
>> +CG_FUNCS(kbl);
>> +CG_FUNCS(bxt);
>> +CG_FUNCS(glk);
>> +CG_FUNCS(bdw);
>> +CG_FUNCS(chv);
>> +CG_FUNCS(hsw);
>> +CG_FUNCS(ivb);
>> +CG_FUNCS(vlv);
>> +CG_FUNCS(gen6);
>> +CG_FUNCS(ilk);
>> +CG_FUNCS(g4x);
>> +CG_FUNCS(i965gm);
>> +CG_FUNCS(i965g);
>> +CG_FUNCS(gen3);
>> +CG_FUNCS(i85x);
>> +CG_FUNCS(i830);
>> +CG_FUNCS(nop);
>
> #undef CF_FUNCS

#undef CG_FUNCS, obviously.

>
> Reviewed-by: Jani Nikula 
>
>
>> +
>>  /**
>>   * intel_init_clock_gating_hooks - setup the clock gating hooks
>>   * @dev_priv: device private
>> @@ -7898,52 +7927,52 @@ static void nop_init_clock_gating(struct 
>> drm_i915_private *dev_priv)
>>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>>  {
>>  if (IS_ALDERLAKE_P(dev_priv))
>> -dev_priv->cg_funcs.init_clock_gating = adlp_init_clock_gating;
>> +dev_priv->cg_funcs = &adlp_cg_funcs;
>>  else if (IS_DG1(dev_priv))
>> -dev_priv->cg_funcs.init_clock_gating = dg1_init_clock_gating;
>> +dev_priv->cg_funcs = &dg1_cg_funcs;
>>  else if (GRAPHICS_VER(dev_priv) == 12)
>> -dev_priv->cg_funcs.init_clock_gating = 
>> gen12lp_init_clock_gating;
>> +dev_priv->cg_funcs = &gen12lp_cg_funcs;
>>  else if (GRAPHICS_VER(dev_priv) == 11)
>> -dev_priv->cg_funcs.init_clock_gating = icl_init_clock_gating;
>> +dev_priv->cg_funcs = &icl_cg_funcs;
>>  else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
>> -dev_priv->cg_funcs.init_clock_gating = cfl_init_clock_gating;
>> +dev_priv->cg_funcs = &cfl_cg_funcs;
>>  else if (IS_SKYLAKE(dev_priv))
>> -dev_priv->cg_funcs.init_clock_gating = skl_init_clock_gating;
>> +dev_priv->cg_funcs = &skl_cg_funcs;
>>  else if (IS_KABYLAKE(dev_priv))
>> -dev_priv->cg_funcs.init_clock_gating = kbl_init_clock_gating;
>> +dev_priv->cg_funcs = &kbl_cg_funcs;
>>  else if (IS_BROXTON(dev_priv))
>> -dev_priv->cg_funcs.init_clock_gating = bxt_init_clock_gating;
>> +dev_priv->cg_funcs = &bxt_cg_funcs;
>>  else if (IS_GEMINILAKE(dev_priv))
>> -dev_priv->cg_funcs.init_clock_gating = glk_init_clock_gating;
>> +dev_priv->cg_funcs = &glk_cg_funcs;
>>  else if (IS_BROADWELL(dev_priv))
>> -dev_priv->cg_funcs.init_clock_gating = bdw_init_clock_gating;
>> +dev_priv->cg_funcs = &bdw_cg_funcs;
>>  else if (IS_CHERRYVIEW(dev_priv))
>> -dev_priv->cg_funcs.init_clock_gating = chv_init_clock_gating;
>> +dev_priv->cg_funcs = &chv_cg_funcs;
>>  else if (IS_HASWELL(dev_priv))
>> -dev_priv->cg_funcs.init_clock_gating = hsw_init_clock_gating;
>> +dev_priv->cg_funcs = &hsw_cg_funcs;
>>  else if (IS_IVYBRIDGE(dev_priv))
>> -dev_priv->cg_funcs.init_clock_gating = ivb_init_clock_gating;
>> +dev_priv->cg_funcs = &ivb_cg_funcs;
>>  else if (IS_VALLEYVIEW(dev_priv))
>> -dev_priv->cg_funcs.in

Re: [Intel-gfx] [PATCH 12/21] drm/i915: constify fdi link training vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> Avoid having writeable function pointers.
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_fdi.c | 18 +++---
>  drivers/gpu/drm/i915/i915_drv.h  |  2 +-
>  3 files changed, 17 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 87950202f4ce..0ad577aceb9d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2100,7 +2100,7 @@ static void ilk_pch_enable(const struct 
> intel_atomic_state *state,
>   assert_pch_transcoder_disabled(dev_priv, pipe);
>  
>   /* For PCH output, training FDI link */
> - dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
> + dev_priv->fdi_funcs->fdi_link_train(crtc, crtc_state);
>  
>   /* We need to program the right clock selection before writing the pixel
>* mutliplier into the DPLL. */
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c 
> b/drivers/gpu/drm/i915/display/intel_fdi.c
> index d9f952e0c67f..68aa9c7b18ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -1005,15 +1005,27 @@ void lpt_fdi_program_mphy(struct drm_i915_private 
> *dev_priv)
>   intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
>  }
>  
> +static const struct drm_i915_fdi_link_train_funcs ilk_funcs = {
> + .fdi_link_train = ilk_fdi_link_train

Oh, I guess we could add , at the end of all of these, across all
patches, even if some of them currently hold only one member. It's just
so much cleaner if ever you need to add another member.

BR,
Jani.


> +};
> +
> +static const struct drm_i915_fdi_link_train_funcs gen6_funcs = {
> + .fdi_link_train = gen6_fdi_link_train
> +};
> +
> +static const struct drm_i915_fdi_link_train_funcs ivb_funcs = {
> + .fdi_link_train = ivb_manual_fdi_link_train
> +};
> +
>  void
>  intel_fdi_init_hook(struct drm_i915_private *dev_priv)
>  {
>   if (IS_IRONLAKE(dev_priv)) {
> - dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
> + dev_priv->fdi_funcs = &ilk_funcs;
>   } else if (IS_SANDYBRIDGE(dev_priv)) {
> - dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
> + dev_priv->fdi_funcs = &gen6_funcs;
>   } else if (IS_IVYBRIDGE(dev_priv)) {
>   /* FIXME: detect B0+ stepping and use auto training */
> - dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
> + dev_priv->fdi_funcs = &ivb_funcs;
>   }
>  }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 461ab0a0f088..b3765222e717 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1006,7 +1006,7 @@ struct drm_i915_private {
>   struct drm_i915_irq_funcs irq_funcs;
>  
>   /* fdi display functions */
> - struct drm_i915_fdi_link_train_funcs fdi_funcs;
> + const struct drm_i915_fdi_link_train_funcs *fdi_funcs;
>  
>   /* display pll funcs */
>   struct drm_i915_dpll_funcs dpll_funcs;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] ✗ Fi.CI.DOCS: warning for i915/display: split and constify vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Patchwork  wrote:
> == Series Details ==
>
> Series: i915/display: split and constify vtable
> URL   : https://patchwork.freedesktop.org/series/94459/
> State : warning
>
> == Summary ==
>
> $ make htmldocs 2>&1 > /dev/null | grep i915
> ./drivers/gpu/drm/i915/display/intel_display.c:164: warning: Excess function 
> parameter 'crtc' description in 'intel_update_watermarks'

Seems legit, please update the kernel-doc.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for DSI driver improvement (rev4)

[Patchwork]

== Series Details ==

Series: DSI driver improvement (rev4)
URL   : https://patchwork.freedesktop.org/series/94237/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 
16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative 
(-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative 
(-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - 
different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' 
- different lock contexts fo

Re: [Intel-gfx] [PATCH 21/21] drm/i915: constify display wm vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> From: Dave Airlie 
>
> This adds some extra checks for the table pointer being
> valid due to some paths not setting it due to failing
> CxSR.

Can we just add a

static const struct drm_i915_wm_disp_funcs nop_wm_funcs = {
};

and point dev_priv->wm_disp at that so we can avoid the double checks?


Other than that,

Reviewed-by: Jani Nikula 


> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 56 ---
>  drivers/gpu/drm/i915/i915_drv.h  |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c  | 74 ++--
>  3 files changed, 81 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 20fd35c6858c..a3d6ab0795a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -161,8 +161,8 @@ static void intel_modeset_setup_hw_state(struct 
> drm_device *dev,
>   */
>  static void intel_update_watermarks(struct drm_i915_private *dev_priv)
>  {
> - if (dev_priv->wm_disp.update_wm)
> - dev_priv->wm_disp.update_wm(dev_priv);
> + if (dev_priv->wm_disp && dev_priv->wm_disp->update_wm)
> + dev_priv->wm_disp->update_wm(dev_priv);
>  }
>  
>  /* returns HPLL frequency in kHz */
> @@ -2566,8 +2566,8 @@ static void intel_pre_plane_update(struct 
> intel_atomic_state *state,
>* we'll continue to update watermarks the old way, if flags 
> tell
>* us to.
>*/
> - if (dev_priv->wm_disp.initial_watermarks)
> - dev_priv->wm_disp.initial_watermarks(state, crtc);
> + if (dev_priv->wm_disp->initial_watermarks)
> + dev_priv->wm_disp->initial_watermarks(state, crtc);
>   else if (new_crtc_state->update_wm_pre)
>   intel_update_watermarks(dev_priv);
>   }
> @@ -2941,8 +2941,8 @@ static void ilk_crtc_enable(struct intel_atomic_state 
> *state,
>   /* update DSPCNTR to configure gamma for pipe bottom color */
>   intel_disable_primary_plane(new_crtc_state);
>  
> - if (dev_priv->wm_disp.initial_watermarks)
> - dev_priv->wm_disp.initial_watermarks(state, crtc);
> + if (dev_priv->wm_disp->initial_watermarks)
> + dev_priv->wm_disp->initial_watermarks(state, crtc);
>   intel_enable_pipe(new_crtc_state);
>  
>   if (new_crtc_state->has_pch_encoder)
> @@ -3152,8 +3152,8 @@ static void hsw_crtc_enable(struct intel_atomic_state 
> *state,
>   if (DISPLAY_VER(dev_priv) >= 11)
>   icl_set_pipe_chicken(new_crtc_state);
>  
> - if (dev_priv->wm_disp.initial_watermarks)
> - dev_priv->wm_disp.initial_watermarks(state, crtc);
> + if (dev_priv->wm_disp && dev_priv->wm_disp->initial_watermarks)
> + dev_priv->wm_disp->initial_watermarks(state, crtc);
>  
>   if (DISPLAY_VER(dev_priv) >= 11) {
>   const struct intel_dbuf_state *dbuf_state =
> @@ -3570,7 +3570,7 @@ static void valleyview_crtc_enable(struct 
> intel_atomic_state *state,
>   /* update DSPCNTR to configure gamma for pipe bottom color */
>   intel_disable_primary_plane(new_crtc_state);
>  
> - dev_priv->wm_disp.initial_watermarks(state, crtc);
> + dev_priv->wm_disp->initial_watermarks(state, crtc);
>   intel_enable_pipe(new_crtc_state);
>  
>   intel_crtc_vblank_on(new_crtc_state);
> @@ -3613,8 +3613,8 @@ static void i9xx_crtc_enable(struct intel_atomic_state 
> *state,
>   /* update DSPCNTR to configure gamma for pipe bottom color */
>   intel_disable_primary_plane(new_crtc_state);
>  
> - if (dev_priv->wm_disp.initial_watermarks)
> - dev_priv->wm_disp.initial_watermarks(state, crtc);
> + if (dev_priv->wm_disp && dev_priv->wm_disp->initial_watermarks)
> + dev_priv->wm_disp->initial_watermarks(state, crtc);
>   else
>   intel_update_watermarks(dev_priv);
>   intel_enable_pipe(new_crtc_state);
> @@ -3682,7 +3682,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state 
> *state,
>   if (DISPLAY_VER(dev_priv) != 2)
>   intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>  
> - if (!dev_priv->wm_disp.initial_watermarks)
> + if (dev_priv->wm_disp && !dev_priv->wm_disp->initial_watermarks)
>   intel_update_watermarks(dev_priv);
>  
>   /* clock the pipe down to 640x480@60 to potentially save power */
> @@ -6790,8 +6790,8 @@ static int intel_crtc_atomic_check(struct 
> intel_atomic_state *state,
>   return ret;
>   }
>  
> - if (dev_priv->wm_disp.compute_pipe_wm) {
> - ret = dev_priv->wm_disp.compute_pipe_wm(state, crtc);
> + if (dev_priv->wm_disp && dev_priv->wm_disp->compute_pipe_wm) {
> + ret = dev_priv->wm_disp->compute_pipe_wm(state, crtc);
>   if (ret) {
>   

Re: [Intel-gfx] [PATCH 00/21] i915/display: split and constify vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie  wrote:
> This is orthogonal to my display ptr refactoring and should probably
> be applied first.

Yeah, overall nice cleanups, and a much easier bandwagon to jump onto
than the other one. ;)

Nothing too bad, a few bugs had crept in, and I had some nitpicks.

> The display funcs vtable was a bit of mess, lots of intermixing of
> internal display functionality and interfaces to watermarks/irqs.
>
> It's also considered not great security practice to leave writeable
> function pointers around for exploits to get into.

On the one hand I get this, but on the other hand the pointers to the
structs do remain writable. I suppose it increases the complexity of an
exploit by some margin?

In any case, I think this is cleaner in general, and that's enough merit
for the change, regardless of the security aspect.

BR,
Jani.

>
> This series attempts to address both problems, first there are a
> few cleanups, then it splits the function table into multiple pieces.
> Some of the splits might be bikesheds but I think we should apply first
> and merge things later if there is good reason.
>
> The second half converts all the vtables to static const structs,
> I've used macros in some of them to make it less messy, the cdclk
> one is probably the worst one.
>
> Dave.
>
>

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [v4 0/5] DSI driver improvement

[Jani Nikula]

On Wed, 08 Sep 2021, Lee Shawn C  wrote:
> v2: Get data length of brightness value more easily while driver try to
> read/write MIPI_DCS_DISPLAY_BRIGHTNESS command.
> v3: fix checkpatch warning.

The series is v4, what's new here?

BR,
Jani.


>
> Signed-off-by: Lee Shawn C 
>
> Lee Shawn C (5):
>   drm/i915/dsi: wait for header and payload credit available
>   drm/i915/dsi: refine send MIPI DCS command sequence
>   drm/i915: Get proper min cdclk if vDSC enabled
>   drm/i915/dsi: Retrieve max brightness level from VBT
>   drm/i915/dsi: Read/write proper brightness value via MIPI DCS command
>
>  drivers/gpu/drm/i915/display/icl_dsi.c| 50 +--
>  drivers/gpu/drm/i915/display/intel_bios.c |  3 ++
>  drivers/gpu/drm/i915/display/intel_cdclk.c| 10 
>  .../i915/display/intel_dsi_dcs_backlight.c| 33 
>  drivers/gpu/drm/i915/i915_drv.h   |  1 +
>  5 files changed, 62 insertions(+), 35 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 5/6] drm/i915: Don't back up pinned LMEM context images and rings during suspend

[Thomas Hellström]

On Wed, 2021-09-08 at 12:07 +0100, Matthew Auld wrote:
> On 06/09/2021 17:55, Thomas Hellström wrote:
> > Pinned context images are now reset during resume. Don't back them
> > up,
> > and assuming that rings can be assumed empty at suspend, don't back
> > them
> > up either.
> > 
> > Introduce a new object flag, I915_BO_ALLOC_PM_VOLATILE meaning that
> > an
> > object is allowed to lose its content on suspend.
> > 
> > Signed-off-by: Thomas Hellström 
> > ---
> >   .../gpu/drm/i915/gem/i915_gem_object_types.h    | 17 ++--
> > -
> >   drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c  |  3 +++
> >   drivers/gpu/drm/i915/gt/intel_lrc.c |  3 ++-
> >   drivers/gpu/drm/i915/gt/intel_ring.c    |  3 ++-
> >   4 files changed, 17 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > index 734cc8e16481..66123ba46247 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > @@ -288,16 +288,19 @@ struct drm_i915_gem_object {
> > I915_SELFTEST_DECLARE(struct list_head st_link);
> >   
> > unsigned long flags;
> > -#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
> > -#define I915_BO_ALLOC_VOLATILE   BIT(1)
> > -#define I915_BO_ALLOC_CPU_CLEAR  BIT(2)
> > -#define I915_BO_ALLOC_USER   BIT(3)
> > +#define I915_BO_ALLOC_CONTIGUOUS  BIT(0)
> > +#define I915_BO_ALLOC_VOLATILE    BIT(1)
> > +#define I915_BO_ALLOC_CPU_CLEAR   BIT(2)
> > +#define I915_BO_ALLOC_USER    BIT(3)
> > +/* Object may lose its contents on suspend / resume */
> > +#define I915_BO_ALLOC_PM_VOLATILE BIT(4)

> 
> PM_SKIP_PINNED? Not sure if that is better.

I think we could update the comment to say "object is allowed to
lose..", I think we could keep PM_VOLATILE to keep it consistent with
the ALLOC_VOLATILE flag?

/Thomas

[Intel-gfx] ✓ Fi.CI.BAT: success for DSI driver improvement (rev4)

[Patchwork]

== Series Details ==

Series: DSI driver improvement (rev4)
URL   : https://patchwork.freedesktop.org/series/94237/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10562 -> Patchwork_20990


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/index.html

Known issues


  Here are the changes found in Patchwork_20990 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html

  * igt@gem_exec_parallel@engines@userptr:
- fi-pnv-d510:[PASS][2] -> [INCOMPLETE][3] ([i915#299])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/fi-pnv-d510/igt@gem_exec_parallel@engi...@userptr.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/fi-pnv-d510/igt@gem_exec_parallel@engi...@userptr.html

  * igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][4] ([i915#2403] / [i915#2722])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/fi-pnv-d510/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][5] ([i915#3921]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#299]: https://gitlab.freedesktop.org/drm/intel/issues/299
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921


Participating hosts (47 -> 39)
--

  Missing(8): fi-ilk-m540 bat-adls-5 bat-dg1-6 fi-bsw-cyan bat-adlp-4 
fi-ctg-p8600 fi-bdw-samus bat-jsl-1 


Build changes
-

  * Linux: CI_DRM_10562 -> Patchwork_20990

  CI-20190529: 20190529
  CI_DRM_10562: d38c3e456e48f3cc74f454615dedc5a82e258402 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6200: 3a6585c472dff11ece952b745244f05e4c93ede5 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20990: e049ecea53d30e72d4efb961d686b654d882e1f6 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

e049ecea53d3 drm/i915/dsi: Read/write proper brightness value via MIPI DCS 
command
5549253e7763 drm/i915/dsi: Retrieve max brightness level from VBT
969335cb39c2 drm/i915: Get proper min cdclk if vDSC enabled
1651e0786737 drm/i915/dsi: refine send MIPI DCS command sequence
22f879c05f7f drm/i915/dsi: wait for header and payload credit available

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/index.html

Re: [Intel-gfx] [v4 0/5] DSI driver improvement

[Lee, Shawn C]

On Wed, 08 Sep 2021, Jani Nikula  wrote:
>On Wed, 08 Sep 2021, Lee Shawn C  wrote:
>> v2: Get data length of brightness value more easily while driver try to
>> read/write MIPI_DCS_DISPLAY_BRIGHTNESS command.
>> v3: fix checkpatch warning.
>
>The series is v4, what's new here?
>
>BR,
>Jani.
>

We don't change anything, just rebase.

Best regards,
Shawn

>
>>
>> Signed-off-by: Lee Shawn C 
>>
>> Lee Shawn C (5):
>>   drm/i915/dsi: wait for header and payload credit available
>>   drm/i915/dsi: refine send MIPI DCS command sequence
>>   drm/i915: Get proper min cdclk if vDSC enabled
>>   drm/i915/dsi: Retrieve max brightness level from VBT
>>   drm/i915/dsi: Read/write proper brightness value via MIPI DCS command
>>
>>  drivers/gpu/drm/i915/display/icl_dsi.c| 50 +--
>>  drivers/gpu/drm/i915/display/intel_bios.c |  3 ++
>>  drivers/gpu/drm/i915/display/intel_cdclk.c| 10 
>>  .../i915/display/intel_dsi_dcs_backlight.c| 33 
>>  drivers/gpu/drm/i915/i915_drv.h   |  1 +
>>  5 files changed, 62 insertions(+), 35 deletions(-)
>
>-- 
>Jani Nikula, Intel Open Source Graphics Center
>

Re: [Intel-gfx] [PATCH v2 5/6] drm/i915: Don't back up pinned LMEM context images and rings during suspend

[Matthew Auld]

On 08/09/2021 13:26, Thomas Hellström wrote:

On Wed, 2021-09-08 at 12:07 +0100, Matthew Auld wrote:

On 06/09/2021 17:55, Thomas Hellström wrote:

Pinned context images are now reset during resume. Don't back them
up,
and assuming that rings can be assumed empty at suspend, don't back
them
up either.

Introduce a new object flag, I915_BO_ALLOC_PM_VOLATILE meaning that
an
object is allowed to lose its content on suspend.

Signed-off-by: Thomas Hellström 
---
   .../gpu/drm/i915/gem/i915_gem_object_types.h    | 17 ++--
-
   drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c  |  3 +++
   drivers/gpu/drm/i915/gt/intel_lrc.c |  3 ++-
   drivers/gpu/drm/i915/gt/intel_ring.c    |  3 ++-
   4 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 734cc8e16481..66123ba46247 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -288,16 +288,19 @@ struct drm_i915_gem_object {
 I915_SELFTEST_DECLARE(struct list_head st_link);
   
 unsigned long flags;

-#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
-#define I915_BO_ALLOC_VOLATILE   BIT(1)
-#define I915_BO_ALLOC_CPU_CLEAR  BIT(2)
-#define I915_BO_ALLOC_USER   BIT(3)
+#define I915_BO_ALLOC_CONTIGUOUS  BIT(0)
+#define I915_BO_ALLOC_VOLATILE    BIT(1)
+#define I915_BO_ALLOC_CPU_CLEAR   BIT(2)
+#define I915_BO_ALLOC_USER    BIT(3)
+/* Object may lose its contents on suspend / resume */
+#define I915_BO_ALLOC_PM_VOLATILE BIT(4)




PM_SKIP_PINNED? Not sure if that is better.


I think we could update the comment to say "object is allowed to
lose..", I think we could keep PM_VOLATILE to keep it consistent with
the ALLOC_VOLATILE flag?


I guess that's the potentially confusing bit. ALLLOC_VOLATILE means the 
pages might be discarded as soon as the pages become unpinned, without 
needing to worry about persisting their contents. With PM_VOLATILE I was 
expecting something similar where unpinned objects can simply be skipped 
or ignored during pm. Anyway, that's just a bikeshed, I think with 
improved comment this should be fine.




/Thomas

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for DSI driver improvement (rev3)

[Lee, Shawn C]

These errors did not relate to this patch series. Thanks!

Best regards,
Shawn

From: Patchwork 
Sent: Friday, September 3, 2021 3:21 AM
To: Lee, Shawn C 
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for DSI driver improvement (rev3)

Patch Details
Series:
DSI driver improvement (rev3)
URL:
https://patchwork.freedesktop.org/series/94237/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20943/index.html
CI Bug Log - changes from CI_DRM_10548_full -> Patchwork_20943_full
Summary

FAILURE

Serious unknown changes coming with Patchwork_20943_full absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20943_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_20943_full:

IGT changes
Possible regressions

  *   igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
 *   shard-iclb: 
PASS
 -> 
INCOMPLETE
 +1 similar issue

Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  *   igt@gem_eio@hibernate:
 *   {shard-rkl}: NOTRUN -> 
FAIL

Known issues

Here are the changes found in Patchwork_20943_full that come from known issues:

IGT changes
Issues hit

  *   igt@gem_create@create-massive:
 *   shard-apl: NOTRUN -> 
DMESG-WARN
 ([i915#3002])
  *   igt@gem_ctx_persistence@engines-hostile-preempt:
 *   shard-snb: NOTRUN -> 
SKIP
 ([fdo#109271] / [i915#1099]) +4 similar issues
  *   igt@gem_ctx_persistence@many-contexts:
 *   shard-tglb: 
PASS
 -> 
FAIL
 ([i915#2410])
  *   igt@gem_exec_fair@basic-deadline:
 *   shard-apl: NOTRUN -> 
FAIL
 ([i915#2846])
  *   igt@gem_exec_fair@basic-flow@rcs0:
 *   shard-tglb: 
PASS
 -> 
FAIL
 ([i915#2842]) +1 similar issue
  *   igt@gem_exec_fair@basic-none@vecs0:
 *   shard-kbl: 
PASS
 -> 
FAIL
 ([i915#2842])
  *   igt@gem_exec_fair@basic-pace-share@rcs0:
 *   shard-glk: 
PASS
 -> 
FAIL
 ([i915#2842])
  *   igt@gem_exec_fair@basic-throttle@rcs0:
 *   shard-iclb: 
PASS
 -> 
FAIL
 ([i915#2849])
  *   igt@gem_mmap_gtt@cpuset-basic-small-copy-odd:
 *   shard-iclb: 
PASS
 -> 
FAIL
 ([i915#307])
  *   igt@gem_pread@exhaustion:
 *   shard-skl: NOTRUN -> 
WARN
 ([i915#2658])
  *   igt@gem_pwrite@basic-exhaustion:
 *   shard-snb: NOTRUN -> 
WARN
 ([i915#2658]) +1 similar issue
  *   igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
 *   shard-iclb: NOTRUN -> 
SKIP
 ([i915#768])
 

Re: [Intel-gfx] [PATCH 4/8] drm/i915/xehp: CCS should use RCS setup functions

[Tvrtko Ursulin]

On 08/09/2021 11:13, Tvrtko Ursulin wrote:


On 07/09/2021 18:19, Matt Roper wrote:

The compute engine handles the same commands the render engine can
(except 3D pipeline), so it makes sense that CCS is more similar to RCS
than non-render engines.

The CCS context state (lrc) is also similar to the render one, so reuse
it. Note that the compute engine has its own CTX_R_PWR_CLK_STATE
register.

In order to avoid having multiple RCS && CCS checks, add the following
engine flag:
  - I915_ENGINE_HAS_RCS_REG_STATE - use the render (larger) reg state 
ctx.


BSpec: 46260
Original-patch-by: Michel Thierry
Cc: Tvrtko Ursulin 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Matt Roper 
---
  drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 8 +---
  drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 ++
  drivers/gpu/drm/i915/gt/intel_engine_types.h  | 1 +
  drivers/gpu/drm/i915/gt/intel_execlists_submission.c  | 2 +-
  drivers/gpu/drm/i915/gt/intel_lrc.c   | 4 ++--
  drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
  drivers/gpu/drm/i915/i915_perf.c  | 4 ++--
  drivers/gpu/drm/i915/i915_reg.h   | 2 +-
  8 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c

index b32f7fed2d9c..fbe10783628b 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -883,7 +883,9 @@ static int igt_shared_ctx_exec(void *arg)
  return err;
  }
-static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct 
i915_vma *vma)

+static int rpcs_query_batch(struct drm_i915_gem_object *rpcs,
+    struct i915_vma *vma,
+    struct intel_engine_cs *engine)
  {
  u32 *cmd;
@@ -894,7 +896,7 @@ static int rpcs_query_batch(struct 
drm_i915_gem_object *rpcs, struct i915_vma *v

  return PTR_ERR(cmd);
  *cmd++ = MI_STORE_REGISTER_MEM_GEN8;
-    *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
+    *cmd++ = 
i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(engine->mmio_base));

  *cmd++ = lower_32_bits(vma->node.start);
  *cmd++ = upper_32_bits(vma->node.start);
  *cmd = MI_BATCH_BUFFER_END;
@@ -955,7 +957,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
  if (err)
  goto err_vma;
-    err = rpcs_query_batch(rpcs, vma);
+    err = rpcs_query_batch(rpcs, vma, ce->engine);
  if (err)
  goto err_batch;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c

index 69944bd8c19d..b346b946602d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -205,6 +205,8 @@ u32 intel_engine_context_size(struct intel_gt *gt, 
u8 class)

  BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
  switch (class) {
+    case COMPUTE_CLASS:
+    fallthrough;
  case RENDER_CLASS:
  switch (GRAPHICS_VER(gt->i915)) {
  default:
@@ -379,6 +381,10 @@ static int intel_engine_setup(struct intel_gt 
*gt, enum intel_engine_id id)

  if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
  engine->props.preempt_timeout_ms = 0;
+    /* features common between engines sharing EUs */
+    if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS)
+    engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
+
  engine->defaults = engine->props; /* never to change again */
  engine->context_size = intel_engine_context_size(gt, 
engine->class);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h 
b/drivers/gpu/drm/i915/gt/intel_engine_types.h

index dcb9d8b2362a..30a0c69c36c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -454,6 +454,7 @@ struct intel_engine_cs {
  #define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
  #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
  #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
+#define I915_ENGINE_HAS_RCS_REG_STATE  BIT(9)
  unsigned int flags;
  /*
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c

index de5f9c86b9a4..4c600c46414d 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3406,7 +3406,7 @@ int intel_execlists_submission_setup(struct 
intel_engine_cs *engine)

  logical_ring_default_vfuncs(engine);
  logical_ring_default_irqs(engine);
-    if (engine->class == RENDER_CLASS)
+    if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
  rcs_submission_override(engine);


Hm, what do pipe control flushes which relate to 3d pipeline end up 
doing on CCS engines?


Right, answer found in the following patch.

Ideally the two would swap places in the series so by 

Re: [Intel-gfx] [PATCH 6/8] drm/i915/xehp: Define context scheduling attributes in lrc descriptor

[Tvrtko Ursulin]

On 07/09/2021 18:19, Matt Roper wrote:

In Dual Context mode the EUs are shared between render and compute
command streamers. The hardware provides a field in the lrc descriptor
to indicate the prioritization of the thread dispatch associated to the
corresponding context.

The context priority is set to 'low' at creation time and relies on the
existing context priority to set it to low/normal/high.

HSDES: 1604462009
Bspec: 46145, 46260
Original-patch-by: Michel Thierry
Cc: Tvrtko Ursulin 
Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Prasad Nallani 
Signed-off-by: Matt Roper 
---
  drivers/gpu/drm/i915/gt/intel_engine_cs.c|  4 +++-
  drivers/gpu/drm/i915/gt/intel_engine_types.h |  1 +
  drivers/gpu/drm/i915/gt/intel_execlists_submission.c |  6 +-
  drivers/gpu/drm/i915/gt/intel_lrc.h  | 10 ++
  drivers/gpu/drm/i915/i915_reg.h  |  4 
  5 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index b346b946602d..2f719f0ecac3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -382,8 +382,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum 
intel_engine_id id)
engine->props.preempt_timeout_ms = 0;
  
  	/* features common between engines sharing EUs */

-   if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS)
+   if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
+   engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
+   }
  
  	engine->defaults = engine->props; /* never to change again */
  
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h

index 30a0c69c36c8..00bf0296b28a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -455,6 +455,7 @@ struct intel_engine_cs {
  #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
  #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
  #define I915_ENGINE_HAS_RCS_REG_STATE  BIT(9)
+#define I915_ENGINE_HAS_EU_PRIORITYBIT(10)
unsigned int flags;
  
  	/*

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 4c600c46414d..2b36ec7f3a04 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -662,9 +662,13 @@ static inline void execlists_schedule_out(struct 
i915_request *rq)
  static u64 execlists_update_context(struct i915_request *rq)
  {
struct intel_context *ce = rq->context;
-   u64 desc = ce->lrc.desc;
+   u64 desc;
u32 tail, prev;
  
+	desc = ce->lrc.desc;

+   if (rq->engine->flags & I915_ENGINE_HAS_EU_PRIORITY)
+   desc |= lrc_desc_priority(rq_prio(rq));
+
/*
 * WaIdleLiteRestore:bdw,skl
 *
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h 
b/drivers/gpu/drm/i915/gt/intel_lrc.h
index 7f697845c4cf..d3f2096b3d51 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -79,4 +79,14 @@ static inline u32 lrc_get_runtime(const struct intel_context 
*ce)
return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
  }
  
+static inline u32 lrc_desc_priority(int prio)

+{
+   if (prio > I915_PRIORITY_NORMAL)
+   return GEN12_CTX_PRIORITY_HIGH;
+   else if (prio < I915_PRIORITY_NORMAL)
+   return GEN12_CTX_PRIORITY_LOW;
+   else
+   return GEN12_CTX_PRIORITY_NORMAL;
+}
+
  #endif /* __INTEL_LRC_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bb185ce9529..5b68c02c35af 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4212,6 +4212,10 @@ enum {
  #define GEN8_CTX_L3LLC_COHERENT (1 << 5)
  #define GEN8_CTX_PRIVILEGE (1 << 8)
  #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
+#define GEN12_CTX_PRIORITY_MASK REG_GENMASK(10, 9)
+#define GEN12_CTX_PRIORITY_HIGH REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 2)
+#define GEN12_CTX_PRIORITY_NORMAL REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 1)
+#define GEN12_CTX_PRIORITY_LOW REG_FIELD_PREP(GEN12_CTX_PRIORITY_MASK, 0)
  
  #define GEN8_CTX_ID_SHIFT 32

  #define GEN8_CTX_ID_WIDTH 21



Haven't checked bspec to check the bitfield but the mechanics look good.

Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko

Re: [Intel-gfx] [PATCH 7/8] drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE

[Tvrtko Ursulin]

On 07/09/2021 18:19, Matt Roper wrote:

We have to specify in the Render Control Unit Mode register
when CCS is enabled.

Bspec: 46034
Original-patch-by: Michel Thierry
Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Vinay Belgaumkar 
Signed-off-by: Daniele Ceraolo Spurio 
Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Matt Roper 
---
  .../drm/i915/gt/intel_execlists_submission.c  | 26 +++
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 26 +++
  drivers/gpu/drm/i915/i915_reg.h   |  3 +++
  3 files changed, 55 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 2b36ec7f3a04..046f7da67ba6 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2874,6 +2874,29 @@ static int execlists_resume(struct intel_engine_cs 
*engine)
return 0;
  }
  
+static int gen12_rcs_resume(struct intel_engine_cs *engine)

+{
+   int ret;
+
+   ret = execlists_resume(engine);
+   if (ret)
+   return ret;
+
+   /*
+* Multi Context programming.
+* just need to program this register once no matter how many CCS


Just


+* engines there are. Since some of the CCS engines might be fused off,
+* we can't do this as part of the init of a specific CCS and we do
+* it during RCS init instead. RCS and all CCS engines are reset


I don't really understand the "can't" part - clearly it would be doable 
if a specific vfunc was assigned to one ccs only, the one which is 
present of course. Not saying that would be nicer since I think it has 
it's own downside.


Perhaps nicest solution is to add an engine flag saying "enables rcu" 
and then execlists and guc resume check that and do stuff?


No strong opinion yet, just discussing.


+* together, so post-reset re-init is covered as well.
+*/
+   if (CCS_MASK(engine->gt))
+   intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
+  _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
+
+   return 0;
+}
+
  static void execlists_reset_prepare(struct intel_engine_cs *engine)
  {
ENGINE_TRACE(engine, "depth<-%d\n",
@@ -3394,6 +3417,9 @@ static void rcs_submission_override(struct 
intel_engine_cs *engine)
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
break;
}
+
+   if (engine->class == RENDER_CLASS)
+   engine->resume = gen12_rcs_resume;
  }
  
  int intel_execlists_submission_setup(struct intel_engine_cs *engine)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 2f5bf7aa7e3b..db956255d076 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2350,6 +2350,29 @@ static bool guc_sched_engine_disabled(struct 
i915_sched_engine *sched_engine)
return !sched_engine->tasklet.callback;
  }
  
+static int gen12_rcs_resume(struct intel_engine_cs *engine)

+{
+   int ret;
+
+   ret = guc_resume(engine);
+   if (ret)
+   return ret;
+
+   /*
+* Multi Context programming.
+* just need to program this register once no matter how many CCS
+* engines there are. Since some of the CCS engines might be fused off,
+* we can't do this as part of the init of a specific CCS and we do
+* it during RCS init instead. RCS and all CCS engines are reset
+* together, so post-reset re-init is covered as well.
+*/
+   if (CCS_MASK(engine->gt))
+   intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
+  _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));


Duplicating the write from gen12_rcs_resume looks passable but when with 
the whole comment then hmm.. How about a helper is added which both 
would call? Like intel_engine_enable_rcu_mode() or something?


Regards,

Tvrtko


+
+   return 0;
+}
+
  static void guc_set_default_submission(struct intel_engine_cs *engine)
  {
engine->submit_request = guc_submit_request;
@@ -2464,6 +2487,9 @@ static void rcs_submission_override(struct 
intel_engine_cs *engine)
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
break;
}
+
+   if (engine->class == RENDER_CLASS)
+   engine->resume = gen12_rcs_resume;
  }
  
  static inline void guc_default_irqs(struct intel_engine_cs *engine)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5b68c02c35af..57f9456f8c61 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -498,6 +498,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
  #define   ECOBITS_PPGTT_CACHE64B  (3 << 8)
  #define   ECOBITS_PPGTT_CACHE4B  

Re: [Intel-gfx] [PATCH] drm/i915: deduplicate frequency dump on debugfs

[Lucas De Marchi]

On Wed, Sep 08, 2021 at 11:54:40AM +0300, Jani Nikula wrote:

On Tue, 07 Sep 2021, Lucas De Marchi  wrote:

Although commit 9dd4b065446a ("drm/i915/gt: Move pm debug files into a
gt aware debugfs") says it was moving debug files to gt/, the
i915_frequency_info file was left behind and its implementation copied
into drivers/gpu/drm/i915/gt/debugfs_gt_pm.c. Over time we had several
patches having to change both places to keep them in sync (and some
patches failing to do so). The initial idea was to remove i915_frequency_info,
but there are user space tools using it. From a quick code search there
are other scripts and test tools besides igt, so it's not simply
updating igt to get rid of the older file.

Here we export a function using drm_printer as parameter and make
both show() implementations to call this same function. Aside from a few
variable name differences, for i915_frequency_info this brings a few
lines that were not previously printed: RP UP EI, RP UP THRESHOLD, RP
DOWN THRESHOLD and RP DOWN EI.  These came in as part of
commit 9c878557b1eb ("drm/i915/gt: Use the RPM config register to
determine clk frequencies"), which didn't change both places.

Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 127 ++---
 drivers/gpu/drm/i915/gt/debugfs_gt_pm.h |   2 +
 drivers/gpu/drm/i915/i915_debugfs.c | 227 +---
 3 files changed, 74 insertions(+), 282 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c 
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index f6733f279890..6a27c011d0ff 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -240,9 +240,8 @@ static int drpc_show(struct seq_file *m, void *unused)
 }
 DEFINE_GT_DEBUGFS_ATTRIBUTE(drpc);

-static int frequency_show(struct seq_file *m, void *unused)
+void debugfs_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)


The debugfs prefix belongs to debugfs, and I don't think we should have
non-static functions with that prefix.

I know it's in line with what's currently in the file, and I've
complained about it before, but apparently that hasn't been enough.


I was surprised by the prefix too.

intel_gt_pm_debugfs.[hc] - would that be better or do you have another
suggestion?

thanks
Lucas De Marchi

Re: [Intel-gfx] [v4 0/5] DSI driver improvement

[Kulkarni, Vandita]

> -Original Message-
> From: Lee, Shawn C 
> Sent: Wednesday, September 8, 2021 6:42 PM
> To: Nikula, Jani ; intel-gfx@lists.freedesktop.org
> Cc: ville.syrj...@linux.intel.com; Kulkarni, Vandita
> ; Chiou, Cooper ;
> Tseng, William 
> Subject: RE: [v4 0/5] DSI driver improvement
> 
> On Wed, 08 Sep 2021, Jani Nikula  wrote:
> >On Wed, 08 Sep 2021, Lee Shawn C  wrote:
> >> v2: Get data length of brightness value more easily while driver try to
> >> read/write MIPI_DCS_DISPLAY_BRIGHTNESS command.
> >> v3: fix checkpatch warning.
> >
> >The series is v4, what's new here?
> >
> >BR,
> >Jani.
> >
> 
> We don't change anything, just rebase.
> 
> Best regards,
> Shawn

Thanks for the patches and reviews.
Pushed v4 based on results on v3 as there is no change.

Thanks,
Vandita
> 
> >
> >>
> >> Signed-off-by: Lee Shawn C 
> >>
> >> Lee Shawn C (5):
> >>   drm/i915/dsi: wait for header and payload credit available
> >>   drm/i915/dsi: refine send MIPI DCS command sequence
> >>   drm/i915: Get proper min cdclk if vDSC enabled
> >>   drm/i915/dsi: Retrieve max brightness level from VBT
> >>   drm/i915/dsi: Read/write proper brightness value via MIPI DCS command
> >>
> >>  drivers/gpu/drm/i915/display/icl_dsi.c| 50 +--
> >>  drivers/gpu/drm/i915/display/intel_bios.c |  3 ++
> >>  drivers/gpu/drm/i915/display/intel_cdclk.c| 10 
> >>  .../i915/display/intel_dsi_dcs_backlight.c| 33 
> >>  drivers/gpu/drm/i915/i915_drv.h   |  1 +
> >>  5 files changed, 62 insertions(+), 35 deletions(-)
> >
> >--
> >Jani Nikula, Intel Open Source Graphics Center
> >

Re: [Intel-gfx] [PATCH 8/8] drm/i915/xehp: Extend uninterruptible OpenCL workloads to CCS

[Tvrtko Ursulin]

On 07/09/2021 18:19, Matt Roper wrote:

From: John Harrison 

Now that OpenCL workloads can run on the compute engine, we need to set
preempt_timeout_ms = 0 on the CCS engines too.

Signed-off-by: John Harrison 
Signed-off-by: Matt Roper 
---
  drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +
  1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 2f719f0ecac3..7e6ac0ae1f07 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -377,16 +377,17 @@ static int intel_engine_setup(struct intel_gt *gt, enum 
intel_engine_id id)
engine->props.timeslice_duration_ms =
CONFIG_DRM_I915_TIMESLICE_DURATION;
  
-	/* Override to uninterruptible for OpenCL workloads. */

-   if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
-   engine->props.preempt_timeout_ms = 0;
-
/* features common between engines sharing EUs */
if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
}
  
+	/* Override to uninterruptible for OpenCL workloads. */

+   if (GRAPHICS_VER(i915) == 12 &&
+   engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
+   engine->props.preempt_timeout_ms = 0;
+
engine->defaults = engine->props; /* never to change again */
  
  	engine->context_size = intel_engine_context_size(gt, engine->class);




Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko

[Intel-gfx] ✗ Fi.CI.IGT: failure for Panel replay phase1 implementation

[Patchwork]

== Series Details ==

Series: Panel replay phase1 implementation
URL   : https://patchwork.freedesktop.org/series/94470/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10562_full -> Patchwork_20989_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_20989_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20989_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_20989_full:

### IGT changes ###

 Possible regressions 

  * igt@syncobj_timeline@multi-wait-for-submit-signaled:
- shard-skl:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-skl7/igt@syncobj_timel...@multi-wait-for-submit-signaled.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-skl2/igt@syncobj_timel...@multi-wait-for-submit-signaled.html

  
Known issues


  Here are the changes found in Patchwork_20989_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-massive:
- shard-snb:  NOTRUN -> [DMESG-WARN][3] ([i915#3002])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-snb2/igt@gem_cre...@create-massive.html
- shard-apl:  NOTRUN -> [DMESG-WARN][4] ([i915#3002])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl8/igt@gem_cre...@create-massive.html

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl:  [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +5 similar 
issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-kbl1/igt@gem_ctx_isolation@preservation...@bcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-kbl4/igt@gem_ctx_isolation@preservation...@bcs0.html

  * igt@gem_ctx_persistence@engines-queued:
- shard-snb:  NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +2 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-snb7/igt@gem_ctx_persiste...@engines-queued.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-tglb: NOTRUN -> [FAIL][8] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-none@rcs0:
- shard-glk:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-glk6/igt@gem_exec_fair@basic-n...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-glk6/igt@gem_exec_fair@basic-n...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl:  NOTRUN -> [FAIL][11] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-kbl6/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar 
issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-tglb5/igt@gem_exec_fair@basic-p...@bcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb7/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_mmap_gtt@cpuset-big-copy-xy:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2428])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-iclb1/igt@gem_mmap_...@cpuset-big-copy-xy.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-iclb2/igt@gem_mmap_...@cpuset-big-copy-xy.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-snb:  NOTRUN -> [WARN][16] ([i915#2658])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-snb2/igt@gem_pwr...@basic-exhaustion.html
- shard-apl:  NOTRUN -> [WARN][17] ([i915#2658])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-apl8/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_userptr_blits@coherency-sync:
- shard-tglb: NOTRUN -> [SKIP][18] ([fdo#110542])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb5/igt@gem_userptr_bl...@coherency-sync.html

  * igt@gem_userptr_blits@create-destroy-unsync:
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#3297]) +1 similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-tglb3/igt@gem_userptr_bl...@create-destroy-unsync.html

  * igt@gem_userptr_blits@vma-merge:
- shard-kbl:  NOTRUN -> [FAIL][20] ([i915#3318])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20989/shard-kbl6/igt@gem_userptr_bl...@vma-merge.html

  * igt@gem_workarounds@suspend-res

Re: [Intel-gfx] [PATCH] drm/i915/adl_s: Remove require_force_probe protection

[Joonas Lahtinen]

Quoting Siddiqui, Ayaz A (2021-09-07 08:43:52)
> 
> 
> > -Original Message-
> > From: Intel-gfx  On Behalf Of Talla
> > Raviteja Goud
> > Sent: Friday, September 3, 2021 11:51 PM
> > To: intel-gfx@lists.freedesktop.org; Surendrakumar Upadhyay, TejaskumarX
> > ; Meena, Mahesh
> > ; Pandey, Hariom 
> > Cc: Talla, RavitejaX Goud ; De Marchi, Lucas
> > 
> > Subject: [Intel-gfx] [PATCH] drm/i915/adl_s: Remove require_force_probe
> > protection
> > 
> > From: ravitejax 

Raviteja, please check your git settings and fill in full name there.

Ayaz, Thomas, when reviewing and merging patches, please pay attention
to the From: and Signed-off-by: tags to make sure they are correct.

Regards, Joonas

Re: [Intel-gfx] [PATCH] drm/i915: deduplicate frequency dump on debugfs

[Lucas De Marchi]

On Wed, Sep 08, 2021 at 07:14:00AM -0700, Lucas De Marchi wrote:

On Wed, Sep 08, 2021 at 11:54:40AM +0300, Jani Nikula wrote:

On Tue, 07 Sep 2021, Lucas De Marchi  wrote:

Although commit 9dd4b065446a ("drm/i915/gt: Move pm debug files into a
gt aware debugfs") says it was moving debug files to gt/, the
i915_frequency_info file was left behind and its implementation copied
into drivers/gpu/drm/i915/gt/debugfs_gt_pm.c. Over time we had several
patches having to change both places to keep them in sync (and some
patches failing to do so). The initial idea was to remove i915_frequency_info,
but there are user space tools using it. From a quick code search there
are other scripts and test tools besides igt, so it's not simply
updating igt to get rid of the older file.

Here we export a function using drm_printer as parameter and make
both show() implementations to call this same function. Aside from a few
variable name differences, for i915_frequency_info this brings a few
lines that were not previously printed: RP UP EI, RP UP THRESHOLD, RP
DOWN THRESHOLD and RP DOWN EI.  These came in as part of
commit 9c878557b1eb ("drm/i915/gt: Use the RPM config register to
determine clk frequencies"), which didn't change both places.

Signed-off-by: Lucas De Marchi 
---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 127 ++---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.h |   2 +
drivers/gpu/drm/i915/i915_debugfs.c | 227 +---
3 files changed, 74 insertions(+), 282 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c 
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index f6733f279890..6a27c011d0ff 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -240,9 +240,8 @@ static int drpc_show(struct seq_file *m, void *unused)
}
DEFINE_GT_DEBUGFS_ATTRIBUTE(drpc);

-static int frequency_show(struct seq_file *m, void *unused)
+void debugfs_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)


The debugfs prefix belongs to debugfs, and I don't think we should have
non-static functions with that prefix.

I know it's in line with what's currently in the file, and I've
complained about it before, but apparently that hasn't been enough.


I was surprised by the prefix too.

intel_gt_pm_debugfs.[hc] - would that be better or do you have another
suggestion?


Something like the below:

renamed:drivers/gpu/drm/i915/gt/debugfs_gt.c -> 
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
renamed:drivers/gpu/drm/i915/gt/debugfs_gt.h -> 
drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
renamed:drivers/gpu/drm/i915/gt/debugfs_engines.c -> 
drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.c
renamed:drivers/gpu/drm/i915/gt/debugfs_engines.h -> 
drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h
renamed:drivers/gpu/drm/i915/gt/debugfs_gt_pm.c -> 
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
renamed:drivers/gpu/drm/i915/gt/debugfs_gt_pm.h -> 
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h


and then rename the functions/macros in these files to follow th
filename

Lucas De Marchi



thanks
Lucas De Marchi

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Suspend / resume backup- and restore of LMEM. (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev3)
URL   : https://patchwork.freedesktop.org/series/94278/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
6374ded0c677 drm/i915/ttm: Implement a function to copy the contents of two 
TTM-base objects
9f81cf996425 drm/i915/gem: Implement a function to process all gem objects of a 
region
6b06e53cb3c8 drm/i915 Implement LMEM backup and restore for suspend / resume
-:291: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#291: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 498 lines checked
9fa23d69f7ed drm/i915/gt: Register the migrate contexts with their engines
e829df93558f drm/i915: Don't back up pinned LMEM context images and rings 
during suspend
b3a1b351a5bf drm/i915: Reduce the number of objects subject to memcpy recover

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Suspend / resume backup- and restore of LMEM. (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev3)
URL   : https://patchwork.freedesktop.org/series/94278/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10563 -> Patchwork_20991


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/index.html

Known issues


  Here are the changes found in Patchwork_20991 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u:   NOTRUN -> [SKIP][1] ([fdo#109271]) +23 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html

  * igt@amdgpu/amd_cs_nop@sync-compute0:
- fi-kbl-r:   NOTRUN -> [SKIP][2] ([fdo#109271]) +21 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-r/igt@amdgpu/amd_cs_...@sync-compute0.html

  * igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u:   NOTRUN -> [WARN][3] ([i915#3718])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4:  [PASS][4] -> [FAIL][5] ([i915#1888])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
- fi-kbl-r:   NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-r/igt@gem_huc_c...@huc-copy.html

  * igt@gem_tiled_blits@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271]) +3 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-soraka/igt@gem_tiled_bl...@basic.html

  * igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][9] -> [FAIL][10] ([i915#2203] / [i915#579])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/fi-kbl-guc/igt@i915_pm_...@module-reload.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-guc/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][11] ([i915#1886] / [i915#2291])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka:  NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-r:   NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-r/igt@kms_chamel...@hdmi-edid-read.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#533])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-r:   NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#533])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-r/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][16] ([fdo#109271]) +48 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-pnv-d510/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@gem_exec_parallel@engines@userptr:
- fi-pnv-d510:[INCOMPLETE][17] ([i915#299]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/fi-pnv-d510/igt@gem_exec_parallel@engi...@userptr.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-pnv-d510/igt@gem_exec_parallel@engi...@userptr.html

  * igt@gem_exec_suspend@basic-s0:
- fi-kbl-soraka:  [INCOMPLETE][19] ([i915#155]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html
- fi-tgl-1115g4:  [FAIL][21] ([i915#1888]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-tgl-1115g4/ig

[Intel-gfx] ✓ Fi.CI.IGT: success for DSI driver improvement (rev4)

[Patchwork]

== Series Details ==

Series: DSI driver improvement (rev4)
URL   : https://patchwork.freedesktop.org/series/94237/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10562_full -> Patchwork_20990_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_20990_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-massive:
- shard-snb:  NOTRUN -> [DMESG-WARN][1] ([i915#3002])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-snb7/igt@gem_cre...@create-massive.html
- shard-apl:  NOTRUN -> [DMESG-WARN][2] ([i915#3002])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-apl3/igt@gem_cre...@create-massive.html

  * igt@gem_ctx_persistence@idempotent:
- shard-snb:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +4 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-snb6/igt@gem_ctx_persiste...@idempotent.html

  * igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2410])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-tglb6/igt@gem_ctx_persiste...@many-contexts.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-tglb8/igt@gem_ctx_persiste...@many-contexts.html

  * igt@gem_ctx_shared@q-in-order:
- shard-snb:  NOTRUN -> [SKIP][6] ([fdo#109271]) +362 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-snb5/igt@gem_ctx_sha...@q-in-order.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) +2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-none@rcs0:
- shard-glk:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-glk6/igt@gem_exec_fair@basic-n...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-glk1/igt@gem_exec_fair@basic-n...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-iclb1/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_suspend@basic-s3:
- shard-apl:  [PASS][12] -> [DMESG-WARN][13] ([i915#180])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-apl7/igt@gem_exec_susp...@basic-s3.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-apl8/igt@gem_exec_susp...@basic-s3.html

  * igt@gem_mmap_gtt@cpuset-medium-copy-xy:
- shard-glk:  [PASS][14] -> [FAIL][15] ([i915#1888] / [i915#307])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-glk3/igt@gem_mmap_...@cpuset-medium-copy-xy.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-glk4/igt@gem_mmap_...@cpuset-medium-copy-xy.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-apl:  NOTRUN -> [WARN][16] ([i915#2658])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-apl6/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_userptr_blits@coherency-sync:
- shard-tglb: NOTRUN -> [SKIP][17] ([fdo#110542])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-tglb3/igt@gem_userptr_bl...@coherency-sync.html

  * igt@gem_userptr_blits@readonly-unsync:
- shard-tglb: NOTRUN -> [SKIP][18] ([i915#3297])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-tglb3/igt@gem_userptr_bl...@readonly-unsync.html

  * igt@gem_userptr_blits@vma-merge:
- shard-kbl:  NOTRUN -> [FAIL][19] ([i915#3318])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-kbl1/igt@gem_userptr_bl...@vma-merge.html

  * igt@gem_workarounds@suspend-resume:
- shard-apl:  NOTRUN -> [DMESG-WARN][20] ([i915#180])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-apl3/igt@gem_workarou...@suspend-resume.html

  * igt@gen9_exec_parse@bb-start-cmd:
- shard-tglb: NOTRUN -> [SKIP][21] ([i915#2856])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-tglb3/igt@gen9_exec_pa...@bb-start-cmd.html

  * igt@i915_pm_rpm@dpms-non-lpsp:
- shard-iclb: NOTRUN -> [SKIP][22] ([fdo#110892])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-iclb7/igt@i915_pm_...@dpms-non-lpsp.html

  * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-tglb: NOTRUN -> [SKIP][23] ([fdo#109506] / [i915#2411])
   [23]: 
https://intel-gfx-ci.01.org/tree

Re: [Intel-gfx] [PATCH 1/8] drm/i915/xehp: Define compute class and engine

[Daniel Vetter]

On Tue, Sep 07, 2021 at 10:19:09AM -0700, Matt Roper wrote:
> Introduce a Compute Command Streamer (CCS), which has access to
> the media and GPGPU pipelines (but not the 3D pipeline).
> 
> To begin with, define the compute class/engine common functions, based
> on the existing render ones.
> 
> Bspec: 46167, 45544
> Original-patch-by: Michel Thierry
> Cc: Daniele Ceraolo Spurio 
> Cc: Tvrtko Ursulin 
> Cc: Vinay Belgaumkar 
> Cc: Szymon Morek 
> UMD (compute): https://github.com/intel/compute-runtime/pull/451
> Signed-off-by: Rodrigo Vivi 
> Signed-off-by: Daniele Ceraolo Spurio 
> Signed-off-by: Aravind Iddamsetty 
> Signed-off-by: Matt Roper 
> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c| 28 
>  drivers/gpu/drm/i915/gt/intel_engine_types.h |  9 ++-
>  drivers/gpu/drm/i915/gt/intel_engine_user.c  |  5 +++-
>  drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h  | 13 +
>  drivers/gpu/drm/i915/i915_reg.h  |  8 ++
>  include/uapi/drm/i915_drm.h  |  1 +
>  6 files changed, 57 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 332efea696a5..69944bd8c19d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -153,6 +153,34 @@ static const struct engine_info intel_engines[] = {
>   { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
>   },
>   },
> + [CCS0] = {
> + .class = COMPUTE_CLASS,
> + .instance = 0,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE }
> + }
> + },
> + [CCS1] = {
> + .class = COMPUTE_CLASS,
> + .instance = 1,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE }
> + }
> + },
> + [CCS2] = {
> + .class = COMPUTE_CLASS,
> + .instance = 2,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE }
> + }
> + },
> + [CCS3] = {
> + .class = COMPUTE_CLASS,
> + .instance = 3,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
> + }
> + },
>  };
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h 
> b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index bfbfe53c23dd..dcb9d8b2362a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -33,7 +33,8 @@
>  #define VIDEO_ENHANCEMENT_CLASS  2
>  #define COPY_ENGINE_CLASS3
>  #define OTHER_CLASS  4
> -#define MAX_ENGINE_CLASS 4
> +#define COMPUTE_CLASS5
> +#define MAX_ENGINE_CLASS 5
>  #define MAX_ENGINE_INSTANCE  7
>  
>  #define I915_MAX_SLICES  3
> @@ -95,6 +96,7 @@ struct i915_ctx_workarounds {
>  
>  #define I915_MAX_VCS 8
>  #define I915_MAX_VECS4
> +#define I915_MAX_CCS 4
>  
>  /*
>   * Engine IDs definitions.
> @@ -117,6 +119,11 @@ enum intel_engine_id {
>   VECS2,
>   VECS3,
>  #define _VECS(n) (VECS0 + (n))
> + CCS0,
> + CCS1,
> + CCS2,
> + CCS3,
> +#define _CCS(n) (CCS0 + (n))
>   I915_NUM_ENGINES
>  #define INVALID_ENGINE ((enum intel_engine_id)-1)
>  };
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c 
> b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 8f8bea08e734..d981621a7c30 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -47,6 +47,7 @@ static const u8 uabi_classes[] = {
>   [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
>   [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
>   [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
> + [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
>  };
>  
>  static int engine_cmp(void *priv, const struct list_head *A,
> @@ -139,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
>   [COPY_ENGINE_CLASS] = "bcs",
>   [VIDEO_DECODE_CLASS] = "vcs",
>   [VIDEO_ENHANCEMENT_CLASS] = "vecs",
> + [COMPUTE_CLASS] = "ccs",
>   };
>  
>   if (class >= ARRAY_SIZE(uabi_names) || !uabi_names[class])
> @@ -162,6 +164,7 @@ static int legacy_ring_idx(const struct legacy_ring *ring)
>   [COPY_ENGINE_CLASS] = { BCS0, 1 },
>   [VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS },
>   [VIDEO_ENHANCEMENT_CLASS] = { VECS0, I915_MAX_VECS },
> + [COMPUTE_CLASS] = { CCS0, I915_MAX_CCS },
>   };
>  
>   if (GEM_DEBUG_WARN_ON(ring->class >= ARRAY_SIZE(map)))
> @@ -190,7 +193,7 @@ static void add_legacy_ring(struct legacy_ring *ring,
>  void intel_engines_driver_register(struct drm_i915_private *i915)
>  {
> 

Re: [Intel-gfx] [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain

[Daniel Vetter]

On Tue, Sep 07, 2021 at 10:19:10AM -0700, Matt Roper wrote:
> The reset domain is shared between render and all compute engines,
> so resetting one will affect the others.
> 
> Note:  Before performing a reset on an RCS or CCS engine, the GuC will
> attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid
> impacting other clients (since some shared modules will be reset).  If
> other engines are executing non-preemptable workloads, the impact is
> unavoidable and some work may be lost.
> 
> Bspec: 52549
> Original-patch-by: Michel Thierry
> Cc: Tvrtko Ursulin 
> Cc: Vinay Belgaumkar 
> Signed-off-by: Daniele Ceraolo Spurio 
> Signed-off-by: Aravind Iddamsetty 
> Signed-off-by: Matt Roper 

Do we have igts validating this all properly?

Specifically that the reset stats are incremented correctly for guilty
respectively victimized contexts.

This is necessary if it doesn't exist yet.

Also you need a patch set here that fixes up the igts which have wrong
assumptions about context isolation.
-Daniel

> ---
>  drivers/gpu/drm/i915/gt/intel_reset.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 91200c43951f..30598c1d070c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -507,6 +507,10 @@ static int gen11_reset_engines(struct intel_gt *gt,
>   [VECS1] = GEN11_GRDOM_VECS2,
>   [VECS2] = GEN11_GRDOM_VECS3,
>   [VECS3] = GEN11_GRDOM_VECS4,
> + [CCS0] = GEN11_GRDOM_RENDER,
> + [CCS1] = GEN11_GRDOM_RENDER,
> + [CCS2] = GEN11_GRDOM_RENDER,
> + [CCS3] = GEN11_GRDOM_RENDER,
>   };
>   struct intel_engine_cs *engine;
>   intel_engine_mask_t tmp;
> -- 
> 2.25.4
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

Re: [Intel-gfx] [PATCH v2] drm/i915: Handle Intel igfx + Intel dgfx hybrid graphics setup

[Daniel Vetter]

On Thu, Sep 02, 2021 at 04:01:40PM +0100, Tvrtko Ursulin wrote:
> 
> On 02/09/2021 15:33, Daniel Vetter wrote:
> > On Tue, Aug 31, 2021 at 02:18:15PM +0100, Tvrtko Ursulin wrote:
> > > 
> > > On 31/08/2021 13:43, Daniel Vetter wrote:
> > > > On Tue, Aug 31, 2021 at 10:15:03AM +0100, Tvrtko Ursulin wrote:
> > > > > 
> > > > > On 30/08/2021 09:26, Daniel Vetter wrote:
> > > > > > On Fri, Aug 27, 2021 at 03:44:42PM +0100, Tvrtko Ursulin wrote:
> > > > > > > 
> > > > > > > On 27/08/2021 15:39, Tvrtko Ursulin wrote:
> > > > > > > > From: Tvrtko Ursulin 
> > > > > > > > 
> > > > > > > > In short this makes i915 work for hybrid setups (DRI_PRIME=1 
> > > > > > > > with Mesa)
> > > > > > > > when rendering is done on Intel dgfx and scanout/composition on 
> > > > > > > > Intel
> > > > > > > > igfx.
> > > > > > > > 
> > > > > > > > Before this patch the driver was not quite ready for that 
> > > > > > > > setup, mainly
> > > > > > > > because it was able to emit a semaphore wait between the two 
> > > > > > > > GPUs, which
> > > > > > > > results in deadlocks because semaphore target location in HWSP 
> > > > > > > > is neither
> > > > > > > > shared between the two, nor mapped in both GGTT spaces.
> > > > > > > > 
> > > > > > > > To fix it the patch adds an additional check to a couple of 
> > > > > > > > relevant code
> > > > > > > > paths in order to prevent using semaphores for inter-engine
> > > > > > > > synchronisation between different driver instances.
> > > > > > > > 
> > > > > > > > Patch also moves singly used i915_gem_object_last_write_engine 
> > > > > > > > to be
> > > > > > > > private in its only calling unit (debugfs), while modifying it 
> > > > > > > > to only
> > > > > > > > show activity belonging to the respective driver instance.
> > > > > > > > 
> > > > > > > > What remains in this problem space is the question of the GEM 
> > > > > > > > busy ioctl.
> > > > > > > > We have a somewhat ambigous comment there saying only status of 
> > > > > > > > native
> > > > > > > > fences will be reported, which could be interpreted as either 
> > > > > > > > i915, or
> > > > > > > > native to the drm fd. For now I have decided to leave that as 
> > > > > > > > is, meaning
> > > > > > > > any i915 instance activity continues to be reported.
> > > > > > > > 
> > > > > > > > v2:
> > > > > > > >  * Avoid adding rq->i915. (Chris)
> > > > > > > > 
> > > > > > > > Signed-off-by: Tvrtko Ursulin 
> > > > > > 
> > > > > > Can't we just delete semaphore code and done?
> > > > > > - GuC won't have it
> > > > > > - media team benchmarked on top of softpin media driver, found no
> > > > > >  difference
> > > > > 
> > > > > You have S-curve for saturated workloads or something else? How 
> > > > > thorough and
> > > > > which media team I guess.
> > > > > 
> > > > >   From memory it was a nice win for some benchmarks (non-saturated 
> > > > > ones), but
> > > > > as I have told you previously, we haven't been putting numbers in 
> > > > > commit
> > > > > messages since it wasn't allowed. I may be able to dig out some more 
> > > > > details
> > > > > if I went trawling through GEM channel IRC logs, although probably 
> > > > > not the
> > > > > actual numbers since those were usually on pastebin. Or you go an 
> > > > > talk with
> > > > > Chris since he probably remembers more details. Or you just decide 
> > > > > you don't
> > > > > care and remove it. I wouldn't do that without putting the complete 
> > > > > story in
> > > > > writing, but it's your call after all.
> > > > 
> > > > Media has also changed, they're not using relocations anymore.
> > > 
> > > Meaning you think it changes the benchmarking story? When coupled with
> > > removal of GPU relocations then possibly yes.
> > > 
> > > > Unless there's solid data performance tuning of any kind that gets in 
> > > > the
> > > > way simply needs to be removed. Yes this is radical, but the codebase is
> > > > in a state to require this.
> > > > 
> > > > So either way we'd need to rebenchmark this if it's really required. 
> > > > Also
> > > 
> > > Therefore can you share what benchmarks have been done or is it secret?  
> > > As
> > > said, I think the non-saturated case was the more interesting one here.
> > > 
> > > > if we really need this code still someone needs to fix the design, the
> > > > current code is making layering violations an art form.
> > > > 
> > > > > Anyway, without the debugfs churn it is more or less two line patch 
> > > > > to fix
> > > > > igfx + dgfx hybrid setup. So while mulling it over this could go in. 
> > > > > I'd
> > > > > just refine it to use a GGTT check instead of GT. And unless DG1 ends 
> > > > > up
> > > > > being GuC only.
> > > > 
> > > > The minimal robust fix here is imo to stop us from upcasting dma_fence 
> > > > to
> > > > i915_request if it's not for our device. Not sprinkle code here into the
> > > > semaphore code. We shouldn't even get this far with foreign fences.
> > > 
> > > Device check does not w

Re: [Intel-gfx] [PATCH][next] drm/i915: clean up inconsistent indenting

[Daniel Vetter]

On Thu, Sep 02, 2021 at 10:57:37PM +0100, Colin King wrote:
> From: Colin Ian King 
> 
> There is a statement that is indented one character too deeply,
> clean this up.
> 
> Signed-off-by: Colin Ian King 

Queued to drm-intel-gt-next, thanks for patch.
-Daniel

> ---
>  drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index de5f9c86b9a4..aeb324b701ec 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2565,7 +2565,7 @@ __execlists_context_pre_pin(struct intel_context *ce,
>   if (!__test_and_set_bit(CONTEXT_INIT_BIT, &ce->flags)) {
>   lrc_init_state(ce, engine, *vaddr);
>  
> -  __i915_gem_object_flush_map(ce->state->obj, 0, 
> engine->context_size);
> + __i915_gem_object_flush_map(ce->state->obj, 0, 
> engine->context_size);
>   }
>  
>   return 0;
> -- 
> 2.32.0
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

Re: [Intel-gfx] [PATCH] drm/i915/request: fix early tracepoints

[Daniel Vetter]

On Fri, Sep 03, 2021 at 12:24:05PM +0100, Matthew Auld wrote:
> Currently we blow up in trace_dma_fence_init, when calling into
> get_driver_name or get_timeline_name, since both the engine and context
> might be NULL(or contain some garbage address) in the case of newly
> allocated slab objects via the request ctor. Note that we also use
> SLAB_TYPESAFE_BY_RCU here, which allows requests to be immediately
> freed, but delay freeing the underlying page by an RCU grace period.
> With this scheme requests can be re-allocated, at the same time as they
> are also being read by some lockless RCU lookup mechanism.
> 
> One possible fix, since we don't yet have a fully initialised request
> when in the ctor, is just setting the context/engine as NULL and adding
> some extra handling in get_driver_name etc. And since the ctor is only
> called for new slab objects(i.e allocate new page and call the ctor for
> each object) it's safe to reset the context/engine prior to calling into
> dma_fence_init, since we can be certain that no one is doing an RCU
> lookup which might depend on peeking at the engine/context, like in
> active_engine(), since the object can't yet be externally visible.
> 
> In the recycled case(which might also be externally visible) the request
> refcount always transitions from 0->1 after we set the context/engine
> etc, which should ensure it's valid to dereference the engine for
> example, when doing an RCU list-walk, so long as we can also increment
> the refcount first. If the refcount is already zero, then the request is
> considered complete/released.  If it's non-zero, then the request might
> be in the process of being re-allocated, or potentially still in flight,
> however after successfully incrementing the refcount, it's possible to
> carefully inspect the request state, to determine if the request is
> still what we were looking for. Note that all externally visible
> requests returned to the cache must have zero refcount.

The commit message here is a bit confusing, since you start out with
describing a solution that you're not actually implementing it. I usually
do this by putting alternate solutions at the bottom, starting with "An
alternate solution would be ..." or so.

And then closing with why we don't do that, here it would be that we do
no longer have a need for these partially set up i915_requests, and
therefore just reverting that complication is the simplest solution.

> An alternative fix then is to instead move the dma_fence_init out from
> the request ctor. Originally this was how it was done, but it was moved
> in:
> 
> commit 855e39e65cfc33a73724f1cc644ffc5754864a20
> Author: Chris Wilson 
> Date:   Mon Feb 3 09:41:48 2020 +
> 
> drm/i915: Initialise basic fence before acquiring seqno
> 
> where it looks like intel_timeline_get_seqno() relied on some of the
> rq->fence state, but that is no longer the case since:
> 
> commit 12ca695d2c1ed26b2dcbb528b42813bd0f216cfc
> Author: Maarten Lankhorst 
> Date:   Tue Mar 23 16:49:50 2021 +0100
> 
> drm/i915: Do not share hwsp across contexts any more, v8.
> 
> intel_timeline_get_seqno() could also be cleaned up slightly by dropping
> the request argument.
> 
> Moving dma_fence_init back out of the ctor, should ensure we have enough
> of the request initialised in case of trace_dma_fence_init.
> Functionally this should be the same, and is effectively what we were
> already open coding before, except now we also assign the fence->lock
> and fence->ops, but since these are invariant for recycled
> requests(which might be externally visible), and will therefore already
> hold the same value, it shouldn't matter. We still leave the
> spin_lock_init() in the ctor, since we can't re-init the rq->lock in
> case it is already held.

Holding rq->lock without having a full reference to it sounds like really
bad taste. I think it would be good to have a (kerneldoc) comment next to
i915_request.lock about this, with a FIXME. But separate patch.

> Fixes: 855e39e65cfc ("drm/i915: Initialise basic fence before acquiring 
> seqno")
> Signed-off-by: Matthew Auld 
> Cc: Michael Mason 
> Cc: Daniel Vetter 

With the commit message restructured a bit, and assuming this one actually
works:

Reviewed-by: Daniel Vetter 

But I'm really not confident :-(
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_request.c | 11 ++-
>  1 file changed, 2 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_request.c 
> b/drivers/gpu/drm/i915/i915_request.c
> index ce446716d092..79da5eca60af 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -829,8 +829,6 @@ static void __i915_request_ctor(void *arg)
>   i915_sw_fence_init(&rq->submit, submit_notify);
>   i915_sw_fence_init(&rq->semaphore, semaphore_notify);
>  
> - dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock, 0, 0);
> -
>   rq->capture_list = NULL;
>  
>   init_llist_head(&rq->execute_cb);
> @@ -905,

[Intel-gfx] [PULL] drm-misc-fixes

[Thomas Zimmermann]

Hi Dave and Daniel,

here's this week's PR for drm-misc-fixes. One patch is a potential deadlock
in TTM, the other enables an additional plane in kmb. I'm slightly unhappy
that the latter one ended up in -fixes as it's not a bugfix AFAICT.

Best regards
Thomas

drm-misc-fixes-2021-09-08:
Short summary of fixes pull:

 * kmb: Emable second plane
 * ttm: Fix potential deadlock during swap

The following changes since commit fa0b1ef5f7a694f48e00804a391245f3471aa155:

  drm: Copy drm_wait_vblank to user before returning (2021-08-17 13:56:03 -0400)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2021-09-08

for you to fetch changes up to c8704b7ec182f9293e6a994310c7d4203428cdfb:

  drm/kmb: Enable alpha blended second plane (2021-09-07 10:10:30 -0700)


Short summary of fixes pull:

 * kmb: Emable second plane
 * ttm: Fix potential deadlock during swap


Edmund Dea (1):
  drm/kmb: Enable alpha blended second plane

xinhui pan (1):
  drm/ttm: Fix a deadlock if the target BO is not idle during swap

 drivers/gpu/drm/kmb/kmb_drv.c   |  8 ++--
 drivers/gpu/drm/kmb/kmb_drv.h   |  5 +++
 drivers/gpu/drm/kmb/kmb_plane.c | 81 -
 drivers/gpu/drm/kmb/kmb_plane.h |  5 ++-
 drivers/gpu/drm/kmb/kmb_regs.h  |  3 ++
 drivers/gpu/drm/ttm/ttm_bo.c|  6 +--
 6 files changed, 90 insertions(+), 18 deletions(-)

--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Felix Imendörffer

Re: [Intel-gfx] [PATCH] kernel/locking: Add context to ww_mutex_trylock.

[Daniel Vetter]

On Wed, Sep 08, 2021 at 12:14:23PM +0200, Peter Zijlstra wrote:
> On Tue, Sep 07, 2021 at 03:20:44PM +0200, Maarten Lankhorst wrote:
> > i915 will soon gain an eviction path that trylock a whole lot of locks
> > for eviction, getting dmesg failures like below:
> > 
> > BUG: MAX_LOCK_DEPTH too low!
> > turning off the locking correctness validator.
> > depth: 48  max: 48!
> > 48 locks held by i915_selftest/5776:
> >  #0: 888101a79240 (&dev->mutex){}-{3:3}, at: 
> > __driver_attach+0x88/0x160
> >  #1: c99778c0 (reservation_ww_class_acquire){+.+.}-{0:0}, at: 
> > i915_vma_pin.constprop.63+0x39/0x1b0 [i915]
> >  #2: 88800cf74de8 (reservation_ww_class_mutex){+.+.}-{3:3}, at: 
> > i915_vma_pin.constprop.63+0x5f/0x1b0 [i915]
> >  #3: 88810c7f9e38 (&vm->mutex/1){+.+.}-{3:3}, at: 
> > i915_vma_pin_ww+0x1c4/0x9d0 [i915]
> >  #4: 88810bad5768 (reservation_ww_class_mutex){+.+.}-{3:3}, at: 
> > i915_gem_evict_something+0x110/0x860 [i915]
> >  #5: 88810bad60e8 (reservation_ww_class_mutex){+.+.}-{3:3}, at: 
> > i915_gem_evict_something+0x110/0x860 [i915]
> > ...
> >  #46: 88811964d768 (reservation_ww_class_mutex){+.+.}-{3:3}, at: 
> > i915_gem_evict_something+0x110/0x860 [i915]
> >  #47: 88811964e0e8 (reservation_ww_class_mutex){+.+.}-{3:3}, at: 
> > i915_gem_evict_something+0x110/0x860 [i915]
> > INFO: lockdep is turned off.
> 
> > As an intermediate solution, add an acquire context to ww_mutex_trylock,
> > which allows us to do proper nesting annotations on the trylocks, making
> > the above lockdep splat disappear.
> 
> Fair enough I suppose.

What's maybe missing from the commit message
- we'll probably use this for ttm too eventually
- even when we add full ww_mutex locking we'll still have the trylock
  fastpath. This is because we have a lock inversion against list locks in
  these eviction paths, and the slow path unroll to drop that list lock is
  a bit nasty (and defintely expensive).

iow even long term this here is needed in some form I think.
-Daniel

> 
> > +/**
> > + * ww_mutex_trylock - tries to acquire the w/w mutex with optional acquire 
> > context
> > + * @lock: mutex to lock
> > + * @ctx: optional w/w acquire context
> > + *
> > + * Trylocks a mutex with the optional acquire context; no deadlock 
> > detection is
> > + * possible. Returns 1 if the mutex has been acquired successfully, 0 
> > otherwise.
> > + *
> > + * Unlike ww_mutex_lock, no deadlock handling is performed. However, if a 
> > @ctx is
> > + * specified, -EALREADY and -EDEADLK handling may happen in calls to 
> > ww_mutex_lock.
> > + *
> > + * A mutex acquired with this function must be released with 
> > ww_mutex_unlock.
> > + */
> > +int __sched
> > +ww_mutex_trylock(struct ww_mutex *ww, struct ww_acquire_ctx *ctx)
> > +{
> > +   bool locked;
> > +
> > +   if (!ctx)
> > +   return mutex_trylock(&ww->base);
> > +
> > +#ifdef CONFIG_DEBUG_MUTEXES
> > +   DEBUG_LOCKS_WARN_ON(ww->base.magic != &ww->base);
> > +#endif
> > +
> > +   preempt_disable();
> > +   locked = __mutex_trylock(&ww->base);
> > +
> > +   if (locked) {
> > +   ww_mutex_set_context_fastpath(ww, ctx);
> > +   mutex_acquire_nest(&ww->base.dep_map, 0, 1, &ctx->dep_map, 
> > _RET_IP_);
> > +   }
> > +   preempt_enable();
> > +
> > +   return locked;
> > +}
> > +EXPORT_SYMBOL(ww_mutex_trylock);
> 
> You'll need a similar hunk in ww_rt_mutex.c

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

[Intel-gfx] [RFC PATCH 2/2] drm/i915/gt: Use spin_lock_irq() instead of local_irq_disable() + spin_lock()

[Sebastian Andrzej Siewior]

execlists_dequeue() is invoked from a function which uses
local_irq_disable() to disable interrupts so the spin_lock() behaves
like spin_lock_irq().
This breaks PREEMPT_RT because local_irq_disable() + spin_lock() is not
the same as spin_lock_irq().

execlists_dequeue_irq() and execlists_dequeue() has each one caller
only. If intel_engine_cs::active::lock is acquired and released with the
_irq suffix then it behaves almost as if execlists_dequeue() would be
invoked with disabled interrupts. The difference is the last part of the
function which is then invoked with enabled interrupts.
I can't tell if this makes a difference. From looking at it, it might
work to move the last unlock at the end of the function as I didn't find
anything that would acquire the lock again.

Reported-by: Clark Williams 
Signed-off-by: Sebastian Andrzej Siewior 
---
 .../drm/i915/gt/intel_execlists_submission.c| 17 +
 1 file changed, 5 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index fc77592d88a96..2ec1dd352960b 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1265,7 +1265,7 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * and context switches) submission.
 */
 
-   spin_lock(&engine->active.lock);
+   spin_lock_irq(&engine->active.lock);
 
/*
 * If the queue is higher priority than the last
@@ -1365,7 +1365,7 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * Even if ELSP[1] is occupied and not worthy
 * of timeslices, our queue might be.
 */
-   spin_unlock(&engine->active.lock);
+   spin_unlock_irq(&engine->active.lock);
return;
}
}
@@ -1391,7 +1391,7 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 
if (last && !can_merge_rq(last, rq)) {
spin_unlock(&ve->base.active.lock);
-   spin_unlock(&engine->active.lock);
+   spin_unlock_irq(&engine->active.lock);
return; /* leave this for another sibling */
}
 
@@ -1552,7 +1552,7 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
 * interrupt for secondary ports).
 */
execlists->queue_priority_hint = queue_prio(execlists);
-   spin_unlock(&engine->active.lock);
+   spin_unlock_irq(&engine->active.lock);
 
/*
 * We can skip poking the HW if we ended up with exactly the same set
@@ -1578,13 +1578,6 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
}
 }
 
-static void execlists_dequeue_irq(struct intel_engine_cs *engine)
-{
-   local_irq_disable(); /* Suspend interrupts across request submission */
-   execlists_dequeue(engine);
-   local_irq_enable(); /* flush irq_work (e.g. breadcrumb enabling) */
-}
-
 static void clear_ports(struct i915_request **ports, int count)
 {
memset_p((void **)ports, NULL, count);
@@ -2377,7 +2370,7 @@ static void execlists_submission_tasklet(struct 
tasklet_struct *t)
}
 
if (!engine->execlists.pending[0]) {
-   execlists_dequeue_irq(engine);
+   execlists_dequeue(engine);
start_timeslice(engine);
}
 
-- 
2.33.0

[Intel-gfx] [PATCH 0/2] drm/i915/gt: Locking splats PREEMPT_RT

[Sebastian Andrzej Siewior]

Clark Williams reported two issues with the i915 driver running on
PREEMPT_RT. While #1 looks simple I have no idea about #2 thus the RFC.

Sebastian

[Intel-gfx] [PATCH 1/2] drm/i915/gt: Queue and wait for the irq_work item.

[Sebastian Andrzej Siewior]

Disabling interrupts and invoking the irq_work function directly breaks
on PREEMPT_RT.
PREEMPT_RT does not invoke all irq_work from hardirq context because
some of the user have spinlock_t locking in the callback function.
These locks are then turned into a sleeping locks which can not be
acquired with disabled interrupts.

Using irq_work_queue() has the benefit that the irqwork will be invoked
in the regular context. In general there is "no" delay between enqueuing
the callback and its invocation because the interrupt is raised right
away on architectures which support it (which includes x86).

Use irq_work_queue() + irq_work_sync() instead invoking the callback
directly.

Reported-by: Clark Williams 
Signed-off-by: Sebastian Andrzej Siewior 
---
 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index 38cc42783dfb2..594dec2f76954 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -318,10 +318,9 @@ void __intel_breadcrumbs_park(struct intel_breadcrumbs *b)
/* Kick the work once more to drain the signalers, and disarm the irq */
irq_work_sync(&b->irq_work);
while (READ_ONCE(b->irq_armed) && !atomic_read(&b->active)) {
-   local_irq_disable();
-   signal_irq_work(&b->irq_work);
-   local_irq_enable();
+   irq_work_queue(&b->irq_work);
cond_resched();
+   irq_work_sync(&b->irq_work);
}
 }
 
-- 
2.33.0

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gt: Locking splats PREEMPT_RT

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Locking splats PREEMPT_RT
URL   : https://patchwork.freedesktop.org/series/94480/
State : failure

== Summary ==

Applying: drm/i915/gt: Queue and wait for the irq_work item.
Applying: drm/i915/gt: Use spin_lock_irq() instead of local_irq_disable() + 
spin_lock()
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/gt/intel_execlists_submission.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/gt/intel_execlists_submission.c
CONFLICT (content): Merge conflict in 
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0002 drm/i915/gt: Use spin_lock_irq() instead of 
local_irq_disable() + spin_lock()
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

Re: [Intel-gfx] [RFC 1/5] drm/i915/panelreplay: update plane selective fetch register definition

[Souza, Jose]

On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> Panel replay can be enabled for all pipes driving DP 2.0 monitor,
> so updated the plane selective fetch register difinition accordingly.

It should mention that this changes are to accommodate differences in DG2.

Anyways, DG2 had PSR2 support dropped so we don't need this whole patch.

> 
> Signed-off-by: Animesh Manna 
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c |  8 +++---
>  drivers/gpu/drm/i915/i915_reg.h  | 32 +---
>  2 files changed, 22 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 3f6fb7d67f84..5fa76b148f6d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1445,7 +1445,7 @@ void intel_psr2_program_plane_sel_fetch(struct 
> intel_plane *plane,
>  
>   val = plane_state ? plane_state->ctl : 0;
>   val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE;
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val);
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(dev_priv, pipe, 
> plane->id), val);
>   if (!val || plane->id == PLANE_CURSOR)
>   return;
>  
> @@ -1453,19 +1453,19 @@ void intel_psr2_program_plane_sel_fetch(struct 
> intel_plane *plane,
>  
>   val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
>   val |= plane_state->uapi.dst.x1;
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(dev_priv, pipe, 
> plane->id), val);
>  
>   /* TODO: consider auxiliary surfaces */
>   x = plane_state->uapi.src.x1 >> 16;
>   y = (plane_state->uapi.src.y1 >> 16) + clip->y1;
>   val = y << 16 | x;
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(dev_priv, pipe, 
> plane->id),
> val);
>  
>   /* Sizes are 0 based */
>   val = (drm_rect_height(clip) - 1) << 16;
>   val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(dev_priv, pipe, 
> plane->id), val);
>  }
>  
>  void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state 
> *crtc_state)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c2853cc005ee..5bc8f22fa9a8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7471,6 +7471,7 @@ enum {
>  #define _SEL_FETCH_PLANE_BASE_7_A0x70960
>  #define _SEL_FETCH_PLANE_BASE_CUR_A  0x70880
>  #define _SEL_FETCH_PLANE_BASE_1_B0x70990
> +#define _DG2_SEL_FETCH_PLANE_BASE_1_B0x71890
>  
>  #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
>_SEL_FETCH_PLANE_BASE_1_A, \
> @@ -7481,31 +7482,34 @@ enum {
>_SEL_FETCH_PLANE_BASE_6_A, \
>_SEL_FETCH_PLANE_BASE_7_A, \
>_SEL_FETCH_PLANE_BASE_CUR_A)
> -#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, 
> _SEL_FETCH_PLANE_BASE_1_B)
> -#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
> - _SEL_FETCH_PLANE_BASE_1_A + \
> - _SEL_FETCH_PLANE_BASE_A(plane))
> +#define _SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) _PIPE(pipe, 
> _SEL_FETCH_PLANE_BASE_1_A, \
> +   DISPLAY_VER(dev_priv) > 
> 12 ? \
> +   
> _DG2_SEL_FETCH_PLANE_BASE_1_B : \
> +   _SEL_FETCH_PLANE_BASE_1_B)
> +#define _SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) 
> (_SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) - \
> +   _SEL_FETCH_PLANE_BASE_1_A 
> + \
> +   
> _SEL_FETCH_PLANE_BASE_A(plane))
>  
>  #define _SEL_FETCH_PLANE_CTL_1_A 0x70890
> -#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, 
> plane) + \
> +#define PLANE_SEL_FETCH_CTL(dev_priv, pipe, plane) 
> _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
>  _SEL_FETCH_PLANE_CTL_1_A - \
>  _SEL_FETCH_PLANE_BASE_1_A)
>  #define PLANE_SEL_FETCH_CTL_ENABLE   REG_BIT(31)
>  
>  #define _SEL_FETCH_PLANE_POS_1_A 0x70894
> -#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, 
> plane) + \
> -_SEL_FETCH_PLANE_POS_1_A 

Re: [Intel-gfx] [RFC 2/5] drm/i915/panelreplay: Feature flag added for panel replay

[Souza, Jose]

On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> Platforms having Display 13 and above will support panel
> replay feature of DP 2.0 monitor. Added a feature flag
> for panel replay.

As all display 13 and newer platforms supports it would be better to have 
#define HAS_PR(i915) (DISPLAY_VER(i915) >= 13) instead of add one more
parameter to intel_device_info.

> 
> Signed-off-by: Animesh Manna 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 1 +
>  drivers/gpu/drm/i915/i915_pci.c  | 1 +
>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
>  3 files changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1fd3040b6771..5b26d7c09b2d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1645,6 +1645,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
>  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) 
> (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
>  #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
> +#define HAS_PR(dev_priv)  (INTEL_INFO(dev_priv)->display.has_pr)
>  #define HAS_PSR_HW_TRACKING(dev_priv) \
>   (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
>  #define HAS_PSR2_SEL_FETCH(dev_priv)  (GRAPHICS_VER(dev_priv) >= 12)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d4a6a9dcf182..c58bd19b5bdf 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -946,6 +946,7 @@ static const struct intel_device_info adl_s_info = {
>   .display.has_hotplug = 1,   
> \
>   .display.has_ipc = 1,   
> \
>   .display.has_psr = 1,   
> \
> + .display.has_pr = 1,\
>   .display.ver = 13,  
> \
>   .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), 
> \
>   .pipe_offsets = {   
> \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> b/drivers/gpu/drm/i915/intel_device_info.h
> index d328bb95c49b..4552a1f88568 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -161,6 +161,7 @@ enum intel_ppgtt_type {
>   func(has_modular_fia); \
>   func(has_overlay); \
>   func(has_psr); \
> + func(has_pr); \
>   func(has_psr_hw_tracking); \
>   func(overlay_needs_physical); \
>   func(supports_tv);

Re: [Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay

[Souza, Jose]

On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> As panel replay feature similar to PSR feature of EDP panel, so currently
> utilized existing psr framework for panel replay.
> 
> Signed-off-by: Animesh Manna 
> ---
>  .../drm/i915/display/intel_display_types.h|  4 ++
>  drivers/gpu/drm/i915/display/intel_dp.c   | 47 +++
>  drivers/gpu/drm/i915/display/intel_psr.c  | 43 +
>  drivers/gpu/drm/i915/display/intel_psr.h  |  3 ++
>  include/drm/drm_dp_helper.h   |  3 ++
>  5 files changed, 91 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c7bcf9183447..6ca9fabb9333 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1066,6 +1066,7 @@ struct intel_crtc_state {
>   bool req_psr2_sdp_prior_scanline;
>   u32 dc3co_exitline;
>   u16 su_y_granularity;
> + bool has_panel_replay;
>  
>   /*
>* Frequence the dpll for the port should run at. Differs from the
> @@ -1526,6 +1527,8 @@ struct intel_psr {
>   bool irq_aux_error;
>   u16 su_w_granularity;
>   u16 su_y_granularity;
> + bool sink_pr_support;
> + bool pr_enabled;

Instead of all the above we could have a function that checks if displayPort is 
eDP or not, to know if is PSR or PR.
sink_support and all the others should be shared for PSR and PR.

>   u32 dc3co_exitline;
>   u32 dc3co_exit_delay;
>   struct delayed_work dc3co_work;
> @@ -1552,6 +1555,7 @@ struct intel_dp {
>   u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
>   u8 fec_capable;
>   u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
> + u8 pr_dpcd;

Used once why cache it?

>   /* source rates */
>   int num_source_rates;
>   const int *source_rates;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index d28bd8c4a8a5..90c708548811 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1560,12 +1560,22 @@ static void intel_dp_compute_vsc_colorimetry(const 
> struct intel_crtc_state *crtc
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> - /*
> -  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> -  * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> -  * Colorimetry Format indication.
> -  */
> - vsc->revision = 0x5;
> + if (crtc_state->has_panel_replay) {
> + /*
> +  * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> +  * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> +  * Encoding/Colorimetry Format indication.
> +  */
> + vsc->revision = 0x7;
> + } else {
> + /*
> +  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> +  * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> +  * Colorimetry Format indication.
> +  */
> + vsc->revision = 0x5;
> + }
> +
>   vsc->length = 0x13;
>  
>   /* DP 1.4a spec, Table 2-120 */
> @@ -1674,6 +1684,22 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp 
> *intel_dp,
>   vsc->revision = 0x4;
>   vsc->length = 0xe;
>   }
> + } else if (intel_dp->psr.pr_enabled) {
> + if (intel_dp->psr.colorimetry_support &&
> + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> + /* [PR, +Colorimetry] */
> + intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> +  vsc);
> + } else {
> + /*
> +  * [PR, -Colorimetry]
> +  * Prepare VSC Header for SU as per DP 2.0 spec, Table 
> 2-223
> +  * VSC SDP supporting 3D stereo + PR (applies to eDP 
> v1.3 or
> +  * higher).
> +  */
> + vsc->revision = 0x6;
> + vsc->length = 0x10;
> + }
>   } else {
>   /*
>* [PSR1]
> @@ -1814,6 +1840,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  
>   intel_vrr_compute_config(pipe_config, conn_state);
>   intel_psr_compute_config(intel_dp, pipe_config);
> + intel_panel_replay_compute_config(intel_dp, pipe_config);
>   intel_drrs_compute_config(intel_dp, pipe_config, output_bpp,
> constant_n);
>   intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> @@ -2719,10 +2746,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct 
> drm_dp_vsc_sdp *vsc,

Re: [Intel-gfx] [RFC 1/5] drm/i915/panelreplay: update plane selective fetch register definition

[Manna, Animesh]

> -Original Message-
> From: Souza, Jose 
> Sent: Thursday, September 9, 2021 12:57 AM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong ; Nikula, Jani
> ; Kahola, Mika ; Navare,
> Manasi D 
> Subject: Re: [Intel-gfx] [RFC 1/5] drm/i915/panelreplay: update plane 
> selective
> fetch register definition
> 
> On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> > Panel replay can be enabled for all pipes driving DP 2.0 monitor, so
> > updated the plane selective fetch register difinition accordingly.
> 
> It should mention that this changes are to accommodate differences in DG2.
> 
> Anyways, DG2 had PSR2 support dropped so we don't need this whole patch.

Panel replay can also use selective fetch/update .. rt? 
DG2 will support panel replay if not PSR2.

Regards,
Animesh
> 
> >
> > Signed-off-by: Animesh Manna 
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c |  8 +++---
> >  drivers/gpu/drm/i915/i915_reg.h  | 32 +---
> >  2 files changed, 22 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 3f6fb7d67f84..5fa76b148f6d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1445,7 +1445,7 @@ void intel_psr2_program_plane_sel_fetch(struct
> > intel_plane *plane,
> >
> > val = plane_state ? plane_state->ctl : 0;
> > val &= plane->id == PLANE_CURSOR ? val :
> PLANE_SEL_FETCH_CTL_ENABLE;
> > -   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
> val);
> > +   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(dev_priv, pipe,
> > +plane->id), val);
> > if (!val || plane->id == PLANE_CURSOR)
> > return;
> >
> > @@ -1453,19 +1453,19 @@ void intel_psr2_program_plane_sel_fetch(struct
> > intel_plane *plane,
> >
> > val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
> > val |= plane_state->uapi.dst.x1;
> > -   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id),
> val);
> > +   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(dev_priv, pipe,
> > +plane->id), val);
> >
> > /* TODO: consider auxiliary surfaces */
> > x = plane_state->uapi.src.x1 >> 16;
> > y = (plane_state->uapi.src.y1 >> 16) + clip->y1;
> > val = y << 16 | x;
> > -   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane-
> >id),
> > +   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(dev_priv, pipe,
> > +plane->id),
> >   val);
> >
> > /* Sizes are 0 based */
> > val = (drm_rect_height(clip) - 1) << 16;
> > val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
> > -   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id),
> val);
> > +   intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(dev_priv, pipe,
> > +plane->id), val);
> >  }
> >
> >  void intel_psr2_program_trans_man_trk_ctl(const struct
> > intel_crtc_state *crtc_state) diff --git
> > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index c2853cc005ee..5bc8f22fa9a8 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7471,6 +7471,7 @@ enum {
> >  #define _SEL_FETCH_PLANE_BASE_7_A  0x70960
> >  #define _SEL_FETCH_PLANE_BASE_CUR_A0x70880
> >  #define _SEL_FETCH_PLANE_BASE_1_B  0x70990
> > +#define _DG2_SEL_FETCH_PLANE_BASE_1_B  0x71890
> >
> >  #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
> >  _SEL_FETCH_PLANE_BASE_1_A, \
> @@ -7481,31 +7482,34 @@ enum {
> >  _SEL_FETCH_PLANE_BASE_6_A, \
> >  _SEL_FETCH_PLANE_BASE_7_A, \
> >  _SEL_FETCH_PLANE_BASE_CUR_A) -
> #define
> > _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe,
> _SEL_FETCH_PLANE_BASE_1_A,
> > _SEL_FETCH_PLANE_BASE_1_B) -#define _SEL_FETCH_PLANE_BASE(pipe,
> plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
> > -   _SEL_FETCH_PLANE_BASE_1_A + \
> > -   _SEL_FETCH_PLANE_BASE_A(plane))
> > +#define _SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) _PIPE(pipe,
> _SEL_FETCH_PLANE_BASE_1_A, \
> > + DISPLAY_VER(dev_priv) >
> 12 ? \
> > +
> _DG2_SEL_FETCH_PLANE_BASE_1_B : \
> > +
> _SEL_FETCH_PLANE_BASE_1_B) #define
> > +_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane)
> (_SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) - \
> > +
> _SEL_FETCH_PLANE_BASE_1_A + \
> > +
> _SEL_FETCH_PLANE_BASE_A(plane))
> >
> >  #define _SEL_FETCH_PLANE_CTL_1_A   0x70890
> > -#define PLANE_SEL_FETCH_CTL(pipe, plane)
> > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> > +#define PLANE_SEL_FETCH_CTL(dev_priv, pipe, plane)
> > +_MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
> >_SEL_FETC

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Suspend / resume backup- and restore of LMEM. (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev3)
URL   : https://patchwork.freedesktop.org/series/94278/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10563_full -> Patchwork_20991_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_20991_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20991_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_20991_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_rps@reset:
- shard-skl:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/shard-skl10/igt@i915_pm_...@reset.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-skl8/igt@i915_pm_...@reset.html

  
Known issues


  Here are the changes found in Patchwork_20991_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-massive:
- shard-apl:  NOTRUN -> [DMESG-WARN][3] ([i915#3002])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-apl3/igt@gem_cre...@create-massive.html

  * igt@gem_ctx_param@set-priority-not-supported:
- shard-tglb: NOTRUN -> [SKIP][4] ([fdo#109314])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-tglb5/igt@gem_ctx_pa...@set-priority-not-supported.html

  * igt@gem_ctx_persistence@legacy-engines-mixed-process:
- shard-snb:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +3 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-mixed-process.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][6] -> [FAIL][7] ([i915#2846])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/shard-glk3/igt@gem_exec_f...@basic-deadline.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-glk7/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk:  [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/shard-glk5/igt@gem_exec_fair@basic-none-r...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-glk3/igt@gem_exec_fair@basic-none-r...@rcs0.html
- shard-tglb: NOTRUN -> [FAIL][10] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-tglb5/igt@gem_exec_fair@basic-none-r...@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-iclb6/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_nop@basic-series:
- shard-glk:  [PASS][14] -> [DMESG-WARN][15] ([i915#118] / 
[i915#95])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/shard-glk4/igt@gem_exec_...@basic-series.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-glk7/igt@gem_exec_...@basic-series.html

  * igt@gem_exec_params@secure-non-master:
- shard-tglb: NOTRUN -> [SKIP][16] ([fdo#112283])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-tglb1/igt@gem_exec_par...@secure-non-master.html

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][17] -> [SKIP][18] ([i915#2190])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/shard-tglb2/igt@gem_huc_c...@huc-copy.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-tglb7/igt@gem_huc_c...@huc-copy.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-snb:  NOTRUN -> [WARN][19] ([i915#2658]) +1 similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-snb2/igt@gem_pwr...@basic-exhaustion.html
- shard-kbl:  NOTRUN -> [WARN][20] ([i915#2658])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-kbl7/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-glk:  NOTRUN -> [SKIP][21] ([fdo#109271]) +3 similar issues
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-glk2/igt@gem_render_c...@linear-

Re: [Intel-gfx] [RFC 4/5] drm/i915/panelreplay: enable/disable panel replay

[Souza, Jose]

On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> TRANS_DP2_CTL register is programmed to enable panel replay from source
> and sink is enabled through panel replay dpcd configuration address.
> 
> Signed-off-by: Animesh Manna 
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 30 
>  drivers/gpu/drm/i915/i915_reg.h  |  1 +
>  include/drm/drm_dp_helper.h  |  3 +++
>  3 files changed, 29 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 660e19c10aa8..1dc6b340d745 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -369,8 +369,12 @@ static void intel_psr_enable_sink(struct intel_dp 
> *intel_dp)
>   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>   u8 dpcd_val = DP_PSR_ENABLE;
>  
> - /* Enable ALPM at sink for psr2 */
> - if (intel_dp->psr.psr2_enabled) {
> + if (intel_dp->psr.pr_enabled) {
> + drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
> +PANEL_REPLAY_ENABLE);
> + return;

If you are sure no other dpcd write is needed better separate this if + return 
from the other


if (intel_dp->psr.pr_enabled) {
...
return;
}

if (intel_dp->psr.psr2_enabled) {

} else {
...
}



> + } else if (intel_dp->psr.psr2_enabled) {
> + /* Enable ALPM at sink for psr2 */
>   drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
>  DP_ALPM_ENABLE |
>  DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> @@ -497,6 +501,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp 
> *intel_dp)
>   return val;
>  }
>  
> +static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
> +ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE);
> +
> + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
> +  TRANS_DP2_PANEL_REPLAY_ENABLE);

PSR2 is not supported in DG2 and I would believe that is the case for panel 
relay.

> +}
> +
>  static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  {
>   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -1077,8 +1092,10 @@ static void intel_psr_activate(struct intel_dp 
> *intel_dp)
>   drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
>   lockdep_assert_held(&intel_dp->psr.lock);
>  
> - /* psr1 and psr2 are mutually exclusive.*/
> - if (intel_dp->psr.psr2_enabled)
> + /* psr1, psr2 and panel-replay are mutually exclusive.*/
> + if (intel_dp->psr.pr_enabled)
> + dg2_activate_panel_replay(intel_dp);
> + else if (intel_dp->psr.psr2_enabled)
>   hsw_activate_psr2(intel_dp);
>   else
>   hsw_activate_psr1(intel_dp);
> @@ -1267,7 +1284,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
>   return;
>   }
>  
> - if (intel_dp->psr.psr2_enabled) {
> + if (intel_dp->psr.pr_enabled) {
> + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
> +  TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
> + } else if (intel_dp->psr.psr2_enabled) {
>   tgl_disallow_dc3co_on_psr2_exit(intel_dp);
>   val = intel_de_read(dev_priv,
>   EDP_PSR2_CTL(intel_dp->psr.transcoder));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5bc8f22fa9a8..9effbc6e5539 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4720,6 +4720,7 @@ enum {
>  #define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME   
> REG_BIT(3)
>  #define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAMEREG_BIT(2)
>  #define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATEREG_BIT(1)
> +#define  ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE   
> REG_BIT(31)
>  #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 
> 16)
>  #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) 
> REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
>  #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK   
> REG_GENMASK(12, 0)
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 1b4dcee3b281..63face4e4f6f 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -707,6 +707,9 @@ struct drm_panel;
>  #define DP_BRANCH_DEVICE_CTRL0x1a1
>  # define DP_BRANCH_DEVICE_IRQ_HPD(1 << 0)
>  
> +#define PANEL_REPLAY_CONFIG 0x1b0
> +# define PANEL_REPLAY_ENABLE(1 << 0)
> +
>  #define

Re: [Intel-gfx] [PATCH 10/19] Move CONTEXT_VALID_BIT check

[Niranjana Vishwanathapura]

On Mon, Aug 30, 2021 at 02:09:57PM +0200, Maarten Lankhorst wrote:

Signed-off-by: Maarten Lankhorst 
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c 
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 1f07ac4e0672..df81a0dc481e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -52,8 +52,6 @@ static int __engine_unpark(struct intel_wakeref *wf)
/* Discard stale context state from across idling */
ce = engine->kernel_context;
if (ce) {
-   GEM_BUG_ON(test_bit(CONTEXT_VALID_BIT, &ce->flags));
-
/* Flush all pending HW writes before we touch the context */
while (unlikely(intel_context_inflight(ce)))
intel_engine_flush_submission(engine);
@@ -68,6 +66,9 @@ static int __engine_unpark(struct intel_wakeref *wf)
 ce->timeline->seqno,
 READ_ONCE(*ce->timeline->hwsp_seqno),
 ce->ring->emit);
+
+   GEM_BUG_ON(test_bit(CONTEXT_VALID_BIT, &ce->flags));
+


Looks good to me.
Reviewed-by: Niranjana Vishwanathapura 


GEM_BUG_ON(ce->timeline->seqno !=
   READ_ONCE(*ce->timeline->hwsp_seqno));
}
--
2.32.0

Re: [Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay

[Manna, Animesh]

> -Original Message-
> From: Souza, Jose 
> Sent: Thursday, September 9, 2021 1:02 AM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong ; Nikula, Jani
> ; Kahola, Mika ; Navare,
> Manasi D 
> Subject: Re: [Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and
> compute config for panel replay
> 
> On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> > As panel replay feature similar to PSR feature of EDP panel, so
> > currently utilized existing psr framework for panel replay.
> >
> > Signed-off-by: Animesh Manna 
> > ---
> >  .../drm/i915/display/intel_display_types.h|  4 ++
> >  drivers/gpu/drm/i915/display/intel_dp.c   | 47 +++
> >  drivers/gpu/drm/i915/display/intel_psr.c  | 43 +
> >  drivers/gpu/drm/i915/display/intel_psr.h  |  3 ++
> >  include/drm/drm_dp_helper.h   |  3 ++
> >  5 files changed, 91 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index c7bcf9183447..6ca9fabb9333 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1066,6 +1066,7 @@ struct intel_crtc_state {
> > bool req_psr2_sdp_prior_scanline;
> > u32 dc3co_exitline;
> > u16 su_y_granularity;
> > +   bool has_panel_replay;
> >
> > /*
> >  * Frequence the dpll for the port should run at. Differs from the
> > @@ -1526,6 +1527,8 @@ struct intel_psr {
> > bool irq_aux_error;
> > u16 su_w_granularity;
> > u16 su_y_granularity;
> > +   bool sink_pr_support;
> > +   bool pr_enabled;
> 
> Instead of all the above we could have a function that checks if displayPort 
> is
> eDP or not, to know if is PSR or PR.
> sink_support and all the others should be shared for PSR and PR.

To get sink capability for panel replay dpcd address 0xb0 is read by the 
source. I feel PSR is using different dpcd address ...rt?
DP 2.0 display only support panel replay ... maybe need to add a check for DP 
2.0 also here before reading about panel replay capability or I am missing 
anything.

Regards,
Animesh 
> 
> > u32 dc3co_exitline;
> > u32 dc3co_exit_delay;
> > struct delayed_work dc3co_work;
> > @@ -1552,6 +1555,7 @@ struct intel_dp {
> > u8
> lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
> > u8 fec_capable;
> > u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
> > +   u8 pr_dpcd;
> 
> Used once why cache it?
> 
> > /* source rates */
> > int num_source_rates;
> > const int *source_rates;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index d28bd8c4a8a5..90c708548811 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1560,12 +1560,22 @@ static void
> intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >
> > -   /*
> > -* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > -* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > -* Colorimetry Format indication.
> > -*/
> > -   vsc->revision = 0x5;
> > +   if (crtc_state->has_panel_replay) {
> > +   /*
> > +* Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> > +* VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> > +* Encoding/Colorimetry Format indication.
> > +*/
> > +   vsc->revision = 0x7;
> > +   } else {
> > +   /*
> > +* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > +* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > +* Colorimetry Format indication.
> > +*/
> > +   vsc->revision = 0x5;
> > +   }
> > +
> > vsc->length = 0x13;
> >
> > /* DP 1.4a spec, Table 2-120 */
> > @@ -1674,6 +1684,22 @@ void intel_dp_compute_psr_vsc_sdp(struct
> intel_dp *intel_dp,
> > vsc->revision = 0x4;
> > vsc->length = 0xe;
> > }
> > +   } else if (intel_dp->psr.pr_enabled) {
> > +   if (intel_dp->psr.colorimetry_support &&
> > +   intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> > +   /* [PR, +Colorimetry] */
> > +   intel_dp_compute_vsc_colorimetry(crtc_state,
> conn_state,
> > +vsc);
> > +   } else {
> > +   /*
> > +* [PR, -Colorimetry]
> > +* Prepare VSC Header for SU as per DP 2.0 spec, Table
> 2-223
> > +* VSC SDP supporting 3D stereo + PR (applies to eDP
> v1.3 or
> > +* higher).
> > +  

Re: [Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay

[Souza, Jose]

On Thu, 2021-09-09 at 01:20 +0530, Manna, Animesh wrote:
> 
> > -Original Message-
> > From: Souza, Jose 
> > Sent: Thursday, September 9, 2021 1:02 AM
> > To: Manna, Animesh ; intel-
> > g...@lists.freedesktop.org
> > Cc: Mun, Gwan-gyeong ; Nikula, Jani
> > ; Kahola, Mika ; Navare,
> > Manasi D 
> > Subject: Re: [Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and
> > compute config for panel replay
> > 
> > On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> > > As panel replay feature similar to PSR feature of EDP panel, so
> > > currently utilized existing psr framework for panel replay.
> > > 
> > > Signed-off-by: Animesh Manna 
> > > ---
> > >  .../drm/i915/display/intel_display_types.h|  4 ++
> > >  drivers/gpu/drm/i915/display/intel_dp.c   | 47 +++
> > >  drivers/gpu/drm/i915/display/intel_psr.c  | 43 +
> > >  drivers/gpu/drm/i915/display/intel_psr.h  |  3 ++
> > >  include/drm/drm_dp_helper.h   |  3 ++
> > >  5 files changed, 91 insertions(+), 9 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index c7bcf9183447..6ca9fabb9333 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1066,6 +1066,7 @@ struct intel_crtc_state {
> > >   bool req_psr2_sdp_prior_scanline;
> > >   u32 dc3co_exitline;
> > >   u16 su_y_granularity;
> > > + bool has_panel_replay;
> > > 
> > >   /*
> > >* Frequence the dpll for the port should run at. Differs from the
> > > @@ -1526,6 +1527,8 @@ struct intel_psr {
> > >   bool irq_aux_error;
> > >   u16 su_w_granularity;
> > >   u16 su_y_granularity;
> > > + bool sink_pr_support;
> > > + bool pr_enabled;
> > 
> > Instead of all the above we could have a function that checks if 
> > displayPort is
> > eDP or not, to know if is PSR or PR.
> > sink_support and all the others should be shared for PSR and PR.
> 
> To get sink capability for panel replay dpcd address 0xb0 is read by the 
> source. I feel PSR is using different dpcd address ...rt?
> DP 2.0 display only support panel replay ... maybe need to add a check for DP 
> 2.0 also here before reading about panel replay capability or I am missing 
> anything.

I mean in the function that we check if sink supports PSR we could check if is 
DP 2.0 and if panel replay is supported and set sink_support to true.

From there we don't need those additional bools, if is eDP we know that PSR is 
supported if is DisplayPort we know that is panel replay.

> 
> Regards,
> Animesh 
> > 
> > >   u32 dc3co_exitline;
> > >   u32 dc3co_exit_delay;
> > >   struct delayed_work dc3co_work;
> > > @@ -1552,6 +1555,7 @@ struct intel_dp {
> > >   u8
> > lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
> > >   u8 fec_capable;
> > >   u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
> > > + u8 pr_dpcd;
> > 
> > Used once why cache it?
> > 
> > >   /* source rates */
> > >   int num_source_rates;
> > >   const int *source_rates;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index d28bd8c4a8a5..90c708548811 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -1560,12 +1560,22 @@ static void
> > intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> > >   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > >   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > 
> > > - /*
> > > -  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > > -  * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > > -  * Colorimetry Format indication.
> > > -  */
> > > - vsc->revision = 0x5;
> > > + if (crtc_state->has_panel_replay) {
> > > + /*
> > > +  * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> > > +  * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> > > +  * Encoding/Colorimetry Format indication.
> > > +  */
> > > + vsc->revision = 0x7;
> > > + } else {
> > > + /*
> > > +  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > > +  * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > > +  * Colorimetry Format indication.
> > > +  */
> > > + vsc->revision = 0x5;
> > > + }
> > > +
> > >   vsc->length = 0x13;
> > > 
> > >   /* DP 1.4a spec, Table 2-120 */
> > > @@ -1674,6 +1684,22 @@ void intel_dp_compute_psr_vsc_sdp(struct
> > intel_dp *intel_dp,
> > >   vsc->revision = 0x4;
> > >   vsc->length = 0xe;
> > >   }
> > > + } else if (intel_dp->psr.pr_enabled) {
> > > + if (intel_dp->psr.colorimetry_support &&
> > > + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> > > + /* [PR,