Re: [Intel-gfx] [PATCH 1/3] drm: use the lookup lock in drm_is_current_master
On Tue, Jul 27, 2021 at 04:37:22PM +0200, Peter Zijlstra wrote:
> On Thu, Jul 22, 2021 at 12:38:10PM +0200, Daniel Vetter wrote:
> > On Thu, Jul 22, 2021 at 05:29:27PM +0800, Desmond Cheong Zhi Xi wrote:
> > > Inside drm_is_current_master, using the outer drm_device.master_mutex
> > > to protect reads of drm_file.master makes the function prone to creating
> > > lock hierarchy inversions. Instead, we can use the
> > > drm_file.master_lookup_lock that sits at the bottom of the lock
> > > hierarchy.
> > >
> > > Reported-by: Daniel Vetter
> > > Signed-off-by: Desmond Cheong Zhi Xi
> > > ---
> > > drivers/gpu/drm/drm_auth.c | 9 +
> > > 1 file changed, 5 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c
> > > index f00354bec3fb..9c24b8cc8e36 100644
> > > --- a/drivers/gpu/drm/drm_auth.c
> > > +++ b/drivers/gpu/drm/drm_auth.c
> > > @@ -63,8 +63,9 @@
> > >
> > > static bool drm_is_current_master_locked(struct drm_file *fpriv)
> > > {
> > > - lockdep_assert_held_once(&fpriv->minor->dev->master_mutex);
> > > -
> > > + /* Either drm_device.master_mutex or drm_file.master_lookup_lock
> > > + * should be held here.
> > > + */
> >
> > Disappointing that lockdep can't check or conditions for us, a
> > lockdep_assert_held_either would be really neat in some cases.
> >
> > Adding lockdep folks, maybe they have ideas.
>
> #ifdef CONFIG_LOCKDEP
> WARN_ON_ONCE(debug_locks && !(lockdep_is_held(&drm_device.master_mutex)
> ||
>
> lockdep_is_held(&drm_file.master_lookup_lock)));
> #endif
>
> doesn't exactly roll off the tongue, but should do as you want I
> suppose.
>
> Would something like:
>
> #define lockdep_assert(cond) WARN_ON_ONCE(debug_locks && !(cond))
>
> Such that we can write:
>
> lockdep_assert(lockdep_is_held(&drm_device.master_mutex) ||
> lockdep_is_held(&drm_file.master_lookup_lock));
>
> make it better ?
Yeah I think that's pretty tidy and flexible.
Desmond, can you pls give this a shot with Peter's patch below?
-Daniel
>
> ---
> Subject: locking/lockdep: Provide lockdep_assert{,_once}() helpers
>
> Extract lockdep_assert{,_once}() helpers to more easily write composite
> assertions like, for example:
>
> lockdep_assert(lockdep_is_held(&drm_device.master_mutex) ||
> lockdep_is_held(&drm_file.master_lookup_lock));
>
> Signed-off-by: Peter Zijlstra (Intel)
> ---
> diff --git a/include/linux/lockdep.h b/include/linux/lockdep.h
> index 5cf387813754..0da67341c1fb 100644
> --- a/include/linux/lockdep.h
> +++ b/include/linux/lockdep.h
> @@ -306,31 +306,29 @@ extern void lock_unpin_lock(struct lockdep_map *lock,
> struct pin_cookie);
>
> #define lockdep_depth(tsk) (debug_locks ? (tsk)->lockdep_depth : 0)
>
> -#define lockdep_assert_held(l) do {
> \
> - WARN_ON(debug_locks && \
> - lockdep_is_held(l) == LOCK_STATE_NOT_HELD); \
> - } while (0)
> +#define lockdep_assert(cond) \
> + do { WARN_ON(debug_locks && !(cond)); } while (0)
>
> -#define lockdep_assert_not_held(l) do {\
> - WARN_ON(debug_locks && \
> - lockdep_is_held(l) == LOCK_STATE_HELD); \
> - } while (0)
> +#define lockdep_assert_once(cond)\
> + do { WARN_ON_ONCE(debug_locks && !(cond)); } while (0)
>
> -#define lockdep_assert_held_write(l) do {\
> - WARN_ON(debug_locks && !lockdep_is_held_type(l, 0));\
> - } while (0)
> +#define lockdep_assert_held(l) \
> + lockdep_assert(lockdep_is_held(l) != LOCK_STAT_NOT_HELD)
>
> -#define lockdep_assert_held_read(l) do {\
> - WARN_ON(debug_locks && !lockdep_is_held_type(l, 1));\
> - } while (0)
> +#define lockdep_assert_not_held(l) \
> + lockdep_assert(lockdep_is_held(l) != LOCK_STATE_HELD)
>
> -#define lockdep_assert_held_once(l) do {\
> - WARN_ON_ONCE(debug_locks && !lockdep_is_held(l)); \
> - } while (0)
> +#define lockdep_assert_held_write(l) \
> + lockdep_assert(lockdep_is_held_type(l, 0))
>
> -#define lockdep_assert_none_held_once() do {
> \
> - WARN_ON_ONCE(debug_locks && current->lockdep_depth);\
> - } while (0)
> +#define lockdep_assert_held_read(l) \
> + lockdep_assert(lockdep_is_held_type(l, 1))
> +
> +#define lockdep_assert_held_once(l) \
> + lockdep_assert_once(lockdep_is_held(l) != LOCK_STAT_NOT_HELD)
> +
> +#define lockdep_assert_none_held_once() \
> + lockdep_assert_once(!current->lockdep_depth)
>
> #define lockdep_recursing(tsk) ((tsk)->lockdep_recursion)
>
> @@ -407,6 +405,9 @@ extern int lock_is_h
Re: [Intel-gfx] refactor the i915 GVT support
On Wed, Jul 28, 2021 at 02:59:25PM -0300, Jason Gunthorpe wrote: > On Wed, Jul 28, 2021 at 01:38:58PM +, Wang, Zhi A wrote: > > > I guess those APIs you were talking about are KVM-only. For other > > hypervisors, e.g. Xen, ARCN cannot use the APIs you mentioned. Not > > sure if you have already noticed that VFIO is KVM-only right now. > > There is very little hard connection between VFIO and KVM, so no, I > don't think that is completely true. The only connection is the SET_KVM notifier as far as I can tell. Which is used by a total of two drivers, including i915/gvt. That being said gvt does not only use vfio, but also does quite a few direct cals to KVM. > In an event, an in-tree version of other hypervisor support for GVT > needs to go through enabling VFIO support so that the existing API > multiplexers we have can be used properly, not adding a shim layer > trying to recreate VFIO inside a GPU driver. Yes. And if we go back to actually looking at the series a lot of it just removes entirely pointless indirect calls that go to generic code and not even the kvm code, or questionable data structure designs. If we were to support another upstream hypervisor we'd just need to union a few fields in struct intel_gpu and maybe introduce a few methods. Preferably in a way that avoids expensive indirect calls in the fast path. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 02/14] vfio/mbochs: Fix missing error unwind of mbochs_used_mbytes
Looks good, Reviewed-by: Christoph Hellwig ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 04/14] vfio: Provide better generic support for open/release vfio_device_ops
> + device->open_count++;
> + if (device->open_count == 1 && device->ops->open_device) {
I would have written this as
if (++device->open_count == 1 && device->ops->open_device) {
to make the pattern more clear, but that is just a minor nitpick.
Otherwise looks good:
Reviewed-by: Christoph Hellwig
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[Intel-gfx] ✗ Fi.CI.IGT: failure for Fix gem_ctx_persistence failures with GuC submission
== Series Details ==
Series: Fix gem_ctx_persistence failures with GuC submission
URL : https://patchwork.freedesktop.org/series/93149/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10415_full -> Patchwork_20733_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20733_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20733_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20733_full:
### IGT changes ###
Possible regressions
* igt@i915_selftest@mock@requests:
- shard-kbl: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-kbl7/igt@i915_selftest@m...@requests.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20733/shard-kbl3/igt@i915_selftest@m...@requests.html
- shard-tglb: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-tglb6/igt@i915_selftest@m...@requests.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20733/shard-tglb3/igt@i915_selftest@m...@requests.html
- shard-apl: [PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-apl6/igt@i915_selftest@m...@requests.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20733/shard-apl8/igt@i915_selftest@m...@requests.html
- shard-glk: [PASS][7] -> [INCOMPLETE][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-glk3/igt@i915_selftest@m...@requests.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20733/shard-glk6/igt@i915_selftest@m...@requests.html
- shard-snb: NOTRUN -> [INCOMPLETE][9]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20733/shard-snb6/igt@i915_selftest@m...@requests.html
- shard-iclb: [PASS][10] -> [INCOMPLETE][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-iclb4/igt@i915_selftest@m...@requests.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20733/shard-iclb6/igt@i915_selftest@m...@requests.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@mock@requests:
- {shard-rkl}:[PASS][12] -> [INCOMPLETE][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-2/igt@i915_selftest@m...@requests.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20733/shard-rkl-1/igt@i915_selftest@m...@requests.html
Known issues
Here are the changes found in Patchwork_20733_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@display-3x:
- shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271]) +39 similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20733/shard-glk6/igt@feature_discov...@display-3x.html
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][15] ([i915#3002])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20733/shard-kbl7/igt@gem_cre...@create-massive.html
* igt@gem_ctx_persistence@smoketest:
- shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1099]) +4
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20733/shard-snb2/igt@gem_ctx_persiste...@smoketest.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#2842]) +1 similar
issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20733/shard-iclb4/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-glk: [PASS][19] -> [FAIL][20] ([i915#2842])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-glk9/igt@gem_exec_fair@basic-n...@rcs0.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20733/shard-glk4/igt@gem_exec_fair@basic-n...@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: NOTRUN -> [FAIL][21] ([i915#2842])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20733/shard-apl6/igt@gem_exec_fair@basic-n...@vcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: NOTRUN -> [FAIL][22] ([i915#2842])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20733/shard-iclb1/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb:
Re: [Intel-gfx] refactor the i915 GVT support
On Thu, Jul 29, 2021 at 09:20:22AM +0200, Christoph Hellwig wrote: > On Wed, Jul 28, 2021 at 02:59:25PM -0300, Jason Gunthorpe wrote: > > On Wed, Jul 28, 2021 at 01:38:58PM +, Wang, Zhi A wrote: > > > > > I guess those APIs you were talking about are KVM-only. For other > > > hypervisors, e.g. Xen, ARCN cannot use the APIs you mentioned. Not > > > sure if you have already noticed that VFIO is KVM-only right now. > > > > There is very little hard connection between VFIO and KVM, so no, I > > don't think that is completely true. > > The only connection is the SET_KVM notifier as far as I can tell. > Which is used by a total of two drivers, including i915/gvt. That > being said gvt does not only use vfio, but also does quite a few > direct cals to KVM. > > > In an event, an in-tree version of other hypervisor support for GVT > > needs to go through enabling VFIO support so that the existing API > > multiplexers we have can be used properly, not adding a shim layer > > trying to recreate VFIO inside a GPU driver. > > Yes. And if we go back to actually looking at the series a lot of > it just removes entirely pointless indirect calls that go to generic > code and not even the kvm code, or questionable data structure designs. > If we were to support another upstream hypervisor we'd just need to > union a few fields in struct intel_gpu and maybe introduce a few > methods. Preferably in a way that avoids expensive indirect calls > in the fast path. fwiw I concur with the direction of this series. gvt landed 5 years ago, that should have been plenty of time to merge at least one of the other backends that float around. If it didn't happen in 5 years it aint suddenly happening in the next few, and the abstraction layer should be sunset. Also yes structuring it more as a helper layer with some unions/subclassing than full blown backend abstractor layer would be a good idea too I guess (it usually is the right thing to do). -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 09/14] vfio/pci: Change vfio_pci_try_bus_reset() to use the dev_set
> +/*
> + * vfio-core considers a group to be viable and will create a vfio_device
> even
> + * if some devices are bound to drivers like pci-stub or pcieport. Here we
> + * require all PCI devices to be inside our dev_set since that ensures they
> stay
> + * put and that every driver controlling the device can co-ordinate with the
> + * device reset.
> + */
> +static struct pci_dev *vfio_pci_find_reset_target(struct vfio_pci_device
> *vdev)
> +{
> + struct vfio_device_set *dev_set = vdev->vdev.dev_set;
> + struct vfio_pci_device *cur;
> + bool needs_reset = false;
> +
> + /* No VFIO device has an open device FD */
s/has an/can have/ ?
Or maybe:
/* No device in the set can have an open device FD */
Otherwise looks good:
Reviewed-by: Christoph Hellwig
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Re: [Intel-gfx] [PATCH] drm/i915: Fix the 12 BPC bits for PIPE_MISC reg
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Monday, July 19, 2021 9:55 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Nikula, Jani
> ;
> ville.syrj...@linux.intel.com
> Subject: [PATCH] drm/i915: Fix the 12 BPC bits for PIPE_MISC reg
Append display in header.
>
> From: Ankit Nautiyal
>
> Till DISPLAY12 the PIPE_MISC bits 5-7 are used to set the Dithering BPC, with
> valid
> values of 6, 8, 10 BPC.
> For ADLP+ these bits are used to set the PORT OUTPUT BPC, with valid values
> of: 6,
> 8, 10, 12 BPC, and need to be programmed whether dithering is enabled or not.
>
> This patch:
> -corrects the bits 5-7 for PIPE MISC register for 12 BPC.
> -renames the bits and mask to have generic names for these bits for dithering
> bpc
> and port output bpc.
>
I guess we have 2 issues here. One is wrong definition of 12bpc for dither
which seems not
even there in hw before display 12 platforms. Other one is the port output bpc
fix.
Would suggest to split this patch in 2 addressing these issues separately. Send
1st patch as
Fixme (with commit it is fixing), and other as normal feature addition.
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 23 +--
> drivers/gpu/drm/i915/i915_reg.h | 16 +++-
> 2 files changed, 24 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 65ddb6c..dc4869f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5760,16 +5760,18 @@ static void bdw_set_pipemisc(const struct
> intel_crtc_state *crtc_state)
>
> switch (crtc_state->pipe_bpp) {
> case 18:
> - val |= PIPEMISC_DITHER_6_BPC;
> + val |= PIPEMISC_6_BPC;
> break;
> case 24:
> - val |= PIPEMISC_DITHER_8_BPC;
> + val |= PIPEMISC_8_BPC;
> break;
> case 30:
> - val |= PIPEMISC_DITHER_10_BPC;
> + val |= PIPEMISC_10_BPC;
> break;
> case 36:
> - val |= PIPEMISC_DITHER_12_BPC;
> + /* Port output 12BPC defined for ADLP+ */
> + if (DISPLAY_VER(dev_priv) > 12)
> + val |= PIPEMISC_12_BPC_ADLP;
We have 12 bpc in TRANS_DDI_FUNC_CTRL for BDW+, so what happens to dithering
if we have 12bpc enabled. We should confirm this.
> break;
> default:
> MISSING_CASE(crtc_state->pipe_bpp);
> @@ -5822,15 +5824,16 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
>
> tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
>
> - switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
> - case PIPEMISC_DITHER_6_BPC:
> + switch (tmp & PIPEMISC_BPC_MASK) {
> + case PIPEMISC_6_BPC:
> return 18;
> - case PIPEMISC_DITHER_8_BPC:
> + case PIPEMISC_8_BPC:
> return 24;
> - case PIPEMISC_DITHER_10_BPC:
> + case PIPEMISC_10_BPC:
> return 30;
> - case PIPEMISC_DITHER_12_BPC:
> - return 36;
> + /* PORT OUTPUT 12 BPC defined for ADLP+ */
> + case PIPEMISC_12_BPC_ADLP:
> + return DISPLAY_VER(dev_priv) > 12 ? 36 : 0;
Returning 0 seems odd, as this will give bpp as 0 which is not right.
We should throw a WARN since getting 12bpc set in pipe_misc is not expected (as
not supported)
on pre gen12.
To me there is some discrepancy here, as transcoder output supports 12bpc so
dithering
also should have that. If not we have a issue with DSI since it tries to get
pipe_bpp from
bdw_get_pipemisc. Please check this out once.
> default:
> MISSING_CASE(tmp);
> return 0;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 943fe48..963d87d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6166,11 +6166,17 @@ enum {
> #define PIPEMISC_HDR_MODE_PRECISION(1 << 23) /* icl+ */
> #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
> #define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
> -#define PIPEMISC_DITHER_BPC_MASK (7 << 5)
> -#define PIPEMISC_DITHER_8_BPC (0 << 5)
> -#define PIPEMISC_DITHER_10_BPC (1 << 5)
> -#define PIPEMISC_DITHER_6_BPC (2 << 5)
> -#define PIPEMISC_DITHER_12_BPC (3 << 5)
> +/*
> + * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
> + * valid values of: 6, 8, 10 BPC.
> + * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
> + * 6, 8, 10, 12 BPC.
> + */
> +#define PIPEMISC_BPC_MASK (7 << 5)
> +#define PIPEMISC_8_BPC (0 << 5)
> +#define PIPEMISC_10_BPC(1 << 5)
> +#define PIPEMISC_6_BPC (2 << 5)
> +#define PIPEMISC_12_BPC_ADLP (4 << 5) /* adlp+ */
> #define PIPEM
[Intel-gfx] ✓ Fi.CI.IGT: success for Provide core infrastructure for managing open/release (rev7)
== Series Details == Series: Provide core infrastructure for managing open/release (rev7) URL : https://patchwork.freedesktop.org/series/92556/ State : success == Summary == CI Bug Log - changes from CI_DRM_10415_full -> Patchwork_20734_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_20734_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-kbl: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20734/shard-kbl7/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@smoketest: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20734/shard-snb2/igt@gem_ctx_persiste...@smoketest.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][3] -> [FAIL][4] ([i915#2842]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20734/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: NOTRUN -> [FAIL][5] ([i915#2842]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20734/shard-kbl6/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20734/shard-iclb1/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-tglb5/igt@gem_exec_fair@basic-p...@bcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20734/shard-tglb5/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [PASS][9] -> [SKIP][10] ([fdo#109271]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-kbl1/igt@gem_exec_fair@basic-p...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20734/shard-kbl4/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-kbl1/igt@gem_exec_fair@basic-p...@vecs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20734/shard-kbl4/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][13] -> [SKIP][14] ([i915#2190]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-tglb7/igt@gem_huc_c...@huc-copy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20734/shard-tglb6/igt@gem_huc_c...@huc-copy.html - shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20734/shard-apl2/igt@gem_huc_c...@huc-copy.html - shard-iclb: NOTRUN -> [SKIP][16] ([i915#2190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20734/shard-iclb1/igt@gem_huc_c...@huc-copy.html * igt@gem_mmap_gtt@cpuset-big-copy-odd: - shard-glk: [PASS][17] -> [FAIL][18] ([i915#1888] / [i915#307]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-glk4/igt@gem_mmap_...@cpuset-big-copy-odd.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20734/shard-glk9/igt@gem_mmap_...@cpuset-big-copy-odd.html * igt@gem_pread@exhaustion: - shard-snb: NOTRUN -> [WARN][19] ([i915#2658]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20734/shard-snb7/igt@gem_pr...@exhaustion.html * igt@gem_pwrite@basic-exhaustion: - shard-kbl: NOTRUN -> [WARN][20] ([i915#2658]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20734/shard-kbl6/igt@gem_pwr...@basic-exhaustion.html * igt@gem_render_copy@linear-to-vebox-y-tiled: - shard-iclb: NOTRUN -> [SKIP][21] ([i915#768]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20734/shard-iclb5/igt@gem_render_c...@linear-to-vebox-y-tiled.html * igt@gem_userptr_blits@create-destroy-unsync: - shard-iclb: NOTRUN -> [SKIP][22] ([i915#3297]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20734/shard-iclb1/igt@gem_userptr_bl...@create-destroy-unsync.html * igt@i915_pm_rpm@gem-execbuf: - shard-iclb: NOTRUN -> [SKIP][23] ([i915#579]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20734/shard-iclb1/igt@i9
Re: [Intel-gfx] refactor the i915 GVT support
On 7/28/2021 8:59 PM, Jason Gunthorpe wrote: > On Wed, Jul 28, 2021 at 01:38:58PM +, Wang, Zhi A wrote: > >> I guess those APIs you were talking about are KVM-only. For other >> hypervisors, e.g. Xen, ARCN cannot use the APIs you mentioned. Not >> sure if you have already noticed that VFIO is KVM-only right now. > There is very little hard connection between VFIO and KVM, so no, I > don't think that is completely true. > > In an event, an in-tree version of other hypervisor support for GVT > needs to go through enabling VFIO support so that the existing API > multiplexers we have can be used properly, not adding a shim layer > trying to recreate VFIO inside a GPU driver. We were delivering the presentation of GVT-g in Xen summit 2018 and we were thinking and talking about supporting VFIO in Xen during the presentation (the video can be found from Youtube). But we didn't see any motiviation from the Xen community to adopt it. If people take a look into the code in QEMU, in the PCI-passthrough part, Xen is actually not using VFIO even nowadays. We would be glad to see someone can influence on that part, especically making all the in-kernel hypervisor to use VFIO in PCI-passthrough and supporting mdev. That would be a huge benefit for all the users. >> GVT-g is designed for many hypervisors not only KVM. In the design, >> we implemented an abstraction layer for different hypervisors. You >> can check the link in the previous email which has an example of how >> the MPT module "xengt" supports GVT-g running under Xen. For >> example, injecting a msi in VFIO/KVM is via playing with >> eventfd. But in Xen, we need to issue a hypercall from Dom0. > This is obviously bad design, Xen should plug into the standardized > eventfd scheme as well and trigger its hypercall this way. Then it can > integrate with the existing VFIO interrupt abstraction infrastructure. > >> others, like querying mappings between GFN and HFN. > This should be done through VFIO containers, there is nothing KVM > specific there. > >> As you can see, to survive from this situation, we have to rely on >> an abstraction layer so that we can prevent introducing coding >> blocks like in the core logic: > No, you have to fix the abstractions we already have to support the > matrix of things you care about. If this can't be done then maybe we > can add new abstractions, but abstractions like this absoultely should > not be done inside drivers. > > Jason That's a good point and we were actually thinking about this before and I believe that's the correct direction. But just like the situation mentioned above, it would be nice if people can really put a great influence on all in-kernel hypervisors to use VFIO which can really benefit all the users. For now, we are just going to take christoph's patches. Zhi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/7] lib/i915/gem_mman: add FIXED mmap mode
On Wed, Jul 28, 2021 at 06:53:50PM -0700, Dixit, Ashutosh wrote: > On Tue, 27 Jul 2021 23:08:40 -0700, Petri Latvala wrote: > > > > On Tue, Jul 27, 2021 at 07:01:24PM -0700, Dixit, Ashutosh wrote: > > > On Mon, 26 Jul 2021 05:03:04 -0700, Matthew Auld wrote: > > > > > > > > diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c > > > > index 4b4f2114..e2514f0c 100644 > > > > --- a/lib/i915/gem_mman.c > > > > +++ b/lib/i915/gem_mman.c > > > > @@ -497,6 +497,43 @@ void *gem_mmap_offset__cpu(int fd, uint32_t > > > > handle, uint64_t offset, > > > > return ptr; > > > > } > > > > > > > > +#define LOCAL_I915_MMAP_OFFSET_FIXED 4 > > > > > > Cc: @Petri Latvala > > > > > > This use of LOCAL declarations is more related to the methodology we > > > follow > > > in IGT rather than this patch. We have seen in the past that such LOCAL's > > > linger on in the code for months and years till someone decides to clean > > > them so the question is can we prevent these LOCAL's from getting > > > introduced in the first place. > > > > > > One reason for these is that we sync IGT headers with drm-next whereas IGT > > > is used to test drm-tip. So the delta between the two results in such > > > LOCAL's as in this case. > > > > > > My proposal is that even if we don't start sync'ing IGT headers with > > > drm-tip (instead of drm-next) we allow direct modification of the headers > > > when needed to avoid introducing such LOCAL's. So in the above case we > > > would add: > > > > > > #define I915_MMAP_OFFSET_FIXED 4 > > > > > > to i915_drm.h as part of this patch and then just use > > > I915_MMAP_OFFSET_FIXED. If another sync happens from drm-next before this > > > #define has appeared there, the compile will break and whoever syncs will > > > need to add this again to i915_drm.h. > > > > I don't like that kind of a breakage at all. That enforces mandatory > > fixups to some poor developer working on unrelated code who doesn't > > necessarily know how to even fix it easily. > > > > Of course an argument can be made that it's an i915 token in an i915 > > header so it will be the i915 people doing it, but for a general case > > that's going to cause more harm than it solves problems, I feel. > > OK, let's not change anything with the headers we import for now. > > > > What do people think about a scheme such as this? The other, perhaps > > > better, option of course is to sync the headers directly with drm-tip > > > (whenever and as often as needed). But the goal in both cases is to avoid > > > LOCAL's, or other things like #ifndef's distributed throughout multiple > > > source files which we also do in such cases. A centralized internal header > > > to contain such declarations might not be so bad. Thanks. > > > > A separate manually written header for new tokens that are not yet in > > drm-next might be the least bad of all options. Although now that I've > > said it, the perfect world would have new tokens done like this: > > > > #ifndef I915_MMAP_OFFSET_FIXED > > #define I915_MMAP_OFFSET_FIXED 4 > > #else > > _Static_assert(I915_MMAP_OFFSET_FIXED == 4, "ABI broken, yikes"); > > #endif > > > > In a different language wrapping all that in a > > > > MAYBE_DECLARE(I915_MMAP_OFFSET_FIXED, 4) > > > > might be easier but with C preprocessor it's a bit more... involved. A > > separate build-time script to generate that header maybe? Such a > > script could also just completely omit the definition if header copies > > already introduce the token. > > IMO all this wouldn't do much more that what gcc already does. For example, > for this: > > #define I915_MMAP_OFFSET_FIXED 4 > #define I915_MMAP_OFFSET_FIXED 4 > > gcc silently ignores the second #define, whereas for: > > #define I915_MMAP_OFFSET_FIXED 4 > #define I915_MMAP_OFFSET_FIXED 5 > > gcc will warn that second I915_MMAP_OFFSET_FIXED is redefined. > > And gcc will error out on things like struct redeclaration. Ah that's good then! (For the record, C99 6.10.3 states this is even standard C behaviour) > > > Recap: > > > > 1) We have kernel headers copied into IGT to ensure it builds fine > > without latest-and-greatest headers installed on the system. > > > > 2) Copies are from drm-next to ensure the next person to copy the > > headers doesn't accidentally drop definitions that originate from a > > vendor-specific tree. (That same reason is also for why one shouldn't > > edit the headers manually) > > > > 3) To get to drm-next, the kernel code needs to be tested with IGT > > first, so we need new definitions to test that kernel code in some > > form. > > I guess it is possible to test with "Test-with:" and merge the kernel > changes first and the IGT changes later with the correct headers but maybe > it's inconvenient? But don't we merge the kernel changes before IGT? Merge rules for kernel vs. userspace is like that, yes. But IGT doesn't count as userspace for those rules and merging order can be more relaxed. > > > 4) LOCAL_* definitions that are cleaned up later
Re: [Intel-gfx] [PATCH i-g-t v2 04/11] lib/i915/gem_mman: add fixed mode to gem_mmap__cpu
On 29/07/2021 00:07, Dixit, Ashutosh wrote:
On Wed, 28 Jul 2021 03:30:34 -0700, Matthew Auld wrote:
diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 337d28fb..6f5e6d72 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -434,7 +434,13 @@ void *gem_mmap__device_coherent(int fd, uint32_t handle,
uint64_t offset,
*/
void *__gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t
size, unsigned prot)
{
- return __gem_mmap(fd, handle, offset, size, prot, 0);
+ void *ptr;
+
+ ptr = __gem_mmap(fd, handle, offset, size, prot, 0);
+ if (!ptr)
+ ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot);
+
+ return ptr;
What about __gem_mmap__wc? Also shouldn't we just fix the __gem_mmap_offset
fallback in __gem_mmap and that will take care of both __gem_mmap__cpu and
__gem_mmap__wc?
For gem_mmap__wc it felt like slightly too much lying, since on discrete
smem-only buffers are always wb, and so the __wc here is not what the
user gets with the new FIXED mode. gem_mmap__device_coherent() I think
matches this new behaviour well, where we don't explicitly state what
the mapping type is, but instead just guarantee that the returned
mapping is device coherent. My rough thinking was to convert most users
of __wc over to __device_coherent(), at least in the tests that we care
about for discrete?
On the other hand if we are happy with the lie, I don't think anything
will break, and pretty much all testscases using mmap I think should
just magically work on discrete, and it does mean a less less work vs
converting to __device_coherent?
(I think it will actually also fix __gem_mmap__device_coherent and
__gem_mmap__cpu_coherent but maybe we can still have those patches in this
series especially if they save a couple of system calls).
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH rdma-next v3 0/3] SG fix together with update to RDMA umem
From: Leon Romanovsky Changelog: v3: * Rewrote to new API suggestion * Split for more patches v2: https://lore.kernel.org/lkml/cover.1626605893.git.leo...@nvidia.com * Changed implementation of first patch, based on our discussion with Christoph. https://lore.kernel.org/lkml/ynwavtt0qmqdx...@infradead.org/ v1: https://lore.kernel.org/lkml/cover.1624955710.git.leo...@nvidia.com/ * Fixed sg_page with a _dma_ API in the umem.c v0: https://lore.kernel.org/lkml/cover.1624361199.git.leo...@nvidia.com Maor Gottlieb (3): lib/scatterlist: Provide a dedicated function to support table append lib/scatterlist: Fix wrong update of orig_nents RDMA: Use the sg_table directly and remove the opencoded version from umem drivers/gpu/drm/drm_prime.c | 13 +- drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 11 +- drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 14 +- drivers/infiniband/core/umem.c | 56 +++--- drivers/infiniband/core/umem_dmabuf.c | 5 +- drivers/infiniband/hw/hns/hns_roce_db.c | 4 +- drivers/infiniband/hw/irdma/verbs.c | 2 +- drivers/infiniband/hw/mlx4/doorbell.c | 3 +- drivers/infiniband/hw/mlx4/mr.c | 4 +- drivers/infiniband/hw/mlx5/doorbell.c | 3 +- drivers/infiniband/hw/mlx5/mr.c | 3 +- drivers/infiniband/hw/qedr/verbs.c | 2 +- drivers/infiniband/sw/rdmavt/mr.c | 2 +- drivers/infiniband/sw/rxe/rxe_mr.c | 2 +- include/linux/scatterlist.h | 54 +- include/rdma/ib_umem.h | 11 +- include/rdma/ib_verbs.h | 28 +++ lib/scatterlist.c | 189 tools/testing/scatterlist/main.c| 38 ++-- 19 files changed, 275 insertions(+), 169 deletions(-) -- 2.31.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH rdma-next v3 1/3] lib/scatterlist: Provide a dedicated function to support table append
From: Maor Gottlieb
RDMA is the only in-kernel user that uses __sg_alloc_table_from_pages to
append pages dynamically. In the next patch. That mode will be extended
and that function will get more parameters. So separate it into a unique
function to make such change more clear.
Signed-off-by: Maor Gottlieb
Signed-off-by: Leon Romanovsky
---
drivers/gpu/drm/drm_prime.c | 13 ---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 11 +++---
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 14 +++-
drivers/infiniband/core/umem.c | 4 +--
include/linux/scatterlist.h | 39 ++---
lib/scatterlist.c | 36 ++-
tools/testing/scatterlist/main.c| 25 +
7 files changed, 90 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index 2a54f86856af..cf3278041f9c 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -807,8 +807,8 @@ struct sg_table *drm_prime_pages_to_sg(struct drm_device
*dev,
struct page **pages, unsigned int
nr_pages)
{
struct sg_table *sg;
- struct scatterlist *sge;
size_t max_segment = 0;
+ int err;
sg = kmalloc(sizeof(struct sg_table), GFP_KERNEL);
if (!sg)
@@ -818,13 +818,12 @@ struct sg_table *drm_prime_pages_to_sg(struct drm_device
*dev,
max_segment = dma_max_mapping_size(dev->dev);
if (max_segment == 0)
max_segment = UINT_MAX;
- sge = __sg_alloc_table_from_pages(sg, pages, nr_pages, 0,
- nr_pages << PAGE_SHIFT,
- max_segment,
- NULL, 0, GFP_KERNEL);
- if (IS_ERR(sge)) {
+ err = sg_alloc_table_from_pages_segment(sg, pages, nr_pages, 0,
+ nr_pages << PAGE_SHIFT,
+ max_segment, GFP_KERNEL);
+ if (err) {
kfree(sg);
- sg = ERR_CAST(sge);
+ sg = ERR_PTR(err);
}
return sg;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 7487bab11f0b..458f797a9e1e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -133,7 +133,6 @@ static int i915_gem_userptr_get_pages(struct
drm_i915_gem_object *obj)
unsigned int max_segment = i915_sg_segment_size();
struct sg_table *st;
unsigned int sg_page_sizes;
- struct scatterlist *sg;
struct page **pvec;
int ret;
@@ -153,13 +152,11 @@ static int i915_gem_userptr_get_pages(struct
drm_i915_gem_object *obj)
spin_unlock(&i915->mm.notifier_lock);
alloc_table:
- sg = __sg_alloc_table_from_pages(st, pvec, num_pages, 0,
-num_pages << PAGE_SHIFT, max_segment,
-NULL, 0, GFP_KERNEL);
- if (IS_ERR(sg)) {
- ret = PTR_ERR(sg);
+ ret = sg_alloc_table_from_pages_segment(st, pvec, num_pages, 0,
+ num_pages << PAGE_SHIFT,
+ max_segment, GFP_KERNEL);
+ if (ret)
goto err;
- }
ret = i915_gem_gtt_prepare_pages(obj, st);
if (ret) {
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
index 0488042fb287..fc372d2e52a1 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
@@ -363,7 +363,6 @@ static int vmw_ttm_map_dma(struct vmw_ttm_tt *vmw_tt)
int ret = 0;
static size_t sgl_size;
static size_t sgt_size;
- struct scatterlist *sg;
if (vmw_tt->mapped)
return 0;
@@ -386,15 +385,12 @@ static int vmw_ttm_map_dma(struct vmw_ttm_tt *vmw_tt)
if (unlikely(ret != 0))
return ret;
- sg = __sg_alloc_table_from_pages(&vmw_tt->sgt, vsgt->pages,
- vsgt->num_pages, 0,
- (unsigned long) vsgt->num_pages << PAGE_SHIFT,
- dma_get_max_seg_size(dev_priv->drm.dev),
- NULL, 0, GFP_KERNEL);
- if (IS_ERR(sg)) {
- ret = PTR_ERR(sg);
+ ret = sg_alloc_table_from_pages_segment(
+ &vmw_tt->sgt, vsgt->pages, vsgt->num_pages, 0,
+ (unsigned long)vsgt->num_pages << PAGE_SHIFT,
+ dma_get_max_seg_size(dev_priv->drm.dev), GFP_KERNEL);
+ if (ret)
goto out_sg_alloc_fail;
- }
if (vsgt->num_page
[Intel-gfx] [PATCH rdma-next v3 2/3] lib/scatterlist: Fix wrong update of orig_nents
From: Maor Gottlieb
orig_nents should represent the number of entries with pages,
but __sg_alloc_table_from_pages sets orig_nents as the number of
total entries in the table. This is wrong when the API is used for
dynamic allocation where not all the table entries are mapped with
pages. It wasn't observed until now, since RDMA umem who uses this
API in the dynamic form doesn't use orig_nents implicit or explicit
by the scatterlist APIs.
Fix it by changing the append API to track the SG append table
state and have an API to free the append table according to the
total number of entries in the table.
Now all APIs set orig_nents as number of enries with pages.
Fixes: 07da1223ec93 ("lib/scatterlist: Add support in dynamic allocation of SG
table from pages")
Signed-off-by: Maor Gottlieb
Signed-off-by: Leon Romanovsky
---
drivers/infiniband/core/umem.c | 34 ---
include/linux/scatterlist.h | 17 +++-
include/rdma/ib_umem.h | 1 +
lib/scatterlist.c| 161 +++
tools/testing/scatterlist/main.c | 45 +
5 files changed, 154 insertions(+), 104 deletions(-)
diff --git a/drivers/infiniband/core/umem.c b/drivers/infiniband/core/umem.c
index b741758e528f..42481e7a72e8 100644
--- a/drivers/infiniband/core/umem.c
+++ b/drivers/infiniband/core/umem.c
@@ -59,7 +59,7 @@ static void __ib_umem_release(struct ib_device *dev, struct
ib_umem *umem, int d
unpin_user_page_range_dirty_lock(sg_page(sg),
DIV_ROUND_UP(sg->length, PAGE_SIZE), make_dirty);
- sg_free_table(&umem->sg_head);
+ sg_free_append_table(&umem->sgt_append);
}
/**
@@ -155,8 +155,7 @@ struct ib_umem *ib_umem_get(struct ib_device *device,
unsigned long addr,
unsigned long dma_attr = 0;
struct mm_struct *mm;
unsigned long npages;
- int ret;
- struct scatterlist *sg = NULL;
+ int pinned, ret;
unsigned int gup_flags = FOLL_WRITE;
/*
@@ -216,28 +215,33 @@ struct ib_umem *ib_umem_get(struct ib_device *device,
unsigned long addr,
while (npages) {
cond_resched();
- ret = pin_user_pages_fast(cur_base,
+ pinned = pin_user_pages_fast(cur_base,
min_t(unsigned long, npages,
PAGE_SIZE /
sizeof(struct page *)),
gup_flags | FOLL_LONGTERM, page_list);
- if (ret < 0)
+ if (pinned < 0) {
+ ret = pinned;
goto umem_release;
+ }
- cur_base += ret * PAGE_SIZE;
- npages -= ret;
- sg = sg_alloc_append_table_from_pages(&umem->sg_head, page_list,
- ret, 0, ret << PAGE_SHIFT,
- ib_dma_max_seg_size(device), sg, npages,
- GFP_KERNEL);
- umem->sg_nents = umem->sg_head.nents;
- if (IS_ERR(sg)) {
- unpin_user_pages_dirty_lock(page_list, ret, 0);
- ret = PTR_ERR(sg);
+ cur_base += pinned * PAGE_SIZE;
+ npages -= pinned;
+ ret = sg_alloc_append_table_from_pages(
+ &umem->sgt_append, page_list, pinned, 0,
+ pinned << PAGE_SHIFT, ib_dma_max_seg_size(device),
+ npages, GFP_KERNEL);
+ umem->sg_nents = umem->sgt_append.sgt.nents;
+ if (ret) {
+ memcpy(&umem->sg_head.sgl, &umem->sgt_append.sgt,
+ sizeof(umem->sgt_append.sgt));
+ unpin_user_pages_dirty_lock(page_list, pinned, 0);
goto umem_release;
}
}
+ memcpy(&umem->sg_head.sgl, &umem->sgt_append.sgt,
+ sizeof(umem->sgt_append.sgt));
if (access & IB_ACCESS_RELAXED_ORDERING)
dma_attr |= DMA_ATTR_WEAK_ORDERING;
diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h
index 5c700f2a0d18..0c7aa5ccebfc 100644
--- a/include/linux/scatterlist.h
+++ b/include/linux/scatterlist.h
@@ -39,6 +39,12 @@ struct sg_table {
unsigned int orig_nents;/* original size of list */
};
+struct sg_append_table {
+ struct sg_table sgt;/* The scatter list table */
+ struct scatterlist *prv;/* last populated sge in the table */
+ unsigned int total_nents; /* Total entries in the table */
+};
+
/*
* Notes on SG table design.
*
@@ -282,14 +288,15 @@ typedef void (sg_free_fn)(struct scatterlist *, unsigned
int);
void __sg_free_table(struct sg_table *, unsigned int, unsigned int,
sg_free_fn *);
void sg_free_table(struct sg_table *);
+void sg_free_append_table(struct
[Intel-gfx] [PATCH rdma-next v3 3/3] RDMA: Use the sg_table directly and remove the opencoded version from umem
From: Maor Gottlieb
This allows using the normal sg_table APIs and makes all the code
cleaner. Remove sgt, nents and nmapd from ib_umem.
Signed-off-by: Maor Gottlieb
Signed-off-by: Leon Romanovsky
Signed-off-by: Jason Gunthorpe
---
drivers/infiniband/core/umem.c | 32 +
drivers/infiniband/core/umem_dmabuf.c | 5 ++--
drivers/infiniband/hw/hns/hns_roce_db.c | 4 ++--
drivers/infiniband/hw/irdma/verbs.c | 2 +-
drivers/infiniband/hw/mlx4/doorbell.c | 3 ++-
drivers/infiniband/hw/mlx4/mr.c | 4 ++--
drivers/infiniband/hw/mlx5/doorbell.c | 3 ++-
drivers/infiniband/hw/mlx5/mr.c | 3 ++-
drivers/infiniband/hw/qedr/verbs.c | 2 +-
drivers/infiniband/sw/rdmavt/mr.c | 2 +-
drivers/infiniband/sw/rxe/rxe_mr.c | 2 +-
include/rdma/ib_umem.h | 10
include/rdma/ib_verbs.h | 28 ++
13 files changed, 59 insertions(+), 41 deletions(-)
diff --git a/drivers/infiniband/core/umem.c b/drivers/infiniband/core/umem.c
index 42481e7a72e8..86d479772fbc 100644
--- a/drivers/infiniband/core/umem.c
+++ b/drivers/infiniband/core/umem.c
@@ -51,11 +51,11 @@ static void __ib_umem_release(struct ib_device *dev, struct
ib_umem *umem, int d
struct scatterlist *sg;
unsigned int i;
- if (umem->nmap > 0)
- ib_dma_unmap_sg(dev, umem->sg_head.sgl, umem->sg_nents,
- DMA_BIDIRECTIONAL);
+ if (dirty)
+ ib_dma_unmap_sgtable_attrs(dev, &umem->sgt_append.sgt,
+ DMA_BIDIRECTIONAL, 0);
- for_each_sg(umem->sg_head.sgl, sg, umem->sg_nents, i)
+ for_each_sgtable_sg(&umem->sgt_append.sgt, sg, i)
unpin_user_page_range_dirty_lock(sg_page(sg),
DIV_ROUND_UP(sg->length, PAGE_SIZE), make_dirty);
@@ -111,7 +111,7 @@ unsigned long ib_umem_find_best_pgsz(struct ib_umem *umem,
/* offset into first SGL */
pgoff = umem->address & ~PAGE_MASK;
- for_each_sg(umem->sg_head.sgl, sg, umem->nmap, i) {
+ for_each_sgtable_dma_sg(&umem->sgt_append.sgt, sg, i) {
/* Walk SGL and reduce max page size if VA/PA bits differ
* for any address.
*/
@@ -121,7 +121,7 @@ unsigned long ib_umem_find_best_pgsz(struct ib_umem *umem,
* the maximum possible page size as the low bits of the iova
* must be zero when starting the next chunk.
*/
- if (i != (umem->nmap - 1))
+ if (i != (umem->sgt_append.sgt.nents - 1))
mask |= va;
pgoff = 0;
}
@@ -231,30 +231,19 @@ struct ib_umem *ib_umem_get(struct ib_device *device,
unsigned long addr,
&umem->sgt_append, page_list, pinned, 0,
pinned << PAGE_SHIFT, ib_dma_max_seg_size(device),
npages, GFP_KERNEL);
- umem->sg_nents = umem->sgt_append.sgt.nents;
if (ret) {
- memcpy(&umem->sg_head.sgl, &umem->sgt_append.sgt,
- sizeof(umem->sgt_append.sgt));
unpin_user_pages_dirty_lock(page_list, pinned, 0);
goto umem_release;
}
}
- memcpy(&umem->sg_head.sgl, &umem->sgt_append.sgt,
- sizeof(umem->sgt_append.sgt));
if (access & IB_ACCESS_RELAXED_ORDERING)
dma_attr |= DMA_ATTR_WEAK_ORDERING;
- umem->nmap =
- ib_dma_map_sg_attrs(device, umem->sg_head.sgl, umem->sg_nents,
- DMA_BIDIRECTIONAL, dma_attr);
-
- if (!umem->nmap) {
- ret = -ENOMEM;
+ ret = ib_dma_map_sgtable_attrs(device, &umem->sgt_append.sgt,
+ DMA_BIDIRECTIONAL, dma_attr);
+ if (ret)
goto umem_release;
- }
-
- ret = 0;
goto out;
umem_release:
@@ -314,7 +303,8 @@ int ib_umem_copy_from(void *dst, struct ib_umem *umem,
size_t offset,
return -EINVAL;
}
- ret = sg_pcopy_to_buffer(umem->sg_head.sgl, umem->sg_nents, dst, length,
+ ret = sg_pcopy_to_buffer(umem->sgt_append.sgt.sgl,
+umem->sgt_append.sgt.orig_nents, dst, length,
offset + ib_umem_offset(umem));
if (ret < 0)
diff --git a/drivers/infiniband/core/umem_dmabuf.c
b/drivers/infiniband/core/umem_dmabuf.c
index c6e875619fac..e824baf4640d 100644
--- a/drivers/infiniband/core/umem_dmabuf.c
+++ b/drivers/infiniband/core/umem_dmabuf.c
@@ -55,9 +55,8 @@ int ib_umem_dmabuf_map_pages(struct ib_umem_dmabuf
*umem_dmabuf)
cur += sg_dma_len(sg);
}
- umem_dmabuf->umem.sg_head.sgl = umem_dmabuf->first_sg;
- umem_dmabuf->umem.sg_head.nents = nmap;
- umem_d
[Intel-gfx] ✗ Fi.CI.BUILD: failure for SG fix together with update to RDMA umem (rev3)
== Series Details == Series: SG fix together with update to RDMA umem (rev3) URL : https://patchwork.freedesktop.org/series/92682/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/gem/i915_gem_ttm.o drivers/gpu/drm/i915/gem/i915_gem_ttm.c: In function ‘i915_ttm_tt_get_st’: drivers/gpu/drm/i915/gem/i915_gem_ttm.c:396:7: error: implicit declaration of function ‘__sg_alloc_table_from_pages’; did you mean ‘sg_alloc_table_from_pages’? [-Werror=implicit-function-declaration] sg = __sg_alloc_table_from_pages ^~~ sg_alloc_table_from_pages drivers/gpu/drm/i915/gem/i915_gem_ttm.c:396:5: error: assignment to ‘struct scatterlist *’ from ‘int’ makes pointer from integer without a cast [-Werror=int-conversion] sg = __sg_alloc_table_from_pages ^ cc1: all warnings being treated as errors scripts/Makefile.build:271: recipe for target 'drivers/gpu/drm/i915/gem/i915_gem_ttm.o' failed make[4]: *** [drivers/gpu/drm/i915/gem/i915_gem_ttm.o] Error 1 scripts/Makefile.build:514: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:514: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:514: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1842: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/selftests: prefer the create_user helper
No need to hand roll the set_placements stuff, now that that we have a
helper for this.
v2: add back the -ENODEV checking since it's possible for stolen to be
probed, and yet still be non-functional
Signed-off-by: Matthew Auld
Cc: Jason Ekstrand
Reviewed-by: Jason Ekstrand
---
.../drm/i915/gem/selftests/i915_gem_mman.c| 34 +++
1 file changed, 4 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 0b2b73d8a364..b20f5621f62b 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -860,24 +860,6 @@ static bool can_mmap(struct drm_i915_gem_object *obj, enum
i915_mmap_type type)
return !no_map;
}
-static void object_set_placements(struct drm_i915_gem_object *obj,
- struct intel_memory_region **placements,
- unsigned int n_placements)
-{
- GEM_BUG_ON(!n_placements);
-
- if (n_placements == 1) {
- struct drm_i915_private *i915 = to_i915(obj->base.dev);
- struct intel_memory_region *mr = placements[0];
-
- obj->mm.placements = &i915->mm.regions[mr->id];
- obj->mm.n_placements = 1;
- } else {
- obj->mm.placements = placements;
- obj->mm.n_placements = n_placements;
- }
-}
-
#define expand32(x) (((x) << 0) | ((x) << 8) | ((x) << 16) | ((x) << 24))
static int __igt_mmap(struct drm_i915_private *i915,
struct drm_i915_gem_object *obj,
@@ -972,15 +954,13 @@ static int igt_mmap(void *arg)
struct drm_i915_gem_object *obj;
int err;
- obj = i915_gem_object_create_region(mr, sizes[i], 0,
I915_BO_ALLOC_USER);
+ obj = __i915_gem_object_create_user(i915, sizes[i],
&mr, 1);
if (obj == ERR_PTR(-ENODEV))
continue;
if (IS_ERR(obj))
return PTR_ERR(obj);
- object_set_placements(obj, &mr, 1);
-
err = __igt_mmap(i915, obj, I915_MMAP_TYPE_GTT);
if (err == 0)
err = __igt_mmap(i915, obj, I915_MMAP_TYPE_WC);
@@ -1101,15 +1081,13 @@ static int igt_mmap_access(void *arg)
struct drm_i915_gem_object *obj;
int err;
- obj = i915_gem_object_create_region(mr, PAGE_SIZE, 0,
I915_BO_ALLOC_USER);
+ obj = __i915_gem_object_create_user(i915, PAGE_SIZE, &mr, 1);
if (obj == ERR_PTR(-ENODEV))
continue;
if (IS_ERR(obj))
return PTR_ERR(obj);
- object_set_placements(obj, &mr, 1);
-
err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_GTT);
if (err == 0)
err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_WB);
@@ -1248,15 +1226,13 @@ static int igt_mmap_gpu(void *arg)
struct drm_i915_gem_object *obj;
int err;
- obj = i915_gem_object_create_region(mr, PAGE_SIZE, 0,
I915_BO_ALLOC_USER);
+ obj = __i915_gem_object_create_user(i915, PAGE_SIZE, &mr, 1);
if (obj == ERR_PTR(-ENODEV))
continue;
if (IS_ERR(obj))
return PTR_ERR(obj);
- object_set_placements(obj, &mr, 1);
-
err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_GTT);
if (err == 0)
err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_WC);
@@ -1405,15 +1381,13 @@ static int igt_mmap_revoke(void *arg)
struct drm_i915_gem_object *obj;
int err;
- obj = i915_gem_object_create_region(mr, PAGE_SIZE, 0,
I915_BO_ALLOC_USER);
+ obj = __i915_gem_object_create_user(i915, PAGE_SIZE, &mr, 1);
if (obj == ERR_PTR(-ENODEV))
continue;
if (IS_ERR(obj))
return PTR_ERR(obj);
- object_set_placements(obj, &mr, 1);
-
err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_GTT);
if (err == 0)
err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_WC);
--
2.26.3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Introduce Intel PXP (rev2)
== Series Details ==
Series: drm/i915: Introduce Intel PXP (rev2)
URL : https://patchwork.freedesktop.org/series/90503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10416_full -> Patchwork_20735_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20735_full:
### Piglit changes ###
Possible regressions
*
spec@arb_gpu_shader_int64@execution@conversion@geom-conversion-explicit-u64vec4-uvec4
(NEW):
- {pig-icl-1065g7}: NOTRUN -> [CRASH][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20735/pig-icl-1065g7/spec@arb_gpu_shader_int64@execution@convers...@geom-conversion-explicit-u64vec4-uvec4.html
*
spec@arb_gpu_shader_int64@execution@conversion@vert-conversion-implicit-i64vec2-dvec2
(NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][2] +7 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20735/pig-icl-1065g7/spec@arb_gpu_shader_int64@execution@convers...@vert-conversion-implicit-i64vec2-dvec2.html
New tests
-
New tests have been introduced between CI_DRM_10416_full and
Patchwork_20735_full:
### New Piglit tests (9) ###
*
spec@arb_gpu_shader_int64@execution@conversion@frag-conversion-implicit-u64vec4-dvec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_gpu_shader_int64@execution@conversion@geom-conversion-explicit-u64vec4-uvec4:
- Statuses : 1 crash(s)
- Exec time: [0.95] s
*
spec@arb_gpu_shader_int64@execution@conversion@geom-conversion-implicit-u64vec2-dvec2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_gpu_shader_int64@execution@conversion@vert-conversion-explicit-bool-uint64_t:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_gpu_shader_int64@execution@conversion@vert-conversion-explicit-u64vec3-bvec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_gpu_shader_int64@execution@conversion@vert-conversion-implicit-i64vec2-dvec2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_gpu_shader_int64@execution@conversion@vert-conversion-implicit-i64vec4-dvec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_gpu_shader_int64@execution@conversion@vert-conversion-implicit-i64vec4-u64vec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_gpu_shader_int64@execution@conversion@vert-conversion-implicit-uint-uint64_t:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_20735_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@display-3x:
- shard-glk: NOTRUN -> [SKIP][3] ([fdo#109271]) +39 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20735/shard-glk5/igt@feature_discov...@display-3x.html
* igt@gem_ctx_persistence@process:
- shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +4
similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20735/shard-snb5/igt@gem_ctx_persiste...@process.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][5] ([i915#2842])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20735/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20735/shard-glk3/igt@gem_exec_fair@basic-throt...@rcs0.html
- shard-iclb: [PASS][8] -> [FAIL][9] ([i915#2849])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20735/shard-iclb2/igt@gem_exec_fair@basic-throt...@rcs0.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2428])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-iclb2/igt@gem_mmap_...@cpuset-big-copy-odd.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20735/shard-iclb7/igt@gem_mmap_...@cpuset-big-copy-odd.html
- shard-glk: [PASS][12] -> [FAIL][13] ([i915#1888] / [i915#307])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-glk5/igt@gem_mmap_...@cpuset-big-copy-odd.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20735/shard-glk1/igt@gem_mmap_...@cpuset-big-copy-odd.html
* igt@gem_pread@exhaustion:
- shard-snb: NOTRUN -> [WARN][14] ([i915#2658])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: prefer the create_user helper (rev2)
== Series Details == Series: drm/i915/selftests: prefer the create_user helper (rev2) URL : https://patchwork.freedesktop.org/series/93131/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0f9180249ece drm/i915/selftests: prefer the create_user helper -:6: WARNING:REPEATED_WORD: Possible repeated word: 'that' #6: No need to hand roll the set_placements stuff, now that that we have a total: 0 errors, 1 warnings, 0 checks, 88 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: prefer the create_user helper (rev2)
== Series Details == Series: drm/i915/selftests: prefer the create_user helper (rev2) URL : https://patchwork.freedesktop.org/series/93131/ State : success == Summary == CI Bug Log - changes from CI_DRM_10418 -> Patchwork_20738 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/index.html Known issues Here are the changes found in Patchwork_20738 that come from known issues: ### IGT changes ### Possible fixes * igt@gem_exec_suspend@basic-s0: - fi-tgl-1115g4: [FAIL][1] ([i915#1888]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7500u: [DMESG-FAIL][3] ([i915#165]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 Participating hosts (41 -> 34) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 fi-bdw-samus bat-jsl-1 Build changes - * Linux: CI_DRM_10418 -> Patchwork_20738 CI-20190529: 20190529 CI_DRM_10418: e8b9eb4ffe9ad59eeda3c5318282fc2d7acbe7da @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6156: 354638455597ac48ac433606b24b82a4d7b65d20 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20738: 0f9180249ece82c37bd71a4480a943d473cf1362 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0f9180249ece drm/i915/selftests: prefer the create_user helper == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftests: fixup igt_shrink_thp
Hi Matt,
On 28/07/2021 16:50, Matthew Auld wrote:
Since the object might still be active here, the shrink_all will simply
ignore it, which blows up in the test, since the pages will still be
there. Currently THP is disabled which should result in the test being
skipped, but if we ever re-enable THP we might start seeing the failure.
Fix this by forcing I915_SHRINK_ACTIVE.
Signed-off-by: Matthew Auld
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index a094f3ce1a90..7a67e880b562 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1575,7 +1575,10 @@ static int igt_shrink_thp(void *arg)
* Now that the pages are *unpinned* shrink-all should invoke
* shmem to truncate our pages.
*/
- i915_gem_shrink_all(i915);
+ i915_gem_shrink(NULL, i915, -1UL, NULL,
+ I915_SHRINK_BOUND |
+ I915_SHRINK_UNBOUND |
+ I915_SHRINK_ACTIVE);
if (i915_gem_object_has_pages(obj)) {
pr_err("shrink-all didn't truncate the pages\n");
err = -EINVAL;
I did s/shrink-all/shrinking/ locally in the comment above, and in
pr_err below the call to shrinker. Are you okay if I repost like that
and with my r-b as part of my series?
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: fixup igt_shrink_thp
On 29/07/2021 11:53, Tvrtko Ursulin wrote:
Hi Matt,
On 28/07/2021 16:50, Matthew Auld wrote:
Since the object might still be active here, the shrink_all will simply
ignore it, which blows up in the test, since the pages will still be
there. Currently THP is disabled which should result in the test being
skipped, but if we ever re-enable THP we might start seeing the failure.
Fix this by forcing I915_SHRINK_ACTIVE.
Signed-off-by: Matthew Auld
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index a094f3ce1a90..7a67e880b562 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1575,7 +1575,10 @@ static int igt_shrink_thp(void *arg)
* Now that the pages are *unpinned* shrink-all should invoke
* shmem to truncate our pages.
*/
- i915_gem_shrink_all(i915);
+ i915_gem_shrink(NULL, i915, -1UL, NULL,
+ I915_SHRINK_BOUND |
+ I915_SHRINK_UNBOUND |
+ I915_SHRINK_ACTIVE);
if (i915_gem_object_has_pages(obj)) {
pr_err("shrink-all didn't truncate the pages\n");
err = -EINVAL;
I did s/shrink-all/shrinking/ locally in the comment above, and in
pr_err below the call to shrinker. Are you okay if I repost like that
and with my r-b as part of my series?
Sure.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH v6 10/15] drm/i915/pxp: interfaces for using protected objects
On Wed, Jul 28, 2021 at 07:01:01PM -0700, Daniele Ceraolo Spurio wrote:
> This api allow user mode to create protected buffers and to mark
> contexts as making use of such objects. Only when using contexts
> marked in such a way is the execution guaranteed to work as expected.
>
> Contexts can only be marked as using protected content at creation time
> (i.e. the parameter is immutable) and they must be both bannable and not
> recoverable.
>
> All protected objects and contexts that have backing storage will be
> considered invalid when the PXP session is destroyed and all new
> submissions using them will be rejected. All intel contexts within the
> invalidated gem contexts will be marked banned. A new flag has been
> added to the RESET_STATS ioctl to report the context invalidation to
> userspace.
>
> This patch was previously sent as 2 separate patches, which have been
> squashed following a request to have all the uapi in a single patch.
> I've retained the s-o-b from both.
>
> v5: squash patches, rebase on proto_ctx, update kerneldoc
>
> v6: rebase on obj create_ext changes
The "rebase" word led me to think it was a small change caused
only by rebasing conflicts, but then I spotted something on
i915_gem_create.c that I didn't remember seeing before.
Since it took me a while to understand what was going on, let me
try to summarize to see if I got it right and to check
with others (Jason in special)
if we are aligned with the recent directions:
With the removal of the vanilla_object from the create_ext,
the addition of the flags was needed.
Then, instead of adding a new user_flags it adds the I915_BO_PROTECTED
to the existent flags (what is cleaner) but then it does
/* Add any flag set by create_ext options */
flags |= ext_flags;
on the new user_create_ext.
What shouldn't be a problem because the ext_flags is really only
the I915_BO_PROTECTED set by our new extension and immutable.
But I'm just trying to see if we are not opening any holes to accept
some undesired flags.
Apparently not.
Am I getting things right? Anything else we should check in here?
Thanks,
Rodrigo.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Bommu Krishnaiah
> Cc: Rodrigo Vivi
> Cc: Chris Wilson
> Cc: Lionel Landwerlin
> Cc: Jason Ekstrand
> Cc: Daniel Vetter
> Reviewed-by: Rodrigo Vivi #v5
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 68 --
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 18
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +
> drivers/gpu/drm/i915/gem/i915_gem_create.c| 75
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 40 -
> drivers/gpu/drm/i915/gem/i915_gem_object.c| 6 ++
> drivers/gpu/drm/i915/gem/i915_gem_object.h| 12 +++
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 89 +++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 15
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 3 +
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 5 ++
> include/uapi/drm/i915_drm.h | 55 +++-
> 13 files changed, 371 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index cff72679ad7c..0cd3e2d06188 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -77,6 +77,8 @@
> #include "gt/intel_gpu_commands.h"
> #include "gt/intel_ring.h"
>
> +#include "pxp/intel_pxp.h"
> +
> #include "i915_gem_context.h"
> #include "i915_trace.h"
> #include "i915_user_extensions.h"
> @@ -241,6 +243,25 @@ static int proto_context_set_persistence(struct
> drm_i915_private *i915,
> return 0;
> }
>
> +static int proto_context_set_protected(struct drm_i915_private *i915,
> +struct i915_gem_proto_context *pc,
> +bool protected)
> +{
> + int ret = 0;
> +
> + if (!intel_pxp_is_enabled(&i915->gt.pxp))
> + ret = -ENODEV;
> + else if (!protected)
> + pc->user_flags &= ~BIT(UCONTEXT_PROTECTED);
> + else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) ||
> + !(pc->user_flags & BIT(UCONTEXT_BANNABLE)))
> + ret = -EPERM;
> + else
> + pc->user_flags |= BIT(UCONTEXT_PROTECTED);
> +
> + return ret;
> +}
> +
> static struct i915_gem_proto_context *
> proto_context_create(struct drm_i915_private *i915, unsigned int flags)
> {
> @@ -686,6 +707,8 @@ static int set_proto_ctx_param(struct
> drm_i915_file_private *fpriv,
> ret = -EPERM;
> else if (args->value)
> pc->user_flags |= BIT(UCONTEXT_BANNABLE);
> + else if (pc->user_flags & BIT(UCONTEXT_PROTECTED))
> + ret = -EPERM;
> else
> pc->user_flag
Re: [Intel-gfx] [PATCH 0/4] Remove CNL - for drm-intel-gt-next
On Wed, Jul 28, 2021 at 03:03:22PM -0700, Lucas De Marchi wrote: > This the part of https://patchwork.freedesktop.org/series/93056/ > that should go through drm-intel-gt-next branch. Acked-by: Rodrigo Vivi > > Lucas De Marchi (4): > drm/i915/gt: remove explicit CNL handling from intel_mocs.c > drm/i915/gt: remove explicit CNL handling from intel_sseu.c > drm/i915/gt: rename CNL references in intel_engine.h > drm/i915/gt: remove GRAPHICS_VER == 10 > > drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 10 +-- > drivers/gpu/drm/i915/gt/intel_engine.h| 2 +- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 - > drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 +- > .../gpu/drm/i915/gt/intel_gt_clock_utils.c| 10 +-- > drivers/gpu/drm/i915/gt/intel_gtt.c | 6 +- > drivers/gpu/drm/i915/gt/intel_lrc.c | 42 +- > drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- > drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +- > drivers/gpu/drm/i915/gt/intel_rps.c | 4 +- > drivers/gpu/drm/i915/gt/intel_sseu.c | 79 --- > drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +- > drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 6 +- > drivers/gpu/drm/i915/i915_drv.h | 4 +- > 14 files changed, 27 insertions(+), 149 deletions(-) > > -- > 2.31.1 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/selftests: fixup igt_shrink_thp
From: Matthew Auld
Since the object might still be active here, the shrink_all will simply
ignore it, which blows up in the test, since the pages will still be
there. Currently THP is disabled which should result in the test being
skipped, but if we ever re-enable THP we might start seeing the failure.
Fix this by forcing I915_SHRINK_ACTIVE.
Signed-off-by: Matthew Auld
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index a094f3ce1a90..acc435f14ac9 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1572,12 +1572,15 @@ static int igt_shrink_thp(void *arg)
goto out_put;
/*
-* Now that the pages are *unpinned* shrink-all should invoke
+* Now that the pages are *unpinned* shrinking should invoke
* shmem to truncate our pages.
*/
- i915_gem_shrink_all(i915);
+ i915_gem_shrink(NULL, i915, -1UL, NULL,
+ I915_SHRINK_BOUND |
+ I915_SHRINK_UNBOUND |
+ I915_SHRINK_ACTIVE);
if (i915_gem_object_has_pages(obj)) {
- pr_err("shrink-all didn't truncate the pages\n");
+ pr_err("shrinking didn't truncate the pages\n");
err = -EINVAL;
goto out_put;
}
--
2.30.2
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[Intel-gfx] [PATCH 2/2] drm/i915: Use Transparent Hugepages when IOMMU is enabled
From: Tvrtko Ursulin
Usage of Transparent Hugepages was disabled in 9987da4b5dcf
("drm/i915: Disable THP until we have a GPU read BW W/A"), but since it
appears majority of performance regressions reported with an enabled IOMMU
can be almost eliminated by turning them on, lets do that by adding a
couple of Kconfig options.
To err on the side of safety we keep the current default in cases where
IOMMU is not active, and only when it is default to the "huge=within_size"
mode. Although there probably would be wins to enable them throughout,
more extensive testing across benchmarks and platforms would need to be
done.
With the patch and IOMMU enabled my local testing on a small Skylake part
shows OglVSTangent regression being reduced from ~14% to ~2%.
v2:
* Add Kconfig dependency to transparent hugepages and some help text.
* Move to helper for easier handling of kernel build options.
References: b901bb89324a ("drm/i915/gemfs: enable THP")
References: 9987da4b5dcf ("drm/i915: Disable THP until we have a GPU read BW
W/A")
References: https://gitlab.freedesktop.org/drm/intel/-/issues/430
Co-developed-by: Chris Wilson
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matthew Auld
Cc: Eero Tamminen
Cc: Tvrtko Ursulin
Cc: Rodrigo Vivi
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi # v1
---
drivers/gpu/drm/i915/Kconfig.profile | 73 +++
drivers/gpu/drm/i915/gem/i915_gemfs.c | 27 --
2 files changed, 97 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index 39328567c200..d49ee794732f 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -119,3 +119,76 @@ config DRM_I915_TIMESLICE_DURATION
/sys/class/drm/card?/engine/*/timeslice_duration_ms
May be 0 to disable timeslicing.
+
+choice
+ prompt "Transparent Hugepage Support (native)"
+ default DRM_I915_THP_NATIVE_NEVER
+ depends on TRANSPARENT_HUGEPAGE
+ help
+ Select the preferred method for allocating from Transparent Hugepages
+ when IOMMU is not enabled.
+
+ config DRM_I915_THP_NATIVE_NEVER
+ bool "Never"
+ help
+ Disable using THP for system memory allocations, individually
+ allocating each 4K chunk as a separate page. It is unlikely that such
+ individual allocations will return contiguous memory.
+
+ config DRM_I915_THP_NATIVE_WITHIN
+ bool "Within size"
+ help
+ Allocate whole 2M superpages while those chunks do not exceed the
+ object size. The remainder of the object will be allocated from 4K
+ pages. No overallocation.
+
+ config DRM_I915_THP_NATIVE_ALWAYS
+ bool "Always"
+ help
+ Allocate the whole object using 2M superpages, even if the object does
+ not require an exact number of superpages.
+
+endchoice
+
+config DRM_I915_THP_NATIVE
+ string
+ default "always" if DRM_I915_THP_NATIVE_ALWAYS
+ default "within_size" if DRM_I915_THP_NATIVE_WITHIN
+ default "never" if DRM_I915_THP_NATIVE_NEVER
+
+choice
+ prompt "Transparent Hugepage Support (IOMMU)"
+ default DRM_I915_THP_IOMMU_WITHIN if TRANSPARENT_HUGEPAGE=y
+ default DRM_I915_THP_IOMMU_NEVER if TRANSPARENT_HUGEPAGE=n
+ depends on TRANSPARENT_HUGEPAGE
+ help
+ Select the preferred method for allocating from Transparent Hugepages
+ with IOMMU active.
+
+ config DRM_I915_THP_IOMMU_NEVER
+ bool "Never"
+ help
+ Disable using THP for system memory allocations, individually
+ allocating each 4K chunk as a separate page. It is unlikely that such
+ individual allocations will return contiguous memory.
+
+ config DRM_I915_THP_IOMMU_WITHIN
+ bool "Within size"
+ help
+ Allocate whole 2M superpages while those chunks do not exceed the
+ object size. The remainder of the object will be allocated from 4K
+ pages. No overallocation.
+
+ config DRM_I915_THP_IOMMU_ALWAYS
+ bool "Always"
+ help
+ Allocate the whole object using 2M superpages, even if the object does
+ not require an exact number of superpages.
+
+endchoice
+
+config DRM_I915_THP_IOMMU
+ string
+ default "always" if DRM_I915_THP_IOMMU_ALWAYS
+ default "within_size" if DRM_I915_THP_IOMMU_WITHIN
+ default "never" if DRM_I915_THP_IOMMU_NEVER
diff --git a/drivers/gpu/drm/i915/gem/i915_gemfs.c
b/drivers/gpu/drm/i915/gem/i915_gemfs.c
index 5e6e8c91ab38..871cbfb02fdf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gemfs.c
+++ b/drivers/gpu/drm/i915/gem/i915_gemfs.c
@@ -11,6 +11,26 @@
#include "i915_drv.h"
#include "i915_gemfs.h"
+#if defined(CONFIG_DRM_I915_THP_NATIVE) && defined(CONFIG_DRM_I915_THP_IOMMU)
+static char *gemfd_mount_opts(struct drm_i915_private *i915)
+{
+ static char thp_native[] = "h
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: fixup igt_shrink_thp
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: fixup igt_shrink_thp
URL : https://patchwork.freedesktop.org/series/93176/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2870e3292b14 drm/i915/selftests: fixup igt_shrink_thp
2b2db1afa93b drm/i915: Use Transparent Hugepages when IOMMU is enabled
-:6: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 9987da4b5dcf ("drm/i915: Disable
THP until we have a GPU read BW W/A")'
#6:
Usage of Transparent Hugepages was disabled in 9987da4b5dcf
-:25: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit b901bb89324a ("drm/i915/gemfs:
enable THP")'
#25:
References: b901bb89324a ("drm/i915/gemfs: enable THP")
-:26: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#26:
References: 9987da4b5dcf ("drm/i915: Disable THP until we have a GPU read BW
W/A")
-:26: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 9987da4b5dcf ("drm/i915: Disable
THP until we have a GPU read BW W/A")'
#26:
References: 9987da4b5dcf ("drm/i915: Disable THP until we have a GPU read BW
W/A")
-:130: WARNING:STATIC_CONST_CHAR_ARRAY: static char array declaration should
probably be static const char
#130: FILE: drivers/gpu/drm/i915/gem/i915_gemfs.c:17:
+ static char thp_native[] = "huge=" CONFIG_DRM_I915_THP_NATIVE;
-:131: WARNING:STATIC_CONST_CHAR_ARRAY: static char array declaration should
probably be static const char
#131: FILE: drivers/gpu/drm/i915/gem/i915_gemfs.c:18:
+ static char thp_iommu[] = "huge=" CONFIG_DRM_I915_THP_IOMMU;
-:146: CHECK:LINE_SPACING: Please don't use multiple blank lines
#146: FILE: drivers/gpu/drm/i915/gem/i915_gemfs.c:33:
+
+
total: 3 errors, 3 warnings, 1 checks, 116 lines checked
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Use Transparent Hugepages when IOMMU is enabled
On Thu, Jul 29, 2021 at 1:19 PM Tvrtko Ursulin
wrote:
>
> From: Tvrtko Ursulin
>
> Usage of Transparent Hugepages was disabled in 9987da4b5dcf
> ("drm/i915: Disable THP until we have a GPU read BW W/A"), but since it
> appears majority of performance regressions reported with an enabled IOMMU
> can be almost eliminated by turning them on, lets do that by adding a
> couple of Kconfig options.
>
> To err on the side of safety we keep the current default in cases where
> IOMMU is not active, and only when it is default to the "huge=within_size"
> mode. Although there probably would be wins to enable them throughout,
> more extensive testing across benchmarks and platforms would need to be
> done.
>
> With the patch and IOMMU enabled my local testing on a small Skylake part
> shows OglVSTangent regression being reduced from ~14% to ~2%.
I guess the 14% regression is iommu disabled vs iommu enabled? Would
be good to clarify that.
> v2:
> * Add Kconfig dependency to transparent hugepages and some help text.
Uh I'm really not a huge fan of Kconfig for everything, especially for
tuning stuff. Maybe if there's a need a module param for debugging,
but otherwise can't we just pick the right default?
And it very much sounds like the right default here is "enable it
unconditionally if we have iommu support".
-Daniel
> * Move to helper for easier handling of kernel build options.
>
> References: b901bb89324a ("drm/i915/gemfs: enable THP")
> References: 9987da4b5dcf ("drm/i915: Disable THP until we have a GPU read BW
> W/A")
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/430
> Co-developed-by: Chris Wilson
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matthew Auld
> Cc: Eero Tamminen
> Cc: Tvrtko Ursulin
> Cc: Rodrigo Vivi
> Signed-off-by: Tvrtko Ursulin
> Reviewed-by: Rodrigo Vivi # v1
> ---
> drivers/gpu/drm/i915/Kconfig.profile | 73 +++
> drivers/gpu/drm/i915/gem/i915_gemfs.c | 27 --
> 2 files changed, 97 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/Kconfig.profile
> b/drivers/gpu/drm/i915/Kconfig.profile
> index 39328567c200..d49ee794732f 100644
> --- a/drivers/gpu/drm/i915/Kconfig.profile
> +++ b/drivers/gpu/drm/i915/Kconfig.profile
> @@ -119,3 +119,76 @@ config DRM_I915_TIMESLICE_DURATION
> /sys/class/drm/card?/engine/*/timeslice_duration_ms
>
> May be 0 to disable timeslicing.
> +
> +choice
> + prompt "Transparent Hugepage Support (native)"
> + default DRM_I915_THP_NATIVE_NEVER
> + depends on TRANSPARENT_HUGEPAGE
> + help
> + Select the preferred method for allocating from Transparent
> Hugepages
> + when IOMMU is not enabled.
> +
> + config DRM_I915_THP_NATIVE_NEVER
> + bool "Never"
> + help
> + Disable using THP for system memory allocations, individually
> + allocating each 4K chunk as a separate page. It is unlikely that
> such
> + individual allocations will return contiguous memory.
> +
> + config DRM_I915_THP_NATIVE_WITHIN
> + bool "Within size"
> + help
> + Allocate whole 2M superpages while those chunks do not exceed the
> + object size. The remainder of the object will be allocated from 4K
> + pages. No overallocation.
> +
> + config DRM_I915_THP_NATIVE_ALWAYS
> + bool "Always"
> + help
> + Allocate the whole object using 2M superpages, even if the object
> does
> + not require an exact number of superpages.
> +
> +endchoice
> +
> +config DRM_I915_THP_NATIVE
> + string
> + default "always" if DRM_I915_THP_NATIVE_ALWAYS
> + default "within_size" if DRM_I915_THP_NATIVE_WITHIN
> + default "never" if DRM_I915_THP_NATIVE_NEVER
> +
> +choice
> + prompt "Transparent Hugepage Support (IOMMU)"
> + default DRM_I915_THP_IOMMU_WITHIN if TRANSPARENT_HUGEPAGE=y
> + default DRM_I915_THP_IOMMU_NEVER if TRANSPARENT_HUGEPAGE=n
> + depends on TRANSPARENT_HUGEPAGE
> + help
> + Select the preferred method for allocating from Transparent
> Hugepages
> + with IOMMU active.
> +
> + config DRM_I915_THP_IOMMU_NEVER
> + bool "Never"
> + help
> + Disable using THP for system memory allocations, individually
> + allocating each 4K chunk as a separate page. It is unlikely that
> such
> + individual allocations will return contiguous memory.
> +
> + config DRM_I915_THP_IOMMU_WITHIN
> + bool "Within size"
> + help
> + Allocate whole 2M superpages while those chunks do not exceed the
> + object size. The remainder of the object will be allocated from 4K
> + pages. No overallocation.
> +
> + config DRM_I915_THP_IOMMU_ALWAYS
> + bool "Always"
> + help
> + Allocate the whole object using 2M superpages, even if the object
> does
> + not require an exact number of superp
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: fixup igt_shrink_thp
== Series Details == Series: series starting with [1/2] drm/i915/selftests: fixup igt_shrink_thp URL : https://patchwork.freedesktop.org/series/93176/ State : success == Summary == CI Bug Log - changes from CI_DRM_10418 -> Patchwork_20739 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/index.html Known issues Here are the changes found in Patchwork_20739 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +29 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@core_hotunplug@unbind-rebind: - fi-bdw-5557u: NOTRUN -> [WARN][2] ([i915#3718]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html * igt@i915_pm_rpm@basic-rte: - fi-bdw-5557u: NOTRUN -> [FAIL][3] ([i915#579]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/fi-bdw-5557u/igt@i915_pm_...@basic-rte.html * igt@i915_selftest@live@execlists: - fi-bsw-kefka: [PASS][4] -> [INCOMPLETE][5] ([i915#2782] / [i915#2940]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html * igt@runner@aborted: - fi-bsw-kefka: NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#1436]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/fi-bsw-kefka/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s0: - fi-tgl-1115g4: [FAIL][8] ([i915#1888]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7500u: [DMESG-FAIL][10] ([i915#165]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 Participating hosts (41 -> 34) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 fi-bdw-samus bat-jsl-1 Build changes - * Linux: CI_DRM_10418 -> Patchwork_20739 CI-20190529: 20190529 CI_DRM_10418: e8b9eb4ffe9ad59eeda3c5318282fc2d7acbe7da @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6156: 354638455597ac48ac433606b24b82a4d7b65d20 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20739: 2b2db1afa93b2526dac8d5674331fe16f109235b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2b2db1afa93b drm/i915: Use Transparent Hugepages when IOMMU is enabled 2870e3292b14 drm/i915/selftests: fixup igt_shrink_thp == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Use Transparent Hugepages when IOMMU is enabled
On 29/07/2021 13:07, Daniel Vetter wrote:
On Thu, Jul 29, 2021 at 1:19 PM Tvrtko Ursulin
wrote:
From: Tvrtko Ursulin
Usage of Transparent Hugepages was disabled in 9987da4b5dcf
("drm/i915: Disable THP until we have a GPU read BW W/A"), but since it
appears majority of performance regressions reported with an enabled IOMMU
can be almost eliminated by turning them on, lets do that by adding a
couple of Kconfig options.
To err on the side of safety we keep the current default in cases where
IOMMU is not active, and only when it is default to the "huge=within_size"
mode. Although there probably would be wins to enable them throughout,
more extensive testing across benchmarks and platforms would need to be
done.
With the patch and IOMMU enabled my local testing on a small Skylake part
shows OglVSTangent regression being reduced from ~14% to ~2%.
I guess the 14% regression is iommu disabled vs iommu enabled? Would
be good to clarify that.
Should be clear from the first paragraph above - "...majority of
performance regressions reported with an _enabled_ IOMMU can be almost
eliminated...".
v2:
* Add Kconfig dependency to transparent hugepages and some help text.
Uh I'm really not a huge fan of Kconfig for everything, especially for
tuning stuff. Maybe if there's a need a module param for debugging,
but otherwise can't we just pick the right default?
Kconfig is picking the right default so I do not see a problem by
allowing override from a deep enough menu. But I also do not feel so
strongly about bikeshedding this to no kconfig, or a module param, or
whatever - there are votes for all three options already, as usual. Main
problem I have is actually..
And it very much sounds like the right default here is "enable it
unconditionally if we have iommu support".
.. about this - who knows? I will remind you of a certain VLK-20150
which I thought was very important for going forward but was falling on
deaf ears for years. As such I am waiting for Eero to come back and
improvise some unofficial testing. It's extra bewildering to me given
how we had the facility and then shut it down just like that.
Regards,
Tvrtko
-Daniel
* Move to helper for easier handling of kernel build options.
References: b901bb89324a ("drm/i915/gemfs: enable THP")
References: 9987da4b5dcf ("drm/i915: Disable THP until we have a GPU read BW
W/A")
References: https://gitlab.freedesktop.org/drm/intel/-/issues/430
Co-developed-by: Chris Wilson
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matthew Auld
Cc: Eero Tamminen
Cc: Tvrtko Ursulin
Cc: Rodrigo Vivi
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi # v1
---
drivers/gpu/drm/i915/Kconfig.profile | 73 +++
drivers/gpu/drm/i915/gem/i915_gemfs.c | 27 --
2 files changed, 97 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index 39328567c200..d49ee794732f 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -119,3 +119,76 @@ config DRM_I915_TIMESLICE_DURATION
/sys/class/drm/card?/engine/*/timeslice_duration_ms
May be 0 to disable timeslicing.
+
+choice
+ prompt "Transparent Hugepage Support (native)"
+ default DRM_I915_THP_NATIVE_NEVER
+ depends on TRANSPARENT_HUGEPAGE
+ help
+ Select the preferred method for allocating from Transparent Hugepages
+ when IOMMU is not enabled.
+
+ config DRM_I915_THP_NATIVE_NEVER
+ bool "Never"
+ help
+ Disable using THP for system memory allocations, individually
+ allocating each 4K chunk as a separate page. It is unlikely that such
+ individual allocations will return contiguous memory.
+
+ config DRM_I915_THP_NATIVE_WITHIN
+ bool "Within size"
+ help
+ Allocate whole 2M superpages while those chunks do not exceed the
+ object size. The remainder of the object will be allocated from 4K
+ pages. No overallocation.
+
+ config DRM_I915_THP_NATIVE_ALWAYS
+ bool "Always"
+ help
+ Allocate the whole object using 2M superpages, even if the object does
+ not require an exact number of superpages.
+
+endchoice
+
+config DRM_I915_THP_NATIVE
+ string
+ default "always" if DRM_I915_THP_NATIVE_ALWAYS
+ default "within_size" if DRM_I915_THP_NATIVE_WITHIN
+ default "never" if DRM_I915_THP_NATIVE_NEVER
+
+choice
+ prompt "Transparent Hugepage Support (IOMMU)"
+ default DRM_I915_THP_IOMMU_WITHIN if TRANSPARENT_HUGEPAGE=y
+ default DRM_I915_THP_IOMMU_NEVER if TRANSPARENT_HUGEPAGE=n
+ depends on TRANSPARENT_HUGEPAGE
+ help
+ Select the preferred method for allocating from Transparent Hugepages
+ with IOMMU active.
+
+ config DRM_I915_THP_IOMMU_NEVER
+ bool "Never"
+ help
+ Disable using THP for
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Use Transparent Hugepages when IOMMU is enabled
On Thu, Jul 29, 2021 at 2:21 PM Tvrtko Ursulin
wrote:
> On 29/07/2021 13:07, Daniel Vetter wrote:
> > On Thu, Jul 29, 2021 at 1:19 PM Tvrtko Ursulin
> > wrote:
> >>
> >> From: Tvrtko Ursulin
> >>
> >> Usage of Transparent Hugepages was disabled in 9987da4b5dcf
> >> ("drm/i915: Disable THP until we have a GPU read BW W/A"), but since it
> >> appears majority of performance regressions reported with an enabled IOMMU
> >> can be almost eliminated by turning them on, lets do that by adding a
> >> couple of Kconfig options.
> >>
> >> To err on the side of safety we keep the current default in cases where
> >> IOMMU is not active, and only when it is default to the "huge=within_size"
> >> mode. Although there probably would be wins to enable them throughout,
> >> more extensive testing across benchmarks and platforms would need to be
> >> done.
> >>
> >> With the patch and IOMMU enabled my local testing on a small Skylake part
> >> shows OglVSTangent regression being reduced from ~14% to ~2%.
> >
> > I guess the 14% regression is iommu disabled vs iommu enabled? Would
> > be good to clarify that.
>
> Should be clear from the first paragraph above - "...majority of
> performance regressions reported with an _enabled_ IOMMU can be almost
> eliminated...".
Yeah I inferred, but might be good to hammer that in by repeating, like
"reduced from 14% (for IOMMU on vs off case) to 2% (IOMMU on with THP
enabled vs IOMMU off with THP disabled)"
> >> v2:
> >> * Add Kconfig dependency to transparent hugepages and some help text.
> >
> > Uh I'm really not a huge fan of Kconfig for everything, especially for
> > tuning stuff. Maybe if there's a need a module param for debugging,
> > but otherwise can't we just pick the right default?
>
> Kconfig is picking the right default so I do not see a problem by
> allowing override from a deep enough menu. But I also do not feel so
> strongly about bikeshedding this to no kconfig, or a module param, or
> whatever - there are votes for all three options already, as usual. Main
> problem I have is actually..
Yeah that's pretty much what Kconfig is abused for: Everyone brings
their bikeshed because they're not quite happy, and it gets "resolved"
by Kconfigs to give everyone what they want. It just leads to
combinatorial explosion that no on tests. Hence unless we have a
demonstrated benefit of the choices there's going to be one default,
and you get to decide (which you did).
> > And it very much sounds like the right default here is "enable it
> > unconditionally if we have iommu support".
>
> .. about this - who knows? I will remind you of a certain VLK-20150
> which I thought was very important for going forward but was falling on
> deaf ears for years. As such I am waiting for Eero to come back and
> improvise some unofficial testing. It's extra bewildering to me given
> how we had the facility and then shut it down just like that.
Oh sure the general performance tuning is terrible, and also the
specific case of when THP. But we're looking the very specific case of
"IOMMU is enabled and it sucks away perf", and it looks like enabling
THP is the answer. So let's just do that.
Ofc we don't have full perf data, but we never have that even with a
nice perf lab (there's always more to benchmark than there's machine
time), so just doing as good as we can is imo perfectly fine enough.
You've put in the work (at least a bit), you get to pick the default
until we find something new.
-Daniel
>
> Regards,
>
> Tvrtko
>
> > -Daniel
> >
> >> * Move to helper for easier handling of kernel build options.
> >>
> >> References: b901bb89324a ("drm/i915/gemfs: enable THP")
> >> References: 9987da4b5dcf ("drm/i915: Disable THP until we have a GPU read
> >> BW W/A")
> >> References: https://gitlab.freedesktop.org/drm/intel/-/issues/430
> >> Co-developed-by: Chris Wilson
> >> Signed-off-by: Chris Wilson
> >> Cc: Joonas Lahtinen
> >> Cc: Matthew Auld
> >> Cc: Eero Tamminen
> >> Cc: Tvrtko Ursulin
> >> Cc: Rodrigo Vivi
> >> Signed-off-by: Tvrtko Ursulin
> >> Reviewed-by: Rodrigo Vivi # v1
> >> ---
> >> drivers/gpu/drm/i915/Kconfig.profile | 73 +++
> >> drivers/gpu/drm/i915/gem/i915_gemfs.c | 27 --
> >> 2 files changed, 97 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/Kconfig.profile
> >> b/drivers/gpu/drm/i915/Kconfig.profile
> >> index 39328567c200..d49ee794732f 100644
> >> --- a/drivers/gpu/drm/i915/Kconfig.profile
> >> +++ b/drivers/gpu/drm/i915/Kconfig.profile
> >> @@ -119,3 +119,76 @@ config DRM_I915_TIMESLICE_DURATION
> >>/sys/class/drm/card?/engine/*/timeslice_duration_ms
> >>
> >>May be 0 to disable timeslicing.
> >> +
> >> +choice
> >> + prompt "Transparent Hugepage Support (native)"
> >> + default DRM_I915_THP_NATIVE_NEVER
> >> + depends on TRANSPARENT_HUGEPAGE
> >> + help
> >> + Select the preferred method for allocating from Transparent
> >> Hugepages
[Intel-gfx] [PATCH v3 0/1] lpsp with hdmi/dp outputs
Squashes the patchset to a single patch to avoid any build failure. Anshuman Gupta (1): drm/i915/dg1: Adjust the AUDIO power domain drivers/gpu/drm/i915/display/intel_audio.c| 4 +- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- .../drm/i915/display/intel_display_power.c| 234 -- .../drm/i915/display/intel_display_power.h| 3 +- 5 files changed, 225 insertions(+), 20 deletions(-) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 1/1] drm/i915/dg1: Adjust the AUDIO power domain
DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power
well. Adjusting the power domain accordingly to
POWER_DOMAIN_AUDIO_VERBS for audio detection and POWER_DOMAIN_AUDIO
for audio playback.
While doing this it requires to use POWER_DOMAIN_AUDIO_MMIO
power domain instead of POWER_DOMAIN_AUDIO in crtc power domain mask
and POWER_DOMAIN_AUDIO_PLAYBACK with intel_display_power_{get, put}
to enable/disable display audio codec power.
It will save the power in use cases when DP/HDMI connectors
configured with PIPE_A without any audio playback.
v1: Changes since RFC
- changed power domain names. [Imre]
- Removed TC{3,6}, AUX_USBC{3,6} and TBT from DG1
power well and PW_3 power domains. [Imre]
- Fixed the order of powe wells , power domains and its
registration. [Imre]
v2:
- Not allowe DC states when AUDIO_MMIO domain enabled. [Imre]
v3:
- Squashes the commits of series to avoid build failure.
Cc: Ville Syrjälä
Cc: Kai Vehmanen
Cc: Uma Shankar
Cc: Imre Deak
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_audio.c| 4 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
.../drm/i915/display/intel_display_power.c| 234 --
.../drm/i915/display/intel_display_power.h| 3 +-
5 files changed, 225 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index 5f4f316b3ab5..532237588511 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -1001,7 +1001,7 @@ static unsigned long
i915_audio_component_get_power(struct device *kdev)
/* Catch potential impedance mismatches before they occur! */
BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
- ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
+ ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK);
if (dev_priv->audio_power_refcount++ == 0) {
if (DISPLAY_VER(dev_priv) >= 9) {
@@ -1034,7 +1034,7 @@ static void i915_audio_component_put_power(struct device
*kdev,
if (IS_GEMINILAKE(dev_priv))
glk_force_audio_cdclk(dev_priv, false);
- intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
+ intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK, cookie);
}
static void i915_audio_component_codec_wake_override(struct device *kdev,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 061a663f43b8..af0cefb6b311 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3463,7 +3463,7 @@ static bool intel_ddi_is_audio_enabled(struct
drm_i915_private *dev_priv,
if (cpu_transcoder == TRANSCODER_EDP)
return false;
- if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
+ if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO))
return false;
return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 97a216edf600..cafd7a95d9d7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3933,7 +3933,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state
*crtc_state)
}
if (HAS_DDI(dev_priv) && crtc_state->has_audio)
- mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
+ mask |= BIT_ULL(POWER_DOMAIN_AUDIO_MMIO);
if (crtc_state->shared_dpll)
mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 81efc77bada0..2675b48d707e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -106,8 +106,10 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
return "PORT_OTHER";
case POWER_DOMAIN_VGA:
return "VGA";
- case POWER_DOMAIN_AUDIO:
- return "AUDIO";
+ case POWER_DOMAIN_AUDIO_MMIO:
+ return "AUDIO_MMIO";
+ case POWER_DOMAIN_AUDIO_PLAYBACK:
+ return "AUDIO_PLAYBAK";
case POWER_DOMAIN_AUX_A:
return "AUX_A";
case POWER_DOMAIN_AUX_B:
@@ -2519,7 +2521,8 @@ intel_display_power_put_mask_in_set(struct
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_PORT_DSI) |\
BIT_ULL(POWER_DOMAIN_PORT_CRT) |\
BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ B
[Intel-gfx] ✗ Fi.CI.IGT: failure for Forcewake and shadowed register updates
== Series Details ==
Series: Forcewake and shadowed register updates
URL : https://patchwork.freedesktop.org/series/93158/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10416_full -> Patchwork_20736_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20736_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20736_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20736_full:
### IGT changes ###
Possible regressions
* igt@i915_selftest@mock@uncore:
- shard-glk: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-glk1/igt@i915_selftest@m...@uncore.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-glk1/igt@i915_selftest@m...@uncore.html
- shard-iclb: [PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-iclb1/igt@i915_selftest@m...@uncore.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb4/igt@i915_selftest@m...@uncore.html
- shard-kbl: [PASS][5] -> [DMESG-WARN][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-kbl3/igt@i915_selftest@m...@uncore.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl4/igt@i915_selftest@m...@uncore.html
- shard-tglb: [PASS][7] -> [DMESG-WARN][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-tglb2/igt@i915_selftest@m...@uncore.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-tglb3/igt@i915_selftest@m...@uncore.html
- shard-skl: [PASS][9] -> [DMESG-WARN][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-skl5/igt@i915_selftest@m...@uncore.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-skl9/igt@i915_selftest@m...@uncore.html
- shard-apl: [PASS][11] -> [DMESG-WARN][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-apl7/igt@i915_selftest@m...@uncore.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-apl8/igt@i915_selftest@m...@uncore.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@mock@uncore:
- {shard-rkl}:[PASS][13] -> [DMESG-WARN][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-rkl-6/igt@i915_selftest@m...@uncore.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-rkl-2/igt@i915_selftest@m...@uncore.html
Known issues
Here are the changes found in Patchwork_20736_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][15] ([i915#3002])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-kbl2/igt@gem_cre...@create-massive.html
- shard-apl: NOTRUN -> [DMESG-WARN][16] ([i915#3002])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-apl3/igt@gem_cre...@create-massive.html
* igt@gem_ctx_persistence@process:
- shard-snb: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#1099]) +2
similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-snb5/igt@gem_ctx_persiste...@process.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][18] -> [FAIL][19] ([i915#2842]) +1 similar
issue
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-glk1/igt@gem_exec_fair@basic-throt...@rcs0.html
- shard-iclb: [PASS][20] -> [FAIL][21] ([i915#2849])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html
* igt@gem_mmap_gtt@cpuset-big-copy-xy:
- shard-iclb: [PASS][22] -> [FAIL][23] ([i915#2428])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10416/shard-iclb4/igt@gem_mmap_...@cpuset-big-copy-xy.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-iclb4/igt@gem_mmap_...@cpuset-big-copy-xy.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][24] ([i915#2658])
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20736/shard-apl8/igt@gem_pr...@exha
[Intel-gfx] ✓ Fi.CI.BAT: success for lpsp with hdmi/dp outputs
== Series Details == Series: lpsp with hdmi/dp outputs URL : https://patchwork.freedesktop.org/series/93179/ State : success == Summary == CI Bug Log - changes from CI_DRM_10418 -> Patchwork_20740 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20740/index.html Known issues Here are the changes found in Patchwork_20740 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-bsw-nick:[PASS][1] -> [INCOMPLETE][2] ([i915#2782] / [i915#2940]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20740/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([i915#1372]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20740/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@runner@aborted: - fi-bsw-nick:NOTRUN -> [FAIL][5] ([fdo#109271] / [i915#1436]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20740/fi-bsw-nick/igt@run...@aborted.html Possible fixes * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7500u: [DMESG-FAIL][6] ([i915#165]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20740/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 Participating hosts (41 -> 34) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 fi-bdw-samus bat-jsl-1 Build changes - * Linux: CI_DRM_10418 -> Patchwork_20740 CI-20190529: 20190529 CI_DRM_10418: e8b9eb4ffe9ad59eeda3c5318282fc2d7acbe7da @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6156: 354638455597ac48ac433606b24b82a4d7b65d20 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20740: cfaa89c8dcfdedd7fa1a7ade6903f8ccca6af953 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == cfaa89c8dcfd drm/i915/dg1: Adjust the AUDIO power domain == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20740/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/selftests: fixup igt_shrink_thp
From: Matthew Auld
Since the object might still be active here, the shrink_all will simply
ignore it, which blows up in the test, since the pages will still be
there. Currently THP is disabled which should result in the test being
skipped, but if we ever re-enable THP we might start seeing the failure.
Fix this by forcing I915_SHRINK_ACTIVE.
Signed-off-by: Matthew Auld
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index a094f3ce1a90..acc435f14ac9 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1572,12 +1572,15 @@ static int igt_shrink_thp(void *arg)
goto out_put;
/*
-* Now that the pages are *unpinned* shrink-all should invoke
+* Now that the pages are *unpinned* shrinking should invoke
* shmem to truncate our pages.
*/
- i915_gem_shrink_all(i915);
+ i915_gem_shrink(NULL, i915, -1UL, NULL,
+ I915_SHRINK_BOUND |
+ I915_SHRINK_UNBOUND |
+ I915_SHRINK_ACTIVE);
if (i915_gem_object_has_pages(obj)) {
- pr_err("shrink-all didn't truncate the pages\n");
+ pr_err("shrinking didn't truncate the pages\n");
err = -EINVAL;
goto out_put;
}
--
2.30.2
___
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[Intel-gfx] [PATCH 2/2] drm/i915: Use Transparent Hugepages when IOMMU is enabled
From: Tvrtko Ursulin
Usage of Transparent Hugepages was disabled in 9987da4b5dcf
("drm/i915: Disable THP until we have a GPU read BW W/A"), but since it
appears majority of performance regressions reported with an enabled IOMMU
can be almost eliminated by turning them on, lets just do that.
To err on the side of safety we keep the current default in cases where
IOMMU is not active, and only when it is default to the "huge=within_size"
mode. Although there probably would be wins to enable them throughout,
more extensive testing across benchmarks and platforms would need to be
done.
With the patch and IOMMU enabled my local testing on a small Skylake part
shows OglVSTangent regression being reduced from ~14% (IOMMU on versus
IOMMU off) to ~2% (same comparison but with THP on).
v2:
* Add Kconfig dependency to transparent hugepages and some help text.
* Move to helper for easier handling of kernel build options.
v3:
* Drop Kconfig. (Daniel)
References: b901bb89324a ("drm/i915/gemfs: enable THP")
References: 9987da4b5dcf ("drm/i915: Disable THP until we have a GPU read BW
W/A")
References: https://gitlab.freedesktop.org/drm/intel/-/issues/430
Co-developed-by: Chris Wilson
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matthew Auld
Cc: Eero Tamminen
Cc: Tvrtko Ursulin
Cc: Rodrigo Vivi
Cc: Daniel Vetter
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Rodrigo Vivi # v1
---
drivers/gpu/drm/i915/gem/i915_gemfs.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gemfs.c
b/drivers/gpu/drm/i915/gem/i915_gemfs.c
index 5e6e8c91ab38..dbdbdc344d87 100644
--- a/drivers/gpu/drm/i915/gem/i915_gemfs.c
+++ b/drivers/gpu/drm/i915/gem/i915_gemfs.c
@@ -6,7 +6,6 @@
#include
#include
-#include
#include "i915_drv.h"
#include "i915_gemfs.h"
@@ -15,6 +14,7 @@ int i915_gemfs_init(struct drm_i915_private *i915)
{
struct file_system_type *type;
struct vfsmount *gemfs;
+ char *opts;
type = get_fs_type("tmpfs");
if (!type)
@@ -26,10 +26,26 @@ int i915_gemfs_init(struct drm_i915_private *i915)
*
* One example, although it is probably better with a per-file
* control, is selecting huge page allocations ("huge=within_size").
-* Currently unused due to bandwidth issues (slow reads) on Broadwell+.
+* However, we only do so to offset the overhead of iommu lookups
+* due to bandwidth issues (slow reads) on Broadwell+.
*/
- gemfs = kern_mount(type);
+ opts = NULL;
+ if (intel_vtd_active()) {
+ if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE)) {
+ static char huge_opt[] = "huge=within_size"; /* r/w */
+
+ opts = huge_opt;
+ drm_info(&i915->drm,
+"Transparent Hugepage mode '%s'\n",
+opts);
+ } else {
+ drm_notice(&i915->drm,
+ "Transparent Hugepage support is recommended
for optimal performance when IOMMU is enabled!\n");
+ }
+ }
+
+ gemfs = vfs_kern_mount(type, SB_KERNMOUNT, type->name, opts);
if (IS_ERR(gemfs))
return PTR_ERR(gemfs);
--
2.30.2
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: fixup igt_shrink_thp
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: fixup igt_shrink_thp
URL : https://patchwork.freedesktop.org/series/93182/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1cac26e2f95f drm/i915/selftests: fixup igt_shrink_thp
054c89f72f0f drm/i915: Use Transparent Hugepages when IOMMU is enabled
-:6: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 9987da4b5dcf ("drm/i915: Disable
THP until we have a GPU read BW W/A")'
#6:
Usage of Transparent Hugepages was disabled in 9987da4b5dcf
-:28: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit b901bb89324a ("drm/i915/gemfs:
enable THP")'
#28:
References: b901bb89324a ("drm/i915/gemfs: enable THP")
-:29: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#29:
References: 9987da4b5dcf ("drm/i915: Disable THP until we have a GPU read BW
W/A")
-:29: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 9987da4b5dcf ("drm/i915: Disable
THP until we have a GPU read BW W/A")'
#29:
References: 9987da4b5dcf ("drm/i915: Disable THP until we have a GPU read BW
W/A")
-:75: WARNING:STATIC_CONST_CHAR_ARRAY: static char array declaration should
probably be static const char
#75: FILE: drivers/gpu/drm/i915/gem/i915_gemfs.c:36:
+ static char huge_opt[] = "huge=within_size"; /* r/w */
total: 3 errors, 2 warnings, 0 checks, 42 lines checked
___
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Use Transparent Hugepages when IOMMU is enabled
On Thu, Jul 29, 2021 at 3:34 PM Tvrtko Ursulin
wrote:
>
> From: Tvrtko Ursulin
>
> Usage of Transparent Hugepages was disabled in 9987da4b5dcf
> ("drm/i915: Disable THP until we have a GPU read BW W/A"), but since it
> appears majority of performance regressions reported with an enabled IOMMU
> can be almost eliminated by turning them on, lets just do that.
>
> To err on the side of safety we keep the current default in cases where
> IOMMU is not active, and only when it is default to the "huge=within_size"
> mode. Although there probably would be wins to enable them throughout,
> more extensive testing across benchmarks and platforms would need to be
> done.
>
> With the patch and IOMMU enabled my local testing on a small Skylake part
> shows OglVSTangent regression being reduced from ~14% (IOMMU on versus
> IOMMU off) to ~2% (same comparison but with THP on).
>
> v2:
> * Add Kconfig dependency to transparent hugepages and some help text.
> * Move to helper for easier handling of kernel build options.
>
> v3:
> * Drop Kconfig. (Daniel)
>
> References: b901bb89324a ("drm/i915/gemfs: enable THP")
> References: 9987da4b5dcf ("drm/i915: Disable THP until we have a GPU read BW
> W/A")
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/430
> Co-developed-by: Chris Wilson
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matthew Auld
> Cc: Eero Tamminen
> Cc: Tvrtko Ursulin
> Cc: Rodrigo Vivi
> Cc: Daniel Vetter
> Signed-off-by: Tvrtko Ursulin
> Reviewed-by: Rodrigo Vivi # v1
On both patches: Acked-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/gem/i915_gemfs.c | 22 +++---
> 1 file changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gemfs.c
> b/drivers/gpu/drm/i915/gem/i915_gemfs.c
> index 5e6e8c91ab38..dbdbdc344d87 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gemfs.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gemfs.c
> @@ -6,7 +6,6 @@
>
> #include
> #include
> -#include
>
> #include "i915_drv.h"
> #include "i915_gemfs.h"
> @@ -15,6 +14,7 @@ int i915_gemfs_init(struct drm_i915_private *i915)
> {
> struct file_system_type *type;
> struct vfsmount *gemfs;
> + char *opts;
>
> type = get_fs_type("tmpfs");
> if (!type)
> @@ -26,10 +26,26 @@ int i915_gemfs_init(struct drm_i915_private *i915)
> *
> * One example, although it is probably better with a per-file
> * control, is selecting huge page allocations ("huge=within_size").
> -* Currently unused due to bandwidth issues (slow reads) on
> Broadwell+.
> +* However, we only do so to offset the overhead of iommu lookups
> +* due to bandwidth issues (slow reads) on Broadwell+.
> */
>
> - gemfs = kern_mount(type);
> + opts = NULL;
> + if (intel_vtd_active()) {
> + if (IS_ENABLED(CONFIG_TRANSPARENT_HUGEPAGE)) {
> + static char huge_opt[] = "huge=within_size"; /* r/w */
> +
> + opts = huge_opt;
> + drm_info(&i915->drm,
> +"Transparent Hugepage mode '%s'\n",
> +opts);
> + } else {
> + drm_notice(&i915->drm,
> + "Transparent Hugepage support is
> recommended for optimal performance when IOMMU is enabled!\n");
> + }
> + }
> +
> + gemfs = vfs_kern_mount(type, SB_KERNMOUNT, type->name, opts);
> if (IS_ERR(gemfs))
> return PTR_ERR(gemfs);
>
> --
> 2.30.2
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
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Re: [Intel-gfx] [PATCH 1/6] drm/i915: correct name of GT forcewake domain in error messages
Reviewed-by: Caz Yokoyama
-caz
On Wed, 2021-07-28 at 22:41 -0700, Matt Roper wrote:
> For historical reasons, the GT forcewake domain used to be referred
> to
> as the "blitter" domain; that name is no longer accurate since the GT
> domain contains a lot of additional registers and functionality
> besides
> just the blitter. Although we renamed the domain in the driver in
> commit 55e3c170950f ("drm/i915: Rename FORCEWAKE_BLITTER to
> FORCEWAKE_GT"), we neglected to update the string that gets printed
> in
> driver error messages; let's do that now to avoid confusion.
>
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 8cf53f54559d..bca548c81572 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -64,7 +64,7 @@ static void mmio_debug_resume(struct
> intel_uncore_mmio_debug *mmio_debug)
>
> static const char * const forcewake_domain_names[] = {
> "render",
> - "blitter",
> + "gt",
> "media",
> "vdbox0",
> "vdbox1",
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: fixup igt_shrink_thp
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: fixup igt_shrink_thp
URL : https://patchwork.freedesktop.org/series/93182/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10418 -> Patchwork_20741
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20741/index.html
Known issues
Here are the changes found in Patchwork_20741 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +29 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20741/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html
* igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u: NOTRUN -> [WARN][2] ([i915#3718])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20741/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html
* igt@i915_pm_rpm@basic-rte:
- fi-bdw-5557u: NOTRUN -> [FAIL][3] ([i915#579])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20741/fi-bdw-5557u/igt@i915_pm_...@basic-rte.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8
similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20741/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html
Possible fixes
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-1115g4: [FAIL][5] ([i915#1888]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20741/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [DMESG-FAIL][7] ([i915#165]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20741/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
Participating hosts (41 -> 34)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600
fi-bdw-samus bat-jsl-1
Build changes
-
* Linux: CI_DRM_10418 -> Patchwork_20741
CI-20190529: 20190529
CI_DRM_10418: e8b9eb4ffe9ad59eeda3c5318282fc2d7acbe7da @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6156: 354638455597ac48ac433606b24b82a4d7b65d20 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20741: 054c89f72f0f9f04e8377c7f9f5c66a6a7d047f8 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
054c89f72f0f drm/i915: Use Transparent Hugepages when IOMMU is enabled
1cac26e2f95f drm/i915/selftests: fixup igt_shrink_thp
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20741/index.html
___
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Re: [Intel-gfx] [PATCH 1/3] drm: use the lookup lock in drm_is_current_master
On Thu, Jul 29, 2021 at 10:32:13PM +0800, Desmond Cheong Zhi Xi wrote: > Sounds good, will do. Thanks for the patch, Peter. > > Just going to make a small edit: > s/LOCK_STAT_NOT_HELD/LOCK_STATE_NOT_HELD/ Bah, I knew I should've compile tested it :-), Thanks! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm: use the lookup lock in drm_is_current_master
On 29/7/21 3:00 pm, Daniel Vetter wrote:
On Tue, Jul 27, 2021 at 04:37:22PM +0200, Peter Zijlstra wrote:
On Thu, Jul 22, 2021 at 12:38:10PM +0200, Daniel Vetter wrote:
On Thu, Jul 22, 2021 at 05:29:27PM +0800, Desmond Cheong Zhi Xi wrote:
Inside drm_is_current_master, using the outer drm_device.master_mutex
to protect reads of drm_file.master makes the function prone to creating
lock hierarchy inversions. Instead, we can use the
drm_file.master_lookup_lock that sits at the bottom of the lock
hierarchy.
Reported-by: Daniel Vetter
Signed-off-by: Desmond Cheong Zhi Xi
---
drivers/gpu/drm/drm_auth.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c
index f00354bec3fb..9c24b8cc8e36 100644
--- a/drivers/gpu/drm/drm_auth.c
+++ b/drivers/gpu/drm/drm_auth.c
@@ -63,8 +63,9 @@
static bool drm_is_current_master_locked(struct drm_file *fpriv)
{
- lockdep_assert_held_once(&fpriv->minor->dev->master_mutex);
-
+ /* Either drm_device.master_mutex or drm_file.master_lookup_lock
+* should be held here.
+*/
Disappointing that lockdep can't check or conditions for us, a
lockdep_assert_held_either would be really neat in some cases.
Adding lockdep folks, maybe they have ideas.
#ifdef CONFIG_LOCKDEP
WARN_ON_ONCE(debug_locks && !(lockdep_is_held(&drm_device.master_mutex)
||
lockdep_is_held(&drm_file.master_lookup_lock)));
#endif
doesn't exactly roll off the tongue, but should do as you want I
suppose.
Would something like:
#define lockdep_assert(cond)WARN_ON_ONCE(debug_locks && !(cond))
Such that we can write:
lockdep_assert(lockdep_is_held(&drm_device.master_mutex) ||
lockdep_is_held(&drm_file.master_lookup_lock));
make it better ?
Yeah I think that's pretty tidy and flexible.
Desmond, can you pls give this a shot with Peter's patch below?
-Daniel
Sounds good, will do. Thanks for the patch, Peter.
Just going to make a small edit:
s/LOCK_STAT_NOT_HELD/LOCK_STATE_NOT_HELD/
Best wishes,
Desmond
---
Subject: locking/lockdep: Provide lockdep_assert{,_once}() helpers
Extract lockdep_assert{,_once}() helpers to more easily write composite
assertions like, for example:
lockdep_assert(lockdep_is_held(&drm_device.master_mutex) ||
lockdep_is_held(&drm_file.master_lookup_lock));
Signed-off-by: Peter Zijlstra (Intel)
---
diff --git a/include/linux/lockdep.h b/include/linux/lockdep.h
index 5cf387813754..0da67341c1fb 100644
--- a/include/linux/lockdep.h
+++ b/include/linux/lockdep.h
@@ -306,31 +306,29 @@ extern void lock_unpin_lock(struct lockdep_map *lock,
struct pin_cookie);
#define lockdep_depth(tsk) (debug_locks ? (tsk)->lockdep_depth : 0)
-#define lockdep_assert_held(l) do { \
- WARN_ON(debug_locks && \
- lockdep_is_held(l) == LOCK_STATE_NOT_HELD); \
- } while (0)
+#define lockdep_assert(cond) \
+ do { WARN_ON(debug_locks && !(cond)); } while (0)
-#define lockdep_assert_not_held(l) do {\
- WARN_ON(debug_locks && \
- lockdep_is_held(l) == LOCK_STATE_HELD); \
- } while (0)
+#define lockdep_assert_once(cond) \
+ do { WARN_ON_ONCE(debug_locks && !(cond)); } while (0)
-#define lockdep_assert_held_write(l) do { \
- WARN_ON(debug_locks && !lockdep_is_held_type(l, 0));\
- } while (0)
+#define lockdep_assert_held(l) \
+ lockdep_assert(lockdep_is_held(l) != LOCK_STAT_NOT_HELD)
-#define lockdep_assert_held_read(l) do {\
- WARN_ON(debug_locks && !lockdep_is_held_type(l, 1));\
- } while (0)
+#define lockdep_assert_not_held(l) \
+ lockdep_assert(lockdep_is_held(l) != LOCK_STATE_HELD)
-#define lockdep_assert_held_once(l) do {\
- WARN_ON_ONCE(debug_locks && !lockdep_is_held(l)); \
- } while (0)
+#define lockdep_assert_held_write(l) \
+ lockdep_assert(lockdep_is_held_type(l, 0))
-#define lockdep_assert_none_held_once() do {\
- WARN_ON_ONCE(debug_locks && current->lockdep_depth); \
- } while (0)
+#define lockdep_assert_held_read(l)\
+ lockdep_assert(lockdep_is_held_type(l, 1))
+
+#define lockdep_assert_held_once(l)\
+ lockdep_assert_once(lockdep_is_held(l) != LOCK_STAT_NOT_HELD)
+
+#define lockdep_assert_none_held_once()\
+ lockdep_assert_once(!current->lockdep_depth)
#define lockdep_recursing(tsk) ((tsk)->lockdep_recursion)
@@ -407,6 +405,9 @@ extern int lock_is_held(const void *);
extern int lockdep_is_held(const void *);
#define lockdep_is_held_type(l, r)(1)
+#define lockdep_assert(c) do { } while (0)
+#define lockdep_assert_once(c) d
Re: [Intel-gfx] [PATCH v3 23/30] drm/i915/dg2: Add MPLLB programming for SNPS PHY
On Fri, Jul 23, 2021 at 10:42:32AM -0700, Matt Roper wrote:
> DG2's SNPS PHYs incorporate a dedicated port PLL called MPLLB which
> takes the place of the shared DPLLs we've used on past platforms. Let's
> add the MPLLB programming sequences; they'll be plugged into the rest of
> the code in future patches.
>
> Bspec: 54032
> Bspec: 53881
> Cc: Lucas De Marchi
> Signed-off-by: Matt Roper
> Signed-off-by: Vandita Kulkarni
> Signed-off-by: Jani Nikula
> Signed-off-by: Nidhi Gupta
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> .../drm/i915/display/intel_display_types.h| 17 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 12 +-
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 517 ++
> drivers/gpu/drm/i915/display/intel_snps_phy.h | 18 +
> drivers/gpu/drm/i915/i915_reg.h | 56 ++
> 7 files changed, 616 insertions(+), 6 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 10b3bb6207ba..d87dbf87cfda 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -267,6 +267,7 @@ i915-y += \
> display/intel_pps.o \
> display/intel_qp_tables.o \
> display/intel_sdvo.o \
> + display/intel_snps_phy.o \
> display/intel_tv.o \
> display/intel_vdsc.o \
> display/intel_vrr.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 400f062d785a..8e88ef5407d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -59,6 +59,7 @@
> #include "display/intel_hdmi.h"
> #include "display/intel_lvds.h"
> #include "display/intel_sdvo.h"
> +#include "display/intel_snps_phy.h"
> #include "display/intel_tv.h"
> #include "display/intel_vdsc.h"
> #include "display/intel_vrr.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 19d8d3eefbc2..00320d89d266 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -884,6 +884,18 @@ enum intel_output_format {
> INTEL_OUTPUT_FORMAT_YCBCR444,
> };
>
> +struct intel_mpllb_state {
> + u32 clock; /* in KHz */
> + u32 ref_control;
> + u32 mpllb_cp;
> + u32 mpllb_div;
> + u32 mpllb_div2;
> + u32 mpllb_fracn1;
> + u32 mpllb_fracn2;
> + u32 mpllb_sscen;
> + u32 mpllb_sscstep;
> +};
> +
> struct intel_crtc_state {
> /*
>* uapi (drm) state. This is the software state shown to userspace.
> @@ -1018,7 +1030,10 @@ struct intel_crtc_state {
> struct intel_shared_dpll *shared_dpll;
>
> /* Actual register state of the dpll, for shared dpll cross-checking. */
> - struct intel_dpll_hw_state dpll_hw_state;
> + union {
> + struct intel_dpll_hw_state dpll_hw_state;
> + struct intel_mpllb_state mpllb_state;
> + };
>
> /*
>* ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 89635da9f6f6..14515e62c05e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -11,6 +11,7 @@
> #include "intel_lvds.h"
> #include "intel_panel.h"
> #include "intel_sideband.h"
> +#include "display/intel_snps_phy.h"
>
> struct intel_limit {
> struct {
> @@ -923,12 +924,13 @@ static int hsw_crtc_compute_clock(struct intel_crtc
> *crtc,
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_atomic_state *state =
> to_intel_atomic_state(crtc_state->uapi.state);
> + struct intel_encoder *encoder =
> + intel_get_crtc_new_encoder(state, crtc_state);
>
> - if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
> - DISPLAY_VER(dev_priv) >= 11) {
> - struct intel_encoder *encoder =
> - intel_get_crtc_new_encoder(state, crtc_state);
> -
> + if (IS_DG2(dev_priv)) {
> + return intel_mpllb_calc_state(crtc_state, encoder);
> + } else if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
> +DISPLAY_VER(dev_priv) >= 11) {
> if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
> drm_dbg_kms(&dev_priv->drm,
> "failed to find PLL for pipe %c\n",
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> new file mode 100644
> index ..6d9205906595
> --- /dev/null
> +++ b/drivers/
Re: [Intel-gfx] [PATCH v3 21/30] drm/i915/dg2: Report INSTDONE_GEOM values in error state
On Fri, Jul 23, 2021 at 10:42:30AM -0700, Matt Roper wrote:
> Xe_HPG adds some additional INSTDONE_GEOM debug registers; the Mesa team
> has indicated that having these reported in the error state would be
> useful for debugging GPU hangs. These registers are replicated per-DSS
> with gslice steering.
>
> Cc: Lionel Landwerlin
> Signed-off-by: Matt Roper
> Acked-by: Lionel Landwerlin
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c| 7 +++
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +++
> drivers/gpu/drm/i915/i915_gpu_error.c| 10 --
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 4 files changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index fc8538ce47ae..71f6e7d7c3b9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1211,6 +1211,13 @@ void intel_engine_get_instdone(const struct
> intel_engine_cs *engine,
> GEN7_ROW_INSTDONE);
> }
> }
> +
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
> + for_each_instdone_gslice_dss_xehp(i915, sseu, iter,
> slice, subslice)
> + instdone->geom_svg[slice][subslice] =
> + read_subslice_reg(engine, slice,
> subslice,
> +
> XEHPG_INSTDONE_GEOM_SVG);
> + }
> } else if (GRAPHICS_VER(i915) >= 7) {
> instdone->instdone =
> intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index b23d76ceea0e..8f9e79074c1c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -76,6 +76,9 @@ struct intel_instdone {
> u32 slice_common_extra[2];
> u32 sampler[GEN_MAX_GSLICES][I915_MAX_SUBSLICES];
> u32 row[GEN_MAX_GSLICES][I915_MAX_SUBSLICES];
> +
> + /* Added in XeHPG */
> + u32 geom_svg[GEN_MAX_GSLICES][I915_MAX_SUBSLICES];
> };
>
> /*
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index c1e744b5ab47..4de7edc451ef 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -431,6 +431,7 @@ static void error_print_instdone(struct
> drm_i915_error_state_buf *m,
> const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu;
> int slice;
> int subslice;
> + int iter;
>
> err_printf(m, " INSTDONE: 0x%08x\n",
> ee->instdone.instdone);
> @@ -445,8 +446,6 @@ static void error_print_instdone(struct
> drm_i915_error_state_buf *m,
> return;
>
> if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 50)) {
> - int iter;
> -
> for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice,
> subslice)
> err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
> slice, subslice,
> @@ -471,6 +470,13 @@ static void error_print_instdone(struct
> drm_i915_error_state_buf *m,
> if (GRAPHICS_VER(m->i915) < 12)
> return;
>
> + if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) {
> + for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice,
> subslice)
> + err_printf(m, " GEOM_SVGUNIT_INSTDONE[%d][%d]:
> 0x%08x\n",
> +slice, subslice,
> +ee->instdone.geom_svg[slice][subslice]);
> + }
> +
> err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n",
> ee->instdone.slice_common_extra[0]);
> err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n",
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b6ffdb89db6f..45cc76f88738 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2686,6 +2686,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108)
> #define GEN7_SAMPLER_INSTDONE_MMIO(0xe160)
> #define GEN7_ROW_INSTDONE_MMIO(0xe164)
> +#define XEHPG_INSTDONE_GEOM_SVG _MMIO(0x666c)
> #define MCFG_MCR_SELECTOR_MMIO(0xfd0)
> #define SF_MCR_SELECTOR _MMIO(0xfd8)
> #define GEN8_MCR_SELECTOR_MMIO(0xfdc)
> --
> 2.25.4
>
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Re: [Intel-gfx] [PATCH v3 22/30] drm/i915/dg2: Define MOCS table for DG2
On Fri, Jul 23, 2021 at 10:42:31AM -0700, Matt Roper wrote:
> Bspec: 45101, 45427
> Cc: Ramalingam C (v5)
> Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
> ---
> drivers/gpu/drm/i915/gt/intel_mocs.c | 35 +++-
> 1 file changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 0c9d0b936c20..d22ca8212092 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -341,6 +341,30 @@ static const struct drm_i915_mocs_entry
> xehpsdv_mocs_table[] = {
> MOCS_ENTRY(63, 0, L3_1_UC),
> };
>
> +static const struct drm_i915_mocs_entry dg2_mocs_table[] = {
> + /* UC - Coherent; GO:L3 */
> + MOCS_ENTRY(0, 0, L3_1_UC | L3_LKUP(1)),
> + /* UC - Coherent; GO:Memory */
> + MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
> + /* UC - Non-Coherent; GO:Memory */
> + MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),
> +
> + /* WB - LC */
> + MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
> +};
> +
> +static const struct drm_i915_mocs_entry dg2_mocs_table_g10_ax[] = {
> + /* Wa_14011441408: Set Go to Memory for MOCS#0 */
> + MOCS_ENTRY(0, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
> + /* UC - Coherent; GO:Memory */
> + MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
> + /* UC - Non-Coherent; GO:Memory */
> + MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),
> +
> + /* WB - LC */
> + MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
> +};
> +
> enum {
> HAS_GLOBAL_MOCS = BIT(0),
> HAS_ENGINE_MOCS = BIT(1),
> @@ -367,7 +391,16 @@ static unsigned int get_mocs_settings(const struct
> drm_i915_private *i915,
> {
> unsigned int flags;
>
> - if (IS_XEHPSDV(i915)) {
> + if (IS_DG2(i915)) {
> + if (IS_DG2_GT_STEP(i915, G10, STEP_A0, (STEP_B0 - 1))) {
> + table->size = ARRAY_SIZE(dg2_mocs_table_g10_ax);
> + table->table = dg2_mocs_table_g10_ax;
> + } else {
> + table->size = ARRAY_SIZE(dg2_mocs_table);
> + table->table = dg2_mocs_table;
> + }
> + table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> + } else if (IS_XEHPSDV(i915)) {
> table->size = ARRAY_SIZE(xehpsdv_mocs_table);
> table->table = xehpsdv_mocs_table;
> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> --
> 2.25.4
>
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Re: [Intel-gfx] [PATCH v6 10/15] drm/i915/pxp: interfaces for using protected objects
On 7/29/2021 4:10 AM, Rodrigo Vivi wrote:
On Wed, Jul 28, 2021 at 07:01:01PM -0700, Daniele Ceraolo Spurio wrote:
This api allow user mode to create protected buffers and to mark
contexts as making use of such objects. Only when using contexts
marked in such a way is the execution guaranteed to work as expected.
Contexts can only be marked as using protected content at creation time
(i.e. the parameter is immutable) and they must be both bannable and not
recoverable.
All protected objects and contexts that have backing storage will be
considered invalid when the PXP session is destroyed and all new
submissions using them will be rejected. All intel contexts within the
invalidated gem contexts will be marked banned. A new flag has been
added to the RESET_STATS ioctl to report the context invalidation to
userspace.
This patch was previously sent as 2 separate patches, which have been
squashed following a request to have all the uapi in a single patch.
I've retained the s-o-b from both.
v5: squash patches, rebase on proto_ctx, update kerneldoc
v6: rebase on obj create_ext changes
The "rebase" word led me to think it was a small change caused
only by rebasing conflicts, but then I spotted something on
i915_gem_create.c that I didn't remember seeing before.
Apologies for not being clear.
Since it took me a while to understand what was going on, let me
try to summarize to see if I got it right and to check
with others (Jason in special)
if we are aligned with the recent directions:
With the removal of the vanilla_object from the create_ext,
the addition of the flags was needed.
yes.
Then, instead of adding a new user_flags it adds the I915_BO_PROTECTED
to the existent flags (what is cleaner) but then it does
/* Add any flag set by create_ext options */
flags |= ext_flags;
on the new user_create_ext.
What shouldn't be a problem because the ext_flags is really only
the I915_BO_PROTECTED set by our new extension and immutable.
But I'm just trying to see if we are not opening any holes to accept
some undesired flags.
Apparently not.
ext_flags are not set directly by the user, but by the create_ext
extension functions, based on the extensions the user has provided. This
should allow the kernel to perform any required checks in the extension
functions before setting the flag (like it happens in this case for the
PXP option).
Am I getting things right? Anything else we should check in here?
yup, got it right.
Daniele
Thanks,
Rodrigo.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Bommu Krishnaiah
Cc: Rodrigo Vivi
Cc: Chris Wilson
Cc: Lionel Landwerlin
Cc: Jason Ekstrand
Cc: Daniel Vetter
Reviewed-by: Rodrigo Vivi #v5
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 68 --
drivers/gpu/drm/i915/gem/i915_gem_context.h | 18
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +
drivers/gpu/drm/i915/gem/i915_gem_create.c| 75
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 40 -
drivers/gpu/drm/i915/gem/i915_gem_object.c| 6 ++
drivers/gpu/drm/i915/gem/i915_gem_object.h| 12 +++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 89 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 15
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 5 ++
include/uapi/drm/i915_drm.h | 55 +++-
13 files changed, 371 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index cff72679ad7c..0cd3e2d06188 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -77,6 +77,8 @@
#include "gt/intel_gpu_commands.h"
#include "gt/intel_ring.h"
+#include "pxp/intel_pxp.h"
+
#include "i915_gem_context.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
@@ -241,6 +243,25 @@ static int proto_context_set_persistence(struct
drm_i915_private *i915,
return 0;
}
+static int proto_context_set_protected(struct drm_i915_private *i915,
+ struct i915_gem_proto_context *pc,
+ bool protected)
+{
+ int ret = 0;
+
+ if (!intel_pxp_is_enabled(&i915->gt.pxp))
+ ret = -ENODEV;
+ else if (!protected)
+ pc->user_flags &= ~BIT(UCONTEXT_PROTECTED);
+ else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) ||
+!(pc->user_flags & BIT(UCONTEXT_BANNABLE)))
+ ret = -EPERM;
+ else
+ pc->user_flags |= BIT(UCONTEXT_PROTECTED);
+
+ return ret;
+}
+
static struct i915_gem_proto_context *
proto_context_create(struct drm_i915_private *i915, unsigned int flags)
{
@@ -686,6 +707,8 @@ static int set_proto_ctx_param(struct drm_i915_file_private
*fpriv,
[Intel-gfx] [PATCH v2 3/6] drm/i915: Make shadow tables range-based
Rather than defining our shadow tables as a list of individual
registers, provide them as a list of register ranges; we'll have some
ranges of multiple registers being added soon (and we already have a
couple adjacent registers that we can squash into a single range now).
This change also defines the table with hex literal values rather than
symbolic register names; since that's how the tables are defined in the
bspec, this change will make it easier to review the tables overall.
v2:
- Force signed comparison on range overlap sanity check
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 +-
drivers/gpu/drm/i915/intel_uncore.c | 160 +-
drivers/gpu/drm/i915/intel_uncore.h | 6 +
drivers/gpu/drm/i915/selftests/intel_uncore.c | 32 ++--
4 files changed, 108 insertions(+), 103 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 9173df59821a..7558414bafb2 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1963,12 +1963,7 @@ void intel_engine_apply_workarounds(struct
intel_engine_cs *engine)
wa_list_apply(engine->gt, &engine->wa_list);
}
-struct mcr_range {
- u32 start;
- u32 end;
-};
-
-static const struct mcr_range mcr_ranges_gen8[] = {
+static const struct i915_range mcr_ranges_gen8[] = {
{ .start = 0x5500, .end = 0x55ff },
{ .start = 0x7000, .end = 0x7fff },
{ .start = 0x9400, .end = 0x97ff },
@@ -1977,7 +1972,7 @@ static const struct mcr_range mcr_ranges_gen8[] = {
{},
};
-static const struct mcr_range mcr_ranges_gen12[] = {
+static const struct i915_range mcr_ranges_gen12[] = {
{ .start = 0x8150, .end = 0x815f },
{ .start = 0x9520, .end = 0x955f },
{ .start = 0xb100, .end = 0xb3ff },
@@ -1986,7 +1981,7 @@ static const struct mcr_range mcr_ranges_gen12[] = {
{},
};
-static const struct mcr_range mcr_ranges_xehp[] = {
+static const struct i915_range mcr_ranges_xehp[] = {
{ .start = 0x4000, .end = 0x4aff },
{ .start = 0x5200, .end = 0x52ff },
{ .start = 0x5400, .end = 0x7fff },
@@ -2004,7 +1999,7 @@ static const struct mcr_range mcr_ranges_xehp[] = {
static bool mcr_range(struct drm_i915_private *i915, u32 offset)
{
- const struct mcr_range *mcr_ranges;
+ const struct i915_range *mcr_ranges;
int i;
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index ea910f7ee635..2cfbc16f7dee 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -946,101 +946,95 @@ static const struct intel_forcewake_range
__vlv_fw_ranges[] = {
find_fw_domain(uncore, offset)
/* *Must* be sorted by offset! See intel_shadow_table_check(). */
-static const i915_reg_t gen8_shadowed_regs[] = {
- RING_TAIL(RENDER_RING_BASE),/* 0x2000 (base) */
- GEN6_RPNSWREQ, /* 0xA008 */
- GEN6_RC_VIDEO_FREQ, /* 0xA00C */
- RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */
- RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */
- RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
+static const struct i915_range gen8_shadowed_regs[] = {
+ { .start = 0x2030, .end = 0x2030 },
+ { .start = 0xA008, .end = 0xA00C },
+ { .start = 0x12030, .end = 0x12030 },
+ { .start = 0x1a030, .end = 0x1a030 },
+ { .start = 0x22030, .end = 0x22030 },
/* TODO: Other registers are not yet used */
};
-static const i915_reg_t gen11_shadowed_regs[] = {
- RING_TAIL(RENDER_RING_BASE),/* 0x2000 (base) */
- RING_EXECLIST_CONTROL(RENDER_RING_BASE),/* 0x2550 */
- GEN6_RPNSWREQ, /* 0xA008 */
- GEN6_RC_VIDEO_FREQ, /* 0xA00C */
- RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
- RING_EXECLIST_CONTROL(BLT_RING_BASE), /* 0x22550 */
- RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C (base) */
- RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE), /* 0x1C0550 */
- RING_TAIL(GEN11_BSD2_RING_BASE),/* 0x1C4000 (base) */
- RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE),/* 0x1C4550 */
- RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */
- RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE), /* 0x1C8550 */
- RING_TAIL(GEN11_BSD3_RING_BASE),/* 0x1D (base) */
- RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE),/* 0x1D0550 */
- RING_TAIL(GEN11_BSD4_RING_BASE),/* 0x1D4000 (base) */
- RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE),/* 0x1D4550 */
- RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D800
Re: [Intel-gfx] [PATCH 01/14] drm/i915/guc/slpc: Initial definitions for SLPC
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Add macros to check for SLPC support. This feature is currently supported
> for Gen12+ and enabled whenever GuC submission is enabled/selected.
>
> Include templates for SLPC init/fini and enable.
>
> v2: Move SLPC helper functions to intel_guc_slpc.c/.h. Define basic
> template for SLPC structure in intel_guc_slpc_types.h. Fix copyright (Michal
> W)
>
> v3: Review comments (Michal W)
>
> v4: Include supported/selected inside slpc struct (Michal W)
>
> Reviewed-by: Michal Wajdeczko
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sundaresan Sujaritha
> Signed-off-by: Daniele Ceraolo Spurio
>
> drm/i915/guc/slpc: Lay out slpc init/enable/fini
>
> Declare init/fini and enable function templates.
>
> v2: Rebase
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sundaresan Sujaritha
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 +
> drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 45 +++
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 33 ++
> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 16 +++
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 ++-
> drivers/gpu/drm/i915/gt/uc/intel_uc.h | 2 +
> 8 files changed, 105 insertions(+), 2 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index ab7679957623..d8eac4468df9 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -186,6 +186,7 @@ i915-y += gt/uc/intel_uc.o \
> gt/uc/intel_guc_fw.o \
> gt/uc/intel_guc_log.o \
> gt/uc/intel_guc_log_debugfs.o \
> + gt/uc/intel_guc_slpc.o \
> gt/uc/intel_guc_submission.o \
> gt/uc/intel_huc.o \
> gt/uc/intel_huc_debugfs.o \
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 979128e28372..39bc3c16057b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -7,6 +7,7 @@
> #include "gt/intel_gt_irq.h"
> #include "gt/intel_gt_pm_irq.h"
> #include "intel_guc.h"
> +#include "intel_guc_slpc.h"
> #include "intel_guc_ads.h"
> #include "intel_guc_submission.h"
> #include "i915_drv.h"
> @@ -157,6 +158,7 @@ void intel_guc_init_early(struct intel_guc *guc)
> intel_guc_ct_init_early(&guc->ct);
> intel_guc_log_init_early(&guc->log);
> intel_guc_submission_init_early(guc);
> + intel_guc_slpc_init_early(&guc->slpc);
>
> mutex_init(&guc->send_mutex);
> spin_lock_init(&guc->irq_lock);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index a9547069ee7e..7da11a0b6059 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -15,6 +15,7 @@
> #include "intel_guc_ct.h"
> #include "intel_guc_log.h"
> #include "intel_guc_reg.h"
> +#include "intel_guc_slpc_types.h"
> #include "intel_uc_fw.h"
> #include "i915_utils.h"
> #include "i915_vma.h"
> @@ -30,6 +31,7 @@ struct intel_guc {
> struct intel_uc_fw fw;
> struct intel_guc_log log;
> struct intel_guc_ct ct;
> + struct intel_guc_slpc slpc;
>
> /* Global engine used to submit requests to GuC */
> struct i915_sched_engine *sched_engine;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> new file mode 100644
> index ..40950f1bf05c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -0,0 +1,45 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_guc_slpc.h"
> +#include "gt/intel_gt.h"
> +
> +static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
> +{
> + return container_of(slpc, struct intel_guc, slpc);
> +}
> +
> +static bool __detect_slpc_supported(struct intel_guc *guc)
> +{
> + /* GuC SLPC is unavailable for pre-Gen12 */
> + return guc->submission_supported &&
> + GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12;
> +}
> +
> +static bool __guc_slpc_selected(struct intel_guc *guc)
> +{
> + if (!intel_guc_slpc_is_supported(guc))
> + return false;
> +
> + return guc->submission_selected;
> +}
> +
> +void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
> +{
> + struct intel_guc *guc = slpc_to_guc(slpc);
> +
> + slpc->supported = __detect_slpc_supported(guc);
> + slpc->selected = __guc_slpc_selected(guc);
> +}
> +
> +int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
> +{
> + return 0;
> +}
> +
> +void
Re: [Intel-gfx] [PATCH 03/14] drm/i915/guc/slpc: Adding SLPC communication interfaces
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Add constants and params that are needed to configure SLPC.
>
> v2: Add a new abi header for SLPC. Replace bitfields with
> genmasks. Address other comments from Michal W.
>
> v3: Add slpc H2G format in abi, other review commments (Michal W)
>
> v4: Update status bits according to latest spec
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sundaresan Sujaritha
> ---
> .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 1 -
> .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 234 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 3 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 7 +
> 4 files changed, 244 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> index d832c8f11c11..ca538e5de940 100644
> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> @@ -135,7 +135,6 @@ enum intel_guc_action {
> INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT = 0x1007,
> INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008,
> INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
> - INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
> INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
> INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
> INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
> b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
> new file mode 100644
> index ..efd2487626f8
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
> @@ -0,0 +1,234 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#ifndef _GUC_ACTIONS_SLPC_ABI_H_
> +#define _GUC_ACTIONS_SLPC_ABI_H_
> +
> +#include
> +#include "i915_reg.h"
> +
> +/**
> + * DOC: SLPC SHARED DATA STRUCTURE
> + *
> + *
> ++--+--+
> + * | CL | Bytes| Description
> |
> + *
> ++==+==+
> + * | 1 | 0-3 | SHARED DATA SIZE
> |
> + * |
> +--+--+
> + * || 4-7 | GLOBAL STATE
> |
> + * |
> +--+--+
> + * || 8-11 | DISPLAY DATA ADDRESS
> |
> + * |
> +--+--+
> + * || 12:63| PADDING
> |
> + *
> ++--+--+
> + * || 0:63 | PADDING(PLATFORM INFO)
> |
> + *
> ++--+--+
> + * | 3 | 0-3 | TASK STATE DATA
> |
> + * +
> +--+--+
> + * || 4:63 | PADDING
> |
> + *
> ++--+--+
> + * |4-21|0:1087| OVERRIDE PARAMS AND BIT FIELDS
> |
> + *
> ++--+--+
> + * || | PADDING + EXTRA RESERVED PAGE
> |
> + *
> ++--+--+
> + */
> +
> +/*
> + * SLPC exposes certain parameters for global configuration by the host.
> + * These are referred to as override parameters, because in most cases
> + * the host will not need to modify the default values used by SLPC.
> + * SLPC remembers the default values which allows the host to easily restore
> + * them by simply unsetting the override. The host can set or unset override
> + * parameters during SLPC (re-)initialization using the SLPC Reset event.
> + * The host can also set or unset override parameters on the fly using the
> + * Parameter Set and Parameter Unset events
> + */
> +
> +#define SLPC_MAX_OVERRIDE_PARAMETERS 256
> +#define SLPC_OVERRIDE_BITFIELD_SIZE \
> + (SLPC_MAX_OVERRIDE_PARAMETERS / 32)
> +
> +#define SLPC_PAGE_SIZE_BYTES 4096
> +#define SLPC_CACHELINE_SIZE_BYTES64
> +#define SLPC_SHARED_DATA_SIZE_BYTE_HEADERSLPC_CACHELINE_SIZE_BYTES
> +#define SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO
> SLPC_CACHELINE_SIZE_BYTES
> +#define SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE
> SLPC_CACHELINE_SI
Re: [Intel-gfx] [PATCH 05/14] drm/i915/guc/slpc: Enable SLPC and add related H2G events
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Add methods for interacting with GuC for enabling SLPC. Enable
> SLPC after GuC submission has been established. GuC load will
> fail if SLPC cannot be successfully initialized. Add various
> helper methods to set/unset the parameters for SLPC. They can
> be set using H2G calls or directly setting bits in the shared
> data structure.
>
> v2: Address several review comments, add new helpers for
> decoding the SLPC min/max frequencies. Use masks instead of hardcoded
> constants. (Michal W)
>
> v3: Split global_state_to_string function, and check for positive
> non-zero return value from intel_guc_send() (Michal W)
>
> v4: Optimize the stringify function and other comments (Michal W)
>
> v5: Enable slpc as well before declaring GuC submission status (Michal W)
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sundaresan Sujaritha
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 226 ++
> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 2 +
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 11 +
> 3 files changed, 239 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index 6d76ea4c0ace..da3e1f8844a9 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -45,6 +45,40 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
> slpc->selected = __guc_slpc_selected(guc);
> }
>
> +static void slpc_mem_set_param(struct slpc_shared_data *data,
> + u32 id, u32 value)
> +{
> + GEM_BUG_ON(id >= SLPC_MAX_OVERRIDE_PARAMETERS);
> + /*
> + * When the flag bit is set, corresponding value will be read
> + * and applied by SLPC.
> + */
> + data->override_params.bits[id >> 5] |= (1 << (id % 32));
> + data->override_params.values[id] = value;
> +}
> +
> +static void slpc_mem_set_enabled(struct slpc_shared_data *data,
> + u8 enable_id, u8 disable_id)
> +{
> + /*
> + * Enabling a param involves setting the enable_id
> + * to 1 and disable_id to 0.
> + */
> + slpc_mem_set_param(data, enable_id, 1);
> + slpc_mem_set_param(data, disable_id, 0);
> +}
> +
> +static void slpc_mem_set_disabled(struct slpc_shared_data *data,
> + u8 enable_id, u8 disable_id)
> +{
> + /*
> + * Disabling a param involves setting the enable_id
> + * to 0 and disable_id to 1.
> + */
> + slpc_mem_set_param(data, disable_id, 1);
> + slpc_mem_set_param(data, enable_id, 0);
> +}
> +
> static int slpc_shared_data_init(struct intel_guc_slpc *slpc)
> {
> struct intel_guc *guc = slpc_to_guc(slpc);
> @@ -63,6 +97,121 @@ static int slpc_shared_data_init(struct intel_guc_slpc
> *slpc)
> return err;
> }
>
> +static u32 slpc_get_state(struct intel_guc_slpc *slpc)
> +{
> + struct slpc_shared_data *data;
> +
> + GEM_BUG_ON(!slpc->vma);
> +
> + drm_clflush_virt_range(slpc->vaddr, sizeof(u32));
> + data = slpc->vaddr;
> +
> + return data->header.global_state;
> +}
> +
> +static bool slpc_is_running(struct intel_guc_slpc *slpc)
> +{
> + return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
> +}
> +
> +static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)
> +{
> + u32 request[] = {
> + GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
> + SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
> + offset,
> + 0,
> + };
> + int ret;
> +
> + ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
> +
> + return ret > 0 ? -EPROTO : ret;
> +}
> +
> +static int slpc_query_task_state(struct intel_guc_slpc *slpc)
> +{
> + struct intel_guc *guc = slpc_to_guc(slpc);
> + struct drm_i915_private *i915 = slpc_to_i915(slpc);
> + u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
> + int ret;
> +
> + ret = guc_action_slpc_query(guc, offset);
> + if (ret)
unlikely(ret) ?
> + drm_err(&i915->drm, "Failed to query task state (%pe)\n",
> + ERR_PTR(ret));
is this indent correct ?
> +
> + drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
> +
> + return ret;
> +}
> +
> +static const char *slpc_global_state_to_string(enum slpc_global_state state)
> +{
> + switch (state) {
> + case SLPC_GLOBAL_STATE_NOT_RUNNING:
> + return "not running";
> + case SLPC_GLOBAL_STATE_INITIALIZING:
> + return "initializing";
> + case SLPC_GLOBAL_STATE_RESETTING:
> + return "resetting";
> + case SLPC_GLOBAL_STATE_RUNNING:
> + return "running";
> + case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
> + return "shutting down";
> + case SLPC_GLOBAL_STATE_ERROR:
> + return "error";
> + default:
> + return "unknown";
> + }
> +}
> +
> +st
Re: [Intel-gfx] [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Cache rp0, rp1 and rpn platform limits into SLPC structure
> for range checking while setting min/max frequencies.
>
> Also add "soft" limits which keep track of frequency changes
> made from userland. These are initially set to platform min
> and max.
>
> v2: Address review comments (Michal W)
> v3: Formatting (Michal W)
> v4: Add separate function to parse rp values (Michal W)
> v5: Perform range checking for set min/max (Michal W)
>
> Signed-off-by: Vinay Belgaumkar
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 115 ++
> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 9 ++
> drivers/gpu/drm/i915/i915_reg.h | 3 +
> 3 files changed, 127 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index 742918875593..bfd5fb0751fd 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -94,6 +94,9 @@ static int slpc_shared_data_init(struct intel_guc_slpc
> *slpc)
> return err;
> }
>
> + slpc->max_freq_softlimit = 0;
> + slpc->min_freq_softlimit = 0;
shouldn't this be in intel_guc_slpc_init() ?
> +
> return err;
> }
>
> @@ -124,6 +127,18 @@ static int guc_action_slpc_set_param(struct intel_guc
> *guc, u8 id, u32 value)
> return ret > 0 ? -EPROTO : ret;
> }
>
> +static int guc_action_slpc_unset_param(struct intel_guc *guc, u8 id)
> +{
> + u32 request[] = {
> + GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
> + SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 2),
> + id,
> + };
> +
> + return intel_guc_send(guc, request, ARRAY_SIZE(request));
> +}
> +
> +
> static bool slpc_is_running(struct intel_guc_slpc *slpc)
> {
> return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
> @@ -177,6 +192,16 @@ static int slpc_set_param(struct intel_guc_slpc *slpc,
> u8 id, u32 value)
> return ret;
> }
>
> +static int slpc_unset_param(struct intel_guc_slpc *slpc,
> + u8 id)
> +{
> + struct intel_guc *guc = slpc_to_guc(slpc);
> +
> + GEM_BUG_ON(id >= SLPC_MAX_PARAM);
> +
> + return guc_action_slpc_unset_param(guc, id);
> +}
> +
> static const char *slpc_global_state_to_string(enum slpc_global_state state)
> {
> switch (state) {
> @@ -307,6 +332,11 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc
> *slpc, u32 val)
> intel_wakeref_t wakeref;
> int ret;
>
> + if ((val < slpc->min_freq) ||
> + (val > slpc->rp0_freq) ||
> + (val < slpc->min_freq_softlimit))
> + return -EINVAL;
> +
> with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
> ret = slpc_set_param(slpc,
> SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
> @@ -317,6 +347,8 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc
> *slpc, u32 val)
> ret = -EIO;
> }
>
> + slpc->max_freq_softlimit = val;
> +
> return ret;
> }
>
> @@ -363,6 +395,11 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc
> *slpc, u32 val)
> intel_wakeref_t wakeref;
> int ret;
>
> + if ((val < slpc->min_freq) ||
> + (val > slpc->rp0_freq) ||
> + (val > slpc->max_freq_softlimit))
> + return -EINVAL;
> +
> with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
> ret = slpc_set_param(slpc,
> SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
> @@ -373,6 +410,8 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc
> *slpc, u32 val)
> ret = -EIO;
> }
>
> + slpc->min_freq_softlimit = val;
> +
> return ret;
> }
>
> @@ -418,6 +457,71 @@ void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
> GEN6_PMINTRMSK, pm_intrmsk_mbz, 0);
> }
>
> +static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
> +{
> + int ret = 0;
> +
> + /*
> + * Softlimits are initially equivalent to platform limits
> + * unless they have deviated from defaults, in which case,
> + * we retain the values and set min/max accordingly.
> + */
> + if (!slpc->max_freq_softlimit)
> + slpc->max_freq_softlimit = slpc->rp0_freq;
> + else if (slpc->max_freq_softlimit != slpc->rp0_freq)
> + ret = intel_guc_slpc_set_max_freq(slpc,
> + slpc->max_freq_softlimit);
if this fails, shouldn't we reset max_freq_softlimit to platform limit ?
otherwise we could be with some potentially bad value forever
> +
> + if (!slpc->min_freq_softlimit)
> + slpc->min_freq_softlimit = slpc->min_freq;
> + else if (slpc->min_freq_softlimit != slpc->min_freq)
> + ret = intel_guc_slpc_set_min_freq(slpc,
> + slpc->min_freq_softlimit);
similar h
[Intel-gfx] [PATCH v1.1 14/25] drm/i915/display: remove CNL ddi buf translation tables
The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly.
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
v1.1: rebase
drivers/gpu/drm/i915/display/intel_ddi.c | 12 +-
.../drm/i915/display/intel_ddi_buf_trans.c| 676 ++
.../drm/i915/display/intel_ddi_buf_trans.h| 4 +-
3 files changed, 214 insertions(+), 478 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6e6d37b97c51..a989a56fc9ff 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1055,8 +1055,8 @@ static void icl_ddi_combo_vswing_program(struct
intel_encoder *encoder,
val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
RCOMP_SCALAR_MASK);
- val |=
SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel);
- val |=
SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel);
+ val |=
SWING_SEL_UPPER(ddi_translations->entries[level].icl.dw2_swing_sel);
+ val |=
SWING_SEL_LOWER(ddi_translations->entries[level].icl.dw2_swing_sel);
/* Program Rcomp scalar for every table entry */
val |= RCOMP_SCALAR(0x98);
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
@@ -1067,16 +1067,16 @@ static void icl_ddi_combo_vswing_program(struct
intel_encoder *encoder,
val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
CURSOR_COEFF_MASK);
- val |=
POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1);
- val |=
POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2);
- val |=
CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff);
+ val |=
POST_CURSOR_1(ddi_translations->entries[level].icl.dw4_post_cursor_1);
+ val |=
POST_CURSOR_2(ddi_translations->entries[level].icl.dw4_post_cursor_2);
+ val |=
CURSOR_COEFF(ddi_translations->entries[level].icl.dw4_cursor_coeff);
intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
}
/* Program PORT_TX_DW7 */
val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
val &= ~N_SCALAR_MASK;
- val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar);
+ val |= N_SCALAR(ddi_translations->entries[level].icl.dw7_n_scalar);
intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 923c962e86a3..ba2c08f1a797 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -417,199 +417,19 @@ static const struct intel_ddi_buf_trans
bxt_ddi_translations_hdmi = {
.hdmi_default_entry = ARRAY_SIZE(_bxt_ddi_translations_hdmi) - 1,
};
-/* Voltage Swing Programming for VccIO 0.85V for DP */
-static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_dp_0_85V[]
= {
- /* NT mV Trans mV db
*/
- { .cnl = { 0xA, 0x5D, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0
*/
- { .cnl = { 0xA, 0x6A, 0x38, 0x00, 0x07 } }, /* 350 500 3.1
*/
- { .cnl = { 0xB, 0x7A, 0x32, 0x00, 0x0D } }, /* 350 700 6.0
*/
- { .cnl = { 0x6, 0x7C, 0x2D, 0x00, 0x12 } }, /* 350 900 8.2
*/
- { .cnl = { 0xA, 0x69, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0
*/
- { .cnl = { 0xB, 0x7A, 0x36, 0x00, 0x09 } }, /* 500 700 2.9
*/
- { .cnl = { 0x6, 0x7C, 0x30, 0x00, 0x0F } }, /* 500 900 5.1
*/
- { .cnl = { 0xB, 0x7D, 0x3C, 0x00, 0x03 } }, /* 650 725 0.9
*/
- { .cnl = { 0x6, 0x7C, 0x34, 0x00, 0x0B } }, /* 600 900 3.5
*/
- { .cnl = { 0x6, 0x7B, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0
*/
-};
-
-static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_0_85V = {
- .entries = _cnl_ddi_translations_dp_0_85V,
- .num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_0_85V),
-};
-
-/* Voltage Swing Programming for VccIO 0.85V for HDMI */
-static const union intel_ddi_buf_trans_entry
_cnl_ddi_translations_hdmi_0_85V[] = {
- /* NT mV Trans mV db
*/
- { .cnl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0
*/
- { .cnl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450 650 3.2
*/
- { .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 450 850 5.5
*/
- { .cnl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } }, /* 650 650 0.0
*/
- { .cnl = { 0x6, 0x7F
Re: [Intel-gfx] [PATCH 07/14] drm/i915/guc/slpc: Add methods to set min/max frequency
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Add param set h2g helpers to set the min and max frequencies
> for use by SLPC.
>
> v2: Address review comments (Michal W)
> v3: Check for positive error code (Michal W)
> v4: Print generic error in set_param (Michal W)
>
> Signed-off-by: Sundaresan Sujaritha
> Signed-off-by: Vinay Belgaumkar
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 89 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 +
> 2 files changed, 91 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index da3e1f8844a9..0959cc9e104a 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -109,6 +109,21 @@ static u32 slpc_get_state(struct intel_guc_slpc *slpc)
> return data->header.global_state;
> }
>
> +static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
> +{
> + u32 request[] = {
> + GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
> + SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2),
> + id,
> + value,
> + };
> + int ret;
> +
> + ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
> +
> + return ret > 0 ? -EPROTO : ret;
> +}
> +
> static bool slpc_is_running(struct intel_guc_slpc *slpc)
> {
> return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
> @@ -146,6 +161,22 @@ static int slpc_query_task_state(struct intel_guc_slpc
> *slpc)
> return ret;
> }
>
> +static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
> +{
> + struct intel_guc *guc = slpc_to_guc(slpc);
> + struct drm_i915_private *i915 = slpc_to_i915(slpc);
> + int ret;
> +
> + GEM_BUG_ON(id >= SLPC_MAX_PARAM);
> +
> + ret = guc_action_slpc_set_param(guc, id, value);
> + if (ret)
> + drm_err(&i915->drm, "Failed to set param %d to %u (%pe)\n",
> + id, value, ERR_PTR(ret));
> +
> + return ret;
> +}
> +
> static const char *slpc_global_state_to_string(enum slpc_global_state state)
> {
> switch (state) {
> @@ -260,6 +291,64 @@ static void slpc_shared_data_reset(struct
> slpc_shared_data *data)
> SLPC_PARAM_TASK_DISABLE_DCC);
> }
>
> +/**
> + * intel_guc_slpc_set_max_freq() - Set max frequency limit for SLPC.
> + * @slpc: pointer to intel_guc_slpc.
> + * @val: frequency (MHz)
> + *
> + * This function will invoke GuC SLPC action to update the max frequency
> + * limit for unslice.
> + *
> + * Return: 0 on success, non-zero error code on failure.
> + */
> +int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
> +{
> + struct drm_i915_private *i915 = slpc_to_i915(slpc);
> + intel_wakeref_t wakeref;
> + int ret;
> +
> + with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
> + ret = slpc_set_param(slpc,
> +SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
> +val);
> +
> + /* Return standardized err code for sysfs calls */
> + if (ret)
> + ret = -EIO;
> + }
> +
> + return ret;
> +}
> +
> +/**
> + * intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
> + * @slpc: pointer to intel_guc_slpc.
> + * @val: frequency (MHz)
> + *
> + * This function will invoke GuC SLPC action to update the min unslice
> + * frequency.
> + *
> + * Return: 0 on success, non-zero error code on failure.
> + */
> +int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
> +{
> + struct drm_i915_private *i915 = slpc_to_i915(slpc);
> + intel_wakeref_t wakeref;
> + int ret;
> +
> + with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
> + ret = slpc_set_param(slpc,
> +SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
> +val);
> +
> + /* Return standardized err code for sysfs calls */
> + if (ret)
> + ret = -EIO;
> + }
> +
> + return ret;
> +}
> +
> /*
> * intel_guc_slpc_enable() - Start SLPC
> * @slpc: pointer to intel_guc_slpc.
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> index bc139682ad0f..788d87ff7b58 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
> @@ -29,5 +29,7 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc);
> int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
> int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
> void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
> +int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val);
> +int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val);
>
> #endif
>
Reviewed-by: Michal Wajdeczko
___
Intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/dp: DPTX writes Swing/Pre-emphs(DPCD 0x103-0x106) requested during PHY Layer testing
On Fri, Feb 26, 2021 at 12:15:54AM -0800, Khaled Almahallawy wrote: > Source needs to write DPCD 103-106 after receiving a PHY request to change > swing/pre-emphasis after reading DPCD 206-207. This is especially needed if > there is a retimer between source and sink and the retimer implements AUX_CH > interception scheme to manage DP PHY settings (e.g. adjusting > Swing/Pre-emphasis > equalization level) for DP output channel. If the source doesn't write to > DPCD 103-106, the retimer may not output the requested swing/pre-emphasis and > eventually we fail compliance. > > v2: Rebase and use crtc->lane_count (Imre) > > Signed-off-by: Khaled Almahallawy Reviewed-by: Imre Deak Sorry for the delay, pushed now, thanks for the patch. > --- > drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 2ec82a5c9f24..1ccf8602b3ef 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -4471,6 +4471,9 @@ static void intel_dp_process_phy_request(struct > intel_dp *intel_dp, > > intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state); > > + drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, > + intel_dp->train_set, crtc_state->lane_count); > + > drm_dp_set_phy_test_pattern(&intel_dp->aux, data, > link_status[DP_DPCD_REV]); > } > -- > 2.25.1 > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 03/18] drm/i915/dg2: Add forcewake table
The DG2 forcewake table is very similar to the one used by XeHP SDV (and
both platforms are even presented as a single table in the bspec). For
the most part DG2 starts using a few additional ranges that were
'reserved' on XeHP SDV and stops using some others. However there is a
single range (0xd800-0xd87f) that needs to be handled differently
between the two platforms (it needs GT wake on XeHP SDV, but render wake
on DG2) so unless we want to wake both domains (which could waste power)
or define new types of forcewake domains for this special case we need
to have separate tables for the two platforms. Let's define the ranges
for both platforms with a parameterized macro so that we don't actually
need to duplicate everything in the code.
It should be fine for DG2 to re-use the Xe_HP shadow register list so we
can continue to use the 'xehpsdv' MMIO write functions and don't need to
spin up a separate DG2 instance.
Bspec: 66534
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_uncore.c | 305 +++-
1 file changed, 168 insertions(+), 137 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 8cf53f54559d..6b38bc2811c1 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1317,143 +1317,170 @@ static const struct intel_forcewake_range
__gen12_fw_ranges[] = {
0x1d3f00 - 0x1d3fff: VD2 */
};
-/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
-static const struct intel_forcewake_range __xehp_fw_ranges[] = {
- GEN_FW_RANGE(0x0, 0x1fff, 0), /*
- 0x0 - 0xaff: reserved
- 0xb00 - 0x1fff: always on */
- GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT),
- GEN_FW_RANGE(0x4b00, 0x51ff, 0), /*
- 0x4b00 - 0x4fff: reserved
- 0x5000 - 0x51ff: always on */
- GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
- GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x8160, 0x81ff, 0), /*
- 0x8160 - 0x817f: reserved
- 0x8180 - 0x81ff: always on */
- GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT),
- GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /*
- 0x8500 - 0x87ff: gt
- 0x8800 - 0x8fff: reserved
- 0x9000 - 0x947f: gt
- 0x9480 - 0x94cf: reserved */
- GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x9560, 0x97ff, 0), /*
- 0x9560 - 0x95ff: always on
- 0x9600 - 0x97ff: reserved */
- GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
- 0x9800 - 0xb4ff: gt
- 0xb500 - 0xbfff: reserved
- 0xc000 - 0xcfff: gt */
- GEN_FW_RANGE(0xd000, 0xd7ff, 0),
- GEN_FW_RANGE(0xd800, 0xdbff, FORCEWAKE_GT),
- GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
- 0xdd00 - 0xddff: gt
- 0xde00 - 0xde7f: reserved */
- GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
- 0xde80 - 0xdfff: render
- 0xe000 - 0xe0ff: reserved
- 0xe100 - 0xe8ff: render */
- GEN_FW_RANGE(0xe900, 0x, FORCEWAKE_GT), /*
- 0xe900 - 0xe9ff: gt
- 0xea00 - 0xefff: reserved
- 0xf000 - 0x: gt */
- GEN_FW_RANGE(0x1, 0x13fff, 0), /*
- 0x1 - 0x11fff: reserved
- 0x12000 - 0x127ff: always on
- 0x12800 - 0x13fff: reserved */
- GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0),
- GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2),
- GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4),
- GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6),
- GEN_FW_RANGE(0x14800, 0x1, FORCEWAKE_RENDER), /*
- 0x14800 - 0x14fff: render
- 0x15000 - 0x16dff: reserved
- 0x16e00 - 0x1: render */
- GEN_FW_RANGE(0x2, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /*
- 0x2 - 0x20fff: VD0
- 0x21000 - 0x21fff: reserved */
- GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
- GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
- 0x24000 - 0x2407f: always on
- 0x24080 - 0x2417f: reserved */
- GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /*
- 0x24180 - 0x241ff: gt
- 0x24200 - 0x249ff: reserved */
- GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /*
- 0x24a00 - 0x24a7f: render
- 0x24a80 - 0x251ff: reserved */
- GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /*
- 0x25200 - 0x252ff: gt
- 0x25300 - 0x25
[Intel-gfx] [PATCH v4 00/18] Begin enabling Xe_HP SDV and DG2 platforms
This series provides some of the initial enablement patches for two upcoming discrete GPUs: * XeHP SDV: Xe_HP (version 12.50) graphics IP, no display IP * DG2: Xe_HPG (version 12.55) graphics IP, Xe_LPD (version 13) display IP Both platforms will need additional enablement patches beyond what's present in this series before they're truly usable, including various LMEM and GuC work that's already happening separately. The new features/functionality that these platforms bring (such as multi-tile support, dedicated compute engines, etc.) may be referenced in passing in some of these patches but will be fully enabled in future series. v2: - General rebase and incorporation of r-b's. - Re-order intel_gt_info and intel_device_info structures to eliminate some unnecessary padding after the size change of intel_engine_mask_t. (Tvrtko) - Use 'intel_step' mechanisms for revid->stepping mapping. (Jani) - Drop the DSC patches for now; they need some rework. (Jani) v3: - About 20 of the patches have landed upstream now. Rebase and resend the rest. Some of these are already reviewed, but have dependencies on other unreviewed patches (e.g., the new engine definitions, the initial SNPS PHY support, etc.). v4: - Several more patches have landed upstream; rebase and re-send the rest. Some of the remaining patches are reviewed but still have dependencies on non-reviewed patches, so the order is shuffled this time to group patches by dependency rather than by xehp vs xehpsdv vs dg2. - Minor cleanup to "drm/i915/xehp: handle new steering options" suggested by Caz. Cc: Rodrigo Vivi Cc: Lucas De Marchi Cc: James Ausmus Akeem G Abodunrin (1): drm/i915/dg2: Add new LRI reg offsets Ankit Nautiyal (1): drm/i915/dg2: Configure PCON in DP pre-enable path Daniele Ceraolo Spurio (1): drm/i915/xehp: handle new steering options Lucas De Marchi (2): drm/i915/xehpsdv: Define MOCS table for XeHP SDV drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper (11): drm/i915/xehpsdv: Define steering tables drm/i915/dg2: Add forcewake table drm/i915/dg2: Update LNCF steering ranges drm/i915/dg2: Add SQIDI steering drm/i915/xehp: Loop over all gslices for INSTDONE processing drm/i915/dg2: Report INSTDONE_GEOM values in error state drm/i915/xehpsdv: Add maximum sseu limits drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV drm/i915/dg2: Define MOCS table for DG2 drm/i915/xehpsdv: Read correct RP_STATE_CAP register drm/i915/dg2: Maintain backward-compatible nested batch behavior Matthew Auld (1): drm/i915/xehp: Changes to ss/eu definitions Stuart Summers (1): drm/i915/xehpsdv: Add compute DSS type drivers/gpu/drm/i915/display/intel_ddi.c | 3 + drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 8 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c| 55 ++-- drivers/gpu/drm/i915/gt/intel_engine_types.h | 15 +- drivers/gpu/drm/i915/gt/intel_gt.c | 68 - drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 + drivers/gpu/drm/i915/gt/intel_lrc.c | 85 +- drivers/gpu/drm/i915/gt/intel_mocs.c | 66 +++- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 1 + drivers/gpu/drm/i915/gt/intel_rps.c | 19 +- drivers/gpu/drm/i915/gt/intel_rps.h | 1 + drivers/gpu/drm/i915/gt/intel_sseu.c | 116 +-- drivers/gpu/drm/i915/gt/intel_sseu.h | 20 +- drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 155 +- drivers/gpu/drm/i915/i915_debugfs.c | 8 +- drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_getparam.c | 6 +- drivers/gpu/drm/i915/i915_gpu_error.c| 36 ++- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 15 +- drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_uncore.c | 305 ++- include/uapi/drm/i915_drm.h | 3 - 24 files changed, 771 insertions(+), 228 deletions(-) -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 02/18] drm/i915/xehpsdv: Define steering tables
Define and initialize the MMIO ranges for which XeHP SDV requires MSLICE
and LNCF steering.
Bspec: 66534
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 19 ++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +--
2 files changed, 27 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 39b224600f38..8e13bfc81634 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -89,6 +89,20 @@ static const struct intel_mmio_range
icl_l3bank_steering_table[] = {
{},
};
+static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
+ { 0x004000, 0x004AFF },
+ { 0x00C800, 0x00CFFF },
+ { 0x00DD00, 0x00DDFF },
+ { 0x00E900, 0x00 }, /* 0xEA00 - OxEFFF is unused */
+ {},
+};
+
+static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
+ { 0x00B000, 0x00B0FF },
+ { 0x00D800, 0x00D8FF },
+ {},
+};
+
static u16 slicemask(struct intel_gt *gt, int count)
{
u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
@@ -115,7 +129,10 @@ int intel_gt_init_mmio(struct intel_gt *gt)
(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
GEN12_MEML3_EN_MASK);
- if (GRAPHICS_VER(i915) >= 11 &&
+ if (IS_XEHPSDV(i915)) {
+ gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
+ gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
+ } else if (GRAPHICS_VER(i915) >= 11 &&
GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
gt->steering_table[L3BANK] = icl_l3bank_steering_table;
gt->info.l3bank_mask =
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index f2ceabb0e2ea..8717337a6c81 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -934,7 +934,6 @@ icl_wa_init_mcr(struct drm_i915_private *i915, struct
i915_wa_list *wal)
__add_mcr_wa(i915, wal, slice, subslice);
}
-__maybe_unused
static void
xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{
@@ -1136,10 +1135,18 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
VSUNIT_CLKGATE_DIS_TGL);
}
+static void
+xehpsdv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
+{
+ xehp_init_mcr(&i915->gt, wal);
+}
+
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_DG1(i915))
+ if (IS_XEHPSDV(i915))
+ xehpsdv_gt_workarounds_init(i915, wal);
+ else if (IS_DG1(i915))
dg1_gt_workarounds_init(i915, wal);
else if (IS_TIGERLAKE(i915))
tgl_gt_workarounds_init(i915, wal);
--
2.25.4
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[Intel-gfx] [PATCH v4 05/18] drm/i915/dg2: Add SQIDI steering
Although DG2_G10 platforms will always have all SQIDI's present and
don't need steering for registers in a SQIDI MMIO range, this isn't true
for DG2_G11 platforms; only SQIDI's 2 and 3 can be used on those.
We handle SQIDI ranges a bit differently from other types of explicit
steering. The SQIDI ranges belong to either the MCFG unit or the SF
unit, both of which have their own dedicated steering registers and do
not use the typical 0xFDC steering control that all other types of
ranges use. Thus we only need to worry about picking a valid initial
value for the MCFG and SF steering registers (0xFD0 and 0xFD8
resepectively) at driver init; they won't change after we set them up so
we don't need to worry about re-steering them explicitly at runtime.
Given that any SQIDI value should work fine for DG2-G10 and XeHP SDV,
while only values of 2 and 3 are valid for DG2-G11, we'll just
initialize the MCFG and SF steering registers to a constant value of "2"
for all XeHP-based platforms for simplicity --- that will work in all
cases.
Bspec: 66534
Cc: Radhakrishna Sripada
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 28 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 8717337a6c81..6895b083523d 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -889,17 +889,24 @@ cfl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
}
-static void __add_mcr_wa(struct drm_i915_private *i915, struct i915_wa_list
*wal,
-unsigned slice, unsigned subslice)
+static void __set_mcr_steering(struct i915_wa_list *wal,
+ i915_reg_t steering_reg,
+ unsigned int slice, unsigned int subslice)
{
u32 mcr, mcr_mask;
mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
- drm_dbg(&i915->drm, "MCR slice/subslice = %x\n", mcr);
+ wa_write_clr_set(wal, steering_reg, mcr_mask, mcr);
+}
+
+static void __add_mcr_wa(struct drm_i915_private *i915, struct i915_wa_list
*wal,
+unsigned int slice, unsigned int subslice)
+{
+ drm_dbg(&i915->drm, "MCR slice=0x%x, subslice=0x%x\n", slice, subslice);
- wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
+ __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice);
}
static void
@@ -953,7 +960,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
* - L3 Bank (fusable)
* - MSLICE (fusable)
* - LNCF (sub-unit within mslice; always present if mslice is present)
-* - SQIDI (always on)
*
* We'll do our default/implicit steering based on GSLICE (in the
* sliceid field) and DSS (in the subsliceid field). If we can
@@ -1003,6 +1009,18 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list
*wal)
WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
__add_mcr_wa(i915, wal, slice, subslice);
+
+ /*
+* SQIDI ranges are special because they use different steering
+* registers than everything else we work with. On XeHP SDV and
+* DG2-G10, any value in the steering registers will work fine since
+* all instances are present, but DG2-G11 only has SQIDI instances at
+* ID's 2 and 3, so we need to steer to one of those. For simplicity
+* we'll just steer to a hardcoded "2" since that value will work
+* everywhere.
+*/
+ __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2);
+ __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f4113e7e8271..39ce6befff52 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2757,6 +2757,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108)
#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
#define GEN7_ROW_INSTDONE _MMIO(0xe164)
+#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
+#define SF_MCR_SELECTOR_MMIO(0xfd8)
#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
#define GEN8_MCR_SLICE(slice)(((slice) & 3) << 26)
#define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
--
2.25.4
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[Intel-gfx] [PATCH v4 04/18] drm/i915/dg2: Update LNCF steering ranges
DG2's replicated register ranges are almost the same at XeHP SDV with
the exception of one LNCF sub-range that switches to gslice steering.
We can re-use the XeHP SDV mslice steering table and just provide a
DG2-specific LNCF steering table.
Bspec: 66534
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 8e13bfc81634..1971e34da254 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -103,6 +103,12 @@ static const struct intel_mmio_range
xehpsdv_lncf_steering_table[] = {
{},
};
+static const struct intel_mmio_range dg2_lncf_steering_table[] = {
+ { 0x00B000, 0x00B0FF },
+ { 0x00D880, 0x00D8FF },
+ {},
+};
+
static u16 slicemask(struct intel_gt *gt, int count)
{
u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
@@ -129,7 +135,10 @@ int intel_gt_init_mmio(struct intel_gt *gt)
(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
GEN12_MEML3_EN_MASK);
- if (IS_XEHPSDV(i915)) {
+ if (IS_DG2(i915)) {
+ gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
+ gt->steering_table[LNCF] = dg2_lncf_steering_table;
+ } else if (IS_XEHPSDV(i915)) {
gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
} else if (GRAPHICS_VER(i915) >= 11 &&
--
2.25.4
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[Intel-gfx] [PATCH v4 01/18] drm/i915/xehp: handle new steering options
From: Daniele Ceraolo Spurio
Xe_HP is more modular than its predecessors and as a consequence it has
more types of replicated registers. As with l3bank regions on previous
platforms, we may need to explicitly re-steer accesses to these new
types of ranges at runtime if we can't find a single default steering
value that satisfies the fusing of all types.
v2:
- Add a local 'i915' variable to reduce gt->i915 usage. (Caz)
- Drop unused 'intel_gt_read_register' prototype. (Caz)
Bspec: 66534
Cc: Tvrtko Ursulin
Cc: Caz Yokoyama
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 42 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h| 7 ++
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.c| 18 +
drivers/gpu/drm/i915/gt/intel_sseu.h| 6 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 89 +++--
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 4 +
drivers/gpu/drm/i915/intel_device_info.h| 1 +
10 files changed, 166 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index a64aa43f7cd9..39b224600f38 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -89,18 +89,40 @@ static const struct intel_mmio_range
icl_l3bank_steering_table[] = {
{},
};
+static u16 slicemask(struct intel_gt *gt, int count)
+{
+ u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
+
+ return intel_slicemask_from_dssmask(dss_mask, count);
+}
+
int intel_gt_init_mmio(struct intel_gt *gt)
{
+ struct drm_i915_private *i915 = gt->i915;
+
intel_gt_init_clock_frequency(gt);
intel_uc_init_mmio(>->uc);
intel_sseu_info_init(gt);
- if (GRAPHICS_VER(gt->i915) >= 11) {
+ /*
+* An mslice is unavailable only if both the meml3 for the slice is
+* disabled *and* all of the DSS in the slice (quadrant) are disabled.
+*/
+ if (HAS_MSLICES(i915))
+ gt->info.mslice_mask =
+ slicemask(gt, GEN_DSS_PER_MSLICE) |
+ (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
+GEN12_MEML3_EN_MASK);
+
+ if (GRAPHICS_VER(i915) >= 11 &&
+ GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
gt->steering_table[L3BANK] = icl_l3bank_steering_table;
gt->info.l3bank_mask =
~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
GEN10_L3BANK_MASK;
+ } else if (HAS_MSLICES(i915)) {
+ MISSING_CASE(INTEL_INFO(i915)->platform);
}
return intel_engines_init_mmio(gt);
@@ -787,6 +809,24 @@ static void intel_gt_get_valid_steering(struct intel_gt
*gt,
*sliceid = 0; /* unused */
*subsliceid = __ffs(gt->info.l3bank_mask);
break;
+ case MSLICE:
+ GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be
impossible! */
+
+ *sliceid = __ffs(gt->info.mslice_mask);
+ *subsliceid = 0;/* unused */
+ break;
+ case LNCF:
+ GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be
impossible! */
+
+ /*
+* 0xFDC[29:28] selects the mslice to steer to and 0xFDC[27]
+* selects which LNCF within the mslice to steer to. An LNCF
+* is always present if its mslice is present, so we can safely
+* just steer to LNCF 0 in all cases.
+*/
+ *sliceid = __ffs(gt->info.mslice_mask) << 1;
+ *subsliceid = 0;/* unused */
+ break;
default:
MISSING_CASE(type);
*sliceid = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 97a5075288d2..a81e21bf1bd1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -47,9 +47,14 @@ struct intel_mmio_range {
* of multicast registers. If another type of steering does not have any
* overlap in valid steering targets with 'subslice' style registers, we will
* need to explicitly re-steer reads of registers of the other type.
+ *
+ * Only the replication types that may need additional non-default steering
+ * are listed here.
*/
enum intel_steering_type {
L3BANK,
+ MSLICE,
+ LNCF,
NUM_STEERING_TYPES
};
@@ -184,6 +189,8 @@ struct intel_gt {
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
+
+ unsigned long mslice_mask;
} info;
};
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/driver
[Intel-gfx] [PATCH v4 08/18] drm/i915/xehp: Changes to ss/eu definitions
From: Matthew Auld
Xe_HP no longer has "slices" in the same way that old platforms did.
There are new concepts (gslices, cslices, mslices) that apply in various
contexts, but for the purposes of fusing slices no longer exist and we
just have one large pool of dual-subslices (DSS) to work with.
Furthermore, the meaning of the DSS fuse is inverted compared to past
platforms --- it now specifies which DSS are enabled rather than which
ones are disabled.
Cc: Rodrigo Vivi
Cc: Lucas De Marchi
Cc: Tvrtko Ursulin
Signed-off-by: Matthew Auld
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Stuart Summers
Signed-off-by: Matt Roper
Signed-off-by: Prasad Nallani
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 24
drivers/gpu/drm/i915/i915_getparam.c | 6 --
drivers/gpu/drm/i915/i915_reg.h | 3 +++
3 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index bbed8e8625e1..5d1b7d06c96b 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -139,17 +139,33 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
* Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.
* Instead of splitting these, provide userspace with an array
* of DSS to more closely represent the hardware resource.
+*
+* In addition, the concept of slice has been removed in Xe_HP.
+* To be compatible with prior generations, assume a single slice
+* across the entire device. Then calculate out the DSS for each
+* workload type within that software slice.
*/
intel_sseu_set_info(sseu, 1, 6, 16);
- s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
- GEN11_GT_S_ENA_MASK;
+ /*
+* As mentioned above, Xe_HP does not have the concept of a slice.
+* Enable one for software backwards compatibility.
+*/
+ if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
+ s_en = 0x1;
+ else
+ s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
+ GEN11_GT_S_ENA_MASK;
dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE);
/* one bit per pair of EUs */
- eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
- GEN11_EU_DIS_MASK);
+ if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
+ eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) &
XEHP_EU_ENA_MASK;
+ else
+ eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
+ GEN11_EU_DIS_MASK);
+
for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
diff --git a/drivers/gpu/drm/i915/i915_getparam.c
b/drivers/gpu/drm/i915/i915_getparam.c
index 24e18219eb50..e289397d9178 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -15,7 +15,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
struct pci_dev *pdev = to_pci_dev(dev->dev);
const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
drm_i915_getparam_t *param = data;
- int value;
+ int value = 0;
switch (param->param) {
case I915_PARAM_IRQ_ACTIVE:
@@ -150,7 +150,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
return -ENODEV;
break;
case I915_PARAM_SUBSLICE_MASK:
- value = sseu->subslice_mask[0];
+ /* Only copy bits from the first slice */
+ memcpy(&value, sseu->subslice_mask,
+ min(sseu->ss_stride, (u8)sizeof(value)));
if (!value)
return -ENODEV;
break;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 62af453c8c54..99858bc593f0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3225,6 +3225,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
+#define XEHP_EU_ENABLE _MMIO(0x9134)
+#define XEHP_EU_ENA_MASK 0xFF
+
#define GEN6_BSD_SLEEP_PSMI_CONTROL_MMIO(0x12050)
#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
--
2.25.4
___
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[Intel-gfx] [PATCH v4 07/18] drm/i915/dg2: Report INSTDONE_GEOM values in error state
Xe_HPG adds some additional INSTDONE_GEOM debug registers; the Mesa team
has indicated that having these reported in the error state would be
useful for debugging GPU hangs. These registers are replicated per-DSS
with gslice steering.
Cc: Lionel Landwerlin
Signed-off-by: Matt Roper
Acked-by: Lionel Landwerlin
Reviewed-by: Matt Atwood
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 7 +++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +++
drivers/gpu/drm/i915/i915_gpu_error.c| 10 --
drivers/gpu/drm/i915/i915_reg.h | 1 +
4 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 06733e86e88b..0a70a3baef9d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1205,6 +1205,13 @@ void intel_engine_get_instdone(const struct
intel_engine_cs *engine,
GEN7_ROW_INSTDONE);
}
}
+
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
+ for_each_instdone_gslice_dss_xehp(i915, sseu, iter,
slice, subslice)
+ instdone->geom_svg[slice][subslice] =
+ read_subslice_reg(engine, slice,
subslice,
+
XEHPG_INSTDONE_GEOM_SVG);
+ }
} else if (GRAPHICS_VER(i915) >= 7) {
instdone->instdone =
intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 0b4846b01626..bfbfe53c23dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -69,6 +69,9 @@ struct intel_instdone {
u32 slice_common_extra[2];
u32 sampler[GEN_MAX_GSLICES][I915_MAX_SUBSLICES];
u32 row[GEN_MAX_GSLICES][I915_MAX_SUBSLICES];
+
+ /* Added in XeHPG */
+ u32 geom_svg[GEN_MAX_GSLICES][I915_MAX_SUBSLICES];
};
/*
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 8230bc3ac8a9..91d5da7b0a2b 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -431,6 +431,7 @@ static void error_print_instdone(struct
drm_i915_error_state_buf *m,
const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu;
int slice;
int subslice;
+ int iter;
err_printf(m, " INSTDONE: 0x%08x\n",
ee->instdone.instdone);
@@ -445,8 +446,6 @@ static void error_print_instdone(struct
drm_i915_error_state_buf *m,
return;
if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 50)) {
- int iter;
-
for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice,
subslice)
err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice,
@@ -471,6 +470,13 @@ static void error_print_instdone(struct
drm_i915_error_state_buf *m,
if (GRAPHICS_VER(m->i915) < 12)
return;
+ if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) {
+ for_each_instdone_gslice_dss_xehp(m->i915, sseu, iter, slice,
subslice)
+ err_printf(m, " GEOM_SVGUNIT_INSTDONE[%d][%d]:
0x%08x\n",
+ slice, subslice,
+ ee->instdone.geom_svg[slice][subslice]);
+ }
+
err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n",
ee->instdone.slice_common_extra[0]);
err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n",
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 39ce6befff52..62af453c8c54 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2757,6 +2757,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108)
#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
#define GEN7_ROW_INSTDONE _MMIO(0xe164)
+#define XEHPG_INSTDONE_GEOM_SVG_MMIO(0x666c)
#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
#define SF_MCR_SELECTOR_MMIO(0xfd8)
#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
--
2.25.4
___
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[Intel-gfx] [PATCH v4 09/18] drm/i915/xehpsdv: Add maximum sseu limits
Due to the removal of legacy slices and the transition to a
gslice/cslice/mslice/etc. design, we'll internally store all DSS under
"slice0."
Signed-off-by: Matt Roper
Reviewed-by: Caz Yokoyama
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 5 -
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 2 +-
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 5d1b7d06c96b..16c0552fcd1d 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -145,7 +145,10 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
* across the entire device. Then calculate out the DSS for each
* workload type within that software slice.
*/
- intel_sseu_set_info(sseu, 1, 6, 16);
+ if (IS_XEHPSDV(gt->i915))
+ intel_sseu_set_info(sseu, 1, 32, 16);
+ else
+ intel_sseu_set_info(sseu, 1, 6, 16);
/*
* As mentioned above, Xe_HP does not have the concept of a slice.
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 74487650b08f..204ea6709460 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -16,7 +16,7 @@ struct intel_gt;
struct drm_printer;
#define GEN_MAX_SLICES (6) /* CNL upper bound */
-#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
+#define GEN_MAX_SUBSLICES (32) /* XEHPSDV upper bound */
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
#define GEN_MAX_EUS(16) /* TGL upper bound */
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index 714fe8495775..a424150b052e 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
@@ -53,7 +53,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
static void gen10_sseu_device_status(struct intel_gt *gt,
struct sseu_dev_info *sseu)
{
-#define SS_MAX 6
+#define SS_MAX 8
struct intel_uncore *uncore = gt->uncore;
const struct intel_gt_info *info = >->info;
u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
--
2.25.4
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[Intel-gfx] [PATCH v4 06/18] drm/i915/xehp: Loop over all gslices for INSTDONE processing
We no longer have traditional slices on Xe_HP platforms, but the
INSTDONE registers are replicated according to gslice representation
which is similar. We can mostly re-use the existing instdone code with
just a few modifications:
* Create an alternate instdone loop macro that will iterate over the
flat DSS space, but still provide the gslice/dss steering values for
compatibility with the legacy code.
* We should allocate INSTDONE storage space according to the maximum
number of gslices rather than the maximum number of legacy slices to
ensure we have enough storage space to hold all of the values. XeHP
design has 8 gslices, whereas older platforms never had more than 3
slices.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 48 +++-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 12 -
drivers/gpu/drm/i915/gt/intel_sseu.h | 7 +++
drivers/gpu/drm/i915/i915_gpu_error.c| 32 +
4 files changed, 66 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index dea0e522c5c7..06733e86e88b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1166,16 +1166,16 @@ void intel_engine_get_instdone(const struct
intel_engine_cs *engine,
u32 mmio_base = engine->mmio_base;
int slice;
int subslice;
+ int iter;
memset(instdone, 0, sizeof(*instdone));
- switch (GRAPHICS_VER(i915)) {
- default:
+ if (GRAPHICS_VER(i915) >= 8) {
instdone->instdone =
intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
if (engine->id != RCS0)
- break;
+ return;
instdone->slice_common =
intel_uncore_read(uncore, GEN7_SC_INSTDONE);
@@ -1185,21 +1185,32 @@ void intel_engine_get_instdone(const struct
intel_engine_cs *engine,
instdone->slice_common_extra[1] =
intel_uncore_read(uncore,
GEN12_SC_INSTDONE_EXTRA2);
}
- for_each_instdone_slice_subslice(i915, sseu, slice, subslice) {
- instdone->sampler[slice][subslice] =
- read_subslice_reg(engine, slice, subslice,
- GEN7_SAMPLER_INSTDONE);
- instdone->row[slice][subslice] =
- read_subslice_reg(engine, slice, subslice,
- GEN7_ROW_INSTDONE);
+
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+ for_each_instdone_gslice_dss_xehp(i915, sseu, iter,
slice, subslice) {
+ instdone->sampler[slice][subslice] =
+ read_subslice_reg(engine, slice,
subslice,
+
GEN7_SAMPLER_INSTDONE);
+ instdone->row[slice][subslice] =
+ read_subslice_reg(engine, slice,
subslice,
+ GEN7_ROW_INSTDONE);
+ }
+ } else {
+ for_each_instdone_slice_subslice(i915, sseu, slice,
subslice) {
+ instdone->sampler[slice][subslice] =
+ read_subslice_reg(engine, slice,
subslice,
+
GEN7_SAMPLER_INSTDONE);
+ instdone->row[slice][subslice] =
+ read_subslice_reg(engine, slice,
subslice,
+ GEN7_ROW_INSTDONE);
+ }
}
- break;
- case 7:
+ } else if (GRAPHICS_VER(i915) >= 7) {
instdone->instdone =
intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
if (engine->id != RCS0)
- break;
+ return;
instdone->slice_common =
intel_uncore_read(uncore, GEN7_SC_INSTDONE);
@@ -1207,22 +1218,15 @@ void intel_engine_get_instdone(const struct
intel_engine_cs *engine,
intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE);
instdone->row[0][0] =
intel_uncore_read(uncore, GEN7_ROW_INSTDONE);
-
- break;
- case 6:
- case 5:
- case 4:
+ } else if (GRAPHICS_VER(i915) >= 4) {
instdone->instdone =
intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
if (engine->id == RCS0)
/* HACK: Using the wrong struct mem
[Intel-gfx] [PATCH v4 17/18] drm/i915/dg2: Maintain backward-compatible nested batch behavior
For tgl+, the per-context setting of MI_MODE[12] determines whether
the bits of a nested MI_BATCH_BUFFER_START instruction should be
interpreted in the traditional manner or whether they should
instead use a new tgl+ meaning that breaks backward compatibility, but
allows nesting into 3rd-level batchbuffers. For previous platforms,
the hardware default for this register bit is to maintain
backward-compatible behavior unless a context intentionally opts into
the new behavior; however Xe_HPG flips the hardware default behavior.
>From a SW perspective, we want to maintain the backward-compatible
behavior for userspace, so we'll apply a fake workaround to set it back
to the legacy behavior on platforms where the hardware default is to
break compatibility. At the moment there is no Linux userspace that
utilizes third-level batchbuffers, so this will avoid userspace from
needing to make any changes. using the legacy meaning is the correct
thing to do. If/when we have userspace consumers that want to utilize
third-level batch nesting, we can provide a context parameter to allow
them to opt-in.
Bspec: 45974, 45718
Cc: John Harrison
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 39 +++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 6895b083523d..3e756b761526 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -644,6 +644,37 @@ static void dg1_ctx_workarounds_init(struct
intel_engine_cs *engine,
DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
}
+static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
+struct i915_wa_list *wal)
+{
+ /*
+* This is a "fake" workaround defined by software to ensure we
+* maintain reliable, backward-compatible behavior for userspace with
+* regards to how nested MI_BATCH_BUFFER_START commands are handled.
+*
+* The per-context setting of MI_MODE[12] determines whether the bits
+* of a nested MI_BATCH_BUFFER_START instruction should be interpreted
+* in the traditional manner or whether they should instead use a new
+* tgl+ meaning that breaks backward compatibility, but allows nesting
+* into 3rd-level batchbuffers. When this new capability was first
+* added in TGL, it remained off by default unless a context
+* intentionally opted in to the new behavior. However Xe_HPG now
+* flips this on by default and requires that we explicitly opt out if
+* we don't want the new behavior.
+*
+* From a SW perspective, we want to maintain the backward-compatible
+* behavior for userspace, so we'll apply a fake workaround to set it
+* back to the legacy behavior on platforms where the hardware default
+* is to break compatibility. At the moment there is no Linux
+* userspace that utilizes third-level batchbuffers, so this will avoid
+* userspace from needing to make any changes. using the legacy
+* meaning is the correct thing to do. If/when we have userspace
+* consumers that want to utilize third-level batch nesting, we can
+* provide a context parameter to allow them to opt-in.
+*/
+ wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN);
+}
+
static void
__intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
struct i915_wa_list *wal,
@@ -651,11 +682,15 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
{
struct drm_i915_private *i915 = engine->i915;
+ wa_init_start(wal, name, engine->name);
+
+ /* Applies to all engines */
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
+ fakewa_disable_nestedbb_mode(engine, wal);
+
if (engine->class != RENDER_CLASS)
return;
- wa_init_start(wal, name, engine->name);
-
if (IS_DG1(i915))
dg1_ctx_workarounds_init(engine, wal);
else if (GRAPHICS_VER(i915) == 12)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ed85f3ec1727..c192c1e096d7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2893,6 +2893,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MI_MODE_MMIO(0x209c)
# define VS_TIMER_DISPATCH (1 << 6)
# define MI_FLUSH_ENABLE (1 << 12)
+# define TGL_NESTED_BB_EN (1 << 12)
# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
# define MODE_IDLE (1 << 9)
# define STOP_RING
[Intel-gfx] [PATCH v4 12/18] drm/i915/xehpsdv: Define MOCS table for XeHP SDV
From: Lucas De Marchi
Like DG1, XeHP SDV doesn't have LLC/eDRAM control values due to being a
dgfx card. XeHP SDV adds 2 more bits: L3_GLBGO to "push the Go point to
memory for L3 destined transaction" and L3_LKP to "enable Lookup for
uncacheable accesses".
Bspec: 45101
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
Signed-off-by: Stuart Summers
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 33 +++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 17848807f111..0c9d0b936c20 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -40,6 +40,8 @@ struct drm_i915_mocs_table {
#define L3_ESC(value) ((value) << 0)
#define L3_SCC(value) ((value) << 1)
#define _L3_CACHEABILITY(value)((value) << 4)
+#define L3_GLBGO(value)((value) << 6)
+#define L3_LKUP(value) ((value) << 7)
/* Helper defines */
#define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
@@ -314,6 +316,31 @@ static const struct drm_i915_mocs_entry dg1_mocs_table[] =
{
MOCS_ENTRY(63, 0, L3_1_UC),
};
+static const struct drm_i915_mocs_entry xehpsdv_mocs_table[] = {
+ /* wa_1608975824 */
+ MOCS_ENTRY(0, 0, L3_3_WB | L3_LKUP(1)),
+
+ /* UC - Coherent; GO:L3 */
+ MOCS_ENTRY(1, 0, L3_1_UC | L3_LKUP(1)),
+ /* UC - Coherent; GO:Memory */
+ MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
+ /* UC - Non-Coherent; GO:Memory */
+ MOCS_ENTRY(3, 0, L3_1_UC | L3_GLBGO(1)),
+ /* UC - Non-Coherent; GO:L3 */
+ MOCS_ENTRY(4, 0, L3_1_UC),
+
+ /* WB */
+ MOCS_ENTRY(5, 0, L3_3_WB | L3_LKUP(1)),
+
+ /* HW Reserved - SW program but never use. */
+ MOCS_ENTRY(48, 0, L3_3_WB | L3_LKUP(1)),
+ MOCS_ENTRY(49, 0, L3_1_UC | L3_LKUP(1)),
+ MOCS_ENTRY(60, 0, L3_1_UC),
+ MOCS_ENTRY(61, 0, L3_1_UC),
+ MOCS_ENTRY(62, 0, L3_1_UC),
+ MOCS_ENTRY(63, 0, L3_1_UC),
+};
+
enum {
HAS_GLOBAL_MOCS = BIT(0),
HAS_ENGINE_MOCS = BIT(1),
@@ -340,7 +367,11 @@ static unsigned int get_mocs_settings(const struct
drm_i915_private *i915,
{
unsigned int flags;
- if (IS_DG1(i915)) {
+ if (IS_XEHPSDV(i915)) {
+ table->size = ARRAY_SIZE(xehpsdv_mocs_table);
+ table->table = xehpsdv_mocs_table;
+ table->n_entries = GEN9_NUM_MOCS_ENTRIES;
+ } else if (IS_DG1(i915)) {
table->size = ARRAY_SIZE(dg1_mocs_table);
table->table = dg1_mocs_table;
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
--
2.25.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 16/18] drm/i915/dg2: Add new LRI reg offsets
From: Akeem G Abodunrin
New LRI register offsets were introduced for DG2, this patch adds
those extra registers, and create new register table for setting offsets
to compare with HW generated context image - especially for gt_lrc test.
Also updates general purpose register with scratch offset for DG2, in
order to use it for live_lrc_fixed selftest.
Cc: Chris P Wilson
Cc: Prathap Kumar Valsan
Signed-off-by: Akeem G Abodunrin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 85 -
1 file changed, 83 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index c3f5bec8ae15..1b7e75e4c011 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -226,6 +226,40 @@ static const u8 gen12_xcs_offsets[] = {
END
};
+static const u8 dg2_xcs_offsets[] = {
+ NOP(1),
+ LRI(15, POSTED),
+ REG16(0x244),
+ REG(0x034),
+ REG(0x030),
+ REG(0x038),
+ REG(0x03c),
+ REG(0x168),
+ REG(0x140),
+ REG(0x110),
+ REG(0x1c0),
+ REG(0x1c4),
+ REG(0x1c8),
+ REG(0x180),
+ REG16(0x2b4),
+ REG(0x120),
+ REG(0x124),
+
+ NOP(1),
+ LRI(9, POSTED),
+ REG16(0x3a8),
+ REG16(0x28c),
+ REG16(0x288),
+ REG16(0x284),
+ REG16(0x280),
+ REG16(0x27c),
+ REG16(0x278),
+ REG16(0x274),
+ REG16(0x270),
+
+ END
+};
+
static const u8 gen8_rcs_offsets[] = {
NOP(1),
LRI(14, POSTED),
@@ -525,6 +559,49 @@ static const u8 xehp_rcs_offsets[] = {
END
};
+static const u8 dg2_rcs_offsets[] = {
+ NOP(1),
+ LRI(15, POSTED),
+ REG16(0x244),
+ REG(0x034),
+ REG(0x030),
+ REG(0x038),
+ REG(0x03c),
+ REG(0x168),
+ REG(0x140),
+ REG(0x110),
+ REG(0x1c0),
+ REG(0x1c4),
+ REG(0x1c8),
+ REG(0x180),
+ REG16(0x2b4),
+ REG(0x120),
+ REG(0x124),
+
+ NOP(1),
+ LRI(9, POSTED),
+ REG16(0x3a8),
+ REG16(0x28c),
+ REG16(0x288),
+ REG16(0x284),
+ REG16(0x280),
+ REG16(0x27c),
+ REG16(0x278),
+ REG16(0x274),
+ REG16(0x270),
+
+ LRI(3, POSTED),
+ REG(0x1b0),
+ REG16(0x5a8),
+ REG16(0x5ac),
+
+ NOP(6),
+ LRI(1, 0),
+ REG(0x0c8),
+
+ END
+};
+
#undef END
#undef REG16
#undef REG
@@ -543,7 +620,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs
*engine)
!intel_engine_has_relative_mmio(engine));
if (engine->class == RENDER_CLASS) {
- if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+ return dg2_rcs_offsets;
+ else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
return xehp_rcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_rcs_offsets;
@@ -554,7 +633,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs
*engine)
else
return gen8_rcs_offsets;
} else {
- if (GRAPHICS_VER(engine->i915) >= 12)
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+ return dg2_xcs_offsets;
+ else if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_xcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 9)
return gen9_xcs_offsets;
--
2.25.4
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 14/18] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP
From: Lucas De Marchi
Instead of maintaining the same if ladder in 3 different places, add a
function to read RP_STATE_CAP.
Signed-off-by: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 8 +++-
drivers/gpu/drm/i915/gt/intel_rps.c | 17 -
drivers/gpu/drm/i915/gt/intel_rps.h | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 8 +++-
4 files changed, 19 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index 4270b5a34a83..1061a62bdfce 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -309,13 +309,11 @@ static int frequency_show(struct seq_file *m, void
*unused)
int max_freq;
rp_state_limits = intel_uncore_read(uncore,
GEN6_RP_STATE_LIMITS);
- if (IS_GEN9_LP(i915)) {
- rp_state_cap = intel_uncore_read(uncore,
BXT_RP_STATE_CAP);
+ rp_state_cap = intel_rps_read_state_cap(rps);
+ if (IS_GEN9_LP(i915))
gt_perf_status = intel_uncore_read(uncore,
BXT_GT_PERF_STATUS);
- } else {
- rp_state_cap = intel_uncore_read(uncore,
GEN6_RP_STATE_CAP);
+ else
gt_perf_status = intel_uncore_read(uncore,
GEN6_GT_PERF_STATUS);
- }
/* RPSTAT1 is in the GT power well */
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 0c8e7f2b06f0..8b0f429ba5be 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -975,20 +975,16 @@ int intel_rps_set(struct intel_rps *rps, u8 val)
static void gen6_rps_init(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
- struct intel_uncore *uncore = rps_to_uncore(rps);
+ u32 rp_state_cap = intel_rps_read_state_cap(rps);
/* All of these values are in units of 50MHz */
/* static values from HW: RP0 > RP1 > RPn (min_freq) */
if (IS_GEN9_LP(i915)) {
- u32 rp_state_cap = intel_uncore_read(uncore, BXT_RP_STATE_CAP);
-
rps->rp0_freq = (rp_state_cap >> 16) & 0xff;
rps->rp1_freq = (rp_state_cap >> 8) & 0xff;
rps->min_freq = (rp_state_cap >> 0) & 0xff;
} else {
- u32 rp_state_cap = intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
-
rps->rp0_freq = (rp_state_cap >> 0) & 0xff;
rps->rp1_freq = (rp_state_cap >> 8) & 0xff;
rps->min_freq = (rp_state_cap >> 16) & 0xff;
@@ -1940,6 +1936,17 @@ u32 intel_rps_read_actual_frequency(struct intel_rps
*rps)
return freq;
}
+u32 intel_rps_read_state_cap(struct intel_rps *rps)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ struct intel_uncore *uncore = rps_to_uncore(rps);
+
+ if (IS_GEN9_LP(i915))
+ return intel_uncore_read(uncore, BXT_RP_STATE_CAP);
+ else
+ return intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
+}
+
/* External interface for intel_ips.ko */
static struct drm_i915_private __rcu *ips_mchdev;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h
b/drivers/gpu/drm/i915/gt/intel_rps.h
index 1d2cfc98b510..6e06dd61f818 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -31,6 +31,7 @@ int intel_gpu_freq(struct intel_rps *rps, int val);
int intel_freq_opcode(struct intel_rps *rps, int val);
u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat1);
u32 intel_rps_read_actual_frequency(struct intel_rps *rps);
+u32 intel_rps_read_state_cap(struct intel_rps *rps);
void gen5_rps_irq_handler(struct intel_rps *rps);
void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0529576f069c..37056b2c044a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -420,13 +420,11 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
int max_freq;
rp_state_limits = intel_uncore_read(&dev_priv->uncore,
GEN6_RP_STATE_LIMITS);
- if (IS_GEN9_LP(dev_priv)) {
- rp_state_cap = intel_uncore_read(&dev_priv->uncore,
BXT_RP_STATE_CAP);
+ rp_state_cap = intel_rps_read_state_cap(rps);
+ if (IS_GEN9_LP(dev_priv))
gt_perf_status = intel_uncore_read(&dev_priv->uncore,
BXT_GT_PERF_STATUS);
- } else {
- rp_state_cap = intel_uncore_read(&dev_priv->uncore,
GEN6_RP_STATE_CAP);
+ else
gt_perf_status = intel_uncore_read(&dev_priv->uncore,
GEN6_GT_PERF_STATUS);
-
[Intel-gfx] [PATCH v4 18/18] drm/i915/dg2: Configure PCON in DP pre-enable path
From: Ankit Nautiyal Add the functions to configure HDMI2.1 pcon for DG2, before DP link training. Signed-off-by: Ankit Nautiyal Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 85856d040637..233f02c617a4 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2576,6 +2576,7 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, if (!is_mst) intel_dp_set_power(intel_dp, DP_SET_POWER_D0); + intel_dp_configure_protocol_converter(intel_dp, crtc_state); intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); /* * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit @@ -2583,6 +2584,8 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, * training */ intel_dp_sink_set_fec_ready(intel_dp, crtc_state); + intel_dp_check_frl_training(intel_dp); + intel_dp_pcon_dsc_configure(intel_dp, crtc_state); /* * 5.h Follow DisplayPort specification training sequence (see notes for -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 15/18] drm/i915/xehpsdv: Read correct RP_STATE_CAP register
The RP_STATE_CAP register is no longer part of the MCHBAR on XEHPSDV; this register is now a per-tile register at GTTMMADDR offset 0x250014. Cc: Rodrigo Vivi Signed-off-by: Matt Roper Signed-off-by: Lucas De Marchi Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/gt/intel_rps.c | 4 +++- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 8b0f429ba5be..10bb172a3826 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1941,7 +1941,9 @@ u32 intel_rps_read_state_cap(struct intel_rps *rps) struct drm_i915_private *i915 = rps_to_i915(rps); struct intel_uncore *uncore = rps_to_uncore(rps); - if (IS_GEN9_LP(i915)) + if (IS_XEHPSDV(i915)) + return intel_uncore_read(uncore, XEHPSDV_RP_STATE_CAP); + else if (IS_GEN9_LP(i915)) return intel_uncore_read(uncore, BXT_RP_STATE_CAP); else return intel_uncore_read(uncore, GEN6_RP_STATE_CAP); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d7e4418955f7..ed85f3ec1727 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4184,6 +4184,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) #define BXT_RP_STATE_CAP_MMIO(0x138170) #define GEN9_RP_STATE_LIMITS _MMIO(0x138148) +#define XEHPSDV_RP_STATE_CAP _MMIO(0x250014) /* * Logical Context regs -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 13/18] drm/i915/dg2: Define MOCS table for DG2
Bspec: 45101, 45427
Cc: Ramalingam C (v5)
Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 35 +++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 0c9d0b936c20..ad021337225d 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -341,6 +341,30 @@ static const struct drm_i915_mocs_entry
xehpsdv_mocs_table[] = {
MOCS_ENTRY(63, 0, L3_1_UC),
};
+static const struct drm_i915_mocs_entry dg2_mocs_table[] = {
+ /* UC - Coherent; GO:L3 */
+ MOCS_ENTRY(0, 0, L3_1_UC | L3_LKUP(1)),
+ /* UC - Coherent; GO:Memory */
+ MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
+ /* UC - Non-Coherent; GO:Memory */
+ MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),
+
+ /* WB - LC */
+ MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
+};
+
+static const struct drm_i915_mocs_entry dg2_mocs_table_g10_ax[] = {
+ /* Wa_14011441408: Set Go to Memory for MOCS#0 */
+ MOCS_ENTRY(0, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
+ /* UC - Coherent; GO:Memory */
+ MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
+ /* UC - Non-Coherent; GO:Memory */
+ MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),
+
+ /* WB - LC */
+ MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
+};
+
enum {
HAS_GLOBAL_MOCS = BIT(0),
HAS_ENGINE_MOCS = BIT(1),
@@ -367,7 +391,16 @@ static unsigned int get_mocs_settings(const struct
drm_i915_private *i915,
{
unsigned int flags;
- if (IS_XEHPSDV(i915)) {
+ if (IS_DG2(i915)) {
+ if (IS_DG2_GT_STEP(i915, G10, STEP_A0, STEP_B0)) {
+ table->size = ARRAY_SIZE(dg2_mocs_table_g10_ax);
+ table->table = dg2_mocs_table_g10_ax;
+ } else {
+ table->size = ARRAY_SIZE(dg2_mocs_table);
+ table->table = dg2_mocs_table;
+ }
+ table->n_entries = GEN9_NUM_MOCS_ENTRIES;
+ } else if (IS_XEHPSDV(i915)) {
table->size = ARRAY_SIZE(xehpsdv_mocs_table);
table->table = xehpsdv_mocs_table;
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
--
2.25.4
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[Intel-gfx] [PATCH v4 10/18] drm/i915/xehpsdv: Add compute DSS type
From: Stuart Summers
Starting in XeHP, the concept of slice has been removed in favor of
DSS (Dual-Subslice) masks for various workload types. These workloads have
been divided into those enabled for geometry and those enabled for compute.
i915 currently maintains a single set of S/SS/EU masks for the device.
The goal of this patch set is to minimize the amount of impact to prior
generations while still giving the user maximum flexibility.
Bspec: 33117, 33118, 20376
Cc: Daniele Ceraolo Spurio
Cc: Matt Roper
Signed-off-by: Stuart Summers
Signed-off-by: Steve Hampson
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 73
drivers/gpu/drm/i915/gt/intel_sseu.h | 5 +-
drivers/gpu/drm/i915/i915_reg.h | 3 +-
include/uapi/drm/i915_drm.h | 3 --
4 files changed, 59 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 16c0552fcd1d..5d3b8dff464c 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -46,11 +46,11 @@ u32 intel_sseu_get_subslices(const struct sseu_dev_info
*sseu, u8 slice)
}
void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u32 ss_mask)
+ u8 *subslice_mask, u32 ss_mask)
{
int offset = slice * sseu->ss_stride;
- memcpy(&sseu->subslice_mask[offset], &ss_mask, sseu->ss_stride);
+ memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
}
unsigned int
@@ -100,14 +100,24 @@ static u16 compute_eu_total(const struct sseu_dev_info
*sseu)
return total;
}
-static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
- u8 s_en, u32 ss_en, u16 eu_en)
+static u32 get_ss_stride_mask(struct sseu_dev_info *sseu, u8 s, u32 ss_en)
+{
+ u32 ss_mask;
+
+ ss_mask = ss_en >> (s * sseu->max_subslices);
+ ss_mask &= GENMASK(sseu->max_subslices - 1, 0);
+
+ return ss_mask;
+}
+
+static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, u8 s_en,
+ u32 g_ss_en, u32 c_ss_en, u16 eu_en)
{
int s, ss;
- /* ss_en represents entire subslice mask across all slices */
+ /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
- sizeof(ss_en) * BITS_PER_BYTE);
+ sizeof(g_ss_en) * BITS_PER_BYTE);
for (s = 0; s < sseu->max_slices; s++) {
if ((s_en & BIT(s)) == 0)
@@ -115,7 +125,23 @@ static void gen11_compute_sseu_info(struct sseu_dev_info
*sseu,
sseu->slice_mask |= BIT(s);
- intel_sseu_set_subslices(sseu, s, ss_en);
+ /*
+* XeHP introduces the concept of compute vs
+* geometry DSS. To reduce variation between GENs
+* around subslice usage, store a mask for both the
+* geometry and compute enabled masks, to provide
+* to user space later in QUERY_TOPOLOGY_INFO, and
+* compute a total enabled subslice count for the
+* purposes of selecting subslices to use in a
+* particular GEM context.
+*/
+ intel_sseu_set_subslices(sseu, s, sseu->compute_subslice_mask,
+get_ss_stride_mask(sseu, s, c_ss_en));
+ intel_sseu_set_subslices(sseu, s, sseu->geometry_subslice_mask,
+get_ss_stride_mask(sseu, s, g_ss_en));
+ intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
+get_ss_stride_mask(sseu, s,
+ g_ss_en | c_ss_en));
for (ss = 0; ss < sseu->max_subslices; ss++)
if (intel_sseu_has_subslice(sseu, s, ss))
@@ -129,7 +155,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
- u32 dss_en;
+ u32 g_dss_en, c_dss_en = 0;
u16 eu_en = 0;
u8 eu_en_fuse;
u8 s_en;
@@ -145,10 +171,12 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
* across the entire device. Then calculate out the DSS for each
* workload type within that software slice.
*/
- if (IS_XEHPSDV(gt->i915))
+ if (IS_XEHPSDV(gt->i915)) {
intel_sseu_set_info(sseu, 1, 32, 16);
- else
+ sseu->has_compute_dss = 1;
+ } else {
intel_sseu_set_info(sseu, 1, 6, 16);
+ }
/*
* As mentioned above, Xe_HP does not have the concept of a slice.
@@ -160,7 +188,9 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
s_en = intel
[Intel-gfx] [PATCH v4 11/18] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV
DG2 supports compute DSS and has the same maximum number of DSS and EU
as XeHP SDV.
Signed-off-by: Matt Roper
Reviewed-by: Caz Yokoyama
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 5d3b8dff464c..eaff221db5b0 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -171,7 +171,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
* across the entire device. Then calculate out the DSS for each
* workload type within that software slice.
*/
- if (IS_XEHPSDV(gt->i915)) {
+ if (IS_DG2(gt->i915) || IS_XEHPSDV(gt->i915)) {
intel_sseu_set_info(sseu, 1, 32, 16);
sseu->has_compute_dss = 1;
} else {
--
2.25.4
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Re: [Intel-gfx] [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits
On 7/29/2021 9:21 AM, Michal Wajdeczko wrote:
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
Cache rp0, rp1 and rpn platform limits into SLPC structure
for range checking while setting min/max frequencies.
Also add "soft" limits which keep track of frequency changes
made from userland. These are initially set to platform min
and max.
v2: Address review comments (Michal W)
v3: Formatting (Michal W)
v4: Add separate function to parse rp values (Michal W)
v5: Perform range checking for set min/max (Michal W)
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 115 ++
.../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 9 ++
drivers/gpu/drm/i915/i915_reg.h | 3 +
3 files changed, 127 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 742918875593..bfd5fb0751fd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -94,6 +94,9 @@ static int slpc_shared_data_init(struct intel_guc_slpc *slpc)
return err;
}
+ slpc->max_freq_softlimit = 0;
+ slpc->min_freq_softlimit = 0;
shouldn't this be in intel_guc_slpc_init() ?
No, we want to maintain softlimits across suspend resume.
+
return err;
}
@@ -124,6 +127,18 @@ static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
return ret > 0 ? -EPROTO : ret;
}
+static int guc_action_slpc_unset_param(struct intel_guc *guc, u8 id)
+{
+ u32 request[] = {
+ GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
+ SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 2),
+ id,
+ };
+
+ return intel_guc_send(guc, request, ARRAY_SIZE(request));
+}
+
+
static bool slpc_is_running(struct intel_guc_slpc *slpc)
{
return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
@@ -177,6 +192,16 @@ static int slpc_set_param(struct intel_guc_slpc *slpc, u8
id, u32 value)
return ret;
}
+static int slpc_unset_param(struct intel_guc_slpc *slpc,
+ u8 id)
+{
+ struct intel_guc *guc = slpc_to_guc(slpc);
+
+ GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+
+ return guc_action_slpc_unset_param(guc, id);
+}
+
static const char *slpc_global_state_to_string(enum slpc_global_state state)
{
switch (state) {
@@ -307,6 +332,11 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc
*slpc, u32 val)
intel_wakeref_t wakeref;
int ret;
+ if ((val < slpc->min_freq) ||
+ (val > slpc->rp0_freq) ||
+ (val < slpc->min_freq_softlimit))
+ return -EINVAL;
+
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
ret = slpc_set_param(slpc,
SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
@@ -317,6 +347,8 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc
*slpc, u32 val)
ret = -EIO;
}
+ slpc->max_freq_softlimit = val;
+
return ret;
}
@@ -363,6 +395,11 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
intel_wakeref_t wakeref;
int ret;
+ if ((val < slpc->min_freq) ||
+ (val > slpc->rp0_freq) ||
+ (val > slpc->max_freq_softlimit))
+ return -EINVAL;
+
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
ret = slpc_set_param(slpc,
SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
@@ -373,6 +410,8 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc
*slpc, u32 val)
ret = -EIO;
}
+ slpc->min_freq_softlimit = val;
+
return ret;
}
@@ -418,6 +457,71 @@ void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
GEN6_PMINTRMSK, pm_intrmsk_mbz, 0);
}
+static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
+{
+ int ret = 0;
+
+ /*
+* Softlimits are initially equivalent to platform limits
+* unless they have deviated from defaults, in which case,
+* we retain the values and set min/max accordingly.
+*/
+ if (!slpc->max_freq_softlimit)
+ slpc->max_freq_softlimit = slpc->rp0_freq;
+ else if (slpc->max_freq_softlimit != slpc->rp0_freq)
+ ret = intel_guc_slpc_set_max_freq(slpc,
+ slpc->max_freq_softlimit);
if this fails, shouldn't we reset max_freq_softlimit to platform limit ?
otherwise we could be with some potentially bad value forever
Well, if this call fails, it's likely the next set_max_freq call will
also fail, so not much point. Also, it will likely (?) just retain the
old value, which is fine.
+
+ if (!slpc->min_freq_softlimit)
+ slpc->min_freq_softlimit = slpc->min_freq;
+ else if (slpc->min_freq_softlimit != slpc->min_freq)
+
Re: [Intel-gfx] [PATCH v4 12/18] drm/i915/xehpsdv: Define MOCS table for XeHP SDV
On Thu, Jul 29, 2021 at 10:00:02AM -0700, Matt Roper wrote:
From: Lucas De Marchi
Like DG1, XeHP SDV doesn't have LLC/eDRAM control values due to being a
dgfx card. XeHP SDV adds 2 more bits: L3_GLBGO to "push the Go point to
memory for L3 destined transaction" and L3_LKP to "enable Lookup for
uncacheable accesses".
Bspec: 45101
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
Signed-off-by: Stuart Summers
Signed-off-by: Matt Roper
+Ayaz, +Daniel
I think this can't land as is since we risk forgetting additional
changes that we will have to do. We already made the mistake once of
forgetting MOCS changes.
There are some patches to initialize unused MOCS entries and similar
that should have been sent already to upstream. Ayaz, what's the state
of those patches?
Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 33 +++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 17848807f111..0c9d0b936c20 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -40,6 +40,8 @@ struct drm_i915_mocs_table {
#define L3_ESC(value) ((value) << 0)
#define L3_SCC(value) ((value) << 1)
#define _L3_CACHEABILITY(value) ((value) << 4)
+#define L3_GLBGO(value)((value) << 6)
+#define L3_LKUP(value) ((value) << 7)
/* Helper defines */
#define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
@@ -314,6 +316,31 @@ static const struct drm_i915_mocs_entry dg1_mocs_table[] =
{
MOCS_ENTRY(63, 0, L3_1_UC),
};
+static const struct drm_i915_mocs_entry xehpsdv_mocs_table[] = {
+ /* wa_1608975824 */
+ MOCS_ENTRY(0, 0, L3_3_WB | L3_LKUP(1)),
+
+ /* UC - Coherent; GO:L3 */
+ MOCS_ENTRY(1, 0, L3_1_UC | L3_LKUP(1)),
+ /* UC - Coherent; GO:Memory */
+ MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
+ /* UC - Non-Coherent; GO:Memory */
+ MOCS_ENTRY(3, 0, L3_1_UC | L3_GLBGO(1)),
+ /* UC - Non-Coherent; GO:L3 */
+ MOCS_ENTRY(4, 0, L3_1_UC),
+
+ /* WB */
+ MOCS_ENTRY(5, 0, L3_3_WB | L3_LKUP(1)),
+
+ /* HW Reserved - SW program but never use. */
+ MOCS_ENTRY(48, 0, L3_3_WB | L3_LKUP(1)),
+ MOCS_ENTRY(49, 0, L3_1_UC | L3_LKUP(1)),
+ MOCS_ENTRY(60, 0, L3_1_UC),
+ MOCS_ENTRY(61, 0, L3_1_UC),
+ MOCS_ENTRY(62, 0, L3_1_UC),
+ MOCS_ENTRY(63, 0, L3_1_UC),
+};
+
enum {
HAS_GLOBAL_MOCS = BIT(0),
HAS_ENGINE_MOCS = BIT(1),
@@ -340,7 +367,11 @@ static unsigned int get_mocs_settings(const struct
drm_i915_private *i915,
{
unsigned int flags;
- if (IS_DG1(i915)) {
+ if (IS_XEHPSDV(i915)) {
+ table->size = ARRAY_SIZE(xehpsdv_mocs_table);
+ table->table = xehpsdv_mocs_table;
+ table->n_entries = GEN9_NUM_MOCS_ENTRIES;
+ } else if (IS_DG1(i915)) {
table->size = ARRAY_SIZE(dg1_mocs_table);
table->table = dg1_mocs_table;
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
--
2.25.4
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: prefer the create_user helper (rev2)
== Series Details == Series: drm/i915/selftests: prefer the create_user helper (rev2) URL : https://patchwork.freedesktop.org/series/93131/ State : success == Summary == CI Bug Log - changes from CI_DRM_10418_full -> Patchwork_20738_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_20738_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-persistence: - shard-snb: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-persistence.html * igt@gem_eio@in-flight-contexts-1us: - shard-iclb: [PASS][2] -> [TIMEOUT][3] ([i915#3070]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/shard-iclb7/igt@gem_...@in-flight-contexts-1us.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/shard-iclb8/igt@gem_...@in-flight-contexts-1us.html - shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/shard-tglb1/igt@gem_...@in-flight-contexts-1us.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/shard-tglb3/igt@gem_...@in-flight-contexts-1us.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-iclb: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/shard-iclb7/igt@gem_exec_fair@basic-p...@bcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/shard-iclb8/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: NOTRUN -> [FAIL][9] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/shard-glk2/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_schedule@semaphore-codependency: - shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271]) +211 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/shard-snb6/igt@gem_exec_sched...@semaphore-codependency.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#2190]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/shard-apl7/igt@gem_huc_c...@huc-copy.html * igt@gem_pwrite@basic-exhaustion: - shard-apl: NOTRUN -> [WARN][14] ([i915#2658]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/shard-apl3/igt@gem_pwr...@basic-exhaustion.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][15] ([i915#3002]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/shard-apl1/igt@gem_userptr_bl...@input-checking.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp: - shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1937]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/shard-apl3/igt@i915_pm_lpsp@kms-l...@kms-lpsp-dp.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#2521]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/shard-skl1/igt@kms_async_fl...@alternate-sync-async-flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/shard-skl9/igt@kms_async_fl...@alternate-sync-async-flip.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip: - shard-skl: NOTRUN -> [FAIL][19] ([i915#3722]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/shard-skl2/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3777]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/shard-apl1/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html * igt@kms_big_fb@y-tiled-64bpp-rotate-270: - shard-kbl: NOTRUN -> [SKIP][21] ([fdo#109271]) +39 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20738/shard-kbl7/igt@kms_big...@y-tiled-64bpp-rotate-270.html * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0: - shard-apl:
Re: [Intel-gfx] [PATCH 12/14] drm/i915/guc/slpc: Sysfs hooks for SLPC
On 28.07.2021 23:11, Vinay Belgaumkar wrote:
> Update the get/set min/max freq hooks to work for
> SLPC case as well. Consolidate helpers for requested/min/max
> frequency get/set to intel_rps where the proper action can
> be taken depending on whether SLPC is enabled.
>
> v2: Add wrappers for getting rp0/1/n frequencies, update
> softlimits in set min/max SLPC functions. Also check for
> boundary conditions before setting them.
>
> v3: Address review comments (Michal W)
>
> v4: Add helper for host part of intel_rps_set_freq helpers (Michal W)
>
> Acked-by: Michal Wajdeczko
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Tvrtko Ursulin
> Signed-off-by: Sujaritha Sundaresan
Reviewed-by: Michal Wajdeczko
> ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 177
> drivers/gpu/drm/i915/gt/intel_rps.h | 10 ++
> drivers/gpu/drm/i915/i915_pmu.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> drivers/gpu/drm/i915/i915_sysfs.c | 83 +++--
> 5 files changed, 207 insertions(+), 67 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> b/drivers/gpu/drm/i915/gt/intel_rps.c
> index e858eeb2c59d..49db8ed9f80d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct intel_rps
> *rps)
> return rps_to_gt(rps)->uncore;
> }
>
> +static struct intel_guc_slpc *rps_to_slpc(struct intel_rps *rps)
> +{
> + struct intel_gt *gt = rps_to_gt(rps);
> +
> + return >->uc.guc.slpc;
> +}
> +
> static bool rps_uses_slpc(struct intel_rps *rps)
> {
> struct intel_gt *gt = rps_to_gt(rps);
> @@ -1960,6 +1967,176 @@ u32 intel_rps_read_actual_frequency(struct intel_rps
> *rps)
> return freq;
> }
>
> +u32 intel_rps_read_punit_req(struct intel_rps *rps)
> +{
> + struct intel_uncore *uncore = rps_to_uncore(rps);
> +
> + return intel_uncore_read(uncore, GEN6_RPNSWREQ);
> +}
> +
> +static u32 intel_rps_get_req(u32 pureq)
> +{
> + u32 req = pureq >> GEN9_SW_REQ_UNSLICE_RATIO_SHIFT;
> +
> + return req;
> +}
> +
> +u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps)
> +{
> + u32 freq = intel_rps_get_req(intel_rps_read_punit_req(rps));
> +
> + return intel_gpu_freq(rps, freq);
> +}
> +
> +u32 intel_rps_get_requested_frequency(struct intel_rps *rps)
> +{
> + if (rps_uses_slpc(rps))
> + return intel_rps_read_punit_req_frequency(rps);
> + else
> + return intel_gpu_freq(rps, rps->cur_freq);
> +}
> +
> +u32 intel_rps_get_max_frequency(struct intel_rps *rps)
> +{
> + struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> +
> + if (rps_uses_slpc(rps))
> + return slpc->max_freq_softlimit;
> + else
> + return intel_gpu_freq(rps, rps->max_freq_softlimit);
> +}
> +
> +u32 intel_rps_get_rp0_frequency(struct intel_rps *rps)
> +{
> + struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> +
> + if (rps_uses_slpc(rps))
> + return slpc->rp0_freq;
> + else
> + return intel_gpu_freq(rps, rps->rp0_freq);
> +}
> +
> +u32 intel_rps_get_rp1_frequency(struct intel_rps *rps)
> +{
> + struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> +
> + if (rps_uses_slpc(rps))
> + return slpc->rp1_freq;
> + else
> + return intel_gpu_freq(rps, rps->rp1_freq);
> +}
> +
> +u32 intel_rps_get_rpn_frequency(struct intel_rps *rps)
> +{
> + struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> +
> + if (rps_uses_slpc(rps))
> + return slpc->min_freq;
> + else
> + return intel_gpu_freq(rps, rps->min_freq);
> +}
> +
> +static int set_max_freq(struct intel_rps *rps, u32 val)
> +{
> + struct drm_i915_private *i915 = rps_to_i915(rps);
> + int ret = 0;
> +
> + mutex_lock(&rps->lock);
> +
> + val = intel_freq_opcode(rps, val);
> + if (val < rps->min_freq ||
> + val > rps->max_freq ||
> + val < rps->min_freq_softlimit) {
> + ret = -EINVAL;
> + goto unlock;
> + }
> +
> + if (val > rps->rp0_freq)
> + drm_dbg(&i915->drm, "User requested overclocking to %d\n",
> + intel_gpu_freq(rps, val));
> +
> + rps->max_freq_softlimit = val;
> +
> + val = clamp_t(int, rps->cur_freq,
> + rps->min_freq_softlimit,
> + rps->max_freq_softlimit);
> +
> + /*
> + * We still need *_set_rps to process the new max_delay and
> + * update the interrupt limits and PMINTRMSK even though
> + * frequency request may be unchanged.
> + */
> + intel_rps_set(rps, val);
> +
> +unlock:
> + mutex_unlock(&rps->lock);
> +
> + return ret;
> +}
> +
> +int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val)
> +{
> + struct intel_guc_slpc *slpc = rps_to_slpc(rps);
> +
> + if (rps_uses_slpc(rps))
> + return intel_guc_slpc_set_max_freq(s
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Forcewake and shadowed register updates (rev2)
== Series Details == Series: Forcewake and shadowed register updates (rev2) URL : https://patchwork.freedesktop.org/series/93158/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/display/intel_display.c:1901:21:expected struct i915_vma *[assigned] vma +drivers/gpu/drm/i915/display/intel_display.c:1901:21:got void [noderef] __iomem *[assigned] iomem +drivers/gpu/drm/i915/display/intel_display.c:1901:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_context.c:1410:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1410:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1410:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:expected struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:got struct i915_address_space * +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/intel_ring_submission.c:1268:24: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/i915_perf.c:1443:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1497:15: warning: memset with byte count of 16777216 -./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block -./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block -./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block -./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block -./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write16' - different lock contexts for basic block -./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write32' - different lock contexts for basic block -./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write8' - different lock contexts for basic block +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original def
Re: [Intel-gfx] [PATCH v6 10/15] drm/i915/pxp: interfaces for using protected objects
On Thu, Jul 29, 2021 at 08:17:44AM -0700, Daniele Ceraolo Spurio wrote: > > > On 7/29/2021 4:10 AM, Rodrigo Vivi wrote: > > On Wed, Jul 28, 2021 at 07:01:01PM -0700, Daniele Ceraolo Spurio wrote: > > > This api allow user mode to create protected buffers and to mark > > > contexts as making use of such objects. Only when using contexts > > > marked in such a way is the execution guaranteed to work as expected. > > > > > > Contexts can only be marked as using protected content at creation time > > > (i.e. the parameter is immutable) and they must be both bannable and not > > > recoverable. > > > > > > All protected objects and contexts that have backing storage will be > > > considered invalid when the PXP session is destroyed and all new > > > submissions using them will be rejected. All intel contexts within the > > > invalidated gem contexts will be marked banned. A new flag has been > > > added to the RESET_STATS ioctl to report the context invalidation to > > > userspace. > > > > > > This patch was previously sent as 2 separate patches, which have been > > > squashed following a request to have all the uapi in a single patch. > > > I've retained the s-o-b from both. > > > > > > v5: squash patches, rebase on proto_ctx, update kerneldoc > > > > > > v6: rebase on obj create_ext changes > > The "rebase" word led me to think it was a small change caused > > only by rebasing conflicts, but then I spotted something on > > i915_gem_create.c that I didn't remember seeing before. > > Apologies for not being clear. > > > > > Since it took me a while to understand what was going on, let me > > try to summarize to see if I got it right and to check > > with others (Jason in special) > > if we are aligned with the recent directions: > > > > With the removal of the vanilla_object from the create_ext, > > the addition of the flags was needed. > > yes. > > > > > Then, instead of adding a new user_flags it adds the I915_BO_PROTECTED > > to the existent flags (what is cleaner) but then it does > > > > /* Add any flag set by create_ext options */ > > flags |= ext_flags; > > > > on the new user_create_ext. > > > > What shouldn't be a problem because the ext_flags is really only > > the I915_BO_PROTECTED set by our new extension and immutable. > > > > But I'm just trying to see if we are not opening any holes to accept > > some undesired flags. > > > > Apparently not. > > ext_flags are not set directly by the user, but by the create_ext extension > functions, based on the extensions the user has provided. This should allow > the kernel to perform any required checks in the extension functions before > setting the flag (like it happens in this case for the PXP option). > > > > > Am I getting things right? Anything else we should check in here? > > yup, got it right. Great, thanks for confirming so I'm okay with: Reviewed-by: Rodrigo Vivi > > Daniele > > > > > Thanks, > > Rodrigo. > > > > > Signed-off-by: Daniele Ceraolo Spurio > > > Signed-off-by: Bommu Krishnaiah > > > Cc: Rodrigo Vivi > > > Cc: Chris Wilson > > > Cc: Lionel Landwerlin > > > Cc: Jason Ekstrand > > > Cc: Daniel Vetter > > > Reviewed-by: Rodrigo Vivi #v5 > > > --- > > > drivers/gpu/drm/i915/gem/i915_gem_context.c | 68 -- > > > drivers/gpu/drm/i915/gem/i915_gem_context.h | 18 > > > .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 + > > > drivers/gpu/drm/i915/gem/i915_gem_create.c| 75 > > > .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 40 - > > > drivers/gpu/drm/i915/gem/i915_gem_object.c| 6 ++ > > > drivers/gpu/drm/i915/gem/i915_gem_object.h| 12 +++ > > > .../gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++ > > > drivers/gpu/drm/i915/pxp/intel_pxp.c | 89 +++ > > > drivers/gpu/drm/i915/pxp/intel_pxp.h | 15 > > > drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 3 + > > > drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 5 ++ > > > include/uapi/drm/i915_drm.h | 55 +++- > > > 13 files changed, 371 insertions(+), 26 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c > > > b/drivers/gpu/drm/i915/gem/i915_gem_context.c > > > index cff72679ad7c..0cd3e2d06188 100644 > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c > > > @@ -77,6 +77,8 @@ > > > #include "gt/intel_gpu_commands.h" > > > #include "gt/intel_ring.h" > > > +#include "pxp/intel_pxp.h" > > > + > > > #include "i915_gem_context.h" > > > #include "i915_trace.h" > > > #include "i915_user_extensions.h" > > > @@ -241,6 +243,25 @@ static int proto_context_set_persistence(struct > > > drm_i915_private *i915, > > > return 0; > > > } > > > +static int proto_context_set_protected(struct drm_i915_private *i915, > > > +struct i915_gem_proto_context *pc, > > > +
Re: [Intel-gfx] [PATCH v6 02/15] mei: pxp: export pavp client to me client bus
On Wed, Jul 28, 2021 at 07:00:53PM -0700, Daniele Ceraolo Spurio wrote:
> From: Vitaly Lubart
>
> Export PAVP client to work with i915 driver,
> for binding it uses kernel component framework.
>
> v2:drop debug prints, refactor match code to match mei_hdcp (Tomas)
>
> Signed-off-by: Vitaly Lubart
> Signed-off-by: Tomas Winkler
> Signed-off-by: Daniele Ceraolo Spurio
> Reviewed-by: Rodrigo Vivi #v1
shouldn't we use the 2020-2021 in the other headers as well?
anyway, rv-b remains
> ---
> drivers/misc/mei/Kconfig | 2 +
> drivers/misc/mei/Makefile | 1 +
> drivers/misc/mei/pxp/Kconfig | 13 ++
> drivers/misc/mei/pxp/Makefile | 7 +
> drivers/misc/mei/pxp/mei_pxp.c | 229 +
> drivers/misc/mei/pxp/mei_pxp.h | 18 +++
> 6 files changed, 270 insertions(+)
> create mode 100644 drivers/misc/mei/pxp/Kconfig
> create mode 100644 drivers/misc/mei/pxp/Makefile
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
>
> diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
> index f5fd5b786607..0e0bcd0da852 100644
> --- a/drivers/misc/mei/Kconfig
> +++ b/drivers/misc/mei/Kconfig
> @@ -47,3 +47,5 @@ config INTEL_MEI_TXE
> Intel Bay Trail
>
> source "drivers/misc/mei/hdcp/Kconfig"
> +source "drivers/misc/mei/pxp/Kconfig"
> +
> diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
> index f1c76f7ee804..d8e5165917f2 100644
> --- a/drivers/misc/mei/Makefile
> +++ b/drivers/misc/mei/Makefile
> @@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
> CFLAGS_mei-trace.o = -I$(src)
>
> obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
> +obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
> diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
> new file mode 100644
> index ..4029b96afc04
> --- /dev/null
> +++ b/drivers/misc/mei/pxp/Kconfig
> @@ -0,0 +1,13 @@
> +
> +# SPDX-License-Identifier: GPL-2.0
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.
> +#
> +config INTEL_MEI_PXP
> + tristate "Intel PXP services of ME Interface"
> + select INTEL_MEI_ME
> + depends on DRM_I915
> + help
> + MEI Support for PXP Services on Intel platforms.
> +
> + Enables the ME FW services required for PXP support through
> + I915 display driver of Intel.
> diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
> new file mode 100644
> index ..0329950d5794
> --- /dev/null
> +++ b/drivers/misc/mei/pxp/Makefile
> @@ -0,0 +1,7 @@
> +# SPDX-License-Identifier: GPL-2.0
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.
> +#
> +# Makefile - PXP client driver for Intel MEI Bus Driver.
> +
> +obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
> diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
> new file mode 100644
> index ..f7380d387bab
> --- /dev/null
> +++ b/drivers/misc/mei/pxp/mei_pxp.c
> @@ -0,0 +1,229 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright © 2020 - 2021 Intel Corporation
> + */
> +
> +/**
> + * DOC: MEI_PXP Client Driver
> + *
> + * The mei_pxp driver acts as a translation layer between PXP
> + * protocol implementer (I915) and ME FW by translating PXP
> + * negotiation messages to ME FW command payloads and vice versa.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "mei_pxp.h"
> +
> +/**
> + * mei_pxp_send_message() - Sends a PXP message to ME FW.
> + * @dev: device corresponding to the mei_cl_device
> + * @message: a message buffer to send
> + * @size: size of the message
> + * Return: 0 on Success, <0 on Failure
> + */
> +static int
> +mei_pxp_send_message(struct device *dev, const void *message, size_t size)
> +{
> + struct mei_cl_device *cldev;
> + ssize_t byte;
> +
> + if (!dev || !message)
> + return -EINVAL;
> +
> + cldev = to_mei_cl_device(dev);
> +
> + /* temporary drop const qualifier till the API is fixed */
> + byte = mei_cldev_send(cldev, (u8 *)message, size);
> + if (byte < 0) {
> + dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
> + return byte;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * mei_pxp_receive_message() - Receives a PXP message from ME FW.
> + * @dev: device corresponding to the mei_cl_device
> + * @buffer: a message buffer to contain the received message
> + * @size: size of the buffer
> + * Return: bytes sent on Success, <0 on Failure
> + */
> +static int
> +mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
> +{
> + struct mei_cl_device *cldev;
> + ssize_t byte;
> +
> + if (!dev || !buffer)
> + return -EINVAL;
> +
> + cldev = to_mei_cl_device(dev);
> +
> + byte = mei_cldev_recv(cldev, buffer, size);
> + if (byte < 0) {
> + dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
> +
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/selftests: fixup igt_shrink_thp
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: fixup igt_shrink_thp
URL : https://patchwork.freedesktop.org/series/93176/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10418_full -> Patchwork_20739_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20739_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20739_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20739_full:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@hugepages:
- shard-skl: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/shard-skl5/igt@i915_selftest@l...@hugepages.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/shard-skl7/igt@i915_selftest@l...@hugepages.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_busy@extended-pageflip-hang-newfb:
- {shard-rkl}:NOTRUN -> [SKIP][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/shard-rkl-2/igt@kms_b...@extended-pageflip-hang-newfb.html
* igt@kms_draw_crc@draw-method-rgb565-blt-ytiled:
- {shard-rkl}:[SKIP][4] ([fdo#111314]) -> [DMESG-WARN][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/shard-rkl-5/igt@kms_draw_...@draw-method-rgb565-blt-ytiled.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/shard-rkl-6/igt@kms_draw_...@draw-method-rgb565-blt-ytiled.html
* igt@runner@aborted:
- {shard-rkl}:([FAIL][6], [FAIL][7], [FAIL][8], [FAIL][9],
[FAIL][10]) ([i915#3002] / [i915#3810] / [i915#3811] / [i915#3871]) ->
([FAIL][11], [FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15], [FAIL][16])
([i915#2029] / [i915#3002] / [i915#3810] / [i915#3811] / [i915#3871])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/shard-rkl-2/igt@run...@aborted.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/shard-rkl-2/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/shard-rkl-1/igt@run...@aborted.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/shard-rkl-1/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/shard-rkl-6/igt@run...@aborted.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/shard-rkl-5/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/shard-rkl-6/igt@run...@aborted.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/shard-rkl-1/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/shard-rkl-5/igt@run...@aborted.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/shard-rkl-6/igt@run...@aborted.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/shard-rkl-6/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_20739_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-apl: NOTRUN -> [DMESG-WARN][17] ([i915#180]) +1 similar
issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/shard-apl3/igt@gem_ctx_isolation@preservation...@bcs0.html
* igt@gem_ctx_persistence@legacy-engines-hostile-preempt:
- shard-snb: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#1099]) +2
similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-hostile-preempt.html
* igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][19] -> [FAIL][20] ([i915#2410])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/shard-tglb7/igt@gem_ctx_persiste...@many-contexts.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: NOTRUN -> [FAIL][21] ([i915#2842])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/shard-kbl1/igt@gem_exec_fair@basic-p...@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][22] -> [FAIL][23] ([i915#2842])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10418/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20739/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html
- shard-iclb:
[Intel-gfx] [PULL] drm-misc-next
drm-misc-next-2021-07-29:
drm-misc-next for v5.15:
UAPI Changes:
- Add modifiers for arm fixed rate compression.
Cross-subsystem Changes:
- Assorted dt binding fixes.
- Convert ssd1307fb to json-schema.
- Update a lot of irc channels to point to OFTC, as everyone moved there.
- Fix the same divide by zero for asilantfb, kyro, rivafb.
Core Changes:
- Document requirements for new atomic properties.
- Add drm_gem_fb_(begin/end)_cpu_access helpers, and use them in some drivers.
- Document drm_property_enum.value for bitfields.
- Add explicit _NO_ for MIPI_DSI flags that disable features.
- Assorted documentation fixes.
- Update fb_damage handling, and move drm_plane_enable_fb_damage_clips to core.
- Add logging and docs to RMFB ioctl.
- Assorted small fixes to dp_mst, master handling.
- Clarify drm lease usage.
Driver Changes:
- Assorted small fixes to panfrost, hibmc, bridge/nwl-dsi, rockchip, vc4.
- More drm -> linux irq conversions.
- Add support for some Logic Technologies and Multi-Inno panels.
- Expose phy-functionality for drm/rockchip, to allow controlling from the
media subsystem.
- Add support for 2 AUO panels.
- Add damage handling to ssd1307fb.
- Improve FIFO handling on mxsfb.
- Assorted small fixes to vmwgfx, and bump version to 2.19 for the new ioctls.
- Improve sony acx424akp backlight handling.
The following changes since commit 15d27b15de965043d6f8e23bc7f34386fcd1a772:
efi: sysfb_efi: fix build when EFI is not set (2021-07-27 11:52:51 +0200)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2021-07-29
for you to fetch changes up to c7d30623540b6e979d7e8647fab18feab4688808:
drm/vc4: hdmi: Remove unused struct (2021-07-29 10:41:16 +0200)
drm-misc-next for v5.15:
UAPI Changes:
- Add modifiers for arm fixed rate compression.
Cross-subsystem Changes:
- Assorted dt binding fixes.
- Convert ssd1307fb to json-schema.
- Update a lot of irc channels to point to OFTC, as everyone moved there.
- Fix the same divide by zero for asilantfb, kyro, rivafb.
Core Changes:
- Document requirements for new atomic properties.
- Add drm_gem_fb_(begin/end)_cpu_access helpers, and use them in some drivers.
- Document drm_property_enum.value for bitfields.
- Add explicit _NO_ for MIPI_DSI flags that disable features.
- Assorted documentation fixes.
- Update fb_damage handling, and move drm_plane_enable_fb_damage_clips to core.
- Add logging and docs to RMFB ioctl.
- Assorted small fixes to dp_mst, master handling.
- Clarify drm lease usage.
Driver Changes:
- Assorted small fixes to panfrost, hibmc, bridge/nwl-dsi, rockchip, vc4.
- More drm -> linux irq conversions.
- Add support for some Logic Technologies and Multi-Inno panels.
- Expose phy-functionality for drm/rockchip, to allow controlling from the
media subsystem.
- Add support for 2 AUO panels.
- Add damage handling to ssd1307fb.
- Improve FIFO handling on mxsfb.
- Assorted small fixes to vmwgfx, and bump version to 2.19 for the new ioctls.
- Improve sony acx424akp backlight handling.
Alexander Sverdlin (1):
video: ep93xx: Prepare clock before using it
Alyssa Rosenzweig (2):
documentation: Update #nouveau IRC channel network
maintainers: Update freedesktop.org IRC channels
Artjom Vejsel (1):
dt-bindings: Add QiShenglong vendor prefix
Bjorn Andersson (2):
dt-bindings: display: simple: Add AUO B133HAN05 & B140HAN06
drm/panel: simple: Add support for two more AUO panels
Chris Morgan (1):
drm/panfrost: devfreq: Don't display error for EPROBE_DEFER
Daniel Vetter (3):
drm/plane: remove drm_helper_get_plane_damage_clips
drm/plane: check that fb_damage is set up when used
drm/plane: Move drm_plane_enable_fb_damage_clips into core
Desmond Cheong Zhi Xi (2):
drm: use the lookup lock in drm_is_current_master
drm: clarify usage of drm leases
Geert Uytterhoeven (7):
drm/bridge: nwl-dsi: Avoid potential multiplication overflow on 32-bit
dt-bindings: display: ssd1307fb: Convert to json-schema
video: fbdev: ssd1307fb: Propagate errors via ssd1307fb_update_display()
video: fbdev: ssd1307fb: Simplify ssd1307fb_update_display()
video: fbdev: ssd1307fb: Extract ssd1307fb_set_{col,page}_range()
video: fbdev: ssd1307fb: Optimize screen updates
video: fbdev: ssd1307fb: Cache address ranges
Heiko Stuebner (3):
drm/rockchip: dsi: add own additional pclk handling
dt-bindings: display: rockchip-dsi: add optional #phy-cells property
drm/rockchip: dsi: add ability to work as a phy instead of full dsi
Jagan Teki (1):
drm/bridge: dw-mipi-dsi: Find the possible DSI devices
Jose Maria Casanova Crespo (1):
drm/prime: fix comment on PRIME Helpers
Linus Walleij (1):
drm/panel-sony-acx424akp: Modernize backlight handling
Maarten Lankhorst
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Remove CNL - for drm-intel-next (rev2)
== Series Details == Series: Remove CNL - for drm-intel-next (rev2) URL : https://patchwork.freedesktop.org/series/93142/ State : failure == Summary == Applying: drm/i915/display: remove PORT_F workaround for CNL Applying: drm/i915/display: remove explicit CNL handling from intel_cdclk.c Applying: drm/i915/display: remove explicit CNL handling from intel_color.c Applying: drm/i915/display: remove explicit CNL handling from intel_combo_phy.c Applying: drm/i915/display: remove explicit CNL handling from intel_crtc.c Applying: drm/i915/display: remove explicit CNL handling from intel_ddi.c Applying: drm/i915/display: remove explicit CNL handling from intel_display_debugfs.c Applying: drm/i915/display: remove explicit CNL handling from intel_dmc.c Applying: drm/i915/display: remove explicit CNL handling from intel_dp.c Applying: drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.c error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_reg.h). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0010 drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.c When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Forcewake and shadowed register updates (rev2)
== Series Details ==
Series: Forcewake and shadowed register updates (rev2)
URL : https://patchwork.freedesktop.org/series/93158/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10420 -> Patchwork_20742
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/index.html
Known issues
Here are the changes found in Patchwork_20742 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +26 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [PASS][2] -> [FAIL][3] ([i915#1888])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-soraka: NOTRUN -> [FAIL][5] ([i915#579])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/fi-kbl-soraka/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][6] ([i915#1886] / [i915#2291])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][9] ([i915#541]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10420/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
Participating hosts (39 -> 34)
--
Additional (1): fi-kbl-soraka
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus bat-jsl-1
Build changes
-
* Linux: CI_DRM_10420 -> Patchwork_20742
CI-20190529: 20190529
CI_DRM_10420: 863957775825d20952875034f22937aec4a71a23 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6158: bb1c96b29234f86cd71d9cbd019aafada9097f24 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20742: 3a2f554722e7d0e7647f92a15261b050db56cdf7 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3a2f554722e7 drm/i915/xehp: Xe_HP shadowed registers are a strict superset of
gen12
4dc7a69ce015 drm/i915/gen12: Update shadowed register table
d4c8c1f86808 drm/i915/gen11: Update shadowed register table
c5be365b37c9 drm/i915: Make shadow tables range-based
7e96fc94addf drm/i915: Re-use gen11 forcewake read functions on gen12
32ceffc23e74 drm/i915: correct name of GT forcewake domain in error messages
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20742/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Begin enabling Xe_HP SDV and DG2 platforms (rev8)
== Series Details == Series: Begin enabling Xe_HP SDV and DG2 platforms (rev8) URL : https://patchwork.freedesktop.org/series/92135/ State : failure == Summary == Applying: drm/i915/xehp: handle new steering options Applying: drm/i915/xehpsdv: Define steering tables Applying: drm/i915/dg2: Add forcewake table Applying: drm/i915/dg2: Update LNCF steering ranges Applying: drm/i915/dg2: Add SQIDI steering Applying: drm/i915/xehp: Loop over all gslices for INSTDONE processing Applying: drm/i915/dg2: Report INSTDONE_GEOM values in error state Applying: drm/i915/xehp: Changes to ss/eu definitions Applying: drm/i915/xehpsdv: Add maximum sseu limits Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gt/intel_sseu.c M drivers/gpu/drm/i915/gt/intel_sseu.h M drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c Auto-merging drivers/gpu/drm/i915/gt/intel_sseu.h CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_sseu.h Auto-merging drivers/gpu/drm/i915/gt/intel_sseu.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0009 drm/i915/xehpsdv: Add maximum sseu limits When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/6] drm/i915: Re-use gen11 forcewake read functions on gen12
Reviewed-by: Caz Yokoyama
-caz
On Wed, 2021-07-28 at 22:41 -0700, Matt Roper wrote:
> The forcewake read logic is identical between gen11 and gen12, only
> the
> forcewake table data (which is tracked separately) differs; there's
> no
> need to generate a separate set of gen12 read functions when the
> gen11
> functions will work just as well.
>
> We'll keep the separate write functions for now since the generated
> code
> directly references different shadow tables between the two
> platforms.
>
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 6 +-
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index bca548c81572..ea910f7ee635 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -945,9 +945,6 @@ static const struct intel_forcewake_range
> __vlv_fw_ranges[] = {
> #define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
> find_fw_domain(uncore, offset)
>
> -#define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \
> - find_fw_domain(uncore, offset)
> -
> /* *Must* be sorted by offset! See intel_shadow_table_check(). */
> static const i915_reg_t gen8_shadowed_regs[] = {
> RING_TAIL(RENDER_RING_BASE),/* 0x2000 (base) */
> @@ -1617,7 +1614,6 @@ __gen_read(func, 16) \
> __gen_read(func, 32) \
> __gen_read(func, 64)
>
> -__gen_reg_read_funcs(gen12_fwtable);
> __gen_reg_read_funcs(gen11_fwtable);
> __gen_reg_read_funcs(fwtable);
> __gen_reg_read_funcs(gen6);
> @@ -2091,7 +2087,7 @@ static int uncore_forcewake_init(struct
> intel_uncore *uncore)
> } else if (GRAPHICS_VER(i915) >= 12) {
> ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
> ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);
> - ASSIGN_READ_MMIO_VFUNCS(uncore, gen12_fwtable);
> + ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
> } else if (GRAPHICS_VER(i915) == 11) {
> ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
> ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable);
___
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[Intel-gfx] [PATCH CI 03/10] drm/i915/bios: Enable parse of two integrated panels timing data
Continuing the conversion from single integrated VBT data to two.
Reviewed-by: Matt Atwood
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c| 53 +---
drivers/gpu/drm/i915/display/intel_bios.h| 1 +
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 7 ++-
drivers/gpu/drm/i915/display/intel_panel.c | 7 +--
drivers/gpu/drm/i915/i915_drv.h | 3 +-
5 files changed, 48 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 9439bfe32b136..fdde8777854ee 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -289,14 +289,15 @@ parse_panel_options(struct drm_i915_private *i915,
/* Try to find integrated panel timing data */
static void
parse_lfp_panel_dtd(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
{
const struct bdb_lvds_lfp_data *lvds_lfp_data;
const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
const struct lvds_dvo_timing *panel_dvo_timing;
const struct lvds_fp_timing *fp_timing;
struct drm_display_mode *panel_fixed_mode;
- int panel_type = i915->vbt.panel_type;
lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
if (!lvds_lfp_data)
@@ -308,7 +309,7 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915,
panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data,
lvds_lfp_data_ptrs,
- panel_type);
+ panel_index);
panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
if (!panel_fixed_mode)
@@ -316,7 +317,7 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915,
fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing);
- i915->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
+ info->lfp_lvds_vbt_mode = panel_fixed_mode;
drm_dbg_kms(&i915->drm,
"Found panel mode in BIOS VBT legacy lfp table:\n");
@@ -324,7 +325,7 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915,
fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data,
lvds_lfp_data_ptrs,
- panel_type);
+ panel_index);
if (fp_timing) {
/* check the resolution, just to be sure */
if (fp_timing->x_res == panel_fixed_mode->hdisplay &&
@@ -339,7 +340,9 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915,
static void
parse_generic_dtd(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
{
const struct bdb_generic_dtd *generic_dtd;
const struct generic_dtd_entry *dtd;
@@ -363,14 +366,14 @@ parse_generic_dtd(struct drm_i915_private *i915,
num_dtd = (get_blocksize(generic_dtd) -
sizeof(struct bdb_generic_dtd)) / generic_dtd->gdtd_size;
- if (i915->vbt.panel_type >= num_dtd) {
+ if (panel_index >= num_dtd) {
drm_err(&i915->drm,
- "Panel type %d not found in table of %d DTD's\n",
- i915->vbt.panel_type, num_dtd);
+ "Panel index %d not found in table of %d DTD's\n",
+ panel_index, num_dtd);
return;
}
- dtd = &generic_dtd->dtd[i915->vbt.panel_type];
+ dtd = &generic_dtd->dtd[panel_index];
panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
if (!panel_fixed_mode)
@@ -413,12 +416,14 @@ parse_generic_dtd(struct drm_i915_private *i915,
"Found panel mode in BIOS VBT generic dtd table:\n");
drm_mode_debug_printmodeline(panel_fixed_mode);
- i915->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
+ info->lfp_lvds_vbt_mode = panel_fixed_mode;
}
static void
parse_panel_dtd(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
{
/*
* Older VBTs provided provided DTD information for internal displays
@@ -429,9 +434,9 @@ parse_panel_dtd(struct drm_i915_private *i915,
* back to trying the old LFP block if that fails.
*/
if (bdb->version >= 229)
- parse_generic_dtd(i915, bdb);
- if (!i915->vbt.lfp_lvds_vbt_mode)
- parse_lfp_panel_dtd(i915, bdb);
+ parse_generic_dtd(
[Intel-gfx] [PATCH CI 04/10] drm/i915/bios: Enable parse of two integrated panels backlight data
Continuing the conversion from single integrated VBT data to two, now
handling backlight data.
Reviewed-by: Matt Atwood
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 59 +++
drivers/gpu/drm/i915/display/intel_bios.h | 1 +
.../drm/i915/display/intel_dp_aux_backlight.c | 11 ++--
.../i915/display/intel_dsi_dcs_backlight.c| 5 +-
drivers/gpu/drm/i915/display/intel_panel.c| 32 ++
drivers/gpu/drm/i915/display/intel_pps.c | 8 ++-
drivers/gpu/drm/i915/i915_drv.h | 18 +++---
7 files changed, 83 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index fdde8777854ee..de461cc9fead9 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -441,11 +441,12 @@ parse_panel_dtd(struct drm_i915_private *i915,
static void
parse_lfp_backlight(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
{
const struct bdb_lfp_backlight_data *backlight_data;
const struct lfp_backlight_data_entry *entry;
- int panel_type = i915->vbt.panel_type;
u16 level;
backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
@@ -459,38 +460,38 @@ parse_lfp_backlight(struct drm_i915_private *i915,
return;
}
- entry = &backlight_data->data[panel_type];
+ entry = &backlight_data->data[panel_index];
- i915->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
- if (!i915->vbt.backlight.present) {
+ info->backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
+ if (!info->backlight.present) {
drm_dbg_kms(&i915->drm,
"PWM backlight not present in VBT (type %u)\n",
entry->type);
return;
}
- i915->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
+ info->backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
if (bdb->version >= 191 &&
get_blocksize(backlight_data) >= sizeof(*backlight_data)) {
const struct lfp_backlight_control_method *method;
- method = &backlight_data->backlight_control[panel_type];
- i915->vbt.backlight.type = method->type;
- i915->vbt.backlight.controller = method->controller;
+ method = &backlight_data->backlight_control[panel_index];
+ info->backlight.type = method->type;
+ info->backlight.controller = method->controller;
}
- i915->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
- i915->vbt.backlight.active_low_pwm = entry->active_low_pwm;
+ info->backlight.pwm_freq_hz = entry->pwm_freq_hz;
+ info->backlight.active_low_pwm = entry->active_low_pwm;
if (bdb->version >= 234) {
u16 min_level;
bool scale;
- level = backlight_data->brightness_level[panel_type].level;
- min_level =
backlight_data->brightness_min_level[panel_type].level;
+ level = backlight_data->brightness_level[panel_index].level;
+ min_level =
backlight_data->brightness_min_level[panel_index].level;
if (bdb->version >= 236)
- scale =
backlight_data->brightness_precision_bits[panel_type] == 16;
+ scale =
backlight_data->brightness_precision_bits[panel_index] == 16;
else
scale = level > 255;
@@ -501,20 +502,20 @@ parse_lfp_backlight(struct drm_i915_private *i915,
drm_warn(&i915->drm, "Brightness min level > 255\n");
level = 255;
}
- i915->vbt.backlight.min_brightness = min_level;
+ info->backlight.min_brightness = min_level;
} else {
- level = backlight_data->level[panel_type];
- i915->vbt.backlight.min_brightness = entry->min_brightness;
+ level = backlight_data->level[panel_index];
+ info->backlight.min_brightness = entry->min_brightness;
}
drm_dbg_kms(&i915->drm,
"VBT backlight PWM modulation frequency %u Hz, "
"active %s, min brightness %u, level %u, controller %u\n",
- i915->vbt.backlight.pwm_freq_hz,
- i915->vbt.backlight.active_low_pwm ? "low" : "high",
- i915->vbt.backlight.min_brightness,
+ info->backlight.pwm_freq_hz,
+ info->backlight.active_low_pwm ? "low" : "high",
+ info->backlight.min_brightness,
level,
-
[Intel-gfx] [PATCH CI 07/10] drm/i915/bios: Enable parse of two DSI panels data
Continuing the conversion from single integrated VBT data to two, now
handling DSI data.
Reviewed-by: Matt Atwood
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/icl_dsi.c | 12 +-
drivers/gpu/drm/i915/display/intel_bios.c| 163 ++-
drivers/gpu/drm/i915/display/intel_bios.h| 1 +
drivers/gpu/drm/i915/display/intel_dsi.c | 8 +-
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 58 ---
drivers/gpu/drm/i915/display/intel_panel.c | 3 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 14 +-
drivers/gpu/drm/i915/i915_drv.h | 30 ++--
8 files changed, 161 insertions(+), 128 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 43ec7fcd3f5d2..0a8360d196cc7 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1846,7 +1846,8 @@ static void icl_dphy_param_init(struct intel_dsi
*intel_dsi)
{
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
+ const struct vbt_dsi_info *vbt_dsi_info =
intel_bios_dsi_info(&intel_dsi->base);
+ struct mipi_config *mipi_config = vbt_dsi_info->config;
u32 tlpx_ns;
u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
u32 ths_prepare_ns, tclk_trail_ns;
@@ -1977,6 +1978,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
struct intel_connector *intel_connector;
struct drm_connector *connector;
struct drm_display_mode *fixed_mode;
+ const struct vbt_dsi_info *vbt_dsi_info;
enum port port;
if (!intel_bios_is_dsi_present(dev_priv, &port))
@@ -2044,13 +2046,15 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
intel_panel_setup_backlight(connector, INVALID_PIPE);
- if (dev_priv->vbt.dsi.config->dual_link)
+ vbt_dsi_info = intel_bios_dsi_info(encoder);
+
+ if (vbt_dsi_info->config->dual_link)
intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
else
intel_dsi->ports = BIT(port);
- intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
- intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
+ intel_dsi->dcs_backlight_ports = vbt_dsi_info->bl_ports;
+ intel_dsi->dcs_cabc_ports = vbt_dsi_info->cabc_ports;
for_each_dsi_port(port, intel_dsi->ports) {
struct intel_dsi_host *host;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 40fa63336cd9d..aa98bef4b8a57 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1022,55 +1022,56 @@ parse_psr(struct drm_i915_private *i915, const struct
bdb_header *bdb,
}
static void parse_dsi_backlight_ports(struct drm_i915_private *i915,
- u16 version, enum port port)
+ u16 version, enum port port,
+ struct ddi_vbt_port_info *info)
{
- if (!i915->vbt.dsi.config->dual_link || version < 197) {
- i915->vbt.dsi.bl_ports = BIT(port);
- if (i915->vbt.dsi.config->cabc_supported)
- i915->vbt.dsi.cabc_ports = BIT(port);
+ if (!info->dsi.config->dual_link || version < 197) {
+ info->dsi.bl_ports = BIT(port);
+ if (info->dsi.config->cabc_supported)
+ info->dsi.cabc_ports = BIT(port);
return;
}
- switch (i915->vbt.dsi.config->dl_dcs_backlight_ports) {
+ switch (info->dsi.config->dl_dcs_backlight_ports) {
case DL_DCS_PORT_A:
- i915->vbt.dsi.bl_ports = BIT(PORT_A);
+ info->dsi.bl_ports = BIT(PORT_A);
break;
case DL_DCS_PORT_C:
- i915->vbt.dsi.bl_ports = BIT(PORT_C);
+ info->dsi.bl_ports = BIT(PORT_C);
break;
default:
case DL_DCS_PORT_A_AND_C:
- i915->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C);
+ info->dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C);
break;
}
- if (!i915->vbt.dsi.config->cabc_supported)
+ if (!info->dsi.config->cabc_supported)
return;
- switch (i915->vbt.dsi.config->dl_dcs_cabc_ports) {
+ switch (info->dsi.config->dl_dcs_cabc_ports) {
case DL_DCS_PORT_A:
- i915->vbt.dsi.cabc_ports = BIT(PORT_A);
+ info->dsi.cabc_ports = BIT(PORT_A);
break;
case DL_DCS_PORT_C:
- i915->vbt.dsi.cabc_ports = BIT(PORT_C);
+ info->dsi.cabc_ports = BIT(PORT_C);
break;
[Intel-gfx] [PATCH CI 05/10] drm/i915/bios: Enable parse of two integrated panels eDP data
Continuing the conversion from single integrated VBT data to two, now
handling eDP data.
Reviewed-by: Matt Atwood
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/g4x_dp.c | 9 ++-
drivers/gpu/drm/i915/display/intel_bios.c | 62 ---
drivers/gpu/drm/i915/display/intel_bios.h | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 9 ++-
.../drm/i915/display/intel_ddi_buf_trans.c| 77 ++-
drivers/gpu/drm/i915/display/intel_dp.c | 7 +-
drivers/gpu/drm/i915/display/intel_pps.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 24 +++---
8 files changed, 104 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
b/drivers/gpu/drm/i915/display/g4x_dp.c
index de0f358184aa3..273bc5295ae33 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -340,6 +340,7 @@ static void intel_dp_get_config(struct intel_encoder
*encoder,
u32 tmp, flags = 0;
enum port port = encoder->port;
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct vbt_edp_info *vbt_edp_info = intel_bios_edp_info(encoder);
if (encoder->type == INTEL_OUTPUT_EDP)
pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
@@ -396,8 +397,8 @@ static void intel_dp_get_config(struct intel_encoder
*encoder,
intel_dotclock_calculate(pipe_config->port_clock,
&pipe_config->dp_m_n);
- if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
- pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
+ if (intel_dp_is_edp(intel_dp) && vbt_edp_info->bpp &&
+ pipe_config->pipe_bpp > vbt_edp_info->bpp) {
/*
* This is a big fat ugly hack.
*
@@ -413,8 +414,8 @@ static void intel_dp_get_config(struct intel_encoder
*encoder,
*/
drm_dbg_kms(&dev_priv->drm,
"pipe has %d bpp for eDP panel, overriding
BIOS-provided max %d bpp\n",
- pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
- dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
+ pipe_config->pipe_bpp, vbt_edp_info->bpp);
+ vbt_edp_info->bpp = pipe_config->pipe_bpp;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index de461cc9fead9..dac81a5ebdaa0 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -786,45 +786,45 @@ parse_power_conservation_features(struct drm_i915_private
*i915,
info->drrs_type = DRRS_NOT_SUPPORTED;
if (bdb->version >= 232)
- i915->vbt.edp.hobl = power->hobl & BIT(panel_index);
+ info->edp.hobl = power->hobl & BIT(panel_index);
}
static void
-parse_edp(struct drm_i915_private *i915, const struct bdb_header *bdb)
+parse_edp(struct drm_i915_private *i915, const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info, int panel_index)
{
const struct bdb_edp *edp;
const struct edp_power_seq *edp_pps;
const struct edp_fast_link_params *edp_link_params;
- int panel_type = i915->vbt.panel_type;
edp = find_section(bdb, BDB_EDP);
if (!edp)
return;
- switch ((edp->color_depth >> (panel_type * 2)) & 3) {
+ switch ((edp->color_depth >> (panel_index * 2)) & 3) {
case EDP_18BPP:
- i915->vbt.edp.bpp = 18;
+ info->edp.bpp = 18;
break;
case EDP_24BPP:
- i915->vbt.edp.bpp = 24;
+ info->edp.bpp = 24;
break;
case EDP_30BPP:
- i915->vbt.edp.bpp = 30;
+ info->edp.bpp = 30;
break;
}
/* Get the eDP sequencing and link info */
- edp_pps = &edp->power_seqs[panel_type];
- edp_link_params = &edp->fast_link_params[panel_type];
+ edp_pps = &edp->power_seqs[panel_index];
+ edp_link_params = &edp->fast_link_params[panel_index];
- i915->vbt.edp.pps = *edp_pps;
+ info->edp.pps = *edp_pps;
switch (edp_link_params->rate) {
case EDP_RATE_1_62:
- i915->vbt.edp.rate = DP_LINK_BW_1_62;
+ info->edp.rate = DP_LINK_BW_1_62;
break;
case EDP_RATE_2_7:
- i915->vbt.edp.rate = DP_LINK_BW_2_7;
+ info->edp.rate = DP_LINK_BW_2_7;
break;
default:
drm_dbg_kms(&i915->drm,
@@ -835,13 +835,13 @@ parse_edp(struct drm_i915_private *i915, const struct
bdb_header *bdb)
switch (edp_link_params->lanes) {
case EDP_LANE_1:
- i915->vbt.edp.lanes = 1;
+ info->edp.lanes = 1;
[Intel-gfx] [PATCH CI 02/10] drm/i915/bios: Start to support two integrated panels
VBT has support for up two integrated panels but i915 only supports one.
So here stating to add the basic support for two integrated panels
and moving the DRRS to ddi_vbt_port_info instead of keeping a global
one.
Other VBT blocks will be converted in following patches.
While at is also nucking lvds_dither as it is not used.
Reviewed-by: Matt Atwood
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 185 +-
drivers/gpu/drm/i915/display/intel_bios.h | 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 5 +-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 5 +-
5 files changed, 150 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index a6cb33f847a43..9439bfe32b136 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -211,22 +211,20 @@ get_lvds_fp_timing(const struct bdb_header *bdb,
return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
}
-/* Parse general panel options */
-static void
-parse_panel_options(struct drm_i915_private *i915,
- const struct bdb_header *bdb)
+/*
+ * Parse and set vbt.panel_type, it will be used by the VBT blocks that are
+ * not being called from parse_integrated_panel() yet.
+ */
+static void parse_panel_type(struct drm_i915_private *i915,
+const struct bdb_header *bdb)
{
const struct bdb_lvds_options *lvds_options;
- int panel_type;
- int drrs_mode;
- int ret;
+ int ret, panel_type;
lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
if (!lvds_options)
return;
- i915->vbt.lvds_dither = lvds_options->pixel_dither;
-
ret = intel_opregion_get_panel_type(i915);
if (ret >= 0) {
drm_WARN_ON(&i915->drm, ret > 0xf);
@@ -246,9 +244,25 @@ parse_panel_options(struct drm_i915_private *i915,
}
i915->vbt.panel_type = panel_type;
+}
+
+/* Parse general panel options */
+static void
+parse_panel_options(struct drm_i915_private *i915,
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info,
+ int panel_index)
+{
+ const struct bdb_lvds_options *lvds_options;
+ int drrs_mode;
+
+ lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
+ if (!lvds_options)
+ return;
+
+ drrs_mode = lvds_options->dps_panel_type_bits >> (panel_index * 2);
+ drrs_mode &= MODE_MASK;
- drrs_mode = (lvds_options->dps_panel_type_bits
- >> (panel_type * 2)) & MODE_MASK;
/*
* VBT has static DRRS = 0 and seamless DRRS = 2.
* The below piece of code is required to adjust vbt.drrs_type
@@ -256,16 +270,16 @@ parse_panel_options(struct drm_i915_private *i915,
*/
switch (drrs_mode) {
case 0:
- i915->vbt.drrs_type = STATIC_DRRS_SUPPORT;
+ info->drrs_type = STATIC_DRRS_SUPPORT;
drm_dbg_kms(&i915->drm, "DRRS supported mode is static\n");
break;
case 2:
- i915->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT;
+ info->drrs_type = SEAMLESS_DRRS_SUPPORT;
drm_dbg_kms(&i915->drm,
"DRRS supported mode is seamless\n");
break;
default:
- i915->vbt.drrs_type = DRRS_NOT_SUPPORTED;
+ info->drrs_type = DRRS_NOT_SUPPORTED;
drm_dbg_kms(&i915->drm,
"DRRS not supported (VBT input)\n");
break;
@@ -710,28 +724,42 @@ parse_driver_features(struct drm_i915_private *i915,
i915->vbt.int_lvds_support = 0;
}
- if (bdb->version < 228) {
- drm_dbg_kms(&i915->drm, "DRRS State Enabled:%d\n",
- driver->drrs_enabled);
- /*
-* If DRRS is not supported, drrs_type has to be set to 0.
-* This is because, VBT is configured in such a way that
-* static DRRS is 0 and DRRS not supported is represented by
-* driver->drrs_enabled=false
-*/
- if (!driver->drrs_enabled)
- i915->vbt.drrs_type = DRRS_NOT_SUPPORTED;
-
+ if (bdb->version < 228)
i915->vbt.psr.enable = driver->psr_enabled;
- }
+}
+
+static void
+parse_driver_features_drrs_only(struct drm_i915_private *i915,
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info)
+{
+ const struct bdb_driver_features *driver;
+
+ if (bdb->version >= 228)
+ return;
+
+ driver = find_sectio
[Intel-gfx] [PATCH CI 10/10] drm/i915/display/tgl+: Use PPS index from vbt
Tigerlake and newer has two instances of PPS, to support up to two eDP panels. Reviewed-by: Matt Atwood Cc: Ville Syrjälä Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_pps.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index f4c15a1f31d15..ee92f416834e5 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -368,7 +368,8 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, memset(regs, 0, sizeof(*regs)); - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || + DISPLAY_VER(dev_priv) >= 12) pps_idx = bxt_power_sequencer_idx(intel_dp); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) pps_idx = vlv_power_sequencer_pipe(intel_dp); -- 2.32.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH CI 06/10] drm/i915/bios: Enable parse of two integrated panels PSR data
Continuing the conversion from single integrated VBT data to two, now
handling PSR data.
Reviewed-by: Matt Atwood
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 73 +--
drivers/gpu/drm/i915/display/intel_bios.h | 2 +
drivers/gpu/drm/i915/display/intel_psr.c | 30 ++
drivers/gpu/drm/i915/i915_drv.h | 34 +--
4 files changed, 77 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index dac81a5ebdaa0..40fa63336cd9d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -729,15 +729,12 @@ parse_driver_features(struct drm_i915_private *i915,
driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS)
i915->vbt.int_lvds_support = 0;
}
-
- if (bdb->version < 228)
- i915->vbt.psr.enable = driver->psr_enabled;
}
static void
-parse_driver_features_drrs_only(struct drm_i915_private *i915,
- const struct bdb_header *bdb,
- struct ddi_vbt_port_info *info)
+parse_driver_features_drrs_psr_only(struct drm_i915_private *i915,
+ const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info)
{
const struct bdb_driver_features *driver;
@@ -757,6 +754,8 @@ parse_driver_features_drrs_only(struct drm_i915_private
*i915,
*/
if (!driver->drrs_enabled)
info->drrs_type = DRRS_NOT_SUPPORTED;
+
+ info->psr.enable = driver->psr_enabled;
}
static void
@@ -774,7 +773,7 @@ parse_power_conservation_features(struct drm_i915_private
*i915,
if (!power)
return;
- i915->vbt.psr.enable = power->psr & BIT(panel_index);
+ info->psr.enable = power->psr & BIT(panel_index);
/*
* If DRRS is not supported, drrs_type has to be set to 0.
@@ -905,11 +904,11 @@ parse_edp(struct drm_i915_private *i915, const struct
bdb_header *bdb,
}
static void
-parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb)
+parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb,
+ struct ddi_vbt_port_info *info, int panel_index)
{
const struct bdb_psr *psr;
const struct psr_table *psr_table;
- int panel_type = i915->vbt.panel_type;
psr = find_section(bdb, BDB_PSR);
if (!psr) {
@@ -917,27 +916,27 @@ parse_psr(struct drm_i915_private *i915, const struct
bdb_header *bdb)
return;
}
- psr_table = &psr->psr_table[panel_type];
+ psr_table = &psr->psr_table[panel_index];
- i915->vbt.psr.full_link = psr_table->full_link;
- i915->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
+ info->psr.full_link = psr_table->full_link;
+ info->psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
/* Allowed VBT values goes from 0 to 15 */
- i915->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
+ info->psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;
switch (psr_table->lines_to_wait) {
case 0:
- i915->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
+ info->psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
break;
case 1:
- i915->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
+ info->psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
break;
case 2:
- i915->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
+ info->psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
break;
case 3:
- i915->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
+ info->psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
break;
default:
drm_dbg_kms(&i915->drm,
@@ -954,13 +953,13 @@ parse_psr(struct drm_i915_private *i915, const struct
bdb_header *bdb)
(DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915))) {
switch (psr_table->tp1_wakeup_time) {
case 0:
- i915->vbt.psr.tp1_wakeup_time_us = 500;
+ info->psr.tp1_wakeup_time_us = 500;
break;
case 1:
- i915->vbt.psr.tp1_wakeup_time_us = 100;
+ info->psr.tp1_wakeup_time_us = 100;
break;
case 3:
- i915->vbt.psr.tp1_wakeup_time_us = 0;
+ info->psr.tp1_wakeup_time_us = 0;
break;
default:
drm_dbg_kms(&i915->drm,
@@ -968,19 +967,19 @@ parse_psr(struct drm_i915_private *i915
[Intel-gfx] [PATCH CI 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port()
Allow MIPI DSI ports to be parsed like any other DDI port.
This will be helpful to integrate into just one function the parse of
information about integrated panels(eDP and DSI).
Cc: Ville Syrjälä
Cc: Jani Nikula
Reviewed-by: Matt Atwood
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index aa667fa711584..a6cb33f847a43 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1709,10 +1709,10 @@ static enum port dvo_port_to_port(struct
drm_i915_private *i915,
* so look for all the possible values for each port.
*/
static const int port_mapping[][3] = {
- [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
- [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
- [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
- [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+ [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, DVO_PORT_MIPIA },
+ [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, DVO_PORT_MIPIB },
+ [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, DVO_PORT_MIPIC },
+ [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, DVO_PORT_MIPID },
[PORT_E] = { DVO_PORT_HDMIE, DVO_PORT_DPE, DVO_PORT_CRT },
[PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
[PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
@@ -1868,6 +1868,12 @@ intel_bios_encoder_supports_edp(const struct
intel_bios_encoder_data *devdata)
devdata->child.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR;
}
+static bool
+intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata)
+{
+ return devdata->child.device_type & DEVICE_TYPE_MIPI_OUTPUT;
+}
+
static bool is_port_valid(struct drm_i915_private *i915, enum port port)
{
/*
@@ -1886,7 +1892,8 @@ static void parse_ddi_port(struct drm_i915_private *i915,
{
const struct child_device_config *child = &devdata->child;
struct ddi_vbt_port_info *info;
- bool is_dvi, is_hdmi, is_dp, is_edp, is_crt, supports_typec_usb,
supports_tbt;
+ bool is_dvi, is_hdmi, is_dp, is_edp, is_crt, supports_typec_usb;
+ bool supports_tbt, is_dsi;
int dp_boost_level, hdmi_boost_level;
enum port port;
@@ -1917,16 +1924,17 @@ static void parse_ddi_port(struct drm_i915_private
*i915,
is_crt = intel_bios_encoder_supports_crt(devdata);
is_hdmi = intel_bios_encoder_supports_hdmi(devdata);
is_edp = intel_bios_encoder_supports_edp(devdata);
+ is_dsi = intel_bios_encoder_supports_dsi(devdata);
supports_typec_usb = intel_bios_encoder_supports_typec_usb(devdata);
supports_tbt = intel_bios_encoder_supports_tbt(devdata);
drm_dbg_kms(&i915->drm,
- "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d
LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n",
+ "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d
LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d DSI:%d\n",
port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp,
HAS_LSPCON(i915) && child->lspcon,
supports_typec_usb, supports_tbt,
- devdata->dsc != NULL);
+ devdata->dsc != NULL, is_dsi);
if (is_dvi) {
u8 ddc_pin;
--
2.32.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH CI 08/10] drm/i915/bios: Nuke panel_type
All the users were converted, now we can drop it.
Reviewed-by: Matt Atwood
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 36 ---
drivers/gpu/drm/i915/i915_drv.h | 1 -
2 files changed, 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index aa98bef4b8a57..ded04e5b7772b 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -211,41 +211,6 @@ get_lvds_fp_timing(const struct bdb_header *bdb,
return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
}
-/*
- * Parse and set vbt.panel_type, it will be used by the VBT blocks that are
- * not being called from parse_integrated_panel() yet.
- */
-static void parse_panel_type(struct drm_i915_private *i915,
-const struct bdb_header *bdb)
-{
- const struct bdb_lvds_options *lvds_options;
- int ret, panel_type;
-
- lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
- if (!lvds_options)
- return;
-
- ret = intel_opregion_get_panel_type(i915);
- if (ret >= 0) {
- drm_WARN_ON(&i915->drm, ret > 0xf);
- panel_type = ret;
- drm_dbg_kms(&i915->drm, "Panel type: %d (OpRegion)\n",
- panel_type);
- } else {
- if (lvds_options->panel_type > 0xf) {
- drm_dbg_kms(&i915->drm,
- "Invalid VBT panel type 0x%x\n",
- lvds_options->panel_type);
- return;
- }
- panel_type = lvds_options->panel_type;
- drm_dbg_kms(&i915->drm, "Panel type: %d (VBT)\n",
- panel_type);
- }
-
- i915->vbt.panel_type = panel_type;
-}
-
/* Parse general panel options */
static void
parse_panel_options(struct drm_i915_private *i915,
@@ -2490,7 +2455,6 @@ void intel_bios_init(struct drm_i915_private *i915)
/* Grab useful general definitions */
parse_general_features(i915, bdb);
parse_general_definitions(i915, bdb);
- parse_panel_type(i915, bdb);
parse_sdvo_panel_data(i915, bdb);
parse_driver_features(i915, bdb);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3535759796033..ad8c838b7df41 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -723,7 +723,6 @@ struct intel_vbt_data {
unsigned int int_lvds_support:1;
unsigned int display_clock_mode:1;
unsigned int fdi_rx_polarity_inverted:1;
- unsigned int panel_type:4;
int lvds_ssc_freq;
unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
enum drm_panel_orientation orientation;
--
2.32.0
___
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[Intel-gfx] [PATCH CI 09/10] drm/i915/bios: Only use opregion panel index for display ver 8 and older
On newer platform this opregion call always fails, also it do not
support multiple panels so dropping it.
Reviewed-by: Matt Atwood
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 19 +++
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index ded04e5b7772b..8775983a75c6b 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1924,7 +1924,7 @@ static void parse_integrated_panel(struct
drm_i915_private *i915,
{
const struct vbt_header *vbt = i915->opregion.vbt;
const struct bdb_header *bdb;
- int lfp_inst = 0, panel_index, opregion_panel_index;
+ int lfp_inst = 0, panel_index;
if (devdata->child.handle == HANDLE_LFP_1)
lfp_inst = 1;
@@ -1937,17 +1937,12 @@ static void parse_integrated_panel(struct
drm_i915_private *i915,
bdb = get_bdb_header(vbt);
panel_index = get_lfp_panel_index(i915, bdb, lfp_inst);
- opregion_panel_index = intel_opregion_get_panel_type(i915);
- /*
-* TODO: the current implementation always use the panel index from
-* opregion if available due to issues with old platforms.
-* But this do not supports two panels and in SKL or newer I never saw a
-* system were this call returns a valid value.
-* So will change this to only use opregion up to BDW in a separated
-* commit.
-*/
- if (opregion_panel_index >= 0)
- panel_index = opregion_panel_index;
+ if (DISPLAY_VER(i915) < 9) {
+ int opregion_panel_index = intel_opregion_get_panel_type(i915);
+
+ if (opregion_panel_index >= 0)
+ opregion_panel_index = panel_index;
+ }
if (panel_index == -1)
return;
--
2.32.0
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Re: [Intel-gfx] [PATCH v2 3/6] drm/i915: Make shadow tables range-based
On Thu, 2021-07-29 at 08:21 -0700, Matt Roper wrote:
> Rather than defining our shadow tables as a list of individual
> registers, provide them as a list of register ranges; we'll have some
> ranges of multiple registers being added soon (and we already have a
> couple adjacent registers that we can squash into a single range
> now).
>
> This change also defines the table with hex literal values rather
> than
> symbolic register names; since that's how the tables are defined in
> the
> bspec, this change will make it easier to review the tables overall.
>
> v2:
> - Force signed comparison on range overlap sanity check
>
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 +-
> drivers/gpu/drm/i915/intel_uncore.c | 160 +---
> --
> drivers/gpu/drm/i915/intel_uncore.h | 6 +
> drivers/gpu/drm/i915/selftests/intel_uncore.c | 32 ++--
> 4 files changed, 108 insertions(+), 103 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 9173df59821a..7558414bafb2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1963,12 +1963,7 @@ void intel_engine_apply_workarounds(struct
> intel_engine_cs *engine)
> wa_list_apply(engine->gt, &engine->wa_list);
> }
>
> -struct mcr_range {
> - u32 start;
> - u32 end;
> -};
> -
> -static const struct mcr_range mcr_ranges_gen8[] = {
> +static const struct i915_range mcr_ranges_gen8[] = {
> { .start = 0x5500, .end = 0x55ff },
> { .start = 0x7000, .end = 0x7fff },
> { .start = 0x9400, .end = 0x97ff },
> @@ -1977,7 +1972,7 @@ static const struct mcr_range mcr_ranges_gen8[]
> = {
> {},
> };
>
> -static const struct mcr_range mcr_ranges_gen12[] = {
> +static const struct i915_range mcr_ranges_gen12[] = {
> { .start = 0x8150, .end = 0x815f },
> { .start = 0x9520, .end = 0x955f },
> { .start = 0xb100, .end = 0xb3ff },
> @@ -1986,7 +1981,7 @@ static const struct mcr_range
> mcr_ranges_gen12[] = {
> {},
> };
>
> -static const struct mcr_range mcr_ranges_xehp[] = {
> +static const struct i915_range mcr_ranges_xehp[] = {
> { .start = 0x4000, .end = 0x4aff },
> { .start = 0x5200, .end = 0x52ff },
> { .start = 0x5400, .end = 0x7fff },
> @@ -2004,7 +1999,7 @@ static const struct mcr_range mcr_ranges_xehp[]
> = {
>
> static bool mcr_range(struct drm_i915_private *i915, u32 offset)
> {
> - const struct mcr_range *mcr_ranges;
> + const struct i915_range *mcr_ranges;
> int i;
>
> if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index ea910f7ee635..2cfbc16f7dee 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -946,101 +946,95 @@ static const struct intel_forcewake_range
> __vlv_fw_ranges[] = {
> find_fw_domain(uncore, offset)
>
> /* *Must* be sorted by offset! See intel_shadow_table_check(). */
> -static const i915_reg_t gen8_shadowed_regs[] = {
> - RING_TAIL(RENDER_RING_BASE),/* 0x2000 (base) */
> - GEN6_RPNSWREQ, /* 0xA008 *
> - GEN6_RC_VIDEO_FREQ, /* 0xA00C */
> - RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */
> - RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */
> - RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
> +static const struct i915_range gen8_shadowed_regs[] = {
> + { .start = 0x2030, .end = 0x2030 },
> + { .start = 0xA008, .end = 0xA00C },
> + { .start = 0x12030, .end = 0x12030 },
> + { .start = 0x1a030, .end = 0x1a030 },
> + { .start = 0x22030, .end = 0x22030 },
You are replacing macro defined values by literal values. These macro
defined values are no longer used in this patch, but used in other
places such as intel_rps.c:gen6_rps_set(). What plan do you have about
the same address is defined in 2 ways, i.e. macro and literal value?
-caz
> /* TODO: Other registers are not yet used */
> };
>
> -static const i915_reg_t gen11_shadowed_regs[] = {
> - RING_TAIL(RENDER_RING_BASE),/* 0x2000
> (base) */
> - RING_EXECLIST_CONTROL(RENDER_RING_BASE),/* 0x2550 */
> - GEN6_RPNSWREQ, /* 0xA008 */
> - GEN6_RC_VIDEO_FREQ, /* 0xA00C */
> - RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
> - RING_EXECLIST_CONTROL(BLT_RING_BASE), /* 0x22550 */
> - RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C
> (base) */
> - RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE), /* 0x1C0550
> */
> - RING_TAIL(GEN11_BSD2_RING_BASE),/* 0x1C4000 (base) */
> - RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE),/* 0x1C4550
> */
> - RING_TAIL(GEN11_VEBOX_RIN
Re: [Intel-gfx] [PATCH 25/25] drm/i915: finish removal of CNL
On Wed, 2021-07-28 at 17:32 -0700, Lucas De Marchi wrote:
> On Wed, Jul 28, 2021 at 02:59:46PM -0700, Lucas De Marchi wrote:
> > With all the users removed, finish removing the CNL platform
> > definitions.
> > We will leave the PCI IDs around as those are exposed to userspace.
> > Even if mesa doesn't support CNL anymore, let's avoid build
> > breakages
> > due to changing the headers.
> >
> > Also, due to drm/i915/gt still using IS_CANNONLAKE() let's just
> > redefine
> > it instead of removing.
>
> +Rodrigo
>
> Rodrigo, when I was going to merge this patch I noticed it was not
> really possible. IS_CANNONLAKE() is used in drm/i915/gt/ so it can't
> be
> removed if part of the patches are merged in one branch and the other
> part in another.
>
> I also checked if it would be possible to do this by using a topic
> branch, but that
> gives conflicts when trying to use the merge base. So, I re-submitted
> the series split in 2: one for drm-intel-next and another for
> drm-intel-gt-next. Here instead of removing IS_CANNONLAKE() I only
> redefine it to 0. I'm keeping your previous r-b below, but please
> let
> me know if all above is fine and your r-b still stands.
oh, I had missed this but I saw that and acked already.
All rv-b are still valid!
>
> thanks
> Lucas De Marchi
>
>
> >
> > Signed-off-by: Lucas De Marchi
> > Reviewed-by: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 8 ++--
> > drivers/gpu/drm/i915/i915_pci.c | 23 +
> > --
> > drivers/gpu/drm/i915/i915_perf.c | 1 -
> > drivers/gpu/drm/i915/intel_device_info.c | 2 --
> > drivers/gpu/drm/i915/intel_device_info.h | 2 --
> > 5 files changed, 7 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 5d5cf5ad0513..6ac90ccbee0b 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1380,7 +1380,7 @@ IS_SUBPLATFORM(const struct drm_i915_private
> > *i915,
> > #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv,
> > INTEL_GEMINILAKE)
> > #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv,
> > INTEL_COFFEELAKE)
> > #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv,
> > INTEL_COMETLAKE)
> > -#define IS_CANNONLAKE(dev_priv)IS_PLATFORM(dev_priv,
> > INTEL_CANNONLAKE)
> > +#define IS_CANNONLAKE(dev_priv)0
> > #define IS_ICELAKE(dev_priv)IS_PLATFORM(dev_priv,
> > INTEL_ICELAKE)
> > #define IS_JSL_EHL(dev_priv)(IS_PLATFORM(dev_priv,
> > INTEL_JASPERLAKE) || \
> > IS_PLATFORM(dev_priv,
> > INTEL_ELKHARTLAKE))
> > @@ -1446,8 +1446,6 @@ IS_SUBPLATFORM(const struct drm_i915_private
> > *i915,
> > #define IS_CML_GT2(dev_priv)(IS_COMETLAKE(dev_priv) && \
> > INTEL_INFO(dev_priv)->gt == 2)
> >
> > -#define IS_CNL_WITH_PORT_F(dev_priv) \
> > - IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE,
> > INTEL_SUBPLATFORM_PORTF)
> > #define IS_ICL_WITH_PORT_F(dev_priv) \
> > IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE,
> > INTEL_SUBPLATFORM_PORTF)
> >
> > @@ -1592,9 +1590,7 @@ IS_SUBPLATFORM(const struct drm_i915_private
> > *i915,
> >
> > /* WaRsDisableCoarsePowerGating:skl,cnl */
> > #define
> > NEEDS_WaRsDisableCoarsePowerGating(dev_priv)\
> > - (IS_CANNONLAKE(dev_priv)
> > || \
> > - IS_SKL_GT3(dev_priv)
> > ||\
> > - IS_SKL_GT4(dev_priv))
> > + (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
> >
> > #define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
> > #define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >=
> > 11 || \
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index ec80cd1cd00c..cb4a46174513 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -787,27 +787,13 @@ static const struct intel_device_info
> > cml_gt2_info = {
> > .gt = 2,
> > };
> >
> > -#define GEN10_FEATURES \
> > - GEN9_FEATURES, \
> > - GEN(10), \
> > - .dbuf.size = 1024 - 4, /* 4 blocks for bypass path
> > allocation */ \
> > - .display.has_dsc = 1, \
> > - .has_coherent_ggtt = false, \
> > - GLK_COLORS
> > -
> > -static const struct intel_device_info cnl_info = {
> > - GEN10_FEATURES,
> > - PLATFORM(INTEL_CANNONLAKE),
> > - .gt = 2,
> > -};
> > -
> > #define GEN11_DEFAULT_PAGE_SIZES \
> > .page_sizes = I915_GTT_PAGE_SIZE_4K | \
> > I915_GTT_PAGE_SIZE_64K | \
> > I915_GTT_PAGE_SIZE_2M
> >
> > #define GEN11_FEATURES \
> > - GEN10_FEATURES, \
> > + GEN9_FEATURES, \
> > GEN11_DEFAULT_PAGE_SIZES, \
> > .abox_mask = BIT(0), \
> > .cpu_transcoder_mask = BIT(TRANSCODER_A) |
> > BIT(TRANSCODER_B) | \
> > @@ -830,10 +816,12 @@ static c
