[Intel-gfx] [PATCH 01/10] drm/i915: Note the addition of timeslicing to the pretend scheduler
Since writing the comment that the scheduler is entirely passive, we've
added minimal timeslicing which adds the most primitive of active
elements (a timeout and reschedule).
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Ramalingam C
---
drivers/gpu/drm/i915/i915_scheduler_types.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h
b/drivers/gpu/drm/i915/i915_scheduler_types.h
index aad81acba9dc..d18e70550054 100644
--- a/drivers/gpu/drm/i915/i915_scheduler_types.h
+++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
@@ -49,6 +49,15 @@ struct i915_sched_attr {
* DAG of each request, we are able to insert it into a sorted queue when it
* is ready, and are able to reorder its portion of the graph to accommodate
* dynamic priority changes.
+ *
+ * Ok, there is now one active element to the "scheduler" in the backends.
+ * We let a new context run for a small amount of time before re-evaluating
+ * the run order. As we re-evaluate, we maintain the strict ordering of
+ * dependencies, but attempt to rotate the active contexts (the current context
+ * is put to the back of its priority queue, then reshuffling its dependents).
+ * This provides minimal timeslicing and prevents a userspace hog (e.g.
+ * something waiting on a user semaphore [VkEvent]) from denying service to
+ * others.
*/
struct i915_sched_node {
struct list_head signalers_list; /* those before us, we depend upon */
--
2.23.0
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[Intel-gfx] [PATCH 05/10] drm/i915: Mark up "sentinel" requests
Sometimes we want to emit a terminator request, a request that flushes
the pipeline and allows no request to come after it. This can be used
for a "preempt-to-idle" to ensure that upon processing the
context-switch to that request, all other active contexts have been
flushed.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 ++
drivers/gpu/drm/i915/i915_request.h | 10 --
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index aa52e5f34dab..eb99f1e804f7 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1253,6 +1253,9 @@ static bool can_merge_rq(const struct i915_request *prev,
if (i915_request_completed(next))
return true;
+ if (i915_request_has_sentinel(prev))
+ return false;
+
if (!can_merge_ctx(prev->hw_context, next->hw_context))
return false;
@@ -1724,6 +1727,9 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
if (last->hw_context == rq->hw_context)
goto done;
+ if (i915_request_has_sentinel(last))
+ goto done;
+
/*
* If GVT overrides us we only ever submit
* port[0], leaving port[1] empty. Note that we
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index 6a95242b280d..96991d64759c 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -216,8 +216,9 @@ struct i915_request {
unsigned long emitted_jiffies;
unsigned long flags;
-#define I915_REQUEST_WAITBOOST BIT(0)
-#define I915_REQUEST_NOPREEMPT BIT(1)
+#define I915_REQUEST_WAITBOOST BIT(0)
+#define I915_REQUEST_NOPREEMPT BIT(1)
+#define I915_REQUEST_SENTINEL BIT(2)
/** timeline->request entry for this request */
struct list_head link;
@@ -440,6 +441,11 @@ static inline bool i915_request_has_nopreempt(const struct
i915_request *rq)
return unlikely(rq->flags & I915_REQUEST_NOPREEMPT);
}
+static inline bool i915_request_has_sentinel(const struct i915_request *rq)
+{
+ return unlikely(rq->flags & I915_REQUEST_SENTINEL);
+}
+
static inline struct intel_timeline *
i915_request_timeline(struct i915_request *rq)
{
--
2.23.0
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[Intel-gfx] [PATCH 06/10] drm/i915/gt: Introduce barrier pulses along engines
To flush idle barriers, and even inflight requests, we want to send a
preemptive 'pulse' along an engine. We use a no-op request along the
pinned kernel_context at high priority so that it should run or else
kick off the stuck requests. We can use this to ensure idle barriers are
immediately flushed, as part of a context cancellation mechanism, or as
part of a heartbeat mechanism to detect and reset a stuck GPU.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 56 +++
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 14 +
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
drivers/gpu/drm/i915/i915_priolist_types.h| 1 +
5 files changed, 73 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index cd9a10ba2516..cfab7c8585b3 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -78,6 +78,7 @@ gt-y += \
gt/intel_breadcrumbs.o \
gt/intel_context.o \
gt/intel_engine_cs.o \
+ gt/intel_engine_heartbeat.o \
gt/intel_engine_pm.o \
gt/intel_engine_pool.o \
gt/intel_engine_sysfs.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
new file mode 100644
index ..2fc413f9d506
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -0,0 +1,56 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_request.h"
+
+#include "intel_context.h"
+#include "intel_engine_heartbeat.h"
+#include "intel_engine_pm.h"
+#include "intel_engine.h"
+#include "intel_gt.h"
+
+static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq)
+{
+ engine->wakeref_serial = READ_ONCE(engine->serial) + 1;
+ i915_request_add_active_barriers(rq);
+}
+
+int intel_engine_pulse(struct intel_engine_cs *engine)
+{
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_BARRIER };
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_request *rq;
+ int err = 0;
+
+ if (!intel_engine_has_preemption(engine))
+ return -ENODEV;
+
+ if (!intel_engine_pm_get_if_awake(engine))
+ return 0;
+
+ if (mutex_lock_interruptible(&ce->timeline->mutex))
+ goto out_rpm;
+
+ intel_context_enter(ce);
+ rq = __i915_request_create(ce, GFP_NOWAIT | __GFP_NOWARN);
+ intel_context_exit(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unlock;
+ }
+
+ rq->flags |= I915_REQUEST_SENTINEL;
+ idle_pulse(engine, rq);
+
+ __i915_request_commit(rq);
+ __i915_request_queue(rq, &attr);
+
+out_unlock:
+ mutex_unlock(&ce->timeline->mutex);
+out_rpm:
+ intel_engine_pm_put(engine);
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
new file mode 100644
index ..b950451b5998
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
@@ -0,0 +1,14 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef INTEL_ENGINE_HEARTBEAT_H
+#define INTEL_ENGINE_HEARTBEAT_H
+
+struct intel_engine_cs;
+
+int intel_engine_pulse(struct intel_engine_cs *engine);
+
+#endif /* INTEL_ENGINE_HEARTBEAT_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 67eb6183648a..7d76611d9df1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -111,7 +111,7 @@ static bool switch_to_kernel_context(struct intel_engine_cs
*engine)
i915_request_add_active_barriers(rq);
/* Install ourselves as a preemption barrier */
- rq->sched.attr.priority = I915_PRIORITY_UNPREEMPTABLE;
+ rq->sched.attr.priority = I915_PRIORITY_BARRIER;
__i915_request_commit(rq);
/* Release our exclusive hold on the engine */
diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h
b/drivers/gpu/drm/i915/i915_priolist_types.h
index 21037a2e2038..ae8bb3cb627e 100644
--- a/drivers/gpu/drm/i915/i915_priolist_types.h
+++ b/drivers/gpu/drm/i915/i915_priolist_types.h
@@ -39,6 +39,7 @@ enum {
* active request.
*/
#define I915_PRIORITY_UNPREEMPTABLE INT_MAX
+#define I915_PRIORITY_BARRIER INT_MAX
#define __NO_PREEMPTION (I915_PRIORITY_WAIT)
--
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[Intel-gfx] [PATCH 09/10] drm/i915: Replace hangcheck by heartbeats
Replace sampling the engine state every so often with a periodic
heartbeat request to measure the health of an engine. This is coupled
with the forced-preemption to allow long running requests to survive so
long as they do not block other users.
The heartbeat interval can be adjusted per-engine using,
/sys/class/drm/card?/engine/*/heartbeat_interval_ms
v2: Couple in sysfs controls
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Jon Bloomfield
Reviewed-by: Jon Bloomfield
---
drivers/gpu/drm/i915/Kconfig.profile | 14 +
drivers/gpu/drm/i915/Makefile | 1 -
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_object.h| 1 -
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 2 -
drivers/gpu/drm/i915/gt/intel_engine.h| 32 --
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 +-
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 115 ++
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 5 +
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 5 +-
drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 29 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 17 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 1 -
drivers/gpu/drm/i915/gt/intel_gt.h| 4 -
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 1 -
drivers/gpu/drm/i915/gt/intel_gt_types.h | 9 -
drivers/gpu/drm/i915/gt/intel_hangcheck.c | 361 --
drivers/gpu/drm/i915/gt/intel_reset.c | 3 +-
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 4 -
drivers/gpu/drm/i915/i915_debugfs.c | 87 -
drivers/gpu/drm/i915/i915_drv.c | 3 -
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_gpu_error.c | 33 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 2 -
drivers/gpu/drm/i915/i915_priolist_types.h| 6 +
25 files changed, 194 insertions(+), 555 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/gt/intel_hangcheck.c
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index 8fceea85937b..d3950aabb497 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -40,3 +40,17 @@ config DRM_I915_PREEMPT_TIMEOUT
/sys/class/drm/card?/engine/*/preempt_timeout_ms
May be 0 to disable the timeout.
+
+config DRM_I915_HEARTBEAT_INTERVAL
+ int "Interval between heartbeat pulses (ms)"
+ default 2500 # milliseconds
+ help
+ While active the driver uses a periodic request, a heartbeat, to
+ check the wellness of the GPU and to regularly flush state changes
+ (idle barriers).
+
+ This is adjustable via
+ /sys/class/drm/card?/engine/*/heartbeat_interval_ms
+
+ May be 0 to disable heartbeats and therefore disable automatic GPU
+ hang detection.
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index cfab7c8585b3..59d356cc406c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -88,7 +88,6 @@ gt-y += \
gt/intel_gt_pm.o \
gt/intel_gt_pm_irq.o \
gt/intel_gt_requests.o \
- gt/intel_hangcheck.o \
gt/intel_lrc.o \
gt/intel_rc6.o \
gt/intel_renderstate.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 1a533ccdb54f..5e5de3081f48 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14338,7 +14338,7 @@ static void intel_plane_unpin_fb(struct
intel_plane_state *old_plane_state)
static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
{
struct i915_sched_attr attr = {
- .priority = I915_PRIORITY_DISPLAY,
+ .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
};
i915_gem_object_wait_priority(obj, 0, &attr);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index c5e14c9c805c..5bd51e397371 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -460,6 +460,5 @@ int i915_gem_object_wait(struct drm_i915_gem_object *obj,
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
unsigned int flags,
const struct i915_sched_attr *attr);
-#define I915_PRIORITY_DISPLAY I915_USER_PRIORITY(I915_PRIORITY_MAX)
#endif
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 7987b54fb1f5..0e97520cb1bb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -100,8 +100,6 @@ void i915_gem_suspend(struct drm_i915_private *i915)
intel_gt_suspend(&i915->gt);
intel_uc_suspend(&i915->gt.uc);
- cancel_delay
[Intel-gfx] [PATCH 07/10] drm/i915/execlists: Cancel banned contexts on schedule-out
On completion of a banned context, scrub the context image so that we do
not replay the active payload. The intent is that we skip banned
payloads on request submission so that the timeline advancement
continues on in the background. However, if we are returning to a
preempted request, i915_request_skip() is ineffective and instead we
need to patch up the context image so that it continues from the start
of the next request.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c| 58 ++
drivers/gpu/drm/i915/gt/selftest_lrc.c | 273 +
2 files changed, 331 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index eb99f1e804f7..79c7ebea2fcc 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -234,6 +234,9 @@ static void execlists_init_reg_state(u32 *reg_state,
const struct intel_engine_cs *engine,
const struct intel_ring *ring,
bool close);
+static void
+__execlists_update_reg_state(const struct intel_context *ce,
+const struct intel_engine_cs *engine);
static void __context_pin_acquire(struct intel_context *ce)
{
@@ -1022,6 +1025,58 @@ static void kick_siblings(struct i915_request *rq,
struct intel_context *ce)
tasklet_schedule(&ve->base.execlists.tasklet);
}
+static void
+mark_complete(struct i915_request *rq, struct intel_engine_cs *engine)
+{
+ const struct intel_timeline * const tl = rcu_dereference(rq->timeline);
+
+ *(u32 *)tl->hwsp_seqno = rq->fence.seqno;
+ GEM_BUG_ON(!i915_request_completed(rq));
+
+ list_for_each_entry_from_reverse(rq, &tl->requests, link) {
+ if (i915_request_signaled(rq))
+ break;
+
+ mark_eio(rq);
+ }
+
+ intel_engine_queue_breadcrumbs(engine);
+}
+
+static void cancel_active(struct i915_request *rq,
+ struct intel_engine_cs *engine)
+{
+ struct intel_context * const ce = rq->hw_context;
+ u32 *regs = ce->lrc_reg_state;
+
+ if (i915_request_completed(rq))
+ return;
+
+ GEM_TRACE("%s(%s): { rq=%llx:%lld }\n",
+ __func__, engine->name, rq->fence.context, rq->fence.seqno);
+ __context_pin_acquire(ce);
+
+ /* Scrub the context image to prevent replaying the previous batch */
+ memcpy(regs, /* skip restoring the vanilla PPHWSP */
+ engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
+ engine->context_size - PAGE_SIZE);
+ execlists_init_reg_state(regs, ce, engine, ce->ring, false);
+
+ /* Ring will be advanced on retire; here we need to reset the context */
+ ce->ring->head = intel_ring_wrap(ce->ring, rq->wa_tail);
+ __execlists_update_reg_state(ce, engine);
+
+ /* We've switched away, so this should be a no-op, but intent matters */
+ ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
+
+ /* Let everyone know that the request may now be retired */
+ rcu_read_lock();
+ mark_complete(rq, engine);
+ rcu_read_unlock();
+
+ __context_pin_release(ce);
+}
+
static inline void
__execlists_schedule_out(struct i915_request *rq,
struct intel_engine_cs * const engine)
@@ -1032,6 +1087,9 @@ __execlists_schedule_out(struct i915_request *rq,
execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
intel_gt_pm_put(engine->gt);
+ if (unlikely(i915_gem_context_is_banned(ce->gem_context)))
+ cancel_active(rq, engine);
+
/*
* If this is part of a virtual engine, its next request may
* have been blocked waiting for access to the active context.
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 198cf2f754f4..1703130ef0ef 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -7,6 +7,7 @@
#include
#include "gem/i915_gem_pm.h"
+#include "gt/intel_engine_heartbeat.h"
#include "gt/intel_reset.h"
#include "i915_selftest.h"
@@ -986,6 +987,277 @@ static int live_nopreempt(void *arg)
goto err_client_b;
}
+struct live_preempt_cancel {
+ struct intel_engine_cs *engine;
+ struct preempt_client a, b;
+};
+
+static int __cancel_active0(struct live_preempt_cancel *arg)
+{
+ struct i915_request *rq;
+ struct igt_live_test t;
+ int err;
+
+ /* Preempt cancel of ELSP0 */
+ GEM_TRACE("%s(%s)\n", __func__, arg->engine->name);
+
+ if (igt_live_test_begin(&t, arg->engine->i915,
+ __func__, arg->engine->name))
+ return -EIO;
+
+ clear_bit(CONTEXT_BANNED, &arg->a.ctx->flags);
+ rq = spinner_create_request(&arg->a.spin,
+
[Intel-gfx] [PATCH 04/10] drm/i915/execlists: Force preemption
If the preempted context takes too long to relinquish control, e.g. it
is stuck inside a shader with arbitration disabled, evict that context
with an engine reset. This ensures that preemptions are reasonably
responsive, providing a tighter QoS for the more important context at
the cost of flagging unresponsive contexts more frequently (i.e. instead
of using an ~10s hangcheck, we now evict at ~100ms). The challenge of
lies in picking a timeout that can be reasonably serviced by HW for
typical workloads, balancing the existing clients against the needs for
responsiveness.
Note that coupled with timeslicing, this will lead to rapid GPU "hang"
detection with multiple active contexts vying for GPU time.
The preempt timeout can be adjusted per-engine using,
/sys/class/drm/card?/engine/*/preempt_timeout_ms
v2: Couple in sysfs control of preemption timeout
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/Kconfig.profile | 15
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 2 +
drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 32 +++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 95 ++--
drivers/gpu/drm/i915/i915_params.h | 2 +-
6 files changed, 146 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index 48df8889a88a..8fceea85937b 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -25,3 +25,18 @@ config DRM_I915_SPIN_REQUEST
May be 0 to disable the initial spin. In practice, we estimate
the cost of enabling the interrupt (if currently disabled) to be
a few microseconds.
+
+config DRM_I915_PREEMPT_TIMEOUT
+ int "Preempt timeout (ms)"
+ default 100 # milliseconds
+ help
+ How long to wait (in milliseconds) for a preemption event to occur
+ when submitting a new context via execlists. If the current context
+ does not hit an arbitration point and yield to HW before the timer
+ expires, the HW will be reset to allow the more important context
+ to execute.
+
+ This is adjustable via
+ /sys/class/drm/card?/engine/*/preempt_timeout_ms
+
+ May be 0 to disable the timeout.
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index c9d639c6becb..1eb51147839a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -304,6 +304,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
engine->instance = info->instance;
__sprint_engine_name(engine);
+ engine->props.preempt_timeout = CONFIG_DRM_I915_PREEMPT_TIMEOUT;
+
/*
* To be overridden by the backend on setup. However to facilitate
* cleanup on error during setup, we always provide the destroy vfunc.
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
index cbe9ec59beeb..aac26097c916 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
@@ -45,10 +45,37 @@ mmio_show(struct kobject *kobj, struct kobj_attribute
*attr, char *buf)
return sprintf(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base);
}
+static ssize_t
+preempt_timeout_show(struct kobject *kobj, struct kobj_attribute *attr,
+char *buf)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+
+ return sprintf(buf, "%lu\n", engine->props.preempt_timeout);
+}
+
+static ssize_t
+preempt_timeout_store(struct kobject *kobj, struct kobj_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+ unsigned long timeout;
+ int err;
+
+ err = kstrtoul(buf, 0, &timeout);
+ if (err)
+ return err;
+
+ engine->props.preempt_timeout = timeout;
+ return count;
+}
+
static struct kobj_attribute name_attr = __ATTR(name, 0444, name_show, NULL);
static struct kobj_attribute class_attr = __ATTR(class, 0444, class_show,
NULL);
static struct kobj_attribute inst_attr = __ATTR(instance, 0444, inst_show,
NULL);
static struct kobj_attribute mmio_attr = __ATTR(mmio_base, 0444, mmio_show,
NULL);
+static struct kobj_attribute preempt_timeout_attr =
+__ATTR(preempt_timeout_ms, 0600, preempt_timeout_show, preempt_timeout_store);
static void kobj_engine_release(struct kobject *kobj)
{
@@ -109,6 +136,11 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915)
if (sysfs_create_files(kobj, files))
goto err_engine;
+ if (CONFIG_DRM_I915_PREEMPT_TIMEOUT &&
+ intel_engine_has_preemption(engine) &&
+
[Intel-gfx] [PATCH 08/10] drm/i915: Cancel non-persistent contexts on close
Normally, we rely on our hangcheck to prevent persistent batches from
hogging the GPU. However, if the user disables hangcheck, this mechanism
breaks down. Despite our insistence that this is unsafe, the users are
equally insistent that they want to use endless batches and will disable
the hangcheck mechanism. We are looking at perhaps replacing hangcheck
with a softer mechanism, that sends a pulse down the engine to check if
it is well. We can use the same preemptive pulse to flush an active
persistent context off the GPU upon context close, preventing resources
being lost and unkillable requests remaining on the GPU after process
termination. To avoid changing the ABI and accidentally breaking
existing userspace, we make the persistence of a context explicit and
enable it by default (matching current ABI). Userspace can opt out of
persistent mode (forcing requests to be cancelled when the context is
closed by process termination or explicitly) by a context parameter. To
facilitate existing use-cases of disabling hangcheck, if the modparam is
disabled (i915.enable_hangcheck=0), we disable persistence mode by
default. (Note, one of the outcomes for supporting endless mode will be
the removal of hangchecking, at which point opting into persistent mode
will be mandatory, or maybe the default perhaps controlled by cgroups.)
v2: Check for hangchecking at context termination, so that we are not
left with undying contexts from a crafty user.
Testcase: igt/gem_ctx_persistence
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michał Winiarski
Cc: Jon Bloomfield
Reviewed-by: Jon Bloomfield
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 132 ++
drivers/gpu/drm/i915/gem/i915_gem_context.h | 15 ++
.../gpu/drm/i915/gem/i915_gem_context_types.h | 1 +
.../gpu/drm/i915/gem/selftests/mock_context.c | 2 +
include/uapi/drm/i915_drm.h | 15 ++
5 files changed, 165 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 5d8221c7ba83..46e5b3b53288 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -70,6 +70,7 @@
#include
#include "gt/intel_lrc_reg.h"
+#include "gt/intel_engine_heartbeat.h"
#include "gt/intel_engine_user.h"
#include "i915_gem_context.h"
@@ -269,6 +270,78 @@ void i915_gem_context_release(struct kref *ref)
schedule_work(&gc->free_work);
}
+static inline struct i915_gem_engines *
+__context_engines_static(struct i915_gem_context *ctx)
+{
+ return rcu_dereference_protected(ctx->engines, true);
+}
+
+static void kill_context(struct i915_gem_context *ctx)
+{
+ intel_engine_mask_t tmp, active, reset;
+ struct intel_gt *gt = &ctx->i915->gt;
+ struct i915_gem_engines_iter it;
+ struct intel_engine_cs *engine;
+ struct intel_context *ce;
+
+ /*
+* If we are already banned, it was due to a guilty request causing
+* a reset and the entire context being evicted from the GPU.
+*/
+ if (i915_gem_context_is_banned(ctx))
+ return;
+
+ i915_gem_context_set_banned(ctx);
+
+ /*
+* Map the user's engine back to the actual engines; one virtual
+* engine will be mapped to multiple engines, and using ctx->engine[]
+* the same engine may be have multiple instances in the user's map.
+* However, we only care about pending requests, so only include
+* engines on which there are incomplete requests.
+*/
+ active = 0;
+ for_each_gem_engine(ce, __context_engines_static(ctx), it) {
+ struct dma_fence *fence;
+
+ if (!ce->timeline)
+ continue;
+
+ fence = i915_active_fence_get(&ce->timeline->last_request);
+ if (!fence)
+ continue;
+
+ engine = to_request(fence)->engine;
+ if (HAS_EXECLISTS(gt->i915))
+ engine = intel_context_inflight(ce);
+ if (engine)
+ active |= engine->mask;
+
+ dma_fence_put(fence);
+ }
+
+ /*
+* Send a "high priority pulse" down the engine to cause the
+* current request to be momentarily preempted. (If it fails to
+* be preempted, it will be reset). As we have marked our context
+* as banned, any incomplete request, including any running, will
+* be skipped following the preemption.
+*/
+ reset = 0;
+ for_each_engine_masked(engine, gt->i915, active, tmp)
+ if (intel_engine_pulse(engine))
+ reset |= engine->mask;
+
+ /*
+* If we are unable to send a preemptive pulse to bump
+* the context from the GPU, we have to resort to a full
+* reset. We hope the collateral damage is worth it.
+*/
+ if (reset)
+
[Intel-gfx] [PATCH 03/10] drm/i915: Expose engine properties via sysfs
Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
that we can expose properties on each engine to the sysadmin.
To start with we have basic analogues of the i915_query ioctl so that we
can pretty print engine discovery from the shell, and flesh out the
directory structure. Later we will add writeable sysadmin properties such
as per-engine timeout controls.
An example tree of the engine properties on Braswell:
/sys/class/drm/card0
└── engine
├── bcs0
│ ├── class
│ ├── heartbeat_interval_ms
│ ├── instance
│ ├── mmio_base
│ └── name
├── rcs0
│ ├── class
│ ├── heartbeat_interval_ms
│ ├── instance
│ ├── mmio_base
│ └── name
├── vcs0
│ ├── class
│ ├── heartbeat_interval_ms
│ ├── instance
│ ├── mmio_base
│ └── name
└── vecs0
├── class
├── heartbeat_interval_ms
├── instance
├── mmio_base
└── name
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Acked-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 119 +++
drivers/gpu/drm/i915/gt/intel_engine_sysfs.h | 14 +++
drivers/gpu/drm/i915/i915_sysfs.c| 3 +
4 files changed, 138 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_sysfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e791d9323b51..cd9a10ba2516 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -78,8 +78,9 @@ gt-y += \
gt/intel_breadcrumbs.o \
gt/intel_context.o \
gt/intel_engine_cs.o \
- gt/intel_engine_pool.o \
gt/intel_engine_pm.o \
+ gt/intel_engine_pool.o \
+ gt/intel_engine_sysfs.o \
gt/intel_engine_user.o \
gt/intel_gt.o \
gt/intel_gt_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
new file mode 100644
index ..cbe9ec59beeb
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
@@ -0,0 +1,119 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include
+#include
+
+#include "i915_drv.h"
+#include "intel_engine.h"
+#include "intel_engine_sysfs.h"
+
+struct kobj_engine {
+ struct kobject base;
+ struct intel_engine_cs *engine;
+};
+
+static struct intel_engine_cs *kobj_to_engine(struct kobject *kobj)
+{
+ return container_of(kobj, struct kobj_engine, base)->engine;
+}
+
+static ssize_t
+name_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%s\n", kobj_to_engine(kobj)->name);
+}
+
+static ssize_t
+class_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", kobj_to_engine(kobj)->uabi_class);
+}
+
+static ssize_t
+inst_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", kobj_to_engine(kobj)->uabi_instance);
+}
+
+static ssize_t
+mmio_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ return sprintf(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base);
+}
+
+static struct kobj_attribute name_attr = __ATTR(name, 0444, name_show, NULL);
+static struct kobj_attribute class_attr = __ATTR(class, 0444, class_show,
NULL);
+static struct kobj_attribute inst_attr = __ATTR(instance, 0444, inst_show,
NULL);
+static struct kobj_attribute mmio_attr = __ATTR(mmio_base, 0444, mmio_show,
NULL);
+
+static void kobj_engine_release(struct kobject *kobj)
+{
+ kfree(kobj);
+}
+
+static struct kobj_type kobj_engine_type = {
+ .release = kobj_engine_release,
+ .sysfs_ops = &kobj_sysfs_ops
+};
+
+static struct kobject *
+kobj_engine(struct kobject *dir, struct intel_engine_cs *engine)
+{
+ struct kobj_engine *ke;
+
+ ke = kzalloc(sizeof(*ke), GFP_KERNEL);
+ if (!ke)
+ return NULL;
+
+ kobject_init(&ke->base, &kobj_engine_type);
+ ke->engine = engine;
+
+ if (kobject_add(&ke->base, dir, "%s", engine->name)) {
+ kobject_put(&ke->base);
+ return NULL;
+ }
+
+ /* xfer ownership to sysfs tree */
+ return &ke->base;
+}
+
+void intel_engines_add_sysfs(struct drm_i915_private *i915)
+{
+ static const struct attribute *files[] = {
+ &name_attr.attr,
+ &class_attr.attr,
+ &inst_attr.attr,
+ &mmio_attr.attr,
+ NULL
+ };
+
+ struct device *kdev = i915->drm.primary->kdev;
+ struct intel_engine_cs *engine;
+ struct kobject *dir;
+
+ d
[Intel-gfx] [PATCH 02/10] drm/i915/execlists: Leave tell-tales as to why pending[] is bad
Before we BUG out with bad pending state, leave a telltale as to which
test failed.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 30 -
drivers/gpu/drm/i915/i915_gem.h | 8
2 files changed, 29 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a0777b3ad68a..5040fbdd81af 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1138,25 +1138,45 @@ assert_pending_valid(const struct
intel_engine_execlists *execlists,
trace_ports(execlists, msg, execlists->pending);
- if (!execlists->pending[0])
+ if (!execlists->pending[0]) {
+ GEM_TRACE_ERR("Nothing pending for promotion!\n");
return false;
+ }
- if (execlists->pending[execlists_num_ports(execlists)])
+ if (execlists->pending[execlists_num_ports(execlists)]) {
+ GEM_TRACE_ERR("Excess pending[%d] for promotion!\n",
+ execlists_num_ports(execlists));
return false;
+ }
for (port = execlists->pending; (rq = *port); port++) {
- if (ce == rq->hw_context)
+ if (ce == rq->hw_context) {
+ GEM_TRACE_ERR("Duplicate context in pending[%zd]\n",
+ port - execlists->pending);
return false;
+ }
ce = rq->hw_context;
if (i915_request_completed(rq))
continue;
- if (i915_active_is_idle(&ce->active))
+ if (i915_active_is_idle(&ce->active)) {
+ GEM_TRACE_ERR("Inactive context in pending[%zd]\n",
+ port - execlists->pending);
+ return false;
+ }
+
+ if (!i915_vma_is_pinned(ce->state)) {
+ GEM_TRACE_ERR("Unpinned context in pending[%zd]\n",
+ port - execlists->pending);
return false;
+ }
- if (!i915_vma_is_pinned(ce->state))
+ if (!i915_vma_is_pinned(ce->ring->vma)) {
+ GEM_TRACE_ERR("Unpinned ringbuffer in pending[%zd]\n",
+ port - execlists->pending);
return false;
+ }
}
return ce;
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index 6795f1daa3d5..63dab3765106 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -37,10 +37,8 @@ struct drm_i915_private;
#define GEM_SHOW_DEBUG() (drm_debug & DRM_UT_DRIVER)
#define GEM_BUG_ON(condition) do { if (unlikely((condition))) {\
- pr_err("%s:%d GEM_BUG_ON(%s)\n", \
- __func__, __LINE__, __stringify(condition)); \
- GEM_TRACE("%s:%d GEM_BUG_ON(%s)\n", \
- __func__, __LINE__, __stringify(condition)); \
+ GEM_TRACE_ERR("%s:%d GEM_BUG_ON(%s)\n", \
+ __func__, __LINE__, __stringify(condition)); \
BUG(); \
} \
} while(0)
@@ -66,11 +64,13 @@ struct drm_i915_private;
#if IS_ENABLED(CONFIG_DRM_I915_TRACE_GEM)
#define GEM_TRACE(...) trace_printk(__VA_ARGS__)
+#define GEM_TRACE_ERR(...) do { pr_err(__VA_ARGS__);
trace_printk(__VA_ARGS__); } while (0)
#define GEM_TRACE_DUMP() ftrace_dump(DUMP_ALL)
#define GEM_TRACE_DUMP_ON(expr) \
do { if (expr) ftrace_dump(DUMP_ALL); } while (0)
#else
#define GEM_TRACE(...) do { } while (0)
+#define GEM_TRACE_ERR(...) do { } while (0)
#define GEM_TRACE_DUMP() do { } while (0)
#define GEM_TRACE_DUMP_ON(expr) BUILD_BUG_ON_INVALID(expr)
#endif
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/10] drm/i915: Flush idle barriers when waiting
If we do find ourselves with an idle barrier inside our active while
waiting, attempt to flush it by emitting a pulse using the kernel
context.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 14 +
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 1 +
drivers/gpu/drm/i915/i915_active.c| 21 +--
3 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index f68acf9118f3..e27bb7f028bd 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -169,3 +169,17 @@ int intel_engine_pulse(struct intel_engine_cs *engine)
intel_engine_pm_put(engine);
return err;
}
+
+int intel_engine_flush_barriers(struct intel_engine_cs *engine)
+{
+ struct i915_request *rq;
+
+ rq = i915_request_create(engine->kernel_context);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ idle_pulse(engine, rq);
+ i915_request_add(rq);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
index 39391004554d..0c1ad0fc091d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
@@ -15,5 +15,6 @@ void intel_engine_park_heartbeat(struct intel_engine_cs
*engine);
void intel_engine_unpark_heartbeat(struct intel_engine_cs *engine);
int intel_engine_pulse(struct intel_engine_cs *engine);
+int intel_engine_flush_barriers(struct intel_engine_cs *engine);
#endif /* INTEL_ENGINE_HEARTBEAT_H */
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
index aa37c07004b9..98d5fe1c7e19 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -6,6 +6,7 @@
#include
+#include "gt/intel_engine_heartbeat.h"
#include "gt/intel_engine_pm.h"
#include "i915_drv.h"
@@ -435,6 +436,21 @@ static void enable_signaling(struct i915_active_fence
*active)
dma_fence_put(fence);
}
+static int flush_barrier(struct active_node *it)
+{
+ struct intel_engine_cs *engine;
+
+ if (!is_barrier(&it->base))
+ return 0;
+
+ engine = __barrier_to_engine(it);
+ smp_rmb(); /* serialise with add_active_barriers */
+ if (!is_barrier(&it->base))
+ return 0;
+
+ return intel_engine_flush_barriers(engine);
+}
+
int i915_active_wait(struct i915_active *ref)
{
struct active_node *it, *n;
@@ -448,8 +464,9 @@ int i915_active_wait(struct i915_active *ref)
/* Flush lazy signals */
enable_signaling(&ref->excl);
rbtree_postorder_for_each_entry_safe(it, n, &ref->tree, node) {
- if (is_barrier(&it->base)) /* unconnected idle barrier */
- continue;
+ err = flush_barrier(it); /* unconnected idle barrier? */
+ if (err)
+ break;
enable_signaling(&it->base);
}
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/perf: store the associated engine of a stream
From: Lionel Landwerlin
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine. For now, we want to
pull the knowledge of which engine we use into a central property.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 30 ++
drivers/gpu/drm/i915/i915_perf_types.h | 5 +
2 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 5a34cad7d824..1a5c6591b9bb 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -197,6 +197,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_pm.h"
+#include "gt/intel_engine_user.h"
#include "gt/intel_lrc_reg.h"
#include "i915_drv.h"
@@ -347,6 +348,7 @@ static const struct i915_oa_format
gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
* @oa_format: An OA unit HW report format
* @oa_periodic: Whether to enable periodic OA unit sampling
* @oa_period_exponent: The OA unit sampling period is derived from this
+ * @engine: The engine (typically rcs0) being monitored by the OA unit
*
* As read_properties_unlocked() enumerates and validates the properties given
* to open a stream of metrics the configuration is built up in the structure
@@ -363,6 +365,8 @@ struct perf_open_properties {
int oa_format;
bool oa_periodic;
int oa_period_exponent;
+
+ struct intel_engine_cs *engine;
};
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
@@ -1205,7 +1209,7 @@ static struct intel_context *oa_pin_context(struct
i915_perf_stream *stream)
int err;
for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
- if (ce->engine->class != RENDER_CLASS)
+ if (ce->engine != stream->engine) /* first match! */
continue;
/*
@@ -2127,7 +2131,13 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
int format_size;
int ret;
- /* If the sysfs metrics/ directory wasn't registered for some
+ if (!props->engine) {
+ DRM_DEBUG("OA engine not specified\n");
+ return -EINVAL;
+ }
+
+ /*
+* If the sysfs metrics/ directory wasn't registered for some
* reason then don't let userspace try their luck with config
* IDs
*/
@@ -2146,7 +2156,8 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
return -ENODEV;
}
- /* To avoid the complexity of having to accurately filter
+ /*
+* To avoid the complexity of having to accurately filter
* counter reports and marshal to the appropriate client
* we currently only allow exclusive access
*/
@@ -2160,6 +2171,9 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
return -EINVAL;
}
+ stream->engine = props->engine;
+ stream->gt = stream->engine->gt;
+
stream->sample_size = sizeof(struct drm_i915_perf_record_header);
format_size = perf->oa_formats[props->oa_format].size;
@@ -2711,7 +2725,6 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
}
stream->perf = perf;
- stream->gt = &perf->i915->gt;
stream->ctx = specific_ctx;
ret = i915_oa_stream_init(stream, param, props);
@@ -2796,6 +2809,15 @@ static int read_properties_unlocked(struct i915_perf
*perf,
return -EINVAL;
}
+ /* At the moment we only support using i915-perf on the RCS. */
+ props->engine = intel_engine_lookup_user(perf->i915,
+I915_ENGINE_CLASS_RENDER,
+0);
+ if (!props->engine) {
+ DRM_DEBUG("No RENDER-capable engines\n");
+ return -EINVAL;
+ }
+
/* Considering that ID = 0 is reserved and assuming that we don't
* (currently) expect any configurations to ever specify duplicate
* values for a particular property ID then the last _PROP_MAX value is
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h
b/drivers/gpu/drm/i915/i915_perf_types.h
index 2d17059d32ee..82cd3b295037 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -140,6 +140,11 @@ struct i915_perf_stream {
*/
intel_wakeref_t wakeref;
+ /**
+* @engine: Engine associated with this performance stream.
+*/
+ struct intel_engine_cs *engine;
+
/**
* @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
* properties given when opening a stream, representing the contents
--
2.23.0
___
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[Intel-gfx] [PATCH 2/2] drm/i915/perf: Store shortcut to intel_uncore
Now that we have the engine stored in i915_perf, we have a means of
accessing intel_gt should we require it. However, we are currently only
using the intel_gt to find the right intel_uncore, so replace our
i915_perf.gt pointer with the more useful i915_perf.uncore.
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 48 +-
drivers/gpu/drm/i915/i915_perf_types.h | 4 +--
2 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 1a5c6591b9bb..77c3cef64548 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -419,14 +419,14 @@ static int get_oa_config(struct i915_perf *perf,
static u32 gen8_oa_hw_tail_read(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
return intel_uncore_read(uncore, GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK;
}
static u32 gen7_oa_hw_tail_read(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
u32 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
return oastatus1 & GEN7_OASTATUS1_TAIL_MASK;
@@ -656,7 +656,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
size_t count,
size_t *offset)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
int report_size = stream->oa_buffer.format_size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
@@ -866,7 +866,7 @@ static int gen8_oa_read(struct i915_perf_stream *stream,
size_t count,
size_t *offset)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
u32 oastatus;
int ret;
@@ -945,7 +945,7 @@ static int gen7_append_oa_reports(struct i915_perf_stream
*stream,
size_t count,
size_t *offset)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
int report_size = stream->oa_buffer.format_size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
@@ -1077,7 +1077,7 @@ static int gen7_oa_read(struct i915_perf_stream *stream,
size_t count,
size_t *offset)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
u32 oastatus1;
int ret;
@@ -1352,8 +1352,8 @@ static void i915_oa_stream_destroy(struct
i915_perf_stream *stream)
free_oa_buffer(stream);
- intel_uncore_forcewake_put(stream->gt->uncore, FORCEWAKE_ALL);
- intel_runtime_pm_put(stream->gt->uncore->rpm, stream->wakeref);
+ intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
+ intel_runtime_pm_put(stream->uncore->rpm, stream->wakeref);
if (stream->ctx)
oa_put_render_ctx_id(stream);
@@ -1368,7 +1368,7 @@ static void i915_oa_stream_destroy(struct
i915_perf_stream *stream)
static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
unsigned long flags;
@@ -1416,7 +1416,7 @@ static void gen7_init_oa_buffer(struct i915_perf_stream
*stream)
static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
unsigned long flags;
@@ -1565,7 +1565,7 @@ static void delay_after_mux(void)
static int hsw_enable_metric_set(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
const struct i915_oa_config *oa_config = stream->oa_config;
/*
@@ -1594,7 +1594,7 @@ static int hsw_enable_metric_set(struct i915_perf_stream
*stream)
static void hsw_disable_metric_set(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
intel_uncore_rmw(uncore, GEN6_UCGCTL1,
GEN6_CSUNIT_CLOCK_GATE_DISABLE, 0);
@@ -1911,7 +1911,7 @@ static int gen8_configure_all_contexts(struct
i915_perf_stream *stream,
static int gen8_enable_metric_set(struct i915_perf_stream *stre
[Intel-gfx] [PATCH i-g-t 2/2] Add i915/gem_ctx_persistence
Sanity test existing persistence and new exciting non-persistent context
behaviour.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michał Winiarski
Cc: Jon Bloomfield
Cc: Tvrtko Ursulin
Cc: Andi Shyti
---
lib/i915/gem_context.c | 37 +++
lib/i915/gem_context.h | 8 +
lib/igt_dummyload.c | 3 +-
lib/ioctl_wrappers.c | 1 +
tests/Makefile.sources | 3 +
tests/i915/gem_ctx_persistence.c | 407 +++
tests/meson.build| 1 +
7 files changed, 459 insertions(+), 1 deletion(-)
create mode 100644 tests/i915/gem_ctx_persistence.c
diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
index 83c5df961..1fae5191f 100644
--- a/lib/i915/gem_context.c
+++ b/lib/i915/gem_context.c
@@ -272,6 +272,43 @@ void gem_context_set_priority(int fd, uint32_t ctx_id, int
prio)
igt_assert_eq(__gem_context_set_priority(fd, ctx_id, prio), 0);
}
+/**
+ * __gem_context_set_persistence:
+ * @i915: open i915 drm file descriptor
+ * @ctx: i915 context id
+ * @state: desired persistence
+ *
+ * Declare whether this context is allowed to persist after closing until
+ * its requests are complete (persistent=true) or if it should be
+ * immediately reaped on closing and its requests cancelled
+ * (persistent=false).
+ *
+ * Returns: An integer equal to zero for success and negative for failure
+ */
+int __gem_context_set_persistence(int i915, uint32_t ctx, bool state)
+{
+ struct drm_i915_gem_context_param p = {
+ .ctx_id = ctx,
+ .param = I915_CONTEXT_PARAM_PERSISTENCE,
+ .value = state,
+ };
+
+ return __gem_context_set_param(i915, &p);
+}
+
+/**
+ * __gem_context_set_persistence:
+ * @i915: open i915 drm file descriptor
+ * @ctx: i915 context id
+ * @state: desired persistence
+ *
+ * Like __gem_context_set_persistence(), except we assert on failure.
+ */
+void gem_context_set_persistence(int i915, uint32_t ctx, bool state)
+{
+ igt_assert_eq(__gem_context_set_persistence(i915, ctx, state), 0);
+}
+
int
__gem_context_clone(int i915,
uint32_t src, unsigned int share,
diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
index 8043c3401..c0d4c9615 100644
--- a/lib/i915/gem_context.h
+++ b/lib/i915/gem_context.h
@@ -24,6 +24,11 @@
#ifndef GEM_CONTEXT_H
#define GEM_CONTEXT_H
+#include
+#include
+
+struct drm_i915_gem_context_param;
+
uint32_t gem_context_create(int fd);
int __gem_context_create(int fd, uint32_t *ctx_id);
void gem_context_destroy(int fd, uint32_t ctx_id);
@@ -58,6 +63,9 @@ int __gem_context_get_param(int fd, struct
drm_i915_gem_context_param *p);
int __gem_context_set_priority(int fd, uint32_t ctx, int prio);
void gem_context_set_priority(int fd, uint32_t ctx, int prio);
+int __gem_context_set_persistence(int i915, uint32_t ctx, bool state);
+void gem_context_set_persistence(int i915, uint32_t ctx, bool state);
+
bool gem_context_has_engine(int fd, uint32_t ctx, uint64_t engine);
#endif /* GEM_CONTEXT_H */
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 65b5cc927..6060878dd 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -450,7 +450,8 @@ void igt_spin_free(int fd, igt_spin_t *spin)
gem_close(fd, spin->poll_handle);
}
- gem_close(fd, spin->handle);
+ if (spin->handle)
+ gem_close(fd, spin->handle);
if (spin->out_fence >= 0)
close(spin->out_fence);
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 280fdd624..628f8b830 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -445,6 +445,7 @@ int gem_wait(int fd, uint32_t handle, int64_t *timeout_ns)
ret = 0;
if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_WAIT, &wait))
ret = -errno;
+ errno = 0;
if (timeout_ns)
*timeout_ns = wait.timeout_ns;
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 343be0500..093eb57f3 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -154,6 +154,9 @@ gem_ctx_isolation_SOURCES = i915/gem_ctx_isolation.c
TESTS_progs += gem_ctx_param
gem_ctx_param_SOURCES = i915/gem_ctx_param.c
+TESTS_progs += gem_ctx_persistence
+gem_ctx_persistence_SOURCES = i915/gem_ctx_persistence.c
+
TESTS_progs += gem_ctx_shared
gem_ctx_shared_SOURCES = i915/gem_ctx_shared.c
diff --git a/tests/i915/gem_ctx_persistence.c b/tests/i915/gem_ctx_persistence.c
new file mode 100644
index 0..854c146ec
--- /dev/null
+++ b/tests/i915/gem_ctx_persistence.c
@@ -0,0 +1,407 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+
[Intel-gfx] [PATCH i-g-t 1/2] i915_drm.h sync
Update to commit fef476f3ab47527a00818ddaf4b46b8c0936 (not upstream!)
Author: Chris Wilson
Date: Mon Aug 5 22:55:44 2019 +0100
drm/i915: Cancel non-persistent contexts on close
for I915_CONTEXT_PARAM_PERSISTENCE
---
include/drm-uapi/i915_drm.h | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 761517f15..7badfa0b1 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -521,6 +521,7 @@ typedef struct drm_i915_irq_wait {
#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
#define I915_SCHEDULER_CAP_PREEMPTION(1ul << 2)
#define I915_SCHEDULER_CAP_SEMAPHORES(1ul << 3)
+#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
#define I915_PARAM_HUC_STATUS 42
@@ -1564,6 +1565,21 @@ struct drm_i915_gem_context_param {
* i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
*/
#define I915_CONTEXT_PARAM_ENGINES 0xa
+
+/*
+ * I915_CONTEXT_PARAM_PERSISTENCE:
+ *
+ * Allow the context and active rendering to survive the process until
+ * completion. Persistence allows fire-and-forget clients to queue up a
+ * bunch of work, hand the output over to a display server and the quit.
+ * If the context is not marked as persistent, upon closing (either via
+ * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure
+ * or process termination), the context and any outstanding requests will be
+ * cancelled (and exported fences for cancelled requests marked as -EIO).
+ *
+ * By default, new contexts allow persistence.
+ */
+#define I915_CONTEXT_PARAM_PERSISTENCE 0xb
/* Must be kept compact -- no holes and well documented */
__u64 value;
@@ -2032,8 +2048,10 @@ struct drm_i915_query {
* (data[X / 8] >> (X % 8)) & 1
*
* - the subslice mask for each slice with one bit per subslice telling
- * whether a subslice is available. The availability of subslice Y in slice
- * X can be queried with the following formula :
+ * whether a subslice is available. Gen12 has dual-subslices, which are
+ * similar to two gen11 subslices. For gen12, this array represents dual-
+ * subslices. The availability of subslice Y in slice X can be queried
+ * with the following formula :
*
* (data[subslice_offset +
* X * subslice_stride +
--
2.23.0
___
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Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/guc: improve documentation
On 10/10/2019 04:02, Daniele Ceraolo Spurio wrote:
> Add a short description of what we expect from GuC and some minor
> improvements to existing documentation. Also remove a comment about a
> difference between GuC and HuC that is not true anymore.
>
> v2: add that the GuC is not mandatory (Martin)
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Michal Wajdeczko
> Cc: Matthew Brost
> Cc: Martin Peres
> Acked-by: Anna Karas
> ---
> Documentation/gpu/i915.rst| 22 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 30 +--
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 3 --
> 4 files changed, 48 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index f1bae7867045..357e9dfa7de1 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -436,12 +436,24 @@ WOPCM Layout
> GuC
> ---
>
> -Firmware Layout
> -~~~
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
> + :doc: GuC
> +
> +GuC Firmware Layout
> +~~~
>
> .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
> :doc: Firmware Layout
>
> +GuC Memory Management
> +~
> +
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
> + :doc: GuC Memory Management
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
> + :functions: intel_guc_allocate_vma
> +
> +
> GuC-specific firmware loader
>
>
> @@ -457,12 +469,6 @@ GuC-based command submission
> .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> :internal:
>
> -GuC Address Space
> -~
> -
> -.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
> - :doc: GuC Address Space
> -
> HuC
> ---
> .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 249c747e9756..ce97600790c2 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -9,6 +9,26 @@
> #include "intel_guc_submission.h"
> #include "i915_drv.h"
>
> +/**
> + * DOC: GuC
> + *
> + * The GuC is a microcontroller inside the GT HW, introduced in gen9. The
> GuC is
> + * designed to offload some of the functionality usually performed by the
> host
> + * driver; currently the main operations it can take care of are:
> + *
> + * - Authentication of the HuC, which is required to fully enable HuC usage.
> + * - Low latency graphics context scheduling (a.k.a. GuC submission).
> + * - GT Power management.
> + *
> + * The enable_guc module parameter can be used to select which of those
> + * operations to enable within GuC. Note that not all the operations are
> + * supported on all gen9+ platforms.
Thanks for the changes!
With an added new line here, this patch is:
Reviewed-by: Martin Peres
> + * Enabling the GuC is not mandatory and therefore the firmware is only
> loaded
> + * if at least one of the operations is selected. However, not loading the
> GuC
> + * might result in the loss of some features that do require the GuC
> (currently
> + * just the HuC, but more are expected to land in the future).
> + */
> +
> static void gen8_guc_raise_irq(struct intel_guc *guc)
> {
> struct intel_gt *gt = guc_to_gt(guc);
> @@ -548,9 +568,15 @@ int intel_guc_resume(struct intel_guc *guc)
> }
>
> /**
> - * DOC: GuC Address Space
> + * DOC: GuC Memory Management
> *
> - * The layout of GuC address space is shown below:
> + * GuC can't allocate any memory for its own usage, so all the allocations
> must
> + * be handled by the host driver. GuC accesses the memory via the GGTT, with
> the
> + * exception of the top and bottom parts of the 4GB address space, which are
> + * instead re-mapped by the GuC HW to memory location of the FW itself
> (WOPCM)
> + * or other parts of the HW. The driver must take care not to place objects
> that
> + * the GuC is going to access in these reserved ranges. The layout of the GuC
> + * address space is shown below:
> *
> * ::
> *
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index f325d3dd564f..849a44add424 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -29,6 +29,12 @@ enum {
> /**
> * DOC: GuC-based command submission
> *
> + * IMPORTANT NOTE: GuC submission is currently not supported in i915. The GuC
> + * firmware is moving to an updated submission interface and we plan to
> + * turn submission back on when that lands. The below documentation (and
> related
> + * code) matches the old submission model and will be updated as part of the
> + * upgrade to the new flow.
> + *
> * GuC client:
> * A intel_guc_client refers to a submission
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm/i915: Note the addition of timeslicing to the pretend scheduler
== Series Details == Series: series starting with [01/10] drm/i915: Note the addition of timeslicing to the pretend scheduler URL : https://patchwork.freedesktop.org/series/67827/ State : warning == Summary == $ dim checkpatch origin/drm-tip cdd8a8ed5e08 drm/i915: Note the addition of timeslicing to the pretend scheduler 421324199ac5 drm/i915/execlists: Leave tell-tales as to why pending[] is bad 634779d033e3 drm/i915: Expose engine properties via sysfs -:68: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #68: new file mode 100644 -:73: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #73: FILE: drivers/gpu/drm/i915/gt/intel_engine_sysfs.c:1: +/* -:74: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #74: FILE: drivers/gpu/drm/i915/gt/intel_engine_sysfs.c:2: + * SPDX-License-Identifier: MIT -:198: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #198: FILE: drivers/gpu/drm/i915/gt/intel_engine_sysfs.h:1: +/* -:199: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #199: FILE: drivers/gpu/drm/i915/gt/intel_engine_sysfs.h:2: + * SPDX-License-Identifier: MIT total: 0 errors, 5 warnings, 0 checks, 158 lines checked b91c01a8795f drm/i915/execlists: Force preemption cd5299b94752 drm/i915: Mark up "sentinel" requests f4cbdbdb52f4 drm/i915/gt: Introduce barrier pulses along engines -:28: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #28: new file mode 100644 -:33: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #33: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:1: +/* -:34: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #34: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:2: + * SPDX-License-Identifier: MIT -:95: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #95: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h:1: +/* -:96: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #96: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h:2: + * SPDX-License-Identifier: MIT total: 0 errors, 5 warnings, 0 checks, 92 lines checked 9d4c48416b66 drm/i915/execlists: Cancel banned contexts on schedule-out 7c1088b89959 drm/i915: Cancel non-persistent contexts on close 475f4b866f55 drm/i915: Replace hangcheck by heartbeats -:236: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to using 'heartbeat', this function's name, in a string #236: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:69: + "%s heartbeat not ticking\n", -:253: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to using 'heartbeat', this function's name, in a string #253: FILE: drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:86: + "stopped heartbeat on %s", -:540: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #540: deleted file mode 100644 total: 0 errors, 3 warnings, 0 checks, 672 lines checked 082c39527d40 drm/i915: Flush idle barriers when waiting ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/execlists: Mark up expected state during reset
Move the BUG_ON around slightly and add some explanations for each to
try and capture the expected state more carefully. We want to compare
the expected active state of our bookkeeping as compared to the tracked
HW state.
References: https://bugs.freedesktop.org/show_bug.cgi?id=111937
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7ea58335f04c..7c0d3c343520 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2777,8 +2777,10 @@ static void __execlists_reset(struct intel_engine_cs
*engine, bool stalled)
if (!rq)
goto unwind;
+ /* We still have requests in-flight; the engine should be active */
+ GEM_BUG_ON(!intel_engine_pm_is_awake(engine));
+
ce = rq->hw_context;
- GEM_BUG_ON(i915_active_is_idle(&ce->active));
GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
/* Proclaim we have exclusive access to the context image! */
@@ -2786,10 +2788,13 @@ static void __execlists_reset(struct intel_engine_cs
*engine, bool stalled)
rq = active_request(rq);
if (!rq) {
+ /* Idle context; tidy up the ring so we can restart afresh */
ce->ring->head = ce->ring->tail;
goto out_replay;
}
+ /* Context has requests still in-flight; it should not be idle! */
+ GEM_BUG_ON(i915_active_is_idle(&ce->active));
ce->ring->head = intel_ring_wrap(ce->ring, rq->head);
/*
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915: Move SAGV block time to dev_priv (rev2)
== Series Details == Series: series starting with [CI,1/2] drm/i915: Move SAGV block time to dev_priv (rev2) URL : https://patchwork.freedesktop.org/series/67799/ State : success == Summary == CI Bug Log - changes from CI_DRM_7046_full -> Patchwork_14733_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14733_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb5/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_ctx_switch@all-light: - shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-apl3/igt@gem_ctx_swi...@all-light.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/shard-apl6/igt@gem_ctx_swi...@all-light.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb7/igt@gem_exec_sched...@reorder-wide-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/shard-iclb4/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup: - shard-hsw: [PASS][7] -> [DMESG-WARN][8] ([fdo#111870]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-hsw1/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/shard-hsw1/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html * igt@gem_userptr_blits@sync-unmap-cycles: - shard-snb: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-snb6/igt@gem_userptr_bl...@sync-unmap-cycles.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/shard-snb4/igt@gem_userptr_bl...@sync-unmap-cycles.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +5 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-apl1/igt@i915_susp...@sysfs-reader.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/shard-apl6/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_legacy@cursor-vs-flip-legacy: - shard-snb: [PASS][13] -> [SKIP][14] ([fdo#109271]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-snb2/igt@kms_cursor_leg...@cursor-vs-flip-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/shard-snb7/igt@kms_cursor_leg...@cursor-vs-flip-legacy.html * igt@kms_flip@2x-flip-vs-rmfb: - shard-hsw: [PASS][15] -> [INCOMPLETE][16] ([fdo#103540]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-hsw8/igt@kms_f...@2x-flip-vs-rmfb.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/shard-hsw2/igt@kms_f...@2x-flip-vs-rmfb.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html * igt@kms_psr@psr2_dpms: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb2/igt@kms_psr@psr2_dpms.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/shard-iclb8/igt@kms_psr@psr2_dpms.html * igt@prime_vgem@fence-wait-bsd2: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109276]) +19 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb1/igt@prime_v...@fence-wait-bsd2.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/shard-iclb3/igt@prime_v...@fence-wait-bsd2.html Possible fixes * igt@gem_eio@in-flight-contexts-immediate: - shard-snb: [FAIL][23] ([fdo#111925]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-snb1/igt@gem_...@in-flight-contexts-immediate.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14733/shard-snb2/igt@gem_...@in-flight-contexts-immediate.html * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][25] ([fd
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915: Note the addition of timeslicing to the pretend scheduler
== Series Details ==
Series: series starting with [01/10] drm/i915: Note the addition of timeslicing
to the pretend scheduler
URL : https://patchwork.freedesktop.org/series/67827/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7047 -> Patchwork_14742
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/index.html
Known issues
Here are the changes found in Patchwork_14742 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_create@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/fi-icl-u3/igt@gem_exec_cre...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/fi-icl-u3/igt@gem_exec_cre...@basic.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live_hangcheck:
- fi-skl-lmem:[PASS][5] -> [INCOMPLETE][6] ([fdo#108744])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/fi-skl-lmem/igt@i915_selftest@live_hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/fi-skl-lmem/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#111407])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_flink_basic@basic:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/fi-icl-u3/igt@gem_flink_ba...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/fi-icl-u3/igt@gem_flink_ba...@basic.html
* igt@gem_sync@basic-many-each:
- {fi-tgl-u}: [INCOMPLETE][11] ([fdo#111880]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/fi-tgl-u/igt@gem_s...@basic-many-each.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/fi-tgl-u/igt@gem_s...@basic-many-each.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
Participating hosts (51 -> 47)
--
Additional (3): fi-byt-j1900 fi-bsw-n3050 fi-pnv-d510
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7047 -> Patchwork_14742
CI-20190529: 20190529
CI_DRM_7047: 23ba5b1f97d3d114d30eead1ca95d5a846a9027c @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14742: 082c39527d400c14faa558e01b66b7f93deea46c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
082c39527d40 drm/i915: Flush idle barriers when waiting
475f4b866f55 drm/i915: Replace hangcheck by heartbeats
7c1088b89959 drm/i915: Cancel non-persistent contexts on close
9d4c48416b66 drm/i915/execlists: Cancel banned contexts on schedule-out
f4cbdbdb52f4 drm/i915/gt: Introduce barrier pulses along engines
cd5299b94752 drm/i915: Mark up "sentinel" requests
b91c01a8795f drm/i915/execlists: Force preemption
634779d033e3 drm/i915: Expose engine properties via sysfs
421324199ac5 drm/i915/execlists: Leave tell-tales as to why pending[] is bad
cdd8a8ed5e08 drm/i915: Note the addition of timeslicing to the pretend scheduler
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: the BCS engine supports relative MMIO
Quoting Daniele Ceraolo Spurio (2019-10-10 00:04:23) > The specs don't mention any specific HW limitation on the blitter and > manual inspection shows that the HW does set the relative MMIO bit in > the LRI of the blitter context image, so we can remove our limitations. I concur, the HW itself sets the bit, so it can't be too harmful... > Signed-off-by: Daniele Ceraolo Spurio > Cc: Chris Wilson > Cc: John Harrison > Cc: Mika Kuoppala Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: simplify the lrc register list for !RCS
Quoting Daniele Ceraolo Spurio (2019-10-10 00:04:24) > There are small differences between the blitter and the video engines in > the xcs context image (e.g. registers 0x200 and 0x204 only exist on the > blitter). Since we never explicitly set a value for those register and > given that we don't need to update the offsets in the lrc image when we > change engine within the class for virtual engine because the HW can > handle that, instead of having a separate define for the BCS we can > just restrict the programming to the part we're interested in, which is > common across the engines. Yeah, my thinking was to be as complete as possible so that if we needed to apply register updates, we could. It was also a fascinating insight into what was stored, I was planning on using it for doing isolation testing (albeit that's a bit chicken-and-egg). > Bspec: 45584 > Signed-off-by: Daniele Ceraolo Spurio > Cc: Chris Wilson > Cc: Mika Kuoppala > Cc: Stuart Summers No qualms about restricting ourselves to the bare essentials on the basis that the context image is meant to be relative-addressed. It did not improve stability of tgl-gem however. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/perf: store the associated engine of a stream
== Series Details ==
Series: series starting with [1/2] drm/i915/perf: store the associated engine
of a stream
URL : https://patchwork.freedesktop.org/series/67828/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7047 -> Patchwork_14743
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14743 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14743, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14743/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14743:
### IGT changes ###
Possible regressions
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/fi-icl-u3/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14743/fi-icl-u3/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
Known issues
Here are the changes found in Patchwork_14743 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_basic@create-fd-close:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/fi-icl-u3/igt@gem_ba...@create-fd-close.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14743/fi-icl-u3/igt@gem_ba...@create-fd-close.html
* igt@i915_selftest@live_coherency:
- fi-glk-dsi: [PASS][5] -> [TIMEOUT][6] ([fdo#111944])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/fi-glk-dsi/igt@i915_selftest@live_coherency.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14743/fi-glk-dsi/igt@i915_selftest@live_coherency.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#111045] / [fdo#111096])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14743/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_flink_basic@basic:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/fi-icl-u3/igt@gem_flink_ba...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14743/fi-icl-u3/igt@gem_flink_ba...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[fdo#111944]: https://bugs.freedesktop.org/show_bug.cgi?id=111944
Participating hosts (51 -> 46)
--
Additional (3): fi-byt-j1900 fi-bsw-n3050 fi-pnv-d510
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-gdg-551 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7047 -> Patchwork_14743
CI-20190529: 20190529
CI_DRM_7047: 23ba5b1f97d3d114d30eead1ca95d5a846a9027c @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14743: fde6feb63d256644e1aec3c32f7e27c2f15ff5e5 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fde6feb63d25 drm/i915/perf: Store shortcut to intel_uncore
af90528ae3bb drm/i915/perf: store the associated engine of a stream
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14743/index.html
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Re: [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/tgl: the BCS engine supports relative MMIO
Quoting Patchwork (2019-10-10 03:08:10) > == Series Details == > > Series: series starting with [1/2] drm/i915/tgl: the BCS engine supports > relative MMIO > URL : https://patchwork.freedesktop.org/series/67809/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_7046 -> Patchwork_14739 > > > Summary > --- > > **SUCCESS** > > No regressions found. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/index.html That's enough (boots and live_lrc found no inconsistencies) convincing, pushed. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH V2 6/8] mdev: introduce virtio device and its device ops
On 2019/9/25 上午7:06, Alex Williamson wrote:
On Tue, 24 Sep 2019 21:53:30 +0800
Jason Wang wrote:
This patch implements basic support for mdev driver that supports
virtio transport for kernel virtio driver.
Signed-off-by: Jason Wang
---
include/linux/mdev.h| 2 +
include/linux/virtio_mdev.h | 145
2 files changed, 147 insertions(+)
create mode 100644 include/linux/virtio_mdev.h
diff --git a/include/linux/mdev.h b/include/linux/mdev.h
index 3414307311f1..73ac27b3b868 100644
--- a/include/linux/mdev.h
+++ b/include/linux/mdev.h
@@ -126,6 +126,8 @@ struct mdev_device *mdev_from_dev(struct device *dev);
enum {
MDEV_ID_VFIO = 1,
+ MDEV_ID_VIRTIO = 2,
+ MDEV_ID_VHOST = 3,
MDEV_ID_VHOST isn't used yet here. Also, given the strong
interdependence between the class_id and the ops structure, we might
wand to define them in the same place. Thanks,
Alex
Rethink about this, consider we may have more types of devices supported
in the future, moving all device_ops to mdev.h seems unnecessary. I
prefer to keep the device_ops into their own headers.
Thanks
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Leave tell-tales as to why pending[] is bad (rev2)
== Series Details == Series: drm/i915/execlists: Leave tell-tales as to why pending[] is bad (rev2) URL : https://patchwork.freedesktop.org/series/67786/ State : success == Summary == CI Bug Log - changes from CI_DRM_7046_full -> Patchwork_14734_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14734_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@preempt-contexts-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#111325]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb6/igt@gem_exec_sched...@preempt-contexts-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/shard-iclb4/igt@gem_exec_sched...@preempt-contexts-bsd.html * igt@gem_userptr_blits@sync-unmap: - shard-hsw: [PASS][3] -> [DMESG-WARN][4] ([fdo#111870]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-hsw7/igt@gem_userptr_bl...@sync-unmap.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/shard-hsw6/igt@gem_userptr_bl...@sync-unmap.html * igt@gem_wait@write-wait-bcs0: - shard-skl: [PASS][5] -> [DMESG-WARN][6] ([fdo#106107]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-skl7/igt@gem_w...@write-wait-bcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/shard-skl6/igt@gem_w...@write-wait-bcs0.html * igt@kms_cursor_crc@pipe-b-cursor-128x128-random: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#103232]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-skl6/igt@kms_cursor_...@pipe-b-cursor-128x128-random.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/shard-skl10/igt@kms_cursor_...@pipe-b-cursor-128x128-random.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-apl2/igt@kms_cursor_...@pipe-c-cursor-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/shard-apl4/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_flip@2x-flip-vs-rmfb: - shard-hsw: [PASS][11] -> [INCOMPLETE][12] ([fdo#103540]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-hsw8/igt@kms_f...@2x-flip-vs-rmfb.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/shard-hsw1/igt@kms_f...@2x-flip-vs-rmfb.html * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: [PASS][13] -> [FAIL][14] ([fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-glk6/igt@kms_f...@flip-vs-expired-vblank.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/shard-glk1/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#109507]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-skl3/igt@kms_f...@flip-vs-suspend-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/shard-skl8/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html * igt@kms_psr@psr2_dpms: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb2/igt@kms_psr@psr2_dpms.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/shard-iclb5/igt@kms_psr@psr2_dpms.html * igt@prime_vgem@fence-wait-bsd2: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109276]) +15 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb1/igt@prime_v...@fence-wait-bsd2.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/shard-iclb7/igt@prime_v...@fence-wait-bsd2.html Possible fixes * igt@gem_exec_balancer@smoke: - shard-iclb: [SKIP][23] ([fdo#110854]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb8/igt@gem_exec_balan...@smoke.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14734/shard-iclb1/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@in-order-bsd2: - shard-iclb: [SKIP][25] ([fdo#109276]) -> [PASS][26] +15 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb6/igt@gem_exec_sched.
Re: [Intel-gfx] [PATCH 8/8] drm/print: introduce new struct drm_device based logging macros
On Wed, 09 Oct 2019, "Ruhl, Michael J" wrote: >>-Original Message- >>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >>Jani Nikula >>+/* Helper for struct drm_device based logging. */ >>+#define __drm_printk(drm, level, type, fmt, ...) \ >>+ dev_##level##type(drm->dev, "[drm] " fmt, ##__VA_ARGS__) > > In the past, I have been able to do a: > > #undef pr_fmt > #define pr_fmt(fmt) "[myinfo here] " fmt > > And have the "[myinfo here]" portion show up the output. > > Is it possible that you might be able to use this instead of "[drm] " fmt? > > I think that the this will be the same result, but might be more in > line with the printk interface? pr_fmt is only used by the pr_() macros in printk.h that use printk. This does not use printk. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gt: Warn CI about an unrecoverable wedge
Hi Chris,
On Wednesday, October 2, 2019 6:00:34 PM CEST Chris Wilson wrote:
> If we have a wedged GPU that we need to recover, but fail, add a taint
> for CI to pickup and schedule a reboot.
As your approach has been chosen by CI, FWIW:
Reviewed-by: Janusz Krzysztofik
Thanks,
Janusz
>
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> Cc: Petri Latvala
> ---
> drivers/gpu/drm/i915/gt/intel_reset.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index e189897e8797..bc1b51349438 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -872,8 +872,14 @@ static bool __intel_gt_unset_wedged(struct intel_gt *gt)
> ok = !HAS_EXECLISTS(gt->i915); /* XXX better agnosticism desired */
> if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
> ok = __intel_gt_reset(gt, ALL_ENGINES) == 0;
> - if (!ok)
> + if (!ok) {
> + /*
> + * Warn CI about the unrecoverable wedged condition.
> + * Time for a reboot.
> + */
> + add_taint_for_CI(TAINT_WARN);
> return false;
> + }
>
> /*
>* Undo nop_submit_request. We prevent all new i915 requests from
>
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Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/huc: improve documentation
On 10/10/2019 04:02, Daniele Ceraolo Spurio wrote:
> Better explain the usage of the microcontroller and what i915 is
> responsible of. While at it, fix the documentation for the auth
> function, which doesn't do any pinning anymore.
>
> v2: add a comment on HuC being optional and descrive how HuC accesses
> memory (Martin)
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Michal Wajdeczko
> Cc: Martin Peres
> Acked-by: Anna Karas
> ---
> Documentation/gpu/i915.rst| 16 +--
> drivers/gpu/drm/i915/gt/uc/intel_huc.c| 33 ---
> drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 15 ---
> 3 files changed, 43 insertions(+), 21 deletions(-)
>
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index 357e9dfa7de1..60bd6e6403da 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -471,8 +471,20 @@ GuC-based command submission
>
> HuC
> ---
> -.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> - :doc: HuC Firmware
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
> + :doc: HuC
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
> + :functions: intel_huc_auth
> +
> +HuC Memory Management
> +~
> +
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
> + :doc: HuC Memory Management
> +
> +HuC Firmware Layout
> +~~~
> +The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_
>
> DMC
> ---
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> index 33608a114d4e..c802e5b68c05 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> @@ -9,6 +9,32 @@
> #include "intel_huc.h"
> #include "i915_drv.h"
>
> +/**
> + * DOC: HuC
> + *
> + * The HuC is a dedicated microcontroller for usage in media HEVC (High
> + * Efficiency Video Coding) operations. Userspace can directly use the
> firmware
> + * capabilities by adding HuC specific commands to batch buffers.
Would be good to separate paragraphs with an empty line, for consistency.
> + * The kernel driver is only responsible for loading the HuC firmware and
> + * triggering its security authentication, which is performed by the GuC. For
> + * The GuC to correctly perform the authentication, the HuC binary must be
> + * loaded before the GuC one. Loading the HuC is optional; however, not using
> + * the HuC might negatively impact power usage and/or performance of media
> + * workloads, depending on the use-cases.
Same here.
> + * See https://github.com/intel/media-driver for the latest details on HuC
> + * functionality.
Well, isn't that the perfect link!? The media team has done a great job
on their communication!
> + */
> +
> +/**
> + * DOC: HuC Memory Management
> + *
> + * Similarly to the GuC, the HuC can't do any memory allocations on its own,
> + * with the difference being that the allocations for HuC usage are handled
> by
> + * the userspace driver instead of the kernel one. The HuC accesses the
> memory
> + * via the PPGTT belonging to the context loaded on the VCS executing the
> + * HuC-specific commands.
> + */
Thanks!
Reviewed-by: Martin Peres
Now, only one firmware is left to document! Jani, can you take actions
to improve the DMC documentation?
Martin
> +
> void intel_huc_init_early(struct intel_huc *huc)
> {
> struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
> @@ -118,10 +144,9 @@ void intel_huc_fini(struct intel_huc *huc)
> *
> * Called after HuC and GuC firmware loading during intel_uc_init_hw().
> *
> - * This function pins HuC firmware image object into GGTT.
> - * Then it invokes GuC action to authenticate passing the offset to RSA
> - * signature through intel_guc_auth_huc(). It then waits for 50ms for
> - * firmware verification ACK and unpins the object.
> + * This function invokes the GuC action to authenticate the HuC firmware,
> + * passing the offset of the RSA signature to intel_guc_auth_huc(). It then
> + * waits for up to 50ms for firmware verification ACK.
> */
> int intel_huc_auth(struct intel_huc *huc)
> {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> index 74602487ed67..d654340d4d03 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> @@ -7,21 +7,6 @@
> #include "intel_huc_fw.h"
> #include "i915_drv.h"
>
> -/**
> - * DOC: HuC Firmware
> - *
> - * Motivation:
> - * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
> - * Efficiency Video Coding) operations. Userspace can use the firmware
> - * capabilities by adding HuC specific commands to batch buffers.
> - *
> - * Implementation:
> - * The same firmware loader is used as the GuC. However, the actual
> - * loading to HW is deferred until GEM initialization is done.
> - *
> - * Note that HuC firmware loading must be done be
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Gen12 E2E compression (rev3)
== Series Details ==
Series: Gen12 E2E compression (rev3)
URL : https://patchwork.freedesktop.org/series/67078/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a2306a44f000 drm/framebuffer: Format modifier for Intel Gen-12 render
compression
7fceadb0dd8f drm/i915: Use intel_tile_height() instead of re-implementing
c5ab08ba0ad9 drm/i915: Move CCS stride alignment W/A inside
intel_fb_stride_alignment
50577506a5d2 drm/i915/tgl: Gen-12 render decompression
5e136b5b4a25 drm/i915: Extract framebufer CCS offset checks into a function
-:48: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each
line
#48: FILE: drivers/gpu/drm/i915/display/intel_display.c:2703:
+ /*
+ * CCS doesn't have its own x/y offset register, so the intra CCS tile
total: 0 errors, 1 warnings, 0 checks, 81 lines checked
eeb4a92dd984 drm/framebuffer: Format modifier for Intel Gen-12 media compression
6049b78b30bd drm/i915: Skip rotated offset adjustment for unsupported modifiers
7ccb87c9160b drm/fb: Extend format_info member arrays to handle four planes
cf0459685876 Gen-12 display can decompress surfaces compressed by the media
engine.
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#13:
compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
-:230: WARNING:LONG_LINE: line over 100 characters
#230: FILE: drivers/gpu/drm/i915/display/intel_display.c:2720:
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct
drm_framebuffer *fb, int color_plane)
-:264: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_display.c:2754:
+ *w = fb->width/hsub;
^
-:265: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#265: FILE: drivers/gpu/drm/i915/display/intel_display.c:2755:
+ *h = fb->height/vsub;
^
-:415: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#415: FILE: drivers/gpu/drm/i915/display/intel_display.c:3620:
if (is_ccs_modifier(fb->modifier)) {
+
-:443: CHECK:LINE_SPACING: Please don't use multiple blank lines
#443: FILE: drivers/gpu/drm/i915/display/intel_display.c:3682:
+
+
-:453: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#453: FILE: drivers/gpu/drm/i915/display/intel_display.c:3692:
+
+ }
-:496: CHECK:SPACING: spaces preferred around that '/' (ctx:VxW)
#496: FILE: drivers/gpu/drm/i915/display/intel_display.c:3731:
+ intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, (ccs
- 1)/ 2);
^
total: 0 errors, 2 warnings, 6 checks, 659 lines checked
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/9] drm/i915/perf: store the associated engine of a stream
== Series Details ==
Series: series starting with [1/9] drm/i915/perf: store the associated engine
of a stream
URL : https://patchwork.freedesktop.org/series/67804/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046_full -> Patchwork_14736_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14736_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_sync@basic-many-each:
- {shard-tglb}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-tglb7/igt@gem_s...@basic-many-each.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/shard-tglb7/igt@gem_s...@basic-many-each.html
New tests
-
New tests have been introduced between CI_DRM_7046_full and
Patchwork_14736_full:
### New IGT tests (1) ###
* igt@i915_selftest@live_perf:
- Statuses : 8 pass(s)
- Exec time: [0.30, 2.63] s
Known issues
Here are the changes found in Patchwork_14736_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +5
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-apl8/igt@gem_ctx_isolat...@rcs0-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/shard-apl1/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +6 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb5/igt@gem_exec_sched...@preemptive-hang-bsd.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html
* igt@gem_mmap_gtt@hang:
- shard-snb: [PASS][7] -> [INCOMPLETE][8] ([fdo#105411])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-snb6/igt@gem_mmap_...@hang.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/shard-snb7/igt@gem_mmap_...@hang.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-hsw: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-hsw1/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/shard-hsw1/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-snb6/igt@gem_userptr_bl...@sync-unmap-cycles.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/shard-snb5/igt@gem_userptr_bl...@sync-unmap-cycles.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#104108])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-skl9/igt@gem_workarou...@suspend-resume-fd.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/shard-skl5/igt@gem_workarou...@suspend-resume-fd.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-hsw: [PASS][15] -> [INCOMPLETE][16] ([fdo#103540])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-hsw5/igt@kms_f...@2x-flip-vs-suspend.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/shard-hsw2/igt@kms_f...@2x-flip-vs-suspend.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#105363])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-skl4/igt@kms_f...@flip-vs-expired-vblank.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/shard-skl4/igt@kms_f...@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +1 similar
issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar
issue
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb2/igt@kms_psr@psr2_dpms.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14736/shard-iclb8/igt@kms_psr@psr2_dpms.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][23] -> [S
[Intel-gfx] [PATCH] drm/i915/selftests: Check that registers are preserved between virtual engines
Make sure that we copy across the registers from one engine to the next,
as we hop around a virtual engine.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 176 +
1 file changed, 176 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 198cf2f754f4..ebb1e9b4e71d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1952,6 +1952,181 @@ static int live_virtual_engine(void *arg)
return 0;
}
+static struct i915_vma *create_scratch(struct intel_gt *gt)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err;
+
+ obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
+
+ vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
+static int preserved_virtual_engine(struct drm_i915_private *i915,
+ struct intel_engine_cs **siblings,
+ unsigned int nsibling)
+{
+#define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
+
+ struct i915_request *last = NULL;
+ struct i915_gem_context *ctx;
+ struct intel_context *ve;
+ struct i915_vma *scratch;
+ struct igt_live_test t;
+ const int num_gpr = 16 * 2; /* each GPR is 2 dwords */
+ unsigned int n;
+ int err = 0;
+
+ ctx = kernel_context(i915);
+ if (!ctx)
+ return -ENOMEM;
+
+ scratch = create_scratch(siblings[0]->gt);
+ if (IS_ERR(scratch)) {
+ err = PTR_ERR(scratch);
+ goto out_close;
+ }
+
+ ve = intel_execlists_create_virtual(ctx, siblings, nsibling);
+ if (IS_ERR(ve)) {
+ err = PTR_ERR(ve);
+ goto out_scratch;
+ }
+
+ err = intel_context_pin(ve);
+ if (err)
+ goto out_put;
+
+ err = igt_live_test_begin(&t, i915, __func__, ve->engine->name);
+ if (err)
+ goto out_unpin;
+
+ for (n = 0; n < num_gpr; n++) {
+ struct intel_engine_cs *engine = siblings[n % nsibling];
+ struct i915_request *rq;
+ u32 *cs;
+
+ rq = i915_request_create(ve);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_end;
+ }
+
+ i915_request_put(last);
+ last = i915_request_get(rq);
+
+ cs = intel_ring_begin(rq, 8);
+ if (IS_ERR(cs)) {
+ i915_request_add(rq);
+ err = PTR_ERR(cs);
+ goto out_end;
+ }
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = CS_GPR(engine, n);
+ *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);
+ *cs++ = 0;
+
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = CS_GPR(engine, (n + 1) % num_gpr);
+ *cs++ = n + 1;
+
+ *cs++ = MI_NOOP;
+ intel_ring_advance(rq, cs);
+
+ /* Restrict this request to run on a particular engine */
+ rq->execution_mask = engine->mask;
+ i915_request_add(rq);
+ }
+
+ if (i915_request_wait(last, 0, HZ / 5) < 0) {
+ err = -ETIME;
+ } else {
+ u32 *map = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
+
+ for (n = 0; n < num_gpr; n++) {
+ if (map[n] != n) {
+ pr_err("Incorrect value[%d] found for
GPR[%d]\n",
+ map[n], n);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_map(scratch->obj);
+ }
+
+out_end:
+ if (igt_live_test_end(&t))
+ err = -EIO;
+ i915_request_put(last);
+out_unpin:
+ intel_context_unpin(ve);
+out_put:
+ intel_context_put(ve);
+out_scratch:
+ i915_vma_unpin_and_release(&scratch, 0);
+out_close:
+ kernel_context_close(ctx);
+ return err;
+
+#undef CS_GPR
+}
+
+static int live_virtual_preserved(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct intel_engine_cs *siblings[MAX_ENGINE_INSTANCE + 1];
+ struct intel_gt *gt = &i915->gt;
+ unsigned int class, inst;
+
+ /*
+* Check that the
[Intel-gfx] ✗ Fi.CI.BAT: failure for Gen12 E2E compression (rev3)
== Series Details == Series: Gen12 E2E compression (rev3) URL : https://patchwork.freedesktop.org/series/67078/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7049 -> Patchwork_14744 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14744 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14744, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14744: ### IGT changes ### Possible regressions * igt@kms_addfb_basic@bo-too-small-due-to-tiling: - fi-kbl-x1275: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-kbl-x1275/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-kbl-x1275/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-apl-guc: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-apl-guc/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-apl-guc/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-bsw-kefka: [PASS][5] -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-bsw-kefka/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-bsw-kefka/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-bdw-5557u: [PASS][7] -> [FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-bdw-5557u/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-bdw-5557u/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-bwr-2160:[PASS][9] -> [FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-bwr-2160/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-bwr-2160/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-skl-6770hq: [PASS][11] -> [FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-skl-6770hq/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-skl-6770hq/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-skl-6600u: [PASS][13] -> [FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-skl-6600u/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-skl-6600u/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-kbl-guc: [PASS][15] -> [FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-kbl-guc/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-kbl-guc/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-kbl-8809g: [PASS][17] -> [FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-kbl-8809g/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-kbl-8809g/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-skl-lmem:[PASS][19] -> [FAIL][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-skl-lmem/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-skl-lmem/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-kbl-r: [PASS][21] -> [FAIL][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-kbl-r/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-kbl-r/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-skl-6260u: [PASS][23] -> [FAIL][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-skl-6260u/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-skl-6260u/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-byt-n2820: [PASS][25] -> [FAIL][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7049/fi-byt-n2820/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14744/fi-byt-n2820/igt@kms_addfb_ba...@bo-too-small-due-to-tiling.html - fi-snb-2600:[PASS][27] -> [FAIL][28] [27]: h
Re: [Intel-gfx] [PATCH 3/4] [v5] drm/i915/color: Extract icl_read_luts()
On 09-Oct-19 7:46 PM, Ville Syrjälä wrote:
On Wed, Oct 09, 2019 at 12:25:41PM +0530, Swati Sharma wrote:
For icl+, have hw read out to create hw blob of gamma
lut values. icl+ platforms supports multi segmented gamma
mode by default, add hw lut creation for this mode.
This will be used to validate gamma programming using dsb
(display state buffer) which is a tgl specific feature.
Major change done-removal of readouts of coarse and fine segments
because PAL_PREC_DATA register isn't giving propoer values.
State checker limited only to "fine segment"
v2: -readout code for multisegmented gamma has to come
up with some intermediate entries that aren't preserved
in hardware (Jani N)
-linear interpolation (Ville)
-moved common code to check gamma_enable to specific funcs,
since icl doesn't support that
v3: -use u16 instead of __u16 [Jani N]
-used single lut [Jani N]
-improved and more readable for loops [Jani N]
-read values directly to actual locations and then fill gaps [Jani N]
-moved cleaning to patch 1 [Jani N]
-renamed icl_read_lut_multi_seg() to icl_read_lut_multi_segment to
make it similar to icl_load_luts()
-renamed icl_compute_interpolated_gamma_blob() to
icl_compute_interpolated_gamma_lut_values() more sensible, I guess
v4: -removed interpolated func for creating gamma lut values
-removed readouts of fine and coarse segments, failure to read
PAL_PREC_DATA
correctly
v5: -added gamma_enable check inside read_luts()
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_color.c | 114 ++---
drivers/gpu/drm/i915/i915_reg.h| 6 ++
2 files changed, 108 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index fa44eb73d088..614e0ad386ca 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1477,6 +1477,25 @@ static int glk_gamma_precision(const struct
intel_crtc_state *crtc_state)
}
}
+static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
+{
+ if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
+ return 0;
+
+ switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
+ case GAMMA_MODE_MODE_8BIT:
+ return 8;
+ case GAMMA_MODE_MODE_10BIT:
+ return 10;
+ case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
+ return 16;
+ default:
+ MISSING_CASE(crtc_state->gamma_mode);
+ return 0;
+ }
+
+}
+
int intel_color_get_gamma_bit_precision(const struct intel_crtc_state
*crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -1488,7 +1507,9 @@ int intel_color_get_gamma_bit_precision(const struct
intel_crtc_state *crtc_stat
else
return i9xx_gamma_precision(crtc_state);
} else {
- if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11)
+ return icl_gamma_precision(crtc_state);
+ else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
return glk_gamma_precision(crtc_state);
else if (IS_IRONLAKE(dev_priv))
return ilk_gamma_precision(crtc_state);
@@ -1519,6 +1540,20 @@ static bool intel_color_lut_entry_equal(struct
drm_color_lut *lut1,
return true;
}
+static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1,
+ struct drm_color_lut *lut2,
+ int lut_size, u32 err)
+{
+ int i;
+
+ for (i = 0; i < 9; i++) {
+ if (!err_check(&lut1[i], &lut2[i], err))
+ return false;
+ }
+
+ return true;
+}
+
bool intel_color_lut_equal(struct drm_property_blob *blob1,
struct drm_property_blob *blob2,
u32 gamma_mode, u32 bit_precision)
@@ -1537,16 +1572,8 @@ bool intel_color_lut_equal(struct drm_property_blob
*blob1,
lut_size2 = drm_color_lut_size(blob2);
/* check sw and hw lut size */
- switch (gamma_mode) {
- case GAMMA_MODE_MODE_8BIT:
- case GAMMA_MODE_MODE_10BIT:
- if (lut_size1 != lut_size2)
- return false;
- break;
- default:
- MISSING_CASE(gamma_mode);
- return false;
- }
+ if (lut_size1 != lut_size2)
+ return false;
lut1 = blob1->data;
lut2 = blob2->data;
@@ -1554,13 +1581,18 @@ bool intel_color_lut_equal(struct drm_property_blob
*blob1,
err = 0x >> bit_precision;
/* check sw and hw lut entry to be equal */
- switch (gamma_mode) {
+ switch (gamm
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Check that registers are preserved between virtual engines
Quoting Chris Wilson (2019-10-10 11:36:57) > Make sure that we copy across the registers from one engine to the next, > as we hop around a virtual engine. Looking at Broadwell's HW context image, there are no GPR registers for xcs. Weird. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: Check that registers are preserved between virtual engines
Make sure that we copy across the registers from one engine to the next,
as we hop around a virtual engine.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
Skip the test on gen8 as the context image is devoid of CS_GPR.
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 180 +
1 file changed, 180 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 198cf2f754f4..9ee1fdd16aff 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1952,6 +1952,33 @@ static int live_virtual_engine(void *arg)
return 0;
}
+static struct i915_vma *create_scratch(struct intel_gt *gt)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err;
+
+ obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
+
+ vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
static int mask_virtual_engine(struct drm_i915_private *i915,
struct intel_engine_cs **siblings,
unsigned int nsibling)
@@ -2076,6 +2103,158 @@ static int live_virtual_mask(void *arg)
return 0;
}
+static int preserved_virtual_engine(struct drm_i915_private *i915,
+ struct intel_engine_cs **siblings,
+ unsigned int nsibling)
+{
+#define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
+
+ struct i915_request *last = NULL;
+ struct i915_gem_context *ctx;
+ struct intel_context *ve;
+ struct i915_vma *scratch;
+ struct igt_live_test t;
+ const int num_gpr = 16 * 2; /* each GPR is 2 dwords */
+ unsigned int n;
+ int err = 0;
+
+ ctx = kernel_context(i915);
+ if (!ctx)
+ return -ENOMEM;
+
+ scratch = create_scratch(siblings[0]->gt);
+ if (IS_ERR(scratch)) {
+ err = PTR_ERR(scratch);
+ goto out_close;
+ }
+
+ ve = intel_execlists_create_virtual(ctx, siblings, nsibling);
+ if (IS_ERR(ve)) {
+ err = PTR_ERR(ve);
+ goto out_scratch;
+ }
+
+ err = intel_context_pin(ve);
+ if (err)
+ goto out_put;
+
+ err = igt_live_test_begin(&t, i915, __func__, ve->engine->name);
+ if (err)
+ goto out_unpin;
+
+ for (n = 0; n < num_gpr; n++) {
+ struct intel_engine_cs *engine = siblings[n % nsibling];
+ struct i915_request *rq;
+ u32 *cs;
+
+ rq = i915_request_create(ve);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_end;
+ }
+
+ i915_request_put(last);
+ last = i915_request_get(rq);
+
+ cs = intel_ring_begin(rq, 8);
+ if (IS_ERR(cs)) {
+ i915_request_add(rq);
+ err = PTR_ERR(cs);
+ goto out_end;
+ }
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = CS_GPR(engine, n);
+ *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);
+ *cs++ = 0;
+
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = CS_GPR(engine, (n + 1) % num_gpr);
+ *cs++ = n + 1;
+
+ *cs++ = MI_NOOP;
+ intel_ring_advance(rq, cs);
+
+ /* Restrict this request to run on a particular engine */
+ rq->execution_mask = engine->mask;
+ i915_request_add(rq);
+ }
+
+ if (i915_request_wait(last, 0, HZ / 5) < 0) {
+ err = -ETIME;
+ } else {
+ u32 *map = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
+
+ for (n = 0; n < num_gpr; n++) {
+ if (map[n] != n) {
+ pr_err("Incorrect value[%d] found for
GPR[%d]\n",
+ map[n], n);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_map(scratch->obj);
+ }
+
+out_end:
+ if (igt_live_test_end(&t))
+ err = -EIO;
+ i915_request_put(last);
+out_unpin:
+ intel_context_unpin(ve);
+out_put:
+ intel_context_put(ve);
+out_scratch:
+ i915_vma_unpin_and_release(&scratch, 0);
+out_close:
+ kernel
[Intel-gfx] [PULL] drm-misc-fixes
Hi Dave, Daniel, Here's this week drm-misc-fixes PR, dealing mostly with SPI probing related issues. Maxime drm-misc-fixes-2019-10-10: Short summary of fixes pull (less than what git shortlog provides): - SPI Aliases fixes for panels - One fix for the tc358767 bridge dealing with visual artifacts The following changes since commit b6559bf3ac32acfe34e17c73d68581e7f7415785: Merge drm-misc-next-fixes-2019-10-02 into drm-misc-fixes (2019-10-03 10:00:13 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2019-10-10 for you to fetch changes up to fd70c7755bf0172ddd33b558aef69c322de3b5cf: drm/bridge: tc358767: fix max_tu_symbol value (2019-10-10 11:15:45 +0200) Short summary of fixes pull (less than what git shortlog provides): - SPI Aliases fixes for panels - One fix for the tc358767 bridge dealing with visual artifacts Laurent Pinchart (5): drm/panel: lg-lb035q02: Fix SPI alias drm/panel: nec-nl8048hl11: Fix SPI alias drm/panel: sony-acx565akm: Fix SPI alias drm/panel: tpo-td028ttec1: Fix SPI alias drm/panel: tpo-td043mtea1: Fix SPI alias Tomi Valkeinen (1): drm/bridge: tc358767: fix max_tu_symbol value drivers/gpu/drm/bridge/tc358767.c| 7 ++- drivers/gpu/drm/panel/panel-lg-lb035q02.c| 9 - drivers/gpu/drm/panel/panel-nec-nl8048hl11.c | 9 - drivers/gpu/drm/panel/panel-sony-acx565akm.c | 9 - drivers/gpu/drm/panel/panel-tpo-td028ttec1.c | 3 +-- drivers/gpu/drm/panel/panel-tpo-td043mtea1.c | 9 - 6 files changed, 39 insertions(+), 7 deletions(-) signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/dp-mst: Drop connection_mutex check
== Series Details == Series: drm/dp-mst: Drop connection_mutex check URL : https://patchwork.freedesktop.org/series/67807/ State : success == Summary == CI Bug Log - changes from CI_DRM_7046_full -> Patchwork_14738_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14738_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@unwedge-stress: - shard-snb: [PASS][1] -> [FAIL][2] ([fdo#109661]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-snb4/igt@gem_...@unwedge-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/shard-snb6/igt@gem_...@unwedge-stress.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +15 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb4/igt@gem_exec_sched...@independent-bsd2.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/shard-iclb8/igt@gem_exec_sched...@independent-bsd2.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb7/igt@gem_exec_sched...@reorder-wide-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/shard-iclb1/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_tiled_swapping@non-threaded: - shard-hsw: [PASS][7] -> [INCOMPLETE][8] ([fdo#103540] / [fdo#108686]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-hsw2/igt@gem_tiled_swapp...@non-threaded.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/shard-hsw6/igt@gem_tiled_swapp...@non-threaded.html * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup: - shard-hsw: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-hsw1/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/shard-hsw5/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html * igt@gem_userptr_blits@sync-unmap-after-close: - shard-snb: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-snb6/igt@gem_userptr_bl...@sync-unmap-after-close.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/shard-snb7/igt@gem_userptr_bl...@sync-unmap-after-close.html * igt@i915_selftest@live_workarounds: - shard-kbl: [PASS][13] -> [DMESG-FAIL][14] ([fdo#111926]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-kbl4/igt@i915_selftest@live_workarounds.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/shard-kbl6/igt@i915_selftest@live_workarounds.html * igt@kms_flip@2x-flip-vs-suspend: - shard-hsw: [PASS][15] -> [INCOMPLETE][16] ([fdo#103540]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-hsw5/igt@kms_f...@2x-flip-vs-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/shard-hsw2/igt@kms_f...@2x-flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-apl2/igt@kms_frontbuffer_track...@fbc-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/shard-apl8/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +6 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc: - shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#106978] / [fdo#107713]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb6/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-indfb-draw-mmap-wc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/shard-iclb1/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-indfb-draw-mmap-wc.html * igt@kms_psr@psr2_dpms: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb2/igt@kms_psr@psr2_dpms.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14738/shard-iclb8/igt@kms_psr@psr2_dpms.html Possible fixes * i
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Mark up expected state during reset
== Series Details ==
Series: drm/i915/execlists: Mark up expected state during reset
URL : https://patchwork.freedesktop.org/series/67830/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7050 -> Patchwork_14745
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14745/index.html
Known issues
Here are the changes found in Patchwork_14745 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7050/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14745/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111407])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7050/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14745/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_ctx_switch@rcs0:
- fi-bxt-dsi: [INCOMPLETE][5] ([fdo#103927]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7050/fi-bxt-dsi/igt@gem_ctx_swi...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14745/fi-bxt-dsi/igt@gem_ctx_swi...@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7050/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14745/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7050/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14745/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
* igt@gem_sync@basic-many-each:
- {fi-tgl-u}: [INCOMPLETE][11] ([fdo#111880]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7050/fi-tgl-u/igt@gem_s...@basic-many-each.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14745/fi-tgl-u/igt@gem_s...@basic-many-each.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
Participating hosts (54 -> 45)
--
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-apl-guc fi-byt-clapper fi-icl-y fi-icl-dsi fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7050 -> Patchwork_14745
CI-20190529: 20190529
CI_DRM_7050: 3cbcf12cbe84552ae4d629e2dd2c0c32603207be @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14745: 550d59bea8458b087f8675bb0dba32109fbca954 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
550d59bea845 drm/i915/execlists: Mark up expected state during reset
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14745/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/24] drm/i915: Introduce intel_atomic_get_plane_state_after_check()
Op 08-10-2019 om 19:03 schreef Ville Syrjälä:
> On Fri, Oct 04, 2019 at 01:34:57PM +0200, Maarten Lankhorst wrote:
>> Use this in all the places where we try to acquire planes after the planes
>> atomic_check().
>>
>> In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
>> but seems like it will be in the future. To add some paranoia, add all planes
>> rather than active planes, because of bigjoiner and planar YUV support having
>> extra planes outside of the core's view that wouldn't be added otherwise.
> If the plane isn't active what good does adding it do?
>
> Maybe the only real exception I can think of is the watermarks
> and the primary vs. gamma/csc_enable on pre-skl, but those are
> already handled correctly.
Planar YUV Y planes are not enumerated, so it's useful to add. Instead of
typing up special case support I thought it was easier to just add all
planes. On bigjoiner slave no planes are enabled either, even if they're
active.
>
>> Signed-off-by: Maarten Lankhorst
>> ---
>> drivers/gpu/drm/i915/display/intel_atomic.c | 41 +--
>> .../gpu/drm/i915/display/intel_atomic_plane.c | 19 +
>> drivers/gpu/drm/i915/display/intel_cdclk.c| 15 ---
>> drivers/gpu/drm/i915/display/intel_color.c| 7 ++--
>> .../drm/i915/display/intel_display_types.h| 6 +++
>> drivers/gpu/drm/i915/intel_pm.c | 14 ---
>> 6 files changed, 66 insertions(+), 36 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
>> b/drivers/gpu/drm/i915/display/intel_atomic.c
>> index c5a552a69752..e6cb85d41c8d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
>> @@ -313,13 +313,10 @@ int intel_atomic_setup_scalers(struct drm_i915_private
>> *dev_priv,
>> struct intel_crtc *intel_crtc,
>> struct intel_crtc_state *crtc_state)
>> {
>> -struct drm_plane *plane = NULL;
>> -struct intel_plane *intel_plane;
>> -struct intel_plane_state *plane_state = NULL;
>> struct intel_crtc_scaler_state *scaler_state =
>> &crtc_state->scaler_state;
>> struct drm_atomic_state *drm_state = crtc_state->base.state;
>> -struct intel_atomic_state *intel_state =
>> to_intel_atomic_state(drm_state);
>> +struct intel_atomic_state *state = to_intel_atomic_state(drm_state);
>> int num_scalers_need;
>> int i;
>>
>> @@ -346,6 +343,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private
>> *dev_priv,
>>
>> /* walkthrough scaler_users bits and start assigning scalers */
>> for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
>> +struct intel_plane_state *plane_state = NULL;
>> int *scaler_id;
>> const char *name;
>> int idx;
>> @@ -361,19 +359,16 @@ int intel_atomic_setup_scalers(struct drm_i915_private
>> *dev_priv,
>> /* panel fitter case: assign as a crtc scaler */
>> scaler_id = &scaler_state->scaler_id;
>> } else {
>> -name = "PLANE";
>> +struct intel_plane *plane;
>>
>> /* plane scaler case: assign as a plane scaler */
>> /* find the plane that set the bit as scaler_user */
>> -plane = drm_state->planes[i].ptr;
>>
>> /*
>> * to enable/disable hq mode, add planes that are using
>> scaler
>> * into this transaction
>> */
>> -if (!plane) {
>> -struct drm_plane_state *state;
>> -
>> +if (!drm_state->planes[i].ptr) {
>> /*
>> * GLK+ scalers don't have a HQ mode so it
>> * isn't necessary to change between HQ and dyn
>> mode
>> @@ -382,24 +377,28 @@ int intel_atomic_setup_scalers(struct drm_i915_private
>> *dev_priv,
>> if (INTEL_GEN(dev_priv) >= 10 ||
>> IS_GEMINILAKE(dev_priv))
>> continue;
>>
>> -plane = drm_plane_from_index(&dev_priv->drm, i);
>> -state = drm_atomic_get_plane_state(drm_state,
>> plane);
>> -if (IS_ERR(state)) {
>> -DRM_DEBUG_KMS("Failed to add [PLANE:%d]
>> to drm_state\n",
>> -plane->base.id);
>> -return PTR_ERR(state);
>> +plane =
>> to_intel_plane(drm_plane_from_index(&dev_priv->drm, i));
>> +plane_state =
>> +
>> intel_atomic_get_plane_state_after_check(state,
>> +
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/tgl: the BCS engine supports relative MMIO
== Series Details ==
Series: series starting with [1/2] drm/i915/tgl: the BCS engine supports
relative MMIO
URL : https://patchwork.freedesktop.org/series/67809/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046_full -> Patchwork_14739_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14739_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_flip@blocking-wf_vblank:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/shard-tglb5/igt@kms_flip@blocking-wf_vblank.html
Known issues
Here are the changes found in Patchwork_14739_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@legacy-bsd1:
- shard-iclb: [PASS][2] -> [INCOMPLETE][3] ([fdo#107713])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb8/igt@gem_ctx_swi...@legacy-bsd1.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/shard-iclb1/igt@gem_ctx_swi...@legacy-bsd1.html
* igt@gem_exec_schedule@deep-render:
- shard-apl: [PASS][4] -> [INCOMPLETE][5] ([fdo#103927]) +1
similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-apl1/igt@gem_exec_sched...@deep-render.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/shard-apl7/igt@gem_exec_sched...@deep-render.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#109276]) +13 similar
issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb2/igt@gem_exec_sched...@promotion-bsd1.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/shard-iclb6/igt@gem_exec_sched...@promotion-bsd1.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#111325]) +3 similar
issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb7/igt@gem_exec_sched...@reorder-wide-bsd.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/shard-iclb4/igt@gem_exec_sched...@reorder-wide-bsd.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [PASS][10] -> [INCOMPLETE][11] ([fdo#104108])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-skl4/igt@gem_soft...@noreloc-s3.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/shard-skl8/igt@gem_soft...@noreloc-s3.html
* igt@gem_tiled_swapping@non-threaded:
- shard-hsw: [PASS][12] -> [DMESG-FAIL][13] ([fdo#108686])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-hsw2/igt@gem_tiled_swapp...@non-threaded.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/shard-hsw1/igt@gem_tiled_swapp...@non-threaded.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [PASS][14] -> [DMESG-WARN][15] ([fdo#111870]) +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-snb6/igt@gem_userptr_bl...@sync-unmap-cycles.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/shard-snb6/igt@gem_userptr_bl...@sync-unmap-cycles.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][16] -> [DMESG-WARN][17] ([fdo#108566]) +3
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-apl1/igt@i915_susp...@sysfs-reader.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/shard-apl4/igt@i915_susp...@sysfs-reader.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [PASS][18] -> [FAIL][19] ([fdo#105363])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-glk6/igt@kms_f...@flip-vs-expired-vblank.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/shard-glk5/igt@kms_f...@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [PASS][20] -> [FAIL][21] ([fdo#103167]) +2 similar
issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [PASS][22] -> [SKIP][23] ([fdo#109441])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb2/igt@kms_psr@psr2_dpms.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14739/shard-iclb1/igt@kms_psr@psr2_dpms.html
Possible fixes
* igt@gem_eio@i
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Check that registers are preserved between virtual engines (rev2)
== Series Details ==
Series: drm/i915/selftests: Check that registers are preserved between virtual
engines (rev2)
URL : https://patchwork.freedesktop.org/series/67837/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7050 -> Patchwork_14746
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14746 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14746, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14746/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14746:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_gtt:
- fi-whl-u: [PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7050/fi-whl-u/igt@i915_selftest@live_gtt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14746/fi-whl-u/igt@i915_selftest@live_gtt.html
Known issues
Here are the changes found in Patchwork_14746 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap@basic-small-bo:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7050/fi-icl-u3/igt@gem_m...@basic-small-bo.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14746/fi-icl-u3/igt@gem_m...@basic-small-bo.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#111407])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7050/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14746/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7050/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14746/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111887]: https://bugs.freedesktop.org/show_bug.cgi?id=111887
Participating hosts (54 -> 45)
--
Missing(9): fi-cml-u2 fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7050 -> Patchwork_14746
CI-20190529: 20190529
CI_DRM_7050: 3cbcf12cbe84552ae4d629e2dd2c0c32603207be @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14746: fbc2a5183c9d48a020e44c18e4dc078a7a0acac0 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fbc2a5183c9d drm/i915/selftests: Check that registers are preserved between
virtual engines
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14746/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/selftests: Check that registers are preserved between virtual engines
Make sure that we copy across the registers from one engine to the next,
as we hop around a virtual engine.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 180 +
1 file changed, 180 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 198cf2f754f4..a691e429ca01 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -19,6 +19,33 @@
#include "gem/selftests/igt_gem_utils.h"
#include "gem/selftests/mock_context.h"
+static struct i915_vma *create_scratch(struct intel_gt *gt)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err;
+
+ obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
+
+ vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
static int live_sanitycheck(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -2076,6 +2103,158 @@ static int live_virtual_mask(void *arg)
return 0;
}
+static int preserved_virtual_engine(struct drm_i915_private *i915,
+ struct intel_engine_cs **siblings,
+ unsigned int nsibling)
+{
+#define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
+
+ struct i915_request *last = NULL;
+ struct i915_gem_context *ctx;
+ struct intel_context *ve;
+ struct i915_vma *scratch;
+ struct igt_live_test t;
+ const int num_gpr = 16 * 2; /* each GPR is 2 dwords */
+ unsigned int n;
+ int err = 0;
+
+ ctx = kernel_context(i915);
+ if (!ctx)
+ return -ENOMEM;
+
+ scratch = create_scratch(siblings[0]->gt);
+ if (IS_ERR(scratch)) {
+ err = PTR_ERR(scratch);
+ goto out_close;
+ }
+
+ ve = intel_execlists_create_virtual(ctx, siblings, nsibling);
+ if (IS_ERR(ve)) {
+ err = PTR_ERR(ve);
+ goto out_scratch;
+ }
+
+ err = intel_context_pin(ve);
+ if (err)
+ goto out_put;
+
+ err = igt_live_test_begin(&t, i915, __func__, ve->engine->name);
+ if (err)
+ goto out_unpin;
+
+ for (n = 0; n < num_gpr; n++) {
+ struct intel_engine_cs *engine = siblings[n % nsibling];
+ struct i915_request *rq;
+ u32 *cs;
+
+ rq = i915_request_create(ve);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_end;
+ }
+
+ i915_request_put(last);
+ last = i915_request_get(rq);
+
+ cs = intel_ring_begin(rq, 8);
+ if (IS_ERR(cs)) {
+ i915_request_add(rq);
+ err = PTR_ERR(cs);
+ goto out_end;
+ }
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = CS_GPR(engine, n);
+ *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);
+ *cs++ = 0;
+
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = CS_GPR(engine, (n + 1) % num_gpr);
+ *cs++ = n + 1;
+
+ *cs++ = MI_NOOP;
+ intel_ring_advance(rq, cs);
+
+ /* Restrict this request to run on a particular engine */
+ rq->execution_mask = engine->mask;
+ i915_request_add(rq);
+ }
+
+ if (i915_request_wait(last, 0, HZ / 5) < 0) {
+ err = -ETIME;
+ } else {
+ u32 *map = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
+
+ for (n = 0; n < num_gpr; n++) {
+ if (map[n] != n) {
+ pr_err("Incorrect value[%d] found for
GPR[%d]\n",
+ map[n], n);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_map(scratch->obj);
+ }
+
+out_end:
+ if (igt_live_test_end(&t))
+ err = -EIO;
+ i915_request_put(last);
+out_unpin:
+ intel_context_unpin(ve);
+out_put:
+ intel_context_put(ve);
+out_scratch:
+ i915_vma_unpin_and_release(&scratch, 0);
+out_close:
+ kernel_context_close(ctx);
+ return err;
+
+#undef CS_GPR
+}
+
+static int live_virtual_preserved(void *arg)
+{
+ struct drm_i915_private *i9
[Intel-gfx] [PATCH 2/2] drm/i915/selftests: Check known register values within the context
Check the logical ring context by asserting that the registers hold
expected start during execution. (It's a bit chicken-and-egg for how
could we manage to execute our request if the registers were not being
updated. Still, it's nice to verify that the HW is working as expected.)
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 138 +
1 file changed, 138 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index a691e429ca01..def1e64aaf1c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -2599,10 +2599,148 @@ static int live_lrc_layout(void *arg)
return err;
}
+static int __live_lrc_state(struct i915_gem_context *fixme,
+ struct intel_engine_cs *engine,
+ struct i915_vma *scratch)
+{
+ struct intel_context *ce;
+ struct i915_request *rq;
+ enum {
+ RING_START_IDX = 0,
+ RING_HEAD_IDX,
+ RING_TAIL_IDX,
+ MAX_IDX
+ };
+ u32 expected[MAX_IDX];
+ u32 *cs;
+ int err;
+ int n;
+
+ ce = intel_context_create(fixme, engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ err = intel_context_pin(ce);
+ if (err)
+ goto err_put;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_unpin;
+ }
+
+ expected[RING_HEAD_IDX] = ce->ring->emit;
+
+ cs = intel_ring_begin(rq, 4 * MAX_IDX);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ i915_request_add(rq);
+ goto err_unpin;
+ }
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base));
+ *cs++ = i915_ggtt_offset(scratch) + RING_START_IDX * sizeof(u32);
+ *cs++ = 0;
+
+ expected[RING_START_IDX] = i915_ggtt_offset(ce->ring->vma);
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(RING_HEAD(engine->mmio_base));
+ *cs++ = i915_ggtt_offset(scratch) + RING_HEAD_IDX * sizeof(u32);
+ *cs++ = 0;
+
+ expected[RING_HEAD_IDX] += 6 * sizeof(u32);
+ if (engine->class == RENDER_CLASS)
+ expected[RING_HEAD_IDX] += 2 * sizeof(u32);
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(RING_TAIL(engine->mmio_base));
+ *cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32);
+ *cs++ = 0;
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ intel_engine_flush_submission(engine);
+ expected[RING_TAIL_IDX] = ce->ring->tail;
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0) {
+ err = -ETIME;
+ goto err_rq;
+ }
+
+ cs = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err_rq;
+ }
+
+ for (n = 0; n < MAX_IDX; n++) {
+ if (cs[n] != expected[n]) {
+ pr_err("%s: Stored register[%d] value[0x%x] did not
match expected[0x%x]\n",
+ engine->name, n, cs[n], expected[n]);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_map(scratch->obj);
+
+err_rq:
+ i915_request_put(rq);
+err_unpin:
+ intel_context_unpin(ce);
+err_put:
+ intel_context_put(ce);
+ return err;
+}
+
+static int live_lrc_state(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ struct i915_gem_context *fixme;
+ struct i915_vma *scratch;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /*
+* Check the live register state matches what we expect for this
+* intel_context.
+*/
+
+ fixme = kernel_context(gt->i915);
+ if (!fixme)
+ return -ENOMEM;
+
+ scratch = create_scratch(gt);
+ if (IS_ERR(scratch)) {
+ err = PTR_ERR(scratch);
+ goto out_close;
+ }
+
+ for_each_engine(engine, gt->i915, id) {
+ err = __live_lrc_state(fixme, engine, scratch);
+ if (err)
+ break;
+ }
+
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+
+ i915_vma_unpin_and_release(&scratch, 0);
+out_close:
+ kernel_context_close(fixme);
+ return err;
+}
+
int intel_lrc_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_lrc_layout),
+ SUBTEST(live_lrc_state),
};
if (!HAS_LOGICAL_RING_CONTEXTS(i915))
--
2.23.0
___
Re: [Intel-gfx] [PATCH 04/24] drm/i915: Remove cursor use of properties for coordinates
Op 07-10-2019 om 21:37 schreef Matt Roper:
> On Fri, Oct 04, 2019 at 01:34:54PM +0200, Maarten Lankhorst wrote:
>> We have a src and dect rectangle, use it instead of relying on
>> the core drm properties.
>>
>> This removes the special case in the watermark code for cursor w/h.
>>
>> Signed-off-by: Maarten Lankhorst
> I think you should make it more clear in the commit message here that
> you're actually overwriting the clipped coordinates in src/dst with the
> unclipped coordinates that we program into our hardware. I missed that
> the first time reading through the patch; using clipped coordinates
> would obviously cause lots of failures.
>
> Actually, even if this is safe at the moment, we're violating the
> documented expectations of the DRM core. I'd suggest also adding a drm
> core patch that updates the comment on drm_plane_state to indicate that
> the contents may or may not be clipped (driver-specific) and that the
> core shouldn't assume either way.
https://patchwork.freedesktop.org/patch/335245/?series=67840&rev=1
?
~Maarten
>
> Matt
>
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 57 +++
>> drivers/gpu/drm/i915/intel_pm.c | 58 +++-
>> 2 files changed, 53 insertions(+), 62 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index c3ac5a5c5185..9e34be48c770 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -10591,16 +10591,16 @@ static u32 intel_cursor_base(const struct
>> intel_plane_state *plane_state)
>> /* ILK+ do this automagically */
>> if (HAS_GMCH(dev_priv) &&
>> plane_state->base.rotation & DRM_MODE_ROTATE_180)
>> -base += (plane_state->base.crtc_h *
>> - plane_state->base.crtc_w - 1) * fb->format->cpp[0];
>> +base += (drm_rect_height(&plane_state->base.dst) *
>> + drm_rect_width(&plane_state->base.dst) - 1) *
>> fb->format->cpp[0];
>>
>> return base;
>> }
>>
>> static u32 intel_cursor_position(const struct intel_plane_state
>> *plane_state)
>> {
>> -int x = plane_state->base.crtc_x;
>> -int y = plane_state->base.crtc_y;
>> +int x = plane_state->base.dst.x1;
>> +int y = plane_state->base.dst.y1;
>> u32 pos = 0;
>>
>> if (x < 0) {
>> @@ -10622,8 +10622,8 @@ static bool intel_cursor_size_ok(const struct
>> intel_plane_state *plane_state)
>> {
>> const struct drm_mode_config *config =
>> &plane_state->base.plane->dev->mode_config;
>> -int width = plane_state->base.crtc_w;
>> -int height = plane_state->base.crtc_h;
>> +int width = drm_rect_width(&plane_state->base.dst);
>> +int height = drm_rect_height(&plane_state->base.dst);
>>
>> return width > 0 && width <= config->cursor_width &&
>> height > 0 && height <= config->cursor_height;
>> @@ -10642,8 +10642,8 @@ static int intel_cursor_check_surface(struct
>> intel_plane_state *plane_state)
>> if (!plane_state->base.visible)
>> return 0;
>>
>> -src_x = plane_state->base.src_x >> 16;
>> -src_y = plane_state->base.src_y >> 16;
>> +src_x = plane_state->base.src.x1 >> 16;
>> +src_y = plane_state->base.src.y1 >> 16;
>>
>> intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
>> offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
>> @@ -10678,6 +10678,10 @@ static int intel_check_cursor(struct
>> intel_crtc_state *crtc_state,
>> if (ret)
>> return ret;
>>
>> +/* Use the unclipped src/dst rectangles, which we program to hw */
>> +plane_state->base.src = drm_plane_state_src(&plane_state->base);
>> +plane_state->base.dst = drm_plane_state_dest(&plane_state->base);
>> +
>> ret = intel_cursor_check_surface(plane_state);
>> if (ret)
>> return ret;
>> @@ -10720,7 +10724,7 @@ static u32 i845_cursor_ctl(const struct
>> intel_crtc_state *crtc_state,
>>
>> static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
>> {
>> -int width = plane_state->base.crtc_w;
>> +int width = drm_rect_width(&plane_state->base.dst);
>>
>> /*
>> * 845g/865g are only limited by the width of their cursors,
>> @@ -10746,8 +10750,8 @@ static int i845_check_cursor(struct intel_crtc_state
>> *crtc_state,
>> /* Check for which cursor types we support */
>> if (!i845_cursor_size_ok(plane_state)) {
>> DRM_DEBUG("Cursor dimension %dx%d not supported\n",
>> - plane_state->base.crtc_w,
>> - plane_state->base.crtc_h);
>> + drm_rect_width(&plane_state->base.dst),
>> + drm_rect_height(&plane_state->base.dst));
>> return -EINVAL;
>> }
>>
>> @@ -10780,8 +10784,8 @@ static void i845_update_cursor(struct intel_plane
>> *plane,
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Check that registers are preserved between virtual engines
On 10/10/2019 12:02, Chris Wilson wrote:
Make sure that we copy across the registers from one engine to the next,
as we hop around a virtual engine.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
Skip the test on gen8 as the context image is devoid of CS_GPR.
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 180 +
1 file changed, 180 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 198cf2f754f4..9ee1fdd16aff 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1952,6 +1952,33 @@ static int live_virtual_engine(void *arg)
return 0;
}
+static struct i915_vma *create_scratch(struct intel_gt *gt)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err;
+
+ obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
+
+ vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
static int mask_virtual_engine(struct drm_i915_private *i915,
struct intel_engine_cs **siblings,
unsigned int nsibling)
@@ -2076,6 +2103,158 @@ static int live_virtual_mask(void *arg)
return 0;
}
+static int preserved_virtual_engine(struct drm_i915_private *i915,
+ struct intel_engine_cs **siblings,
+ unsigned int nsibling)
+{
+#define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
+
+ struct i915_request *last = NULL;
+ struct i915_gem_context *ctx;
+ struct intel_context *ve;
+ struct i915_vma *scratch;
+ struct igt_live_test t;
+ const int num_gpr = 16 * 2; /* each GPR is 2 dwords */
+ unsigned int n;
+ int err = 0;
+
+ ctx = kernel_context(i915);
+ if (!ctx)
+ return -ENOMEM;
+
+ scratch = create_scratch(siblings[0]->gt);
+ if (IS_ERR(scratch)) {
+ err = PTR_ERR(scratch);
+ goto out_close;
+ }
+
+ ve = intel_execlists_create_virtual(ctx, siblings, nsibling);
+ if (IS_ERR(ve)) {
+ err = PTR_ERR(ve);
+ goto out_scratch;
+ }
+
+ err = intel_context_pin(ve);
+ if (err)
+ goto out_put;
+
+ err = igt_live_test_begin(&t, i915, __func__, ve->engine->name);
+ if (err)
+ goto out_unpin;
+
+ for (n = 0; n < num_gpr; n++) {
+ struct intel_engine_cs *engine = siblings[n % nsibling];
+ struct i915_request *rq;
+ u32 *cs;
+
+ rq = i915_request_create(ve);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_end;
+ }
+
+ i915_request_put(last);
+ last = i915_request_get(rq);
+
+ cs = intel_ring_begin(rq, 8);
+ if (IS_ERR(cs)) {
+ i915_request_add(rq);
+ err = PTR_ERR(cs);
+ goto out_end;
+ }
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = CS_GPR(engine, n);
+ *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);
+ *cs++ = 0;
+
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = CS_GPR(engine, (n + 1) % num_gpr);
+ *cs++ = n + 1;
+
+ *cs++ = MI_NOOP;
+ intel_ring_advance(rq, cs);
+
+ /* Restrict this request to run on a particular engine */
+ rq->execution_mask = engine->mask;
+ i915_request_add(rq);
+ }
+
+ if (i915_request_wait(last, 0, HZ / 5) < 0) {
+ err = -ETIME;
+ } else {
+ u32 *map = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
+
+ for (n = 0; n < num_gpr; n++) {
+ if (map[n] != n) {
+ pr_err("Incorrect value[%d] found for
GPR[%d]\n",
+ map[n], n);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_map(scratch->obj);
+ }
+
+out_end:
+ if (igt_live_test_end(&t))
+ err = -EIO;
+ i915_request_put(last);
+out_unpin:
+ intel_context_unpin(ve);
+out_put:
+ intel_context_put(ve);
+out_scratch:
+ i915_vma_unpin
Re: [Intel-gfx] [PATCH v4 5/5] drm/i915/pmu: Support multiple GPUs
Hi guys,
Any feedback on the below?
On 06/09/2019 16:47, Tvrtko Ursulin wrote:
Peter, Thomas,
If you could spare a moment for some brainstorming on the topic of
uncore PMU and multiple providers it would be appreciated.
So from i915 we export some metrics as uncore PMU, which shows up under
/sys/devices/i915. Shortsightedness or what, we did not realize that one
day we could have more than one i915 device in a system which now
creates a problem, or at least raises a question on naming.
The patch below works around this by appending the PCI device name to
additional instances of i915 when it registers with perf_pmu_register.
Question is if there is a better solution, or if not, whether you are
aware of any plans to extend the perf core to better support this? Are
there any other uncore PMU providers in an identical situation?
Regards,
Tvrtko
On 01/08/2019 16:54, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
With discrete graphics system can have both integrated and discrete GPU
handled by i915.
Currently we use a fixed name ("i915") when registering as the uncore PMU
provider which stops working in this case.
To fix this we add the PCI device name string to non-integrated devices
handled by us. Integrated devices keep the legacy name preserving
backward compatibility.
v2:
* Detect IGP and keep legacy name. (Michal)
* Use PCI device name as suffix. (Michal, Chris)
v3:
* Constify the name. (Chris)
* Use pci_domain_nr. (Chris)
v4:
* Fix kfree_const usage. (Chris)
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Michal Wajdeczko
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pmu.c | 25 +++--
drivers/gpu/drm/i915/i915_pmu.h | 4
2 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c
b/drivers/gpu/drm/i915/i915_pmu.c
index e0e0180bca7c..e0fea227077e 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -1053,6 +1053,15 @@ static void
i915_pmu_unregister_cpuhp_state(struct i915_pmu *pmu)
cpuhp_remove_multi_state(cpuhp_slot);
}
+static bool is_igp(struct pci_dev *pdev)
+{
+ /* IGP is :00:02.0 */
+ return pci_domain_nr(pdev->bus) == 0 &&
+ pdev->bus->number == 0 &&
+ PCI_SLOT(pdev->devfn) == 2 &&
+ PCI_FUNC(pdev->devfn) == 0;
+}
+
void i915_pmu_register(struct drm_i915_private *i915)
{
struct i915_pmu *pmu = &i915->pmu;
@@ -1083,10 +1092,19 @@ void i915_pmu_register(struct drm_i915_private
*i915)
hrtimer_init(&pmu->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
pmu->timer.function = i915_sample;
- ret = perf_pmu_register(&pmu->base, "i915", -1);
- if (ret)
+ if (!is_igp(i915->drm.pdev))
+ pmu->name = kasprintf(GFP_KERNEL,
+ "i915-%s",
+ dev_name(i915->drm.dev));
+ else
+ pmu->name = "i915";
+ if (!pmu->name)
goto err;
+ ret = perf_pmu_register(&pmu->base, pmu->name, -1);
+ if (ret)
+ goto err_name;
+
ret = i915_pmu_register_cpuhp_state(pmu);
if (ret)
goto err_unreg;
@@ -1095,6 +1113,8 @@ void i915_pmu_register(struct drm_i915_private
*i915)
err_unreg:
perf_pmu_unregister(&pmu->base);
+err_name:
+ kfree_const(pmu->name);
err:
pmu->base.event_init = NULL;
free_event_attributes(pmu);
@@ -1116,5 +1136,6 @@ void i915_pmu_unregister(struct drm_i915_private
*i915)
perf_pmu_unregister(&pmu->base);
pmu->base.event_init = NULL;
+ kfree_const(pmu->name);
free_event_attributes(pmu);
}
diff --git a/drivers/gpu/drm/i915/i915_pmu.h
b/drivers/gpu/drm/i915/i915_pmu.h
index 4fc4f2478301..ff24f3bb0102 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -46,6 +46,10 @@ struct i915_pmu {
* @base: PMU base.
*/
struct pmu base;
+ /**
+ * @name: Name as registered with perf core.
+ */
+ const char *name;
/**
* @lock: Lock protecting enable mask and ref count handling.
*/
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Re: [Intel-gfx] [PATCH 07/24] drm/i915: Introduce intel_atomic_get_plane_state_after_check()
On Thu, Oct 10, 2019 at 01:56:42PM +0200, Maarten Lankhorst wrote:
> Op 08-10-2019 om 19:03 schreef Ville Syrjälä:
> > On Fri, Oct 04, 2019 at 01:34:57PM +0200, Maarten Lankhorst wrote:
> >> Use this in all the places where we try to acquire planes after the planes
> >> atomic_check().
> >>
> >> In case of intel_modeset_all_pipes() this is not yet done after
> >> atomic_check,
> >> but seems like it will be in the future. To add some paranoia, add all
> >> planes
> >> rather than active planes, because of bigjoiner and planar YUV support
> >> having
> >> extra planes outside of the core's view that wouldn't be added otherwise.
> > If the plane isn't active what good does adding it do?
> >
> > Maybe the only real exception I can think of is the watermarks
> > and the primary vs. gamma/csc_enable on pre-skl, but those are
> > already handled correctly.
>
> Planar YUV Y planes are not enumerated, so it's useful to add. Instead of
> typing up special case support I thought it was easier to just add all
> planes. On bigjoiner slave no planes are enabled either, even if they're
> active.
I think once we have the state split we should get rid of all the
special casing of the Y planes. Then they (and the bigjoiner slave
planes) should just look like an active planes which is not
logically enabled by uapi.
>
> >
> >> Signed-off-by: Maarten Lankhorst
> >> ---
> >> drivers/gpu/drm/i915/display/intel_atomic.c | 41 +--
> >> .../gpu/drm/i915/display/intel_atomic_plane.c | 19 +
> >> drivers/gpu/drm/i915/display/intel_cdclk.c| 15 ---
> >> drivers/gpu/drm/i915/display/intel_color.c| 7 ++--
> >> .../drm/i915/display/intel_display_types.h| 6 +++
> >> drivers/gpu/drm/i915/intel_pm.c | 14 ---
> >> 6 files changed, 66 insertions(+), 36 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> >> b/drivers/gpu/drm/i915/display/intel_atomic.c
> >> index c5a552a69752..e6cb85d41c8d 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> >> @@ -313,13 +313,10 @@ int intel_atomic_setup_scalers(struct
> >> drm_i915_private *dev_priv,
> >> struct intel_crtc *intel_crtc,
> >> struct intel_crtc_state *crtc_state)
> >> {
> >> - struct drm_plane *plane = NULL;
> >> - struct intel_plane *intel_plane;
> >> - struct intel_plane_state *plane_state = NULL;
> >>struct intel_crtc_scaler_state *scaler_state =
> >>&crtc_state->scaler_state;
> >>struct drm_atomic_state *drm_state = crtc_state->base.state;
> >> - struct intel_atomic_state *intel_state =
> >> to_intel_atomic_state(drm_state);
> >> + struct intel_atomic_state *state = to_intel_atomic_state(drm_state);
> >>int num_scalers_need;
> >>int i;
> >>
> >> @@ -346,6 +343,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private
> >> *dev_priv,
> >>
> >>/* walkthrough scaler_users bits and start assigning scalers */
> >>for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
> >> + struct intel_plane_state *plane_state = NULL;
> >>int *scaler_id;
> >>const char *name;
> >>int idx;
> >> @@ -361,19 +359,16 @@ int intel_atomic_setup_scalers(struct
> >> drm_i915_private *dev_priv,
> >>/* panel fitter case: assign as a crtc scaler */
> >>scaler_id = &scaler_state->scaler_id;
> >>} else {
> >> - name = "PLANE";
> >> + struct intel_plane *plane;
> >>
> >>/* plane scaler case: assign as a plane scaler */
> >>/* find the plane that set the bit as scaler_user */
> >> - plane = drm_state->planes[i].ptr;
> >>
> >>/*
> >> * to enable/disable hq mode, add planes that are using
> >> scaler
> >> * into this transaction
> >> */
> >> - if (!plane) {
> >> - struct drm_plane_state *state;
> >> -
> >> + if (!drm_state->planes[i].ptr) {
> >>/*
> >> * GLK+ scalers don't have a HQ mode so it
> >> * isn't necessary to change between HQ and dyn
> >> mode
> >> @@ -382,24 +377,28 @@ int intel_atomic_setup_scalers(struct
> >> drm_i915_private *dev_priv,
> >>if (INTEL_GEN(dev_priv) >= 10 ||
> >> IS_GEMINILAKE(dev_priv))
> >>continue;
> >>
> >> - plane = drm_plane_from_index(&dev_priv->drm, i);
> >> - state = drm_atomic_get_plane_state(drm_state,
> >> plane);
> >> - if (IS_ERR(state)) {
> >> - DRM_DEBUG_KMS("Failed to add [PLANE:%d]
> >> to drm_state\n",
> >> -
Re: [Intel-gfx] [PATCH 15/24] drm/i915: Try to make bigjoiner work in atomic check, v2.
Op 08-10-2019 om 21:40 schreef Ville Syrjälä:
> On Fri, Oct 04, 2019 at 01:35:05PM +0200, Maarten Lankhorst wrote:
>> When the clock is higher than the dotclock, try with 2 pipes enabled.
>> If we can enable 2, then we will go into big joiner mode, and steal
>> the adjacent crtc.
>>
>> This only links the crtc's in software, no hardware or plane
>> programming is done yet. Blobs are also copied from the master's
>> crtc_state, so it doesn't depend at commit time on the other
>> crtc_state.
>>
>> Changes since v1:
>> - Rename pipe timings to transcoder timings, as they are now different.
>>
>> Signed-off-by: Maarten Lankhorst
>> ---
>> drivers/gpu/drm/i915/display/intel_atomic.c | 15 +-
>> drivers/gpu/drm/i915/display/intel_atomic.h | 3 +-
>> drivers/gpu/drm/i915/display/intel_display.c | 218 --
>> .../drm/i915/display/intel_display_types.h| 11 +-
>> drivers/gpu/drm/i915/display/intel_dp.c | 25 +-
>> 5 files changed, 234 insertions(+), 38 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
>> b/drivers/gpu/drm/i915/display/intel_atomic.c
>> index 4783d7ff4fcf..a5b11bd9da68 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
>> @@ -228,25 +228,26 @@ void intel_crtc_free_hw_state(struct intel_crtc_state
>> *crtc_state)
>> intel_crtc_put_color_blobs(crtc_state);
>> }
>>
>> -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
>> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
>> + const struct intel_crtc_state *from_crtc_state)
>> {
>> intel_crtc_put_color_blobs(crtc_state);
>>
>> -if (crtc_state->uapi.degamma_lut)
>> +if (from_crtc_state->uapi.degamma_lut)
>> crtc_state->hw.degamma_lut =
>> -drm_property_blob_get(crtc_state->uapi.degamma_lut);
>> +
>> drm_property_blob_get(from_crtc_state->uapi.degamma_lut);
>> else
>> crtc_state->hw.degamma_lut = NULL;
>>
>> -if (crtc_state->uapi.gamma_lut)
>> +if (from_crtc_state->uapi.gamma_lut)
>> crtc_state->hw.gamma_lut =
>> -drm_property_blob_get(crtc_state->uapi.gamma_lut);
>> +drm_property_blob_get(from_crtc_state->uapi.gamma_lut);
>> else
>> crtc_state->hw.gamma_lut = NULL;
>>
>> -if (crtc_state->uapi.ctm)
>> +if (from_crtc_state->uapi.ctm)
>> crtc_state->hw.ctm =
>> -drm_property_blob_get(crtc_state->uapi.ctm);
>> +drm_property_blob_get(from_crtc_state->uapi.ctm);
>> else
>> crtc_state->hw.ctm = NULL;
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
>> b/drivers/gpu/drm/i915/display/intel_atomic.h
>> index 42be91e0772a..8da84d64aa04 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
>> @@ -36,7 +36,8 @@ struct drm_crtc_state *intel_crtc_duplicate_state(struct
>> drm_crtc *crtc);
>> void intel_crtc_destroy_state(struct drm_crtc *crtc,
>> struct drm_crtc_state *state);
>> void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
>> -void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
>> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
>> + const struct intel_crtc_state
>> *from_crtc_state);
>> struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
>> void intel_atomic_state_clear(struct drm_atomic_state *state);
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index caab8cfddcbd..c2b3c7b6f39b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -123,7 +123,7 @@ static void ironlake_pch_clock_get(struct intel_crtc
>> *crtc,
>> static int intel_framebuffer_init(struct intel_framebuffer *ifb,
>>struct drm_i915_gem_object *obj,
>>struct drm_mode_fb_cmd2 *mode_cmd);
>> -static void intel_set_pipe_timings(const struct intel_crtc_state
>> *crtc_state);
>> +static void intel_set_transcoder_timings(const struct intel_crtc_state
>> *crtc_state);
>> static void intel_set_pipe_src_size(const struct intel_crtc_state
>> *crtc_state);
>> static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state
>> *crtc_state,
>> const struct intel_link_m_n *m_n,
>> @@ -6308,7 +6308,7 @@ static void ironlake_crtc_enable(struct
>> intel_crtc_state *pipe_config,
>> if (intel_crtc_has_dp_encoder(pipe_config))
>> intel_dp_set_m_n(pipe_config, M1_N1);
>>
>> -intel_set_pipe_timings(pipe_config);
>> +intel_set_transcoder_timings(pipe_config);
>> intel_set_pipe
Re: [Intel-gfx] [PATCH] drm/i915/execlists: Mark up expected state during reset
Chris Wilson writes:
> Move the BUG_ON around slightly and add some explanations for each to
> try and capture the expected state more carefully. We want to compare
> the expected active state of our bookkeeping as compared to the tracked
> HW state.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=111937
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 7ea58335f04c..7c0d3c343520 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2777,8 +2777,10 @@ static void __execlists_reset(struct intel_engine_cs
> *engine, bool stalled)
> if (!rq)
> goto unwind;
>
> + /* We still have requests in-flight; the engine should be active */
> + GEM_BUG_ON(!intel_engine_pm_is_awake(engine));
> +
> ce = rq->hw_context;
> - GEM_BUG_ON(i915_active_is_idle(&ce->active));
> GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
>
> /* Proclaim we have exclusive access to the context image! */
> @@ -2786,10 +2788,13 @@ static void __execlists_reset(struct intel_engine_cs
> *engine, bool stalled)
>
> rq = active_request(rq);
> if (!rq) {
> + /* Idle context; tidy up the ring so we can restart afresh */
> ce->ring->head = ce->ring->tail;
> goto out_replay;
> }
>
> + /* Context has requests still in-flight; it should not be idle! */
> + GEM_BUG_ON(i915_active_is_idle(&ce->active));
> ce->ring->head = intel_ring_wrap(ce->ring, rq->head);
>
> /*
> --
> 2.23.0
>
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[Intel-gfx] Does the i915 VBT tell us if a panel is an OLED panel?
Hi Jani, During plumbers I had some discussions with Daniel about supporting OLED screens. Userspace may need to know that a panel is OLED for 2 reasons: 1) To avoid screen burn-in 2) OLED screens do not have a classic backlight, so in some cases some sort of brightness/contrast emulation through gamma tables may be necessary to still allow the user to control the brightness. The idea we've discussed is to add a property on the drm_connector (details to be filled in) which indicates that the panel is an OLED panel. This has lead to the question: "how do we know the panel is OLED"? Do you know if this info is coded into the VBT somewhere? Regards, Hans ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Check that registers are preserved between virtual engines
Quoting Tvrtko Ursulin (2019-10-10 13:31:04)
>
> On 10/10/2019 12:02, Chris Wilson wrote:
> > Make sure that we copy across the registers from one engine to the next,
> > as we hop around a virtual engine.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > ---
> > Skip the test on gen8 as the context image is devoid of CS_GPR.
> > ---
> > drivers/gpu/drm/i915/gt/selftest_lrc.c | 180 +
> > 1 file changed, 180 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > index 198cf2f754f4..9ee1fdd16aff 100644
> > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > @@ -1952,6 +1952,33 @@ static int live_virtual_engine(void *arg)
> > return 0;
> > }
> >
> > +static struct i915_vma *create_scratch(struct intel_gt *gt)
> > +{
> > + struct drm_i915_gem_object *obj;
> > + struct i915_vma *vma;
> > + int err;
> > +
> > + obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
> > + if (IS_ERR(obj))
> > + return ERR_CAST(obj);
> > +
> > + i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
> > +
> > + vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
> > + if (IS_ERR(vma)) {
> > + i915_gem_object_put(obj);
> > + return vma;
> > + }
> > +
> > + err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
> > + if (err) {
> > + i915_gem_object_put(obj);
> > + return ERR_PTR(err);
> > + }
> > +
> > + return vma;
> > +}
> > +
> > static int mask_virtual_engine(struct drm_i915_private *i915,
> > struct intel_engine_cs **siblings,
> > unsigned int nsibling)
> > @@ -2076,6 +2103,158 @@ static int live_virtual_mask(void *arg)
> > return 0;
> > }
> >
> > +static int preserved_virtual_engine(struct drm_i915_private *i915,
> > + struct intel_engine_cs **siblings,
> > + unsigned int nsibling)
> > +{
> > +#define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
> > +
> > + struct i915_request *last = NULL;
> > + struct i915_gem_context *ctx;
> > + struct intel_context *ve;
> > + struct i915_vma *scratch;
> > + struct igt_live_test t;
> > + const int num_gpr = 16 * 2; /* each GPR is 2 dwords */
> > + unsigned int n;
> > + int err = 0;
> > +
> > + ctx = kernel_context(i915);
> > + if (!ctx)
> > + return -ENOMEM;
> > +
> > + scratch = create_scratch(siblings[0]->gt);
> > + if (IS_ERR(scratch)) {
> > + err = PTR_ERR(scratch);
> > + goto out_close;
> > + }
> > +
> > + ve = intel_execlists_create_virtual(ctx, siblings, nsibling);
> > + if (IS_ERR(ve)) {
> > + err = PTR_ERR(ve);
> > + goto out_scratch;
> > + }
> > +
> > + err = intel_context_pin(ve);
> > + if (err)
> > + goto out_put;
> > +
> > + err = igt_live_test_begin(&t, i915, __func__, ve->engine->name);
> > + if (err)
> > + goto out_unpin;
> > +
> > + for (n = 0; n < num_gpr; n++) {
> > + struct intel_engine_cs *engine = siblings[n % nsibling];
> > + struct i915_request *rq;
> > + u32 *cs;
> > +
> > + rq = i915_request_create(ve);
> > + if (IS_ERR(rq)) {
> > + err = PTR_ERR(rq);
> > + goto out_end;
> > + }
> > +
> > + i915_request_put(last);
> > + last = i915_request_get(rq);
> > +
> > + cs = intel_ring_begin(rq, 8);
> > + if (IS_ERR(cs)) {
> > + i915_request_add(rq);
> > + err = PTR_ERR(cs);
> > + goto out_end;
> > + }
> > +
> > + *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
> > + *cs++ = CS_GPR(engine, n);
> > + *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);
> > + *cs++ = 0;
> > +
> > + *cs++ = MI_LOAD_REGISTER_IMM(1);
> > + *cs++ = CS_GPR(engine, (n + 1) % num_gpr);
> > + *cs++ = n + 1;
> > +
> > + *cs++ = MI_NOOP;
> > + intel_ring_advance(rq, cs);
> > +
> > + /* Restrict this request to run on a particular engine */
> > + rq->execution_mask = engine->mask;
> > + i915_request_add(rq);
> > + }
> > +
> > + if (i915_request_wait(last, 0, HZ / 5) < 0) {
> > + err = -ETIME;
> > + } else {
> > + u32 *map = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
> > +
> > + for (n = 0; n < num_gpr; n++) {
> > + if (map[n] != n) {
> > + pr_err("Incorrect value[%d] found for
> > GPR[%d]\n",
> > +map[n], n
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/3] drm/i915: Add microcontrollers documentation section
== Series Details ==
Series: series starting with [v2,1/3] drm/i915: Add microcontrollers
documentation section
URL : https://patchwork.freedesktop.org/series/67810/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046_full -> Patchwork_14740_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14740_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@perf_pmu@enable-race-vcs1:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][1] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/shard-tglb3/igt@perf_...@enable-race-vcs1.html
Known issues
Here are the changes found in Patchwork_14740_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [PASS][2] -> [DMESG-WARN][3] ([fdo#108566]) +4
similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-apl4/igt@gem_ctx_isolat...@bcs0-s3.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/shard-apl1/igt@gem_ctx_isolat...@bcs0-s3.html
* igt@gem_ctx_switch@all-light:
- shard-apl: [PASS][4] -> [INCOMPLETE][5] ([fdo#103927])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-apl3/igt@gem_ctx_swi...@all-light.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/shard-apl1/igt@gem_ctx_swi...@all-light.html
* igt@gem_eio@unwedge-stress:
- shard-snb: [PASS][6] -> [FAIL][7] ([fdo#109661])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-snb4/igt@gem_...@unwedge-stress.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/shard-snb5/igt@gem_...@unwedge-stress.html
* igt@gem_exec_schedule@independent-bsd:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#111325]) +1 similar issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb5/igt@gem_exec_sched...@independent-bsd.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/shard-iclb4/igt@gem_exec_sched...@independent-bsd.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-hsw: [PASS][10] -> [DMESG-WARN][11] ([fdo#111870])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-hsw1/igt@gem_userptr_bl...@sync-unmap-cycles.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/shard-hsw2/igt@gem_userptr_bl...@sync-unmap-cycles.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-hsw: [PASS][12] -> [INCOMPLETE][13] ([fdo#103540])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-hsw5/igt@kms_f...@2x-flip-vs-suspend.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/shard-hsw7/igt@kms_f...@2x-flip-vs-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][14] -> [FAIL][15] ([fdo#105363])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-skl4/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/shard-skl3/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
- shard-glk: [PASS][16] -> [FAIL][17] ([fdo#105363])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-glk9/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/shard-glk1/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-iclb: [PASS][18] -> [FAIL][19] ([fdo#103167]) +6 similar
issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [PASS][20] -> [SKIP][21] ([fdo#109441])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb2/igt@kms_psr@psr2_dpms.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/shard-iclb1/igt@kms_psr@psr2_dpms.html
* igt@perf@blocking:
- shard-skl: [PASS][22] -> [FAIL][23] ([fdo#110728])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-skl6/igt@p...@blocking.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14740/shard-skl7/igt@p...@blocking.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][24] -> [SKIP][25] ([fdo#109276]) +10 similar
issues
[24]:
https://i
Re: [Intel-gfx] [PATCH 07/24] drm/i915: Introduce intel_atomic_get_plane_state_after_check()
Op 10-10-2019 om 14:39 schreef Ville Syrjälä:
> On Thu, Oct 10, 2019 at 01:56:42PM +0200, Maarten Lankhorst wrote:
>> Op 08-10-2019 om 19:03 schreef Ville Syrjälä:
>>> On Fri, Oct 04, 2019 at 01:34:57PM +0200, Maarten Lankhorst wrote:
Use this in all the places where we try to acquire planes after the planes
atomic_check().
In case of intel_modeset_all_pipes() this is not yet done after
atomic_check,
but seems like it will be in the future. To add some paranoia, add all
planes
rather than active planes, because of bigjoiner and planar YUV support
having
extra planes outside of the core's view that wouldn't be added otherwise.
>>> If the plane isn't active what good does adding it do?
>>>
>>> Maybe the only real exception I can think of is the watermarks
>>> and the primary vs. gamma/csc_enable on pre-skl, but those are
>>> already handled correctly.
>> Planar YUV Y planes are not enumerated, so it's useful to add. Instead of
>> typing up special case support I thought it was easier to just add all
>> planes. On bigjoiner slave no planes are enabled either, even if they're
>> active.
> I think once we have the state split we should get rid of all the
> special casing of the Y planes. Then they (and the bigjoiner slave
> planes) should just look like an active planes which is not
> logically enabled by uapi.
With the plane split it's doable, even for watermarks, but prefer to do it
later on, not change the world too much. :)
There is no issue in the core with adding planes that are disabled, so I don't
see the problem?
~Maarten
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 41 +--
.../gpu/drm/i915/display/intel_atomic_plane.c | 19 +
drivers/gpu/drm/i915/display/intel_cdclk.c| 15 ---
drivers/gpu/drm/i915/display/intel_color.c| 7 ++--
.../drm/i915/display/intel_display_types.h| 6 +++
drivers/gpu/drm/i915/intel_pm.c | 14 ---
6 files changed, 66 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index c5a552a69752..e6cb85d41c8d 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -313,13 +313,10 @@ int intel_atomic_setup_scalers(struct
drm_i915_private *dev_priv,
struct intel_crtc *intel_crtc,
struct intel_crtc_state *crtc_state)
{
- struct drm_plane *plane = NULL;
- struct intel_plane *intel_plane;
- struct intel_plane_state *plane_state = NULL;
struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
struct drm_atomic_state *drm_state = crtc_state->base.state;
- struct intel_atomic_state *intel_state =
to_intel_atomic_state(drm_state);
+ struct intel_atomic_state *state = to_intel_atomic_state(drm_state);
int num_scalers_need;
int i;
@@ -346,6 +343,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv,
/* walkthrough scaler_users bits and start assigning scalers */
for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
+ struct intel_plane_state *plane_state = NULL;
int *scaler_id;
const char *name;
int idx;
@@ -361,19 +359,16 @@ int intel_atomic_setup_scalers(struct
drm_i915_private *dev_priv,
/* panel fitter case: assign as a crtc scaler */
scaler_id = &scaler_state->scaler_id;
} else {
- name = "PLANE";
+ struct intel_plane *plane;
/* plane scaler case: assign as a plane scaler */
/* find the plane that set the bit as scaler_user */
- plane = drm_state->planes[i].ptr;
/*
* to enable/disable hq mode, add planes that are using
scaler
* into this transaction
*/
- if (!plane) {
- struct drm_plane_state *state;
-
+ if (!drm_state->planes[i].ptr) {
/*
* GLK+ scalers don't have a HQ mode so it
* isn't necessary to change between HQ and dyn
mode
@@ -382,24 +377,28 @@ int intel_atomic_setup_scalers(struct
drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) >= 10 ||
IS_GEMINILAKE(dev_priv))
continue;
- plane = drm_plane_from_index(&dev_p
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Check that registers are preserved between virtual engines
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Check that registers are
preserved between virtual engines
URL : https://patchwork.freedesktop.org/series/67843/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7051 -> Patchwork_14747
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14747/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14747:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_selftest@live_gt_lrc}:
- fi-skl-6600u: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7051/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14747/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html
- fi-cfl-8109u: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7051/fi-cfl-8109u/igt@i915_selftest@live_gt_lrc.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14747/fi-cfl-8109u/igt@i915_selftest@live_gt_lrc.html
- fi-kbl-r: [PASS][5] -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7051/fi-kbl-r/igt@i915_selftest@live_gt_lrc.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14747/fi-kbl-r/igt@i915_selftest@live_gt_lrc.html
- fi-skl-6260u: [PASS][7] -> [DMESG-FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7051/fi-skl-6260u/igt@i915_selftest@live_gt_lrc.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14747/fi-skl-6260u/igt@i915_selftest@live_gt_lrc.html
- {fi-icl-u4}:[PASS][9] -> [DMESG-FAIL][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7051/fi-icl-u4/igt@i915_selftest@live_gt_lrc.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14747/fi-icl-u4/igt@i915_selftest@live_gt_lrc.html
- fi-skl-6770hq: [PASS][11] -> [DMESG-FAIL][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7051/fi-skl-6770hq/igt@i915_selftest@live_gt_lrc.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14747/fi-skl-6770hq/igt@i915_selftest@live_gt_lrc.html
- fi-cfl-guc: [PASS][13] -> [DMESG-FAIL][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7051/fi-cfl-guc/igt@i915_selftest@live_gt_lrc.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14747/fi-cfl-guc/igt@i915_selftest@live_gt_lrc.html
- fi-skl-lmem:[PASS][15] -> [DMESG-FAIL][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7051/fi-skl-lmem/igt@i915_selftest@live_gt_lrc.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14747/fi-skl-lmem/igt@i915_selftest@live_gt_lrc.html
- fi-skl-iommu: [PASS][17] -> [DMESG-FAIL][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7051/fi-skl-iommu/igt@i915_selftest@live_gt_lrc.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14747/fi-skl-iommu/igt@i915_selftest@live_gt_lrc.html
- fi-cfl-8700k: [PASS][19] -> [DMESG-FAIL][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7051/fi-cfl-8700k/igt@i915_selftest@live_gt_lrc.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14747/fi-cfl-8700k/igt@i915_selftest@live_gt_lrc.html
- fi-whl-u: [PASS][21] -> [DMESG-FAIL][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7051/fi-whl-u/igt@i915_selftest@live_gt_lrc.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14747/fi-whl-u/igt@i915_selftest@live_gt_lrc.html
- fi-skl-guc: [PASS][23] -> [DMESG-FAIL][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7051/fi-skl-guc/igt@i915_selftest@live_gt_lrc.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14747/fi-skl-guc/igt@i915_selftest@live_gt_lrc.html
- fi-kbl-7500u: [PASS][25] -> [DMESG-FAIL][26]
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7051/fi-kbl-7500u/igt@i915_selftest@live_gt_lrc.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14747/fi-kbl-7500u/igt@i915_selftest@live_gt_lrc.html
- fi-kbl-guc: [PASS][27] -> [DMESG-FAIL][28]
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7051/fi-kbl-guc/igt@i915_selftest@live_gt_lrc.html
[28]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14747/fi-kbl-guc/igt@i915_selftest@live_gt_lrc.html
- fi-kbl-8809g: [PASS][29] -> [DMESG-FAIL][30]
[29]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7051/fi-kbl-8809g/igt@i915_selftest@live_gt_lrc.html
[30]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14747/fi-kbl-8809g/igt@i915_selftest@live_gt_lrc.html
- fi
[Intel-gfx] [PATCH 1/2] drm/i915/selftests: Check known register values within the context
Check the logical ring context by asserting that the registers hold
expected start during execution. (It's a bit chicken-and-egg for how
could we manage to execute our request if the registers were not being
updated. Still, it's nice to verify that the HW is working as expected.)
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 138 +
1 file changed, 138 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index a691e429ca01..def1e64aaf1c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -2599,10 +2599,148 @@ static int live_lrc_layout(void *arg)
return err;
}
+static int __live_lrc_state(struct i915_gem_context *fixme,
+ struct intel_engine_cs *engine,
+ struct i915_vma *scratch)
+{
+ struct intel_context *ce;
+ struct i915_request *rq;
+ enum {
+ RING_START_IDX = 0,
+ RING_HEAD_IDX,
+ RING_TAIL_IDX,
+ MAX_IDX
+ };
+ u32 expected[MAX_IDX];
+ u32 *cs;
+ int err;
+ int n;
+
+ ce = intel_context_create(fixme, engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ err = intel_context_pin(ce);
+ if (err)
+ goto err_put;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_unpin;
+ }
+
+ expected[RING_HEAD_IDX] = ce->ring->emit;
+
+ cs = intel_ring_begin(rq, 4 * MAX_IDX);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ i915_request_add(rq);
+ goto err_unpin;
+ }
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base));
+ *cs++ = i915_ggtt_offset(scratch) + RING_START_IDX * sizeof(u32);
+ *cs++ = 0;
+
+ expected[RING_START_IDX] = i915_ggtt_offset(ce->ring->vma);
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(RING_HEAD(engine->mmio_base));
+ *cs++ = i915_ggtt_offset(scratch) + RING_HEAD_IDX * sizeof(u32);
+ *cs++ = 0;
+
+ expected[RING_HEAD_IDX] += 6 * sizeof(u32);
+ if (engine->class == RENDER_CLASS)
+ expected[RING_HEAD_IDX] += 2 * sizeof(u32);
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(RING_TAIL(engine->mmio_base));
+ *cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32);
+ *cs++ = 0;
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ intel_engine_flush_submission(engine);
+ expected[RING_TAIL_IDX] = ce->ring->tail;
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0) {
+ err = -ETIME;
+ goto err_rq;
+ }
+
+ cs = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err_rq;
+ }
+
+ for (n = 0; n < MAX_IDX; n++) {
+ if (cs[n] != expected[n]) {
+ pr_err("%s: Stored register[%d] value[0x%x] did not
match expected[0x%x]\n",
+ engine->name, n, cs[n], expected[n]);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_map(scratch->obj);
+
+err_rq:
+ i915_request_put(rq);
+err_unpin:
+ intel_context_unpin(ce);
+err_put:
+ intel_context_put(ce);
+ return err;
+}
+
+static int live_lrc_state(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ struct i915_gem_context *fixme;
+ struct i915_vma *scratch;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /*
+* Check the live register state matches what we expect for this
+* intel_context.
+*/
+
+ fixme = kernel_context(gt->i915);
+ if (!fixme)
+ return -ENOMEM;
+
+ scratch = create_scratch(gt);
+ if (IS_ERR(scratch)) {
+ err = PTR_ERR(scratch);
+ goto out_close;
+ }
+
+ for_each_engine(engine, gt->i915, id) {
+ err = __live_lrc_state(fixme, engine, scratch);
+ if (err)
+ break;
+ }
+
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+
+ i915_vma_unpin_and_release(&scratch, 0);
+out_close:
+ kernel_context_close(fixme);
+ return err;
+}
+
int intel_lrc_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_lrc_layout),
+ SUBTEST(live_lrc_state),
};
if (!HAS_LOGICAL_RING_CONTEXTS(i915))
--
2.23.0
___
[Intel-gfx] [PATCH 2/2] drm/i915/selftests: Check that GPR are cleared for new contexts
We want the general purpose registers to be clear in all new contexts so
that we can be confident that no information is leaked from one to the
next.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 185 ++---
1 file changed, 166 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index def1e64aaf1c..0f63016f91bc 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -19,6 +19,9 @@
#include "gem/selftests/igt_gem_utils.h"
#include "gem/selftests/mock_context.h"
+#define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
+#define NUM_GPR_DW (16 * 2) /* each GPR is 2 dwords */
+
static struct i915_vma *create_scratch(struct intel_gt *gt)
{
struct drm_i915_gem_object *obj;
@@ -2107,16 +2110,14 @@ static int preserved_virtual_engine(struct
drm_i915_private *i915,
struct intel_engine_cs **siblings,
unsigned int nsibling)
{
-#define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
-
struct i915_request *last = NULL;
struct i915_gem_context *ctx;
struct intel_context *ve;
struct i915_vma *scratch;
struct igt_live_test t;
- const int num_gpr = 16 * 2; /* each GPR is 2 dwords */
unsigned int n;
int err = 0;
+ u32 *cs;
ctx = kernel_context(i915);
if (!ctx)
@@ -2142,10 +2143,9 @@ static int preserved_virtual_engine(struct
drm_i915_private *i915,
if (err)
goto out_unpin;
- for (n = 0; n < num_gpr; n++) {
+ for (n = 0; n < NUM_GPR_DW; n++) {
struct intel_engine_cs *engine = siblings[n % nsibling];
struct i915_request *rq;
- u32 *cs;
rq = i915_request_create(ve);
if (IS_ERR(rq)) {
@@ -2169,7 +2169,7 @@ static int preserved_virtual_engine(struct
drm_i915_private *i915,
*cs++ = 0;
*cs++ = MI_LOAD_REGISTER_IMM(1);
- *cs++ = CS_GPR(engine, (n + 1) % num_gpr);
+ *cs++ = CS_GPR(engine, (n + 1) % NUM_GPR_DW);
*cs++ = n + 1;
*cs++ = MI_NOOP;
@@ -2182,21 +2182,26 @@ static int preserved_virtual_engine(struct
drm_i915_private *i915,
if (i915_request_wait(last, 0, HZ / 5) < 0) {
err = -ETIME;
- } else {
- u32 *map = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
+ goto out_end;
+ }
- for (n = 0; n < num_gpr; n++) {
- if (map[n] != n) {
- pr_err("Incorrect value[%d] found for
GPR[%d]\n",
- map[n], n);
- err = -EINVAL;
- break;
- }
- }
+ cs = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto out_end;
+ }
- i915_gem_object_unpin_map(scratch->obj);
+ for (n = 0; n < NUM_GPR_DW; n++) {
+ if (cs[n] != n) {
+ pr_err("Incorrect value[%d] found for GPR[%d]\n",
+ cs[n], n);
+ err = -EINVAL;
+ break;
+ }
}
+ i915_gem_object_unpin_map(scratch->obj);
+
out_end:
if (igt_live_test_end(&t))
err = -EIO;
@@ -2210,8 +2215,6 @@ static int preserved_virtual_engine(struct
drm_i915_private *i915,
out_close:
kernel_context_close(ctx);
return err;
-
-#undef CS_GPR
}
static int live_virtual_preserved(void *arg)
@@ -2736,11 +2739,155 @@ static int live_lrc_state(void *arg)
return err;
}
+static int gpr_make_dirty(struct intel_engine_cs *engine)
+{
+ struct i915_request *rq;
+ u32 *cs;
+ int n;
+
+ rq = i915_request_create(engine->kernel_context);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ cs = intel_ring_begin(rq, 2 * NUM_GPR_DW + 2);
+ if (IS_ERR(cs)) {
+ i915_request_add(rq);
+ return PTR_ERR(cs);
+ }
+
+ *cs++ = MI_LOAD_REGISTER_IMM(NUM_GPR_DW);
+ for (n = 0; n < NUM_GPR_DW; n++) {
+ *cs++ = CS_GPR(engine, n);
+ *cs++ = STACK_MAGIC;
+ }
+ *cs++ = MI_NOOP;
+
+ intel_ring_advance(rq, cs);
+ i915_request_add(rq);
+
+ return 0;
+}
+
+static int __live_gpr_clear(struct i915_gem_context *fixme,
+ struct intel_engine_cs *engine,
+ struct i915_vma *scratch)
+{
+ struct intel_context *ce;
+ struct i915_request *rq;
+ u32 *cs;
+ int err;
+ int n;
+
+ if (INTEL_G
Re: [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Check that GPR are cleared for new contexts
Quoting Chris Wilson (2019-10-10 14:15:21)
> +static int __live_gpr_clear(struct i915_gem_context *fixme,
> + struct intel_engine_cs *engine,
> + struct i915_vma *scratch)
> +{
> + struct intel_context *ce;
> + struct i915_request *rq;
> + u32 *cs;
> + int err;
> + int n;
> +
> + if (INTEL_GEN(engine->i915) < 8 && engine->class != RENDER_CLASS)
> + return 0; /* GPR only on rcs0 for gen8 */
Nice comment, shame about the code.
I'll wait to make sure that this does indeed fail on Broadwell.
-Chris
___
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Re: [Intel-gfx] Does the i915 VBT tell us if a panel is an OLED panel?
On Thu, 10 Oct 2019, Hans de Goede wrote: > Hi Jani, > > During plumbers I had some discussions with Daniel about supporting > OLED screens. Userspace may need to know that a panel is OLED for 2 > reasons: > > 1) To avoid screen burn-in > 2) OLED screens do not have a classic backlight, so in some cases > some sort of brightness/contrast emulation through gamma tables may > be necessary to still allow the user to control the brightness. I'd think most OLED displays have a native way to control brightness. Some eDP panels can use the eDP PWM pin to control brightness, although it does not directly drive an actual backlight, and some others use the eDP standard DPCD brightness control methods. Similarly, OLED DSI displays have DCS commands for this. Often I've seen various content adaptive brightness settings combined with the OLED brightness control, so it can be more power efficient than using gamma. > The idea we've discussed is to add a property on the drm_connector > (details to be filled in) which indicates that the panel is an OLED > panel. > > This has lead to the question: "how do we know the panel is OLED"? > > Do you know if this info is coded into the VBT somewhere? Not AFAICT. But there is the indication of the brightness control method, and one option is the eDP AUX interface. I fathom it's entirely possible for panels to use the eDP AUX interface for controlling an LCD backlight, so this does not directly translate to OLED. However, the DisplayID spec has Display Device Data block (0x0c) that contains Display Device Technology byte, including a value for Organic LED/OEL. I haven't actually checked any OLED displays if they have this or not, and we don't currently parse it in drm, but this seems like a better option than VBT. Moreover, this is usable also for regular DP, which should be as important as eDP for the burn-in avoidance. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/dp-mst: Drop connection_mutex check
On Wed, Oct 09, 2019 at 06:46:38PM -0400, Lyude Paul wrote:
> oh, completely forgot about this one
>
> Reviewed-by: Lyude Paul
Thanks for your review, applied to drm-misc-next.
-Daniel
>
> On Thu, 2019-10-10 at 00:41 +0200, Daniel Vetter wrote:
> > Private atomic objects have grown their own locking with
> >
> > commit b962a12050a387e4bbf3a48745afe1d29d396b0d
> > Author: Rob Clark
> > Date: Mon Oct 22 14:31:22 2018 +0200
> >
> > drm/atomic: integrate modeset lock with private objects
> >
> > which means we're no longer relying on connection_mutex for mst state
> > locking needs.
> >
> > Cc: Lyude Paul
> > Cc: Sean Paul
> > Signed-off-by: Daniel Vetter
> > ---
> > drivers/gpu/drm/drm_dp_mst_topology.c | 1 -
> > 1 file changed, 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> > b/drivers/gpu/drm/drm_dp_mst_topology.c
> > index 6b14b63b8d62..9364e4f42975 100644
> > --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> > @@ -4186,7 +4186,6 @@ struct drm_dp_mst_topology_state
> > *drm_atomic_get_mst_topology_state(struct drm_a
> > {
> > struct drm_device *dev = mgr->dev;
> >
> > - WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
> > return
> > to_dp_mst_topology_state(drm_atomic_get_private_obj_state(state, &mgr-
> > >base));
> > }
> > EXPORT_SYMBOL(drm_atomic_get_mst_topology_state);
> --
> Cheers,
> Lyude Paul
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/vbt: Handle generic DTD block
== Series Details == Series: drm/i915/vbt: Handle generic DTD block URL : https://patchwork.freedesktop.org/series/67811/ State : success == Summary == CI Bug Log - changes from CI_DRM_7046_full -> Patchwork_14741_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14741_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276]) +20 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb4/igt@gem_exec_sched...@independent-bsd2.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/shard-iclb6/igt@gem_exec_sched...@independent-bsd2.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb7/igt@gem_exec_sched...@reorder-wide-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/shard-iclb4/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-skl4/igt@gem_soft...@noreloc-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/shard-skl1/igt@gem_soft...@noreloc-s3.html * igt@gem_tiled_swapping@non-threaded: - shard-apl: [PASS][7] -> [DMESG-FAIL][8] ([fdo#108686]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-apl3/igt@gem_tiled_swapp...@non-threaded.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/shard-apl4/igt@gem_tiled_swapp...@non-threaded.html - shard-hsw: [PASS][9] -> [INCOMPLETE][10] ([fdo#103540] / [fdo#108686]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-hsw2/igt@gem_tiled_swapp...@non-threaded.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/shard-hsw5/igt@gem_tiled_swapp...@non-threaded.html * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup: - shard-hsw: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-hsw1/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/shard-hsw1/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-apl4/igt@gem_workarou...@suspend-resume-context.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/shard-apl1/igt@gem_workarou...@suspend-resume-context.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html * igt@kms_psr@psr2_dpms: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb2/igt@kms_psr@psr2_dpms.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/shard-iclb7/igt@kms_psr@psr2_dpms.html * igt@perf_pmu@cpu-hotplug: - shard-glk: [PASS][19] -> [TIMEOUT][20] ([fdo#111800]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-glk5/igt@perf_...@cpu-hotplug.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/shard-glk5/igt@perf_...@cpu-hotplug.html Possible fixes * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [SKIP][21] ([fdo#109276]) -> [PASS][22] +16 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb7/igt@gem_exec_sched...@preempt-queue-bsd1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/shard-iclb1/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_exec_schedule@wide-bsd: - shard-iclb: [SKIP][23] ([fdo#111325]) -> [PASS][24] +4 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7046/shard-iclb4/igt@gem_exec_sched...@wide-bsd.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14741/shard-iclb6/igt@gem_exec_sched...@wide-bsd.html * igt@gem_userptr_blits@sync-unmap-after-close: - shard-hsw: [DMESG-WARN][25] ([fdo#111870]) -> [PASS][26] +1 similar issue [25]: https://int
[Intel-gfx] [PATCH] drm/i915: Honour O_NONBLOCK before throttling execbuf submissions
Check the user's flags on the struct file before deciding whether or not
to stall before submitting a request. This allows us to reasonably
cheaply honour O_NONBLOCK without checking at more critical phases
during request submission.
Suggested-by: Joonas Lahtinen
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 21 ---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 98816c35ffc3..bc6bcb8f6d79 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2189,15 +2189,22 @@ static int __eb_pin_engine(struct i915_execbuffer *eb,
struct intel_context *ce)
intel_context_timeline_unlock(tl);
if (rq) {
- if (i915_request_wait(rq,
- I915_WAIT_INTERRUPTIBLE,
- MAX_SCHEDULE_TIMEOUT) < 0) {
- i915_request_put(rq);
- err = -EINTR;
- goto err_exit;
- }
+ bool nonblock = eb->file->filp->f_flags & O_NONBLOCK;
+ long timeout;
+
+ timeout = MAX_SCHEDULE_TIMEOUT;
+ if (nonblock)
+ timeout = 0;
+ timeout = i915_request_wait(rq,
+ I915_WAIT_INTERRUPTIBLE,
+ timeout);
i915_request_put(rq);
+
+ if (timeout < 0) {
+ err = nonblock ? -EWOULDBLOCK : timeout;
+ goto err_exit;
+ }
}
eb->engine = ce->engine;
--
2.23.0
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Re: [Intel-gfx] [PATCH] drm/i915: Honour O_NONBLOCK before throttling execbuf submissions
Quoting Chris Wilson (2019-10-10 14:48:49) > Check the user's flags on the struct file before deciding whether or not > to stall before submitting a request. This allows us to reasonably > cheaply honour O_NONBLOCK without checking at more critical phases > during request submission. One might reasonably expect poll(POLLOUT) to be supported as well in this case :| Bring on ugpu. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 04/24] drm/i915: Remove cursor use of properties for coordinates
Op 07-10-2019 om 21:37 schreef Matt Roper: > On Fri, Oct 04, 2019 at 01:34:54PM +0200, Maarten Lankhorst wrote: >> We have a src and dect rectangle, use it instead of relying on >> the core drm properties. >> >> This removes the special case in the watermark code for cursor w/h. >> >> Signed-off-by: Maarten Lankhorst > I think you should make it more clear in the commit message here that > you're actually overwriting the clipped coordinates in src/dst with the > unclipped coordinates that we program into our hardware. I missed that > the first time reading through the patch; using clipped coordinates > would obviously cause lots of failures. > > Actually, even if this is safe at the moment, we're violating the > documented expectations of the DRM core. I'd suggest also adding a drm > core patch that updates the comment on drm_plane_state to indicate that > the contents may or may not be clipped (driver-specific) and that the > core shouldn't assume either way. Updated the core's expectations, to explicitly allow the unclipped coordinates, and pushed patch 2-6 with the feedback. Thanks for reviews all. :) ~Maarten ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/24] drm/i915: Prepare to split crtc state in uapi and hw state
Op 08-10-2019 om 19:06 schreef Ville Syrjälä:
> On Fri, Oct 04, 2019 at 01:34:58PM +0200, Maarten Lankhorst wrote:
>> We want to split drm_crtc_state into the user visible state
>> and actual hardware state. To prepare for this, we need some
>> ground rules what should be in each state:
>>
>> In uapi we use:
>> - crtc, *_changed flags, event, commit, state, mode_blob,
>> (plane/connector/encoder)_mask.
>>
>> In hw state we use what's displayed in hardware:
>> - enable, active, (adjusted) mode, color property blobs.
>>
>> clear_intel_crtc_state and hw readout need to be updated for these rules,
>> which will allow us to enable 2 joined pipes.
> I still have hard time with reading this patch. I still think it
> would be easier to read if we didn't do both the "uapi" and "hw" changes
> at the same time.
>
> step 1.
> struct drm_crtc_state uapi;
> struct {
> // hw state
> } base;
>
> step 2.
> s/base/hw/
>
> I think that would make it more obvious which parts of the code are
> looking at which state.
It wouldn't I think, but here's
a dumb change with spatch on this patch.
//+ struct {
//+ bool active, enable;
//+ struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
//+ struct drm_display_mode mode, adjusted_mode;
//+ } hw;
@@
struct intel_crtc_state *T;
@@
-T->uapi.active
+T->hw.active
@@
struct intel_crtc_state *T;
@@
-T->uapi.enable
+T->hw.enable
@@
struct intel_crtc_state *T;
@@
-T->uapi.degamma_lut
+T->hw.degamma_lut
@@
struct intel_crtc_state *T;
@@
-T->uapi.gamma_lut
+T->hw.gamma_lut
@@
struct intel_crtc_state *T;
@@
-T->uapi.ctm
+T->hw.ctm
@@
struct intel_crtc_state *T;
@@
-T->uapi.mode
+T->hw.mode
@@
struct intel_crtc_state *T;
@@
-T->uapi.adjusted_mode
+T->hw.adjusted_mode
I replaced all the instances where we use the uapi members instead of the hw
members explicitly in this patch, and came up with the following diff below.
Only the intel_color readout is potentially incorrect, the 2 explicit uapi uses
in intel_display.c are needed.
Didn't fix it because of hw readout, it possibly needs slightly more thought.
Does this satisfy the readability requirements? :)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ab10c33266bf..cbf4c6e6e661 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11217,7 +11217,7 @@ int intel_get_load_detect_pipe(struct drm_connector
*connector,
goto fail;
}
- crtc_state->uapi.active = crtc_state->uapi.enable = true;
+ crtc_state->hw.active = crtc_state->hw.enable = true;
if (!mode)
mode = &load_detect_mode;
@@ -13578,7 +13578,7 @@ static int intel_atomic_check(struct drm_device *dev,
if (!needs_modeset(new_crtc_state))
continue;
- if (!new_crtc_state->uapi.enable) {
+ if (!new_crtc_state->hw.enable) {
any_ms = true;
continue;
}
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 5586891572f8..52712bb9ed15 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1623,7 +1623,7 @@ static void i9xx_read_luts(struct intel_crtc_state
*crtc_state)
if (!crtc_state->gamma_enable)
return;
- crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
+ crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
}
static struct drm_property_blob *
@@ -1673,9 +1673,9 @@ static void i965_read_luts(struct intel_crtc_state
*crtc_state)
return;
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
- crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
+ crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
else
- crtc_state->uapi.gamma_lut = i965_read_lut_10p6(crtc_state);
+ crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc_state);
}
static struct drm_property_blob *
@@ -1715,7 +1715,7 @@ chv_read_cgm_lut(const struct intel_crtc_state
*crtc_state)
static void chv_read_luts(struct intel_crtc_state *crtc_state)
{
if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
- crtc_state->uapi.gamma_lut = chv_read_cgm_lut(crtc_state);
+ crtc_state->hw.gamma_lut = chv_read_cgm_lut(crtc_state);
else
i965_read_luts(crtc_state);
}
@@ -1762,9 +1762,9 @@ static void ilk_read_luts(struct intel_crtc_state
*crtc_state)
return;
if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
- crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
+ crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
else
- crtc_stat
[Intel-gfx] [PATCH] RFC drm/i915: Allow userspace to specify ringsize on construction
No good reason why we must always use a static ringsize, so let
userspace select one during construction.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 83 +++--
include/uapi/drm/i915_drm.h | 12 +++
2 files changed, 89 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 46e5b3b53288..9635e377c8ae 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -455,23 +455,30 @@ __create_context(struct drm_i915_private *i915)
return ERR_PTR(err);
}
-static void
+static int
context_apply_all(struct i915_gem_context *ctx,
- void (*fn)(struct intel_context *ce, void *data),
+ int (*fn)(struct intel_context *ce, void *data),
void *data)
{
struct i915_gem_engines_iter it;
struct intel_context *ce;
+ int err = 0;
- for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it)
- fn(ce, data);
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+ err = fn(ce, data);
+ if (err)
+ break;
+ }
i915_gem_context_unlock_engines(ctx);
+
+ return err;
}
-static void __apply_ppgtt(struct intel_context *ce, void *vm)
+static int __apply_ppgtt(struct intel_context *ce, void *vm)
{
i915_vm_put(ce->vm);
ce->vm = i915_vm_get(vm);
+ return 0;
}
static struct i915_address_space *
@@ -509,9 +516,10 @@ static void __set_timeline(struct intel_timeline **dst,
intel_timeline_put(old);
}
-static void __apply_timeline(struct intel_context *ce, void *timeline)
+static int __apply_timeline(struct intel_context *ce, void *timeline)
{
__set_timeline(&ce->timeline, timeline);
+ return 0;
}
static void __assign_timeline(struct i915_gem_context *ctx,
@@ -1086,6 +1094,65 @@ static int set_ppgtt(struct drm_i915_file_private
*file_priv,
return err;
}
+static int __apply_ringsize(struct intel_context *ce, void *sz)
+{
+ int err = 0;
+
+ if (intel_context_lock_pinned(ce))
+ return -EINTR;
+
+ if (intel_context_is_pinned(ce)) {
+ err = -EBUSY; /* In active use! Come back later! */
+ goto unlock;
+ }
+
+ if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
+ struct intel_ring *ring;
+
+ /* Replace the existing ringbuffer */
+ ring = intel_engine_create_ring(ce->engine,
+ (unsigned long)sz);
+ if (IS_ERR(ring)) {
+ err = PTR_ERR(ring);
+ goto unlock;
+ }
+
+ intel_ring_put(ce->ring);
+ ce->ring = ring;
+
+ /* Context image will be updated on next pin */
+ } else {
+ ce->ring = sz;
+ }
+
+unlock:
+ intel_context_unlock_pinned(ce);
+ return err;
+}
+
+static int set_ringsize(struct i915_gem_context *ctx,
+ struct drm_i915_gem_context_param *args)
+{
+ if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915))
+ return -ENODEV;
+
+ if (args->size)
+ return -EINVAL;
+
+ if (!IS_ALIGNED(args->value, I915_GTT_PAGE_SIZE))
+ return -EINVAL;
+
+ if (args->value < I915_GTT_PAGE_SIZE)
+ return -EINVAL;
+
+ if (args->value > 128 * I915_GTT_PAGE_SIZE)
+ return -EINVAL;
+
+ return context_apply_all(ctx,
+__apply_ringsize,
+__intel_context_ring_size(args->value));
+}
+
static int gen8_emit_rpcs_config(struct i915_request *rq,
struct intel_context *ce,
struct intel_sseu sseu)
@@ -1798,6 +1865,10 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
ret = set_persistence(ctx, args);
break;
+ case I915_CONTEXT_PARAM_RINGSIZE:
+ ret = set_ringsize(ctx, args);
+ break;
+
case I915_CONTEXT_PARAM_BAN_PERIOD:
default:
ret = -EINVAL;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index eb9e704d717a..e375cd2cf66b 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1580,6 +1580,18 @@ struct drm_i915_gem_context_param {
* By default, new contexts allow persistence.
*/
#define I915_CONTEXT_PARAM_PERSISTENCE 0xb
+
+/*
+ *
+ * I915_CONTEXT_PARAM_RINGSIZE:
+ *
+ * Sets the size of the ringbuffer to use for logical ring contexts.
+ * Only possible to be set prior to first use, i.e. during construction.
+ * Only applies to the current set of engine and lost for those engines
+ * are repla
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave and Daniel, This pull request includes the ones we missed for -rc1 drm-intel-next-fixes-2019-09-26 & drm-intel-next-fixes-2019-09-19 plus few fixes for execlists requests and CML display. Here goes drm-intel-fixes-2019-10-10: - Fix CML display by adding a missing ID. - Drop redundant list_del_init - Only enqueue already completed requests to avoid races - Fixup preempt-to-busy vs reset of a virtual request - Protect peeking at execlists->active - execlists->active is serialised by the tasklet drm-intel-next-fixes-2019-09-19: - Extend old HSW workaround to fix some GPU hangs on Haswell GT2 - Fix return error code on GEM mmap. - White list a chicken bit register for push constants legacy mode on Mesa - Fix resume issue related to GGTT restore - Remove incorrect BUG_ON on execlist's schedule-out - Fix unrecoverable GPU hangs with Vulkan compute workloads on SKL drm-intel-next-fixes-2019-09-26: - Fix concurrence on cases where requests where getting retired at same time as resubmitted to HW - Fix gen9 display resolutions by setting the right max plane width - Fix GPU hang on preemption - Mark contents as dirty on a write fault. This was breaking cursor sprite with dumb buffers. Thanks, Rodrigo. The following changes since commit da0c9ea146cbe92b832f1b0f694840ea8eb33cce: Linux 5.4-rc2 (2019-10-06 14:27:30 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2019-10-10 for you to fetch changes up to e137d3abdfca0fb6fc270da576a9d9d6a1f8d8b3: drm/i915/gt: execlists->active is serialised by the tasklet (2019-10-09 14:39:31 -0700) - Fix CML display by adding a missing ID. - Drop redundant list_del_init - Only enqueue already completed requests to avoid races - Fixup preempt-to-busy vs reset of a virtual request - Protect peeking at execlists->active - execlists->active is serialised by the tasklet drm-intel-next-fixes-2019-09-19: - Extend old HSW workaround to fix some GPU hangs on Haswell GT2 - Fix return error code on GEM mmap. - White list a chicken bit register for push constants legacy mode on Mesa - Fix resume issue related to GGTT restore - Remove incorrect BUG_ON on execlist's schedule-out - Fix unrecoverable GPU hangs with Vulkan compute workloads on SKL drm-intel-next-fixes-2019-09-26: - Fix concurrence on cases where requests where getting retired at same time as resubmitted to HW - Fix gen9 display resolutions by setting the right max plane width - Fix GPU hang on preemption - Mark contents as dirty on a write fault. This was breaking cursor sprite with dumb buffers. Chris Wilson (12): drm/i915/execlists: Remove incorrect BUG_ON for schedule-out drm/i915: Perform GGTT restore much earlier during resume drm/i915: Don't mix srcu tag and negative error codes drm/i915: Extend Haswell GT1 PSMI workaround to all drm/i915: Verify the engine after acquiring the active.lock drm/i915: Prevent bonded requests from overtaking each other on preemption drm/i915: Mark contents as dirty on a write fault drm/i915/execlists: Drop redundant list_del_init(&rq->sched.link) drm/i915: Only enqueue already completed requests drm/i915: Fixup preempt-to-busy vs reset of a virtual request drm/i915/execlists: Protect peeking at execlists->active drm/i915/gt: execlists->active is serialised by the tasklet Kenneth Graunke (1): drm/i915: Whitelist COMMON_SLICE_CHICKEN2 Matt Roper (1): drm/i915/cml: Add second PCH ID for CMP Ville Syrjälä (1): drm/i915: Bump skl+ max plane width to 5k for linear/x-tiled drivers/gpu/drm/i915/display/intel_display.c | 15 +++- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 12 ++-- drivers/gpu/drm/i915/gem/i915_gem_pm.c | 3 - drivers/gpu/drm/i915/gt/intel_engine.h | 14 drivers/gpu/drm/i915/gt/intel_engine_cs.c| 16 ++--- drivers/gpu/drm/i915/gt/intel_lrc.c | 101 +-- drivers/gpu/drm/i915/gt/intel_reset.c| 12 ++-- drivers/gpu/drm/i915/gt/intel_reset.h| 2 +- drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 + drivers/gpu/drm/i915/i915_drv.c | 5 ++ drivers/gpu/drm/i915/i915_gem.h | 6 ++ drivers/gpu/drm/i915/i915_request.c | 69 ++ drivers/gpu/drm/i915/i915_request.h | 2 +- drivers/gpu/drm/i915/intel_pch.c | 1 + drivers/gpu/drm/i915/intel_pch.h | 1 + drivers/gpu/drm/i915/selftests/i915_gem.c| 6 ++ 17 files changed, 188 insertions(+), 82 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/24] drm/i915: Prepare to split crtc state in uapi and hw state
On Thu, Oct 10, 2019 at 04:21:00PM +0200, Maarten Lankhorst wrote:
> Op 08-10-2019 om 19:06 schreef Ville Syrjälä:
> > On Fri, Oct 04, 2019 at 01:34:58PM +0200, Maarten Lankhorst wrote:
> >> We want to split drm_crtc_state into the user visible state
> >> and actual hardware state. To prepare for this, we need some
> >> ground rules what should be in each state:
> >>
> >> In uapi we use:
> >> - crtc, *_changed flags, event, commit, state, mode_blob,
> >> (plane/connector/encoder)_mask.
> >>
> >> In hw state we use what's displayed in hardware:
> >> - enable, active, (adjusted) mode, color property blobs.
> >>
> >> clear_intel_crtc_state and hw readout need to be updated for these rules,
> >> which will allow us to enable 2 joined pipes.
> > I still have hard time with reading this patch. I still think it
> > would be easier to read if we didn't do both the "uapi" and "hw" changes
> > at the same time.
> >
> > step 1.
> > struct drm_crtc_state uapi;
> > struct {
> > // hw state
> > } base;
> >
> > step 2.
> > s/base/hw/
> >
> > I think that would make it more obvious which parts of the code are
> > looking at which state.
>
> It wouldn't I think, but here's
> a dumb change with spatch on this patch.
>
> //+ struct {
> //+ bool active, enable;
> //+ struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
> //+ struct drm_display_mode mode, adjusted_mode;
> //+ } hw;
>
> @@
> struct intel_crtc_state *T;
> @@
> -T->uapi.active
> +T->hw.active
This doesn't really help me. There is no .uapi in upstream
code. I would like to see just the .base->.uapi changes
alone first so I can review which parts start to look at
the uapi state to make sure we aren't changing too much.
Then I'd like to to see the .base->.hw changes so that I
convince myself we didn't miss anything in the .base->.uapi
conversion.
And all the remaining drm_crtc_state usage is going to
make us miss something for sure, so getting rid of all that
first would probably help.
>
> @@
> struct intel_crtc_state *T;
> @@
> -T->uapi.enable
> +T->hw.enable
>
> @@
> struct intel_crtc_state *T;
> @@
> -T->uapi.degamma_lut
> +T->hw.degamma_lut
>
>
> @@
> struct intel_crtc_state *T;
> @@
> -T->uapi.gamma_lut
> +T->hw.gamma_lut
>
> @@
> struct intel_crtc_state *T;
> @@
> -T->uapi.ctm
> +T->hw.ctm
>
> @@
> struct intel_crtc_state *T;
> @@
> -T->uapi.mode
> +T->hw.mode
>
> @@
> struct intel_crtc_state *T;
> @@
> -T->uapi.adjusted_mode
> +T->hw.adjusted_mode
>
> I replaced all the instances where we use the uapi members instead of the hw
> members explicitly in this patch, and came up with the following diff below.
>
> Only the intel_color readout is potentially incorrect, the 2 explicit uapi
> uses in intel_display.c are needed.
> Didn't fix it because of hw readout, it possibly needs slightly more thought.
>
> Does this satisfy the readability requirements? :)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index ab10c33266bf..cbf4c6e6e661 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11217,7 +11217,7 @@ int intel_get_load_detect_pipe(struct drm_connector
> *connector,
> goto fail;
> }
>
> - crtc_state->uapi.active = crtc_state->uapi.enable = true;
> + crtc_state->hw.active = crtc_state->hw.enable = true;
>
> if (!mode)
> mode = &load_detect_mode;
> @@ -13578,7 +13578,7 @@ static int intel_atomic_check(struct drm_device *dev,
> if (!needs_modeset(new_crtc_state))
> continue;
>
> - if (!new_crtc_state->uapi.enable) {
> + if (!new_crtc_state->hw.enable) {
> any_ms = true;
> continue;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 5586891572f8..52712bb9ed15 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1623,7 +1623,7 @@ static void i9xx_read_luts(struct intel_crtc_state
> *crtc_state)
> if (!crtc_state->gamma_enable)
> return;
>
> - crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
> + crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
> }
>
> static struct drm_property_blob *
> @@ -1673,9 +1673,9 @@ static void i965_read_luts(struct intel_crtc_state
> *crtc_state)
> return;
>
> if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> - crtc_state->uapi.gamma_lut = i9xx_read_lut_8(crtc_state);
> + crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
> else
> - crtc_state->uapi.gamma_lut = i965_read_lut_10p6(crtc_state);
> + crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc_state);
> }
>
> st
[Intel-gfx] [PATCH 2/5] drm/i915: s/hdcp2_hdmi_msg_data/hdcp2_hdmi_msg_timeout/
From: Ville Syrjälä
The array is there only for timeout, "data" doesn't mean anything
so let's rename the thing to be more descriptive.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0a6846c5ba95..13c588ae88a4 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1527,13 +1527,13 @@ bool intel_hdmi_hdcp_check_link(struct
intel_digital_port *intel_dig_port)
return true;
}
-struct hdcp2_hdmi_msg_data {
+struct hdcp2_hdmi_msg_timeout {
u8 msg_id;
u32 timeout;
u32 timeout2;
};
-static const struct hdcp2_hdmi_msg_data hdcp2_msg_data[] = {
+static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
{ HDCP_2_2_AKE_INIT, 0, 0 },
{ HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
{ HDCP_2_2_AKE_NO_STORED_KM, 0, 0 },
@@ -1564,12 +1564,12 @@ static int get_hdcp2_msg_timeout(u8 msg_id, bool
is_paired)
{
int i;
- for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++)
- if (hdcp2_msg_data[i].msg_id == msg_id &&
+ for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++)
+ if (hdcp2_msg_timeout[i].msg_id == msg_id &&
(msg_id != HDCP_2_2_AKE_SEND_HPRIME || is_paired))
- return hdcp2_msg_data[i].timeout;
- else if (hdcp2_msg_data[i].msg_id == msg_id)
- return hdcp2_msg_data[i].timeout2;
+ return hdcp2_msg_timeout[i].timeout;
+ else if (hdcp2_msg_timeout[i].msg_id == msg_id)
+ return hdcp2_msg_timeout[i].timeout2;
return -EINVAL;
}
--
2.21.0
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[Intel-gfx] [PATCH 1/5] drm/i915: Shrink eDRAM ways/sets arrays
From: Ville Syrjälä
Make the ways/sets arrays static cosnt u8 to shrink things a bit.
text data bss dec hex filename
- 23935629 128 246926074 i915_drv.o
+ 23818629 128 245755fff i915_drv.o
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f02a34722217..0b8c13ae4857 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1073,8 +1073,8 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap)
{
- const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
- const unsigned int sets[4] = { 1, 1, 2, 2 };
+ static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
+ static const u8 sets[4] = { 1, 1, 2, 2 };
return EDRAM_NUM_BANKS(cap) *
ways[EDRAM_WAYS_IDX(cap)] *
--
2.21.0
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[Intel-gfx] [PATCH 3/5] drm/i915: Remove dead weight from hdcp2_msg_timeout[]
From: Ville Syrjälä
The .read_2_2() hooks is never called for any of the message
types with a zero timeout. So it's all just dead weight which
we can chuck.
text data bss dec hex filename
- 34701360 0 3506188f5 intel_hdmi.o
+ 34633360 0 3499388b1 intel_hdmi.o
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 13c588ae88a4..8a574be86bc6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1534,19 +1534,12 @@ struct hdcp2_hdmi_msg_timeout {
};
static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
- { HDCP_2_2_AKE_INIT, 0, 0 },
{ HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
- { HDCP_2_2_AKE_NO_STORED_KM, 0, 0 },
- { HDCP_2_2_AKE_STORED_KM, 0, 0 },
{ HDCP_2_2_AKE_SEND_HPRIME, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
{ HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
- { HDCP_2_2_LC_INIT, 0, 0 },
{ HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, 0 },
- { HDCP_2_2_SKE_SEND_EKS, 0, 0 },
{ HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
- { HDCP_2_2_REP_SEND_ACK, 0, 0 },
- { HDCP_2_2_REP_STREAM_MANAGE, 0, 0 },
{ HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
};
--
2.21.0
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[Intel-gfx] [PATCH 5/5] drm/i915: Make hdcp2_msg_timeout.timeout u16
From: Ville Syrjälä
All the timeout values fit in u16, so let's shrink the structure
a bit.
This ends up actually increasing the .text size a bit due to
some changes in instructions (constant imul+small jmps replaced
with mov+bigger jmpqs). Seems pretty arbitrary to me so I'll
just pretend I didn't see it.
text data bss dec hex filename
- 34521360 0 348818841 intel_hdmi.o
+ 34537360 0 348978851 intel_hdmi.o
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 2dd798d8b961..5e97df38d281 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1529,7 +1529,7 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port
*intel_dig_port)
struct hdcp2_hdmi_msg_timeout {
u8 msg_id;
- u32 timeout;
+ u16 timeout;
};
static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
--
2.21.0
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[Intel-gfx] [PATCH 4/5] drm/i915: Remove hdcp2_hdmi_msg_timeout.timeout2
From: Ville Syrjälä
The only reason for the timeout2 value in the array is the
HDCP_2_2_AKE_SEND_HPRIME message. But that one still needs
special casing inside the loop, and so just ends up making
the code harder to read. Let's just remove this leaky
timeout2 abstraction and special case that one command
in a way that is easy to understand. We can then remove the
timeout2 member from struct entirely.
text data bss dec hex filename
- 34633360 0 3499388b1 intel_hdmi.o
+ 34521360 0 348818841 intel_hdmi.o
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 28 ---
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 8a574be86bc6..2dd798d8b961 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1530,17 +1530,14 @@ bool intel_hdmi_hdcp_check_link(struct
intel_digital_port *intel_dig_port)
struct hdcp2_hdmi_msg_timeout {
u8 msg_id;
u32 timeout;
- u32 timeout2;
};
static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
- { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
- { HDCP_2_2_AKE_SEND_HPRIME, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
- HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
- { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
- { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, 0 },
- { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
- { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
+ { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
+ { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
+ { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
+ { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
+ { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
};
static
@@ -1557,12 +1554,17 @@ static int get_hdcp2_msg_timeout(u8 msg_id, bool
is_paired)
{
int i;
- for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++)
- if (hdcp2_msg_timeout[i].msg_id == msg_id &&
- (msg_id != HDCP_2_2_AKE_SEND_HPRIME || is_paired))
+ if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
+ if (is_paired)
+ return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
+ else
+ return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
+ if (hdcp2_msg_timeout[i].msg_id == msg_id)
return hdcp2_msg_timeout[i].timeout;
- else if (hdcp2_msg_timeout[i].msg_id == msg_id)
- return hdcp2_msg_timeout[i].timeout2;
+ }
return -EINVAL;
}
--
2.21.0
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/perf: store the associated engine of a stream
On 10/10/2019 10:27, Chris Wilson wrote:
From: Lionel Landwerlin
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine. For now, we want to
pull the knowledge of which engine we use into a central property.
Signed-off-by: Lionel Landwerlin
Your changes look fine :
Reviewed-by: Lionel Landwerlin
Thanks!
---
drivers/gpu/drm/i915/i915_perf.c | 30 ++
drivers/gpu/drm/i915/i915_perf_types.h | 5 +
2 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 5a34cad7d824..1a5c6591b9bb 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -197,6 +197,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_pm.h"
+#include "gt/intel_engine_user.h"
#include "gt/intel_lrc_reg.h"
#include "i915_drv.h"
@@ -347,6 +348,7 @@ static const struct i915_oa_format
gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
* @oa_format: An OA unit HW report format
* @oa_periodic: Whether to enable periodic OA unit sampling
* @oa_period_exponent: The OA unit sampling period is derived from this
+ * @engine: The engine (typically rcs0) being monitored by the OA unit
*
* As read_properties_unlocked() enumerates and validates the properties given
* to open a stream of metrics the configuration is built up in the structure
@@ -363,6 +365,8 @@ struct perf_open_properties {
int oa_format;
bool oa_periodic;
int oa_period_exponent;
+
+ struct intel_engine_cs *engine;
};
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
@@ -1205,7 +1209,7 @@ static struct intel_context *oa_pin_context(struct
i915_perf_stream *stream)
int err;
for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
- if (ce->engine->class != RENDER_CLASS)
+ if (ce->engine != stream->engine) /* first match! */
continue;
/*
@@ -2127,7 +2131,13 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
int format_size;
int ret;
- /* If the sysfs metrics/ directory wasn't registered for some
+ if (!props->engine) {
+ DRM_DEBUG("OA engine not specified\n");
+ return -EINVAL;
+ }
+
+ /*
+* If the sysfs metrics/ directory wasn't registered for some
* reason then don't let userspace try their luck with config
* IDs
*/
@@ -2146,7 +2156,8 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
return -ENODEV;
}
- /* To avoid the complexity of having to accurately filter
+ /*
+* To avoid the complexity of having to accurately filter
* counter reports and marshal to the appropriate client
* we currently only allow exclusive access
*/
@@ -2160,6 +2171,9 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
return -EINVAL;
}
+ stream->engine = props->engine;
+ stream->gt = stream->engine->gt;
+
stream->sample_size = sizeof(struct drm_i915_perf_record_header);
format_size = perf->oa_formats[props->oa_format].size;
@@ -2711,7 +2725,6 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
}
stream->perf = perf;
- stream->gt = &perf->i915->gt;
stream->ctx = specific_ctx;
ret = i915_oa_stream_init(stream, param, props);
@@ -2796,6 +2809,15 @@ static int read_properties_unlocked(struct i915_perf
*perf,
return -EINVAL;
}
+ /* At the moment we only support using i915-perf on the RCS. */
+ props->engine = intel_engine_lookup_user(perf->i915,
+I915_ENGINE_CLASS_RENDER,
+0);
+ if (!props->engine) {
+ DRM_DEBUG("No RENDER-capable engines\n");
+ return -EINVAL;
+ }
+
/* Considering that ID = 0 is reserved and assuming that we don't
* (currently) expect any configurations to ever specify duplicate
* values for a particular property ID then the last _PROP_MAX value is
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h
b/drivers/gpu/drm/i915/i915_perf_types.h
index 2d17059d32ee..82cd3b295037 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -140,6 +140,11 @@ struct i915_perf_stream {
*/
intel_wakeref_t wakeref;
+ /**
+* @engine: Engine associated with this performance stream.
+*/
+ struct intel_engine_cs *engine;
+
/**
* @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
* properties given when opening a stream, representing the contents
___
Re: [Intel-gfx] [PATCH 2/2] drm/i915/perf: Store shortcut to intel_uncore
On 10/10/2019 10:27, Chris Wilson wrote: Now that we have the engine stored in i915_perf, we have a means of accessing intel_gt should we require it. However, we are currently only using the intel_gt to find the right intel_uncore, so replace our i915_perf.gt pointer with the more useful i915_perf.uncore. Signed-off-by: Chris Wilson Cc: Lionel Landwerlin --- Reviewed-by: Lionel Landwerlin ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/perf: store the associated engine of a stream
Quoting Lionel Landwerlin (2019-10-10 15:57:32) > On 10/10/2019 10:27, Chris Wilson wrote: > > From: Lionel Landwerlin > > > > We'll use this information later to verify that a client trying to > > reconfigure the stream does so on the right engine. For now, we want to > > pull the knowledge of which engine we use into a central property. > > > > Signed-off-by: Lionel Landwerlin > > > Your changes look fine : > > Reviewed-by: Lionel Landwerlin Reviewed-by: Chris Wilson And the queue gradually shrinks. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/2] drm/i915/perf: store the associated engine of a stream
From: Lionel Landwerlin
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine. For now, we want to
pull the knowledge of which engine we use into a central property.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_perf.c | 30 ++
drivers/gpu/drm/i915/i915_perf_types.h | 5 +
2 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 5a34cad7d824..1a5c6591b9bb 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -197,6 +197,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_pm.h"
+#include "gt/intel_engine_user.h"
#include "gt/intel_lrc_reg.h"
#include "i915_drv.h"
@@ -347,6 +348,7 @@ static const struct i915_oa_format
gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
* @oa_format: An OA unit HW report format
* @oa_periodic: Whether to enable periodic OA unit sampling
* @oa_period_exponent: The OA unit sampling period is derived from this
+ * @engine: The engine (typically rcs0) being monitored by the OA unit
*
* As read_properties_unlocked() enumerates and validates the properties given
* to open a stream of metrics the configuration is built up in the structure
@@ -363,6 +365,8 @@ struct perf_open_properties {
int oa_format;
bool oa_periodic;
int oa_period_exponent;
+
+ struct intel_engine_cs *engine;
};
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
@@ -1205,7 +1209,7 @@ static struct intel_context *oa_pin_context(struct
i915_perf_stream *stream)
int err;
for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
- if (ce->engine->class != RENDER_CLASS)
+ if (ce->engine != stream->engine) /* first match! */
continue;
/*
@@ -2127,7 +2131,13 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
int format_size;
int ret;
- /* If the sysfs metrics/ directory wasn't registered for some
+ if (!props->engine) {
+ DRM_DEBUG("OA engine not specified\n");
+ return -EINVAL;
+ }
+
+ /*
+* If the sysfs metrics/ directory wasn't registered for some
* reason then don't let userspace try their luck with config
* IDs
*/
@@ -2146,7 +2156,8 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
return -ENODEV;
}
- /* To avoid the complexity of having to accurately filter
+ /*
+* To avoid the complexity of having to accurately filter
* counter reports and marshal to the appropriate client
* we currently only allow exclusive access
*/
@@ -2160,6 +2171,9 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
return -EINVAL;
}
+ stream->engine = props->engine;
+ stream->gt = stream->engine->gt;
+
stream->sample_size = sizeof(struct drm_i915_perf_record_header);
format_size = perf->oa_formats[props->oa_format].size;
@@ -2711,7 +2725,6 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
}
stream->perf = perf;
- stream->gt = &perf->i915->gt;
stream->ctx = specific_ctx;
ret = i915_oa_stream_init(stream, param, props);
@@ -2796,6 +2809,15 @@ static int read_properties_unlocked(struct i915_perf
*perf,
return -EINVAL;
}
+ /* At the moment we only support using i915-perf on the RCS. */
+ props->engine = intel_engine_lookup_user(perf->i915,
+I915_ENGINE_CLASS_RENDER,
+0);
+ if (!props->engine) {
+ DRM_DEBUG("No RENDER-capable engines\n");
+ return -EINVAL;
+ }
+
/* Considering that ID = 0 is reserved and assuming that we don't
* (currently) expect any configurations to ever specify duplicate
* values for a particular property ID then the last _PROP_MAX value is
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h
b/drivers/gpu/drm/i915/i915_perf_types.h
index 2d17059d32ee..82cd3b295037 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -140,6 +140,11 @@ struct i915_perf_stream {
*/
intel_wakeref_t wakeref;
+ /**
+* @engine: Engine associated with this performance stream.
+*/
+ struct intel_engine_cs *engine;
+
/**
* @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
* properties given when opening a stream, representing the contents
--
2.23.0
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[Intel-gfx] [CI 2/2] drm/i915/perf: Store shortcut to intel_uncore
Now that we have the engine stored in i915_perf, we have a means of
accessing intel_gt should we require it. However, we are currently only
using the intel_gt to find the right intel_uncore, so replace our
i915_perf.gt pointer with the more useful i915_perf.uncore.
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 48 +-
drivers/gpu/drm/i915/i915_perf_types.h | 4 +--
2 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 1a5c6591b9bb..77c3cef64548 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -419,14 +419,14 @@ static int get_oa_config(struct i915_perf *perf,
static u32 gen8_oa_hw_tail_read(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
return intel_uncore_read(uncore, GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK;
}
static u32 gen7_oa_hw_tail_read(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
u32 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
return oastatus1 & GEN7_OASTATUS1_TAIL_MASK;
@@ -656,7 +656,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
size_t count,
size_t *offset)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
int report_size = stream->oa_buffer.format_size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
@@ -866,7 +866,7 @@ static int gen8_oa_read(struct i915_perf_stream *stream,
size_t count,
size_t *offset)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
u32 oastatus;
int ret;
@@ -945,7 +945,7 @@ static int gen7_append_oa_reports(struct i915_perf_stream
*stream,
size_t count,
size_t *offset)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
int report_size = stream->oa_buffer.format_size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
@@ -1077,7 +1077,7 @@ static int gen7_oa_read(struct i915_perf_stream *stream,
size_t count,
size_t *offset)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
u32 oastatus1;
int ret;
@@ -1352,8 +1352,8 @@ static void i915_oa_stream_destroy(struct
i915_perf_stream *stream)
free_oa_buffer(stream);
- intel_uncore_forcewake_put(stream->gt->uncore, FORCEWAKE_ALL);
- intel_runtime_pm_put(stream->gt->uncore->rpm, stream->wakeref);
+ intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
+ intel_runtime_pm_put(stream->uncore->rpm, stream->wakeref);
if (stream->ctx)
oa_put_render_ctx_id(stream);
@@ -1368,7 +1368,7 @@ static void i915_oa_stream_destroy(struct
i915_perf_stream *stream)
static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
unsigned long flags;
@@ -1416,7 +1416,7 @@ static void gen7_init_oa_buffer(struct i915_perf_stream
*stream)
static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
unsigned long flags;
@@ -1565,7 +1565,7 @@ static void delay_after_mux(void)
static int hsw_enable_metric_set(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
const struct i915_oa_config *oa_config = stream->oa_config;
/*
@@ -1594,7 +1594,7 @@ static int hsw_enable_metric_set(struct i915_perf_stream
*stream)
static void hsw_disable_metric_set(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
intel_uncore_rmw(uncore, GEN6_UCGCTL1,
GEN6_CSUNIT_CLOCK_GATE_DISABLE, 0);
@@ -1911,7 +1911,7 @@ static int gen8_configure_all_contexts(struct
i915_perf_stream *stream,
static int gen8_enable_metric_s
Re: [Intel-gfx] [PATCH 7/9] drm/i915/perf: Allow dynamic reconfiguration of the OA stream
On 10/10/2019 00:19, Chris Wilson wrote:
From: Lionel Landwerlin
Introduce a new perf_ioctl command to change the OA configuration of the
active stream. This allows the OA stream to be reconfigured between
batch buffers, giving greater flexibility in sampling. We inject a
request into the OA context to reconfigure the stream asynchronously on
the GPU in between and ordered with execbuffer calls.
Signed-off-by: Lionel Landwerlin
So much simpler :)
---
drivers/gpu/drm/i915/i915_perf.c | 34 +++-
include/uapi/drm/i915_drm.h | 10 ++
2 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 12cc47aece21..3b77db8995f3 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2856,6 +2856,28 @@ static void i915_perf_disable_locked(struct
i915_perf_stream *stream)
stream->ops->disable(stream);
}
+static int i915_perf_config_locked(struct i915_perf_stream *stream,
+ unsigned long metrics_set)
+{
+ struct i915_oa_config *config;
+ int err = 0;
+
+ config = i915_perf_get_oa_config(stream->perf, metrics_set);
+ if (!config)
+ return -EINVAL;
+
+ if (config != stream->oa_config) {
+ if (stream->pinned_ctx)
+ err = emit_oa_config(stream, stream->pinned_ctx);
+ if (err == 0)
+ config = xchg(&stream->oa_config, config);
+ }
+
+ i915_oa_config_put(config);
+
+ return err;
+}
+
/**
* i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs
* @stream: An i915 perf stream
@@ -2879,6 +2901,8 @@ static long i915_perf_ioctl_locked(struct
i915_perf_stream *stream,
case I915_PERF_IOCTL_DISABLE:
i915_perf_disable_locked(stream);
return 0;
+ case I915_PERF_IOCTL_CONFIG:
+ return i915_perf_config_locked(stream, arg);
For REMOVE_CONFIG we passed a pointer to an u64, not sure whether we
should reuse the same pattern here?
I don't mind the current version.
-Lionel
}
return -EINVAL;
@@ -4017,7 +4041,15 @@ void i915_perf_fini(struct drm_i915_private *i915)
*/
int i915_perf_ioctl_version(void)
{
- return 1;
+ /*
+* 1: Initial version
+* I915_PERF_IOCTL_ENABLE
+* I915_PERF_IOCTL_DISABLE
+*
+* 2: Added runtime modification of OA config.
+* I915_PERF_IOCTL_CONFIG
+*/
+ return 2;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 0c7b2815fbf1..5e66f7c60261 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1932,6 +1932,16 @@ struct drm_i915_perf_open_param {
*/
#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
+/**
+ * Change metrics_set captured by a stream.
+ *
+ * Will not take effect until the stream is restart, or upon the next
+ * execbuf when attached to a specific context.
+ *
+ * This ioctl is available in perf revision 2.
+ */
+#define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
+
/**
* Common to all i915 perf records
*/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Check known register values within the context
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Check known register
values within the context
URL : https://patchwork.freedesktop.org/series/67849/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7055 -> Patchwork_14748
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14748/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14748:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_selftest@live_gt_lrc}:
- fi-bdw-5557u: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7055/fi-bdw-5557u/igt@i915_selftest@live_gt_lrc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14748/fi-bdw-5557u/igt@i915_selftest@live_gt_lrc.html
- fi-skl-6600u: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7055/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14748/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html
- fi-cfl-8109u: [PASS][5] -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7055/fi-cfl-8109u/igt@i915_selftest@live_gt_lrc.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14748/fi-cfl-8109u/igt@i915_selftest@live_gt_lrc.html
- fi-kbl-r: [PASS][7] -> [DMESG-FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7055/fi-kbl-r/igt@i915_selftest@live_gt_lrc.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14748/fi-kbl-r/igt@i915_selftest@live_gt_lrc.html
- fi-skl-6260u: [PASS][9] -> [DMESG-FAIL][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7055/fi-skl-6260u/igt@i915_selftest@live_gt_lrc.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14748/fi-skl-6260u/igt@i915_selftest@live_gt_lrc.html
- {fi-icl-u4}:[PASS][11] -> [DMESG-FAIL][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7055/fi-icl-u4/igt@i915_selftest@live_gt_lrc.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14748/fi-icl-u4/igt@i915_selftest@live_gt_lrc.html
- fi-skl-6770hq: [PASS][13] -> [DMESG-FAIL][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7055/fi-skl-6770hq/igt@i915_selftest@live_gt_lrc.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14748/fi-skl-6770hq/igt@i915_selftest@live_gt_lrc.html
- fi-cfl-guc: [PASS][15] -> [DMESG-FAIL][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7055/fi-cfl-guc/igt@i915_selftest@live_gt_lrc.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14748/fi-cfl-guc/igt@i915_selftest@live_gt_lrc.html
- fi-skl-lmem:[PASS][17] -> [DMESG-FAIL][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7055/fi-skl-lmem/igt@i915_selftest@live_gt_lrc.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14748/fi-skl-lmem/igt@i915_selftest@live_gt_lrc.html
- {fi-tgl-u}: [PASS][19] -> [DMESG-FAIL][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7055/fi-tgl-u/igt@i915_selftest@live_gt_lrc.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14748/fi-tgl-u/igt@i915_selftest@live_gt_lrc.html
- fi-skl-iommu: [PASS][21] -> [DMESG-FAIL][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7055/fi-skl-iommu/igt@i915_selftest@live_gt_lrc.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14748/fi-skl-iommu/igt@i915_selftest@live_gt_lrc.html
- fi-cfl-8700k: [PASS][23] -> [DMESG-FAIL][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7055/fi-cfl-8700k/igt@i915_selftest@live_gt_lrc.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14748/fi-cfl-8700k/igt@i915_selftest@live_gt_lrc.html
- fi-icl-u2: [PASS][25] -> [DMESG-FAIL][26]
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7055/fi-icl-u2/igt@i915_selftest@live_gt_lrc.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14748/fi-icl-u2/igt@i915_selftest@live_gt_lrc.html
- fi-whl-u: [PASS][27] -> [DMESG-FAIL][28]
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7055/fi-whl-u/igt@i915_selftest@live_gt_lrc.html
[28]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14748/fi-whl-u/igt@i915_selftest@live_gt_lrc.html
- fi-skl-guc: [PASS][29] -> [DMESG-FAIL][30]
[29]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7055/fi-skl-guc/igt@i915_selftest@live_gt_lrc.html
[30]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14748/fi-skl-guc/igt@i915_selftest@live_gt_lrc.html
- fi-kbl-7500u: [PAS
Re: [Intel-gfx] [PATCH 7/9] drm/i915/perf: Allow dynamic reconfiguration of the OA stream
Quoting Lionel Landwerlin (2019-10-10 16:22:25) > On 10/10/2019 00:19, Chris Wilson wrote: > > From: Lionel Landwerlin > > > > Introduce a new perf_ioctl command to change the OA configuration of the > > active stream. This allows the OA stream to be reconfigured between > > batch buffers, giving greater flexibility in sampling. We inject a > > request into the OA context to reconfigure the stream asynchronously on > > the GPU in between and ordered with execbuffer calls. > > > > Signed-off-by: Lionel Landwerlin > > > So much simpler :) Indeed, it all came together into a much more coherent story. > > --- > > /** > >* i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs > >* @stream: An i915 perf stream > > @@ -2879,6 +2901,8 @@ static long i915_perf_ioctl_locked(struct > > i915_perf_stream *stream, > > case I915_PERF_IOCTL_DISABLE: > > i915_perf_disable_locked(stream); > > return 0; > > + case I915_PERF_IOCTL_CONFIG: > > + return i915_perf_config_locked(stream, arg); > > For REMOVE_CONFIG we passed a pointer to an u64, not sure whether we > should reuse the same pattern here? Aiui, the user creates oa-config handles, and/or queries them. If we are simpler talking handles that fit inside unsigned long (so assume u32) then I don't see the harm in passing an id rather than a pointer. The alternative is this takes an uuid string? Or you want to always use u64 handles? I guess you will have a better idea what works better after playing around with userspace. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/selftests: Check known register values within the context
Check the logical ring context by asserting that the registers hold
expected start during execution. (It's a bit chicken-and-egg for how
could we manage to execute our request if the registers were not being
updated. Still, it's nice to verify that the HW is working as expected.)
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 126 +
1 file changed, 126 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index a691e429ca01..0aa36b1b2389 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -2599,10 +2599,136 @@ static int live_lrc_layout(void *arg)
return err;
}
+static int __live_lrc_state(struct i915_gem_context *fixme,
+ struct intel_engine_cs *engine,
+ struct i915_vma *scratch)
+{
+ struct intel_context *ce;
+ struct i915_request *rq;
+ enum {
+ RING_START_IDX = 0,
+ RING_TAIL_IDX,
+ MAX_IDX
+ };
+ u32 expected[MAX_IDX];
+ u32 *cs;
+ int err;
+ int n;
+
+ ce = intel_context_create(fixme, engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ err = intel_context_pin(ce);
+ if (err)
+ goto err_put;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_unpin;
+ }
+
+ cs = intel_ring_begin(rq, 4 * MAX_IDX);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ i915_request_add(rq);
+ goto err_unpin;
+ }
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base));
+ *cs++ = i915_ggtt_offset(scratch) + RING_START_IDX * sizeof(u32);
+ *cs++ = 0;
+
+ expected[RING_START_IDX] = i915_ggtt_offset(ce->ring->vma);
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(RING_TAIL(engine->mmio_base));
+ *cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32);
+ *cs++ = 0;
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ intel_engine_flush_submission(engine);
+ expected[RING_TAIL_IDX] = ce->ring->tail;
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0) {
+ err = -ETIME;
+ goto err_rq;
+ }
+
+ cs = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err_rq;
+ }
+
+ for (n = 0; n < MAX_IDX; n++) {
+ if (cs[n] != expected[n]) {
+ pr_err("%s: Stored register[%d] value[0x%x] did not
match expected[0x%x]\n",
+ engine->name, n, cs[n], expected[n]);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_map(scratch->obj);
+
+err_rq:
+ i915_request_put(rq);
+err_unpin:
+ intel_context_unpin(ce);
+err_put:
+ intel_context_put(ce);
+ return err;
+}
+
+static int live_lrc_state(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ struct i915_gem_context *fixme;
+ struct i915_vma *scratch;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /*
+* Check the live register state matches what we expect for this
+* intel_context.
+*/
+
+ fixme = kernel_context(gt->i915);
+ if (!fixme)
+ return -ENOMEM;
+
+ scratch = create_scratch(gt);
+ if (IS_ERR(scratch)) {
+ err = PTR_ERR(scratch);
+ goto out_close;
+ }
+
+ for_each_engine(engine, gt->i915, id) {
+ err = __live_lrc_state(fixme, engine, scratch);
+ if (err)
+ break;
+ }
+
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+
+ i915_vma_unpin_and_release(&scratch, 0);
+out_close:
+ kernel_context_close(fixme);
+ return err;
+}
+
int intel_lrc_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_lrc_layout),
+ SUBTEST(live_lrc_state),
};
if (!HAS_LOGICAL_RING_CONTEXTS(i915))
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/selftests: Check that GPR are cleared for new contexts
We want the general purpose registers to be clear in all new contexts so
that we can be confident that no information is leaked from one to the
next.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 185 ++---
1 file changed, 166 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 0aa36b1b2389..1276da059dc6 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -19,6 +19,9 @@
#include "gem/selftests/igt_gem_utils.h"
#include "gem/selftests/mock_context.h"
+#define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
+#define NUM_GPR_DW (16 * 2) /* each GPR is 2 dwords */
+
static struct i915_vma *create_scratch(struct intel_gt *gt)
{
struct drm_i915_gem_object *obj;
@@ -2107,16 +2110,14 @@ static int preserved_virtual_engine(struct
drm_i915_private *i915,
struct intel_engine_cs **siblings,
unsigned int nsibling)
{
-#define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
-
struct i915_request *last = NULL;
struct i915_gem_context *ctx;
struct intel_context *ve;
struct i915_vma *scratch;
struct igt_live_test t;
- const int num_gpr = 16 * 2; /* each GPR is 2 dwords */
unsigned int n;
int err = 0;
+ u32 *cs;
ctx = kernel_context(i915);
if (!ctx)
@@ -2142,10 +2143,9 @@ static int preserved_virtual_engine(struct
drm_i915_private *i915,
if (err)
goto out_unpin;
- for (n = 0; n < num_gpr; n++) {
+ for (n = 0; n < NUM_GPR_DW; n++) {
struct intel_engine_cs *engine = siblings[n % nsibling];
struct i915_request *rq;
- u32 *cs;
rq = i915_request_create(ve);
if (IS_ERR(rq)) {
@@ -2169,7 +2169,7 @@ static int preserved_virtual_engine(struct
drm_i915_private *i915,
*cs++ = 0;
*cs++ = MI_LOAD_REGISTER_IMM(1);
- *cs++ = CS_GPR(engine, (n + 1) % num_gpr);
+ *cs++ = CS_GPR(engine, (n + 1) % NUM_GPR_DW);
*cs++ = n + 1;
*cs++ = MI_NOOP;
@@ -2182,21 +2182,26 @@ static int preserved_virtual_engine(struct
drm_i915_private *i915,
if (i915_request_wait(last, 0, HZ / 5) < 0) {
err = -ETIME;
- } else {
- u32 *map = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
+ goto out_end;
+ }
- for (n = 0; n < num_gpr; n++) {
- if (map[n] != n) {
- pr_err("Incorrect value[%d] found for
GPR[%d]\n",
- map[n], n);
- err = -EINVAL;
- break;
- }
- }
+ cs = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto out_end;
+ }
- i915_gem_object_unpin_map(scratch->obj);
+ for (n = 0; n < NUM_GPR_DW; n++) {
+ if (cs[n] != n) {
+ pr_err("Incorrect value[%d] found for GPR[%d]\n",
+ cs[n], n);
+ err = -EINVAL;
+ break;
+ }
}
+ i915_gem_object_unpin_map(scratch->obj);
+
out_end:
if (igt_live_test_end(&t))
err = -EIO;
@@ -2210,8 +2215,6 @@ static int preserved_virtual_engine(struct
drm_i915_private *i915,
out_close:
kernel_context_close(ctx);
return err;
-
-#undef CS_GPR
}
static int live_virtual_preserved(void *arg)
@@ -2724,11 +2727,155 @@ static int live_lrc_state(void *arg)
return err;
}
+static int gpr_make_dirty(struct intel_engine_cs *engine)
+{
+ struct i915_request *rq;
+ u32 *cs;
+ int n;
+
+ rq = i915_request_create(engine->kernel_context);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ cs = intel_ring_begin(rq, 2 * NUM_GPR_DW + 2);
+ if (IS_ERR(cs)) {
+ i915_request_add(rq);
+ return PTR_ERR(cs);
+ }
+
+ *cs++ = MI_LOAD_REGISTER_IMM(NUM_GPR_DW);
+ for (n = 0; n < NUM_GPR_DW; n++) {
+ *cs++ = CS_GPR(engine, n);
+ *cs++ = STACK_MAGIC;
+ }
+ *cs++ = MI_NOOP;
+
+ intel_ring_advance(rq, cs);
+ i915_request_add(rq);
+
+ return 0;
+}
+
+static int __live_gpr_clear(struct i915_gem_context *fixme,
+ struct intel_engine_cs *engine,
+ struct i915_vma *scratch)
+{
+ struct intel_context *ce;
+ struct i915_request *rq;
+ u32 *cs;
+ int err;
+ int n;
+
+ if (INTEL_G
[Intel-gfx] [PATCH] drm/i915: Don't disable interrupts independently of the lock
The locks (active.lock and rq->lock) need to be taken with disabled interrupts. This is done in i915_request_retire() by disabling the interrupts independently of the locks itself. While local_irq_disable()+spin_lock() equals spin_lock_irq() on vanilla it does not on PREEMPT_RT. Also, it is not obvious if there is a special reason to why the interrupts are disabled independently of the lock. Enable/disable interrupts as part of the locking instruction. Signed-off-by: Sebastian Andrzej Siewior --- drivers/gpu/drm/i915/i915_request.c |8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -251,15 +251,13 @@ static bool i915_request_retire(struct i active->retire(active, rq); } - local_irq_disable(); - /* * We only loosely track inflight requests across preemption, * and so we may find ourselves attempting to retire a _completed_ * request that we have removed from the HW and put back on a run * queue. */ - spin_lock(&rq->engine->active.lock); + spin_lock_irq(&rq->engine->active.lock); list_del(&rq->sched.link); spin_unlock(&rq->engine->active.lock); @@ -278,9 +276,7 @@ static bool i915_request_retire(struct i __notify_execute_cb(rq); } GEM_BUG_ON(!list_empty(&rq->execute_cb)); - spin_unlock(&rq->lock); - - local_irq_enable(); + spin_unlock_irq(&rq->lock); remove_from_client(rq); list_del(&rq->link); ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 7/9] drm/i915/perf: Allow dynamic reconfiguration of the OA stream
On 10/10/2019 18:44, Chris Wilson wrote: Quoting Lionel Landwerlin (2019-10-10 16:22:25) On 10/10/2019 00:19, Chris Wilson wrote: From: Lionel Landwerlin Introduce a new perf_ioctl command to change the OA configuration of the active stream. This allows the OA stream to be reconfigured between batch buffers, giving greater flexibility in sampling. We inject a request into the OA context to reconfigure the stream asynchronously on the GPU in between and ordered with execbuffer calls. Signed-off-by: Lionel Landwerlin So much simpler :) Indeed, it all came together into a much more coherent story. --- /** * i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs * @stream: An i915 perf stream @@ -2879,6 +2901,8 @@ static long i915_perf_ioctl_locked(struct i915_perf_stream *stream, case I915_PERF_IOCTL_DISABLE: i915_perf_disable_locked(stream); return 0; + case I915_PERF_IOCTL_CONFIG: + return i915_perf_config_locked(stream, arg); For REMOVE_CONFIG we passed a pointer to an u64, not sure whether we should reuse the same pattern here? Aiui, the user creates oa-config handles, and/or queries them. If we are simpler talking handles that fit inside unsigned long (so assume u32) then I don't see the harm in passing an id rather than a pointer. The alternative is this takes an uuid string? Or you want to always use u64 handles? I guess you will have a better idea what works better after playing around with userspace. -Chris Yeah, that's a fine interface actually. This should really have you as the author. Reviewed-by: Lionel Landwerlin ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 9/9] drm/i915/execlists: Prevent merging requests with conflicting flags
On 10/10/2019 00:19, Chris Wilson wrote:
We set out-of-bound parameters inside the i915_requests.flags field,
such as disabling preemption or marking the end-of-context. We should
not coalesce consecutive requests if they have differing instructions
as we only inspect the last active request in a context. Thus if we
allow a later request to be merged into the same execution context, it
will mask any of the earlier flags.
References: 2a98f4e65bba ("drm/i915: add infrastructure to hold off preemption on a
request")
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Nice.
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7ea58335f04c..d0687a94c8d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1233,6 +1233,9 @@ static bool can_merge_rq(const struct i915_request *prev,
if (i915_request_completed(next))
return true;
+ if (unlikely(prev->flags ^ next->flags) & I915_REQUEST_NOPREEMPT)
+ return false;
+
if (!can_merge_ctx(prev->hw_context, next->hw_context))
return false;
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/10] drm/i915: Note the addition of timeslicing to the pretend scheduler
== Series Details ==
Series: series starting with [01/10] drm/i915: Note the addition of timeslicing
to the pretend scheduler
URL : https://patchwork.freedesktop.org/series/67827/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7047_full -> Patchwork_14742_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14742_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14742_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14742_full:
### IGT changes ###
Possible regressions
* igt@i915_hangman@error-state-capture-bcs0:
- shard-apl: [PASS][1] -> [FAIL][2] +3 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/shard-apl1/igt@i915_hang...@error-state-capture-bcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/shard-apl1/igt@i915_hang...@error-state-capture-bcs0.html
- shard-iclb: [PASS][3] -> [FAIL][4] +2 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/shard-iclb3/igt@i915_hang...@error-state-capture-bcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/shard-iclb2/igt@i915_hang...@error-state-capture-bcs0.html
* igt@i915_hangman@error-state-capture-rcs0:
- shard-skl: [PASS][5] -> [FAIL][6] +3 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/shard-skl3/igt@i915_hang...@error-state-capture-rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/shard-skl1/igt@i915_hang...@error-state-capture-rcs0.html
- shard-glk: [PASS][7] -> [FAIL][8] +3 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/shard-glk9/igt@i915_hang...@error-state-capture-rcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/shard-glk1/igt@i915_hang...@error-state-capture-rcs0.html
* igt@i915_hangman@error-state-capture-vcs0:
- shard-kbl: [PASS][9] -> [FAIL][10] +4 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/shard-kbl4/igt@i915_hang...@error-state-capture-vcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/shard-kbl7/igt@i915_hang...@error-state-capture-vcs0.html
* igt@i915_hangman@error-state-capture-vcs1:
- shard-iclb: NOTRUN -> [FAIL][11]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/shard-iclb1/igt@i915_hang...@error-state-capture-vcs1.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-iclb: [PASS][12] -> [DMESG-WARN][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/shard-iclb2/igt@kms_fbcon_...@psr-suspend.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/shard-iclb1/igt@kms_fbcon_...@psr-suspend.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_hangman@error-state-capture-rcs0:
- {shard-tglb}: [PASS][14] -> [FAIL][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/shard-tglb6/igt@i915_hang...@error-state-capture-rcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/shard-tglb6/igt@i915_hang...@error-state-capture-rcs0.html
* igt@syncobj_wait@invalid-multi-wait-all-unsubmitted-signaled:
- {shard-tglb}: [PASS][16] -> [INCOMPLETE][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/shard-tglb2/igt@syncobj_w...@invalid-multi-wait-all-unsubmitted-signaled.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/shard-tglb6/igt@syncobj_w...@invalid-multi-wait-all-unsubmitted-signaled.html
### Piglit changes ###
Possible regressions
* spec@arb_shader_image_load_store@shader-mem-barrier (NEW):
- pig-glk-j5005: NOTRUN -> [FAIL][18]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14742/pig-glk-j5005/spec@arb_shader_image_load_st...@shader-mem-barrier.html
New tests
-
New tests have been introduced between CI_DRM_7047_full and
Patchwork_14742_full:
### New Piglit tests (1) ###
* spec@arb_shader_image_load_store@shader-mem-barrier:
- Statuses : 1 fail(s)
- Exec time: [2.79] s
Known issues
Here are the changes found in Patchwork_14742_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109276]) +17 similar
issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/shard-iclb4/igt@gem_exec_sched...@independent-bsd2.html
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Enable bigjoiner support, second approach. (rev3)
== Series Details == Series: Enable bigjoiner support, second approach. (rev3) URL : https://patchwork.freedesktop.org/series/67590/ State : failure == Summary == Applying: HAX to make DSC work on the icelake test system Applying: drm/i915: Fix for_each_intel_plane_mask definition Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_display.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_display.h No changes -- Patch already applied. Applying: drm/i915: Introduce and use intel_atomic_crtc_state_for_each_plane_state. Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_display.h M drivers/gpu/drm/i915/intel_pm.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_pm.c No changes -- Patch already applied. Applying: drm/i915: Remove cursor use of properties for coordinates Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_display.c M drivers/gpu/drm/i915/intel_pm.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_display.c No changes -- Patch already applied. Applying: drm/i915: Use intel_plane_state in prepare and cleanup plane_fb Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_display.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_display.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_display.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0005 drm/i915: Use intel_plane_state in prepare and cleanup plane_fb When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Honour O_NONBLOCK before throttling execbuf submissions
== Series Details ==
Series: drm/i915: Honour O_NONBLOCK before throttling execbuf submissions
URL : https://patchwork.freedesktop.org/series/67850/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7056 -> Patchwork_14749
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14749/index.html
Known issues
Here are the changes found in Patchwork_14749 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14749/fi-blb-e6850/igt@gem_exec_susp...@basic-s4-devices.html
* igt@gem_mmap_gtt@basic-read-write:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14749/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
Possible fixes
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][5] ([fdo#103927] / [fdo#111381]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14749/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@i915_module_load@reload-with-fault-injection:
- {fi-icl-dsi}: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-icl-dsi/igt@i915_module_l...@reload-with-fault-injection.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14749/fi-icl-dsi/igt@i915_module_l...@reload-with-fault-injection.html
* igt@i915_selftest@live_execlists:
- {fi-icl-guc}: [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-icl-guc/igt@i915_selftest@live_execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14749/fi-icl-guc/igt@i915_selftest@live_execlists.html
* igt@kms_addfb_basic@unused-modifier:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-icl-u3/igt@kms_addfb_ba...@unused-modifier.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14749/fi-icl-u3/igt@kms_addfb_ba...@unused-modifier.html
* igt@kms_busy@basic-flip-a:
- {fi-tgl-u2}:[DMESG-WARN][13] ([fdo#111600]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14749/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111407]) -> [FAIL][16] ([fdo#111045]
/ [fdo#111096])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14749/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111867]: https://bugs.freedesktop.org/show_bug.cgi?id=111867
Participating hosts (54 -> 47)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7056 -> Patchwork_14749
CI-20190529: 20190529
CI_DRM_7056: 589ed9c309ff4c26532bbc7ac6dcce9514bbd1e9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14749: 1bf5e78297b2d829e1487d563b45181017a66462 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1bf5e78297b2 drm/i915: Honour
[Intel-gfx] ✗ Fi.CI.BUILD: failure for RFC drm/i915: Allow userspace to specify ringsize on construction
== Series Details == Series: RFC drm/i915: Allow userspace to specify ringsize on construction URL : https://patchwork.freedesktop.org/series/67852/ State : failure == Summary == Applying: RFC drm/i915: Allow userspace to specify ringsize on construction Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gem/i915_gem_context.c M include/uapi/drm/i915_drm.h Falling back to patching base and 3-way merge... Auto-merging include/uapi/drm/i915_drm.h CONFLICT (content): Merge conflict in include/uapi/drm/i915_drm.h Auto-merging drivers/gpu/drm/i915/gem/i915_gem_context.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gem/i915_gem_context.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 RFC drm/i915: Allow userspace to specify ringsize on construction When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915: Shrink eDRAM ways/sets arrays
== Series Details ==
Series: series starting with [1/5] drm/i915: Shrink eDRAM ways/sets arrays
URL : https://patchwork.freedesktop.org/series/67853/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7056 -> Patchwork_14752
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14752 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14752, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14752/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14752:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_hangcheck:
- fi-hsw-4770r: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14752/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html
Known issues
Here are the changes found in Patchwork_14752 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14752/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][5] -> [INCOMPLETE][6] ([fdo#107718])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14752/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@basic-write-read-distinct:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724]) +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14752/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
Possible fixes
* igt@i915_module_load@reload-with-fault-injection:
- {fi-icl-dsi}: [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-icl-dsi/igt@i915_module_l...@reload-with-fault-injection.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14752/fi-icl-dsi/igt@i915_module_l...@reload-with-fault-injection.html
* igt@i915_selftest@live_execlists:
- {fi-icl-guc}: [INCOMPLETE][11] ([fdo#107713]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-icl-guc/igt@i915_selftest@live_execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14752/fi-icl-guc/igt@i915_selftest@live_execlists.html
* igt@kms_addfb_basic@unused-modifier:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-icl-u3/igt@kms_addfb_ba...@unused-modifier.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14752/fi-icl-u3/igt@kms_addfb_ba...@unused-modifier.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
Participating hosts (54 -> 47)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7056 -> Patchwork_14752
CI-20190529: 20190529
CI_DRM_7056: 589ed9c309ff4c26532bbc7ac6dcce9514bbd1e9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14752: 770d7f9be1dc476e8774a91addc34b7099ff1772 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
770d7f9be1dc drm/i915: Make hdcp2_msg_timeout.timeout u16
24c9ff1cca7e drm/i915: Remove hdcp2_hdmi_msg_timeout.timeout2
7e072255546e drm/i915: Remove dead weight from hdcp2_msg_timeout[]
d958cb47d4ac drm/i915: s/hdcp2_hdmi_msg_data/hdcp2_hdmi_msg_timeout/
64800ed28892 drm/i915: Shrink eDRAM ways/sets arrays
== Logs ==
For more det
Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915: Move SAGV block time to dev_priv (rev2)
On Wed, Oct 09, 2019 at 10:37:21PM +, Patchwork wrote:
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Move SAGV block time to
dev_priv (rev2)
URL : https://patchwork.freedesktop.org/series/67799/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7da5381e3ab8 drm/i915: Move SAGV block time to dev_priv
-:63: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#63: FILE: drivers/gpu/drm/i915/intel_pm.c:3657:
+ return;
+ } else {
I agree, it's one of my pet peeves, but i915's codebase doesn't:
"if ladders" with returns inside are used all over the place.
Lucas De Marchi
total: 0 errors, 1 warnings, 0 checks, 69 lines checked
cc743a676c3a drm/i915/tgl: Read SAGV block time from PCODE
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/perf: store the associated engine of a stream
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/perf: store the associated
engine of a stream
URL : https://patchwork.freedesktop.org/series/67857/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7056 -> Patchwork_14753
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14753/index.html
Known issues
Here are the changes found in Patchwork_14753 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_create@basic:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-icl-u2/igt@gem_exec_cre...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14753/fi-icl-u2/igt@gem_exec_cre...@basic.html
Possible fixes
* igt@i915_module_load@reload-with-fault-injection:
- {fi-icl-dsi}: [INCOMPLETE][3] ([fdo#107713]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-icl-dsi/igt@i915_module_l...@reload-with-fault-injection.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14753/fi-icl-dsi/igt@i915_module_l...@reload-with-fault-injection.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][5] ([fdo#111407]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7056/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14753/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (54 -> 43)
--
Missing(11): fi-icl-u4 fi-bxt-dsi fi-ilk-m540 fi-tgl-u2 fi-hsw-4200u
fi-byt-squawks fi-bsw-cyan fi-icl-y fi-bdw-samus fi-byt-clapper fi-skl-6600u
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7056 -> Patchwork_14753
CI-20190529: 20190529
CI_DRM_7056: 589ed9c309ff4c26532bbc7ac6dcce9514bbd1e9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14753: f4a9cb42dbd75b70628b6e0d2f34c69a953c7152 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f4a9cb42dbd7 drm/i915/perf: Store shortcut to intel_uncore
48987ec6a0f7 drm/i915/perf: store the associated engine of a stream
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14753/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Don't disable interrupts independently of the lock
Quoting Sebastian Andrzej Siewior (2019-10-10 17:06:40) > The locks (active.lock and rq->lock) need to be taken with disabled > interrupts. This is done in i915_request_retire() by disabling the > interrupts independently of the locks itself. > While local_irq_disable()+spin_lock() equals spin_lock_irq() on vanilla > it does not on PREEMPT_RT. Also, it is not obvious if there is a special > reason > to why the interrupts are disabled independently of the lock. > > Enable/disable interrupts as part of the locking instruction. > > Signed-off-by: Sebastian Andrzej Siewior > --- > drivers/gpu/drm/i915/i915_request.c |8 ++-- > 1 file changed, 2 insertions(+), 6 deletions(-) > > --- a/drivers/gpu/drm/i915/i915_request.c > +++ b/drivers/gpu/drm/i915/i915_request.c > @@ -251,15 +251,13 @@ static bool i915_request_retire(struct i > active->retire(active, rq); > } > > - local_irq_disable(); > - > /* > * We only loosely track inflight requests across preemption, > * and so we may find ourselves attempting to retire a _completed_ > * request that we have removed from the HW and put back on a run > * queue. > */ > - spin_lock(&rq->engine->active.lock); > + spin_lock_irq(&rq->engine->active.lock); > list_del(&rq->sched.link); > spin_unlock(&rq->engine->active.lock); > > @@ -278,9 +276,7 @@ static bool i915_request_retire(struct i > __notify_execute_cb(rq); > } > GEM_BUG_ON(!list_empty(&rq->execute_cb)); > - spin_unlock(&rq->lock); > - > - local_irq_enable(); > + spin_unlock_irq(&rq->lock); Nothing screams about the imbalance? irq off from one lock to the other? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Don't disable interrupts independently of the lock
On 2019-10-10 19:11:27 [+0100], Chris Wilson wrote: > > --- a/drivers/gpu/drm/i915/i915_request.c > > +++ b/drivers/gpu/drm/i915/i915_request.c > > @@ -251,15 +251,13 @@ static bool i915_request_retire(struct i > > active->retire(active, rq); > > } > > > > - local_irq_disable(); > > - > > /* > > * We only loosely track inflight requests across preemption, > > * and so we may find ourselves attempting to retire a _completed_ > > * request that we have removed from the HW and put back on a run > > * queue. > > */ > > - spin_lock(&rq->engine->active.lock); > > + spin_lock_irq(&rq->engine->active.lock); > > list_del(&rq->sched.link); > > spin_unlock(&rq->engine->active.lock); > > > > @@ -278,9 +276,7 @@ static bool i915_request_retire(struct i > > __notify_execute_cb(rq); > > } > > GEM_BUG_ON(!list_empty(&rq->execute_cb)); > > - spin_unlock(&rq->lock); > > - > > - local_irq_enable(); > > + spin_unlock_irq(&rq->lock); > > Nothing screams about the imbalance? irq off from one lock to the other? There is no imbalance, is there? Interrupts are disabled as part of acquiring the first lock and enabled again as part of releasing the second lock. It may not look beautiful. I'm just not sure if this | spin_lock_irq(&rq->engine->active.lock); | list_del(&rq->sched.link); | spin_unlock_irq(&rq->engine->active.lock); | | spin_lock_irq(&rq->lock); | i915_request_mark_complete(rq); … | spin_unlock_irq(&rq->lock); has been avoided because an interrupt here could change something or if this is just an optimisation. > -Chris Sebastian ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 3/6] drm/i915/display/icl: HW state readout for transcoder port sync config
After the state is committed, we readout the HW registers and compare
the HW state with the SW state that we just committed.
For Transcdoer port sync, we add master_transcoder and the
salves bitmask to the crtc_state, hence we need to read those during
the HW state readout to avoid pipe state mismatch.
v9:
* Initialize master_transcoder = INVALID at get config (Ville)
v8:
* Use master_select -1, address TRANS_EDP case (Ville)
* Rename master_transcoder to _readout (Lucas)
v7:
* NDont read HW state for DSI
v6:
* Go through both parts of HW readout (Maarten)
* Add a WARN if the same trans configured as
master and slave (Ville, Maarten)
v5:
* Add return INVALID in defaut case (Maarten)
v4:
* Get power domains in master loop for get_config (Ville)
v3:
* Add TRANSCODER_D (Maarten)
* v3 Reviewed-by: Maarten Lankhorst
v2:
* Add Transcoder_D and MISSING_CASE (Maarten)
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Matt Roper
Cc: Jani Nikula
Signed-off-by: Manasi Navare
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 59
1 file changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f37b28da3768..a79dec6d7f49 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10481,6 +10481,59 @@ static void haswell_get_ddi_port_state(struct
intel_crtc *crtc,
}
}
+static enum transcoder transcoder_master_readout(struct drm_i915_private
*dev_priv,
+enum transcoder cpu_transcoder)
+{
+ u32 trans_port_sync, master_select;
+
+ trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder));
+
+ if ((trans_port_sync & PORT_SYNC_MODE_ENABLE) == 0)
+ return INVALID_TRANSCODER;
+
+ master_select = trans_port_sync &
+ PORT_SYNC_MODE_MASTER_SELECT_MASK;
+ if (master_select == 0)
+ return TRANSCODER_EDP;
+ else
+ return master_select - 1;
+}
+
+static void icelake_get_trans_port_sync_config(struct intel_crtc_state
*crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ u32 transcoders;
+ enum transcoder cpu_transcoder;
+
+ crtc_state->master_transcoder = transcoder_master_readout(dev_priv,
+
crtc_state->cpu_transcoder);
+
+ transcoders = BIT(TRANSCODER_A) |
+ BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C) |
+ BIT(TRANSCODER_D);
+ for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
+ enum intel_display_power_domain power_domain;
+ intel_wakeref_t trans_wakeref;
+
+ power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
+ trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
+
power_domain);
+
+ if (!trans_wakeref)
+ continue;
+
+ if (transcoder_master_readout(dev_priv, cpu_transcoder) ==
+ crtc_state->cpu_transcoder)
+ crtc_state->sync_mode_slaves_mask |=
BIT(cpu_transcoder);
+
+ intel_display_power_put(dev_priv, power_domain, trans_wakeref);
+ }
+
+ WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER &&
+ crtc_state->sync_mode_slaves_mask);
+}
+
static bool haswell_get_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
@@ -10490,6 +10543,8 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
u64 power_domain_mask;
bool active;
+ pipe_config->master_transcoder = INVALID_TRANSCODER;
+
intel_crtc_init_scalers(crtc, pipe_config);
power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
@@ -10600,6 +10655,10 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
pipe_config->pixel_multiplier = 1;
}
+ if (INTEL_GEN(dev_priv) >= 11 &&
+ !transcoder_is_dsi(pipe_config->cpu_transcoder))
+ icelake_get_trans_port_sync_config(pipe_config);
+
out:
for_each_power_domain(power_domain, power_domain_mask)
intel_display_power_put(dev_priv,
--
2.19.1
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Check known register values within the context
== Series Details == Series: series starting with [1/2] drm/i915/selftests: Check known register values within the context URL : https://patchwork.freedesktop.org/series/67862/ State : success == Summary == CI Bug Log - changes from CI_DRM_7057 -> Patchwork_14754 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14754/index.html Known issues Here are the changes found in Patchwork_14754 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap_gtt@basic-copy: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7057/fi-icl-u3/igt@gem_mmap_...@basic-copy.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14754/fi-icl-u3/igt@gem_mmap_...@basic-copy.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][3] -> [DMESG-WARN][4] ([fdo#102614]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7057/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14754/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@gem_flink_basic@double-flink: - fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7057/fi-icl-u3/igt@gem_flink_ba...@double-flink.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14754/fi-icl-u3/igt@gem_flink_ba...@double-flink.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][7] ([fdo#111045] / [fdo#111096]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7057/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14754/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 Participating hosts (52 -> 47) -- Additional (2): fi-kbl-soraka fi-tgl-u2 Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7057 -> Patchwork_14754 CI-20190529: 20190529 CI_DRM_7057: 15a100ce137c88af5eed22fa1deeb290e491629b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14754: daf44ad5a4b0647879ec293ab8b83adb305b8bac @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == daf44ad5a4b0 drm/i915/selftests: Check that GPR are cleared for new contexts 1bd3e9abe4fd drm/i915/selftests: Check known register values within the context == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14754/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Don't disable interrupts independently of the lock (rev2)
== Series Details == Series: drm/i915: Don't disable interrupts independently of the lock (rev2) URL : https://patchwork.freedesktop.org/series/59289/ State : failure == Summary == Applying: drm/i915: Don't disable interrupts independently of the lock error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_request.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915: Don't disable interrupts independently of the lock When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v7,1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync (rev2)
== Series Details == Series: series starting with [v7,1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync (rev2) URL : https://patchwork.freedesktop.org/series/67806/ State : failure == Summary == Applying: drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync Applying: drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_display.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0002 drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] drm/i915/display: Check if FBC and DMC are fused off
Those features could be fused off on GEN9 non-low power and newer
GENs.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 6 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 39c65f051468..086a8e6e86f1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7643,7 +7643,9 @@ enum {
#define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
#define SKL_DFSM _MMIO(0x51000)
+#define SKL_DFSM_DISPLAY_PM_DISABLE(1 << 27)
#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
+#define SKL_DFSM_DMC_DISABLE (1 << 23)
#define BXT_DFSM_CDCLK_LIMIT_MASK (3 << 23)
#define BXT_DFSM_CDCLK_LIMIT_675 (0 << 23)
#define BXT_DFSM_CDCLK_LIMIT_540 (1 << 23)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 5cfa197090e2..deeab3790a51 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -983,6 +983,12 @@ void intel_device_info_runtime_init(struct
drm_i915_private *dev_priv)
if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
info->display.has_hdcp = 0;
+
+ if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
+ info->display.has_fbc = 0;
+
+ if (!IS_GEN9_BC(dev_priv) && dfsm & SKL_DFSM_DMC_DISABLE)
+ info->display.has_csr = 0;
}
/* Initialize slice/subslice/EU info */
--
2.23.0
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[Intel-gfx] [PATCH 1/4] drm/i915/display: Handle fused off display correctly
If all pipes are fused off it means that display is disabled, similar
like we handle for GEN 7 and 8 right above.
On GEN 9 the bit 31 is "Internal Graphics Disable" and on newer GENs
it has another function, probably on GEN 9 when bit 31 is set all
the 3 pipes disable bit are set, so we can unify the handling.
Cc: Lucas De Marchi
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_device_info.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 85e480bdc673..c01fccfe3cca 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -972,15 +972,14 @@ void intel_device_info_runtime_init(struct
drm_i915_private *dev_priv)
enabled_mask &= ~BIT(PIPE_D);
/*
-* At least one pipe should be enabled and if there are
-* disabled pipes, they should be the last ones, with no holes
-* in the mask.
+* If there are disabled pipes, they should be the last ones,
+* with no holes in the mask.
*/
- if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
+ if (enabled_mask && !is_power_of_2(enabled_mask + 1))
DRM_ERROR("invalid pipe fuse configuration:
enabled_mask=0x%x\n",
enabled_mask);
- else
- info->pipe_mask = enabled_mask;
+
+ info->pipe_mask = enabled_mask;
}
/* Initialize slice/subslice/EU info */
--
2.23.0
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