Re: [Intel-gfx] [PATCH 1/2] drm/i915: HSW PSR fix inverted sink DP_PSR_CFG link setup.
On Fri, Feb 07, 2014 at 04:09:47PM -0200, Rodrigo Vivi wrote: > As pointed out by Ville we were using inverted logic here. > According to spec: > For link standby mode set 170h[1] = 1. > For full link disabling set 170h[1] = 0. > > Cc: Ville Syrjälä > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/intel_dp.c | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 50381f7..4ecda72 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1661,12 +1661,12 @@ static void intel_edp_psr_enable_sink(struct intel_dp > *intel_dp) > /* Enable PSR in sink */ > if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) > intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, > - DP_PSR_ENABLE & > - ~DP_PSR_MAIN_LINK_ACTIVE); > - else > - intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, > DP_PSR_ENABLE | > DP_PSR_MAIN_LINK_ACTIVE); > + else > + intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, > + DP_PSR_ENABLE & > + ~DP_PSR_MAIN_LINK_ACTIVE); I think this is now the opposite of what we want. Ie. if the sink doesn't require training we should disable the main link. Otherwise we should keep the main link on, and that way avoid the need to train on PSR exit. Actually I'm not sure that's really what we want. I think the hardware can do the training on its own, so in theory we should just always disable the main link. Although the PM guide has a comment indicating that the hardware training can fail, in which case software must repeat it. We don't have code to do that, so I guess leaving the main link on is the safer option. Would be nice to have a comment in the code stating as much, if this is indeed the reason why the code was written this way. > > /* Setup AUX registers */ > I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); > -- > 1.7.11.7 -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: PSR HSW: update after enabling sprite.
On Fri, Feb 7, 2014 at 5:17 PM, Ville Syrjälä wrote: > On Fri, Feb 07, 2014 at 04:09:48PM -0200, Rodrigo Vivi wrote: >> On the current structure HSW doesn't support PSR with sprites enabled >> but sprites can be enabled after PSR was enabled what would cause >> user to miss screen updates. >> >> Cc: Ville Syrjälä >> Signed-off-by: Rodrigo Vivi >> --- >> drivers/gpu/drm/i915/intel_sprite.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/intel_sprite.c >> b/drivers/gpu/drm/i915/intel_sprite.c >> index 336ae6c..3132686 100644 >> --- a/drivers/gpu/drm/i915/intel_sprite.c >> +++ b/drivers/gpu/drm/i915/intel_sprite.c >> @@ -318,6 +318,8 @@ ivb_update_plane(struct drm_plane *plane, struct >> drm_crtc *crtc, >> I915_WRITE(SPRSURF(pipe), >> i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); >> POSTING_READ(SPRSURF(pipe)); >> + >> + intel_edp_psr_update(dev); > > I was thinking this might be better placed in intel_update_plane() > since the fbc/ips stuff is there, but I can live with it being here too. I agree there is better. > > But should if have a HSW check on it? BDW doesn't have this restriction > anymore, right? yes, it should... you are right! > >> } >> >> static void >> -- >> 1.7.11.7 > > -- > Ville Syrjälä > Intel OTC I also agree with Daniel we need a test case for that... so, will provide this and a new patch version later -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 10/28] lib/display: Add support for the cursor plane
Signed-off-by: Damien Lespiau
---
lib/igt_kms.c | 148 ++
lib/igt_kms.h | 13 +-
2 files changed, 150 insertions(+), 11 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 64fb39a..3b75478 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -889,16 +889,29 @@ void igt_display_init(igt_display_t *display, int drm_fd)
for (i = 0; i < display->n_pipes; i++) {
igt_pipe_t *pipe = &display->pipes[i];
igt_plane_t *plane;
+ int p;
pipe->display = display;
pipe->pipe = i;
- pipe->n_planes = 1;
/* primary plane */
- plane = &pipe->planes[0];
+ p = IGT_PLANE_PRIMARY;
+ plane = &pipe->planes[p];
plane->pipe = pipe;
- plane->index = 0;
+ plane->index = p;
plane->is_primary = true;
+
+ /* cursor plane */
+ p++;
+ plane = &pipe->planes[p];
+ plane->pipe = pipe;
+ plane->index = p;
+ plane->is_cursor = true;
+
+ pipe->n_planes = ++p;
+
+ /* make sure we don't overflow the plane array */
+ igt_assert(pipe->n_planes <= IGT_MAX_PLANES);
}
/*
@@ -1009,6 +1022,22 @@ static igt_pipe_t
*igt_output_get_driving_pipe(igt_output_t *output)
return &display->pipes[pipe];
}
+static igt_plane_t *igt_pipe_get_plane(igt_pipe_t *pipe, enum igt_plane plane)
+{
+ int idx;
+
+ /* Cursor plane is always the upper plane */
+ if (plane == IGT_PLANE_CURSOR)
+ idx = pipe->n_planes - 1;
+ else {
+ igt_assert_f(plane >= 0 && plane < (pipe->n_planes - 1),
+"plane=%d\n", plane);
+ idx = plane;
+ }
+
+ return &pipe->planes[idx];
+}
+
static uint32_t igt_plane_get_fd_id(igt_plane_t *plane)
{
if (plane->fb)
@@ -1017,10 +1046,53 @@ static uint32_t igt_plane_get_fd_id(igt_plane_t *plane)
return 0;
}
+static uint32_t igt_plane_get_fb_gem_handle(igt_plane_t *plane)
+{
+ if (plane->fb)
+ return plane->fb->gem_handle;
+ else
+ return 0;
+}
+
+static int igt_cursor_commit(igt_plane_t *plane, igt_output_t *output)
+{
+ igt_display_t *display = output->display;
+ uint32_t crtc_id = output->config.crtc->crtc_id;
+ int ret;
+
+ if (plane->position_changed) {
+ int x = plane->crtc_x;
+ int y = plane->crtc_y;
+
+ LOG(display,
+ "%s: MoveCursor pipe %c, (%d, %d)\n",
+ igt_output_name(output),
+ pipe_name(output->config.pipe),
+ x, y);
+
+ ret = drmModeMoveCursor(display->drm_fd, crtc_id, x, y);
+
+ igt_assert(ret == 0);
+
+ plane->position_changed = false;
+ }
+
+ return 0;
+}
+
+static int igt_plane_commit(igt_plane_t *plane, igt_output_t *output)
+{
+ if (plane->is_cursor)
+ igt_cursor_commit(plane, output);
+
+ return 0;
+}
+
static int igt_output_commit(igt_output_t *output)
{
igt_display_t *display = output->display;
igt_pipe_t *pipe;
+ int i;
pipe = igt_output_get_driving_pipe(output);
if (pipe->need_set_crtc) {
@@ -1073,6 +1145,48 @@ static int igt_output_commit(igt_output_t *output)
pipe->need_set_crtc = false;
}
+ if (pipe->need_set_cursor) {
+ igt_plane_t *cursor;
+ uint32_t gem_handle, crtc_id;
+ int ret;
+
+ cursor = igt_pipe_get_plane(pipe, IGT_PLANE_CURSOR);
+ crtc_id = output->config.crtc->crtc_id;
+ gem_handle = igt_plane_get_fb_gem_handle(cursor);
+
+ if (gem_handle) {
+ LOG(display,
+ "%s: SetCursor pipe %c, fb %u %dx%d\n",
+ igt_output_name(output),
+ pipe_name(output->config.pipe),
+ gem_handle,
+ cursor->fb->width, cursor->fb->height);
+
+ ret = drmModeSetCursor(display->drm_fd, crtc_id,
+ gem_handle,
+ cursor->fb->width,
+ cursor->fb->height);
+ } else {
+ LOG(display,
+ "%s: SetCursor pipe %c, disabling\n",
+ igt_output_name(output),
+ pipe_name(output->config.pipe));
+
+ ret = drmModeSetCursor(display->drm_fd, crtc_id,
+ 0, 0, 0);
+ }
+
+ ig
Re: [Intel-gfx] [PATCH] drm/i915: Fix correct FIFO size for Baytrail
On Fri, Feb 07, 2014 at 09:56:29PM +0530, Vijay Purushothaman wrote: > On 2/7/2014 9:28 PM, Ville Syrjälä wrote: > > On Fri, Feb 07, 2014 at 08:43:12PM +0530, Vijay Purushothaman wrote: > >> B-spec says the FIFO total size is 512. So fix this to 512. > >> > >> Signed-off-by: Vijay Purushothaman > >> --- > >> drivers/gpu/drm/i915/i915_reg.h |2 +- > >> 1 file changed, 1 insertion(+), 1 deletion(-) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_reg.h > >> b/drivers/gpu/drm/i915/i915_reg.h > >> index cc3ea04..fb73031 100644 > >> --- a/drivers/gpu/drm/i915/i915_reg.h > >> +++ b/drivers/gpu/drm/i915/i915_reg.h > >> @@ -3395,7 +3395,7 @@ > >> #define I915_FIFO_LINE_SIZE 64 > >> #define I830_FIFO_LINE_SIZE 32 > >> > >> -#define VALLEYVIEW_FIFO_SIZE 255 > >> +#define VALLEYVIEW_FIFO_SIZE 511 > >> #define G4X_FIFO_SIZE127 > >> #define I965_FIFO_SIZE 512 > >> #define I945_FIFO_SIZE 127 > > > > Reviewed-by: Ville Syrjälä > > Thanks for the review. > > > > > Not that we actually use the value anywhere at the moment. > > This value is used when the display controller is configured in Max FIFO > mode. This is working fine in the android tree. At this moment i am > rewriting some logic related to this Max FIFO, memory arbiter credits > and drain latency handling for the sprite planes. I should have the > patches ready over the week end, will test it on monday once i get to > office. Oh right, we do use it in g4x_compute_wm0() which would mean this patch is actually wrong when not in maxfifo mode. We'd need to dynamically select the correct value. When not in maxfifo read the FIFO size from the DSPARB, and when in maxfifo use the 511 value. > > > > As a side note the FIFO sizing for gmch platforms seems to be a place > > where the documentation is rather poor. It kind of looks like there > > are off by one errors in the text, and yet when I was playing around > > with this stuff on gen2/gen4 machines it kind of looks like the > > hardware has the same off by one issues too. IIRC my conlusion was > > that the last cacheline in the FIFO can't actually be used. So > > specifying 511 matches with my conclusion. > > I agree.. I was thrown off by this oddity as well and it took some time > for me to understand this completely. The display block in Baytrail is a > mix and match of features from gen4 & gen5 (Cantiga, Crestline and > Ironlake). No wonder this chip has the same h/w issues.. > > > > > One other thing I did notice now that I look at our g4x/vlv watermark > > code. We seem to assume the watermarks for g4x/vlv work the same way > > as pch platforms. Ie. you specify the minimum level of data left in the > > FIFO before it needs to start fetching more. But the documentation > > suggests that it's the other way around, where you specify the max > > amount of free space allowed in the FIFO before more data needs to be > > fetched. We use the latter logic for gen2-gen4. I wonder if the spec > > is wrong, or if your code is wrong. I guess I just need to verify it > > on real hardware at some point... > > > I think this is implemented correctly in the android kernel.. On a high > level the split is something like 32 KB FIFO per pipe - 16 KB for > primary plane and 8 KB for each sprite. When we are in single display > mode we can configure the entire 64KB FIFO for the same pipe. I'm not talking about the split, but rather the actual watermark for any single plane. This is what the spec says: "Number in 64Bs of space in FIFO above which the Display A Stream will generate requests to Memory" That to me sounds like it wants the opposite value than what we program in. But I think I need to verify this at some point on some g4x machine. > There is > another trick to enable trickle feed.. With all these tricks i am seeing > good memory self refresh numbers - almost on par with the theoretical > target. I should be able to post the patch series on monday once i do > some sanity testing.. Enable trickle feed to get better power savings? Sounds strange. Trickle feed isn't really explained all that well anywhere but based on what I've gathered, my idea has been that it would keep the memory awake almost constantly by trickling in small amounts of data whenever the FIFO has a little bit of room. IIRC I did some experiments which supported that conclusion. I can't recall the specifics anymore but I think with trickle feed enabled, the watermarks were more or less useless. Only when I disabled trickle feed, the watermark level started to have a real effect (ie. set it too low and you get underruns). -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: HSW PSR fix inverted sink DP_PSR_CFG link setup.
On Fri, Feb 7, 2014 at 5:14 PM, Ville Syrjälä wrote: > On Fri, Feb 07, 2014 at 04:09:47PM -0200, Rodrigo Vivi wrote: >> As pointed out by Ville we were using inverted logic here. >> According to spec: >> For link standby mode set 170h[1] = 1. >> For full link disabling set 170h[1] = 0. >> >> Cc: Ville Syrjälä >> Signed-off-by: Rodrigo Vivi >> --- >> drivers/gpu/drm/i915/intel_dp.c | 8 >> 1 file changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c >> b/drivers/gpu/drm/i915/intel_dp.c >> index 50381f7..4ecda72 100644 >> --- a/drivers/gpu/drm/i915/intel_dp.c >> +++ b/drivers/gpu/drm/i915/intel_dp.c >> @@ -1661,12 +1661,12 @@ static void intel_edp_psr_enable_sink(struct >> intel_dp *intel_dp) >> /* Enable PSR in sink */ >> if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) >> intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, >> - DP_PSR_ENABLE & >> - ~DP_PSR_MAIN_LINK_ACTIVE); >> - else >> - intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, >> DP_PSR_ENABLE | >> DP_PSR_MAIN_LINK_ACTIVE); >> + else >> + intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, >> + DP_PSR_ENABLE & >> + ~DP_PSR_MAIN_LINK_ACTIVE); > > I think this is now the opposite of what we want. Ie. if the sink > doesn't require training we should disable the main link. Otherwise we > should keep the main link on, and that way avoid the need to train on > PSR exit. To be honest, I think I agree with you, but apparently performance counter inc improved on this way... > > Actually I'm not sure that's really what we want. I think the hardware > can do the training on its own, so in theory we should just always disable > the main link. Although the PM guide has a comment indicating that the > hardware training can fail, in which case software must repeat it. We > don't have code to do that, so I guess leaving the main link on is the > safer option. Would be nice to have a comment in the code stating as > much, if this is indeed the reason why the code was written this way. I'll do a carefull check and local tests and send new version fixed or with good comments. > >> >> /* Setup AUX registers */ >> I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); >> -- >> 1.7.11.7 > > -- > Ville Syrjälä > Intel OTC -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/6] drm/i915: get_plane_config for i9xx v10
Read out the current plane configuration at init time into a new
plane_config structure. This allows us to track any existing
framebuffers attached to the plane and potentially re-use them in our
fbdev code for a smooth handoff.
v2: update for new pitch_for_width function (Jesse)
comment how get_plane_config works with shared fbs (Jesse)
v3: s/ARGB/XRGB (Ville)
use pipesrc width/height (Ville)
fix fourcc comment (Bob)
use drm_format_plane_cpp (Ville)
v4: use fb for tracking fb data object (Ville)
v5: fix up gen2 pitch limits (Ville)
v6: read out stride as well (Daniel)
v7: split out init ordering changes (Daniel)
don't fetch config if !CONFIG_FB
v8: use proper height in get_plane_config (Chris)
v9: fix CONFIG_FB check for modular configs (Jani)
v10: add comment about stolen allocation stomping
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h |3 +
drivers/gpu/drm/i915/intel_display.c | 140 ++
drivers/gpu/drm/i915/intel_drv.h |8 ++
3 files changed, 151 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 728b9c3..bde0b47 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -393,6 +393,7 @@ struct drm_i915_error_state {
struct intel_connector;
struct intel_crtc_config;
+struct intel_plane_config;
struct intel_crtc;
struct intel_limit;
struct dpll;
@@ -431,6 +432,8 @@ struct drm_i915_display_funcs {
* fills out the pipe-config with the hw state. */
bool (*get_pipe_config)(struct intel_crtc *,
struct intel_crtc_config *);
+ void (*get_plane_config)(struct intel_crtc *,
+struct intel_plane_config *);
int (*crtc_mode_set)(struct drm_crtc *crtc,
int x, int y,
struct drm_framebuffer *old_fb);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5f0e4df..783e785 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2033,6 +2033,27 @@ unsigned long intel_gen4_compute_page_offset(int *x, int
*y,
}
}
+int intel_format_to_fourcc(int format)
+{
+ switch (format) {
+ case DISPPLANE_8BPP:
+ return DRM_FORMAT_C8;
+ case DISPPLANE_BGRX555:
+ return DRM_FORMAT_XRGB1555;
+ case DISPPLANE_BGRX565:
+ return DRM_FORMAT_RGB565;
+ default:
+ case DISPPLANE_BGRX888:
+ return DRM_FORMAT_XRGB;
+ case DISPPLANE_RGBX888:
+ return DRM_FORMAT_XBGR;
+ case DISPPLANE_BGRX101010:
+ return DRM_FORMAT_XRGB2101010;
+ case DISPPLANE_RGBX101010:
+ return DRM_FORMAT_XBGR2101010;
+ }
+}
+
static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
int x, int y)
{
@@ -5517,6 +5538,96 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
pipe_config->port_clock = clock.dot / 5;
}
+static void i9xx_get_plane_config(struct intel_crtc *crtc,
+ struct intel_plane_config *plane_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_gem_object *obj = NULL;
+ struct drm_mode_fb_cmd2 mode_cmd = { 0 };
+ u32 val, base, offset;
+ int pipe = crtc->pipe, plane = crtc->plane;
+ int fourcc, pixel_format;
+ int aligned_height;
+
+ plane_config->fb = kzalloc(sizeof(*plane_config->fb), GFP_KERNEL);
+ if (!plane_config->fb) {
+ DRM_DEBUG_KMS("failed to alloc fb\n");
+ return;
+ }
+
+ val = I915_READ(DSPCNTR(plane));
+
+ if (INTEL_INFO(dev)->gen >= 4)
+ if (val & DISPPLANE_TILED)
+ plane_config->tiled = true;
+
+ pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
+ fourcc = intel_format_to_fourcc(pixel_format);
+ plane_config->fb->base.pixel_format = fourcc;
+ plane_config->fb->base.bits_per_pixel =
+ drm_format_plane_cpp(fourcc, 0) * 8;
+
+ if (INTEL_INFO(dev)->gen >= 4) {
+ if (plane_config->tiled)
+ offset = I915_READ(DSPTILEOFF(plane));
+ else
+ offset = I915_READ(DSPLINOFF(plane));
+ base = I915_READ(DSPSURF(plane)) & 0xf000;
+ } else {
+ base = I915_READ(DSPADDR(plane));
+ }
+
+ val = I915_READ(PIPESRC(pipe));
+ plane_config->fb->base.width = ((val >> 16) & 0xfff) + 1;
+ plane_config->fb->base.height = ((val >> 0) & 0xfff) + 1;
+
+ val = I915_READ(DSPSTRIDE(pipe));
+ plane_config->fb->base.pitches[0] = val & 0xff80;
+
+ aligned_height = intel_align_height(dev, plane_config->fb-
[Intel-gfx] [PATCH 6/6] drm/i915: Wrap the preallocated BIOS framebuffer and preserve for KMS fbcon v10
Retrieve current framebuffer config info from the regs and create an fb
object for the buffer the BIOS or boot loader left us. This should
allow for smooth transitions to userspace apps once we finish the
initial configuration construction.
v2: check for non-native modes and adjust (Jesse)
fixup aperture and cmap frees (Imre)
use unlocked unref if init_bios fails (Jesse)
fix curly brace around DSPADDR check (Imre)
comment failure path for pin_and_fence (Imre)
v3: fixup fixup of aperture frees (Chris)
v4: update to current bits (locking & pin_and_fence hack) (Jesse)
v5: move fb config fetch to display code (Jesse)
re-order hw state readout on initial load to suit fb inherit (Jesse)
re-add pin_and_fence in fbdev code to make sure we refcount properly (Je
v6: rename to plane_config (Daniel)
check for valid object when initializing BIOS fb (Jesse)
split from plane_config readout and other display changes (Jesse)
drop use_bios_fb option (Chris)
update comments (Jesse)
rework fbdev_init_bios for clarity (Jesse)
drop fb obj ref under lock (Chris)
v7: use fb object from plane_config instead (Ville)
take ref on fb object (Jesse)
v8: put under i915_fastboot option (Jesse)
fix fb ptr checking (Jesse)
inform drm_fb_helper if we fail to enable a connector (Jesse)
drop unnecessary enabled[] modifications in failure cases (Chris)
split from BIOS connector config readout (Daniel)
don't memset the fb buffer if preallocated (Chris)
alloc ifbdev up front and pass to init_bios (Chris)
check for bad ifbdev in restore_mode too (Chris)
v9: fix up !fastboot bpp setting (Jesse)
fix up !fastboot helper alloc (Jesse)
make sure BIOS fb is sufficient for biggest active pipe (Jesse)
v10:fix up size calculation for proposed fbs (Chris)
go back to two pass pipe fb assignment (Chris)
add warning for active pipes w/o fbs (Chris)
clean up num_pipes checks in fbdev_init and fbdev_restore_mode (Chris)
move i915.fastboot into fbdev_init (Chris)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_drv.h |1 +
drivers/gpu/drm/i915/intel_fbdev.c | 155 +---
2 files changed, 145 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8f5e798..80e6ad2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -113,6 +113,7 @@ struct intel_fbdev {
struct intel_framebuffer *fb;
struct list_head fbdev_list;
struct drm_display_mode *our_mode;
+ int preferred_bpp;
};
struct intel_encoder {
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
b/drivers/gpu/drm/i915/intel_fbdev.c
index 8ce3405..71a57ed 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -132,6 +132,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
struct drm_framebuffer *fb;
struct drm_i915_gem_object *obj;
int size, ret;
+ bool prealloc = false;
mutex_lock(&dev->struct_mutex);
@@ -143,6 +144,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
intel_fb = ifbdev->fb;
} else {
DRM_DEBUG_KMS("re-using BIOS fb\n");
+ prealloc = true;
sizes->fb_width = intel_fb->base.width;
sizes->fb_height = intel_fb->base.height;
}
@@ -204,7 +206,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
* If the object is stolen however, it will be full of whatever
* garbage was left in there.
*/
- if (ifbdev->fb->obj->stolen)
+ if (ifbdev->fb->obj->stolen && !prealloc)
memset_io(info->screen_base, 0, info->screen_size);
/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
@@ -319,7 +321,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper
*fb_helper,
}
if (!to_intel_crtc(encoder->crtc)->active) {
- DRM_DEBUG_KMS("connector %s on inactive crtc %d,
borting\n",
+ DRM_DEBUG_KMS("connector %s on inactive crtc %d,
aborting\n",
drm_get_connector_name(connector),
encoder->crtc->base.id);
return false;
@@ -364,27 +366,156 @@ static void intel_fbdev_destroy(struct drm_device *dev,
kfree(ifbdev->fb);
}
+/*
+ * Build an intel_fbdev struct using a BIOS allocated framebuffer, if possible.
+ * The core display code will have read out the current plane configuration,
+ * so we use that to figure out if there's an object for us to use as the
+ * fb, and if so, we re-use it for the fbdev configuration.
+ *
+ * Note we only support a single fb shared across pipes for boot (mostly for
+ * fbcon), so we just find the biggest and use that.
+ */
+static bool intel_fbdev_init_bios(str
Re: [Intel-gfx] [PATCH 4/7] drm/i915: Disable SF pipelined attribute fetch for SNB
On 02/04/2014 11:59 AM, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > According to Bspec we need to disable SF pipelined attribute fetch > whenever SF outputs exceed 16 and normal clip mode is used. A quick > glance at Mesa suggests that these conditions could happen. So let's > just always set the magic bit. > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/i915_reg.h | 3 ++- > drivers/gpu/drm/i915/intel_pm.c | 8 > 2 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 7aa2cf5..0334507 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -790,7 +790,8 @@ > #define _3D_CHICKEN3 0x02090 > #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) > #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) > -#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)((x)<<1) > +#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)((x)<<1) /* gen8+ */ > +#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH(1 << 1) /* > gen6 */ > > #define MI_MODE 0x0209c > # define VS_TIMER_DISPATCH (1 << 6) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 6a09281..7247084 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4683,6 +4683,14 @@ static void gen6_init_clock_gating(struct drm_device > *dev) > _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); > > /* > + * Bspec says: > + * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and > + * 3DSTATE_SF number of SF output attributes is more than 16." > + */ > + I915_WRITE(_3D_CHICKEN3, > + > _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); > + > + /* >* According to the spec the following bits should be >* set in order to enable memory self-refresh and fbc: >* The bit21 and bit22 of 0x42000 > I'm almost positive Mesa will hit this case. Nice catch! Reviewed-by: Kenneth Graunke signature.asc Description: OpenPGP digital signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/6] drm/i915: alloc intel_fb in the intel_fbdev struct
Allocate this struct instead, so we can re-use another allocated
elsewhere if needed.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c |4 ++--
drivers/gpu/drm/i915/intel_drv.h |2 +-
drivers/gpu/drm/i915/intel_fbdev.c | 27 +++
3 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 450bb40..112da42 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7975,11 +7975,11 @@ mode_fits_in_fbdev(struct drm_device *dev,
if (dev_priv->fbdev == NULL)
return NULL;
- obj = dev_priv->fbdev->ifb.obj;
+ obj = dev_priv->fbdev->fb->obj;
if (obj == NULL)
return NULL;
- fb = &dev_priv->fbdev->ifb.base;
+ fb = &dev_priv->fbdev->fb->base;
if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
fb->bits_per_pixel))
return NULL;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1e5a0a6..8f5e798 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -110,7 +110,7 @@ struct intel_framebuffer {
struct intel_fbdev {
struct drm_fb_helper helper;
- struct intel_framebuffer ifb;
+ struct intel_framebuffer *fb;
struct list_head fbdev_list;
struct drm_display_mode *our_mode;
};
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
b/drivers/gpu/drm/i915/intel_fbdev.c
index d6a8a71..fb07ba6 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -62,11 +62,20 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
{
struct intel_fbdev *ifbdev =
container_of(helper, struct intel_fbdev, helper);
+ struct intel_framebuffer *fb;
struct drm_device *dev = helper->dev;
struct drm_mode_fb_cmd2 mode_cmd = {};
struct drm_i915_gem_object *obj;
int size, ret;
+ fb = kzalloc(sizeof(*fb), GFP_KERNEL);
+ if (!fb) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ ifbdev->fb = fb;
+
/* we don't do packed 24bpp */
if (sizes->surface_bpp == 24)
sizes->surface_bpp = 32;
@@ -97,7 +106,7 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
goto out_unref;
}
- ret = intel_framebuffer_init(dev, &ifbdev->ifb, &mode_cmd, obj);
+ ret = intel_framebuffer_init(dev, ifbdev->fb, &mode_cmd, obj);
if (ret)
goto out_unpin;
@@ -116,7 +125,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
{
struct intel_fbdev *ifbdev =
container_of(helper, struct intel_fbdev, helper);
- struct intel_framebuffer *intel_fb = &ifbdev->ifb;
+ struct intel_framebuffer *intel_fb = ifbdev->fb;
struct drm_device *dev = helper->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct fb_info *info;
@@ -126,11 +135,12 @@ static int intelfb_create(struct drm_fb_helper *helper,
mutex_lock(&dev->struct_mutex);
- if (!intel_fb->obj) {
+ if (!intel_fb || !intel_fb->obj) {
DRM_DEBUG_KMS("no BIOS fb, allocating a new one\n");
ret = intelfb_alloc(helper, sizes);
if (ret)
goto out_unlock;
+ intel_fb = ifbdev->fb;
} else {
DRM_DEBUG_KMS("re-using BIOS fb\n");
sizes->fb_width = intel_fb->base.width;
@@ -148,7 +158,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
info->par = helper;
- fb = &ifbdev->ifb.base;
+ fb = &ifbdev->fb->base;
ifbdev->helper.fb = fb;
ifbdev->helper.fbdev = info;
@@ -194,7 +204,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
* If the object is stolen however, it will be full of whatever
* garbage was left in there.
*/
- if (ifbdev->ifb.obj->stolen)
+ if (ifbdev->fb->obj->stolen)
memset_io(info->screen_base, 0, info->screen_size);
/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
@@ -258,8 +268,9 @@ static void intel_fbdev_destroy(struct drm_device *dev,
drm_fb_helper_fini(&ifbdev->helper);
- drm_framebuffer_unregister_private(&ifbdev->ifb.base);
- intel_framebuffer_fini(&ifbdev->ifb);
+ drm_framebuffer_unregister_private(&ifbdev->fb->base);
+ intel_framebuffer_fini(ifbdev->fb);
+ kfree(ifbdev->fb);
}
int intel_fbdev_init(struct drm_device *dev)
@@ -322,7 +333,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int
state)
* been restored from swap. If the object is stolen however, it will be
* full of whatever garbage was left
[Intel-gfx] [PATCH 5/6] drm/i915: allow re-use BIOS connector config for initial fbdev config
The BIOS or boot loader will generally create an initial display
configuration for us that includes some set of active pipes and
displays. This routine tries to figure out which pipes and connectors
are active and stuffs them into the crtcs and modes array given to us by
the drm_fb_helper code.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_fbdev.c | 91
1 file changed, 91 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
b/drivers/gpu/drm/i915/intel_fbdev.c
index fb07ba6..8ce3405 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -246,6 +246,97 @@ static void intel_crtc_fb_gamma_get(struct drm_crtc *crtc,
u16 *red, u16 *green,
*blue = intel_crtc->lut_b[regno] << 8;
}
+static struct drm_fb_helper_crtc *
+intel_fb_helper_crtc(struct drm_fb_helper *fb_helper, struct drm_crtc *crtc)
+{
+ int i;
+
+ for (i = 0; i < fb_helper->crtc_count; i++)
+ if (fb_helper->crtc_info[i].mode_set.crtc == crtc)
+ return &fb_helper->crtc_info[i];
+
+ return NULL;
+}
+
+/*
+ * Try to read the BIOS display configuration and use it for the initial
+ * fb configuration.
+ *
+ * The BIOS or boot loader will generally create an initial display
+ * configuration for us that includes some set of active pipes and displays.
+ * This routine tries to figure out which pipes and connectors are active
+ * and stuffs them into the crtcs and modes array given to us by the
+ * drm_fb_helper code.
+ *
+ * The overall sequence is:
+ * intel_fbdev_init - from driver load
+ * intel_fbdev_init_bios - initialize the intel_fbdev using BIOS data
+ * drm_fb_helper_init - build fb helper structs
+ * drm_fb_helper_single_add_all_connectors - more fb helper structs
+ * intel_fbdev_initial_config - apply the config
+ * drm_fb_helper_initial_config - call ->probe then register_framebuffer()
+ * drm_setup_crtcs - build crtc config for fbdev
+ * intel_fb_initial_config - find active connectors etc
+ * drm_fb_helper_single_fb_probe - set up fbdev
+ * intelfb_create - re-use or alloc fb, build out fbdev structs
+ *
+ * If the BIOS or boot loader leaves the display in VGA mode, there's not
+ * much we can do; switching out of that mode involves allocating a new,
+ * high res buffer, and also recalculating bandwidth requirements for the
+ * new bpp configuration.
+ */
+static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
+ struct drm_fb_helper_crtc **crtcs,
+ struct drm_display_mode **modes,
+ bool *enabled, int width, int height)
+{
+ int i;
+
+ for (i = 0; i < fb_helper->connector_count; i++) {
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
+
+ connector = fb_helper->connector_info[i]->connector;
+ if (!enabled[i]) {
+ DRM_DEBUG_KMS("connector %d not enabled, skipping\n",
+ connector->base.id);
+ continue;
+ }
+
+ encoder = connector->encoder;
+ if (!encoder || !encoder->crtc) {
+ DRM_DEBUG_KMS("connector %d has no encoder or crtc,
skipping\n",
+ connector->base.id);
+ enabled[i] = false;
+ continue;
+ }
+
+ if (WARN_ON(!encoder->crtc->enabled)) {
+ DRM_DEBUG_KMS("connector %s on crtc %d has inconsistent
state, aborting\n",
+ drm_get_connector_name(connector),
+ encoder->crtc->base.id);
+ return false;
+ }
+
+ if (!to_intel_crtc(encoder->crtc)->active) {
+ DRM_DEBUG_KMS("connector %s on inactive crtc %d,
borting\n",
+ drm_get_connector_name(connector),
+ encoder->crtc->base.id);
+ return false;
+ }
+
+ modes[i] = &encoder->crtc->mode;
+ crtcs[i] = intel_fb_helper_crtc(fb_helper, encoder->crtc);
+
+ DRM_DEBUG_KMS("connector %s on crtc %d: %s\n",
+ drm_get_connector_name(connector),
+ encoder->crtc->base.id,
+ modes[i]->name);
+ }
+
+ return true;
+}
+
static struct drm_fb_helper_funcs intel_fb_helper_funcs = {
.gamma_set = intel_crtc_fb_gamma_set,
.gamma_get = intel_crtc_fb_gamma_get,
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/6] drm/i915: split aligned height calculation out v2
For use by get_plane_config.
v2: cleanup tile_height bits (Chris)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4d4a0d9..5f0e4df 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1929,6 +1929,14 @@ static bool need_vtd_wa(struct drm_device *dev)
return false;
}
+static int intel_align_height(struct drm_device *dev, int height, bool tiled)
+{
+ int tile_height;
+
+ tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
+ return ALIGN(height, tile_height);
+}
+
int
intel_pin_and_fence_fb_obj(struct drm_device *dev,
struct drm_i915_gem_object *obj,
@@ -10559,7 +10567,7 @@ int intel_framebuffer_init(struct drm_device *dev,
struct drm_mode_fb_cmd2 *mode_cmd,
struct drm_i915_gem_object *obj)
{
- int aligned_height, tile_height;
+ int aligned_height;
int pitch_limit;
int ret;
@@ -10653,9 +10661,8 @@ int intel_framebuffer_init(struct drm_device *dev,
if (mode_cmd->offsets[0] != 0)
return -EINVAL;
- tile_height = IS_GEN2(dev) ? 16 : 8;
- aligned_height = ALIGN(mode_cmd->height,
- obj->tiling_mode ? tile_height : 1);
+ aligned_height = intel_align_height(dev, mode_cmd->height,
+ obj->tiling_mode);
/* FIXME drm helper for size checks (especially planar formats)? */
if (obj->base.size < aligned_height * mode_cmd->pitches[0])
return -EINVAL;
--
1.7.9.5
___
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/6] drm/i915: get_plane_config support for ILK+
This should allow BIOS fb inheritance to work on ILK+ machines too.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 92 ++
1 file changed, 92 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 783e785..450bb40 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6571,6 +6571,96 @@ static void ironlake_get_pfit_config(struct intel_crtc
*crtc,
}
}
+static void ironlake_get_plane_config(struct intel_crtc *crtc,
+ struct intel_plane_config *plane_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_gem_object *obj = NULL;
+ struct drm_mode_fb_cmd2 mode_cmd = { 0 };
+ u32 val, base, offset;
+ int pipe = crtc->pipe, plane = crtc->plane;
+ int fourcc, pixel_format;
+ int aligned_height;
+
+ plane_config->fb = kzalloc(sizeof(*plane_config->fb), GFP_KERNEL);
+ if (!plane_config->fb) {
+ DRM_DEBUG_KMS("failed to alloc fb\n");
+ return;
+ }
+
+ val = I915_READ(DSPCNTR(plane));
+
+ if (INTEL_INFO(dev)->gen >= 4)
+ if (val & DISPPLANE_TILED)
+ plane_config->tiled = true;
+
+ pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
+ fourcc = intel_format_to_fourcc(pixel_format);
+ plane_config->fb->base.pixel_format = fourcc;
+ plane_config->fb->base.bits_per_pixel =
+ drm_format_plane_cpp(fourcc, 0) * 8;
+
+ base = I915_READ(DSPSURF(plane)) & 0xf000;
+ if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+ offset = I915_READ(DSPOFFSET(plane));
+ } else {
+ if (plane_config->tiled)
+ offset = I915_READ(DSPTILEOFF(plane));
+ else
+ offset = I915_READ(DSPLINOFF(plane));
+ }
+
+ val = I915_READ(PIPESRC(pipe));
+ plane_config->fb->base.width = ((val >> 16) & 0xfff) + 1;
+ plane_config->fb->base.height = ((val >> 0) & 0xfff) + 1;
+
+ val = I915_READ(DSPSTRIDE(pipe));
+ plane_config->fb->base.pitches[0] = val & 0xff80;
+
+ aligned_height = intel_align_height(dev, plane_config->fb->base.height,
+ plane_config->tiled);
+
+ plane_config->size = ALIGN(plane_config->fb->base.pitches[0] *
+ aligned_height, PAGE_SIZE);
+
+ DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x,
pitch %d, size 0x%x\n",
+ pipe, plane, plane_config->fb->base.width,
+ plane_config->fb->base.height,
+ plane_config->fb->base.bits_per_pixel, base,
+ plane_config->fb->base.pitches[0],
+ plane_config->size);
+
+ /*
+* If the fb is shared between multiple heads, we'll just get the
+* first one.
+*/
+ obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
+
plane_config->size);
+ if (!obj)
+ return;
+
+ mode_cmd.pixel_format = fourcc;
+ mode_cmd.width = plane_config->fb->base.width;
+ mode_cmd.height = plane_config->fb->base.height;
+ mode_cmd.pitches[0] = plane_config->fb->base.pitches[0];
+
+ mutex_lock(&dev->struct_mutex);
+
+ if (intel_framebuffer_init(dev, plane_config->fb, &mode_cmd, obj)) {
+ DRM_DEBUG_KMS("intel fb init failed\n");
+ goto out_unref_obj;
+ }
+
+ mutex_unlock(&dev->struct_mutex);
+ DRM_DEBUG_KMS("plane fb obj %p\n", plane_config->fb->obj);
+ return;
+
+out_unref_obj:
+ drm_gem_object_unreference(&obj->base);
+ mutex_unlock(&dev->struct_mutex);
+}
+
static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_config *pipe_config)
{
@@ -10833,6 +10923,7 @@ static void intel_init_display(struct drm_device *dev)
if (HAS_DDI(dev)) {
dev_priv->display.get_pipe_config = haswell_get_pipe_config;
+ dev_priv->display.get_plane_config = ironlake_get_plane_config;
dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
dev_priv->display.crtc_enable = haswell_crtc_enable;
dev_priv->display.crtc_disable = haswell_crtc_disable;
@@ -10840,6 +10931,7 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.update_plane = ironlake_update_plane;
} else if (HAS_PCH_SPLIT(dev)) {
dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
+ dev_priv->display.get_plane_config = ironlake_get_plane_config;
dev_priv
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add Baytrail PSR Support.
On Fri, Feb 07, 2014 at 04:05:26PM -0200, Rodrigo Vivi wrote:
> On Fri, Feb 7, 2014 at 3:24 PM, Ville Syrjälä
> wrote:
> > On Wed, Feb 05, 2014 at 05:04:31PM -0200, Rodrigo Vivi wrote:
> >> This patch adds PSR Support to Baytrail.
> >>
> >> Baytrail cannot easily detect screen updates and force PSR exit.
> >> So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy}
> >> and update to enable it back on next display mark_idle.
> >>
> >> v2: Also inactivate PSR on cursor update.
> >> v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
> >> early on page flip besides avoid initializing inactive/active flag
> >> more than once.
> >> v4: Fix identation issues.
> >> v5: Rebase and add Baytrail per pipe support although leaving PIPE_B
> >> support disabled by for now since it isn't working properly yet.
> >> v6: Removing forgotten comment and useless clkgating definition.
> >> v7: Remove inactivate from set_domain. Chris warned this was semanticaly
> >> wrong.
> >> v8: Accept Ville's suggestions: Use register's names matching spec and
> >> warn if transition took longer than it should.
> >> v9: New version with delayed work to get PSR back. Disabling it on
> >> set_domain but not rescheduing it back until next finish_page_flip.
> >>
> >> Cc: Chris Wilson
> >> Cc: Ville Syrjälä
> >> Signed-off-by: Rodrigo Vivi
> >> ---
> >> drivers/gpu/drm/i915/i915_debugfs.c | 36 -
> >> drivers/gpu/drm/i915/i915_drv.h | 5 +-
> >> drivers/gpu/drm/i915/i915_gem.c | 12 ++
> >> drivers/gpu/drm/i915/i915_reg.h | 37 +
> >> drivers/gpu/drm/i915/i915_suspend.c | 2 +-
> >> drivers/gpu/drm/i915/intel_display.c | 18 ++-
> >> drivers/gpu/drm/i915/intel_dp.c | 256
> >> ++-
> >> drivers/gpu/drm/i915/intel_drv.h | 1 +
> >> 8 files changed, 323 insertions(+), 44 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> >> b/drivers/gpu/drm/i915/i915_debugfs.c
> >> index bc8707f..2949c48 100644
> >> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> >> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> >> @@ -1900,6 +1900,8 @@ static int i915_edp_psr_status(struct seq_file *m,
> >> void *data)
> >> struct drm_device *dev = node->minor->dev;
> >> struct drm_i915_private *dev_priv = dev->dev_private;
> >> u32 psrperf = 0;
> >> + u32 statA = 0;
> >> + u32 statB = 0;
> >> bool enabled = false;
> >>
> >> intel_runtime_pm_get(dev_priv);
> >> @@ -1907,14 +1909,38 @@ static int i915_edp_psr_status(struct seq_file *m,
> >> void *data)
> >> seq_printf(m, "Sink_Support: %s\n",
> >> yesno(dev_priv->psr.sink_support));
> >> seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
> >>
> >> - enabled = HAS_PSR(dev) &&
> >> - I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
> >> - seq_printf(m, "Enabled: %s\n", yesno(enabled));
> >> + if (HAS_PSR(dev)) {
> >> + if (IS_VALLEYVIEW(dev)) {
> >> + statA = I915_READ(VLV_PSRSTAT(PIPE_A)) &
> >> + VLV_EDP_PSR_CURR_STATE_MASK;
> >> + statB = I915_READ(VLV_PSRSTAT(PIPE_B)) &
> >> + VLV_EDP_PSR_CURR_STATE_MASK;
> >> + enabled = ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
> >> +(statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE) ||
> >> +(statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
> >> +(statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE));
> >> + } else
> >> + enabled = I915_READ(EDP_PSR_CTL(dev)) &
> >> EDP_PSR_ENABLE;
> >> + }
> >> + seq_printf(m, "Enabled: %s", yesno(enabled));
> >>
> >> - if (HAS_PSR(dev))
> >> + if (IS_VALLEYVIEW(dev)) {
> >> + if ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
> >> + (statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
> >> + seq_puts(m, " pipe A");
> >> + if ((statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
> >> + (statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
> >> + seq_puts(m, " pipe B");
> >> + }
> >> +
> >> + seq_puts(m, "\n");
> >> +
> >> + /* VLV PSR has no kind of performance counter */
> >> + if (HAS_PSR(dev) && !IS_VALLEYVIEW(dev)) {
> >> psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
> >> EDP_PSR_PERF_CNT_MASK;
> >> - seq_printf(m, "Performance_Counter: %u\n", psrperf);
> >> + seq_printf(m, "Performance_Counter: %u\n", psrperf);
> >> + }
> >>
> >> intel_runtime_pm_put(dev_priv);
> >> return 0;
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> >> b/drivers/gpu/drm/i915/i915_drv.h
> >> index 21470be..87c346a 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -747,7 +747,9 @@ struct i915_psr {
> >> boo
Re: [Intel-gfx] intel_sdvo_init: trying to register non-static key
On Fri, 2014-02-07 at 15:51 +0100, Daniel Vetter wrote: > On Fri, Feb 07, 2014 at 12:28:09PM +0100, Borislav Petkov wrote: > > On Fri, Feb 07, 2014 at 01:12:22PM +0200, Imre Deak wrote: > > > On Fri, 2014-02-07 at 13:04 +0200, Jani Nikula wrote: > > > > Imre, is this the same i2c_del_adapter issue you're looking at? Any > > > > patches to try yet? > > > > > > It looks like the same issue yes. The following patch fixed it for me: > > > > > > http://patchwork.freedesktop.org/patch/18698/ > > > > > > I'm working on an improved version of this, but the main thing - to > > > remove the connector's sysfs entries before actually destroying the > > > encoder and connector objects - will remain the same as in the above > > > patch. > > > > You could shoot the final version my way so that I give it a run too. > > The final version will only change the code layout a bit, but not the > logic. So a tested-by from you for v1 would be helpful anyway, to make > really sure you've reported the same issue. If that's not the case then we > need to dig deeper, so better not to waste a few days waiting for v2. I just realized it's a different issue, since it's on the init path. Also we set the drm device as the parent for the sdvo i2c adapter as opposed to the dp i2c adapter where it's the connector device. So the above patch won't help in Borislav's case. I'm looking into this issue anyway. --Imre > -Daniel signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 11/11] drm/i915: Calling rotate and inverse rotate transformations after clipping
From: Sagar Kamble
With clipped sprites these transformations are not working. these
functions transform complete sprite irrespective of clipping present.
This leads to invisible portion of sprite show up when rotate 180 if
it was out of visible area before.
v4: Moved rotate transform for source rectangle after clipping.
Added rotate and inverse rotate transform for destination rect.
Signed-off-by: Sagar Kamble
Tested-by: Sagar Kamble
---
drivers/gpu/drm/i915/intel_sprite.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 62b9f84..799f6a9 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -769,9 +769,6 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
max_scale = intel_plane->max_downscale << 16;
min_scale = intel_plane->can_scale ? 1 : (1 << 16);
- drm_rect_rotate(&src, fb->width << 16, fb->height << 16,
- intel_plane->rotation);
-
hscale = drm_rect_calc_hscale_relaxed(&src, &dst, min_scale, max_scale);
BUG_ON(hscale < 0);
@@ -785,6 +782,13 @@ intel_update_plane(struct drm_plane *plane, struct
drm_crtc *crtc,
crtc_w = drm_rect_width(&dst);
crtc_h = drm_rect_height(&dst);
+ drm_rect_rotate(&src, fb->width << 16, fb->height << 16,
+ intel_plane->rotation);
+
+ drm_rect_rotate(&dst, intel_crtc->config.pipe_src_w,
+ intel_crtc->config.pipe_src_h,
+ intel_plane->rotation);
+
if (visible) {
/* check again in case clipping clamped the results */
hscale = drm_rect_calc_hscale(&src, &dst, min_scale, max_scale);
@@ -811,7 +815,11 @@ intel_update_plane(struct drm_plane *plane, struct
drm_crtc *crtc,
drm_rect_height(&dst) * vscale -
drm_rect_height(&src));
drm_rect_rotate_inv(&src, fb->width << 16, fb->height << 16,
- intel_plane->rotation);
+ intel_plane->rotation);
+
+ drm_rect_rotate_inv(&dst, intel_crtc->config.pipe_src_w,
+ intel_crtc->config.pipe_src_h,
+ intel_plane->rotation);
/* sanity check to make sure the src viewport wasn't enlarged */
WARN_ON(src.x1 < (int) src_x ||
--
1.8.5
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add Baytrail PSR Support.
On Fri, Feb 7, 2014 at 3:24 PM, Ville Syrjälä
wrote:
> On Wed, Feb 05, 2014 at 05:04:31PM -0200, Rodrigo Vivi wrote:
>> This patch adds PSR Support to Baytrail.
>>
>> Baytrail cannot easily detect screen updates and force PSR exit.
>> So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy}
>> and update to enable it back on next display mark_idle.
>>
>> v2: Also inactivate PSR on cursor update.
>> v3: Inactivate PSR on mark_busy, dset_domain and sw_finish_ioctl, and
>> early on page flip besides avoid initializing inactive/active flag
>> more than once.
>> v4: Fix identation issues.
>> v5: Rebase and add Baytrail per pipe support although leaving PIPE_B
>> support disabled by for now since it isn't working properly yet.
>> v6: Removing forgotten comment and useless clkgating definition.
>> v7: Remove inactivate from set_domain. Chris warned this was semanticaly
>> wrong.
>> v8: Accept Ville's suggestions: Use register's names matching spec and
>> warn if transition took longer than it should.
>> v9: New version with delayed work to get PSR back. Disabling it on
>> set_domain but not rescheduing it back until next finish_page_flip.
>>
>> Cc: Chris Wilson
>> Cc: Ville Syrjälä
>> Signed-off-by: Rodrigo Vivi
>> ---
>> drivers/gpu/drm/i915/i915_debugfs.c | 36 -
>> drivers/gpu/drm/i915/i915_drv.h | 5 +-
>> drivers/gpu/drm/i915/i915_gem.c | 12 ++
>> drivers/gpu/drm/i915/i915_reg.h | 37 +
>> drivers/gpu/drm/i915/i915_suspend.c | 2 +-
>> drivers/gpu/drm/i915/intel_display.c | 18 ++-
>> drivers/gpu/drm/i915/intel_dp.c | 256
>> ++-
>> drivers/gpu/drm/i915/intel_drv.h | 1 +
>> 8 files changed, 323 insertions(+), 44 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>> b/drivers/gpu/drm/i915/i915_debugfs.c
>> index bc8707f..2949c48 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -1900,6 +1900,8 @@ static int i915_edp_psr_status(struct seq_file *m,
>> void *data)
>> struct drm_device *dev = node->minor->dev;
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> u32 psrperf = 0;
>> + u32 statA = 0;
>> + u32 statB = 0;
>> bool enabled = false;
>>
>> intel_runtime_pm_get(dev_priv);
>> @@ -1907,14 +1909,38 @@ static int i915_edp_psr_status(struct seq_file *m,
>> void *data)
>> seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
>> seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
>>
>> - enabled = HAS_PSR(dev) &&
>> - I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
>> - seq_printf(m, "Enabled: %s\n", yesno(enabled));
>> + if (HAS_PSR(dev)) {
>> + if (IS_VALLEYVIEW(dev)) {
>> + statA = I915_READ(VLV_PSRSTAT(PIPE_A)) &
>> + VLV_EDP_PSR_CURR_STATE_MASK;
>> + statB = I915_READ(VLV_PSRSTAT(PIPE_B)) &
>> + VLV_EDP_PSR_CURR_STATE_MASK;
>> + enabled = ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
>> +(statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE) ||
>> +(statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
>> +(statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE));
>> + } else
>> + enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
>> + }
>> + seq_printf(m, "Enabled: %s", yesno(enabled));
>>
>> - if (HAS_PSR(dev))
>> + if (IS_VALLEYVIEW(dev)) {
>> + if ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
>> + (statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
>> + seq_puts(m, " pipe A");
>> + if ((statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
>> + (statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
>> + seq_puts(m, " pipe B");
>> + }
>> +
>> + seq_puts(m, "\n");
>> +
>> + /* VLV PSR has no kind of performance counter */
>> + if (HAS_PSR(dev) && !IS_VALLEYVIEW(dev)) {
>> psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
>> EDP_PSR_PERF_CNT_MASK;
>> - seq_printf(m, "Performance_Counter: %u\n", psrperf);
>> + seq_printf(m, "Performance_Counter: %u\n", psrperf);
>> + }
>>
>> intel_runtime_pm_put(dev_priv);
>> return 0;
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 21470be..87c346a 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -747,7 +747,9 @@ struct i915_psr {
>> bool sink_support;
>> bool source_ok;
>> bool setup_done;
>> + bool active;
>> struct mutex lock;
>> + struct delayed_work work;
>> };
>>
>> enum intel_pch {
>> @@ -1867,7 +1869,8 @@ struct drm_i915_file_private {
>>
>> #define HAS_DDI(dev) (INTEL_INFO
Re: [Intel-gfx] [PATCH 0/5] Add power feature debugfs disabling
On Thu, Feb 06, 2014 at 05:37:29PM +0100, Daniel Vetter wrote: > On Thu, Feb 6, 2014 at 4:44 PM, Jeff McGee wrote: > > Our Android system validation tests are expecting these interfaces. That's > > not igt, I know, but is supporting downstream test suites a priority? I can > > get our val guys on the list to +1 the need for these patches. Likewise I > > can request a developer from my team to review these patches. Or are you > > looking specifically for someone outside our downstream product to 2nd the > > need-for and quality of the patches? > > I don't mind if something is only used in one product - if it's useful > sooner or later other product teams will pick up on in. So upstreaming > is the right thing. But if you add a debugfs for tests I also want to > have the tests upstreamed for the following reasons: > > - If a product team deems it useful to test something, our upstream QA > should probably do the same. > > - Without testcases actually using these on upstream there's a good > chance that we'll break them. Which means forward-rolling to new > forklifts will be more of a pain than strictly needed. We already have > our issues with upstream collaboration, no need to make it more ugly. > > - For interfaces used in tests/scripts I also want to do a bit of api > review, which is best done by looking at the actual users. Ofc debugfs > doesn't have strict abi guarantees imposed by the linux community like > ioctls/sysfs which we're essentially never allowed to break. But > change the interfaces still has its costs. > > Cheers, Daniel Thanks for the clarification. I think there is a willingness from our Android teams, both dev and val, to invest in igt as we've just started to do. I don't know the history well, but we obvious have a lot invested in our own test suites, and so bridging those with igt will take time and may occur on the back burner while the focus has to be on Android product. -Jeff ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 04/28] lib: Introduce a for_each_connected_output() macro
So we can easily cycle through them in tests without knowing too many internal details about how igt_display_t organize its data. Signed-off-by: Damien Lespiau --- lib/igt_kms.h | 4 1 file changed, 4 insertions(+) diff --git a/lib/igt_kms.h b/lib/igt_kms.h index 80cdfb6..1d06767 100644 --- a/lib/igt_kms.h +++ b/lib/igt_kms.h @@ -158,5 +158,9 @@ igt_plane_t *igt_ouput_get_plane(igt_output_t *output, enum igt_plane plane); void igt_plane_set_fb(igt_plane_t *plane, struct kmstest_fb *fb); +#define for_each_connected_output(display, output) \ + for (int i__ = 0; i__ < (display)->n_outputs; i__++) \ + if ((output = &(display)->outputs[i__]), output->valid) + #endif /* __IGT_KMS_H__ */ -- 1.8.3.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 05/28] kms_pipe_crc_basic: Use for_each_connected_output()
Signed-off-by: Damien Lespiau
---
tests/kms_pipe_crc_basic.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/tests/kms_pipe_crc_basic.c b/tests/kms_pipe_crc_basic.c
index fdec077..7d48ca6 100644
--- a/tests/kms_pipe_crc_basic.c
+++ b/tests/kms_pipe_crc_basic.c
@@ -81,16 +81,13 @@ static void test_read_crc(data_t *data, int pipe, unsigned
flags)
igt_display_t *display = &data->display;
igt_pipe_crc_t *pipe_crc;
igt_crc_t *crcs = NULL;
- int valid_connectors = 0, i;
+ int valid_connectors = 0;
+ igt_output_t *output;
- for (i = 0; i < display->n_outputs; i++) {
- igt_output_t *output = &display->outputs[i];
+ for_each_connected_output(display, output) {
igt_plane_t *primary;
drmModeModeInfo *mode;
- if (!output->valid)
- continue;
-
igt_output_set_pipe(output, pipe);
fprintf(stdout, "%s: Testing connector %s using pipe %c\n",
--
1.8.3.1
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[Intel-gfx] [PATCH igt 16/28] lib/crc: Add a helper to read a single CRC value
In this case, we also take care of starting/stopping the CRC collection.
Signed-off-by: Damien Lespiau
---
lib/igt_debugfs.c | 14 ++
lib/igt_debugfs.h | 1 +
2 files changed, 15 insertions(+)
diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index a0d84bf..4a4a4dd 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -342,6 +342,20 @@ igt_pipe_crc_get_crcs(igt_pipe_crc_t *pipe_crc, int n_crcs,
}
/*
+ * Read 1 CRC from @pipe_crc. This function blocks until the CRC is retrieved.
+ * @out_crc must be allocated by the caller.
+ *
+ * This function takes care of the pipe_crc book-keeping, it will start/stop
+ * the collection of the CRC.
+ */
+void igt_pipe_crc_collect_crc(igt_pipe_crc_t *pipe_crc, igt_crc_t *out_crc)
+{
+ igt_pipe_crc_start(pipe_crc);
+ read_one_crc(pipe_crc, out_crc);
+ igt_pipe_crc_stop(pipe_crc);
+}
+
+/*
* Drop caches
*/
diff --git a/lib/igt_debugfs.h b/lib/igt_debugfs.h
index 075e446..6b7e623 100644
--- a/lib/igt_debugfs.h
+++ b/lib/igt_debugfs.h
@@ -79,6 +79,7 @@ void igt_pipe_crc_start(igt_pipe_crc_t *pipe_crc);
void igt_pipe_crc_stop(igt_pipe_crc_t *pipe_crc);
void igt_pipe_crc_get_crcs(igt_pipe_crc_t *pipe_crc, int n_crcs,
igt_crc_t **out_crcs);
+void igt_pipe_crc_collect_crc(igt_pipe_crc_t *pipe_crc, igt_crc_t *out_crc);
/*
* Drop caches
--
1.8.3.1
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Re: [Intel-gfx] [PATCH 1/2] tests/pm_rps: Round requested freq correctly
On Fri, Feb 07, 2014 at 11:15:15AM +0100, Daniel Vetter wrote:
> On Fri, Feb 7, 2014 at 10:33 AM, Chris Wilson
> wrote:
> > On Fri, Feb 07, 2014 at 10:03:33AM +0100, Daniel Vetter wrote:
> >> The kernel will round it, so if we don't we'll have a spurious
> >> mismatch. Happens on my machine here with 650-1300MHz range, where the
> >> midpoint is 975.
> >>
> >> Cc: Jeff McGee
> >> Signed-off-by: Daniel Vetter
> >> ---
> >> tests/pm_rps.c | 3 +++
> >> 1 file changed, 3 insertions(+)
> >>
> >> diff --git a/tests/pm_rps.c b/tests/pm_rps.c
> >> index 467038104ec6..27e758755e3f 100644
> >> --- a/tests/pm_rps.c
> >> +++ b/tests/pm_rps.c
> >> @@ -350,6 +350,9 @@ static void min_max_config(void (*check)(void))
> >> {
> >> int fmid = (origfreqs[RPn] + origfreqs[RP0]) / 2;
> >>
> >> + /* hw (and so kernel) currently rounds to 50 MHz ... */
> >
> > s/rounds/truncates/ or if it really does round, you need to adjust the
> > calculation.
>
> We just need to use something divisible by 50 so that the value we
> write and the one we get match up. Whether it's truncating or rounding
> doesn't matter really.
> -Daniel
Darn, I considered this possibility but forgot to account for it in the test.
I think what I was going to do was to create another writeval variant
which doesn't do read back matching check. This was because I didn't want to
assume that all systems use a 50 Mhz frequency increment (do they all?).
-Jeff
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Re: [Intel-gfx] [PATCH 1/2] tests/pm_rps: Round requested freq correctly
On Fri, Feb 07, 2014 at 08:44:14AM -0600, Jeff McGee wrote:
> On Fri, Feb 07, 2014 at 11:15:15AM +0100, Daniel Vetter wrote:
> > On Fri, Feb 7, 2014 at 10:33 AM, Chris Wilson
> > wrote:
> > > On Fri, Feb 07, 2014 at 10:03:33AM +0100, Daniel Vetter wrote:
> > >> The kernel will round it, so if we don't we'll have a spurious
> > >> mismatch. Happens on my machine here with 650-1300MHz range, where the
> > >> midpoint is 975.
> > >>
> > >> Cc: Jeff McGee
> > >> Signed-off-by: Daniel Vetter
> > >> ---
> > >> tests/pm_rps.c | 3 +++
> > >> 1 file changed, 3 insertions(+)
> > >>
> > >> diff --git a/tests/pm_rps.c b/tests/pm_rps.c
> > >> index 467038104ec6..27e758755e3f 100644
> > >> --- a/tests/pm_rps.c
> > >> +++ b/tests/pm_rps.c
> > >> @@ -350,6 +350,9 @@ static void min_max_config(void (*check)(void))
> > >> {
> > >> int fmid = (origfreqs[RPn] + origfreqs[RP0]) / 2;
> > >>
> > >> + /* hw (and so kernel) currently rounds to 50 MHz ... */
> > >
> > > s/rounds/truncates/ or if it really does round, you need to adjust the
> > > calculation.
> >
> > We just need to use something divisible by 50 so that the value we
> > write and the one we get match up. Whether it's truncating or rounding
> > doesn't matter really.
> > -Daniel
>
> Darn, I considered this possibility but forgot to account for it in the test.
> I think what I was going to do was to create another writeval variant
> which doesn't do read back matching check. This was because I didn't want to
> assume that all systems use a 50 Mhz frequency increment (do they all?).
VLV sure doesn't.
--
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH] drm/i915: Disable dp aux irq on g4x
On Fri, Feb 07, 2014 at 03:14:01PM +0100, Daniel Vetter wrote: > Apparently it's broken in the exact same way as the gmbus irq. For > reference of the full story see > > commit c12aba5aa0e60b7947bc8b6ea25ef55c4acf81a4 > Author: Jiri Kosina > Date: Tue Mar 19 09:56:57 2013 +0100 > > drm/i915: stop using GMBUS IRQs on Gen4 chips > > The effect is that we have a storm of unclaimed interrupts on the > legacy irq line. If that one is used by a different device then the > kernel will complain and rather quickly kill the irq source. Which > breaks any device trying to actually use the legacy irq line. > > This regression has been introduced > > commit 4aeebd7443e36b0a40032e518a9338f48bd27efc > Author: Daniel Vetter > Date: Thu Oct 31 09:53:36 2013 +0100 > > drm/i915: dp aux irq support for g4x/vlv > > v2: Cross-reference dp aux and gmbus gen4 comments. And another patch to bring those references closer together, perhaps near to the other feature check macros? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/9] drm/i915: Propagate PCI read/write errors during vga_set_state()
From: Chris Wilson
This has very little effect other than log the errors in case of failure,
and we then hope for the best.
Signed-off-by: Chris Wilson
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6ecd9da..1e9dd84 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11570,12 +11570,21 @@ int intel_modeset_vga_set_state(struct drm_device
*dev, bool state)
unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL :
INTEL_GMCH_CTRL;
u16 gmch_ctrl;
- pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl);
+ if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
+ DRM_ERROR("failed to read control word\n");
+ return -EIO;
+ }
+
if (state)
gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
else
gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
- pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl);
+
+ if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
+ DRM_ERROR("failed to write control word\n");
+ return -EIO;
+ }
+
return 0;
}
--
1.8.3.1
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[Intel-gfx] [PATCH 1/9] drm/i915: Propagate errors on failed PPGTT
From: Ben Widawsky
Clean up the return values/error handling so it's obvious what is going
on. This was tripped over in the PPGTT branch where code was added to do
a ret = foo() near the top, and this ended up bypassing some error cases
later.
These errors shouldn't exist with today's code, but a future patch
will add a ret = ..., and this the value of ret needs to be set
explicitly.
v2: Missed an error in alloc_page for gen6
Signed-off-by: Ben Widawsky
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6e858e1..2996c83 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -362,7 +362,7 @@ static void gen8_ppgtt_cleanup(struct i915_address_space
*vm)
static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
{
struct page *pt_pages;
- int i, j, ret = -ENOMEM;
+ int i, j, ret;
const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
@@ -408,14 +408,17 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
uint64_t size)
temp = pci_map_page(ppgtt->base.dev->pdev,
&ppgtt->pd_pages[i], 0,
PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
- if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
+ ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, temp);
+ if (ret)
goto err_out;
ppgtt->pd_dma_addr[i] = temp;
ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) *
GEN8_PDES_PER_PAGE, GFP_KERNEL);
- if (!ppgtt->gen8_pt_dma_addr[i])
+ if (!ppgtt->gen8_pt_dma_addr[i]) {
+ ret = -ENOMEM;
goto err_out;
+ }
for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j];
@@ -423,7 +426,8 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
uint64_t size)
p, 0, PAGE_SIZE,
PCI_DMA_BIDIRECTIONAL);
- if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp))
+ ret = pci_dma_mapping_error(ppgtt->base.dev->pdev,
temp);
+ if (ret)
goto err_out;
ppgtt->gen8_pt_dma_addr[i][j] = temp;
@@ -907,14 +911,18 @@ alloc:
for (i = 0; i < ppgtt->num_pd_entries; i++) {
ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
- if (!ppgtt->pt_pages[i])
+ if (!ppgtt->pt_pages[i]) {
+ ret = -ENOMEM;
goto err_pt_alloc;
+ }
}
ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
GFP_KERNEL);
- if (!ppgtt->pt_dma_addr)
+ if (!ppgtt->pt_dma_addr) {
+ ret = -ENOMEM;
goto err_pt_alloc;
+ }
for (i = 0; i < ppgtt->num_pd_entries; i++) {
dma_addr_t pt_addr;
--
1.8.3.1
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[Intel-gfx] [PATCH 9/9] drm/i915: PF CRC may not work on HSW
From: Ville Syrjälä
When using pipe A and transcoder EDP w/o panel fitter on
HSW, the PF CRC isn't available as the panel fitter is entirely
bypassed. Check for this and refuse to give out CRCs.
Signed-off-by: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2dc05c3..de020c0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2548,7 +2548,30 @@ static int ilk_pipe_crc_ctl_reg(enum
intel_pipe_crc_source *source,
return 0;
}
-static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
+static bool hsw_crc_source_pf_ok(struct drm_device *dev, enum pipe pipe)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *crtc =
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
+ bool ok;
+
+ if (!IS_HASWELL(dev) || pipe != PIPE_A)
+ return true;
+
+ mutex_lock(&crtc->base.mutex);
+
+ /* pipe A -> no panel fitter -> transcoder EDP == no PF CRC */
+ ok = !crtc->active ||
+ crtc->config.cpu_transcoder != TRANSCODER_EDP ||
+ crtc->config.pch_pfit.enabled;
+
+ mutex_unlock(&crtc->base.mutex);
+
+ return ok;
+}
+
+static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
+ enum pipe pipe,
+ enum intel_pipe_crc_source *source,
uint32_t *val)
{
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
@@ -2562,6 +2585,8 @@ static int ivb_pipe_crc_ctl_reg(enum
intel_pipe_crc_source *source,
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
break;
case INTEL_PIPE_CRC_SOURCE_PF:
+ if (!hsw_crc_source_pf_ok(dev, pipe))
+ return -EINVAL;
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
break;
case INTEL_PIPE_CRC_SOURCE_NONE:
@@ -2598,7 +2623,7 @@ static int pipe_crc_set_source(struct drm_device *dev,
enum pipe pipe,
else if (IS_GEN5(dev) || IS_GEN6(dev))
ret = ilk_pipe_crc_ctl_reg(&source, &val);
else
- ret = ivb_pipe_crc_ctl_reg(&source, &val);
+ ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
if (ret != 0)
return ret;
--
1.8.3.1
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[Intel-gfx] [PATCH 0/9] drm-intel-collector - update
This is another drm-intel-collector updated notice: http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector Here goes the update list in order for better reviewers assignment: Patch drm/i915: Propagate errors on failed PPGTT - Reviewer: Patch drm/i915: wrap crtc enable/disable - Reviewer: Patch drm/i915: make crtc enable/disable asynchronous - Reviewer: Patch drm/i915: Propagate PCI read/write errors during vga_set_state() - Reviewer: Patch drm/i915: Short-circuit no-op vga_set_state() - Reviewer: Patch drm/i915: Verify address field of PCBR register. - Reviewer: Patch drm/i915: Bring UP Power Wells before disabling RC6. - Reviewer: Patch drm/i915: Flush GPU rendering with a lockless wait during a pagefault - Reviewer: Patch drm/i915: PF CRC may not work on HSW - Reviewer: Overall Process: drm-intel-collector - review request 1. Daniel pushs drm-intel-testing (every 2 weeks) 2. I rebase drm-intel-collector onto drm-intel-testing 3. Add Reviewer: tag with voluntered reviewers. If you don't believe you should be assigned on a particular patch please don't get mad just tell you wont review or volunteer someone else. 4. I resubmit remaining patches for review without picking any new (drm-intel-collector - review request) drm-intel-collector - updated 5. One week later I collect all simple (1-2) patches that wasn't yet reviewed and not queued by Daniel from one testing update until another. 6. Request automated QA's PRTS automated i-g-t tests comparing drm-intel-testing x drm-intel-collector 7. If tests are ok I send the update notification or the patches as a series to intel-gfx mailing list for better tracking and to be reviewed. (drm-intel-collector - updated) 8. Let me know volunteers for review new patches and also let me know if I've picked any patch that I shouldn't. There are some reasons that some patches can be left behind: 1. Your patch didn't applied cleanly and I couldn't easily solve the conflicts. 2. Kernel didn't compiled with your patch. 3. I simply missed it. If you believe this is the case please warn me. Please help me to get these patches reviewed and queued by Daniel. Also, please let me know if you have further ideas how to improve this process. Thanks in advance, Rodrigo. Ben Widawsky (1): drm/i915: Propagate errors on failed PPGTT Chris Wilson (3): drm/i915: Propagate PCI read/write errors during vga_set_state() drm/i915: Short-circuit no-op vga_set_state() drm/i915: Flush GPU rendering with a lockless wait during a pagefault Deepak S (2): drm/i915: Verify address field of PCBR register. drm/i915: Bring UP Power Wells before disabling RC6. Jesse Barnes (2): drm/i915: wrap crtc enable/disable drm/i915: make crtc enable/disable asynchronous Ville Syrjälä (1): drm/i915: PF CRC may not work on HSW drivers/gpu/drm/i915/i915_debugfs.c | 29 - drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 4 +- drivers/gpu/drm/i915/i915_gem.c | 17 - drivers/gpu/drm/i915/i915_gem_gtt.c | 20 -- drivers/gpu/drm/i915/i915_irq.c | 10 ++- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_display.c | 116 +-- drivers/gpu/drm/i915/intel_drv.h | 5 ++ drivers/gpu/drm/i915/intel_pm.c | 15 - 10 files changed, 182 insertions(+), 37 deletions(-) -- 1.8.3.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 8/9] drm/i915: Flush GPU rendering with a lockless wait during a pagefault
From: Chris Wilson
Arjan van de Ven reported that on his test machine that he was seeing
stalls of greater than 1 frame greatly impacting the user experience. He
tracked this down to being the locked flush during a pagefault as being
the culprit hogging the struct_mutex and so blocking any other user from
proceeding. Stalling on a pagefault is bad behaviour on userspace's
part, for one it means that they are ignoring the coherency rules on
pointer access through the GTT, but fortunately we can apply the same
trick as the set-to-domain ioctl to do a lightweight, nonblocking flush
of outstanding rendering first.
"Prior to the patch it looks like this
(this one testrun does not show the 20ms+ I've seen occasionally)
4.99 ms 2.36 ms31360 __wait_seqno i915_wait_seqno
i915_gem_object_wait_rendering i915_gem_object_set_to_gtt_domain i915_gem_fault
__do_fault handle_
+pte_fault handle_mm_fault __do_page_fault do_page_fault page_fault
4.99 ms 2.75 ms 107751 __wait_seqno i915_gem_wait_ioctl drm_ioctl
i915_compat_ioctl compat_sys_ioctl ia32_sysret
4.99 ms 1.63 ms 1666 i915_mutex_lock_interruptible i915_gem_fault
__do_fault handle_pte_fault handle_mm_fault __do_page_fault do_page_fault
page_fa
+ult
4.93 ms 2.45 ms 980 i915_mutex_lock_interruptible
intel_crtc_page_flip drm_mode_page_flip_ioctl drm_ioctl i915_compat_ioctl
compat_sys_ioctl ia32_
+sysret
4.89 ms 2.20 ms 3283 i915_mutex_lock_interruptible
i915_gem_wait_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret
4.34 ms 1.66 ms 1715 i915_mutex_lock_interruptible
i915_gem_pwrite_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret
3.73 ms 3.73 ms 49 i915_mutex_lock_interruptible
i915_gem_set_domain_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl
ia32_sysret
3.17 ms 0.33 ms 931 i915_mutex_lock_interruptible
i915_gem_madvise_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret
2.97 ms 0.43 ms 1029 i915_mutex_lock_interruptible
i915_gem_busy_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret
2.55 ms 0.51 ms 735 i915_gem_get_tiling drm_ioctl
i915_compat_ioctl compat_sys_ioctl ia32_sysret
After the patch it looks like this:
4.99 ms 2.14 ms22212 __wait_seqno i915_gem_wait_ioctl drm_ioctl
i915_compat_ioctl compat_sys_ioctl ia32_sysret
4.86 ms 0.99 ms14170 __wait_seqno
i915_gem_object_wait_rendering__nonblocking i915_gem_fault __do_fault
handle_pte_fault handle_mm_fault __do_page_
+fault do_page_fault page_fault
3.59 ms 1.31 ms 325 i915_gem_get_tiling drm_ioctl
i915_compat_ioctl compat_sys_ioctl ia32_sysret
3.37 ms 3.37 ms 65 i915_mutex_lock_interruptible
i915_gem_wait_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret
2.58 ms 2.58 ms 65 i915_mutex_lock_interruptible
i915_gem_do_execbuffer.isra.23 i915_gem_execbuffer2 drm_ioctl i915_compat_ioctl
compat_sys_ioctl
+ia32_sysret
2.19 ms 2.19 ms 65 i915_mutex_lock_interruptible
intel_crtc_page_flip drm_mode_page_flip_ioctl drm_ioctl i915_compat_ioctl
compat_sys_ioctl ia32_
+sysret
2.18 ms 2.18 ms 65 i915_mutex_lock_interruptible
i915_gem_busy_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret
1.66 ms 1.66 ms 65 i915_gem_set_tiling drm_ioctl
i915_compat_ioctl compat_sys_ioctl ia32_sysret
It may not look like it, but this is quite a large difference, and I've
been unable to reproduce > 5 msec delays at all, while before they do
happen (just not in the trace above)."
gem_gtt_hog on an old Pineview (GMA3150),
before: 4969.119ms
after: 4122.749ms
Reported-by: Arjan van de Ven
Testcase: igt/gem_gtt_hog
Signed-off-by: Chris Wilson
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_gem.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a8a069f..6008d88 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1184,7 +1184,7 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj,
*/
static __must_check int
i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
- struct drm_file *file,
+ struct drm_i915_file_private
*file_priv,
bool readonly)
{
struct drm_device *dev = obj->base.dev;
@@ -1211,7 +1211,7 @@ i915_gem_object_wait_rendering__nonblocking(struct
drm_i915_gem_object *obj,
reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
mutex_unlock(&dev->struct_mutex);
- ret = __wait_seqno(ring, seqno, reset_counter, true, NULL,
file->driver_priv);
+ ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv);
mutex_lock(&dev->struct
[Intel-gfx] [PATCH 6/9] drm/i915: Verify address field of PCBR register.
From: Deepak S
RC6 should be enabled only if the PCBR register is programmed properly
either BIOS or Gfx. This patches address the case where PCBR
allocation fails due buggy BIOS or due to stolen memory allocation
failed.
v2: Add #define for magic numbers (Daniel)
v3: Use VLV_PCBR_ADDR_SHIFT instead of MASK (Jani)
Signed-off-by: Deepak S
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 9 +++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cc3ea04..41905ab 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4987,6 +4987,7 @@
#define GEN6_GT_GFX_RC60x138108
#define GEN6_GT_GFX_RC6p 0x13810C
#define GEN6_GT_GFX_RC6pp 0x138110
+#define VLV_PCBR_ADDR_SHIFT12
#define GEN6_PCODE_MAILBOX 0x138124
#define GEN6_PCODE_READY (1<<31)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f74d7f5..8caffb3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3602,7 +3602,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_ring_buffer *ring;
- u32 gtfifodbg, val, hw_max, hw_min, rc6_mode = 0;
+ u32 gtfifodbg, val, hw_max, hw_min, rc6_mode = 0, pcbr;
int i;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
@@ -3647,7 +3647,12 @@ static void valleyview_enable_rps(struct drm_device *dev)
_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
VLV_MEDIA_RC6_COUNT_EN |
VLV_RENDER_RC6_COUNT_EN));
- if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
+
+ /* Enable RC6 Only if the PCBR address is configured either by
+* BIOS or Gfx Driver */
+ pcbr = I915_READ(VLV_PCBR);
+ if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE &&
+ (pcbr >> VLV_PCBR_ADDR_SHIFT))
rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
intel_print_rc6_info(dev, rc6_mode);
--
1.8.3.1
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[Intel-gfx] [PATCH 3/9] drm/i915: make crtc enable/disable asynchronous
From: Jesse Barnes
The intent is to get back to userspace as quickly as possible so it can
start doing drawing or whatever. It should also allow our
suspend/resume/init time to improve a lot.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_irq.c | 10 +-
drivers/gpu/drm/i915/intel_display.c | 27 ---
drivers/gpu/drm/i915/intel_drv.h | 4
3 files changed, 33 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e9c94c9..749c20f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -917,8 +917,16 @@ static void i915_hotplug_work_func(struct work_struct
*work)
intel_connector = to_intel_connector(connector);
intel_encoder = intel_connector->encoder;
if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
- if (intel_encoder->hot_plug)
+ if (intel_encoder->hot_plug) {
+ struct drm_crtc *crtc =
+ intel_encoder->base.crtc;
+ if (crtc) {
+ mutex_lock(&crtc->mutex);
+
intel_sync_crtc(intel_encoder->base.crtc);
+ mutex_unlock(&crtc->mutex);
+ }
intel_encoder->hot_plug(intel_encoder);
+ }
if (intel_hpd_irq_event(dev, connector))
changed = true;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 21a950d..6ecd9da 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1746,6 +1746,11 @@ static void intel_crtc_disable_work(struct work_struct
*work)
{
struct intel_crtc *intel_crtc = container_of(work, struct intel_crtc,
disable_work);
+ struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
+
+ mutex_lock(&intel_crtc->base.mutex);
+ dev_priv->display._crtc_disable(&intel_crtc->base);
+ mutex_unlock(&intel_crtc->base.mutex);
}
void intel_queue_crtc_disable(struct drm_crtc *crtc)
@@ -1761,6 +1766,11 @@ static void intel_crtc_enable_work(struct work_struct
*work)
{
struct intel_crtc *intel_crtc = container_of(work, struct intel_crtc,
enable_work);
+ struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
+
+ mutex_lock(&intel_crtc->base.mutex);
+ dev_priv->display._crtc_enable(&intel_crtc->base);
+ mutex_unlock(&intel_crtc->base.mutex);
}
static void intel_queue_crtc_enable(struct drm_crtc *crtc)
@@ -1772,14 +1782,16 @@ static void intel_queue_crtc_enable(struct drm_crtc
*crtc)
queue_work(dev_priv->wq, &intel_crtc->enable_work);
}
-static void intel_sync_crtc(struct drm_crtc *crtc)
+void intel_sync_crtc(struct drm_crtc *crtc)
{
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ WARN(!mutex_is_locked(&intel_crtc->base.mutex), "need crtc mutex\n");
+
+ mutex_unlock(&intel_crtc->base.mutex);
flush_work(&intel_crtc->disable_work);
flush_work(&intel_crtc->enable_work);
+ mutex_lock(&intel_crtc->base.mutex);
}
/**
@@ -9781,8 +9793,9 @@ static int intel_set_mode(struct drm_crtc *crtc,
ret = __intel_set_mode(crtc, mode, x, y, fb);
- if (ret == 0)
- intel_modeset_check_state(crtc->dev);
+ /* FIXME: need to check after the CRTC changes have been applied */
+// if (ret == 0)
+// intel_modeset_check_state(crtc->dev);
return ret;
}
@@ -10348,8 +10361,8 @@ static void intel_crtc_init(struct drm_device *dev, int
pipe)
drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
- INIT_WORK(intel_crtc->enable_work, intel_crtc_enable_work);
- INIT_WORK(intel_crtc->disable_work, intel_crtc_disable_work);
+ INIT_WORK(&intel_crtc->enable_work, intel_crtc_enable_work);
+ INIT_WORK(&intel_crtc->disable_work, intel_crtc_disable_work);
}
enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5b5b51e..f104fe1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -376,6 +376,9 @@ struct intel_crtc {
/* watermarks currently being used */
struct intel_pipe_wm active;
} wm;
+
+ struct work_struct enable_work;
+ struct work_struct disable_work;
};
struct intel_plane_wm_parameters {
@@ -
[Intel-gfx] [PATCH 7/9] drm/i915: Bring UP Power Wells before disabling RC6.
From: Deepak S
We need do forcewake before Disabling RC6, This is what the BIOS
expects while going into suspend.
v2: updated commit message. (Daniel)
Signed-off-by: Deepak S
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8caffb3..2d74bf9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3184,8 +3184,14 @@ static void valleyview_disable_rps(struct drm_device
*dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ /* we're doing forcewake before Disabling RC6,
+* This what the BIOS expects when going into suspend */
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
I915_WRITE(GEN6_RC_CONTROL, 0);
+ gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
+
gen6_disable_rps_interrupts(dev);
if (dev_priv->vlv_pctx) {
--
1.8.3.1
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[Intel-gfx] [PATCH 2/9] drm/i915: wrap crtc enable/disable
From: Jesse Barnes
This allows us to hide queuing of enable/disable later.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/intel_display.c | 83 +---
drivers/gpu/drm/i915/intel_drv.h | 1 +
4 files changed, 71 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2d05d7c..2213791 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -461,7 +461,7 @@ static int i915_drm_freeze(struct drm_device *dev)
*/
mutex_lock(&dev->mode_config.mutex);
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
- dev_priv->display.crtc_disable(crtc);
+ intel_queue_crtc_disable(crtc);
mutex_unlock(&dev->mode_config.mutex);
intel_modeset_suspend_hw(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9ba8eab..5968859 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -434,8 +434,8 @@ struct drm_i915_display_funcs {
int (*crtc_mode_set)(struct drm_crtc *crtc,
int x, int y,
struct drm_framebuffer *old_fb);
- void (*crtc_enable)(struct drm_crtc *crtc);
- void (*crtc_disable)(struct drm_crtc *crtc);
+ void (*_crtc_enable)(struct drm_crtc *crtc);
+ void (*_crtc_disable)(struct drm_crtc *crtc);
void (*off)(struct drm_crtc *crtc);
void (*write_eld)(struct drm_connector *connector,
struct drm_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4d4a0d9..21a950d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1742,6 +1742,46 @@ static void lpt_disable_pch_transcoder(struct
drm_i915_private *dev_priv)
I915_WRITE(_TRANSA_CHICKEN2, val);
}
+static void intel_crtc_disable_work(struct work_struct *work)
+{
+ struct intel_crtc *intel_crtc = container_of(work, struct intel_crtc,
+disable_work);
+}
+
+void intel_queue_crtc_disable(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ queue_work(dev_priv->wq, &intel_crtc->disable_work);
+}
+
+static void intel_crtc_enable_work(struct work_struct *work)
+{
+ struct intel_crtc *intel_crtc = container_of(work, struct intel_crtc,
+enable_work);
+}
+
+static void intel_queue_crtc_enable(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ queue_work(dev_priv->wq, &intel_crtc->enable_work);
+}
+
+static void intel_sync_crtc(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ flush_work(&intel_crtc->disable_work);
+ flush_work(&intel_crtc->enable_work);
+}
+
/**
* intel_enable_pipe - enable a pipe, asserting requirements
* @dev_priv: i915 private structure
@@ -4328,7 +4368,6 @@ static void intel_crtc_update_sarea(struct drm_crtc *crtc,
void intel_crtc_update_dpms(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_encoder *intel_encoder;
bool enable = false;
@@ -4336,9 +4375,9 @@ void intel_crtc_update_dpms(struct drm_crtc *crtc)
enable |= intel_encoder->connectors_active;
if (enable)
- dev_priv->display.crtc_enable(crtc);
+ intel_queue_crtc_enable(crtc);
else
- dev_priv->display.crtc_disable(crtc);
+ intel_queue_crtc_disable(crtc);
intel_crtc_update_sarea(crtc, enable);
}
@@ -4353,7 +4392,7 @@ static void intel_crtc_disable(struct drm_crtc *crtc)
/* crtc should still be enabled when we disable it. */
WARN_ON(!crtc->enabled);
- dev_priv->display.crtc_disable(crtc);
+ dev_priv->display._crtc_disable(crtc);
intel_crtc->eld_vld = false;
intel_crtc_update_sarea(crtc, false);
dev_priv->display.off(crtc);
@@ -7575,6 +7614,8 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
goto fail;
}
+ intel_sync_crtc(crtc);
+
/* we only need to pin inside GTT if cursor is non-phy */
mutex_lock(&dev->struct_mutex);
if (!dev_priv->info->cursor_needs_physica
[Intel-gfx] [PATCH 5/9] drm/i915: Short-circuit no-op vga_set_state()
From: Chris Wilson Touching the VGA registers risks a hard machine hang, at least on this ivb machine after removing a conflicting efifb. This is more than likely related to the discovery that VGA IO decode on the more recent PCH platforms is terminally broken. Signed-off-by: Chris Wilson Cc: Ville Syrjälä Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1e9dd84..c411bf8 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11575,6 +11575,9 @@ int intel_modeset_vga_set_state(struct drm_device *dev, bool state) return -EIO; } + if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) + return 0; + if (state) gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; else -- 1.8.3.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: add a display info file to debugfs v2
Can be expanded up on to include all sorts of things (HDMI infoframe
data, more DP status, etc). Should be useful for bug reports to get a
baseline on the display config and info.
v2: use seq_putc (Rodrigo)
describe mode field names (Rodrigo)
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_debugfs.c | 159 +++
drivers/gpu/drm/i915/i915_drv.h |4 +
2 files changed, 163 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index bc8707f..f5a88f4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2074,6 +2074,164 @@ static int i915_power_domain_info(struct seq_file *m,
void *unused)
return 0;
}
+static void intel_seq_print_mode(struct seq_file *m, int tabs,
+struct drm_display_mode *mode)
+{
+ int i;
+
+ for (i = 0; i < tabs; i++)
+ seq_putc(m, '\t');
+
+ seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d
htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
+ mode->base.id, mode->name,
+ mode->vrefresh, mode->clock,
+ mode->hdisplay, mode->hsync_start,
+ mode->hsync_end, mode->htotal,
+ mode->vdisplay, mode->vsync_start,
+ mode->vsync_end, mode->vtotal,
+ mode->type, mode->flags);
+}
+
+static void intel_encoder_info(struct seq_file *m,
+ struct intel_crtc *intel_crtc,
+ struct intel_encoder *intel_encoder)
+{
+ struct drm_info_node *node = (struct drm_info_node *) m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct drm_crtc *crtc = &intel_crtc->base;
+ struct intel_connector *intel_connector;
+ struct drm_encoder *encoder;
+
+ encoder = &intel_encoder->base;
+ seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
+ encoder->base.id, drm_get_encoder_name(encoder));
+ for_each_connector_on_encoder(dev, encoder, intel_connector) {
+ struct drm_connector *connector = &intel_connector->base;
+ seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
+ connector->base.id,
+ drm_get_connector_name(connector),
+ drm_get_connector_status_name(connector->status));
+ if (connector->status == connector_status_connected) {
+ struct drm_display_mode *mode = &crtc->mode;
+ seq_printf(m, ", mode:\n");
+ intel_seq_print_mode(m, 2, mode);
+ } else {
+ seq_putc(m, '\n');
+ }
+ }
+}
+
+static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
+{
+ struct drm_info_node *node = (struct drm_info_node *) m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct drm_crtc *crtc = &intel_crtc->base;
+ struct intel_encoder *intel_encoder;
+
+ seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
+ crtc->fb->base.id, crtc->x, crtc->y,
+ crtc->fb->width, crtc->fb->height);
+ for_each_encoder_on_crtc(dev, crtc, intel_encoder)
+ intel_encoder_info(m, intel_crtc, intel_encoder);
+}
+
+static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
+{
+ struct drm_display_mode *mode = panel->fixed_mode;
+
+ seq_printf(m, "\tfixed mode:\n");
+ intel_seq_print_mode(m, 2, mode);
+}
+
+static void intel_dp_info(struct seq_file *m,
+ struct intel_connector *intel_connector)
+{
+ struct intel_encoder *intel_encoder = intel_connector->encoder;
+ struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
+
+ seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
+ seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
+ "no");
+ if (intel_encoder->type == INTEL_OUTPUT_EDP)
+ intel_panel_info(m, &intel_connector->panel);
+}
+
+static void intel_hdmi_info(struct seq_file *m,
+ struct intel_connector *intel_connector)
+{
+ struct intel_encoder *intel_encoder = intel_connector->encoder;
+ struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
+
+ seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
+ "no");
+}
+
+static void intel_lvds_info(struct seq_file *m,
+ struct intel_connector *intel_connector)
+{
+ intel_panel_info(m, &intel_connector->panel);
+}
+
+static void intel_connector_info(struct seq_file *m,
+struct drm_connector *connector)
+{
+ struct intel_connector
[Intel-gfx] [PATCH 1/2] drm: expose subpixel order name routine v2
Just like we have for connector type etc.
v2: drop static array (Chris)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/drm_crtc.c | 16
include/drm/drm_crtc.h |1 +
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 3b7d32d..8136f09 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -215,6 +215,16 @@ static const struct drm_prop_enum_list
drm_encoder_enum_list[] =
{ DRM_MODE_ENCODER_DSI, "DSI" },
};
+static const struct drm_prop_enum_list drm_subpixel_enum_list[] =
+{
+ { SubPixelUnknown, "Unknown" },
+ { SubPixelHorizontalRGB, "Horizontal RGB" },
+ { SubPixelHorizontalBGR, "Horizontal BGR" },
+ { SubPixelVerticalRGB, "Vertical RGB" },
+ { SubPixelVerticalBGR, "Vertical BGR" },
+ { SubPixelNone, "None" },
+};
+
void drm_connector_ida_init(void)
{
int i;
@@ -264,6 +274,12 @@ const char *drm_get_connector_status_name(enum
drm_connector_status status)
}
EXPORT_SYMBOL(drm_get_connector_status_name);
+const char *drm_get_subpixel_order_name(enum subpixel_order order)
+{
+ return drm_subpixel_enum_list[order].name;
+}
+EXPORT_SYMBOL(drm_get_subpixel_order_name);
+
static char printable_char(int c)
{
return isascii(c) && isprint(c) ? c : '?';
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 71727b6..ce9ee60 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -991,6 +991,7 @@ extern void drm_encoder_cleanup(struct drm_encoder
*encoder);
extern const char *drm_get_connector_name(const struct drm_connector
*connector);
extern const char *drm_get_connector_status_name(enum drm_connector_status
status);
+extern const char *drm_get_subpixel_order_name(enum subpixel_order order);
extern const char *drm_get_dpms_name(int val);
extern const char *drm_get_dvi_i_subconnector_name(int val);
extern const char *drm_get_dvi_i_select_name(int val);
--
1.7.9.5
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[Intel-gfx] [PATCH 1/3] drm/i915: dp: fix order of dp aux i2c device cleanup
Atm we set the parent of the dp i2c device to be the correspondig
connector device. During driver cleanup we first remove the connector
device through intel_modeset_cleanup()->drm_sysfs_connector_remove() and
only after that the i2c device through the encoder's destroy callback.
This order is not supported by the device core and we'll get a warning,
see the below bugzilla ticket. The proper order is to remove first any
child device and only then the parent device.
The first part of the fix changes the i2c device's parent to be the drm
device. Its logical owner is not the connector anyway, but the encoder.
Since the encoder doesn't have a device object, the next best choice is
the drm device. This is the same what we do in the case of the sdvo i2c
device and what the nouveau driver does.
The second part creates a symlink in the connector's sysfs directory
pointing to the i2c device. This is so, that we keep the current ABI,
which also makes sense in case someone wants to look up the i2c device
belonging to a specific connector. To remove this symlink a new
unregister callback is added to the connector. In general this should
remove any custom interfaces we added, through which the connector can
be accessed.
I also thought of moving the connector sysfs cleanup into its destroy
callback, but that would mean allowing user space access to race with
the destruction of the encoders for example. The following comment
for drm_mode_config_cleanup() also tells me that we have to make sure
there is no pending or new access to the connectors before we call it:
"""
Note that since this /should/ happen single-threaded at driver/device
teardown time, no locking is required. It's the driver's job to
ensure that this guarantee actually holds true.
"""
Reference:
http://lists.freedesktop.org/archives/intel-gfx/2014-January/038782.html
Reference:
http://lists.freedesktop.org/archives/intel-gfx/2014-February/039427.html
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70523
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_display.c | 5 +
drivers/gpu/drm/i915/intel_dp.c | 24 +++-
drivers/gpu/drm/i915/intel_drv.h | 7 +++
3 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4d4a0d9..5b5ec8a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11472,6 +11472,11 @@ void intel_modeset_cleanup(struct drm_device *dev)
/* destroy the backlight and sysfs files before encoders/connectors */
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+ struct intel_connector *intel_connector;
+
+ intel_connector = to_intel_connector(connector);
+ if (intel_connector->unregister)
+ intel_connector->unregister(intel_connector);
intel_panel_destroy_backlight(connector);
drm_sysfs_connector_remove(connector);
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5477a72..b82fd53 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -777,10 +777,20 @@ out:
return ret;
}
+static void
+intel_dp_connector_unregister(struct intel_connector *intel_connector)
+{
+ struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
+
+ sysfs_remove_link(&intel_connector->base.kdev->kobj,
+ intel_dp->adapter.dev.kobj.name);
+}
+
static int
intel_dp_i2c_init(struct intel_dp *intel_dp,
struct intel_connector *intel_connector, const char *name)
{
+ struct drm_device *dev;
int ret;
DRM_DEBUG_KMS("i2c_init %s\n", name);
@@ -794,9 +804,20 @@ intel_dp_i2c_init(struct intel_dp *intel_dp,
strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) -
1);
intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
intel_dp->adapter.algo_data = &intel_dp->algo;
- intel_dp->adapter.dev.parent = intel_connector->base.kdev;
+ dev = intel_connector->base.dev;
+ intel_dp->adapter.dev.parent = dev->dev;
ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
+ if (ret < 0)
+ return ret;
+
+ ret = sysfs_create_link(&intel_connector->base.kdev->kobj,
+ &intel_dp->adapter.dev.kobj,
+ intel_dp->adapter.dev.kobj.name);
+
+ if (ret < 0)
+ i2c_del_adapter(&intel_dp->adapter);
+
return ret;
}
@@ -3803,6 +3824,7 @@ intel_dp_init_connector(struct intel_digital_port
*intel_dig_port,
intel_connector->get_hw_state =
intel_ddi_connector_get_hw_state;
else
intel_connector->get_hw_state = intel_connector_get_hw_state;
+ intel_connector->unregister = intel_dp_connector_unregi
[Intel-gfx] [PATCH 2/3] drm/i915: sdvo: fix error path in sdvo_connector_init
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_sdvo.c | 49 +++
1 file changed, 39 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
b/drivers/gpu/drm/i915/intel_sdvo.c
index 95bdfb3..e9a2680 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -2381,16 +2381,22 @@ intel_sdvo_get_slave_addr(struct drm_device *dev,
struct intel_sdvo *sdvo)
return 0x72;
}
-static void
+static int
intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
struct intel_sdvo *encoder)
{
- drm_connector_init(encoder->base.base.dev,
- &connector->base.base,
+ struct drm_connector *drm_connector;
+ int ret;
+
+ drm_connector = &connector->base.base;
+ ret = drm_connector_init(encoder->base.base.dev,
+ drm_connector,
&intel_sdvo_connector_funcs,
connector->base.base.connector_type);
+ if (ret < 0)
+ return ret;
- drm_connector_helper_add(&connector->base.base,
+ drm_connector_helper_add(drm_connector,
&intel_sdvo_connector_helper_funcs);
connector->base.base.interlace_allowed = 1;
@@ -2399,7 +2405,16 @@ intel_sdvo_connector_init(struct intel_sdvo_connector
*connector,
connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
intel_connector_attach_encoder(&connector->base, &encoder->base);
- drm_sysfs_connector_add(&connector->base.base);
+ ret = drm_sysfs_connector_add(drm_connector);
+ if (ret < 0)
+ goto err1;
+
+ return 0;
+
+err1:
+ drm_connector_cleanup(drm_connector);
+
+ return ret;
}
static void
@@ -2459,7 +2474,11 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int
device)
intel_sdvo->is_hdmi = true;
}
- intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
+ if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
+ kfree(intel_sdvo_connector);
+ return false;
+ }
+
if (intel_sdvo->is_hdmi)
intel_sdvo_add_hdmi_properties(intel_sdvo,
intel_sdvo_connector);
@@ -2490,7 +2509,10 @@ intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int
type)
intel_sdvo->is_tv = true;
- intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
+ if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
+ kfree(intel_sdvo_connector);
+ return false;
+ }
if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector,
type))
goto err;
@@ -2534,8 +2556,11 @@ intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo,
int device)
intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
}
- intel_sdvo_connector_init(intel_sdvo_connector,
- intel_sdvo);
+ if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
+ kfree(intel_sdvo_connector);
+ return false;
+ }
+
return true;
}
@@ -2566,7 +2591,11 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int
device)
intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
}
- intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
+ if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
+ kfree(intel_sdvo_connector);
+ return false;
+ }
+
if (!intel_sdvo_create_enhance_property(intel_sdvo,
intel_sdvo_connector))
goto err;
--
1.8.4
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[Intel-gfx] [PATCH 3/3] drm/i915: sdvo: add i2c sysfs symlink to the connector's directory
This is the same what we do for DP connectors, so make things more
consistent.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_sdvo.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
b/drivers/gpu/drm/i915/intel_sdvo.c
index e9a2680..b269a7e 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -2381,6 +2381,19 @@ intel_sdvo_get_slave_addr(struct drm_device *dev, struct
intel_sdvo *sdvo)
return 0x72;
}
+static void
+intel_sdvo_connector_unregister(struct intel_connector *intel_connector)
+{
+ struct drm_connector *drm_connector;
+ struct intel_sdvo *sdvo_encoder;
+
+ drm_connector = &intel_connector->base;
+ sdvo_encoder = intel_attached_sdvo(&intel_connector->base);
+
+ sysfs_remove_link(&drm_connector->kdev->kobj,
+ sdvo_encoder->ddc.dev.kobj.name);
+}
+
static int
intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
struct intel_sdvo *encoder)
@@ -2403,14 +2416,23 @@ intel_sdvo_connector_init(struct intel_sdvo_connector
*connector,
connector->base.base.doublescan_allowed = 0;
connector->base.base.display_info.subpixel_order =
SubPixelHorizontalRGB;
connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
+ connector->base.unregister = intel_sdvo_connector_unregister;
intel_connector_attach_encoder(&connector->base, &encoder->base);
ret = drm_sysfs_connector_add(drm_connector);
if (ret < 0)
goto err1;
+ ret = sysfs_create_link(&encoder->ddc.dev.kobj,
+ &drm_connector->kdev->kobj,
+ encoder->ddc.dev.kobj.name);
+ if (ret < 0)
+ goto err2;
+
return 0;
+err2:
+ drm_sysfs_connector_remove(drm_connector);
err1:
drm_connector_cleanup(drm_connector);
--
1.8.4
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Re: [Intel-gfx] Request for feedback - Sprite flip notification support
On Fri, Feb 7, 2014 at 7:36 AM, Vijay Purushothaman wrote: > Ping.. Could you please suggest whether this is okay? If you think this is > not worth or if nuclear page flip is on the horizon i will focus on display > self refresh patches.. Since we need to keep userspace ABIs working essentially forever I prefer if we don't have to add temporary fixes. If it fits into Ville's overall plans though we could merge all the backend patches though, as preparation for the new atomic interfaces. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] 3.13.1 - WARNING at drivers/gpu/drm/i915/i915_irq.c:1240
On Thu, Feb 06, 2014 at 11:29:34PM +0100, Thomas Meyer wrote: > Am Dienstag, den 04.02.2014, 21:17 +0100 schrieb Daniel Vetter: > > On Tue, Feb 04, 2014 at 08:37:02PM +0100, Thomas Meyer wrote: > > > > > > Hi, > > > > > > I see a *lot* of these warning in 3.13.1. > > > 3.12.x never showed this problem. > > > Any ideas?! > > > > Can you please try latest the drm-intel-nightly git branch from > > git://anongit.freedesktop.org/drm-intel ? > > > > If that one's still affected then please boot with drm.debug=0xe added to > > your kernel cmdline, reproduce the WARN and attach the complete dmesg. > > > > Hi, > > with 3.13.0-drm-00890-g4055ebc (drm-intel-nightly) I get these warnings: Can you please boot with drm.debug=0xe and attach the complete dmesg? Thanks, Daniel > > [0.550068] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). > [0.550070] [drm] Driver supports precise vblank timestamp query. > [0.550146] vgaarb: device changed decodes: > PCI::00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem > [0.621056] [drm:i965_irq_handler] *ERROR* pipe A underrun > [0.860335] fbcon: inteldrmfb (fb0) is primary device > [0.940094] [ cut here ] > [0.940103] WARNING: CPU: 0 PID: 1 at > drivers/gpu/drm/i915/intel_panel.c:714 i965_enable_backlight+0x12a/0x150() > [0.940103] backlight already enabled > [0.940105] Modules linked in: > [0.940109] CPU: 0 PID: 1 Comm: swapper Not tainted > 3.13.0-drm-00890-g4055ebc #122 > [0.940110] Hardware name: Acer Aspire 1810T/JM11-MS, BIOS v1.3310 > 03/25/2010 > [0.940113] 0009 8802368a1448 81546104 > 8802368a1480 > [0.940115] 810391fc 880234ff4000 > 880234fb8400 > [0.940118] c000 880236a11c00 8802368a14e0 > 81039267 > [0.940119] Call Trace: > [0.940125] [] dump_stack+0x19/0x1b > [0.940129] [] warn_slowpath_common+0x6c/0x90 > [0.940132] [] warn_slowpath_fmt+0x47/0x50 > [0.940135] [] ? schedule_timeout+0xf9/0x190 > [0.940138] [] i965_enable_backlight+0x12a/0x150 > [0.940141] [] ? gen4_write64+0x30/0x30 > [0.940144] [] intel_panel_enable_backlight+0x96/0xd0 > [0.940146] [] intel_enable_lvds+0x158/0x170 > [0.940148] [] ? gen4_write64+0x30/0x30 > [0.940152] [] i9xx_crtc_enable+0x2f1/0x420 > [0.940155] [] __intel_set_mode+0x8af/0x1660 > [0.940159] [] intel_set_mode+0x11/0x30 > [0.940162] [] intel_crtc_set_config+0x984/0xc70 > [0.940165] [] ? > set_inverse_trans_unicode.isra.5+0xb8/0xd0 > [0.940169] [] drm_mode_set_config_internal+0x5d/0xe0 > [0.940173] [] drm_fb_helper_set_par+0x69/0xf0 > [0.940177] [] fbcon_init+0x504/0x580 > [0.940180] [] visual_init+0xb3/0x110 > [0.940183] [] do_bind_con_driver+0x153/0x320 > [0.940186] [] do_take_over_console+0x114/0x1c0 > [0.940188] [] do_fbcon_takeover+0x5b/0xc0 > [0.940191] [] fbcon_event_notify+0x60d/0x720 > [0.940194] [] notifier_call_chain+0x4c/0x70 > [0.940197] [] __blocking_notifier_call_chain+0x48/0x70 > [0.940200] [] blocking_notifier_call_chain+0x11/0x20 > [0.940204] [] fb_notifier_call_chain+0x16/0x20 > [0.940207] [] register_framebuffer+0x1e6/0x320 > [0.940211] [] drm_fb_helper_initial_config+0x327/0x500 > [0.940214] [] ? > intel_modeset_setup_hw_state+0x8e8/0xbe0 > [0.940217] [] ? __kmalloc+0xc4/0xf0 > [0.940220] [] ? kmem_cache_alloc+0xac/0xb0 > [0.940224] [] intel_fbdev_initial_config+0x1c/0x20 > [0.940227] [] i915_driver_load+0xda1/0xde0 > [0.940231] [] drm_dev_register+0x76/0x160 > [0.940234] [] drm_get_pci_dev+0x9b/0x210 > [0.940237] [] i915_pci_probe+0x36/0x50 > [0.940240] [] pci_device_probe+0x7c/0xe0 > [0.940244] [] driver_probe_device+0x6d/0x230 > [0.940247] [] __driver_attach+0x8b/0x90 > [0.940250] [] ? __device_attach+0x40/0x40 > [0.940253] [] bus_for_each_dev+0x63/0xa0 > [0.940256] [] driver_attach+0x19/0x20 > [0.940258] [] bus_add_driver+0x170/0x220 > [0.940262] [] ? drm_core_init+0x109/0x109 > [0.940265] [] driver_register+0x5f/0xf0 > [0.940268] [] ? drm_core_init+0x109/0x109 > [0.940271] [] __pci_register_driver+0x3a/0x40 > [0.940273] [] drm_pci_init+0x115/0x130 > [0.940276] [] ? drm_core_init+0x109/0x109 > [0.940279] [] i915_init+0x6a/0x6c > [0.940281] [] do_one_initcall+0x10a/0x160 > [0.940284] [] ? parse_args+0x1e8/0x320 > [0.940287] [] kernel_init_freeable+0x142/0x1d1 > [0.940290] [] ? do_early_param+0x88/0x88 > [0.940292] [] ? rest_init+0x80/0x80 > [0.940295] [] kernel_init+0x9/0x120 > [0.940297] [] ret_from_fork+0x7a/0xb0 > [0.940300] [] ? rest_init+0x80/0x80 > [0.940305] ---[ end trace 529feadd43242174 ]--- > [1.002905] Console: switching to colour frame buffer device 170x48 > > And this one, but I'm not sure if this one i
[Intel-gfx] [PATCH 2/2] tests/pm_rps: remove setfreq
It's unused.
Cc: Jeff McGee
Signed-off-by: Daniel Vetter
---
tests/pm_rps.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index 27e758755e3f..3d374f92f82d 100644
--- a/tests/pm_rps.c
+++ b/tests/pm_rps.c
@@ -110,17 +110,6 @@ static int do_writeval(FILE *filp, int val, int lerrno)
#define writeval(filp, val) do_writeval(filp, val, 0)
#define writeval_inval(filp, val) do_writeval(filp, val, EINVAL)
-static void setfreq(int val)
-{
- if (val > readval(stuff[MAX].filp)) {
- writeval(stuff[MAX].filp, val);
- writeval(stuff[MIN].filp, val);
- } else {
- writeval(stuff[MIN].filp, val);
- writeval(stuff[MAX].filp, val);
- }
-}
-
static void checkit(const int *freqs)
{
igt_assert(freqs[MIN] <= freqs[MAX]);
--
1.8.1.4
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[Intel-gfx] [PATCH 1/2] tests/pm_rps: Round requested freq correctly
The kernel will round it, so if we don't we'll have a spurious
mismatch. Happens on my machine here with 650-1300MHz range, where the
midpoint is 975.
Cc: Jeff McGee
Signed-off-by: Daniel Vetter
---
tests/pm_rps.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index 467038104ec6..27e758755e3f 100644
--- a/tests/pm_rps.c
+++ b/tests/pm_rps.c
@@ -350,6 +350,9 @@ static void min_max_config(void (*check)(void))
{
int fmid = (origfreqs[RPn] + origfreqs[RP0]) / 2;
+ /* hw (and so kernel) currently rounds to 50 MHz ... */
+ fmid = fmid / 50 * 50;
+
log("\nCheck original min and max...\n");
check();
--
1.8.1.4
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Re: [Intel-gfx] [PATCH v2] drm/i915: Restore rps/rc6 on reset
On Tue, Feb 04, 2014 at 11:32:31AM -0600, jeff.mc...@intel.com wrote: > From: Jeff McGee > > A check of rps/rc6 state after i915_reset determined that the ring > MAX_IDLE registers were returned to their hardware defaults and that > the GEN6_PMIMR register was set to mask all interrupts. This change > restores those values to their pre-reset states by re-initializing > rps/rc6 in i915_reset. A full re-initialization was opted for versus > a targeted set of restore operations for simplicity and maintain- > ability. Note that the re-initialization is not done for Ironlake, > due to a past comment that it causes problems. > > Also updated the rps initialization sequence to preserve existing > min/max values in the case of a re-init. We assume the values were > validated upon being set and do not do further range checking. The > debugfs interface for changing min/max was updated with range > checking to ensure this condition (already present in sysfs > interface). > > v2: fix rps logging to output hw_max and hw_min, not rps.max_delay > and rps.min_delay which don't strictly represent hardware limits. > Add igt testcase to signed-off-by section. > > Testcase: igt/pm_rps/reset > Signed-off-by: Jeff McGee Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3] drm/i915: Update rps interrupt limits
On Tue, Feb 04, 2014 at 11:37:01AM -0600, jeff.mc...@intel.com wrote: > From: Jeff McGee > > sysfs changes to rps min and max delay were only triggering an update > of the rps interrupt limits if the active delay required an update. > This change ensures that interrupt limits are always updated. > > v2: correct compile issue missed on rebase > v3: add igt testcases to signed-off-by section > > Testcase: igt/pm_rps/min-max-config-idle > Testcase: igt/pm_rps/min-max-config-loaded > Signed-off-by: Jeff McGee Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] tests/pm_rps: Round requested freq correctly
On Fri, Feb 07, 2014 at 10:03:33AM +0100, Daniel Vetter wrote:
> The kernel will round it, so if we don't we'll have a spurious
> mismatch. Happens on my machine here with 650-1300MHz range, where the
> midpoint is 975.
>
> Cc: Jeff McGee
> Signed-off-by: Daniel Vetter
> ---
> tests/pm_rps.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/tests/pm_rps.c b/tests/pm_rps.c
> index 467038104ec6..27e758755e3f 100644
> --- a/tests/pm_rps.c
> +++ b/tests/pm_rps.c
> @@ -350,6 +350,9 @@ static void min_max_config(void (*check)(void))
> {
> int fmid = (origfreqs[RPn] + origfreqs[RP0]) / 2;
>
> + /* hw (and so kernel) currently rounds to 50 MHz ... */
s/rounds/truncates/ or if it really does round, you need to adjust the
calculation.
> + fmid = fmid / 50 * 50;
> +
> log("\nCheck original min and max...\n");
> check();
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] intel_sdvo_init: trying to register non-static key
Hi guys, so I'm seeing this on rc1 + tip during boot: [0.558106] Linux agpgart interface v0.103 [0.558283] [drm] Initialized drm 1.1.0 20060810 [0.562280] [drm] Memory usable by graphics device = 2048M [0.632301] i915 :00:02.0: irq 42 for MSI/MSI-X [0.632401] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [0.632485] [drm] Driver supports precise vblank timestamp query. [0.633200] vgaarb: device changed decodes: PCI::00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem [0.655917] INFO: trying to register non-static key. [0.656003] the code is fine but needs lockdep annotation. [0.656083] turning off the locking correctness validator. [0.656165] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 3.14.0-rc1+ #1 [0.656248] Hardware name: LENOVO 2320CTO/2320CTO, BIOS G2ET86WW (2.06 ) 11/13/2012 [0.656348] 880213ca8000 880213d01518 8160ffa8 810ad3c1 [0.656641] 8800cabc7560 880213d01618 8109e7c7 880213ca8000 [0.656929] 880213ca8780 8802 [0.657216] Call Trace: [0.657295] [] dump_stack+0x4f/0x7c [0.657378] [] ? console_unlock+0x2a1/0x450 [0.657465] [] __lock_acquire+0x1b57/0x1d50 [0.657551] [] ? mark_held_locks+0x74/0x140 [0.657637] [] ? debug_check_no_locks_freed+0x8e/0x160 [0.657724] [] ? lockdep_init_map+0xb3/0x570 [0.657809] [] ? trace_hardirqs_on_caller+0x11d/0x1e0 [0.657897] [] ? kernfs_addrm_finish+0x38/0x60 [0.657982] [] lock_acquire+0x87/0x130 [0.658062] [] ? kernfs_addrm_finish+0x38/0x60 [0.658148] [] kernfs_deactivate+0x10e/0x150 [0.658232] [] ? kernfs_addrm_finish+0x38/0x60 [0.658318] [] kernfs_addrm_finish+0x38/0x60 [0.658404] [] kernfs_remove_by_name_ns+0x58/0xb0 [0.658490] [] remove_files.isra.1+0x41/0x80 [0.658574] [] sysfs_remove_group+0x50/0xb0 [0.658659] [] sysfs_remove_groups+0x3b/0x60 [0.658746] [] device_remove_attrs+0x5b/0x80 [0.658832] [] device_del+0x125/0x1c0 [0.658915] [] device_unregister+0x16/0x30 [0.659000] [] i2c_del_adapter+0x1ba/0x270 [0.659086] [] intel_sdvo_init+0x1f6/0x820 [0.659172] [] ? preempt_count_sub+0xb1/0x100 [0.659258] [] ? _raw_spin_unlock_irqrestore+0x4b/0x80 [0.659347] [] ? gen6_read32+0x63/0x170 [0.659431] [] intel_modeset_init+0xb3d/0x1010 [0.659519] [] ? intel_power_domains_init_hw+0xa9/0x110 [0.659606] [] i915_driver_load+0xd5f/0xeb0 [0.659692] [] drm_dev_register+0x8a/0x190 [0.659777] [] drm_get_pci_dev+0xf9/0x230 [0.659861] [] i915_pci_probe+0x3b/0x60 [0.659945] [] local_pci_probe+0x4e/0xa0 [0.660029] [] ? get_device+0x19/0x20 [0.660110] [] pci_device_probe+0xe1/0x130 [0.660194] [] driver_probe_device+0x7b/0x240 [0.660279] [] __driver_attach+0xab/0xb0 [0.660363] [] ? driver_probe_device+0x240/0x240 [0.660448] [] bus_for_each_dev+0x5e/0x90 [0.660532] [] driver_attach+0x1e/0x20 [0.660615] [] bus_add_driver+0x117/0x230 [0.660698] [] driver_register+0x64/0xf0 [0.660780] [] __pci_register_driver+0x64/0x70 [0.660869] [] ? ftrace_define_fields_drm_vblank_event+0x6d/0x6d [0.660970] [] drm_pci_init+0x115/0x130 [0.661054] [] ? ftrace_define_fields_drm_vblank_event+0x6d/0x6d [0.661157] [] i915_init+0x6a/0x6c [0.661241] [] do_one_initcall+0x4e/0x170 [0.661328] [] ? parse_args+0xb0/0x360 [0.661412] [] kernel_init_freeable+0x106/0x19a [0.661497] [] ? do_early_param+0x86/0x86 [0.661580] [] ? rest_init+0xd0/0xd0 [0.661663] [] kernel_init+0xe/0x130 [0.661746] [] ret_from_fork+0x7c/0xb0 [0.661828] [] ? rest_init+0xd0/0xd0 [0.747947] [drm] GMBUS [i915 gmbus dpb] timed out, falling back to bit banging on pin 5 [0.758745] fbcon: inteldrmfb (fb0) is primary device -- Regards/Gruss, Boris. Sent from a fat crate under my desk. Formatting is fine. -- ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/vlv: Added write-enable pte bit support
>> What happens when we GTT-mapped write a batchbuffer that had previously been >> silently made RO by the kernel? Does the CPU take a fault? We tested this particular case, doing the relocation inside the Batch buffer, which is mapped to GTT as read-only, from the exec-buffer path. On doing so, there were no faults observed on the CPU side. Also we don't see any ring hangs, when forcing the GPU to do a write access on the buffers marked as RO. Just the writes were getting rejected. Best Regards Akash -Original Message- From: Eric Anholt [mailto:e...@anholt.net] Sent: Friday, February 07, 2014 3:11 AM To: Goel, Akash; intel-gfx@lists.freedesktop.org Cc: Goel, Akash Subject: Re: [Intel-gfx] [PATCH] drm/i915/vlv: Added write-enable pte bit support akash.g...@intel.com writes: > From: Akash Goel > > This adds support for using the write-enable bit in the GTT entry for VLV. > This is handled via a read-only flag in the GEM buffer object which is > then used to check if the write-enable bit has to be set or not when > writing the GTT entries. > Currently by default only the Batch buffer & Ring buffers are being > marked as read only. What happens when we GTT-mapped write a batchbuffer that had previously been silently made RO by the kernel? Does the CPU take a fault? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] tests/gem_gtt_hog: Fix for BDW
On Thu, Feb 06, 2014 at 07:46:38PM -0200, Rodrigo Vivi wrote:
> Update XY_COLOR_BLT command for Broadwell.
>
> v2: stash devid and remove ugly double allocation. (by Chris).
> v3: fix inverted blt command size and stash fd, devid and intel_gen.
>
> Cc: Chris Wilson ch...@chris-wilson.co.uk>
> Signed-off-by: Rodrigo Vivi
> ---
> tests/gem_gtt_hog.c | 59
> +++--
> 1 file changed, 39 insertions(+), 20 deletions(-)
>
> diff --git a/tests/gem_gtt_hog.c b/tests/gem_gtt_hog.c
> index 53cd7eb..3149ff4 100644
> --- a/tests/gem_gtt_hog.c
> +++ b/tests/gem_gtt_hog.c
> @@ -44,30 +44,43 @@
>
> static const uint32_t canary = 0xdeadbeef;
>
> +typedef struct data {
> + int fd;
> + int devid;
> + int intel_gen;
> +} data_t;
> +
> static double elapsed(const struct timeval *start,
> const struct timeval *end)
> {
> return 1e6*(end->tv_sec - start->tv_sec) + (end->tv_usec -
> start->tv_usec);
> }
>
> -static void busy(int fd, uint32_t handle, int size, int loops)
> +static void busy(data_t *data, uint32_t handle, int size, int loops)
> {
> struct drm_i915_gem_relocation_entry reloc[20];
> struct drm_i915_gem_exec_object2 gem_exec[2];
> struct drm_i915_gem_execbuffer2 execbuf;
> struct drm_i915_gem_pwrite gem_pwrite;
> struct drm_i915_gem_create create;
> - uint32_t buf[122], *b;
> - int i;
> + uint32_t buf[170], *b;
> + int i, b_size;
>
> memset(reloc, 0, sizeof(reloc));
> memset(gem_exec, 0, sizeof(gem_exec));
> memset(&execbuf, 0, sizeof(execbuf));
>
> b = buf;
> + b_size = sizeof(uint32_t) * (data->intel_gen >= 8 ? 170 : 122);
> for (i = 0; i < 20; i++) {
> - *b++ = XY_COLOR_BLT_CMD_NOLEN | 4 |
> - COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB;
> + if (data->intel_gen >= 8) {
> + *b++ = MI_NOOP;
Not required, instead you just round up the buf to the next qword after
ending the batch.
> + *b++ = XY_COLOR_BLT_CMD_NOLEN | 5 |
> + COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB;
> + } else {
> + *b++ = XY_COLOR_BLT_CMD_NOLEN | 4 |
> + COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB;
> + }
> *b++ = 0xf0 << 16 | 1 << 25 | 1 << 24 | 4096;
> *b++ = 0;
> *b++ = size >> 12 << 16 | 1024;
> @@ -76,6 +89,8 @@ static void busy(int fd, uint32_t handle, int size, int
> loops)
> reloc[i].read_domains = I915_GEM_DOMAIN_RENDER;
> reloc[i].write_domain = I915_GEM_DOMAIN_RENDER;
> *b++ = 0;
> + if (data->intel_gen >= 8)
> + *b++ = 0;
> *b++ = canary;
> }
> *b++ = MI_BATCH_BUFFER_END;
if ((b - buf) & 1))
*b++ = 0;
> @@ -86,56 +101,55 @@ static void busy(int fd, uint32_t handle, int size, int
> loops)
>
> create.handle = 0;
> create.size = 4096;
> - drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create);
> + drmIoctl(data->fd, DRM_IOCTL_I915_GEM_CREATE, &create);
> gem_exec[1].handle = create.handle;
> gem_exec[1].relocation_count = 20;
> gem_exec[1].relocs_ptr = (uintptr_t)reloc;
>
> execbuf.buffers_ptr = (uintptr_t)gem_exec;
> execbuf.buffer_count = 2;
> - execbuf.batch_len = sizeof(buf);
> + execbuf.batch_len = b_size;
I would have personally used (b - buf) * sizeof(buf[0]);
> execbuf.flags = 1 << 11;
> - if (HAS_BLT_RING(intel_get_drm_devid(fd)))
> + if (HAS_BLT_RING(data->devid))
> execbuf.flags |= I915_EXEC_BLT;
>
> gem_pwrite.handle = gem_exec[1].handle;
> gem_pwrite.offset = 0;
> - gem_pwrite.size = sizeof(buf);
> + gem_pwrite.size = b_size;
and gem_pwrite.size = execbuf.batch_len;
-Chris
--
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Re: [Intel-gfx] [PATCH 1/2] tests/pm_rps: Round requested freq correctly
On Fri, Feb 7, 2014 at 10:33 AM, Chris Wilson wrote:
> On Fri, Feb 07, 2014 at 10:03:33AM +0100, Daniel Vetter wrote:
>> The kernel will round it, so if we don't we'll have a spurious
>> mismatch. Happens on my machine here with 650-1300MHz range, where the
>> midpoint is 975.
>>
>> Cc: Jeff McGee
>> Signed-off-by: Daniel Vetter
>> ---
>> tests/pm_rps.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/tests/pm_rps.c b/tests/pm_rps.c
>> index 467038104ec6..27e758755e3f 100644
>> --- a/tests/pm_rps.c
>> +++ b/tests/pm_rps.c
>> @@ -350,6 +350,9 @@ static void min_max_config(void (*check)(void))
>> {
>> int fmid = (origfreqs[RPn] + origfreqs[RP0]) / 2;
>>
>> + /* hw (and so kernel) currently rounds to 50 MHz ... */
>
> s/rounds/truncates/ or if it really does round, you need to adjust the
> calculation.
We just need to use something divisible by 50 so that the value we
write and the one we get match up. Whether it's truncating or rounding
doesn't matter really.
-Daniel
--
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] intel_sdvo_init: trying to register non-static key
Imre, is this the same i2c_del_adapter issue you're looking at? Any patches to try yet? BR, Jani. On Fri, 07 Feb 2014, Borislav Petkov wrote: > Hi guys, > > so I'm seeing this on rc1 + tip during boot: > > [0.558106] Linux agpgart interface v0.103 > [0.558283] [drm] Initialized drm 1.1.0 20060810 > [0.562280] [drm] Memory usable by graphics device = 2048M > [0.632301] i915 :00:02.0: irq 42 for MSI/MSI-X > [0.632401] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). > [0.632485] [drm] Driver supports precise vblank timestamp query. > [0.633200] vgaarb: device changed decodes: > PCI::00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem > [0.655917] INFO: trying to register non-static key. > [0.656003] the code is fine but needs lockdep annotation. > [0.656083] turning off the locking correctness validator. > [0.656165] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 3.14.0-rc1+ #1 > [0.656248] Hardware name: LENOVO 2320CTO/2320CTO, BIOS G2ET86WW (2.06 ) > 11/13/2012 > [0.656348] 880213ca8000 880213d01518 8160ffa8 > 810ad3c1 > [0.656641] 8800cabc7560 880213d01618 8109e7c7 > 880213ca8000 > [0.656929] 880213ca8780 > 8802 > [0.657216] Call Trace: > [0.657295] [] dump_stack+0x4f/0x7c > [0.657378] [] ? console_unlock+0x2a1/0x450 > [0.657465] [] __lock_acquire+0x1b57/0x1d50 > [0.657551] [] ? mark_held_locks+0x74/0x140 > [0.657637] [] ? debug_check_no_locks_freed+0x8e/0x160 > [0.657724] [] ? lockdep_init_map+0xb3/0x570 > [0.657809] [] ? trace_hardirqs_on_caller+0x11d/0x1e0 > [0.657897] [] ? kernfs_addrm_finish+0x38/0x60 > [0.657982] [] lock_acquire+0x87/0x130 > [0.658062] [] ? kernfs_addrm_finish+0x38/0x60 > [0.658148] [] kernfs_deactivate+0x10e/0x150 > [0.658232] [] ? kernfs_addrm_finish+0x38/0x60 > [0.658318] [] kernfs_addrm_finish+0x38/0x60 > [0.658404] [] kernfs_remove_by_name_ns+0x58/0xb0 > [0.658490] [] remove_files.isra.1+0x41/0x80 > [0.658574] [] sysfs_remove_group+0x50/0xb0 > [0.658659] [] sysfs_remove_groups+0x3b/0x60 > [0.658746] [] device_remove_attrs+0x5b/0x80 > [0.658832] [] device_del+0x125/0x1c0 > [0.658915] [] device_unregister+0x16/0x30 > [0.659000] [] i2c_del_adapter+0x1ba/0x270 > [0.659086] [] intel_sdvo_init+0x1f6/0x820 > [0.659172] [] ? preempt_count_sub+0xb1/0x100 > [0.659258] [] ? _raw_spin_unlock_irqrestore+0x4b/0x80 > [0.659347] [] ? gen6_read32+0x63/0x170 > [0.659431] [] intel_modeset_init+0xb3d/0x1010 > [0.659519] [] ? intel_power_domains_init_hw+0xa9/0x110 > [0.659606] [] i915_driver_load+0xd5f/0xeb0 > [0.659692] [] drm_dev_register+0x8a/0x190 > [0.659777] [] drm_get_pci_dev+0xf9/0x230 > [0.659861] [] i915_pci_probe+0x3b/0x60 > [0.659945] [] local_pci_probe+0x4e/0xa0 > [0.660029] [] ? get_device+0x19/0x20 > [0.660110] [] pci_device_probe+0xe1/0x130 > [0.660194] [] driver_probe_device+0x7b/0x240 > [0.660279] [] __driver_attach+0xab/0xb0 > [0.660363] [] ? driver_probe_device+0x240/0x240 > [0.660448] [] bus_for_each_dev+0x5e/0x90 > [0.660532] [] driver_attach+0x1e/0x20 > [0.660615] [] bus_add_driver+0x117/0x230 > [0.660698] [] driver_register+0x64/0xf0 > [0.660780] [] __pci_register_driver+0x64/0x70 > [0.660869] [] ? > ftrace_define_fields_drm_vblank_event+0x6d/0x6d > [0.660970] [] drm_pci_init+0x115/0x130 > [0.661054] [] ? > ftrace_define_fields_drm_vblank_event+0x6d/0x6d > [0.661157] [] i915_init+0x6a/0x6c > [0.661241] [] do_one_initcall+0x4e/0x170 > [0.661328] [] ? parse_args+0xb0/0x360 > [0.661412] [] kernel_init_freeable+0x106/0x19a > [0.661497] [] ? do_early_param+0x86/0x86 > [0.661580] [] ? rest_init+0xd0/0xd0 > [0.661663] [] kernel_init+0xe/0x130 > [0.661746] [] ret_from_fork+0x7c/0xb0 > [0.661828] [] ? rest_init+0xd0/0xd0 > [0.747947] [drm] GMBUS [i915 gmbus dpb] timed out, falling back to bit > banging on pin 5 > [0.758745] fbcon: inteldrmfb (fb0) is primary device > > -- > Regards/Gruss, > Boris. > > Sent from a fat crate under my desk. Formatting is fine. > -- -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] intel_sdvo_init: trying to register non-static key
On Fri, 2014-02-07 at 13:04 +0200, Jani Nikula wrote: > Imre, is this the same i2c_del_adapter issue you're looking at? Any > patches to try yet? It looks like the same issue yes. The following patch fixed it for me: http://patchwork.freedesktop.org/patch/18698/ I'm working on an improved version of this, but the main thing - to remove the connector's sysfs entries before actually destroying the encoder and connector objects - will remain the same as in the above patch. --Imre > > BR, > Jani. > > > On Fri, 07 Feb 2014, Borislav Petkov wrote: > > Hi guys, > > > > so I'm seeing this on rc1 + tip during boot: > > > > [0.558106] Linux agpgart interface v0.103 > > [0.558283] [drm] Initialized drm 1.1.0 20060810 > > [0.562280] [drm] Memory usable by graphics device = 2048M > > [0.632301] i915 :00:02.0: irq 42 for MSI/MSI-X > > [0.632401] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). > > [0.632485] [drm] Driver supports precise vblank timestamp query. > > [0.633200] vgaarb: device changed decodes: > > PCI::00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem > > [0.655917] INFO: trying to register non-static key. > > [0.656003] the code is fine but needs lockdep annotation. > > [0.656083] turning off the locking correctness validator. > > [0.656165] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 3.14.0-rc1+ #1 > > [0.656248] Hardware name: LENOVO 2320CTO/2320CTO, BIOS G2ET86WW (2.06 ) > > 11/13/2012 > > [0.656348] 880213ca8000 880213d01518 8160ffa8 > > 810ad3c1 > > [0.656641] 8800cabc7560 880213d01618 8109e7c7 > > 880213ca8000 > > [0.656929] 880213ca8780 > > 8802 > > [0.657216] Call Trace: > > [0.657295] [] dump_stack+0x4f/0x7c > > [0.657378] [] ? console_unlock+0x2a1/0x450 > > [0.657465] [] __lock_acquire+0x1b57/0x1d50 > > [0.657551] [] ? mark_held_locks+0x74/0x140 > > [0.657637] [] ? debug_check_no_locks_freed+0x8e/0x160 > > [0.657724] [] ? lockdep_init_map+0xb3/0x570 > > [0.657809] [] ? trace_hardirqs_on_caller+0x11d/0x1e0 > > [0.657897] [] ? kernfs_addrm_finish+0x38/0x60 > > [0.657982] [] lock_acquire+0x87/0x130 > > [0.658062] [] ? kernfs_addrm_finish+0x38/0x60 > > [0.658148] [] kernfs_deactivate+0x10e/0x150 > > [0.658232] [] ? kernfs_addrm_finish+0x38/0x60 > > [0.658318] [] kernfs_addrm_finish+0x38/0x60 > > [0.658404] [] kernfs_remove_by_name_ns+0x58/0xb0 > > [0.658490] [] remove_files.isra.1+0x41/0x80 > > [0.658574] [] sysfs_remove_group+0x50/0xb0 > > [0.658659] [] sysfs_remove_groups+0x3b/0x60 > > [0.658746] [] device_remove_attrs+0x5b/0x80 > > [0.658832] [] device_del+0x125/0x1c0 > > [0.658915] [] device_unregister+0x16/0x30 > > [0.659000] [] i2c_del_adapter+0x1ba/0x270 > > [0.659086] [] intel_sdvo_init+0x1f6/0x820 > > [0.659172] [] ? preempt_count_sub+0xb1/0x100 > > [0.659258] [] ? _raw_spin_unlock_irqrestore+0x4b/0x80 > > [0.659347] [] ? gen6_read32+0x63/0x170 > > [0.659431] [] intel_modeset_init+0xb3d/0x1010 > > [0.659519] [] ? > > intel_power_domains_init_hw+0xa9/0x110 > > [0.659606] [] i915_driver_load+0xd5f/0xeb0 > > [0.659692] [] drm_dev_register+0x8a/0x190 > > [0.659777] [] drm_get_pci_dev+0xf9/0x230 > > [0.659861] [] i915_pci_probe+0x3b/0x60 > > [0.659945] [] local_pci_probe+0x4e/0xa0 > > [0.660029] [] ? get_device+0x19/0x20 > > [0.660110] [] pci_device_probe+0xe1/0x130 > > [0.660194] [] driver_probe_device+0x7b/0x240 > > [0.660279] [] __driver_attach+0xab/0xb0 > > [0.660363] [] ? driver_probe_device+0x240/0x240 > > [0.660448] [] bus_for_each_dev+0x5e/0x90 > > [0.660532] [] driver_attach+0x1e/0x20 > > [0.660615] [] bus_add_driver+0x117/0x230 > > [0.660698] [] driver_register+0x64/0xf0 > > [0.660780] [] __pci_register_driver+0x64/0x70 > > [0.660869] [] ? > > ftrace_define_fields_drm_vblank_event+0x6d/0x6d > > [0.660970] [] drm_pci_init+0x115/0x130 > > [0.661054] [] ? > > ftrace_define_fields_drm_vblank_event+0x6d/0x6d > > [0.661157] [] i915_init+0x6a/0x6c > > [0.661241] [] do_one_initcall+0x4e/0x170 > > [0.661328] [] ? parse_args+0xb0/0x360 > > [0.661412] [] kernel_init_freeable+0x106/0x19a > > [0.661497] [] ? do_early_param+0x86/0x86 > > [0.661580] [] ? rest_init+0xd0/0xd0 > > [0.661663] [] kernel_init+0xe/0x130 > > [0.661746] [] ret_from_fork+0x7c/0xb0 > > [0.661828] [] ? rest_init+0xd0/0xd0 > > [0.747947] [drm] GMBUS [i915 gmbus dpb] timed out, falling back to bit > > banging on pin 5 > > [0.758745] fbcon: inteldrmfb (fb0) is primary device > > > > -- > > Regards/Gruss, > > Boris. > > > > Sent from a fat crate under my desk. Formatting is fine. > > -- > signature.asc Description: This is a digitally signed message part _
Re: [Intel-gfx] intel_sdvo_init: trying to register non-static key
On Fri, Feb 07, 2014 at 01:12:22PM +0200, Imre Deak wrote: > On Fri, 2014-02-07 at 13:04 +0200, Jani Nikula wrote: > > Imre, is this the same i2c_del_adapter issue you're looking at? Any > > patches to try yet? > > It looks like the same issue yes. The following patch fixed it for me: > > http://patchwork.freedesktop.org/patch/18698/ > > I'm working on an improved version of this, but the main thing - to > remove the connector's sysfs entries before actually destroying the > encoder and connector objects - will remain the same as in the above > patch. You could shoot the final version my way so that I give it a run too. Thanks. -- Regards/Gruss, Boris. Sent from a fat crate under my desk. Formatting is fine. -- ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/vlv: Replaced Blitter ring based flips with MMIO Flips for VLV.
Please could you kindly elaborate here, it will help us to proceed further with this patch. Best Regards Akash -Original Message- From: Goel, Akash Sent: Monday, January 13, 2014 3:17 PM To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org Subject: RE: [Intel-gfx] [PATCH 2/2] drm/i915/vlv: Replaced Blitter ring based flips with MMIO Flips for VLV. >> Rather exporting deep magic from i915_gem, just emit the request after the >> mmio flip and use the normal signalling mechanisms. There are other users >> who could also use a request after a flip. Sorry, couldn't understand your point. With Command streamer based flips, we could use the cross ring MBOX mechanism at Hw level, to ensure that buffer is flipped only when the rendering is completed. But with MMIO flips, need to ensure that we somehow introduce a wait for the rendering to complete, before updating the Display Surface Address register, to effect the flip. Best Regards Akash -Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Thursday, January 09, 2014 5:02 PM To: Goel, Akash Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/vlv: Replaced Blitter ring based flips with MMIO Flips for VLV. On Thu, Jan 09, 2014 at 04:56:39PM +0530, akash.g...@intel.com wrote: > From: Akash Goel > > Using MMIO based flips now on VLV for Media power well residency optimization. > The blitter ring is currently being used just for the command streamer > based flip calls. For pure 3D workloads, with MMIO flips, there will > be no use of blitter ring and this will ensure the 100% residency in D0i3 for > Media well. > The other alternative of having Render ring based flip calls is not > being used, as that option adversly affects the performance (FPS) of > certain 3D Apps Rather exporting deep magic from i915_gem, just emit the request after the mmio flip and use the normal signalling mechanisms. There are other users who could also use a request after a flip. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 0/3] Rendering specific Hw workarounds for VLV
From: Akash Goel The following patches leads to stable behavior on VLV, especially when playing 3D Apps, benchmarks. Addressed review comments from Ville. Akash Goel (3): drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore' drm/i915/vlv: Added a rendering specific Hw WA 'WaReadAfterWriteHazard' drm/i915/vlv: Modified the programming of 2 regs in Ring initialisation drivers/gpu/drm/i915/intel_ringbuffer.c | 68 ++--- 1 file changed, 63 insertions(+), 5 deletions(-) -- 1.8.5.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/3] drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore'
From: Akash Goel
Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI
Store data commands.
v2: Modified the WA comment. (Ville)
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d897a19..2ac6600 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2183,6 +2183,29 @@ intel_ring_invalidate_all_caches(struct
intel_ring_buffer *ring)
uint32_t flush_domains;
int ret;
+ if (IS_VALLEYVIEW(ring->dev)) {
+ /*
+* WaTlbInvalidateStoreDataBefore
+* Before pipecontrol with TLB invalidate set, need 2 store
+* data commands (such as MI_STORE_DATA_IMM or
MI_STORE_DATA_INDEX)
+* Without this, hardware cannot guarantee the command after the
+* PIPE_CONTROL with TLB inv will not use the old TLB values.
+* FIXME, should also apply to snb, ivb
+*/
+ int i;
+ ret = intel_ring_begin(ring, 4 * 2);
+ if (ret)
+ return ret;
+ for (i = 0; i < 2; i++) {
+ intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
+ intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_INDEX <<
+ MI_STORE_DWORD_INDEX_SHIFT);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, MI_NOOP);
+ }
+ intel_ring_advance(ring);
+ }
+
flush_domains = 0;
if (ring->gpu_caches_dirty)
flush_domains = I915_GEM_GPU_DOMAINS;
--
1.8.5.2
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[Intel-gfx] [PATCH v2 3/3] drm/i915/vlv: Modified the programming of 2 regs in Ring initialisation
From: Akash Goel
Modified programming of following 2 regs in Render ring initialisation fn.
1. GFX_MODE_GEN7 (Enabling TLB invalidate)
2. MI_MODE (Enabling MI Flush)
v2: Removed the enabling of MI_FLUSH (Ville)
Added new comments (Ville).
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 49370a1..0d7d927b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -563,7 +563,10 @@ static int init_render_ring(struct intel_ring_buffer *ring)
int ret = init_ring_common(ring);
if (INTEL_INFO(dev)->gen > 3)
- I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
+ /* FIXME, should also apply to ivb */
+ if (!IS_VALLEYVIEW(dev))
+ I915_WRITE(MI_MODE,
+ _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
/* We need to disable the AsyncFlip performance optimisations in order
* to use MI_WAIT_FOR_EVENT within the CS. It should already be
@@ -579,10 +582,16 @@ static int init_render_ring(struct intel_ring_buffer
*ring)
I915_WRITE(GFX_MODE,
_MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
- if (IS_GEN7(dev))
- I915_WRITE(GFX_MODE_GEN7,
- _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
- _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
+ if (IS_GEN7(dev)) {
+ if (IS_VALLEYVIEW(dev)) {
+ /* FIXME, should also apply to ivb */
+ I915_WRITE(GFX_MODE_GEN7,
+ _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
+ } else
+ I915_WRITE(GFX_MODE_GEN7,
+ _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
+ _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
+ }
if (INTEL_INFO(dev)->gen >= 5) {
ret = init_pipe_control(ring);
--
1.8.5.2
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[Intel-gfx] [PATCH v2 2/3] drm/i915/vlv: Added a rendering specific Hw WA 'WaReadAfterWriteHazard'
From: Akash Goel
Added a new rendering specific Workaround 'WaReadAfterWriteHazard'.
In this WA, need to add 12 MI Store Dword commands to ensure proper
flush of h/w pipeline.
v2: Modified the WA comment (Ville)
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2ac6600..49370a1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2173,6 +2173,32 @@ intel_ring_flush_all_caches(struct intel_ring_buffer
*ring)
trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
+ if (IS_VALLEYVIEW(ring->dev)) {
+ /*
+* WaReadAfterWriteHazard
+* Send a number of Store Data commands here to finish
+* flushing hardware pipeline.This is needed in the case
+* where the next workload tries reading from the same
+* surface that this batch writes to. Without these StoreDWs,
+* not all of the data will actually be flushd to the surface
+* by the time the next batch starts reading it, possibly
+* causing a small amount of corruption.
+* FIXME, should also apply to snb, ivb.
+*/
+ int i;
+ ret = intel_ring_begin(ring, 4 * 12);
+ if (ret)
+ return ret;
+ for (i = 0; i < 12; i++) {
+ intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
+ intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_INDEX <<
+
MI_STORE_DWORD_INDEX_SHIFT);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, MI_NOOP);
+ }
+ intel_ring_advance(ring);
+ }
+
ring->gpu_caches_dirty = false;
return 0;
}
--
1.8.5.2
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Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/vlv: Modified the programming of 2 regs in Ring initialisation
On Fri, Feb 07, 2014 at 05:52:12PM +0530, akash.g...@intel.com wrote: > From: Akash Goel > > Modified programming of following 2 regs in Render ring initialisation fn. > 1. GFX_MODE_GEN7 (Enabling TLB invalidate) The changelog needs to explain why. According to the spec this is a pessimisation. > 2. MI_MODE (Enabling MI Flush) And this is out-of-date. Doesn't describe the actual change nor why. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 00/11] Enabling 180 degree rotation for sprite and crtc planes
From: Sagar Kamble These patches will enable 180 degree rotation for CRTC and Sprite planes. Changelog: 1. drm/i915: Add 180 degree primary plane rotation support Addressed review comments for CRTC rotation from FBC, page flip, CRTC active/ inactive perspective. 2. drm/i915: Calling rotate and inverse rotate transformations after clipping Moved drm_rect_rotate below clip operation in intel_update_plane. Added rotate and inverse rotate transforms for dest rect as well. 3. drm: Add drm_mode_create_rotation_property() Fixed bug in drm_mode_create_rotation_property to create entries only for supported rotations. Sagar Kamble (2): drm/i915: Add 180 degree primary plane rotation support drm/i915: Calling rotate and inverse rotate transformations after clipping Ville Syrjälä (9): drm: Move DRM_ROTATE bits out of omapdrm into drm_crtc.h drm: Add support_bits parameter to drm_property_create_bitmask() drm: Add drm_mode_create_rotation_property() drm/omap: Switch omapdrm over to drm_mode_create_rotation_property() drm: Add drm_rect rotation functions drm: Add drm_rotation_simplify() drm/i915: Add 180 degree sprite rotation support drm/i915: Make intel_plane_restore() return an error drm/i915: Add rotation property for sprites drivers/gpu/drm/drm_crtc.c | 69 - drivers/gpu/drm/drm_rect.c | 140 +++ drivers/gpu/drm/i915/i915_dma.c | 12 +++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 4 + drivers/gpu/drm/i915/intel_display.c | 86 - drivers/gpu/drm/i915/intel_drv.h | 5 +- drivers/gpu/drm/i915/intel_pm.c | 9 +++ drivers/gpu/drm/i915/intel_sprite.c | 101 +++-- drivers/gpu/drm/omapdrm/omap_drv.h | 7 -- drivers/gpu/drm/omapdrm/omap_plane.c | 17 ++--- include/drm/drm_crtc.h | 15 +++- include/drm/drm_rect.h | 6 ++ 13 files changed, 440 insertions(+), 32 deletions(-) -- 1.8.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 02/11] drm: Add support_bits parameter to drm_property_create_bitmask()
From: Ville Syrjälä
Make drm_property_create_bitmask() a bit more generic by allowing the
caller to specify which bits are in fact supported. This allows multiple
callers to use the same enum list, but still create different versions
of the same property with different list of supported bits.
Signed-off-by: Ville Syrjälä
Tested-by: Sagar Kamble
---
drivers/gpu/drm/drm_crtc.c | 6 +-
include/drm/drm_crtc.h | 3 ++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 3b7d32d..628d3d3 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -2906,7 +2906,8 @@ EXPORT_SYMBOL(drm_property_create_enum);
struct drm_property *drm_property_create_bitmask(struct drm_device *dev,
int flags, const char *name,
const struct drm_prop_enum_list *props,
-int num_values)
+int num_values,
+unsigned int supported_bits)
{
struct drm_property *property;
int i, ret;
@@ -2918,6 +2919,9 @@ struct drm_property *drm_property_create_bitmask(struct
drm_device *dev,
return NULL;
for (i = 0; i < num_values; i++) {
+ if (!(supported_bits & (1 << i)))
+ continue;
+
ret = drm_property_add_enum(property, i,
props[i].type,
props[i].name);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index d5c46c1..41b86d2 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1070,7 +1070,8 @@ extern struct drm_property
*drm_property_create_enum(struct drm_device *dev, int
struct drm_property *drm_property_create_bitmask(struct drm_device *dev,
int flags, const char *name,
const struct drm_prop_enum_list *props,
-int num_values);
+int num_values,
+unsigned int supported_bits);
struct drm_property *drm_property_create_range(struct drm_device *dev, int
flags,
const char *name,
uint64_t min, uint64_t max);
--
1.8.5
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[Intel-gfx] [PATCH v4 03/11] drm: Add drm_mode_create_rotation_property()
From: Ville Syrjälä
Add a function to create a standards compliant rotation property.
v4: For creating rotation bitmask property send number of values
as only number of set rotations
Signed-off-by: Ville Syrjälä
Signed-off-by: Sagar Kamble
Tested-by: Sagar Kamble
---
drivers/gpu/drm/drm_crtc.c | 33 +
include/drm/drm_crtc.h | 2 ++
2 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 628d3d3..e7bbbad 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -4118,3 +4118,36 @@ void drm_mode_config_cleanup(struct drm_device *dev)
idr_destroy(&dev->mode_config.crtc_idr);
}
EXPORT_SYMBOL(drm_mode_config_cleanup);
+
+/*
+* Function to get number of bits set in bitmask
+* using Brian Kernighan's Algorithm
+*/
+unsigned int bits_set(unsigned int n)
+{
+ unsigned int count = 0;
+
+ while (n) {
+ n &= (n-1);
+ count ++;
+ }
+ return count;
+}
+
+struct drm_property *drm_mode_create_rotation_property(struct drm_device *dev,
+ unsigned int
supported_rotations)
+{
+ static const struct drm_prop_enum_list props[] = {
+ { DRM_ROTATE_0, "rotate-0" },
+ { DRM_ROTATE_90, "rotate-90" },
+ { DRM_ROTATE_180, "rotate-180" },
+ { DRM_ROTATE_270, "rotate-270" },
+ { DRM_REFLECT_X, "reflect-x" },
+ { DRM_REFLECT_Y, "reflect-y" },
+ };
+
+ return drm_property_create_bitmask(dev, 0, "rotation",
+ props, bits_set(supported_rotations),
+ supported_rotations);
+}
+EXPORT_SYMBOL(drm_mode_create_rotation_property);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 41b86d2..4b3ac70 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1183,6 +1183,8 @@ extern int drm_format_plane_cpp(uint32_t format, int
plane);
extern int drm_format_horz_chroma_subsampling(uint32_t format);
extern int drm_format_vert_chroma_subsampling(uint32_t format);
extern const char *drm_get_format_name(uint32_t format);
+extern struct drm_property *drm_mode_create_rotation_property(struct
drm_device *dev,
+ unsigned int
supported_rotations);
/* Helpers */
static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev,
--
1.8.5
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[Intel-gfx] [PATCH v4 01/11] drm: Move DRM_ROTATE bits out of omapdrm into drm_crtc.h
From: Ville Syrjälä
The rotation property stuff should be standardized among all drivers.
Move the bits to drm_crtc.h from omap_drv.h.
Signed-off-by: Ville Syrjälä
Tested-by: Sagar Kamble
---
drivers/gpu/drm/omapdrm/omap_drv.h | 7 ---
include/drm/drm_crtc.h | 8
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h
b/drivers/gpu/drm/omapdrm/omap_drv.h
index 428b2981..aac8e10 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.h
+++ b/drivers/gpu/drm/omapdrm/omap_drv.h
@@ -119,13 +119,6 @@ struct omap_drm_private {
struct omap_drm_irq error_handler;
};
-/* this should probably be in drm-core to standardize amongst drivers */
-#define DRM_ROTATE_0 0
-#define DRM_ROTATE_90 1
-#define DRM_ROTATE_180 2
-#define DRM_ROTATE_270 3
-#define DRM_REFLECT_X 4
-#define DRM_REFLECT_Y 5
#ifdef CONFIG_DEBUG_FS
int omap_debugfs_init(struct drm_minor *minor);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 71727b6..d5c46c1 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -65,6 +65,14 @@ struct drm_object_properties {
uint64_t values[DRM_OBJECT_MAX_PROPERTY];
};
+/* rotation property bits */
+#define DRM_ROTATE_0 0
+#define DRM_ROTATE_90 1
+#define DRM_ROTATE_180 2
+#define DRM_ROTATE_270 3
+#define DRM_REFLECT_X 4
+#define DRM_REFLECT_Y 5
+
/*
* Note on terminology: here, for brevity and convenience, we refer to
connector
* control chips as 'CRTCs'. They can control any type of connector, VGA,
LVDS,
--
1.8.5
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[Intel-gfx] [PATCH v4 05/11] drm: Add drm_rect rotation functions
From: Ville Syrjälä
Add some helper functions to move drm_rects between different rotated
coordinate spaces. One function does the forward transform and
another does the inverse.
Signed-off-by: Ville Syrjälä
Tested-by: Sagar Kamble
---
drivers/gpu/drm/drm_rect.c | 140 +
include/drm/drm_rect.h | 6 ++
2 files changed, 146 insertions(+)
diff --git a/drivers/gpu/drm/drm_rect.c b/drivers/gpu/drm/drm_rect.c
index 7047ca0..631f5af 100644
--- a/drivers/gpu/drm/drm_rect.c
+++ b/drivers/gpu/drm/drm_rect.c
@@ -293,3 +293,143 @@ void drm_rect_debug_print(const struct drm_rect *r, bool
fixed_point)
DRM_DEBUG_KMS("%dx%d%+d%+d\n", w, h, r->x1, r->y1);
}
EXPORT_SYMBOL(drm_rect_debug_print);
+
+/**
+ * drm_rect_rotate - Rotate the rectangle
+ * @r: rectangle to be rotated
+ * @width: Width of the coordinate space
+ * @height: Height of the coordinate space
+ * @rotation: Transformation to be applied
+ *
+ * Apply @rotation to the coordinates of rectangle @r.
+ *
+ * @width and @height combined with @rotation define
+ * the location of the new origin.
+ *
+ * @width correcsponds to the horizontal and @height
+ * to the vertical axis of the untransformed coordinate
+ * space.
+ */
+void drm_rect_rotate(struct drm_rect *r,
+int width, int height,
+unsigned int rotation)
+{
+ struct drm_rect tmp;
+
+ if (rotation & (BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y))) {
+ tmp = *r;
+
+ if (rotation & BIT(DRM_REFLECT_X)) {
+ r->x1 = width - tmp.x2;
+ r->x2 = width - tmp.x1;
+ }
+
+ if (rotation & BIT(DRM_REFLECT_Y)) {
+ r->y1 = height - tmp.y2;
+ r->y2 = height - tmp.y1;
+ }
+ }
+
+ switch (rotation & 0xf) {
+ case BIT(DRM_ROTATE_0):
+ break;
+ case BIT(DRM_ROTATE_90):
+ tmp = *r;
+ r->x1 = tmp.y1;
+ r->x2 = tmp.y2;
+ r->y1 = width - tmp.x2;
+ r->y2 = width - tmp.x1;
+ break;
+ case BIT(DRM_ROTATE_180):
+ tmp = *r;
+ r->x1 = width - tmp.x2;
+ r->x2 = width - tmp.x1;
+ r->y1 = height - tmp.y2;
+ r->y2 = height - tmp.y1;
+ break;
+ case BIT(DRM_ROTATE_270):
+ tmp = *r;
+ r->x1 = height - tmp.y2;
+ r->x2 = height - tmp.y1;
+ r->y1 = tmp.x1;
+ r->y2 = tmp.x2;
+ break;
+ default:
+ break;
+ }
+}
+EXPORT_SYMBOL(drm_rect_rotate);
+
+/**
+ * drm_rect_rotate_inv - Inverse rotate the rectangle
+ * @r: rectangle to be rotated
+ * @width: Width of the coordinate space
+ * @height: Height of the coordinate space
+ * @rotation: Transformation whose inverse is to be applied
+ *
+ * Apply the inverse of @rotation to the coordinates
+ * of rectangle @r.
+ *
+ * @width and @height combined with @rotation define
+ * the location of the new origin.
+ *
+ * @width correcsponds to the horizontal and @height
+ * to the vertical axis of the original untransformed
+ * coordinate space, so that you never have to flip
+ * them when doing a rotatation and its inverse.
+ * That is, if you do:
+ *
+ * drm_rotate(&r, width, height, rotation);
+ * drm_rotate_inv(&r, width, height, rotation);
+ *
+ * you will always get back the original rectangle.
+ */
+void drm_rect_rotate_inv(struct drm_rect *r,
+int width, int height,
+unsigned int rotation)
+{
+ struct drm_rect tmp;
+
+ switch (rotation & 0xf) {
+ case BIT(DRM_ROTATE_0):
+ break;
+ case BIT(DRM_ROTATE_90):
+ tmp = *r;
+ r->x1 = width - tmp.y2;
+ r->x2 = width - tmp.y1;
+ r->y1 = tmp.x1;
+ r->y2 = tmp.x2;
+ break;
+ case BIT(DRM_ROTATE_180):
+ tmp = *r;
+ r->x1 = width - tmp.x2;
+ r->x2 = width - tmp.x1;
+ r->y1 = height - tmp.y2;
+ r->y2 = height - tmp.y1;
+ break;
+ case BIT(DRM_ROTATE_270):
+ tmp = *r;
+ r->x1 = tmp.y1;
+ r->x2 = tmp.y2;
+ r->y1 = height - tmp.x2;
+ r->y2 = height - tmp.x1;
+ break;
+ default:
+ break;
+ }
+
+ if (rotation & (BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y))) {
+ tmp = *r;
+
+ if (rotation & BIT(DRM_REFLECT_X)) {
+ r->x1 = width - tmp.x2;
+ r->x2 = width - tmp.x1;
+ }
+
+ if (rotation & BIT(DRM_REFLECT_Y)) {
+ r->y1 = height - tmp.y2;
+ r->y2 = height - tmp.y1;
+
[Intel-gfx] [PATCH v4 04/11] drm/omap: Switch omapdrm over to drm_mode_create_rotation_property()
From: Ville Syrjälä
Use the new drm_mode_create_rotation_property() in omapdrm.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/omapdrm/omap_plane.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c
b/drivers/gpu/drm/omapdrm/omap_plane.c
index 046d5e6..fee8f35 100644
--- a/drivers/gpu/drm/omapdrm/omap_plane.c
+++ b/drivers/gpu/drm/omapdrm/omap_plane.c
@@ -300,16 +300,13 @@ void omap_plane_install_properties(struct drm_plane
*plane,
if (priv->has_dmm) {
prop = priv->rotation_prop;
if (!prop) {
- const struct drm_prop_enum_list props[] = {
- { DRM_ROTATE_0, "rotate-0" },
- { DRM_ROTATE_90, "rotate-90" },
- { DRM_ROTATE_180, "rotate-180" },
- { DRM_ROTATE_270, "rotate-270" },
- { DRM_REFLECT_X, "reflect-x" },
- { DRM_REFLECT_Y, "reflect-y" },
- };
- prop = drm_property_create_bitmask(dev, 0, "rotation",
- props, ARRAY_SIZE(props));
+ prop = drm_mode_create_rotation_property(dev,
+
BIT(DRM_ROTATE_0) |
+
BIT(DRM_ROTATE_90) |
+
BIT(DRM_ROTATE_180) |
+
BIT(DRM_ROTATE_270) |
+
BIT(DRM_REFLECT_X) |
+
BIT(DRM_REFLECT_Y));
if (prop == NULL)
return;
priv->rotation_prop = prop;
--
1.8.5
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[Intel-gfx] [PATCH v4 06/11] drm: Add drm_rotation_simplify()
From: Ville Syrjälä
drm_rotation_simplify() can be used to eliminate unsupported rotation
flags. It will check if any unsupported flags are present, and if so
it will modify the rotation to an alternate form by adding 180 degrees
to rotation angle, and flipping the reflect x and y bits. The hope is
that this identity transform will eliminate the unsupported flags.
Of course that might not result in any more supported rotation, so
the caller is still responsible for checking the result afterwards.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_crtc.c | 30 ++
include/drm/drm_crtc.h | 2 ++
2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index e7bbbad..30e0008 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -4006,6 +4006,36 @@ int drm_format_vert_chroma_subsampling(uint32_t format)
EXPORT_SYMBOL(drm_format_vert_chroma_subsampling);
/**
+ * drm_rotation_simplify() - Try to simplify the rotation
+ * @rotation: Rotation to be simplified
+ * @supported_rotations: Supported rotations
+ *
+ * Attempt to simplify the rotation to a form that is supported.
+ * Eg. if the hardware supports everything except DRM_REFLECT_X
+ * one could call this function like this:
+ *
+ * drm_rotation_simplify(rotation, BIT(DRM_ROTATE_0) |
+ * BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_180) |
+ * BIT(DRM_ROTATE_270) | BIT(DRM_REFLECT_Y));
+ *
+ * to eliminate the DRM_ROTATE_X flag. Depending on what kind of
+ * transforms the hardware supports, this function may not
+ * be able to produce a supported transform, so the caller should
+ * check the result afterwards.
+ */
+unsigned int drm_rotation_simplify(unsigned int rotation,
+ unsigned int supported_rotations)
+{
+ if (rotation & ~supported_rotations) {
+ rotation ^= BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y);
+ rotation = (rotation & ~0xf) | BIT((ffs(rotation & 0xf) + 1) %
4);
+ }
+
+ return rotation;
+}
+EXPORT_SYMBOL(drm_rotation_simplify);
+
+/**
* drm_mode_config_init - initialize DRM mode_configuration structure
* @dev: DRM device
*
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 4b3ac70..18f2eed 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1185,6 +1185,8 @@ extern int drm_format_vert_chroma_subsampling(uint32_t
format);
extern const char *drm_get_format_name(uint32_t format);
extern struct drm_property *drm_mode_create_rotation_property(struct
drm_device *dev,
unsigned int
supported_rotations);
+extern unsigned int drm_rotation_simplify(unsigned int rotation,
+ unsigned int supported_rotations);
/* Helpers */
static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev,
--
1.8.5
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[Intel-gfx] [PATCH v4 10/11] drm/i915: Add 180 degree primary plane rotation support
From: Sagar Kamble
Primary planes support 180 degree rotation. Expose the feature
through rotation drm property.
v2: Calculating linear/tiled offsets based on pipe source width and
height. Added 180 degree rotation support in ironlake_update_plane.
v3: Checking if CRTC is active before issueing update_plane. Added
wait for vblank to make sure we dont overtake page flips. Disabling
FBC since it does not work with rotated planes.
v4: Updated rotation checks for pending flips, fbc disable. Creating
rotation property only for Gen4 onwards. Property resetting as part
of lastclose.
Signed-off-by: Sagar Kamble
Tested-by: Sagar Kamble
---
drivers/gpu/drm/i915/i915_dma.c | 12 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 86 ++--
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 9
5 files changed, 106 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 258b1be..fcd9e34 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1836,6 +1836,8 @@ int i915_driver_open(struct drm_device *dev, struct
drm_file *file)
void i915_driver_lastclose(struct drm_device * dev)
{
drm_i915_private_t *dev_priv = dev->dev_private;
+ struct drm_crtc *crtc;
+ struct drm_plane *plane;
/* On gen6+ we refuse to init without kms enabled, but then the drm core
* goes right around and calls lastclose. Check for this and don't clean
@@ -1843,6 +1845,16 @@ void i915_driver_lastclose(struct drm_device * dev)
if (!dev_priv)
return;
+ if (dev_priv->rotation_property) {
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
+ drm_object_property_set_value(&crtc->base,
+ dev_priv->rotation_property, 0);
+
+ list_for_each_entry(plane, &dev->mode_config.plane_list, head)
+ drm_object_property_set_value(&plane->base,
+ dev_priv->rotation_property, 0);
+ }
+
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
intel_fbdev_restore_mode(dev);
vga_switcheroo_process_delayed_switch();
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 57906c5..d3000c4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3553,6 +3553,7 @@
#define DISPPLANE_NO_LINE_DOUBLE 0
#define DISPPLANE_STEREO_POLARITY_FIRST 0
#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
+#define DISPPLANE_ROTATE_180 (1<<15)
#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
#define DISPPLANE_TILED (1<<10)
#define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4d4a0d9..4a4f650 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2037,6 +2037,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
unsigned long linear_offset;
u32 dspcntr;
u32 reg;
+ int pixel_size;
switch (plane) {
case 0:
@@ -2047,6 +2048,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
return -EINVAL;
}
+ pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
intel_fb = to_intel_framebuffer(fb);
obj = intel_fb->obj;
@@ -2054,6 +2056,8 @@ static int i9xx_update_plane(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
dspcntr = I915_READ(reg);
/* Mask out pixel format bits in case we change it */
dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
+ dspcntr &= ~DISPPLANE_ROTATE_180;
+
switch (fb->pixel_format) {
case DRM_FORMAT_C8:
dspcntr |= DISPPLANE_8BPP;
@@ -2095,8 +2099,6 @@ static int i9xx_update_plane(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
if (IS_G4X(dev))
dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
- I915_WRITE(reg, dspcntr);
-
linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
if (INTEL_INFO(dev)->gen >= 4) {
@@ -2109,6 +2111,17 @@ static int i9xx_update_plane(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
intel_crtc->dspaddr_offset = linear_offset;
}
+ if (intel_crtc->rotation == BIT(DRM_ROTATE_180)) {
+ dspcntr |= DISPPLANE_ROTATE_180;
+
+ x += (intel_crtc->config.pipe_src_w - 1);
+ y += (intel_crtc->config.pipe_src_h - 1);
+ linear_offset += (intel_crtc->config.pipe_src_h - 1) *
fb->pitches[0] +
+ inte
[Intel-gfx] [PATCH v4 07/11] drm/i915: Add 180 degree sprite rotation support
From: Ville Syrjälä
The sprite planes (in fact all display planes starting from gen4)
support 180 degree rotation. Add the relevant low level bits to the
sprite code to make use of that feature.
The upper layers are not yet plugged in.
v2: HSW handles the rotated buffer offset automagically
Signed-off-by: Ville Syrjälä
Tested-by: Sagar Kamble
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_drv.h| 1 +
drivers/gpu/drm/i915/intel_sprite.c | 37 +
3 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index abd18cd..57906c5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3637,6 +3637,7 @@
#define DVS_YUV_ORDER_UYVY (1<<16)
#define DVS_YUV_ORDER_YVYU (2<<16)
#define DVS_YUV_ORDER_VYUY (3<<16)
+#define DVS_ROTATE_180 (1<<15)
#define DVS_DEST_KEY (1<<2)
#define DVS_TRICKLE_FEED_DISABLE (1<<14)
#define DVS_TILED(1<<10)
@@ -3707,6 +3708,7 @@
#define SPRITE_YUV_ORDER_UYVY(1<<16)
#define SPRITE_YUV_ORDER_YVYU(2<<16)
#define SPRITE_YUV_ORDER_VYUY(3<<16)
+#define SPRITE_ROTATE_180(1<<15)
#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
#define SPRITE_INT_GAMMA_ENABLE (1<<13)
#define SPRITE_TILED (1<<10)
@@ -3780,6 +3782,7 @@
#define SP_YUV_ORDER_UYVY(1<<16)
#define SP_YUV_ORDER_YVYU(2<<16)
#define SP_YUV_ORDER_VYUY(3<<16)
+#define SP_ROTATE_180(1<<15)
#define SP_TILED (1<<10)
#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 44067bc..85864fc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -397,6 +397,7 @@ struct intel_plane {
unsigned int crtc_w, crtc_h;
uint32_t src_x, src_y;
uint32_t src_w, src_h;
+ unsigned int rotation;
/* Since we need to change the watermarks before/after
* enabling/disabling the planes, we need to store the parameters here
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 336ae6c..477d4d7 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -60,6 +60,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc
*crtc,
sprctl &= ~SP_PIXFORMAT_MASK;
sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
sprctl &= ~SP_TILED;
+ sprctl &= ~SP_ROTATE_180;
switch (fb->pixel_format) {
case DRM_FORMAT_YUYV:
@@ -131,6 +132,14 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc
*crtc,
fb->pitches[0]);
linear_offset -= sprsurf_offset;
+ if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
+ sprctl |= SP_ROTATE_180;
+
+ x += src_w;
+ y += src_h;
+ linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
+ }
+
I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
@@ -238,6 +247,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
sprctl &= ~SPRITE_RGB_ORDER_RGBX;
sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
sprctl &= ~SPRITE_TILED;
+ sprctl &= ~SPRITE_ROTATE_180;
switch (fb->pixel_format) {
case DRM_FORMAT_XBGR:
@@ -299,6 +309,17 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
pixel_size, fb->pitches[0]);
linear_offset -= sprsurf_offset;
+ if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
+ sprctl |= SPRITE_ROTATE_180;
+
+ /* HSW does this automagically in hardware */
+ if (!IS_HASWELL(dev)) {
+ x += src_w;
+ y += src_h;
+ linear_offset += src_h * fb->pitches[0] + src_w *
pixel_size;
+ }
+ }
+
I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
@@ -422,6 +443,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
dvscntr &= ~DVS_RGB_ORDER_XBGR;
dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
dvscntr &= ~DVS_TILED;
+ dvscntr &= ~DVS_ROTATE_180;
switch (fb->pixel_format) {
case DRM_FORMAT_XBGR:
@@ -478,6 +500,14 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
pixel_size, fb->pitches[0]);
linear_offset -= dvssurf_offset;
+ if (intel_plane->rotation == BI
[Intel-gfx] [PATCH v4 09/11] drm/i915: Add rotation property for sprites
From: Ville Syrjälä
Sprite planes support 180 degree rotation. The lower layers are now in
place, so hook in the standard rotation property to expose the feature
to the users.
Signed-off-by: Ville Syrjälä
Tested-by: Sagar Kamble
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_sprite.c | 42 -
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fa37dfd..ea2efc3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1548,6 +1548,7 @@ typedef struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
+ struct drm_property *rotation_property;
uint32_t hw_context_size;
struct list_head context_list;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 511934c..62b9f84 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1047,6 +1047,30 @@ out_unlock:
return ret;
}
+static int intel_plane_set_property(struct drm_plane *plane,
+ struct drm_property *prop,
+ uint64_t val)
+{
+ struct drm_i915_private *dev_priv = plane->dev->dev_private;
+ struct intel_plane *intel_plane = to_intel_plane(plane);
+ uint64_t old_val;
+ int ret = -ENOENT;
+
+ if (prop == dev_priv->rotation_property) {
+ /* exactly one rotation angle please */
+ if (hweight32(val & 0xf) != 1)
+ return -EINVAL;
+
+ old_val = intel_plane->rotation;
+ intel_plane->rotation = val;
+ ret = intel_plane_restore(plane);
+ if (ret)
+ intel_plane->rotation = old_val;
+ }
+
+ return ret;
+}
+
int intel_plane_restore(struct drm_plane *plane)
{
struct intel_plane *intel_plane = to_intel_plane(plane);
@@ -1073,6 +1097,7 @@ static const struct drm_plane_funcs intel_plane_funcs = {
.update_plane = intel_update_plane,
.disable_plane = intel_disable_plane,
.destroy = intel_destroy_plane,
+ .set_property = intel_plane_set_property,
};
static uint32_t ilk_plane_formats[] = {
@@ -1109,6 +1134,7 @@ static uint32_t vlv_plane_formats[] = {
int
intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
{
+ struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_plane *intel_plane;
unsigned long possible_crtcs;
const uint32_t *plane_formats;
@@ -1183,8 +1209,22 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe,
int plane)
&intel_plane_funcs,
plane_formats, num_plane_formats,
false);
- if (ret)
+ if (ret) {
kfree(intel_plane);
+ goto out;
+ }
+
+ if (!dev_priv->rotation_property)
+ dev_priv->rotation_property =
+ drm_mode_create_rotation_property(dev,
+ BIT(DRM_ROTATE_0) |
+ BIT(DRM_ROTATE_180));
+
+ if (dev_priv->rotation_property)
+ drm_object_attach_property(&intel_plane->base.base,
+ dev_priv->rotation_property,
+ intel_plane->rotation);
+ out:
return ret;
}
--
1.8.5
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[Intel-gfx] [PATCH v4 08/11] drm/i915: Make intel_plane_restore() return an error
From: Ville Syrjälä
Propagate the error from intel_update_plane() up through
intel_plane_restore() to the caller. This will be used for
rollback purposes when setting properties fails.
Signed-off-by: Ville Syrjälä
Tested-by: Sagar Kamble
---
drivers/gpu/drm/i915/intel_drv.h| 2 +-
drivers/gpu/drm/i915/intel_sprite.c | 14 +++---
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 85864fc..7a79b8e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -897,7 +897,7 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t
sdvo_reg, bool is_sdvob);
int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
enum plane plane);
-void intel_plane_restore(struct drm_plane *plane);
+int intel_plane_restore(struct drm_plane *plane);
void intel_plane_disable(struct drm_plane *plane);
int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
struct drm_file *file_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 477d4d7..511934c 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1047,18 +1047,18 @@ out_unlock:
return ret;
}
-void intel_plane_restore(struct drm_plane *plane)
+int intel_plane_restore(struct drm_plane *plane)
{
struct intel_plane *intel_plane = to_intel_plane(plane);
if (!plane->crtc || !plane->fb)
- return;
+ return 0;
- intel_update_plane(plane, plane->crtc, plane->fb,
- intel_plane->crtc_x, intel_plane->crtc_y,
- intel_plane->crtc_w, intel_plane->crtc_h,
- intel_plane->src_x, intel_plane->src_y,
- intel_plane->src_w, intel_plane->src_h);
+ return intel_update_plane(plane, plane->crtc, plane->fb,
+ intel_plane->crtc_x, intel_plane->crtc_y,
+ intel_plane->crtc_w, intel_plane->crtc_h,
+ intel_plane->src_x, intel_plane->src_y,
+ intel_plane->src_w, intel_plane->src_h);
}
void intel_plane_disable(struct drm_plane *plane)
--
1.8.5
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[Intel-gfx] [PATCH v2 1/1] tests/kms_rotate_crc: Test to verify rotation of planes through CRC
From: Sagar Kamble
This test will verify 180 degree rotation of CRTC and sprite planes
by grabbing CRC for already rotated image and comparing with CRC calculated
after triggering rotation through DRM property.
v2: Using cairo_rotate to created reference rotated version of CRTC and
Sprite Image. Moved variable data above igt_main. Logging to stdout.
Created separate subtest for verifying CRTC alone and CRTC+Sprite combination.
Signed-off-by: Sagar Kamble
Tested-by: Sagar Kamble
---
tests/Makefile.sources | 1 +
tests/kms_rotate_crc.c | 586 +
2 files changed, 587 insertions(+)
create mode 100644 tests/kms_rotate_crc.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index a8c0c96..c19fc88 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -59,6 +59,7 @@ TESTS_progs_M = \
kms_flip \
kms_pipe_crc_basic \
kms_render \
+ kms_rotate_crc \
kms_setmode \
pm_lpsp \
pm_pc8 \
diff --git a/tests/kms_rotate_crc.c b/tests/kms_rotate_crc.c
new file mode 100644
index 000..06d9611
--- /dev/null
+++ b/tests/kms_rotate_crc.c
@@ -0,0 +1,586 @@
+/*
+ * Copyright ?? 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Author:
+ *Sagar Kamble
+ */
+
+
+#include
+#include
+#include
+#include
+
+#include "drm_fourcc.h"
+
+#include "drmtest.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+
+#define DRM_ROTATE_0 0
+#define DRM_ROTATE_90 1
+#define DRM_ROTATE_180 2
+#define DRM_ROTATE_270 3
+#define DRM_REFLECT_X 4
+#define DRM_REFLECT_Y 5
+#define DRM_ROTATE_NUM 6
+
+#define BIT(x) (1 << x)
+
+typedef struct {
+ struct kmstest_connector_config config;
+ drmModeModeInfo mode;
+ struct kmstest_fb fb[DRM_ROTATE_NUM];
+ struct kmstest_fb sprite_fb[DRM_ROTATE_NUM]
+} connector_t;
+
+typedef struct {
+ int drm_fd;
+ igt_debugfs_t debugfs;
+ drmModeRes *resources;
+ igt_crc_t ref_crtc_crc[DRM_ROTATE_NUM];
+ igt_crc_t ref_sprite_crc[DRM_ROTATE_NUM];
+ igt_pipe_crc_t **pipe_crc;
+ uint32_t crtc_id;
+ uint32_t sprite_id;
+ uint32_t crtc_idx;
+ uint32_t crtc_fb_id[DRM_ROTATE_NUM];
+ uint32_t sprite_fb_id[DRM_ROTATE_NUM];
+} data_t;
+
+static void set_rotation(int drm_fd, bool is_sprite, uint32_t plane_id,
uint64_t rotation)
+{
+ int i = 0, j = 0, ret = 0;
+ drmModeObjectPropertiesPtr props = NULL;
+
+ props = drmModeObjectGetProperties(drm_fd, plane_id,
+ is_sprite ? DRM_MODE_OBJECT_PLANE :
DRM_MODE_OBJECT_CRTC);
+ fprintf(stdout, "\nPlane id: 0x%x, Count_props=%d ", plane_id,
props->count_props);
+
+ for (i = 0; i < props->count_props; i++)
+ {
+ drmModePropertyPtr prop = drmModeGetProperty(drm_fd,
props->props[i]);
+ fprintf(stdout, "\nProp->name=%s ", prop->name);
+
+ if (strcmp(prop->name, "rotation") == 0)
+ {
+ igt_assert(prop->flags & DRM_MODE_PROP_BITMASK);
+ fprintf(stdout, "\nRotation property enum count %d",
prop->count_enums);
+ fprintf(stdout, "\nRotation type\tValue");
+ for (j = 0; j < prop->count_enums; j++)
+ fprintf(stdout, "\n%s: 0x%x",
prop->enums[j].name, prop->enums[j].value);
+
+ ret = drmModeObjectSetProperty(drm_fd, plane_id,
is_sprite ? DRM_MODE_OBJECT_PLANE : DRM_MODE_OBJECT_CRTC,
+
(uint32_t)prop->prop_id, rotation);
+ if (ret)
+ {
+ fprintf(stdout, "\nRotation setting\(0x%x\)
failed !!!", rotation);
+ return;
+ }
Re: [Intel-gfx] [PATCH 02/13] drm/i915: Implement command buffer parsing logic
On Wed, 29 Jan 2014, bradley.d.vol...@intel.com wrote:
> +static int valid_reg(const u32 *table, int count, u32 addr)
> +{
> + if (table && count != 0) {
> + int i;
> +
> + for (i = 0; i < count; i++) {
> + if (table[i] == addr)
> + return 1;
> + }
> + }
You go to great lengths to validate the register tables are sorted, but
in the end you don't take advantage of this fact by bailing out early if
the lookup goes past the addr.
Is this optimization the main reason for having the tables sorted, or
are there other reasons too (I couldn't find any)?
I'm beginning to wonder if this is a premature optimization that adds
extra code. For master restricted registers you will always scan the
regular reg table completely first. Perhaps a better option would be to
have all registers in the same table, with a separate master flag,
ordered by how frequently they are expected to be used. We do want to
optimize for the happy day scenario. But maybe it's too early to tell.
I'm inclined to ripping out the sort requirement and check, if the sole
purpose is optimization, for simplicity's sake.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH] drm/i915: Disable dp aux irq on g4x
Apparently it's broken in the exact same way as the gmbus irq. For reference of the full story see commit c12aba5aa0e60b7947bc8b6ea25ef55c4acf81a4 Author: Jiri Kosina Date: Tue Mar 19 09:56:57 2013 +0100 drm/i915: stop using GMBUS IRQs on Gen4 chips The effect is that we have a storm of unclaimed interrupts on the legacy irq line. If that one is used by a different device then the kernel will complain and rather quickly kill the irq source. Which breaks any device trying to actually use the legacy irq line. This regression has been introduced commit 4aeebd7443e36b0a40032e518a9338f48bd27efc Author: Daniel Vetter Date: Thu Oct 31 09:53:36 2013 +0100 drm/i915: dp aux irq support for g4x/vlv v2: Cross-reference dp aux and gmbus gen4 comments. Cc: Jani Nikula Cc: Jiri Kosina Cc: Chris Wilson Reported-and-tested-by: Jiri Kosina Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 10 +- drivers/gpu/drm/i915/intel_i2c.c | 7 --- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index c00b6e352c2b..341da95ddc87 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -390,6 +390,14 @@ static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp, } } +/* + * dp aux on gen4 seems to be able to generate legacy interrupts even when in MSI + * mode (similar to how gmbus is broken). This results in spurious interrupt + * warnings if the legacy irq no. is shared with another device. The kernel then + * disables that interrupt source and so prevents the other device from working + * properly. + */ +#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) static int intel_dp_aux_ch(struct intel_dp *intel_dp, uint8_t *send, int send_bytes, @@ -404,7 +412,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, int i, ret, recv_bytes; uint32_t status; int try, precharge, clock = 0; - bool has_aux_irq = true; + bool has_aux_irq = HAS_AUX_IRQ(dev); uint32_t timeout; /* dp aux is extremely sensitive to irq latency, hence request the diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index b1dc33f47899..1a3d512e4efa 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -260,9 +260,10 @@ intel_gpio_setup(struct intel_gmbus *bus, u32 pin) /* * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI - * mode. This results in spurious interrupt warnings if the legacy irq no. is - * shared with another device. The kernel then disables that interrupt source - * and so prevents the other device from working properly. + * mode (similar to how dp aux is broken). This results in spurious interrupt + * warnings if the legacy irq no. is shared with another device. The kernel then + * disables that interrupt source and so prevents the other device from working + * properly. */ #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) static int -- 1.8.5.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/vlv: Modified the programming of 2 regs in Ring initialisation
> 1. GFX_MODE_GEN7 (Enabling TLB invalidate) >> The changelog needs to explain why. According to the spec this is a >> pessimisation. Ok, Will look into this. > 2. MI_MODE (Enabling MI Flush) >> And this is out-of-date. Doesn't describe the actual change nor why. Sorry I did not update the commit message properly. Actually I have reverted the change, enabling of MI_FLUSH, in this new version of the patch, as you also said this is obsolete. Best Regards Akash -Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Friday, February 07, 2014 6:01 PM To: Goel, Akash Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/vlv: Modified the programming of 2 regs in Ring initialisation On Fri, Feb 07, 2014 at 05:52:12PM +0530, akash.g...@intel.com wrote: > From: Akash Goel > > Modified programming of following 2 regs in Render ring initialisation fn. > 1. GFX_MODE_GEN7 (Enabling TLB invalidate) The changelog needs to explain why. According to the spec this is a pessimisation. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] Fix LIBDRM_PATH for top android build
Sorry for late reply, I still have trouble keeping track my patches with this email-patching-way-of-doing-things. Yes, that is correct, the tools should also benefit from the same fix. Joao -Original Message- From: Lespiau, Damien Sent: Friday, January 31, 2014 10:20 AM To: Barbalho, Rafael Cc: Mateo Lozano, Oscar; Santos, Joao; intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH] Fix LIBDRM_PATH for top android build On Fri, Jan 31, 2014 at 09:36:25AM +, Barbalho, Rafael wrote: > The patch is incomplete. If you change these macros in the tests > directory then why does it not need to be changed in the tools > directory also? > > I have a patch that refactors these macros into a third file, I'll > send it up for review later once I fix another issue I have in the > patch series. Holding the horses then! -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/vlv: Modified the programming of 2 regs in Ring initialisation
On Fri, Feb 07, 2014 at 05:52:12PM +0530, akash.g...@intel.com wrote:
> From: Akash Goel
>
> Modified programming of following 2 regs in Render ring initialisation fn.
> 1. GFX_MODE_GEN7 (Enabling TLB invalidate)
> 2. MI_MODE (Enabling MI Flush)
>
> v2: Removed the enabling of MI_FLUSH (Ville)
> Added new comments (Ville).
>
> Signed-off-by: Akash Goel
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 19 ++-
> 1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 49370a1..0d7d927b 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -563,7 +563,10 @@ static int init_render_ring(struct intel_ring_buffer
> *ring)
> int ret = init_ring_common(ring);
>
> if (INTEL_INFO(dev)->gen > 3)
> - I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
> + /* FIXME, should also apply to ivb */
> + if (!IS_VALLEYVIEW(dev))
> + I915_WRITE(MI_MODE,
> + _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
Was this supposed to be here? I guess it should be a separate patch.
>
> /* We need to disable the AsyncFlip performance optimisations in order
>* to use MI_WAIT_FOR_EVENT within the CS. It should already be
> @@ -579,10 +582,16 @@ static int init_render_ring(struct intel_ring_buffer
> *ring)
> I915_WRITE(GFX_MODE,
> _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
>
> - if (IS_GEN7(dev))
> - I915_WRITE(GFX_MODE_GEN7,
> -_MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
> -_MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
> + if (IS_GEN7(dev)) {
> + if (IS_VALLEYVIEW(dev)) {
> + /* FIXME, should also apply to ivb */
> + I915_WRITE(GFX_MODE_GEN7,
> + _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
> + } else
> + I915_WRITE(GFX_MODE_GEN7,
> + _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
> + _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
> + }
>
> if (INTEL_INFO(dev)->gen >= 5) {
> ret = init_pipe_control(ring);
> --
> 1.8.5.2
>
> ___
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--
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Intel OTC
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/vlv: Replaced Blitter ring based flips with MMIO Flips for VLV.
On Fri, Feb 07, 2014 at 11:59:29AM +, Goel, Akash wrote: > Please could you kindly elaborate here, it will help us to proceed further > with this patch. As Chris said, instead of rolling your own code to track when flips are emitted to the ring, simply add a real request (with the add_request function) like the execbuf paths. Then add any additional trackin you need to our request structure. -Daniel > > Best Regards > Akash > > -Original Message- > From: Goel, Akash > Sent: Monday, January 13, 2014 3:17 PM > To: Chris Wilson > Cc: intel-gfx@lists.freedesktop.org > Subject: RE: [Intel-gfx] [PATCH 2/2] drm/i915/vlv: Replaced Blitter ring > based flips with MMIO Flips for VLV. > > >> Rather exporting deep magic from i915_gem, just emit the request after the > >> mmio flip and use the normal signalling mechanisms. There are other users > >> who could also use a request after a flip. > > Sorry, couldn't understand your point. > > With Command streamer based flips, we could use the cross ring MBOX mechanism > at Hw level, to ensure that buffer is flipped only when the rendering is > completed. > > But with MMIO flips, need to ensure that we somehow introduce a wait for the > rendering to complete, before updating the Display Surface Address register, > to effect the flip. > > Best Regards > Akash > > -Original Message- > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] > Sent: Thursday, January 09, 2014 5:02 PM > To: Goel, Akash > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/vlv: Replaced Blitter ring > based flips with MMIO Flips for VLV. > > On Thu, Jan 09, 2014 at 04:56:39PM +0530, akash.g...@intel.com wrote: > > From: Akash Goel > > > > Using MMIO based flips now on VLV for Media power well residency > > optimization. > > The blitter ring is currently being used just for the command streamer > > based flip calls. For pure 3D workloads, with MMIO flips, there will > > be no use of blitter ring and this will ensure the 100% residency in D0i3 > > for Media well. > > The other alternative of having Render ring based flip calls is not > > being used, as that option adversly affects the performance (FPS) of > > certain 3D Apps > > Rather exporting deep magic from i915_gem, just emit the request after the > mmio flip and use the normal signalling mechanisms. There are other users who > could also use a request after a flip. > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 21/28] lib: Include drm_fourcc.h from igt_kms.h
This include is needed for the DRM_FORMAT* defines used in the fb creation helpers. Signed-off-by: Damien Lespiau --- lib/igt_kms.h | 1 + tests/kms_cursor_crc.c | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/lib/igt_kms.h b/lib/igt_kms.h index 8110dad..96dd9e4 100644 --- a/lib/igt_kms.h +++ b/lib/igt_kms.h @@ -27,6 +27,7 @@ #include +#include #include #include diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c index 6cdb785..e8c923f 100644 --- a/tests/kms_cursor_crc.c +++ b/tests/kms_cursor_crc.c @@ -28,8 +28,6 @@ #include #include -#include "drm_fourcc.h" - #include "drmtest.h" #include "igt_debugfs.h" #include "igt_kms.h" -- 1.8.3.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 15/28] lib/crc: Factor out reading a single CRC value
Signed-off-by: Damien Lespiau
---
lib/igt_debugfs.c | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index 4b96521..a0d84bf 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -301,6 +301,21 @@ static bool pipe_crc_init_from_string(igt_crc_t *crc,
const char *line)
return n == 6;
}
+static bool read_one_crc(igt_pipe_crc_t *pipe_crc, igt_crc_t *out)
+{
+ ssize_t bytes_read;
+ char buf[pipe_crc->buffer_len];
+
+ bytes_read = read(pipe_crc->crc_fd, &buf, pipe_crc->line_len);
+ igt_assert_cmpint(bytes_read, ==, pipe_crc->line_len);
+ buf[bytes_read] = '\0';
+
+ if (!pipe_crc_init_from_string(out, buf))
+ return false;
+
+ return true;
+}
+
/*
* Read @n_crcs from the @pipe_crc. This function blocks until @n_crcs are
* retrieved.
@@ -309,9 +324,7 @@ void
igt_pipe_crc_get_crcs(igt_pipe_crc_t *pipe_crc, int n_crcs,
igt_crc_t **out_crcs)
{
- ssize_t bytes_read;
igt_crc_t *crcs;
- char buf[pipe_crc->buffer_len];
int n = 0;
crcs = calloc(n_crcs, sizeof(igt_crc_t));
@@ -319,11 +332,7 @@ igt_pipe_crc_get_crcs(igt_pipe_crc_t *pipe_crc, int n_crcs,
do {
igt_crc_t *crc = &crcs[n];
- bytes_read = read(pipe_crc->crc_fd, &buf, pipe_crc->line_len);
- igt_assert_cmpint(bytes_read, ==, pipe_crc->line_len);
- buf[bytes_read] = '\0';
-
- if (!pipe_crc_init_from_string(crc, buf))
+ if (!read_one_crc(pipe_crc, crc))
continue;
n++;
--
1.8.3.1
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[Intel-gfx] [PATCH igt 24/28] lib/display: Add a way to wait at every commit for inspection
Signed-off-by: Damien Lespiau
---
lib/igt_kms.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 74e52b6..fbbf6aa 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1368,6 +1368,9 @@ int igt_display_commit(igt_display_t *display)
LOG_UNINDENT(display);
+ if (getenv("IGT_DISPLAY_WAIT_AT_COMMIT"))
+ igt_wait_for_keypress();
+
return 0;
}
--
1.8.3.1
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[Intel-gfx] [PATCH igt 08/28] tests/kms_cursor_crc: Move the array of cursor fb_ids to the stack
This array is not used outside ouf create_cursor_fb(). A stack allocated
array is enough.
Signed-off-by: Damien Lespiau
---
tests/kms_cursor_crc.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c
index 38aa1ab..9ddee06 100644
--- a/tests/kms_cursor_crc.c
+++ b/tests/kms_cursor_crc.c
@@ -52,7 +52,6 @@ typedef struct {
int drm_fd;
igt_debugfs_t debugfs;
drmModeRes *resources;
- uint32_t fb_id[NUM_CURSOR_TYPES];
struct kmstest_fb fb[NUM_CURSOR_TYPES];
igt_pipe_crc_t **pipe_crc;
} data_t;
@@ -313,11 +312,12 @@ static void create_cursor_fb(data_t *data,
double r, double g, double b, double a)
{
cairo_t *cr;
+ uint32_t fb_id[NUM_CURSOR_TYPES];
- data->fb_id[cursor_type] = kmstest_create_fb2(data->drm_fd, 64, 64,
- DRM_FORMAT_ARGB,
false,
- &data->fb[cursor_type]);
- igt_assert(data->fb_id[cursor_type]);
+ fb_id[cursor_type] = kmstest_create_fb2(data->drm_fd, 64, 64,
+ DRM_FORMAT_ARGB, false,
+ &data->fb[cursor_type]);
+ igt_assert(fb_id[cursor_type]);
cr = kmstest_get_cairo_ctx(data->drm_fd,
&data->fb[cursor_type]);
--
1.8.3.1
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[Intel-gfx] [PATCH igt 12/28] kms_cursor_crc: Port the test to the new modeset API
Signed-off-by: Damien Lespiau
---
tests/kms_cursor_crc.c | 201 ++---
1 file changed, 106 insertions(+), 95 deletions(-)
diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c
index 9ddee06..76e2845 100644
--- a/tests/kms_cursor_crc.c
+++ b/tests/kms_cursor_crc.c
@@ -43,101 +43,66 @@ enum cursor_type {
};
typedef struct {
- struct kmstest_connector_config config;
- drmModeModeInfo mode;
- struct kmstest_fb fb;
-} connector_t;
-
-typedef struct {
int drm_fd;
igt_debugfs_t debugfs;
- drmModeRes *resources;
+ igt_display_t display;
+ struct kmstest_fb primary_fb;
struct kmstest_fb fb[NUM_CURSOR_TYPES];
igt_pipe_crc_t **pipe_crc;
} data_t;
typedef struct {
data_t *data;
- uint32_t crtc_id;
- int crtc_idx;
+ igt_output_t *output;
+ enum pipe pipe;
igt_crc_t ref_crc;
bool crc_must_match;
int left, right, top, bottom;
} test_data_t;
-static bool
-connector_set_mode(data_t *data, connector_t *connector, drmModeModeInfo *mode)
+static void create_fb_for_mode(data_t *data, drmModeModeInfo *mode)
{
- struct kmstest_connector_config *config = &connector->config;
unsigned int fb_id;
cairo_t *cr;
- int ret;
fb_id = kmstest_create_fb2(data->drm_fd,
mode->hdisplay, mode->vdisplay,
DRM_FORMAT_XRGB,
- false, &connector->fb);
+ false, &data->primary_fb);
igt_assert(fb_id);
/* black */
- cr = kmstest_get_cairo_ctx(data->drm_fd, &connector->fb);
+ cr = kmstest_get_cairo_ctx(data->drm_fd, &data->primary_fb);
kmstest_paint_color(cr, 0, 0, mode->hdisplay, mode->vdisplay,
0.0, 0.0, 0.0);
igt_assert(cairo_status(cr) == 0);
cairo_destroy(cr);
-
-#if 0
- fprintf(stdout, "Using pipe %c, %dx%d\n", pipe_name(config->pipe),
- mode->hdisplay, mode->vdisplay);
-#endif
-
- ret = drmModeSetCrtc(data->drm_fd,
-config->crtc->crtc_id,
-connector->fb.fb_id,
-0, 0, /* x, y */
-&config->connector->connector_id,
-1,
-mode);
- igt_assert(ret == 0);
-
- return 0;
}
-static igt_pipe_crc_t *create_crc(data_t *data, int crtc_idx)
+static igt_pipe_crc_t *create_crc(data_t *data, enum pipe pipe)
{
igt_pipe_crc_t *crc;
- crc = igt_pipe_crc_new(&data->debugfs, data->drm_fd, crtc_idx,
+ crc = igt_pipe_crc_new(&data->debugfs, data->drm_fd, pipe,
INTEL_PIPE_CRC_SOURCE_AUTO);
return crc;
}
-static void display_init(data_t *data)
-{
- data->resources = drmModeGetResources(data->drm_fd);
- igt_assert(data->resources);
-
- data->pipe_crc = calloc(data->resources->count_crtcs,
sizeof(data->pipe_crc[0]));
-}
-
-static void display_fini(data_t *data)
-{
- free(data->pipe_crc);
-
- drmModeFreeResources(data->resources);
-}
-
static void do_single_test(test_data_t *test_data, int x, int y)
{
data_t *data = test_data->data;
- igt_pipe_crc_t *pipe_crc = data->pipe_crc[test_data->crtc_idx];
+ igt_display_t *display = &data->display;
+ igt_pipe_crc_t *pipe_crc = data->pipe_crc[test_data->pipe];
igt_crc_t *crcs = NULL;
+ igt_plane_t *cursor;
printf("."); fflush(stdout);
- igt_assert(drmModeMoveCursor(data->drm_fd, test_data->crtc_id, x, y) ==
0);
- igt_wait_for_vblank(data->drm_fd, test_data->crtc_idx);
+ cursor = igt_ouput_get_plane(test_data->output, IGT_PLANE_CURSOR);
+ igt_plane_set_position(cursor, x, y);
+ igt_display_commit(display);
+ igt_wait_for_vblank(data->drm_fd, test_data->pipe);
igt_pipe_crc_start(pipe_crc);
igt_pipe_crc_get_crcs(pipe_crc, 1, &crcs);
@@ -158,18 +123,39 @@ static void do_test(test_data_t *test_data,
do_single_test(test_data, left, bottom);
}
+static void cursor_enable(test_data_t *test_data, enum cursor_type cursor_type)
+{
+ data_t *data = test_data->data;
+ igt_display_t *display = &data->display;
+ igt_output_t *output = test_data->output;
+ igt_plane_t *cursor;
+
+ cursor = igt_ouput_get_plane(output, IGT_PLANE_CURSOR);
+ igt_plane_set_fb(cursor, &data->fb[cursor_type]);
+ igt_display_commit(display);
+}
+
+static void cursor_disable(test_data_t *test_data)
+{
+ data_t *data = test_data->data;
+ igt_display_t *display = &data->display;
+ igt_output_t *output = test_data->output;
+ igt_plane_t *cursor;
+
+ cursor = igt_ouput_get_plane(output, IGT_PLANE_CURSOR);
+ igt_plane_set_fb(cursor, NULL);
+ ig
[Intel-gfx] [PATCH igt 18/28] lib/display: Add support for DRM planes
We can now extend our plane support beyond primary and cursor planes.
Signed-off-by: Damien Lespiau
---
lib/igt_kms.c | 116 +-
lib/igt_kms.h | 6 +++
2 files changed, 120 insertions(+), 2 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 1933fa6..23a7318 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -862,6 +862,7 @@ static void igt_output_refresh(igt_output_t *output)
void igt_display_init(igt_display_t *display, int drm_fd)
{
drmModeRes *resources;
+ drmModePlaneRes *plane_resources;
bool verbose;
char *env;
int i;
@@ -892,10 +893,13 @@ void igt_display_init(igt_display_t *display, int drm_fd)
*/
display->n_pipes = resources->count_crtcs;
+ plane_resources = drmModeGetPlaneResources(display->drm_fd);
+ igt_assert(plane_resources);
+
for (i = 0; i < display->n_pipes; i++) {
igt_pipe_t *pipe = &display->pipes[i];
igt_plane_t *plane;
- int p;
+ int p, j;
pipe->display = display;
pipe->pipe = i;
@@ -907,6 +911,26 @@ void igt_display_init(igt_display_t *display, int drm_fd)
plane->index = p;
plane->is_primary = true;
+ /* add the planes that can be used with that pipe */
+ for (j = 0; j < plane_resources->count_planes; j++) {
+ drmModePlane *drm_plane;
+
+ drm_plane = drmModeGetPlane(display->drm_fd,
+ plane_resources->planes[j]);
+ igt_assert(drm_plane);
+
+ if (!(drm_plane->possible_crtcs & (1 << i))) {
+ drmModeFreePlane(drm_plane);
+ continue;
+ }
+
+ p++;
+ plane = &pipe->planes[p];
+ plane->pipe = pipe;
+ plane->index = p;
+ plane->drm_plane = drm_plane;
+ }
+
/* cursor plane */
p++;
plane = &pipe->planes[p];
@@ -943,6 +967,7 @@ void igt_display_init(igt_display_t *display, int drm_fd)
igt_output_refresh(output);
}
+ drmModeFreePlaneResources(plane_resources);
drmModeFreeResources(resources);
LOG_UNINDENT(display);
@@ -958,6 +983,20 @@ int igt_display_get_n_pipes(igt_display_t *display)
return display->n_pipes;
}
+static void igt_pipe_fini(igt_pipe_t *pipe)
+{
+ int i;
+
+ for (i = 0; i < pipe->n_planes; i++) {
+ igt_plane_t *plane = &pipe->planes[i];
+
+ if (plane->drm_plane) {
+ drmModeFreePlane(plane->drm_plane);
+ plane->drm_plane = NULL;
+ }
+ }
+}
+
static void igt_output_fini(igt_output_t *output)
{
if (output->valid)
@@ -969,6 +1008,9 @@ void igt_display_fini(igt_display_t *display)
{
int i;
+ for (i = 0; i < display->n_pipes; i++)
+ igt_pipe_fini(&display->pipes[i]);
+
for (i = 0; i < display->n_outputs; i++)
igt_output_fini(&display->outputs[i]);
free(display->outputs);
@@ -1110,10 +1152,76 @@ static int igt_cursor_commit(igt_plane_t *plane,
igt_output_t *output)
return 0;
}
+static int igt_drm_plane_commit(igt_plane_t *plane, igt_output_t *output)
+{
+ igt_display_t *display = output->display;
+ uint32_t fb_id, crtc_id;
+ int ret;
+
+ fb_id = igt_plane_get_fd_id(plane);
+ crtc_id = output->config.crtc->crtc_id;
+
+ if (plane->fb_changed && fb_id == 0) {
+ LOG(display,
+ "%s: SetPlane pipe %c, plane %d, disabling\n",
+ igt_output_name(output),
+ pipe_name(output->config.pipe),
+ plane->index);
+
+ ret = drmModeSetPlane(display->drm_fd,
+ plane->drm_plane->plane_id,
+ crtc_id,
+ fb_id,
+ 0,/* flags */
+ 0, 0, /* crtc_x, crtc_y */
+ 0, 0, /* crtc_w, crtc_h */
+ IGT_FIXED(0,0), /* src_x */
+ IGT_FIXED(0,0), /* src_y */
+ IGT_FIXED(0,0), /* src_w */
+ IGT_FIXED(0,0) /* src_h */);
+
+ igt_assert(ret == 0);
+
+ plane->fb_changed = false;
+ } else if (plane->fb_changed || plane->position_changed) {
+ LOG(display,
+ "%s: SetPlane %c.%d, fb %u, position (%d, %d)\n",
+ igt_output_name(output),
[Intel-gfx] [PATCH igt 20/28] kms_cursor_crc: Use kmstest_create_color_fb()
Signed-off-by: Damien Lespiau
---
tests/kms_cursor_crc.c | 25 +
1 file changed, 5 insertions(+), 20 deletions(-)
diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c
index a386ad9..6cdb785 100644
--- a/tests/kms_cursor_crc.c
+++ b/tests/kms_cursor_crc.c
@@ -61,25 +61,6 @@ typedef struct {
} test_data_t;
-static void create_fb_for_mode(data_t *data, drmModeModeInfo *mode)
-{
- unsigned int fb_id;
- cairo_t *cr;
-
- fb_id = kmstest_create_fb2(data->drm_fd,
- mode->hdisplay, mode->vdisplay,
- DRM_FORMAT_XRGB,
- false, &data->primary_fb);
- igt_assert(fb_id);
-
- /* black */
- cr = kmstest_get_cairo_ctx(data->drm_fd, &data->primary_fb);
- kmstest_paint_color(cr, 0, 0, mode->hdisplay, mode->vdisplay,
- 0.0, 0.0, 0.0);
- igt_assert(cairo_status(cr) == 0);
- cairo_destroy(cr);
-}
-
static igt_pipe_crc_t *create_crc(data_t *data, enum pipe pipe)
{
igt_pipe_crc_t *crc;
@@ -214,7 +195,11 @@ static bool prepare_crtc(test_data_t *test_data,
igt_output_t *output)
/* create and set the primary plane fb */
mode = igt_output_get_mode(output);
- create_fb_for_mode(data, mode);
+ kmstest_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB,
+ false, /* tiled */
+ 0.0, 0.0, 0.0,
+ &data->primary_fb);
primary = igt_ouput_get_plane(output, IGT_PLANE_PRIMARY);
igt_plane_set_fb(primary, &data->primary_fb);
--
1.8.3.1
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[Intel-gfx] [PATCH igt 14/28] lib/display: Check if we're trying to use the same pipe on 2 outputs
Signed-off-by: Damien Lespiau
---
lib/igt_kms.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index c503ebb..1933fa6 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -977,10 +977,34 @@ void igt_display_fini(igt_display_t *display)
static void igt_display_refresh(igt_display_t *display)
{
- int i;
+ int i, j;
display->pipes_in_use = 0;
+ /* Check that two outputs aren't trying to use the same pipe */
+for (i = 0; i < display->n_outputs; i++) {
+igt_output_t *a = &display->outputs[i];
+
+if (a->pending_crtc_idx_mask == -1UL)
+continue;
+
+for (j = 0; j < display->n_outputs; j++) {
+igt_output_t *b = &display->outputs[j];
+
+if (i == j)
+continue;
+
+if (b->pending_crtc_idx_mask == -1UL)
+continue;
+
+igt_assert_f(a->pending_crtc_idx_mask !=
+ b->pending_crtc_idx_mask,
+ "%s and %s are both trying to use pipe
%c\n",
+ igt_output_name(a), igt_output_name(b),
+ pipe_name(ffs(a->pending_crtc_idx_mask) -
1));
+}
+}
+
/*
* The pipe allocation has to be done in two phases:
* - first, try to satisfy the outputs where a pipe has been specified
--
1.8.3.1
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[Intel-gfx] [PATCH igt 03/28] lib: Introduce symbolic names for display planes
It'd be nice to have symbolic names for planes instead of using an index
in igt_output_get_plane().
We also namespace the enum to not conflict with anyone.
Signed-off-by: Damien Lespiau
---
lib/igt_display.h | 18 +-
lib/igt_kms.c | 18 --
lib/igt_kms.h | 2 +-
3 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/lib/igt_display.h b/lib/igt_display.h
index 84638b2..77a75a7 100644
--- a/lib/igt_display.h
+++ b/lib/igt_display.h
@@ -33,16 +33,16 @@ enum pipe {
};
#define pipe_name(p) ((p) + 'A')
-/* FIXME: i915_drm.h on Android pollutes the general namespace. */
-#undef PLANE_A
-#undef PLANE_B
-
-enum plane {
-PLANE_A = 0,
-PLANE_B,
-PLANE_C,
+/* We namespace this enum to not conflict with the Android i915_drm.h */
+enum igt_plane {
+IGT_PLANE_1 = 0,
+IGT_PLANE_PRIMARY = IGT_PLANE_1,
+IGT_PLANE_2,
+IGT_PLANE_3,
+IGT_PLANE_CURSOR,
};
-#define plane_name(p) ((p) + 'A')
+
+const char *plane_name(enum igt_plane p);
#define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index dfa6b41..e3e902a 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -764,6 +764,20 @@ void kmstest_free_connector_config(struct
kmstest_connector_config *config)
drmModeFreeConnector(config->connector);
}
+const char *plane_name(enum igt_plane p)
+{
+ static const char *names[] = {
+ [IGT_PLANE_1] = "plane1",
+ [IGT_PLANE_2] = "plane2",
+ [IGT_PLANE_3] = "plane3",
+ [IGT_PLANE_CURSOR] = "cursor",
+ };
+
+ igt_assert(p < ARRAY_SIZE(names) && names[p]);
+
+ return names[p];
+}
+
/*
* A small modeset API
*/
@@ -1106,12 +1120,12 @@ static igt_plane_t *igt_pipe_get_plane(igt_pipe_t
*pipe, int index)
return &pipe->planes[index];
}
-igt_plane_t *igt_ouput_get_plane(igt_output_t *output, int index)
+igt_plane_t *igt_ouput_get_plane(igt_output_t *output, enum igt_plane plane)
{
igt_pipe_t *pipe;
pipe = igt_output_get_driving_pipe(output);
- return igt_pipe_get_plane(pipe, 0);
+ return igt_pipe_get_plane(pipe, plane);
}
void igt_plane_set_fb(igt_plane_t *plane, struct kmstest_fb *fb)
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 901fc1a..80cdfb6 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -154,7 +154,7 @@ void igt_display_set_verbose(igt_display_t *display, bool
verbose);
const char *igt_output_name(igt_output_t *output);
drmModeModeInfo *igt_output_get_mode(igt_output_t *output);
void igt_output_set_pipe(igt_output_t *output, enum pipe pipe);
-igt_plane_t *igt_ouput_get_plane(igt_output_t *output, int index);
+igt_plane_t *igt_ouput_get_plane(igt_output_t *output, enum igt_plane plane);
void igt_plane_set_fb(igt_plane_t *plane, struct kmstest_fb *fb);
--
1.8.3.1
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[Intel-gfx] [PATCH igt 28/28] kms_plane: Start a basic display plane test
We test the sprite plane positionning in there, for now.
Signed-off-by: Damien Lespiau
---
tests/.gitignore | 1 +
tests/Makefile.sources | 1 +
tests/kms_plane.c | 247 +
3 files changed, 249 insertions(+)
create mode 100644 tests/kms_plane.c
diff --git a/tests/.gitignore b/tests/.gitignore
index bce8a42..6bb92e3 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -110,6 +110,7 @@ kms_cursor_crc
kms_fbc_crc
kms_flip
kms_pipe_crc_basic
+kms_plane
kms_render
kms_setmode
pm_lpsp
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index cb96b09..f9f6686 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -58,6 +58,7 @@ TESTS_progs_M = \
kms_fbc_crc \
kms_flip \
kms_pipe_crc_basic \
+ kms_plane \
kms_render \
kms_setmode \
pm_lpsp \
diff --git a/tests/kms_plane.c b/tests/kms_plane.c
new file mode 100644
index 000..94f5d2c
--- /dev/null
+++ b/tests/kms_plane.c
@@ -0,0 +1,247 @@
+/*
+ * Copyright ?? 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Damien Lespiau
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+
+#include "drmtest.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+
+typedef struct {
+ int drm_fd;
+ igt_debugfs_t debugfs;
+ igt_display_t display;
+} data_t;
+
+/*
+ * Plane position test.
+ * - We start by grabbing a reference CRC of a full green fb being scanned
+ * out on the primary plane
+ * - Then we scannout 2 planes:
+ * - the primary plane uses a green fb with a black rectangle
+ * - a plane, on top of the primary plane, with a green fb that is set-up
+ *to cover the black rectangle of the primary plane fb
+ * The resulting CRC should be identical to the reference CRC
+ */
+
+typedef struct {
+ data_t *data;
+ igt_pipe_crc_t *pipe_crc;
+ igt_crc_t reference_crc;
+} test_position_t;
+
+/*
+ * create a green fb with a black rectangle at (rect_x,rect_y) and of size
+ * (rect_w,rect_h)
+ */
+static void
+create_fb_for_mode__position(data_t *data, drmModeModeInfo *mode,
+double rect_x, double rect_y,
+double rect_w, double rect_h,
+struct kmstest_fb *fb /* out */)
+{
+ unsigned int fb_id;
+ cairo_t *cr;
+
+ fb_id = kmstest_create_fb(data->drm_fd,
+ mode->hdisplay, mode->vdisplay,
+ 32 /* bpp */, 24 /* depth */,
+ false /* tiling */,
+ fb);
+ igt_assert(fb_id);
+
+ cr = kmstest_get_cairo_ctx(data->drm_fd, fb);
+ kmstest_paint_color(cr, 0, 0, mode->hdisplay, mode->vdisplay,
+ 0.0, 1.0, 0.0);
+ kmstest_paint_color(cr, rect_x, rect_y, rect_w, rect_h, 0.0, 0.0, 0.0);
+ igt_assert(cairo_status(cr) == 0);
+ cairo_destroy(cr);
+}
+
+static void
+test_position_init(test_position_t *test, igt_output_t *output, enum pipe pipe)
+{
+ data_t *data = test->data;
+ struct kmstest_fb green_fb;
+ drmModeModeInfo *mode;
+ igt_plane_t *primary;
+
+ test->pipe_crc = igt_pipe_crc_new(&data->debugfs, data->drm_fd,
+ pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
+
+ igt_output_set_pipe(output, pipe);
+ primary = igt_ouput_get_plane(output, 0);
+
+ mode = igt_output_get_mode(output);
+ kmstest_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB,
+ false, /* tiled */
+ 0.0, 1.0, 0.0,
+ &green_fb);
+ igt_plane_set_fb(primary, &green_fb);
+
+ igt_dis
[Intel-gfx] [PATCH igt 02/28] kms_pipe_crc_basic: Port to the new modeset API
Signed-off-by: Damien Lespiau
---
tests/kms_pipe_crc_basic.c | 126 +++--
1 file changed, 29 insertions(+), 97 deletions(-)
diff --git a/tests/kms_pipe_crc_basic.c b/tests/kms_pipe_crc_basic.c
index f4a97eb..fdec077 100644
--- a/tests/kms_pipe_crc_basic.c
+++ b/tests/kms_pipe_crc_basic.c
@@ -34,17 +34,10 @@
#include "igt_kms.h"
typedef struct {
- struct kmstest_connector_config config;
- struct kmstest_fb fb;
- bool valid;
-} connector_t;
-
-typedef struct {
int drm_fd;
igt_debugfs_t debugfs;
- drmModeRes *resources;
- int n_connectors;
- connector_t *connectors;
+ igt_display_t display;
+ struct kmstest_fb fb;
} data_t;
static void test_bad_command(data_t *data, const char *cmd)
@@ -62,120 +55,58 @@ static void test_bad_command(data_t *data, const char *cmd)
fclose(ctl);
}
-static void connector_init(data_t *data, connector_t *connector,
- uint32_t id, uint32_t crtc_id_mask)
-{
- int ret;
-
- ret = kmstest_get_connector_config(data->drm_fd, id, crtc_id_mask,
- &connector->config);
- if (ret == 0)
- connector->valid = true;
- else
- connector->valid = false;
-
-}
-
-static void connector_fini(connector_t *connector)
+static void create_fb_for_mode(data_t *data, drmModeModeInfo *mode)
{
- kmstest_free_connector_config(&connector->config);
-}
-
-static bool
-connector_set_mode(data_t *data, connector_t *connector, drmModeModeInfo *mode)
-{
- struct kmstest_connector_config *config = &connector->config;
unsigned int fb_id;
cairo_t *cr;
- int ret;
fb_id = kmstest_create_fb(data->drm_fd,
mode->hdisplay, mode->vdisplay,
32 /* bpp */, 24 /* depth */,
false /* tiling */,
- &connector->fb);
+ &data->fb);
igt_assert(fb_id);
- cr = kmstest_get_cairo_ctx(data->drm_fd, &connector->fb);
+ cr = kmstest_get_cairo_ctx(data->drm_fd, &data->fb);
kmstest_paint_color(cr, 0, 0, mode->hdisplay, mode->vdisplay,
0.0, 1.0, 0.0);
igt_assert(cairo_status(cr) == 0);
cairo_destroy(cr);
-
-#if 0
- fprintf(stdout, "Using pipe %c, %dx%d\n", pipe_name(config->pipe),
- mode->hdisplay, mode->vdisplay);
-#endif
-
- ret = drmModeSetCrtc(data->drm_fd,
-config->crtc->crtc_id,
-connector->fb.fb_id,
-0, 0, /* x, y */
-&config->connector->connector_id,
-1,
-mode);
- igt_assert(ret == 0);
-
- return 0;
-}
-
-static void display_init(data_t *data)
-{
- data->resources = drmModeGetResources(data->drm_fd);
- igt_assert(data->resources);
-
- data->n_connectors = data->resources->count_connectors;
- data->connectors = calloc(data->n_connectors, sizeof(connector_t));
- igt_assert(data->connectors);
-}
-
-static void connectors_init(data_t *data, uint32_t crtc_id_mask)
-{
- int i;
-
- for (i = 0; i < data->n_connectors; i++) {
- uint32_t id = data->resources->connectors[i];
-
- connector_init(data, &data->connectors[i], id, crtc_id_mask);
- }
-}
-
-static void display_fini(data_t *data)
-{
- int i;
-
- for (i = 0; i < data->n_connectors; i++)
- connector_fini(&data->connectors[i]);
- free(data->connectors);
-
- drmModeFreeResources(data->resources);
}
#define TEST_SEQUENCE (1<<0)
static void test_read_crc(data_t *data, int pipe, unsigned flags)
{
- connector_t *connector;
+ igt_display_t *display = &data->display;
igt_pipe_crc_t *pipe_crc;
igt_crc_t *crcs = NULL;
int valid_connectors = 0, i;
- connectors_init(data, 1 << pipe);
+ for (i = 0; i < display->n_outputs; i++) {
+ igt_output_t *output = &display->outputs[i];
+ igt_plane_t *primary;
+ drmModeModeInfo *mode;
- for (i = 0; i < data->n_connectors; i++) {
- connector = &data->connectors[i];
-
- if (!connector->valid)
+ if (!output->valid)
continue;
- fprintf(stdout, "%s: Testing connector %u\n",
- igt_subtest_name(),
connector->config.connector->connector_id);
+ igt_output_set_pipe(output, pipe);
+
+ fprintf(stdout, "%s: Testing connector %s using pipe %c\n",
+ igt_subtest_name(), igt_output_name(output),
+ pipe_name(pipe));
- connector_set_mode(data, connector,
&connecto
[Intel-gfx] [PATCH igt 13/28] lib/display: Allow to override the display verbosity with an env variale
Signed-off-by: Damien Lespiau
---
lib/igt_kms.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index e2413e5..c503ebb 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -863,6 +863,7 @@ void igt_display_init(igt_display_t *display, int drm_fd)
{
drmModeRes *resources;
bool verbose;
+ char *env;
int i;
/*
@@ -873,6 +874,11 @@ void igt_display_init(igt_display_t *display, int drm_fd)
memset(display, 0, sizeof(igt_display_t));
display->verbose = verbose;
+ /* allow a verbose override from an env variable */
+ env = getenv("IGT_DISPLAY_VERBOSE");
+ if (env)
+ display->verbose = atoi(env) != 0;
+
LOG_INDENT(display, "init");
display->drm_fd = drm_fd;
--
1.8.3.1
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[Intel-gfx] [PATCH igt 01/28] lib: Introduce a modeset API
The goals here are:
- Reduce duplicated code in each KMS test
- Provide an API that looks more like what we want for atomic
modesets. The hope is then that it'll be easy to switch, at
run-time, between the "legacy" path and atomic modesets, keeping
the same API for tests.
Signed-off-by: Damien Lespiau
---
lib/igt_kms.c | 364 ++
lib/igt_kms.h | 59 ++
2 files changed, 423 insertions(+)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 3960d24..dfa6b41 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -24,6 +24,7 @@
#define _GNU_SOURCE
#include
+#include
#include
#include
#include
@@ -763,3 +764,366 @@ void kmstest_free_connector_config(struct
kmstest_connector_config *config)
drmModeFreeConnector(config->connector);
}
+/*
+ * A small modeset API
+ */
+
+#define LOG_SPACES ""
+#define LOG_N_SPACES (sizeof(LOG_SPACES) - 1)
+
+#define LOG_INDENT(d, section) \
+ do {\
+ igt_display_log(d, "%s {\n", section); \
+ igt_display_log_shift(d, 1);\
+ } while (0)
+#define LOG_UNINDENT(d)\
+ do {\
+ igt_display_log_shift(d, -1); \
+ igt_display_log(d, "}\n"); \
+ } while (0)
+#define LOG(d, fmt, ...) igt_display_log(d, fmt, ## __VA_ARGS__)
+
+static int __attribute__((format(printf, 2, 3)))
+igt_display_log(igt_display_t *display, const char *fmt, ...)
+{
+ va_list args;
+ int n, i;
+
+ if (!display->verbose)
+ return 0;
+
+ va_start(args, fmt);
+ n = printf("display: ");
+ for (i = 0; i < display->log_shift; i++)
+ n += printf("%s", LOG_SPACES);
+ n += vprintf(fmt, args);
+ va_end(args);
+
+ return n;
+}
+
+static void igt_display_log_shift(igt_display_t *display, int shift)
+{
+ display->log_shift += shift;
+ igt_assert(display->log_shift >= 0);
+}
+
+static void igt_output_refresh(igt_output_t *output)
+{
+ igt_display_t *display = output->display;
+ int ret;
+ unsigned long crtc_idx_mask;
+
+ /* we mask out the pipes already in use */
+ crtc_idx_mask = output->pending_crtc_idx_mask & ~display->pipes_in_use;
+
+ if (output->valid)
+ kmstest_free_connector_config(&output->config);
+ ret = kmstest_get_connector_config(display->drm_fd,
+ output->id,
+ crtc_idx_mask,
+ &output->config);
+ if (ret == 0)
+ output->valid = true;
+ else
+ output->valid = false;
+
+ if (!output->valid)
+ return;
+
+ if (!output->name) {
+ drmModeConnector *c = output->config.connector;
+
+ asprintf(&output->name, "%s-%d",
+kmstest_connector_type_str(c->connector_type),
+c->connector_type_id);
+ }
+
+ LOG(display, "%s: Selecting pipe %c\n", output->name,
+ pipe_name(output->config.pipe));
+
+ display->pipes_in_use |= 1 << output->config.pipe;
+}
+
+void igt_display_init(igt_display_t *display, int drm_fd)
+{
+ drmModeRes *resources;
+ bool verbose;
+ int i;
+
+ /*
+* It's valid to set verbose before the init so we can get debugging
+* output for the init() itself.
+*/
+ verbose = display->verbose;
+ memset(display, 0, sizeof(igt_display_t));
+ display->verbose = verbose;
+
+ LOG_INDENT(display, "init");
+
+ display->drm_fd = drm_fd;
+
+ resources = drmModeGetResources(display->drm_fd);
+ igt_assert(resources);
+
+ /*
+* We cache the number of pipes, that number is a physical limit of the
+* hardware and cannot change of time (for now, at least).
+*/
+ display->n_pipes = resources->count_crtcs;
+
+ for (i = 0; i < display->n_pipes; i++) {
+ igt_pipe_t *pipe = &display->pipes[i];
+ igt_plane_t *plane;
+
+ pipe->display = display;
+ pipe->pipe = i;
+ pipe->n_planes = 1;
+
+ /* primary plane */
+ plane = &pipe->planes[0];
+ plane->pipe = pipe;
+ plane->index = 0;
+ plane->is_primary = true;
+ }
+
+ /*
+* The number of connectors is set, so we just initialize the outputs
+* array in _init(). This may change when we need dynamic connectors
+* (say DisplayPort MST).
+*/
+ display->n_outputs = resources->count_connectors;
+ display->outputs = calloc(display->n_outputs, sizeof(igt_output_t));
+
[Intel-gfx] [PATCH igt 06/28] lib/display: Add an accessor to retrieve the number of pipes
Signed-off-by: Damien Lespiau
---
lib/igt_kms.c | 5 +
lib/igt_kms.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index e3e902a..38ee82b 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -934,6 +934,11 @@ void igt_display_set_verbose(igt_display_t *display, bool
verbose)
display->verbose = verbose;
}
+int igt_display_get_n_pipes(igt_display_t *display)
+{
+ return display->n_pipes;
+}
+
static void igt_output_fini(igt_output_t *output)
{
if (output->valid)
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 1d06767..bb74fc4 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -150,6 +150,7 @@ void igt_display_init(igt_display_t *display, int drm_fd);
void igt_display_fini(igt_display_t *display);
int igt_display_commit(igt_display_t *display);
void igt_display_set_verbose(igt_display_t *display, bool verbose);
+int igt_display_get_n_pipes(igt_display_t *display);
const char *igt_output_name(igt_output_t *output);
drmModeModeInfo *igt_output_get_mode(igt_output_t *output);
--
1.8.3.1
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[Intel-gfx] [PATCH igt 19/28] lib: Introduce a new helper kmstest_create_color_fb()
We need to create fbs of a single color in a few places. Time to
abstract that out to a helper function.
Signed-off-by: Damien Lespiau
---
lib/igt_kms.c | 19 +++
lib/igt_kms.h | 4
2 files changed, 23 insertions(+)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 23a7318..74e52b6 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -358,6 +358,25 @@ unsigned int kmstest_create_fb2(int fd, int width, int
height, uint32_t format,
return fb_id;
}
+unsigned int kmstest_create_color_fb(int fd, int width, int height,
+uint32_t format, bool tiled,
+double r, double g, double b,
+struct kmstest_fb *fb /* out */)
+{
+ unsigned int fb_id;
+ cairo_t *cr;
+
+ fb_id = kmstest_create_fb2(fd, width, height, format, tiled, fb);
+ igt_assert(fb_id);
+
+ cr = kmstest_get_cairo_ctx(fd, fb);
+ kmstest_paint_color(cr, 0, 0, width, height, r, g, b);
+ igt_assert(cairo_status(cr) == 0);
+ cairo_destroy(cr);
+
+ return fb_id;
+}
+
static cairo_format_t drm_format_to_cairo(uint32_t drm_format)
{
struct format_desc_struct *f;
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index a37f6b9..8110dad 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -79,6 +79,10 @@ unsigned int kmstest_create_fb(int fd, int width, int
height, int bpp,
struct kmstest_fb *fb_info);
unsigned int kmstest_create_fb2(int fd, int width, int height, uint32_t format,
bool tiled, struct kmstest_fb *fb);
+unsigned int kmstest_create_color_fb(int fd, int width, int height,
+uint32_t format, bool tiled,
+double r, double g, double b,
+struct kmstest_fb *fb /* out */);
void kmstest_remove_fb(int fd, struct kmstest_fb *fb_info);
cairo_t *kmstest_get_cairo_ctx(int fd, struct kmstest_fb *fb);
cairo_surface_t *kmstest_get_cairo_surface(int fd, struct kmstest_fb *fb);
--
1.8.3.1
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[Intel-gfx] [PATCH igt 11/28] lib/display: Add a way to specify we don't care about the pipe to use
Signed-off-by: Damien Lespiau
---
lib/igt_kms.c | 12
lib/igt_kms.h | 6 ++
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 3b75478..e2413e5 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1226,10 +1226,14 @@ void igt_output_set_pipe(igt_output_t *output, enum
pipe pipe)
{
igt_display_t *display = output->display;
- LOG(display, "%s: set_pipe(%c)\n", igt_output_name(output),
- pipe_name(pipe));
-
- output->pending_crtc_idx_mask = 1 << pipe;
+ if (pipe == PIPE_ANY) {
+ LOG(display, "%s: set_pipe(any)\n", igt_output_name(output));
+ output->pending_crtc_idx_mask = -1UL;
+ } else {
+ LOG(display, "%s: set_pipe(%c)\n", igt_output_name(output),
+ pipe_name(pipe));
+ output->pending_crtc_idx_mask = 1 << pipe;
+ }
}
igt_plane_t *igt_ouput_get_plane(igt_output_t *output, enum igt_plane plane)
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index e86cff4..07cf8a2 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -170,6 +170,12 @@ void igt_plane_set_position(igt_plane_t *plane, int x, int
y);
for (int i__ = 0; i__ < (display)->n_outputs; i__++) \
if ((output = &(display)->outputs[i__]), output->valid)
+/*
+ * Can be used with igt_output_set_pipe() to mean we don't care about the pipe
+ * that should drive this output
+ */
+#define PIPE_ANY (-1)
+
#define IGT_FIXED(i,f) ((i) << 16 | (f))
#endif /* __IGT_KMS_H__ */
--
1.8.3.1
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[Intel-gfx] [PATCH igt 09/28] lib/display: Fix the SetCrtc disabling log message
We were displaying the value of fb_id (0), when the actual interesting
thing about this call it that it'll just down the pipe.
Signed-off-by: Damien Lespiau
---
lib/igt_kms.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 38ee82b..64fb39a 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1055,10 +1055,9 @@ static int igt_output_commit(igt_output_t *output)
mode);
} else {
LOG(display,
- "%s: SetCrtc pipe %c, fb %u\n",
+ "%s: SetCrtc pipe %c, disabling\n",
igt_output_name(output),
- pipe_name(output->config.pipe),
- fb_id);
+ pipe_name(output->config.pipe));
ret = drmModeSetCrtc(display->drm_fd,
crtc_id,
--
1.8.3.1
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[Intel-gfx] [PATCH igt 25/28] lib/display: Print the fb id, not its pointer in the set_fb() log message
Signed-off-by: Damien Lespiau --- lib/igt_kms.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/igt_kms.c b/lib/igt_kms.c index fbbf6aa..7d74bf8 100644 --- a/lib/igt_kms.c +++ b/lib/igt_kms.c @@ -1411,8 +1411,8 @@ void igt_plane_set_fb(igt_plane_t *plane, struct kmstest_fb *fb) igt_pipe_t *pipe = plane->pipe; igt_display_t *display = pipe->display; - LOG(display, "%c.%d: plane_set_fb(%p)\n", pipe_name(pipe->pipe), - plane->index, fb); + LOG(display, "%c.%d: plane_set_fb(%d)\n", pipe_name(pipe->pipe), + plane->index, fb ? fb->fb_id : 0); plane->fb = fb; -- 1.8.3.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 17/28] tests/kms_cursor_crc: Use igt_pipe_crc_collect_crc()
Signed-off-by: Damien Lespiau
---
tests/kms_cursor_crc.c | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c
index 76e2845..a386ad9 100644
--- a/tests/kms_cursor_crc.c
+++ b/tests/kms_cursor_crc.c
@@ -94,7 +94,7 @@ static void do_single_test(test_data_t *test_data, int x, int
y)
data_t *data = test_data->data;
igt_display_t *display = &data->display;
igt_pipe_crc_t *pipe_crc = data->pipe_crc[test_data->pipe];
- igt_crc_t *crcs = NULL;
+ igt_crc_t crc;
igt_plane_t *cursor;
printf("."); fflush(stdout);
@@ -104,14 +104,11 @@ static void do_single_test(test_data_t *test_data, int x,
int y)
igt_display_commit(display);
igt_wait_for_vblank(data->drm_fd, test_data->pipe);
- igt_pipe_crc_start(pipe_crc);
- igt_pipe_crc_get_crcs(pipe_crc, 1, &crcs);
- igt_pipe_crc_stop(pipe_crc);
+ igt_pipe_crc_collect_crc(pipe_crc, &crc);
if (test_data->crc_must_match)
- igt_assert(igt_crc_equal(&crcs[0], &test_data->ref_crc));
+ igt_assert(igt_crc_equal(&crc, &test_data->ref_crc));
else
- igt_assert(!igt_crc_equal(&crcs[0], &test_data->ref_crc));
- free(crcs);
+ igt_assert(!igt_crc_equal(&crc, &test_data->ref_crc));
}
static void do_test(test_data_t *test_data,
@@ -207,7 +204,6 @@ static void test_crc(test_data_t *test_data, enum
cursor_type cursor_type,
static bool prepare_crtc(test_data_t *test_data, igt_output_t *output)
{
drmModeModeInfo *mode;
- igt_crc_t *crcs = NULL;
data_t *data = test_data->data;
igt_display_t *display = &data->display;
igt_pipe_crc_t *pipe_crc;
@@ -249,11 +245,7 @@ static bool prepare_crtc(test_data_t *test_data,
igt_output_t *output)
igt_wait_for_vblank(data->drm_fd, test_data->pipe);
/* get reference crc w/o cursor */
- igt_pipe_crc_start(pipe_crc);
- igt_pipe_crc_get_crcs(pipe_crc, 1, &crcs);
- test_data->ref_crc = crcs[0];
- igt_pipe_crc_stop(pipe_crc);
- free(crcs);
+ igt_pipe_crc_collect_crc(pipe_crc, &test_data->ref_crc);
return true;
}
--
1.8.3.1
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[Intel-gfx] [PATCH igt 26/28] lib/display: Wait for a vblank after SetPlane()
Let's be testing friendly and gently wait for the next vblank before
returning from commit() when needed.
After igt_display_commit() one can safely look at the CRC.
Signed-off-by: Damien Lespiau
---
lib/igt_kms.c | 8
lib/igt_kms.h | 5 +++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 7d74bf8..862d8ba 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1174,11 +1174,13 @@ static int igt_cursor_commit(igt_plane_t *plane,
igt_output_t *output)
static int igt_drm_plane_commit(igt_plane_t *plane, igt_output_t *output)
{
igt_display_t *display = output->display;
+ igt_pipe_t *pipe;
uint32_t fb_id, crtc_id;
int ret;
fb_id = igt_plane_get_fd_id(plane);
crtc_id = output->config.crtc->crtc_id;
+ pipe = igt_output_get_driving_pipe(output);
if (plane->fb_changed && fb_id == 0) {
LOG(display,
@@ -1227,6 +1229,7 @@ static int igt_drm_plane_commit(igt_plane_t *plane,
igt_output_t *output)
plane->fb_changed = false;
plane->position_changed = false;
+ pipe->need_wait_for_vblank = true;
}
return 0;
@@ -1346,6 +1349,11 @@ static int igt_output_commit(igt_output_t *output)
igt_plane_commit(plane, output);
}
+ if (pipe->need_wait_for_vblank) {
+ igt_wait_for_vblank(display->drm_fd, pipe->pipe);
+ pipe->need_wait_for_vblank = false;
+ }
+
return 0;
}
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 96dd9e4..8c1c0a7 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -136,8 +136,9 @@ typedef struct {
struct igt_pipe {
igt_display_t *display;
enum pipe pipe;
- unsigned int need_set_crtc : 1;
- unsigned int need_set_cursor : 1;
+ unsigned int need_set_crtc: 1;
+ unsigned int need_set_cursor : 1;
+ unsigned int need_wait_for_vblank : 1;
#define IGT_MAX_PLANES 4
int n_planes;
igt_plane_t planes[IGT_MAX_PLANES];
--
1.8.3.1
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[Intel-gfx] [PATCH igt 22/28] kms_pipe_crc_basic: Use kmstest_create_color_fb()
Reducing again the per-test number of lines.
Signed-off-by: Damien Lespiau
---
tests/kms_pipe_crc_basic.c | 26 ++
1 file changed, 6 insertions(+), 20 deletions(-)
diff --git a/tests/kms_pipe_crc_basic.c b/tests/kms_pipe_crc_basic.c
index f4de64f..8a45c5b 100644
--- a/tests/kms_pipe_crc_basic.c
+++ b/tests/kms_pipe_crc_basic.c
@@ -55,25 +55,6 @@ static void test_bad_command(data_t *data, const char *cmd)
fclose(ctl);
}
-static void create_fb_for_mode(data_t *data, drmModeModeInfo *mode)
-{
- unsigned int fb_id;
- cairo_t *cr;
-
- fb_id = kmstest_create_fb(data->drm_fd,
- mode->hdisplay, mode->vdisplay,
- 32 /* bpp */, 24 /* depth */,
- false /* tiling */,
- &data->fb);
- igt_assert(fb_id);
-
- cr = kmstest_get_cairo_ctx(data->drm_fd, &data->fb);
- kmstest_paint_color(cr, 0, 0, mode->hdisplay, mode->vdisplay,
- 0.0, 1.0, 0.0);
- igt_assert(cairo_status(cr) == 0);
- cairo_destroy(cr);
-}
-
#define TEST_SEQUENCE (1<<0)
static void test_read_crc(data_t *data, int pipe, unsigned flags)
@@ -95,7 +76,12 @@ static void test_read_crc(data_t *data, int pipe, unsigned
flags)
pipe_name(pipe));
mode = igt_output_get_mode(output);
- create_fb_for_mode(data, mode);
+ kmstest_create_color_fb(data->drm_fd,
+ mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB,
+ false, /* tiled */
+ 0.0, 1.0, 0.0,
+ &data->fb);
primary = igt_ouput_get_plane(output, 0);
igt_plane_set_fb(primary, &data->fb);
--
1.8.3.1
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[Intel-gfx] [PATCH igt 07/28] kms_pipe_crc_basic: Use igt_display_get_n_pipes() instead of hardcoding 3
Signed-off-by: Damien Lespiau
---
tests/kms_pipe_crc_basic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/kms_pipe_crc_basic.c b/tests/kms_pipe_crc_basic.c
index 7d48ca6..f4de64f 100644
--- a/tests/kms_pipe_crc_basic.c
+++ b/tests/kms_pipe_crc_basic.c
@@ -169,7 +169,7 @@ igt_main
igt_subtest("bad-nb-words-3")
test_bad_command(&data, "pipe A none option");
- for (int i = 0; i < 3; i++) {
+ for (int i = 0; i < igt_display_get_n_pipes(&data.display); i++) {
igt_subtest_f("read-crc-pipe-%c", 'A'+i)
test_read_crc(&data, i, 0);
--
1.8.3.1
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[Intel-gfx] [PATCH igt 23/28] lib: Add a helper to wait for a keypress
Signed-off-by: Damien Lespiau
---
lib/drmtest.c | 13 +
lib/drmtest.h | 2 ++
2 files changed, 15 insertions(+)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index f7262d7..f0635d3 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -46,6 +46,7 @@
#include
#include
#include
+#include
#include "drmtest.h"
#include "i915_drm.h"
@@ -1687,3 +1688,15 @@ void igt_drop_root(void)
igt_assert(getgid() == 2);
igt_assert(getuid() == 2);
}
+
+void igt_wait_for_keypress(void)
+{
+ struct termios oldt, newt;
+
+ tcgetattr ( STDIN_FILENO, &oldt );
+ newt = oldt;
+ newt.c_lflag &= ~( ICANON | ECHO );
+ tcsetattr ( STDIN_FILENO, TCSANOW, &newt );
+ getchar();
+ tcsetattr ( STDIN_FILENO, TCSANOW, &oldt );
+}
diff --git a/lib/drmtest.h b/lib/drmtest.h
index d42a6f7..af68ee8 100644
--- a/lib/drmtest.h
+++ b/lib/drmtest.h
@@ -361,4 +361,6 @@ void igt_system_suspend_autoresume(void);
/* dropping priviledges */
void igt_drop_root(void);
+void igt_wait_for_keypress(void);
+
#endif /* DRMTEST_H */
--
1.8.3.1
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Re: [Intel-gfx] intel_sdvo_init: trying to register non-static key
On Fri, Feb 07, 2014 at 12:28:09PM +0100, Borislav Petkov wrote: > On Fri, Feb 07, 2014 at 01:12:22PM +0200, Imre Deak wrote: > > On Fri, 2014-02-07 at 13:04 +0200, Jani Nikula wrote: > > > Imre, is this the same i2c_del_adapter issue you're looking at? Any > > > patches to try yet? > > > > It looks like the same issue yes. The following patch fixed it for me: > > > > http://patchwork.freedesktop.org/patch/18698/ > > > > I'm working on an improved version of this, but the main thing - to > > remove the connector's sysfs entries before actually destroying the > > encoder and connector objects - will remain the same as in the above > > patch. > > You could shoot the final version my way so that I give it a run too. The final version will only change the code layout a bit, but not the logic. So a tested-by from you for v1 would be helpful anyway, to make really sure you've reported the same issue. If that's not the case then we need to dig deeper, so better not to waste a few days waiting for v2. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
