[PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions

[Mary Bennett]

Thank you for reviewing this patch.

v1->v2:
  * Add XCValu RTL.
  * Change assembly mnemonics from mixed case to lower case.

v2->v3:
  * Change commit message from past tense to present.
  * Add documentation for new dg-effective-targets.

This patch series presents the comprehensive implementation of the MAC and ALU
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
Mary Bennett 
Nandni Jamnadas 
Pietra Ferreira 
Charlie Keaney
Jessica Mills
Craig Blackmore 
Simon Cook 
Jeremy Bennett 
Helene Chelin 

  RISC-V: Add support for XCValu extension in CV32E40P
  RISC-V: Add support for XCVmac extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |   6 +
 gcc/config/riscv/constraints.md   |   7 +
 gcc/config/riscv/corev.def|  43 ++
 gcc/config/riscv/corev.md | 693 ++
 gcc/config/riscv/predicates.md|   5 +
 gcc/config/riscv/riscv-builtins.cc|  13 +
 gcc/config/riscv/riscv-ftypes.def |  11 +
 gcc/config/riscv/riscv-opts.h |   7 +
 gcc/config/riscv/riscv.cc |   7 +
 gcc/config/riscv/riscv.md |   1 +
 gcc/config/riscv/riscv.opt|   3 +
 gcc/doc/extend.texi   | 174 +
 gcc/doc/sourcebuild.texi  |  12 +
 .../gcc.target/riscv/cv-alu-compile.c | 252 +++
 .../riscv/cv-alu-fail-compile-addn.c  |  11 +
 .../riscv/cv-alu-fail-compile-addrn.c |  11 +
 .../riscv/cv-alu-fail-compile-addun.c |  11 +
 .../riscv/cv-alu-fail-compile-addurn.c|  11 +
 .../riscv/cv-alu-fail-compile-clip.c  |  11 +
 .../riscv/cv-alu-fail-compile-clipu.c |  11 +
 .../riscv/cv-alu-fail-compile-subn.c  |  11 +
 .../riscv/cv-alu-fail-compile-subrn.c |  11 +
 .../riscv/cv-alu-fail-compile-subun.c |  11 +
 .../riscv/cv-alu-fail-compile-suburn.c|  11 +
 .../gcc.target/riscv/cv-alu-fail-compile.c|  32 +
 .../gcc.target/riscv/cv-mac-compile.c | 198 +
 .../riscv/cv-mac-fail-compile-mac.c   |  25 +
 .../riscv/cv-mac-fail-compile-machhsn.c   |  24 +
 .../riscv/cv-mac-fail-compile-machhsrn.c  |  24 +
 .../riscv/cv-mac-fail-compile-machhun.c   |  24 +
 .../riscv/cv-mac-fail-compile-machhurn.c  |  24 +
 .../riscv/cv-mac-fail-compile-macsn.c |  24 +
 .../riscv/cv-mac-fail-compile-macsrn.c|  24 +
 .../riscv/cv-mac-fail-compile-macun.c |  24 +
 .../riscv/cv-mac-fail-compile-macurn.c|  24 +
 .../riscv/cv-mac-fail-compile-msu.c   |  25 +
 .../riscv/cv-mac-fail-compile-mulhhsn.c   |  24 +
 .../riscv/cv-mac-fail-compile-mulhhsrn.c  |  24 +
 .../riscv/cv-mac-fail-compile-mulhhun.c   |  24 +
 .../riscv/cv-mac-fail-compile-mulhhurn.c  |  24 +
 .../riscv/cv-mac-fail-compile-mulsn.c |  24 +
 .../riscv/cv-mac-fail-compile-mulsrn.c|  24 +
 .../riscv/cv-mac-fail-compile-mulun.c |  24 +
 .../riscv/cv-mac-fail-compile-mulurn.c|  24 +
 .../riscv/cv-mac-test-autogeneration.c|  18 +
 gcc/testsuite/lib/target-supports.exp |  26 +
 46 files changed, 2052 insertions(+)
 create mode 100644 gcc/config/riscv/corev.def
 create mode 100644 gcc/config/riscv/corev.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addurn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clip.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clipu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-suburn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mac.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compil

[PATCH v3 1/2] RISC-V: Add support for XCVmac extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add XCVmac.
* config/riscv/riscv-ftypes.def: Add XCVmac builtins.
* config/riscv/riscv-opts.h: Likewise.
* config/riscv/riscv.md: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Add XCVmac builtin documentation.
* doc/sourcebuild.texi: Likewise.
* config/riscv/corev.def: New file.
* config/riscv/corev.md: New file.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp: Add new effective target check.
* gcc.target/riscv/cv-mac-compile.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mac.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-machhsn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-machhsrn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-machhun.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-machhurn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-macsn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-macsrn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-macun.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-macurn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-msu.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulhhsn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulhhsrn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulhhun.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulhhurn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulsn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulsrn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulun.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulurn.c: New test.
* gcc.target/riscv/cv-mac-test-autogeneration.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc   |   4 +
 gcc/config/riscv/corev.def|  19 +
 gcc/config/riscv/corev.md | 390 ++
 gcc/config/riscv/riscv-builtins.cc|  10 +
 gcc/config/riscv/riscv-ftypes.def |   5 +
 gcc/config/riscv/riscv-opts.h |   5 +
 gcc/config/riscv/riscv.md |   1 +
 gcc/config/riscv/riscv.opt|   3 +
 gcc/doc/extend.texi   |  80 
 gcc/doc/sourcebuild.texi  |   9 +
 .../gcc.target/riscv/cv-mac-compile.c | 198 +
 .../riscv/cv-mac-fail-compile-mac.c   |  25 ++
 .../riscv/cv-mac-fail-compile-machhsn.c   |  24 ++
 .../riscv/cv-mac-fail-compile-machhsrn.c  |  24 ++
 .../riscv/cv-mac-fail-compile-machhun.c   |  24 ++
 .../riscv/cv-mac-fail-compile-machhurn.c  |  24 ++
 .../riscv/cv-mac-fail-compile-macsn.c |  24 ++
 .../riscv/cv-mac-fail-compile-macsrn.c|  24 ++
 .../riscv/cv-mac-fail-compile-macun.c |  24 ++
 .../riscv/cv-mac-fail-compile-macurn.c|  24 ++
 .../riscv/cv-mac-fail-compile-msu.c   |  25 ++
 .../riscv/cv-mac-fail-compile-mulhhsn.c   |  24 ++
 .../riscv/cv-mac-fail-compile-mulhhsrn.c  |  24 ++
 .../riscv/cv-mac-fail-compile-mulhhun.c   |  24 ++
 .../riscv/cv-mac-fail-compile-mulhhurn.c  |  24 ++
 .../riscv/cv-mac-fail-compile-mulsn.c |  24 ++
 .../riscv/cv-mac-fail-compile-mulsrn.c|  24 ++
 .../riscv/cv-mac-fail-compile-mulun.c |  24 ++
 .../riscv/cv-mac-fail-compile-mulurn.c|  24 ++
 .../riscv/cv-mac-test-autogeneration.c|  18 +
 gcc/testsuite/lib/target-supports.exp |  13 +
 31 files changed, 1189 insertions(+)
 create mode 100644 gcc/config/riscv/corev.def
 create mode 100644 gcc/config/riscv/corev.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mac.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsn.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhun.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhurn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macurn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-msu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhsn.c
 create mode

[PATCH v3 2/2] RISC-V: Add support for XCValu extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add the XCValu
extension.
* config/riscv/constraints.md: Add builtins for the XCValu
extension.
* config/riscv/predicates.md (immediate_register_operand):
Likewise.
* config/riscv/corev.def: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
  (RISCV_ATYPE_UHI): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv-opts.h: Likewise.
* config/riscv/riscv.opt: Likewise.
* config/riscv/riscv.cc (riscv_print_operand): Likewise.
* doc/extend.texi: Add XCValu documentation.
* doc/sourcebuild.texi: Likewise.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp: Add proc for the XCValu extension.
* gcc.target/riscv/cv-alu-compile.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-addn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-addrn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-addun.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-addurn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-clip.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-clipu.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-subn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-subrn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-subun.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-suburn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |   7 +
 gcc/config/riscv/corev.def|  24 ++
 gcc/config/riscv/corev.md | 303 ++
 gcc/config/riscv/predicates.md|   5 +
 gcc/config/riscv/riscv-builtins.cc|   3 +
 gcc/config/riscv/riscv-ftypes.def |   6 +
 gcc/config/riscv/riscv-opts.h |   2 +
 gcc/config/riscv/riscv.cc |   7 +
 gcc/doc/extend.texi   |  94 ++
 gcc/doc/sourcebuild.texi  |   3 +
 .../gcc.target/riscv/cv-alu-compile.c | 252 +++
 .../riscv/cv-alu-fail-compile-addn.c  |  11 +
 .../riscv/cv-alu-fail-compile-addrn.c |  11 +
 .../riscv/cv-alu-fail-compile-addun.c |  11 +
 .../riscv/cv-alu-fail-compile-addurn.c|  11 +
 .../riscv/cv-alu-fail-compile-clip.c  |  11 +
 .../riscv/cv-alu-fail-compile-clipu.c |  11 +
 .../riscv/cv-alu-fail-compile-subn.c  |  11 +
 .../riscv/cv-alu-fail-compile-subrn.c |  11 +
 .../riscv/cv-alu-fail-compile-subun.c |  11 +
 .../riscv/cv-alu-fail-compile-suburn.c|  11 +
 .../gcc.target/riscv/cv-alu-fail-compile.c|  32 ++
 gcc/testsuite/lib/target-supports.exp |  13 +
 24 files changed, 863 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addurn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clip.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clipu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-suburn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 53e21fa4bce..e7c1a99fbd2 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -311,6 +311,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"svpbmt",  ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1483,6 +1484,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"ztso", &gcc_options::x_riscv_ztso_subext, MASK_ZTSO},
 
   {"xcvmac",&g

[PATCH v4 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions

[Mary Bennett]

This patch series presents the comprehensive implementation of the MAC and ALU
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
    Mary Bennett 
Nandni Jamnadas 
Pietra Ferreira 
Charlie Keaney
Jessica Mills
Craig Blackmore 
Simon Cook 
Jeremy Bennett 
Helene Chelin 

  RISC-V: Add support for XCValu extension in CV32E40P
  RISC-V: Add support for XCVmac extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |   6 +
 gcc/config/riscv/constraints.md   |   7 +
 gcc/config/riscv/corev.def|  43 ++
 gcc/config/riscv/corev.md | 693 ++
 gcc/config/riscv/predicates.md|   5 +
 gcc/config/riscv/riscv-builtins.cc|  13 +
 gcc/config/riscv/riscv-ftypes.def |  11 +
 gcc/config/riscv/riscv.cc |   7 +
 gcc/config/riscv/riscv.md |   1 +
 gcc/config/riscv/riscv.opt|   7 +
 gcc/doc/extend.texi   | 174 +
 gcc/doc/sourcebuild.texi  |  12 +
 .../gcc.target/riscv/cv-alu-compile.c | 252 +++
 .../riscv/cv-alu-fail-compile-addn.c  |  11 +
 .../riscv/cv-alu-fail-compile-addrn.c |  11 +
 .../riscv/cv-alu-fail-compile-addun.c |  11 +
 .../riscv/cv-alu-fail-compile-addurn.c|  11 +
 .../riscv/cv-alu-fail-compile-clip.c  |  11 +
 .../riscv/cv-alu-fail-compile-clipu.c |  11 +
 .../riscv/cv-alu-fail-compile-subn.c  |  11 +
 .../riscv/cv-alu-fail-compile-subrn.c |  11 +
 .../riscv/cv-alu-fail-compile-subun.c |  11 +
 .../riscv/cv-alu-fail-compile-suburn.c|  11 +
 .../gcc.target/riscv/cv-alu-fail-compile.c|  32 +
 .../gcc.target/riscv/cv-mac-compile.c | 198 +
 .../riscv/cv-mac-fail-compile-mac.c   |  25 +
 .../riscv/cv-mac-fail-compile-machhsn.c   |  24 +
 .../riscv/cv-mac-fail-compile-machhsrn.c  |  24 +
 .../riscv/cv-mac-fail-compile-machhun.c   |  24 +
 .../riscv/cv-mac-fail-compile-machhurn.c  |  24 +
 .../riscv/cv-mac-fail-compile-macsn.c |  24 +
 .../riscv/cv-mac-fail-compile-macsrn.c|  24 +
 .../riscv/cv-mac-fail-compile-macun.c |  24 +
 .../riscv/cv-mac-fail-compile-macurn.c|  24 +
 .../riscv/cv-mac-fail-compile-msu.c   |  25 +
 .../riscv/cv-mac-fail-compile-mulhhsn.c   |  24 +
 .../riscv/cv-mac-fail-compile-mulhhsrn.c  |  24 +
 .../riscv/cv-mac-fail-compile-mulhhun.c   |  24 +
 .../riscv/cv-mac-fail-compile-mulhhurn.c  |  24 +
 .../riscv/cv-mac-fail-compile-mulsn.c |  24 +
 .../riscv/cv-mac-fail-compile-mulsrn.c|  24 +
 .../riscv/cv-mac-fail-compile-mulun.c |  24 +
 .../riscv/cv-mac-fail-compile-mulurn.c|  24 +
 .../riscv/cv-mac-test-autogeneration.c|  18 +
 gcc/testsuite/lib/target-supports.exp |  26 +
 45 files changed, 2049 insertions(+)
 create mode 100644 gcc/config/riscv/corev.def
 create mode 100644 gcc/config/riscv/corev.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addurn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clip.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clipu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-suburn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mac.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsn.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhun.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhurn.c
 create mode 100644 gcc/testsuite/gcc.target/ris

[PATCH v4 2/2] RISC-V: Add support for XCValu extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add the XCValu
extension.
* config/riscv/constraints.md: Add builtins for the XCValu
extension.
* config/riscv/predicates.md (immediate_register_operand):
Likewise.
* config/riscv/corev.def: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
  (RISCV_ATYPE_UHI): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv-opts.h: Likewise.
* config/riscv/riscv.opt: Likewise.
* config/riscv/riscv.cc (riscv_print_operand): Likewise.
* doc/extend.texi: Add XCValu documentation.
* doc/sourcebuild.texi: Likewise.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp: Add proc for the XCValu extension.
* gcc.target/riscv/cv-alu-compile.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-addn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-addrn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-addun.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-addurn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-clip.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-clipu.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-subn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-subrn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-subun.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-suburn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |   7 +
 gcc/config/riscv/corev.def|  24 ++
 gcc/config/riscv/corev.md | 303 ++
 gcc/config/riscv/predicates.md|   5 +
 gcc/config/riscv/riscv-builtins.cc|   3 +
 gcc/config/riscv/riscv-ftypes.def |   6 +
 gcc/config/riscv/riscv.cc |   7 +
 gcc/config/riscv/riscv.opt|   2 +
 gcc/doc/extend.texi   |  94 ++
 gcc/doc/sourcebuild.texi  |   3 +
 .../gcc.target/riscv/cv-alu-compile.c | 252 +++
 .../riscv/cv-alu-fail-compile-addn.c  |  11 +
 .../riscv/cv-alu-fail-compile-addrn.c |  11 +
 .../riscv/cv-alu-fail-compile-addun.c |  11 +
 .../riscv/cv-alu-fail-compile-addurn.c|  11 +
 .../riscv/cv-alu-fail-compile-clip.c  |  11 +
 .../riscv/cv-alu-fail-compile-clipu.c |  11 +
 .../riscv/cv-alu-fail-compile-subn.c  |  11 +
 .../riscv/cv-alu-fail-compile-subrn.c |  11 +
 .../riscv/cv-alu-fail-compile-subun.c |  11 +
 .../riscv/cv-alu-fail-compile-suburn.c|  11 +
 .../gcc.target/riscv/cv-alu-fail-compile.c|  32 ++
 gcc/testsuite/lib/target-supports.exp |  13 +
 24 files changed, 863 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addurn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clip.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clipu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-suburn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 62de116803e..908e8e0c8bd 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -311,6 +311,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"svpbmt",  ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1483,6 +1484,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"ztso", &gcc_options::x_riscv_ztso_subext, MASK_ZTSO},
 
   {"xcvmac",&gc

[PATCH v4 1/2] RISC-V: Add support for XCVmac extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add XCVmac.
* config/riscv/riscv-ftypes.def: Add XCVmac builtins.
* config/riscv/riscv-opts.h: Likewise.
* config/riscv/riscv.md: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Add XCVmac builtin documentation.
* doc/sourcebuild.texi: Likewise.
* config/riscv/corev.def: New file.
* config/riscv/corev.md: New file.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp: Add new effective target check.
* gcc.target/riscv/cv-mac-compile.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mac.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-machhsn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-machhsrn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-machhun.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-machhurn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-macsn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-macsrn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-macun.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-macurn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-msu.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulhhsn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulhhsrn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulhhun.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulhhurn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulsn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulsrn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulun.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulurn.c: New test.
* gcc.target/riscv/cv-mac-test-autogeneration.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc   |   4 +
 gcc/config/riscv/corev.def|  19 +
 gcc/config/riscv/corev.md | 390 ++
 gcc/config/riscv/riscv-builtins.cc|  10 +
 gcc/config/riscv/riscv-ftypes.def |   5 +
 gcc/config/riscv/riscv.md |   1 +
 gcc/config/riscv/riscv.opt|   5 +
 gcc/doc/extend.texi   |  80 
 gcc/doc/sourcebuild.texi  |   9 +
 .../gcc.target/riscv/cv-mac-compile.c | 198 +
 .../riscv/cv-mac-fail-compile-mac.c   |  25 ++
 .../riscv/cv-mac-fail-compile-machhsn.c   |  24 ++
 .../riscv/cv-mac-fail-compile-machhsrn.c  |  24 ++
 .../riscv/cv-mac-fail-compile-machhun.c   |  24 ++
 .../riscv/cv-mac-fail-compile-machhurn.c  |  24 ++
 .../riscv/cv-mac-fail-compile-macsn.c |  24 ++
 .../riscv/cv-mac-fail-compile-macsrn.c|  24 ++
 .../riscv/cv-mac-fail-compile-macun.c |  24 ++
 .../riscv/cv-mac-fail-compile-macurn.c|  24 ++
 .../riscv/cv-mac-fail-compile-msu.c   |  25 ++
 .../riscv/cv-mac-fail-compile-mulhhsn.c   |  24 ++
 .../riscv/cv-mac-fail-compile-mulhhsrn.c  |  24 ++
 .../riscv/cv-mac-fail-compile-mulhhun.c   |  24 ++
 .../riscv/cv-mac-fail-compile-mulhhurn.c  |  24 ++
 .../riscv/cv-mac-fail-compile-mulsn.c |  24 ++
 .../riscv/cv-mac-fail-compile-mulsrn.c|  24 ++
 .../riscv/cv-mac-fail-compile-mulun.c |  24 ++
 .../riscv/cv-mac-fail-compile-mulurn.c|  24 ++
 .../riscv/cv-mac-test-autogeneration.c|  18 +
 gcc/testsuite/lib/target-supports.exp |  13 +
 30 files changed, 1186 insertions(+)
 create mode 100644 gcc/config/riscv/corev.def
 create mode 100644 gcc/config/riscv/corev.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mac.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsn.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhun.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhurn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macurn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-msu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhsn.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile

[PATCH] RISCV: Bugfix for incorrect documentation heading nesting

[Mary Bennett]

gcc/ChangeLog:
* doc/extend.texi: Change subsubsection to subsection for
  CORE-V built-ins.
---
 gcc/doc/extend.texi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index ffe8532ad91..e8180945ab4 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -21719,7 +21719,7 @@ vector intrinsic specification, which is available at 
the following link:
 All of these functions are declared in the include file @file{riscv_vector.h}.
 
 @node CORE-V Built-in Functions
-@subsubsection CORE-V Built-in Functions
+@subsection CORE-V Built-in Functions
 
 These built-in functions are available for the CORE-V MAC machine
 architecture. For more information on CORE-V built-ins, please see
-- 
2.34.1

[PATCH v2 0/1] RISC-V: Support CORE-V XCVMEM extension

[Mary Bennett]

This patch series presents the comprehensive implementation of the MEM
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

RISC-V: Add support for XCVmem extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |  29 ++
 gcc/config/riscv/corev.md | 270 ++
 gcc/config/riscv/predicates.md|  20 +-
 gcc/config/riscv/riscv-protos.h   |  12 +-
 gcc/config/riscv/riscv.cc |  48 +++-
 gcc/config/riscv/riscv.h  |   4 +-
 gcc/config/riscv/riscv.md |  26 +-
 gcc/config/riscv/riscv.opt|   2 +
 gcc/doc/sourcebuild.texi  |   3 +
 .../gcc.target/riscv/cv-mem-lb-compile-1.c|  23 ++
 .../gcc.target/riscv/cv-mem-lb-compile-2.c|  24 ++
 .../gcc.target/riscv/cv-mem-lb-compile-3.c|  16 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-1.c   |  23 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-2.c   |  24 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-3.c   |  16 ++
 .../gcc.target/riscv/cv-mem-lh-compile-1.c|  23 ++
 .../gcc.target/riscv/cv-mem-lh-compile-2.c|  24 ++
 .../gcc.target/riscv/cv-mem-lh-compile-3.c|  16 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-1.c   |  23 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-2.c   |  24 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-3.c   |  16 ++
 .../gcc.target/riscv/cv-mem-lw-compile-1.c|  38 +++
 .../gcc.target/riscv/cv-mem-lw-compile-2.c|  38 +++
 .../gcc.target/riscv/cv-mem-lw-compile-3.c|  22 ++
 .../riscv/cv-mem-operand-compile-1.c  |  19 ++
 .../riscv/cv-mem-operand-compile-2.c  |  20 ++
 .../riscv/cv-mem-operand-compile-3.c  |  28 ++
 .../riscv/cv-mem-operand-compile-4.c  |  21 ++
 .../riscv/cv-mem-operand-compile-5.c  |  25 ++
 .../riscv/cv-mem-operand-compile-6.c  |  21 ++
 .../riscv/cv-mem-operand-compile-7.c  |  24 ++
 .../riscv/cv-mem-operand-compile-8.c  |  18 ++
 .../gcc.target/riscv/cv-mem-sb-compile-1.c|  36 +++
 .../gcc.target/riscv/cv-mem-sb-compile-2.c|  38 +++
 .../gcc.target/riscv/cv-mem-sb-compile-3.c|  30 ++
 .../gcc.target/riscv/cv-mem-sh-compile-1.c|  36 +++
 .../gcc.target/riscv/cv-mem-sh-compile-2.c|  38 +++
 .../gcc.target/riscv/cv-mem-sh-compile-3.c|  30 ++
 .../gcc.target/riscv/cv-mem-sw-compile-1.c|  36 +++
 .../gcc.target/riscv/cv-mem-sw-compile-2.c|  38 +++
 .../gcc.target/riscv/cv-mem-sw-compile-3.c|  30 ++
 gcc/testsuite/lib/target-supports.exp |  13 +
 43 files changed, 1247 insertions(+), 20 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-7.c
 create mode 100644 gcc/testsuite/gcc.t

[PATCH v2 1/1] RISC-V: Add support for XCVmem extension in CV32E40P

[Mary Bennett]

XCVmem adds more loads and stores. To prevent non-XCVmem loads and
stores from generating illegal XCVmem specific operands, constraint
'm' was redefined. 'm' does not accept POST_MODIFY or reg + reg
addresses.

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add the XCVmem
  extension.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/predicates.md: Likewise.
* config/riscv/riscv-protos.h: Likewise.
* config/riscv/riscv.cc: Add POST_MODIFY.
* config/riscv/riscv.h: Likewise.
* config/riscv/riscv.md: Prevent XCVmem operands being
  used in non-XCVmem loads and stores.
* config/riscv/constraints.md: Likewise.
* config/riscv/predicates.md: Likewise.
* doc/sourcebuild.texi: Add XCVmem documentation.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-mem-operand-compile-1.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-2.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-3.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-4.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-5.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-6.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-7.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-8.c: New test.
* gcc.target/riscv/cv-mem-lb-compile-1.c: New test.
* gcc.target/riscv/cv-mem-lb-compile-2.c: New test.
* gcc.target/riscv/cv-mem-lb-compile-3.c: New test.
* gcc.target/riscv/cv-mem-lbu-compile-1.c: New test.
* gcc.target/riscv/cv-mem-lbu-compile-2.c: New test.
* gcc.target/riscv/cv-mem-lbu-compile-3.c: New test.
* gcc.target/riscv/cv-mem-lh-compile-1.c: New test.
* gcc.target/riscv/cv-mem-lh-compile-2.c: New test.
* gcc.target/riscv/cv-mem-lh-compile-3.c: New test.
* gcc.target/riscv/cv-mem-lhu-compile-1.c: New test.
* gcc.target/riscv/cv-mem-lhu-compile-2.c: New test.
* gcc.target/riscv/cv-mem-lhu-compile-3.c: New test.
* gcc.target/riscv/cv-mem-lw-compile-1.c: New test.
* gcc.target/riscv/cv-mem-lw-compile-2.c: New test.
* gcc.target/riscv/cv-mem-lw-compile-3.c: New test.
* gcc.target/riscv/cv-mem-sb-compile-1.c: New test.
* gcc.target/riscv/cv-mem-sb-compile-2.c: New test.
* gcc.target/riscv/cv-mem-sb-compile-3.c: New test.
* gcc.target/riscv/cv-mem-sh-compile-1.c: New test.
* gcc.target/riscv/cv-mem-sh-compile-2.c: New test.
* gcc.target/riscv/cv-mem-sh-compile-3.c: New test.
* gcc.target/riscv/cv-mem-sw-compile-1.c: New test.
* gcc.target/riscv/cv-mem-sw-compile-2.c: New test.
* gcc.target/riscv/cv-mem-sw-compile-3.c: New test.
* lib/target-supports.exp: Add proc for XCVmem.

Change the priority of the XCVmem instructions

Returned corev.md to be included at the bottom of riscv.md.

Files Changed:
 * corev.md: Added generic load/ store instructions with lower
   priority than the XCVmem load/ store instructions.
 * riscv.md: Prevent generic load/ store instructions having higher
   priority than XCVmem load/ store if the extension is included.
---
 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |  29 ++
 gcc/config/riscv/corev.md | 270 ++
 gcc/config/riscv/predicates.md|  20 +-
 gcc/config/riscv/riscv-protos.h   |  12 +-
 gcc/config/riscv/riscv.cc |  48 +++-
 gcc/config/riscv/riscv.h  |   4 +-
 gcc/config/riscv/riscv.md |  26 +-
 gcc/config/riscv/riscv.opt|   2 +
 gcc/doc/sourcebuild.texi  |   3 +
 .../gcc.target/riscv/cv-mem-lb-compile-1.c|  23 ++
 .../gcc.target/riscv/cv-mem-lb-compile-2.c|  24 ++
 .../gcc.target/riscv/cv-mem-lb-compile-3.c|  16 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-1.c   |  23 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-2.c   |  24 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-3.c   |  16 ++
 .../gcc.target/riscv/cv-mem-lh-compile-1.c|  23 ++
 .../gcc.target/riscv/cv-mem-lh-compile-2.c|  24 ++
 .../gcc.target/riscv/cv-mem-lh-compile-3.c|  16 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-1.c   |  23 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-2.c   |  24 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-3.c   |  16 ++
 .../gcc.target/riscv/cv-mem-lw-compile-1.c|  38 +++
 .../gcc.target/riscv/cv-mem-lw-compile-2.c|  38 +++
 .../gcc.target/riscv/cv-mem-lw-compile-3.c|  22 ++
 .../riscv/cv-mem

[PATCH v2 0/1] RISC-V: Support CORE-V XCVBITMAIP extension

[Mary Bennett]

v1 -> v2:
 * Updated rtl for bclr, bset, insert and extract[u].

This patch series presents the comprehensive implementation of the BITMANIP
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

RISC-V: Add support for XCVbitmanip extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |  16 ++
 gcc/config/riscv/corev.def|  13 ++
 gcc/config/riscv/corev.md | 164 ++
 gcc/config/riscv/predicates.md|  16 ++
 gcc/config/riscv/riscv-builtins.cc|   1 +
 gcc/config/riscv/riscv-ftypes.def |   5 +
 gcc/config/riscv/riscv.cc |  13 ++
 gcc/config/riscv/riscv.opt|   2 +
 gcc/doc/extend.texi   |  53 ++
 gcc/doc/sourcebuild.texi  |   3 +
 .../riscv/cv-bitmanip-compile-bclr.c  |  27 +++
 .../riscv/cv-bitmanip-compile-bclrr.c |  18 ++
 .../riscv/cv-bitmanip-compile-bitrev.c|  30 
 .../riscv/cv-bitmanip-compile-bset.c  |  27 +++
 .../riscv/cv-bitmanip-compile-bsetr.c |  18 ++
 .../riscv/cv-bitmanip-compile-clb.c   |  18 ++
 .../riscv/cv-bitmanip-compile-cnt.c   |  18 ++
 .../riscv/cv-bitmanip-compile-extract.c   |  27 +++
 .../riscv/cv-bitmanip-compile-extractr.c  |  18 ++
 .../riscv/cv-bitmanip-compile-extractu.c  |  27 +++
 .../riscv/cv-bitmanip-compile-extractur.c |  18 ++
 .../riscv/cv-bitmanip-compile-ff1.c   |  18 ++
 .../riscv/cv-bitmanip-compile-fl1.c   |  18 ++
 .../riscv/cv-bitmanip-compile-insert.c|  24 +++
 .../riscv/cv-bitmanip-compile-insertr.c   |  18 ++
 .../riscv/cv-bitmanip-compile-ror.c   |  18 ++
 .../riscv/cv-bitmanip-fail-compile-bclr.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-bitrev.c   |  23 +++
 .../riscv/cv-bitmanip-fail-compile-bset.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-extract.c  |  25 +++
 .../riscv/cv-bitmanip-fail-compile-extractu.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-insert.c   |  25 +++
 gcc/testsuite/lib/target-supports.exp |  13 ++
 34 files changed, 791 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclrr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bitrev.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bset.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bsetr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-clb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-cnt.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extract.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extractr.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extractu.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extractur.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-ff1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-fl1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-insert.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-insertr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-ror.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-bclr.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-bitrev.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-bset.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-extract.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-extractu.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-insert.c

-- 
2.34.1

[PATCH v2 1/1] RISC-V: Add support for XCVbitmanip extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add XCVbitmanip.
* config/riscv/constraints.md: Likewise.
* config/riscv/corev.def: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/predicates.md: Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Add XCVbitmanip builtin documentation.
* doc/sourcebuild.texi: Likewise.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bitmanip-compile-bclr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bclrr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bitrev.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bset.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bsetr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-clb.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-cnt.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extract.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extractr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extractu.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extractur.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-ff1.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-fl1.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-insert.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-insertr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-ror.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-bclr.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-bitrev.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-bset.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-extract.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-extractu.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-insert.c: New test.
* lib/target-supports.exp: Add proc for the XCVbitmanip extension.
---
 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |  16 ++
 gcc/config/riscv/corev.def|  13 ++
 gcc/config/riscv/corev.md | 164 ++
 gcc/config/riscv/predicates.md|  16 ++
 gcc/config/riscv/riscv-builtins.cc|   1 +
 gcc/config/riscv/riscv-ftypes.def |   5 +
 gcc/config/riscv/riscv.cc |  13 ++
 gcc/config/riscv/riscv.opt|   2 +
 gcc/doc/extend.texi   |  53 ++
 gcc/doc/sourcebuild.texi  |   3 +
 .../riscv/cv-bitmanip-compile-bclr.c  |  27 +++
 .../riscv/cv-bitmanip-compile-bclrr.c |  18 ++
 .../riscv/cv-bitmanip-compile-bitrev.c|  30 
 .../riscv/cv-bitmanip-compile-bset.c  |  27 +++
 .../riscv/cv-bitmanip-compile-bsetr.c |  18 ++
 .../riscv/cv-bitmanip-compile-clb.c   |  18 ++
 .../riscv/cv-bitmanip-compile-cnt.c   |  18 ++
 .../riscv/cv-bitmanip-compile-extract.c   |  27 +++
 .../riscv/cv-bitmanip-compile-extractr.c  |  18 ++
 .../riscv/cv-bitmanip-compile-extractu.c  |  27 +++
 .../riscv/cv-bitmanip-compile-extractur.c |  18 ++
 .../riscv/cv-bitmanip-compile-ff1.c   |  18 ++
 .../riscv/cv-bitmanip-compile-fl1.c   |  18 ++
 .../riscv/cv-bitmanip-compile-insert.c|  24 +++
 .../riscv/cv-bitmanip-compile-insertr.c   |  18 ++
 .../riscv/cv-bitmanip-compile-ror.c   |  18 ++
 .../riscv/cv-bitmanip-fail-compile-bclr.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-bitrev.c   |  23 +++
 .../riscv/cv-bitmanip-fail-compile-bset.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-extract.c  |  25 +++
 .../riscv/cv-bitmanip-fail-compile-extractu.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-insert.c   |  25 +++
 gcc/testsuite/lib/target-supports.exp |  13 ++
 34 files changed, 791 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclrr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bitrev.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bset.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bsetr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-clb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-cnt.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extract.c
 create mode

[PATCH v2 2/2] RISC-V: Fix XCValu test

[Mary Bennett]

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-alu-fail-compile.c: Change warning to error.
---
 .../gcc.target/riscv/cv-alu-fail-compile.c| 40 +--
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c 
b/gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c
index bbdb2d58c3f..89c7f6f2f5a 100644
--- a/gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c
+++ b/gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c
@@ -7,26 +7,26 @@ extern int d;
 int
 foo(int a, int b, int c)
 {
-d += __builtin_riscv_cv_alu_slet (a, b); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_sletu (a, b);  /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_addN (a, b, 31);  /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_addRN (a, b, 31); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_adduN (a, b, 31); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_adduRN (a, b, 31); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_clip (a, 31); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_clipu (a, 35); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_extbs (a); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_extbz (a); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_exths (a); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_exthz (a); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_min (a, b); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_minu (a, b); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_max (a, b); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_maxu (a, b); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_subN (a, b, 31); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_subRN (a, b, 31); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_subuN (a, b, 31); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_subuRN (a, b, 31); /* { dg-warning "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_slet (a, b); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_sletu (a, b);  /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_addN (a, b, 31);  /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_addRN (a, b, 31); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_adduN (a, b, 31); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_adduRN (a, b, 31); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_clip (a, 31); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_clipu (a, 35); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_extbs (a); /* { dg-error "implicit declaration 
of function" } */
+d += __builtin_riscv_cv_alu_extbz (a); /* { dg-error "implicit declaration 
of function" } */
+d += __builtin_riscv_cv_alu_exths (a); /* { dg-error "implicit declaration 
of function" } */
+d += __builtin_riscv_cv_alu_exthz (a); /* { dg-error "implicit declaration 
of function" } */
+d += __builtin_riscv_cv_alu_min (a, b); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_minu (a, b); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_max (a, b); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_maxu (a, b); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_subN (a, b, 31); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_subRN (a, b, 31); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_subuN (a, b, 31); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_subuRN (a, b, 31); /* { dg-error "implicit 
declaration of function" } */
 
 return d;
 }
-- 
2.34.1

[PATCH v2 0/2] RISC-V: Support CORE-V XCVSIMD extension

[Mary Bennett]

This patch series presents the comprehensive implementation of the SIMD
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

RISC-V: Add support for XCVsimd extension in CV32E40P
RISC-V: Fix XCValu test

 gcc/common/config/riscv/riscv-common.cc   |2 +
 gcc/config/riscv/constraints.md   |   30 +
 gcc/config/riscv/corev.def|  156 ++
 gcc/config/riscv/corev.md | 1908 +
 gcc/config/riscv/predicates.md|   20 +
 gcc/config/riscv/riscv-builtins.cc|1 +
 gcc/config/riscv/riscv-ftypes.def |9 +
 gcc/config/riscv/riscv.cc |8 +
 gcc/config/riscv/riscv.opt|2 +
 gcc/doc/extend.texi   |  886 
 gcc/doc/sourcebuild.texi  |3 +
 .../riscv/cv-simd-abs-b-compile-1.c   |   11 +
 .../riscv/cv-simd-abs-h-compile-1.c   |   11 +
 .../riscv/cv-simd-add-b-compile-1.c   |   11 +
 .../riscv/cv-simd-add-div2-compile-1.c|   11 +
 .../riscv/cv-simd-add-div4-compile-1.c|   11 +
 .../riscv/cv-simd-add-div8-compile-1.c|   11 +
 .../riscv/cv-simd-add-h-compile-1.c   |   11 +
 .../riscv/cv-simd-add-sc-b-compile-1.c|   30 +
 .../riscv/cv-simd-add-sc-h-compile-1.c|   30 +
 .../riscv/cv-simd-and-b-compile-1.c   |   11 +
 .../riscv/cv-simd-and-h-compile-1.c   |   11 +
 .../riscv/cv-simd-and-sc-b-compile-1.c|   30 +
 .../riscv/cv-simd-and-sc-h-compile-1.c|   30 +
 .../riscv/cv-simd-avg-b-compile-1.c   |   11 +
 .../riscv/cv-simd-avg-h-compile-1.c   |   11 +
 .../riscv/cv-simd-avg-sc-b-compile-1.c|   30 +
 .../riscv/cv-simd-avg-sc-h-compile-1.c|   30 +
 .../riscv/cv-simd-avgu-b-compile-1.c  |   11 +
 .../riscv/cv-simd-avgu-h-compile-1.c  |   11 +
 .../riscv/cv-simd-avgu-sc-b-compile-1.c   |   24 +
 .../riscv/cv-simd-avgu-sc-h-compile-1.c   |   24 +
 .../riscv/cv-simd-cmpeq-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmpeq-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmpeq-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpeq-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpge-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmpge-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmpge-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpge-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpgeu-b-compile-1.c|   11 +
 .../riscv/cv-simd-cmpgeu-h-compile-1.c|   11 +
 .../riscv/cv-simd-cmpgeu-sc-b-compile-1.c |   24 +
 .../riscv/cv-simd-cmpgeu-sc-h-compile-1.c |   24 +
 .../riscv/cv-simd-cmpgt-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmpgt-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmpgt-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpgt-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpgtu-b-compile-1.c|   11 +
 .../riscv/cv-simd-cmpgtu-h-compile-1.c|   11 +
 .../riscv/cv-simd-cmpgtu-sc-b-compile-1.c |   24 +
 .../riscv/cv-simd-cmpgtu-sc-h-compile-1.c |   24 +
 .../riscv/cv-simd-cmple-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmple-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmple-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmple-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpleu-b-compile-1.c|   11 +
 .../riscv/cv-simd-cmpleu-h-compile-1.c|   11 +
 .../riscv/cv-simd-cmpleu-sc-b-compile-1.c |   24 +
 .../riscv/cv-simd-cmpleu-sc-h-compile-1.c |   24 +
 .../riscv/cv-simd-cmplt-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmplt-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmplt-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmplt-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpltu-b-compile-1.c|   11 +
 .../riscv/cv-simd-cmpltu-h-compile-1.c|   11 +
 .../riscv/cv-simd-cmpltu-sc-b-compile-1.c |   24 +
 .../riscv/cv-simd-cmpltu-sc-h-compile-1.c |   24 +
 .../riscv/cv-simd-cmpne-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmpne-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmpne-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpne-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cplxconj-compile-1.c|   11 +
 .../riscv/cv-simd-cplxmul-i-compil

[PATCH v3 2/2] RISC-V: Fix XCValu test

[Mary Bennett]

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-alu-fail-compile.c: Change warning to error.
---
 .../gcc.target/riscv/cv-alu-fail-compile.c| 40 +--
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c 
b/gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c
index bbdb2d58c3f..89c7f6f2f5a 100644
--- a/gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c
+++ b/gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c
@@ -7,26 +7,26 @@ extern int d;
 int
 foo(int a, int b, int c)
 {
-d += __builtin_riscv_cv_alu_slet (a, b); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_sletu (a, b);  /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_addN (a, b, 31);  /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_addRN (a, b, 31); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_adduN (a, b, 31); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_adduRN (a, b, 31); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_clip (a, 31); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_clipu (a, 35); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_extbs (a); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_extbz (a); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_exths (a); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_exthz (a); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_min (a, b); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_minu (a, b); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_max (a, b); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_maxu (a, b); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_subN (a, b, 31); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_subRN (a, b, 31); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_subuN (a, b, 31); /* { dg-warning "implicit 
declaration of function" } */
-d += __builtin_riscv_cv_alu_subuRN (a, b, 31); /* { dg-warning "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_slet (a, b); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_sletu (a, b);  /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_addN (a, b, 31);  /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_addRN (a, b, 31); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_adduN (a, b, 31); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_adduRN (a, b, 31); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_clip (a, 31); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_clipu (a, 35); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_extbs (a); /* { dg-error "implicit declaration 
of function" } */
+d += __builtin_riscv_cv_alu_extbz (a); /* { dg-error "implicit declaration 
of function" } */
+d += __builtin_riscv_cv_alu_exths (a); /* { dg-error "implicit declaration 
of function" } */
+d += __builtin_riscv_cv_alu_exthz (a); /* { dg-error "implicit declaration 
of function" } */
+d += __builtin_riscv_cv_alu_min (a, b); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_minu (a, b); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_max (a, b); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_maxu (a, b); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_subN (a, b, 31); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_subRN (a, b, 31); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_subuN (a, b, 31); /* { dg-error "implicit 
declaration of function" } */
+d += __builtin_riscv_cv_alu_subuRN (a, b, 31); /* { dg-error "implicit 
declaration of function" } */
 
 return d;
 }
-- 
2.34.1

[PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension

[Mary Bennett]

v2 -> v3:
 * Removed duplicate ftype.

This patch series presents the comprehensive implementation of the SIMD
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

RISC-V: Add support for XCVsimd extension in CV32E40P
RISC-V: Fix XCValu test

 gcc/common/config/riscv/riscv-common.cc   |2 +
 gcc/config/riscv/constraints.md   |   30 +
 gcc/config/riscv/corev.def|  156 ++
 gcc/config/riscv/corev.md | 1908 +
 gcc/config/riscv/predicates.md|   20 +
 gcc/config/riscv/riscv-builtins.cc|1 +
 gcc/config/riscv/riscv-ftypes.def |8 +
 gcc/config/riscv/riscv.cc |8 +
 gcc/config/riscv/riscv.opt|2 +
 gcc/doc/extend.texi   |  886 
 gcc/doc/sourcebuild.texi  |3 +
 .../gcc.target/riscv/cv-alu-fail-compile.c|   40 +-
 .../riscv/cv-simd-abs-b-compile-1.c   |   11 +
 .../riscv/cv-simd-abs-h-compile-1.c   |   11 +
 .../riscv/cv-simd-add-b-compile-1.c   |   11 +
 .../riscv/cv-simd-add-div2-compile-1.c|   11 +
 .../riscv/cv-simd-add-div4-compile-1.c|   11 +
 .../riscv/cv-simd-add-div8-compile-1.c|   11 +
 .../riscv/cv-simd-add-h-compile-1.c   |   11 +
 .../riscv/cv-simd-add-sc-b-compile-1.c|   30 +
 .../riscv/cv-simd-add-sc-h-compile-1.c|   30 +
 .../riscv/cv-simd-and-b-compile-1.c   |   11 +
 .../riscv/cv-simd-and-h-compile-1.c   |   11 +
 .../riscv/cv-simd-and-sc-b-compile-1.c|   30 +
 .../riscv/cv-simd-and-sc-h-compile-1.c|   30 +
 .../riscv/cv-simd-avg-b-compile-1.c   |   11 +
 .../riscv/cv-simd-avg-h-compile-1.c   |   11 +
 .../riscv/cv-simd-avg-sc-b-compile-1.c|   30 +
 .../riscv/cv-simd-avg-sc-h-compile-1.c|   30 +
 .../riscv/cv-simd-avgu-b-compile-1.c  |   11 +
 .../riscv/cv-simd-avgu-h-compile-1.c  |   11 +
 .../riscv/cv-simd-avgu-sc-b-compile-1.c   |   24 +
 .../riscv/cv-simd-avgu-sc-h-compile-1.c   |   24 +
 .../riscv/cv-simd-cmpeq-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmpeq-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmpeq-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpeq-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpge-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmpge-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmpge-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpge-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpgeu-b-compile-1.c|   11 +
 .../riscv/cv-simd-cmpgeu-h-compile-1.c|   11 +
 .../riscv/cv-simd-cmpgeu-sc-b-compile-1.c |   24 +
 .../riscv/cv-simd-cmpgeu-sc-h-compile-1.c |   24 +
 .../riscv/cv-simd-cmpgt-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmpgt-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmpgt-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpgt-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpgtu-b-compile-1.c|   11 +
 .../riscv/cv-simd-cmpgtu-h-compile-1.c|   11 +
 .../riscv/cv-simd-cmpgtu-sc-b-compile-1.c |   24 +
 .../riscv/cv-simd-cmpgtu-sc-h-compile-1.c |   24 +
 .../riscv/cv-simd-cmple-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmple-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmple-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmple-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpleu-b-compile-1.c|   11 +
 .../riscv/cv-simd-cmpleu-h-compile-1.c|   11 +
 .../riscv/cv-simd-cmpleu-sc-b-compile-1.c |   24 +
 .../riscv/cv-simd-cmpleu-sc-h-compile-1.c |   24 +
 .../riscv/cv-simd-cmplt-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmplt-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmplt-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmplt-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpltu-b-compile-1.c|   11 +
 .../riscv/cv-simd-cmpltu-h-compile-1.c|   11 +
 .../riscv/cv-simd-cmpltu-sc-b-compile-1.c |   24 +
 .../riscv/cv-simd-cmpltu-sc-h-compile-1.c |   24 +
 .../riscv/cv-simd-cmpne-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmpne-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmpne-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpne-sc-h-compile-1.c

Re: [PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P

[Mary Bennett]

On 09/01/2024 18:43, Jeff Law wrote:



On 1/8/24 06:14, Mary Bennett wrote:
Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md


Contributors:
   Mary Bennett 
   Nandni Jamnadas 
   Pietra Ferreira 
   Charlie Keaney
   Jessica Mills
   Craig Blackmore 
   Simon Cook 
   Jeremy Bennett 
   Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Create XCVbi extension
  support.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Implement cv_branch pattern
  for cv.beqimm and cv.bneimm.
* config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
  branch instruction pattern.
* config/riscv/constraints.md: Implement constraints
  cv_bi_s5 - signed 5-bit immediate.
* config/riscv/predicates.md: Implement predicate
  const_int5s_operand - signed 5 bit immediate.
* doc/sourcebuild.texi: Add XCVbi documentation.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
* lib/target-supports.exp: Add proc for XCVbi.
Assuming this has gone through a testing cycle, this is fine for the 
trunk.


Thanks,
jeff


This patch passes regression. Are there any other changes required 
before it can be merged?



Kind regards,

Mary



OpenPGP_0xEA0457E97E867D75.asc
Description: OpenPGP public key


OpenPGP_signature.asc
Description: OpenPGP digital signature

[PATCH v3 0/1] RISC-V: Support CORE-V XCVBITMAIP extension

[Mary Bennett]

v2 -> v3:
 * Updated rtl for cnt, ff1, fl1, bclr, bset, insert and extract[u].
 * cv.bitrev requires groups of bits to reverse order. bitreverse does not
   support this.

This patch series presents the comprehensive implementation of the BITMANIP
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

RISC-V: Add support for XCVbitmanip extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |  16 ++
 gcc/config/riscv/corev.def|  13 ++
 gcc/config/riscv/corev.md | 184 ++
 gcc/config/riscv/predicates.md|  16 ++
 gcc/config/riscv/riscv-builtins.cc|   1 +
 gcc/config/riscv/riscv-ftypes.def |   5 +
 gcc/config/riscv/riscv.cc |  13 ++
 gcc/config/riscv/riscv.opt|   2 +
 gcc/doc/extend.texi   |  53 +
 gcc/doc/sourcebuild.texi  |   3 +
 .../riscv/cv-bitmanip-compile-bclr.c  |  27 +++
 .../riscv/cv-bitmanip-compile-bclrr.c |  18 ++
 .../riscv/cv-bitmanip-compile-bitrev.c|  30 +++
 .../riscv/cv-bitmanip-compile-bset.c  |  27 +++
 .../riscv/cv-bitmanip-compile-bsetr.c |  18 ++
 .../riscv/cv-bitmanip-compile-clb.c   |  18 ++
 .../riscv/cv-bitmanip-compile-cnt.c   |  18 ++
 .../riscv/cv-bitmanip-compile-extract.c   |  27 +++
 .../riscv/cv-bitmanip-compile-extractr.c  |  18 ++
 .../riscv/cv-bitmanip-compile-extractu.c  |  27 +++
 .../riscv/cv-bitmanip-compile-extractur.c |  18 ++
 .../riscv/cv-bitmanip-compile-ff1.c   |  18 ++
 .../riscv/cv-bitmanip-compile-fl1.c   |  18 ++
 .../riscv/cv-bitmanip-compile-insert.c|  24 +++
 .../riscv/cv-bitmanip-compile-insertr.c   |  18 ++
 .../riscv/cv-bitmanip-compile-ror.c   |  18 ++
 .../riscv/cv-bitmanip-fail-compile-bclr.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-bitrev.c   |  23 +++
 .../riscv/cv-bitmanip-fail-compile-bset.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-extract.c  |  25 +++
 .../riscv/cv-bitmanip-fail-compile-extractu.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-insert.c   |  25 +++
 gcc/testsuite/lib/target-supports.exp |  13 ++
 34 files changed, 811 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclrr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bitrev.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bset.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bsetr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-clb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-cnt.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extract.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extractr.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extractu.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extractur.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-ff1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-fl1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-insert.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-insertr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-ror.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-bclr.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-bitrev.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-bset.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-extract.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-extractu.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-insert.c

-- 
2.34.1

[PATCH v3 1/1] RISC-V: Add support for XCVbitmanip extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add XCVbitmanip.
* config/riscv/constraints.md: Likewise.
* config/riscv/corev.def: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/predicates.md: Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Add XCVbitmanip builtin documentation.
* doc/sourcebuild.texi: Likewise.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bitmanip-compile-bclr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bclrr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bitrev.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bset.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bsetr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-clb.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-cnt.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extract.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extractr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extractu.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extractur.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-ff1.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-fl1.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-insert.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-insertr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-ror.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-bclr.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-bitrev.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-bset.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-extract.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-extractu.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-insert.c: New test.
* lib/target-supports.exp: Add proc for the XCVbitmanip extension.
---
 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |  16 ++
 gcc/config/riscv/corev.def|  13 ++
 gcc/config/riscv/corev.md | 184 ++
 gcc/config/riscv/predicates.md|  16 ++
 gcc/config/riscv/riscv-builtins.cc|   1 +
 gcc/config/riscv/riscv-ftypes.def |   5 +
 gcc/config/riscv/riscv.cc |  13 ++
 gcc/config/riscv/riscv.opt|   2 +
 gcc/doc/extend.texi   |  53 +
 gcc/doc/sourcebuild.texi  |   3 +
 .../riscv/cv-bitmanip-compile-bclr.c  |  27 +++
 .../riscv/cv-bitmanip-compile-bclrr.c |  18 ++
 .../riscv/cv-bitmanip-compile-bitrev.c|  30 +++
 .../riscv/cv-bitmanip-compile-bset.c  |  27 +++
 .../riscv/cv-bitmanip-compile-bsetr.c |  18 ++
 .../riscv/cv-bitmanip-compile-clb.c   |  18 ++
 .../riscv/cv-bitmanip-compile-cnt.c   |  18 ++
 .../riscv/cv-bitmanip-compile-extract.c   |  27 +++
 .../riscv/cv-bitmanip-compile-extractr.c  |  18 ++
 .../riscv/cv-bitmanip-compile-extractu.c  |  27 +++
 .../riscv/cv-bitmanip-compile-extractur.c |  18 ++
 .../riscv/cv-bitmanip-compile-ff1.c   |  18 ++
 .../riscv/cv-bitmanip-compile-fl1.c   |  18 ++
 .../riscv/cv-bitmanip-compile-insert.c|  24 +++
 .../riscv/cv-bitmanip-compile-insertr.c   |  18 ++
 .../riscv/cv-bitmanip-compile-ror.c   |  18 ++
 .../riscv/cv-bitmanip-fail-compile-bclr.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-bitrev.c   |  23 +++
 .../riscv/cv-bitmanip-fail-compile-bset.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-extract.c  |  25 +++
 .../riscv/cv-bitmanip-fail-compile-extractu.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-insert.c   |  25 +++
 gcc/testsuite/lib/target-supports.exp |  13 ++
 34 files changed, 811 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclrr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bitrev.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bset.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bsetr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-clb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-cnt.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extract.c
 create mode 100644

[PATCH v3 0/1] RISC-V: Support CORE-V XCVMEM extension

[Mary Bennett]

This patch series presents the comprehensive implementation of the MEM
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

RISC-V: Add support for XCVmem extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |  29 ++
 gcc/config/riscv/corev.md | 270 ++
 gcc/config/riscv/predicates.md|  20 +-
 gcc/config/riscv/riscv-protos.h   |  12 +-
 gcc/config/riscv/riscv.cc |  48 +++-
 gcc/config/riscv/riscv.h  |   4 +-
 gcc/config/riscv/riscv.md |  26 +-
 gcc/config/riscv/riscv.opt|   2 +
 gcc/doc/sourcebuild.texi  |   3 +
 .../gcc.target/riscv/cv-mem-lb-compile-1.c|  21 ++
 .../gcc.target/riscv/cv-mem-lb-compile-2.c|  24 ++
 .../gcc.target/riscv/cv-mem-lb-compile-3.c|  16 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-1.c   |  21 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-2.c   |  24 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-3.c   |  16 ++
 .../gcc.target/riscv/cv-mem-lh-compile-1.c|  21 ++
 .../gcc.target/riscv/cv-mem-lh-compile-2.c|  24 ++
 .../gcc.target/riscv/cv-mem-lh-compile-3.c|  16 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-1.c   |  21 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-2.c   |  24 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-3.c   |  16 ++
 .../gcc.target/riscv/cv-mem-lw-compile-1.c|  33 +++
 .../gcc.target/riscv/cv-mem-lw-compile-2.c|  38 +++
 .../gcc.target/riscv/cv-mem-lw-compile-3.c|  22 ++
 .../riscv/cv-mem-operand-compile-1.c  |  19 ++
 .../riscv/cv-mem-operand-compile-2.c  |  20 ++
 .../riscv/cv-mem-operand-compile-3.c  |  28 ++
 .../riscv/cv-mem-operand-compile-4.c  |  21 ++
 .../riscv/cv-mem-operand-compile-5.c  |  25 ++
 .../riscv/cv-mem-operand-compile-6.c  |  21 ++
 .../riscv/cv-mem-operand-compile-7.c  |  24 ++
 .../riscv/cv-mem-operand-compile-8.c  |  18 ++
 .../gcc.target/riscv/cv-mem-sb-compile-1.c|  32 +++
 .../gcc.target/riscv/cv-mem-sb-compile-2.c|  38 +++
 .../gcc.target/riscv/cv-mem-sb-compile-3.c|  30 ++
 .../gcc.target/riscv/cv-mem-sh-compile-1.c|  32 +++
 .../gcc.target/riscv/cv-mem-sh-compile-2.c|  38 +++
 .../gcc.target/riscv/cv-mem-sh-compile-3.c|  30 ++
 .../gcc.target/riscv/cv-mem-sw-compile-1.c|  32 +++
 .../gcc.target/riscv/cv-mem-sw-compile-2.c|  38 +++
 .../gcc.target/riscv/cv-mem-sw-compile-3.c|  30 ++
 gcc/testsuite/lib/target-supports.exp |  13 +
 43 files changed, 1222 insertions(+), 20 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-7.c
 create mode 100644 gcc/testsuite/gcc.t

[PATCH v3 1/1] RISC-V: Add support for XCVmem extension in CV32E40P

[Mary Bennett]

XCVmem adds more loads and stores. To prevent non-XCVmem loads and
stores from generating illegal XCVmem specific operands, constraint
'm' was redefined. 'm' does not accept POST_MODIFY or reg + reg
addresses.

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add the XCVmem
  extension.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/predicates.md: Likewise.
* config/riscv/riscv-protos.h: Likewise.
* config/riscv/riscv.cc: Add POST_MODIFY.
* config/riscv/riscv.h: Likewise.
* config/riscv/riscv.md: Prevent XCVmem operands being
  used in non-XCVmem loads and stores.
* config/riscv/constraints.md: Likewise.
* config/riscv/predicates.md: Likewise.
* doc/sourcebuild.texi: Add XCVmem documentation.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-mem-operand-compile-1.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-2.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-3.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-4.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-5.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-6.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-7.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-8.c: New test.
* gcc.target/riscv/cv-mem-lb-compile-1.c: New test.
* gcc.target/riscv/cv-mem-lb-compile-2.c: New test.
* gcc.target/riscv/cv-mem-lb-compile-3.c: New test.
* gcc.target/riscv/cv-mem-lbu-compile-1.c: New test.
* gcc.target/riscv/cv-mem-lbu-compile-2.c: New test.
* gcc.target/riscv/cv-mem-lbu-compile-3.c: New test.
* gcc.target/riscv/cv-mem-lh-compile-1.c: New test.
* gcc.target/riscv/cv-mem-lh-compile-2.c: New test.
* gcc.target/riscv/cv-mem-lh-compile-3.c: New test.
* gcc.target/riscv/cv-mem-lhu-compile-1.c: New test.
* gcc.target/riscv/cv-mem-lhu-compile-2.c: New test.
* gcc.target/riscv/cv-mem-lhu-compile-3.c: New test.
* gcc.target/riscv/cv-mem-lw-compile-1.c: New test.
* gcc.target/riscv/cv-mem-lw-compile-2.c: New test.
* gcc.target/riscv/cv-mem-lw-compile-3.c: New test.
* gcc.target/riscv/cv-mem-sb-compile-1.c: New test.
* gcc.target/riscv/cv-mem-sb-compile-2.c: New test.
* gcc.target/riscv/cv-mem-sb-compile-3.c: New test.
* gcc.target/riscv/cv-mem-sh-compile-1.c: New test.
* gcc.target/riscv/cv-mem-sh-compile-2.c: New test.
* gcc.target/riscv/cv-mem-sh-compile-3.c: New test.
* gcc.target/riscv/cv-mem-sw-compile-1.c: New test.
* gcc.target/riscv/cv-mem-sw-compile-2.c: New test.
* gcc.target/riscv/cv-mem-sw-compile-3.c: New test.
* lib/target-supports.exp: Add proc for XCVmem.
---
 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |  29 ++
 gcc/config/riscv/corev.md | 270 ++
 gcc/config/riscv/predicates.md|  20 +-
 gcc/config/riscv/riscv-protos.h   |  12 +-
 gcc/config/riscv/riscv.cc |  48 +++-
 gcc/config/riscv/riscv.h  |   4 +-
 gcc/config/riscv/riscv.md |  26 +-
 gcc/config/riscv/riscv.opt|   2 +
 gcc/doc/sourcebuild.texi  |   3 +
 .../gcc.target/riscv/cv-mem-lb-compile-1.c|  21 ++
 .../gcc.target/riscv/cv-mem-lb-compile-2.c|  24 ++
 .../gcc.target/riscv/cv-mem-lb-compile-3.c|  16 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-1.c   |  21 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-2.c   |  24 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-3.c   |  16 ++
 .../gcc.target/riscv/cv-mem-lh-compile-1.c|  21 ++
 .../gcc.target/riscv/cv-mem-lh-compile-2.c|  24 ++
 .../gcc.target/riscv/cv-mem-lh-compile-3.c|  16 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-1.c   |  21 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-2.c   |  24 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-3.c   |  16 ++
 .../gcc.target/riscv/cv-mem-lw-compile-1.c|  33 +++
 .../gcc.target/riscv/cv-mem-lw-compile-2.c|  38 +++
 .../gcc.target/riscv/cv-mem-lw-compile-3.c|  22 ++
 .../riscv/cv-mem-operand-compile-1.c  |  19 ++
 .../riscv/cv-mem-operand-compile-2.c  |  20 ++
 .../riscv/cv-mem-operand-compile-3.c  |  28 ++
 .../riscv/cv-mem-operand-compile-4.c  |  21 ++
 .../riscv/cv-mem-operand-compile-5.c  |  25 ++
 .../riscv/cv-mem-operand-compile-6.c  |  21 ++
 .../riscv/cv-mem-operand-compile-7.c  |  24 ++
 .../

[PATCH v4 1/1] RISC-V: Add support for XCVbitmanip extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add XCVbitmanip.
* config/riscv/constraints.md: Likewise.
* config/riscv/corev.def: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/predicates.md: Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Add XCVbitmanip builtin documentation.
* doc/sourcebuild.texi: Likewise.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bitmanip-compile-bclr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bclrr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bitrev.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bset.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bsetr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-clb.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-cnt.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extract.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extractr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extractu.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extractur.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-ff1.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-fl1.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-insert.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-insertr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-ror.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-bclr.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-bitrev.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-bset.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-extract.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-extractu.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-insert.c: New test.
* lib/target-supports.exp: Add proc for the XCVbitmanip extension.
---
 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |  16 ++
 gcc/config/riscv/corev.def|  13 ++
 gcc/config/riscv/corev.md | 182 ++
 gcc/config/riscv/predicates.md|  16 ++
 gcc/config/riscv/riscv-builtins.cc|   1 +
 gcc/config/riscv/riscv-ftypes.def |   5 +
 gcc/config/riscv/riscv.cc |  13 ++
 gcc/config/riscv/riscv.opt|   2 +
 gcc/doc/extend.texi   |  53 +
 gcc/doc/sourcebuild.texi  |   3 +
 .../riscv/cv-bitmanip-compile-bclr.c  |  27 +++
 .../riscv/cv-bitmanip-compile-bclrr.c |  18 ++
 .../riscv/cv-bitmanip-compile-bitrev.c|  30 +++
 .../riscv/cv-bitmanip-compile-bset.c  |  27 +++
 .../riscv/cv-bitmanip-compile-bsetr.c |  18 ++
 .../riscv/cv-bitmanip-compile-clb.c   |  18 ++
 .../riscv/cv-bitmanip-compile-cnt.c   |  18 ++
 .../riscv/cv-bitmanip-compile-extract.c   |  27 +++
 .../riscv/cv-bitmanip-compile-extractr.c  |  18 ++
 .../riscv/cv-bitmanip-compile-extractu.c  |  27 +++
 .../riscv/cv-bitmanip-compile-extractur.c |  18 ++
 .../riscv/cv-bitmanip-compile-ff1.c   |  18 ++
 .../riscv/cv-bitmanip-compile-fl1.c   |  18 ++
 .../riscv/cv-bitmanip-compile-insert.c|  24 +++
 .../riscv/cv-bitmanip-compile-insertr.c   |  18 ++
 .../riscv/cv-bitmanip-compile-ror.c   |  18 ++
 .../riscv/cv-bitmanip-fail-compile-bclr.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-bitrev.c   |  23 +++
 .../riscv/cv-bitmanip-fail-compile-bset.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-extract.c  |  25 +++
 .../riscv/cv-bitmanip-fail-compile-extractu.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-insert.c   |  25 +++
 gcc/testsuite/lib/target-supports.exp |  13 ++
 34 files changed, 809 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclrr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bitrev.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bset.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bsetr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-clb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-cnt.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extract.c
 create mode 100644

[PATCH v4 0/1] RISC-V: Support CORE-V XCVBITMAIP extension

[Mary Bennett]

This patch series presents the comprehensive implementation of the BITMANIP
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

RISC-V: Add support for XCVbitmanip extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |  16 ++
 gcc/config/riscv/corev.def|  13 ++
 gcc/config/riscv/corev.md | 182 ++
 gcc/config/riscv/predicates.md|  16 ++
 gcc/config/riscv/riscv-builtins.cc|   1 +
 gcc/config/riscv/riscv-ftypes.def |   5 +
 gcc/config/riscv/riscv.cc |  13 ++
 gcc/config/riscv/riscv.opt|   2 +
 gcc/doc/extend.texi   |  53 +
 gcc/doc/sourcebuild.texi  |   3 +
 .../riscv/cv-bitmanip-compile-bclr.c  |  27 +++
 .../riscv/cv-bitmanip-compile-bclrr.c |  18 ++
 .../riscv/cv-bitmanip-compile-bitrev.c|  30 +++
 .../riscv/cv-bitmanip-compile-bset.c  |  27 +++
 .../riscv/cv-bitmanip-compile-bsetr.c |  18 ++
 .../riscv/cv-bitmanip-compile-clb.c   |  18 ++
 .../riscv/cv-bitmanip-compile-cnt.c   |  18 ++
 .../riscv/cv-bitmanip-compile-extract.c   |  27 +++
 .../riscv/cv-bitmanip-compile-extractr.c  |  18 ++
 .../riscv/cv-bitmanip-compile-extractu.c  |  27 +++
 .../riscv/cv-bitmanip-compile-extractur.c |  18 ++
 .../riscv/cv-bitmanip-compile-ff1.c   |  18 ++
 .../riscv/cv-bitmanip-compile-fl1.c   |  18 ++
 .../riscv/cv-bitmanip-compile-insert.c|  24 +++
 .../riscv/cv-bitmanip-compile-insertr.c   |  18 ++
 .../riscv/cv-bitmanip-compile-ror.c   |  18 ++
 .../riscv/cv-bitmanip-fail-compile-bclr.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-bitrev.c   |  23 +++
 .../riscv/cv-bitmanip-fail-compile-bset.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-extract.c  |  25 +++
 .../riscv/cv-bitmanip-fail-compile-extractu.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-insert.c   |  25 +++
 gcc/testsuite/lib/target-supports.exp |  13 ++
 34 files changed, 809 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclrr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bitrev.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bset.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bsetr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-clb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-cnt.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extract.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extractr.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extractu.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extractur.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-ff1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-fl1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-insert.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-insertr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-ror.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-bclr.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-bitrev.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-bset.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-extract.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-extractu.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-insert.c

-- 
2.34.1

[PATCH v5 0/1] RISC-V: Support CORE-V XCVBI extension

[Mary Bennett]

Thank you for reviewing my patches and merging XCVelw.

This patch series presents the comprehensive implementation of the BI
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

RISC-V: Add support for XCVbi extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |  4 ++
 gcc/config/riscv/constraints.md   | 21 +---
 gcc/config/riscv/corev.def|  3 ++
 gcc/config/riscv/corev.md | 51 ++-
 gcc/config/riscv/predicates.md|  4 ++
 gcc/config/riscv/riscv.md |  2 +-
 gcc/config/riscv/riscv.opt|  2 +
 gcc/doc/sourcebuild.texi  |  3 ++
 .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++
 gcc/testsuite/lib/target-supports.exp | 13 +
 12 files changed, 198 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c

-- 
2.34.1

[PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Create XCVbi extension
  support.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Implement cv_branch pattern
  for cv.beqimm and cv.bneimm.
* config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
  branch instruction pattern.
* config/riscv/constraints.md: Implement constraints
  cv_bi_s5 - signed 5-bit immediate.
* config/riscv/predicates.md: Implement predicate
  const_int5s_operand - signed 5 bit immediate.
* doc/sourcebuild.texi: Add XCVbi documentation.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
* lib/target-supports.exp: Add proc for XCVbi.
---
 gcc/common/config/riscv/riscv-common.cc   |  2 +
 gcc/config/riscv/constraints.md   |  6 +++
 gcc/config/riscv/corev.md | 37 ++
 gcc/config/riscv/predicates.md|  4 ++
 gcc/config/riscv/riscv.md |  2 +-
 gcc/config/riscv/riscv.opt|  2 +
 gcc/doc/sourcebuild.texi  |  3 ++
 .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++
 gcc/testsuite/lib/target-supports.exp | 13 +
 12 files changed, 198 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0301d170a41..d61164a42b9 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -355,6 +355,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1730,6 +1731,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"xcvmac",&gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
   {"xcvalu",&gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
   {"xcvelw",&gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
+  {"xcvbi", &gcc_options::x_riscv_xcv_subext, MASK_XCVBI},
 
   {"xtheadba",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
   {"xtheadbb",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index ee1c12b2e51..e4bfa227a2f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -262,3 +262,9 @@
   (and (match_code "const_int")
(and (match_test "IN_RANGE (ival, 0, 1073741823)")
 (match_test "exact_log2 (ival + 1) != -1"
+
+(define_constraint "CV_bi_sign5"
+  "@internal
+   A 5-bit signed immediate for CORE-V Immediate Branch."
+  (and (match_code "const_int")
+   (match_test "IN_RANGE (ival, -16, 15)")))
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index adad2409fb6..66e0e998e41 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -706,3 +706,40 @@
 
   [(set_attr "type" "load")
   (set_attr "mode" "SI")])
+
+;; XCVBI Instructions
+(define_insn "*cv_branch"
+  [(set (pc)
+   (if_then_else
+(match_operator 1 "equality_operator"
+[(match_operand:X 2 "register_operand" "r")
+ (match_operand:X 3 "const_int5s_operand" 
"CV_bi_sign5")])
+(label_ref (match_operand 0 "" ""))
+(pc)))]
+  "TARGET_XCVBI"
+{
+  if (get_attr_length (insn) == 12)
+return "cv.b%N1\t%2,%z3,1f; jump\t%

[PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add XCVelw.
* config/riscv/corev.def: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Add XCVelw builtin documentation.
* doc/sourcebuild.texi: Likewise.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-elw-compile-1.c: Create test for cv.elw.
* testsuite/lib/target-supports.exp: Add proc for the XCVelw extension.
---
 gcc/common/config/riscv/riscv-common.cc   |  2 ++
 gcc/config/riscv/corev.def|  3 +++
 gcc/config/riscv/corev.md | 15 +++
 gcc/config/riscv/riscv-builtins.cc|  2 ++
 gcc/config/riscv/riscv-ftypes.def |  1 +
 gcc/config/riscv/riscv.opt|  2 ++
 gcc/doc/extend.texi   |  8 
 gcc/doc/sourcebuild.texi  |  3 +++
 .../gcc.target/riscv/cv-elw-elw-compile-1.c   | 11 +++
 gcc/testsuite/lib/target-supports.exp | 13 +
 10 files changed, 60 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 5111626157b..c8c0d0a2252 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -312,6 +312,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1676,6 +1677,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"xcvmac",&gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
   {"xcvalu",&gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
+  {"xcvelw",&gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
 
   {"xtheadba",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
   {"xtheadbb",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/corev.def b/gcc/config/riscv/corev.def
index 17580df3c41..3b9ec029d06 100644
--- a/gcc/config/riscv/corev.def
+++ b/gcc/config/riscv/corev.def
@@ -41,3 +41,6 @@ RISCV_BUILTIN (cv_alu_subN, "cv_alu_subN", 
RISCV_BUILTIN_DIRECT, RISCV_SI_FT
 RISCV_BUILTIN (cv_alu_subuN,"cv_alu_subuN", RISCV_BUILTIN_DIRECT, 
RISCV_USI_FTYPE_USI_USI_UQI,  cvalu),
 RISCV_BUILTIN (cv_alu_subRN,"cv_alu_subRN", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI_SI_UQI, cvalu),
 RISCV_BUILTIN (cv_alu_subuRN,   "cv_alu_subuRN",RISCV_BUILTIN_DIRECT, 
RISCV_USI_FTYPE_USI_USI_UQI,  cvalu),
+
+// XCVELW
+RISCV_BUILTIN (cv_elw_elw_si, "cv_elw_elw", RISCV_BUILTIN_DIRECT, 
RISCV_USI_FTYPE_VOID_PTR, cvelw),
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 1350bd4b81e..c7a2ba07bcc 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -24,6 +24,9 @@
   UNSPEC_CV_ALU_CLIPR
   UNSPEC_CV_ALU_CLIPU
   UNSPEC_CV_ALU_CLIPUR
+
+  ;;CORE-V EVENT LOAD
+  UNSPECV_CV_ELW
 ])
 
 ;; XCVMAC extension.
@@ -691,3 +694,15 @@
   cv.suburnr\t%0,%2,%3"
   [(set_attr "type" "arith")
   (set_attr "mode" "SI")])
+
+;; XCVELW builtins
+(define_insn "riscv_cv_elw_elw_si"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+   (unspec_volatile [(match_operand:SI 1 "move_operand" "p")]
+ UNSPECV_CV_ELW))]
+
+  "TARGET_XCVELW && !TARGET_64BIT"
+  "cv.elw\t%0,%a1"
+
+  [(set_attr "type" "load")
+  (set_attr "mode" "SI")])
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index fc3976f3ba1..5ee11ebe3bc 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -128,6 +128,7 @@ AVAIL (hint_pause, (!0))
 // CORE-V AVAIL
 AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT)
 AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
+AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT)
 
 /* Construct a riscv_builtin_description from the given arguments.
 
@@ -168,6 +169,7 @@ AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
 #define RISCV_ATYPE_HI intHI_type_node
 #define 

[PATCH v4 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions

[Mary Bennett]

Thank you for reviewing my patches!

v1 -> v2:
  * Bring the MEM into the operand for cv.elw. The new predicate is
move_operand.
  * Add comment to riscv.md detailing why corev.md must appear before
the generic riscv instructions.

v2 -> v3:
  * Merge patterns for CORE-V branch immediate and generic RISC-V so to
supress the generic patterns if XCVbi is available.

v3 -> v4:
  * Add duplicate content of "*branch" to corev.md.

This patch series presents the comprehensive implementation of the ELW and BI
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

RISC-V: Update XCValu constraints to match other vendors
RISC-V: Add support for XCVelw extension in CV32E40P
RISC-V: Add support for XCVbi extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |  4 ++
 gcc/config/riscv/constraints.md   | 21 +---
 gcc/config/riscv/corev.def|  3 ++
 gcc/config/riscv/corev.md | 51 ++-
 gcc/config/riscv/predicates.md|  4 ++
 gcc/config/riscv/riscv-builtins.cc|  2 +
 gcc/config/riscv/riscv-ftypes.def |  1 +
 gcc/config/riscv/riscv.md |  2 +-
 gcc/config/riscv/riscv.opt|  4 ++
 gcc/doc/extend.texi   |  8 +++
 gcc/doc/sourcebuild.texi  |  6 +++
 .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +
 .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +
 .../gcc.target/riscv/cv-elw-elw-compile-1.c   | 11 
 gcc/testsuite/lib/target-supports.exp | 26 ++
 17 files changed, 263 insertions(+), 10 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c

-- 
2.34.1

[PATCH v4 2/3] RISC-V: Update XCValu constraints to match other vendors

[Mary Bennett]

gcc/ChangeLog:
* config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
* config/riscv/corev.md: Likewise.
---
 gcc/config/riscv/constraints.md | 15 ---
 gcc/config/riscv/corev.md   |  4 ++--
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 68be4515c04..2711efe68c5 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -151,13 +151,6 @@
 (define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? GR_REGS 
: NO_REGS"
   "An integer register for  ZFA or XTheadFmv.")
 
-;; CORE-V Constraints
-(define_constraint "CVP2"
-  "Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
-  (and (match_code "const_int")
-   (and (match_test "IN_RANGE (ival, 0, 1073741823)")
-(match_test "exact_log2 (ival + 1) != -1"
-
 ;; Vector constraints.
 
 (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS"
@@ -246,3 +239,11 @@
A MEM with a valid address for th.[l|s]*ur* instructions."
   (and (match_code "mem")
(match_test "th_memidx_legitimate_index_p (op, true)")))
+
+;; CORE-V Constraints
+(define_constraint "CV_alu_pow2"
+  "@internal
+   Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
+  (and (match_code "const_int")
+   (and (match_test "IN_RANGE (ival, 0, 1073741823)")
+(match_test "exact_log2 (ival + 1) != -1"
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index c7a2ba07bcc..92bf0b5d6a6 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -516,7 +516,7 @@
 (define_insn "riscv_cv_alu_clip"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
-   (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
+   (match_operand:SI 2 "immediate_register_operand" 
"CV_alu_pow2,r")]
 UNSPEC_CV_ALU_CLIP))]
 
   "TARGET_XCVALU && !TARGET_64BIT"
@@ -529,7 +529,7 @@
 (define_insn "riscv_cv_alu_clipu"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
-   (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
+   (match_operand:SI 2 "immediate_register_operand" 
"CV_alu_pow2,r")]
 UNSPEC_CV_ALU_CLIPU))]
 
   "TARGET_XCVALU && !TARGET_64BIT"
-- 
2.34.1

[PATCH v4 3/3] RISC-V: Add support for XCVbi extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Create XCVbi extension
  support.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Implement cv_branch pattern
  for cv.beqimm and cv.bneimm.
* config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
  branch instruction pattern.
* config/riscv/constraints.md: Implement constraints
  cv_bi_s5 - signed 5-bit immediate.
* config/riscv/predicates.md: Implement predicate
  const_int5s_operand - signed 5 bit immediate.
* doc/sourcebuild.texi: Add XCVbi documentation.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
* lib/target-supports.exp: Add proc for XCVbi.
---
 gcc/common/config/riscv/riscv-common.cc   |  2 +
 gcc/config/riscv/constraints.md   |  6 +++
 gcc/config/riscv/corev.md | 32 +
 gcc/config/riscv/predicates.md|  4 ++
 gcc/config/riscv/riscv.md |  2 +-
 gcc/config/riscv/riscv.opt|  2 +
 gcc/doc/sourcebuild.texi  |  3 ++
 .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++
 gcc/testsuite/lib/target-supports.exp | 13 +
 12 files changed, 193 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index c8c0d0a2252..125f8fb71f7 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -313,6 +313,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1678,6 +1679,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"xcvmac",&gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
   {"xcvalu",&gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
   {"xcvelw",&gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
+  {"xcvbi", &gcc_options::x_riscv_xcv_subext, MASK_XCVBI},
 
   {"xtheadba",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
   {"xtheadbb",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 2711efe68c5..718b4bd77df 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -247,3 +247,9 @@
   (and (match_code "const_int")
(and (match_test "IN_RANGE (ival, 0, 1073741823)")
 (match_test "exact_log2 (ival + 1) != -1"
+
+(define_constraint "CV_bi_sign5"
+  "@internal
+   A 5-bit signed immediate for CORE-V Immediate Branch."
+  (and (match_code "const_int")
+   (match_test "IN_RANGE (ival, -16, 15)")))
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 92bf0b5d6a6..92e30a8ae04 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -706,3 +706,35 @@
 
   [(set_attr "type" "load")
   (set_attr "mode" "SI")])
+
+;; XCVBI Instructions
+(define_insn "cv_branch"
+  [(set (pc)
+   (if_then_else
+(match_operator 1 "equality_operator"
+[(match_operand:X 2 "register_operand" "r")
+ (match_operand:X 3 "const_int5s_operand" 
"CV_bi_sign5")])
+(label_ref (match_operand 0 "" ""))
+(pc)))]
+  "TARGET_XCVBI"
+  "cv.b%C1imm\t%2,%3,%0"
+  [(set_attr "type" "branch")
+

[PATCH 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions

[Mary Bennett]

This patch series presents the comprehensive implementation of the ELW and BI
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

RISC-V: Update XCValu constraints to match other vendors
RISC-V: Add support for XCVelw extension in CV32E40P
RISC-V: Add support for XCVbi extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |  4 ++
 gcc/config/riscv/constraints.md   | 21 +---
 gcc/config/riscv/corev.def|  3 ++
 gcc/config/riscv/corev.md | 33 -
 gcc/config/riscv/predicates.md|  4 ++
 gcc/config/riscv/riscv-builtins.cc|  2 +
 gcc/config/riscv/riscv-ftypes.def |  1 +
 gcc/config/riscv/riscv.md |  9 +++-
 gcc/config/riscv/riscv.opt|  4 ++
 gcc/doc/extend.texi   |  8 
 gcc/doc/sourcebuild.texi  |  6 +++
 .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++
 .../gcc.target/riscv/cv-elw-elw-compile-1.c   | 11 +
 gcc/testsuite/lib/target-supports.exp | 26 ++
 17 files changed, 252 insertions(+), 10 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c

-- 
2.34.1

[PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add XCVelw.
* config/riscv/corev.def: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Add XCVelw builtin documentation.
* doc/sourcebuild.texi: Likewise.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-elw-compile-1.c: Create test for cv.elw.
* testsuite/lib/target-supports.exp: Add proc for the XCVelw extension.
---
 gcc/common/config/riscv/riscv-common.cc   |  2 ++
 gcc/config/riscv/corev.def|  3 +++
 gcc/config/riscv/corev.md | 15 +++
 gcc/config/riscv/riscv-builtins.cc|  2 ++
 gcc/config/riscv/riscv-ftypes.def |  1 +
 gcc/config/riscv/riscv.opt|  2 ++
 gcc/doc/extend.texi   |  8 
 gcc/doc/sourcebuild.texi  |  3 +++
 .../gcc.target/riscv/cv-elw-elw-compile-1.c   | 11 +++
 gcc/testsuite/lib/target-supports.exp | 13 +
 10 files changed, 60 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 526dbb7603b..6a1978bd0e4 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -312,6 +312,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1667,6 +1668,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"xcvmac",&gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
   {"xcvalu",&gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
+  {"xcvelw",&gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
 
   {"xtheadba",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
   {"xtheadbb",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/corev.def b/gcc/config/riscv/corev.def
index 17580df3c41..3b9ec029d06 100644
--- a/gcc/config/riscv/corev.def
+++ b/gcc/config/riscv/corev.def
@@ -41,3 +41,6 @@ RISCV_BUILTIN (cv_alu_subN, "cv_alu_subN", 
RISCV_BUILTIN_DIRECT, RISCV_SI_FT
 RISCV_BUILTIN (cv_alu_subuN,"cv_alu_subuN", RISCV_BUILTIN_DIRECT, 
RISCV_USI_FTYPE_USI_USI_UQI,  cvalu),
 RISCV_BUILTIN (cv_alu_subRN,"cv_alu_subRN", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI_SI_UQI, cvalu),
 RISCV_BUILTIN (cv_alu_subuRN,   "cv_alu_subuRN",RISCV_BUILTIN_DIRECT, 
RISCV_USI_FTYPE_USI_USI_UQI,  cvalu),
+
+// XCVELW
+RISCV_BUILTIN (cv_elw_elw_si, "cv_elw_elw", RISCV_BUILTIN_DIRECT, 
RISCV_USI_FTYPE_VOID_PTR, cvelw),
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 1350bd4b81e..be66b1428a7 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -24,6 +24,9 @@
   UNSPEC_CV_ALU_CLIPR
   UNSPEC_CV_ALU_CLIPU
   UNSPEC_CV_ALU_CLIPUR
+
+  ;;CORE-V EVENT LOAD
+  UNSPECV_CV_ELW
 ])
 
 ;; XCVMAC extension.
@@ -691,3 +694,15 @@
   cv.suburnr\t%0,%2,%3"
   [(set_attr "type" "arith")
   (set_attr "mode" "SI")])
+
+;; XCVELW builtins
+(define_insn "riscv_cv_elw_elw_si"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+  (unspec_volatile [(mem:SI (match_operand:SI 1 "address_operand" "p"))]
+  UNSPECV_CV_ELW))]
+
+  "TARGET_XCVELW && !TARGET_64BIT"
+  "cv.elw\t%0,%a1"
+
+  [(set_attr "type" "load")
+  (set_attr "mode" "SI")])
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index fc3976f3ba1..5ee11ebe3bc 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -128,6 +128,7 @@ AVAIL (hint_pause, (!0))
 // CORE-V AVAIL
 AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT)
 AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
+AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT)
 
 /* Construct a riscv_builtin_description from the given arguments.
 
@@ -168,6 +169,7 @@ AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
 #define RISCV_ATYPE_HI intHI_type_n

[PATCH 2/3] RISC-V: Update XCValu constraints to match other vendors

[Mary Bennett]

gcc/ChangeLog:
* config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
* config/riscv/corev.md: Likewise.
---
 gcc/config/riscv/constraints.md | 15 ---
 gcc/config/riscv/corev.md   |  4 ++--
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 68be4515c04..2711efe68c5 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -151,13 +151,6 @@
 (define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? GR_REGS 
: NO_REGS"
   "An integer register for  ZFA or XTheadFmv.")
 
-;; CORE-V Constraints
-(define_constraint "CVP2"
-  "Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
-  (and (match_code "const_int")
-   (and (match_test "IN_RANGE (ival, 0, 1073741823)")
-(match_test "exact_log2 (ival + 1) != -1"
-
 ;; Vector constraints.
 
 (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS"
@@ -246,3 +239,11 @@
A MEM with a valid address for th.[l|s]*ur* instructions."
   (and (match_code "mem")
(match_test "th_memidx_legitimate_index_p (op, true)")))
+
+;; CORE-V Constraints
+(define_constraint "CV_alu_pow2"
+  "@internal
+   Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
+  (and (match_code "const_int")
+   (and (match_test "IN_RANGE (ival, 0, 1073741823)")
+(match_test "exact_log2 (ival + 1) != -1"
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index be66b1428a7..0109e1836cf 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -516,7 +516,7 @@
 (define_insn "riscv_cv_alu_clip"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
-   (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
+   (match_operand:SI 2 "immediate_register_operand" 
"CV_alu_pow2,r")]
 UNSPEC_CV_ALU_CLIP))]
 
   "TARGET_XCVALU && !TARGET_64BIT"
@@ -529,7 +529,7 @@
 (define_insn "riscv_cv_alu_clipu"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
-   (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
+   (match_operand:SI 2 "immediate_register_operand" 
"CV_alu_pow2,r")]
 UNSPEC_CV_ALU_CLIPU))]
 
   "TARGET_XCVALU && !TARGET_64BIT"
-- 
2.34.1

[PATCH 3/3] RISC-V: Add support for XCVbi extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 


gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Create XCVbi extension
  support.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Implement cv_branch pattern
  for cv.beqimm and cv.bneimm.
* config/riscv/riscv.md: Change pattern priority so corev.md
  patterns run before riscv.md patterns.
* config/riscv/constraints.md: Implement constraints
  cv_bi_s5 - signed 5-bit immediate.
* config/riscv/predicates.md: Implement predicate
  const_int5s_operand - signed 5 bit immediate.
* doc/sourcebuild.texi: Add XCVbi documentation.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
* lib/target-supports.exp: Add proc for XCVbi.
---
 gcc/common/config/riscv/riscv-common.cc   |  2 +
 gcc/config/riscv/constraints.md   |  6 +++
 gcc/config/riscv/corev.md | 14 ++
 gcc/config/riscv/predicates.md|  4 ++
 gcc/config/riscv/riscv.md |  9 +++-
 gcc/config/riscv/riscv.opt|  2 +
 gcc/doc/sourcebuild.texi  |  3 ++
 .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++
 gcc/testsuite/lib/target-supports.exp | 13 +
 12 files changed, 182 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 6a1978bd0e4..04631e007f0 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -313,6 +313,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1669,6 +1670,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"xcvmac",&gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
   {"xcvalu",&gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
   {"xcvelw",&gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
+  {"xcvbi", &gcc_options::x_riscv_xcv_subext, MASK_XCVBI},
 
   {"xtheadba",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
   {"xtheadbb",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 2711efe68c5..718b4bd77df 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -247,3 +247,9 @@
   (and (match_code "const_int")
(and (match_test "IN_RANGE (ival, 0, 1073741823)")
 (match_test "exact_log2 (ival + 1) != -1"
+
+(define_constraint "CV_bi_sign5"
+  "@internal
+   A 5-bit signed immediate for CORE-V Immediate Branch."
+  (and (match_code "const_int")
+   (match_test "IN_RANGE (ival, -16, 15)")))
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 0109e1836cf..7d7b952d817 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -706,3 +706,17 @@
 
   [(set_attr "type" "load")
   (set_attr "mode" "SI")])
+
+;; XCVBI Builtins
+(define_insn "cv_branch"
+  [(set (pc)
+   (if_then_else
+(match_operator 1 "equality_operator"
+[(match_operand:X 2 "register_operand" "r")
+ (match_operand:X 3 "const_int5s_operand" 
"CV_bi_sign5")])
+(label_ref (match_operand 0 "" ""))
+(pc)))]
+  "TARGET_XCVBI"
+  "cv.b%C1imm\t%2,%3,%0"
+  [(set_attr "type" "branch")
+   (set_

[PATCH 0/1] RISC-V: Support CORE-V XCVBITMAIP extension

[Mary Bennett]

This patch series presents the comprehensive implementation of the BITMANIP
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

RISC-V: Add support for XCVbitmanip extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |   5 +
 gcc/config/riscv/corev.def|  13 +
 gcc/config/riscv/corev.md | 342 ++
 gcc/config/riscv/predicates.md|  16 +
 gcc/config/riscv/riscv-builtins.cc|   1 +
 gcc/config/riscv/riscv-ftypes.def |   5 +
 gcc/config/riscv/riscv.opt|   2 +
 gcc/doc/extend.texi   |  53 +++
 gcc/doc/sourcebuild.texi  |   3 +
 .../riscv/cv-bitmanip-compile-bclr.c  |  27 ++
 .../riscv/cv-bitmanip-compile-bclrr.c |  18 +
 .../riscv/cv-bitmanip-compile-bitrev.c|  30 ++
 .../riscv/cv-bitmanip-compile-bset.c  |  27 ++
 .../riscv/cv-bitmanip-compile-bsetr.c |  18 +
 .../riscv/cv-bitmanip-compile-clb.c   |  18 +
 .../riscv/cv-bitmanip-compile-cnt.c   |  18 +
 .../riscv/cv-bitmanip-compile-extract.c   |  27 ++
 .../riscv/cv-bitmanip-compile-extractr.c  |  18 +
 .../riscv/cv-bitmanip-compile-extractu.c  |  27 ++
 .../riscv/cv-bitmanip-compile-extractur.c |  18 +
 .../riscv/cv-bitmanip-compile-ff1.c   |  18 +
 .../riscv/cv-bitmanip-compile-fl1.c   |  18 +
 .../riscv/cv-bitmanip-compile-insert.c|  24 ++
 .../riscv/cv-bitmanip-compile-insertr.c   |  18 +
 .../riscv/cv-bitmanip-compile-ror.c   |  18 +
 .../riscv/cv-bitmanip-fail-compile-bclr.c |  25 ++
 .../riscv/cv-bitmanip-fail-compile-bitrev.c   |  23 ++
 .../riscv/cv-bitmanip-fail-compile-bset.c |  25 ++
 .../riscv/cv-bitmanip-fail-compile-extract.c  |  25 ++
 .../riscv/cv-bitmanip-fail-compile-extractu.c |  25 ++
 .../riscv/cv-bitmanip-fail-compile-insert.c   |  22 ++
 gcc/testsuite/lib/target-supports.exp |  13 +
 33 files changed, 942 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclrr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bitrev.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bset.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bsetr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-clb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-cnt.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extract.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extractr.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extractu.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extractur.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-ff1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-fl1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-insert.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-insertr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-ror.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-bclr.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-bitrev.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-bset.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-extract.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-extractu.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-insert.c

-- 
2.34.1

[PATCH 1/1] RISC-V: Add support for XCVbitmanip extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add XCVbitmanip.
* config/riscv/constraints.md: Likewise.
* config/riscv/corev.def: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/predicates.md: Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Add XCVbitmanip builtin documentation.
* doc/sourcebuild.texi: Likewise.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bitmanip-compile-bclr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bclrr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bitrev.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bset.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bsetr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-clb.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-cnt.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extract.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extractr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extractu.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extractur.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-ff1.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-fl1.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-insert.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-insertr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-ror.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-bclr.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-bitrev.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-bset.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-extract.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-extractu.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-insert.c: New test.
* lib/target-supports.exp: Add proc for the XCVbitmanip extension.
---
 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |   5 +
 gcc/config/riscv/corev.def|  13 +
 gcc/config/riscv/corev.md | 342 ++
 gcc/config/riscv/predicates.md|  16 +
 gcc/config/riscv/riscv-builtins.cc|   1 +
 gcc/config/riscv/riscv-ftypes.def |   5 +
 gcc/config/riscv/riscv.opt|   2 +
 gcc/doc/extend.texi   |  53 +++
 gcc/doc/sourcebuild.texi  |   3 +
 .../riscv/cv-bitmanip-compile-bclr.c  |  27 ++
 .../riscv/cv-bitmanip-compile-bclrr.c |  18 +
 .../riscv/cv-bitmanip-compile-bitrev.c|  30 ++
 .../riscv/cv-bitmanip-compile-bset.c  |  27 ++
 .../riscv/cv-bitmanip-compile-bsetr.c |  18 +
 .../riscv/cv-bitmanip-compile-clb.c   |  18 +
 .../riscv/cv-bitmanip-compile-cnt.c   |  18 +
 .../riscv/cv-bitmanip-compile-extract.c   |  27 ++
 .../riscv/cv-bitmanip-compile-extractr.c  |  18 +
 .../riscv/cv-bitmanip-compile-extractu.c  |  27 ++
 .../riscv/cv-bitmanip-compile-extractur.c |  18 +
 .../riscv/cv-bitmanip-compile-ff1.c   |  18 +
 .../riscv/cv-bitmanip-compile-fl1.c   |  18 +
 .../riscv/cv-bitmanip-compile-insert.c|  24 ++
 .../riscv/cv-bitmanip-compile-insertr.c   |  18 +
 .../riscv/cv-bitmanip-compile-ror.c   |  18 +
 .../riscv/cv-bitmanip-fail-compile-bclr.c |  25 ++
 .../riscv/cv-bitmanip-fail-compile-bitrev.c   |  23 ++
 .../riscv/cv-bitmanip-fail-compile-bset.c |  25 ++
 .../riscv/cv-bitmanip-fail-compile-extract.c  |  25 ++
 .../riscv/cv-bitmanip-fail-compile-extractu.c |  25 ++
 .../riscv/cv-bitmanip-fail-compile-insert.c   |  22 ++
 gcc/testsuite/lib/target-supports.exp |  13 +
 33 files changed, 942 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclrr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bitrev.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bset.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bsetr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-clb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-cnt.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extract.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extractr.c
 create mode 100644

[PATCH 0/1] RISC-V: Support CORE-V XCVSIMD extension

[Mary Bennett]

This patch series presents the comprehensive implementation of the SIMD
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

RISC-V: Add support for XCVsimd extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |2 +
 gcc/config/riscv/constraints.md   |   30 +
 gcc/config/riscv/corev.def|  156 ++
 gcc/config/riscv/corev.md | 1908 +
 gcc/config/riscv/predicates.md|   20 +
 gcc/config/riscv/riscv-builtins.cc|1 +
 gcc/config/riscv/riscv-ftypes.def |9 +
 gcc/config/riscv/riscv.cc |8 +
 gcc/config/riscv/riscv.opt|2 +
 gcc/doc/extend.texi   |  886 
 gcc/doc/sourcebuild.texi  |3 +
 .../riscv/cv-simd-abs-b-compile-1.c   |   11 +
 .../riscv/cv-simd-abs-h-compile-1.c   |   11 +
 .../riscv/cv-simd-add-b-compile-1.c   |   11 +
 .../riscv/cv-simd-add-div2-compile-1.c|   11 +
 .../riscv/cv-simd-add-div4-compile-1.c|   11 +
 .../riscv/cv-simd-add-div8-compile-1.c|   11 +
 .../riscv/cv-simd-add-h-compile-1.c   |   11 +
 .../riscv/cv-simd-add-sc-b-compile-1.c|   30 +
 .../riscv/cv-simd-add-sc-h-compile-1.c|   30 +
 .../riscv/cv-simd-and-b-compile-1.c   |   11 +
 .../riscv/cv-simd-and-h-compile-1.c   |   11 +
 .../riscv/cv-simd-and-sc-b-compile-1.c|   30 +
 .../riscv/cv-simd-and-sc-h-compile-1.c|   30 +
 .../riscv/cv-simd-avg-b-compile-1.c   |   11 +
 .../riscv/cv-simd-avg-h-compile-1.c   |   11 +
 .../riscv/cv-simd-avg-sc-b-compile-1.c|   30 +
 .../riscv/cv-simd-avg-sc-h-compile-1.c|   30 +
 .../riscv/cv-simd-avgu-b-compile-1.c  |   11 +
 .../riscv/cv-simd-avgu-h-compile-1.c  |   11 +
 .../riscv/cv-simd-avgu-sc-b-compile-1.c   |   24 +
 .../riscv/cv-simd-avgu-sc-h-compile-1.c   |   24 +
 .../riscv/cv-simd-cmpeq-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmpeq-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmpeq-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpeq-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpge-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmpge-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmpge-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpge-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpgeu-b-compile-1.c|   11 +
 .../riscv/cv-simd-cmpgeu-h-compile-1.c|   11 +
 .../riscv/cv-simd-cmpgeu-sc-b-compile-1.c |   24 +
 .../riscv/cv-simd-cmpgeu-sc-h-compile-1.c |   24 +
 .../riscv/cv-simd-cmpgt-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmpgt-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmpgt-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpgt-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpgtu-b-compile-1.c|   11 +
 .../riscv/cv-simd-cmpgtu-h-compile-1.c|   11 +
 .../riscv/cv-simd-cmpgtu-sc-b-compile-1.c |   24 +
 .../riscv/cv-simd-cmpgtu-sc-h-compile-1.c |   24 +
 .../riscv/cv-simd-cmple-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmple-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmple-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmple-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpleu-b-compile-1.c|   11 +
 .../riscv/cv-simd-cmpleu-h-compile-1.c|   11 +
 .../riscv/cv-simd-cmpleu-sc-b-compile-1.c |   24 +
 .../riscv/cv-simd-cmpleu-sc-h-compile-1.c |   24 +
 .../riscv/cv-simd-cmplt-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmplt-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmplt-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmplt-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpltu-b-compile-1.c|   11 +
 .../riscv/cv-simd-cmpltu-h-compile-1.c|   11 +
 .../riscv/cv-simd-cmpltu-sc-b-compile-1.c |   24 +
 .../riscv/cv-simd-cmpltu-sc-h-compile-1.c |   24 +
 .../riscv/cv-simd-cmpne-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmpne-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmpne-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpne-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cplxconj-compile-1.c|   11 +
 .../riscv/cv-simd-cplxmul-i-compile-1.c   |

[PATCH 0/1] RISC-V: Support CORE-V XCVMEM extension

[Mary Bennett]

This patch series presents the comprehensive implementation of the MEM
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

RISC-V: Add support for XCVmem extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |  28 +++
 gcc/config/riscv/corev.md | 227 ++
 gcc/config/riscv/predicates.md|  20 +-
 gcc/config/riscv/riscv-protos.h   |  12 +-
 gcc/config/riscv/riscv.cc |  48 +++-
 gcc/config/riscv/riscv.h  |   6 +-
 gcc/config/riscv/riscv.md |  46 ++--
 gcc/config/riscv/riscv.opt|   2 +
 gcc/doc/sourcebuild.texi  |   3 +
 .../gcc.target/riscv/cv-mem-lb-compile-1.c|  23 ++
 .../gcc.target/riscv/cv-mem-lb-compile-2.c|  24 ++
 .../gcc.target/riscv/cv-mem-lb-compile-3.c|  16 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-1.c   |  23 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-2.c   |  24 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-3.c   |  16 ++
 .../gcc.target/riscv/cv-mem-lh-compile-1.c|  23 ++
 .../gcc.target/riscv/cv-mem-lh-compile-2.c|  24 ++
 .../gcc.target/riscv/cv-mem-lh-compile-3.c|  16 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-1.c   |  23 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-2.c   |  24 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-3.c   |  16 ++
 .../gcc.target/riscv/cv-mem-lw-compile-1.c|  38 +++
 .../gcc.target/riscv/cv-mem-lw-compile-2.c|  38 +++
 .../gcc.target/riscv/cv-mem-lw-compile-3.c|  22 ++
 .../riscv/cv-mem-operand-compile-1.c  |  19 ++
 .../riscv/cv-mem-operand-compile-2.c  |  20 ++
 .../riscv/cv-mem-operand-compile-3.c  |  28 +++
 .../riscv/cv-mem-operand-compile-4.c  |  21 ++
 .../riscv/cv-mem-operand-compile-5.c  |  25 ++
 .../riscv/cv-mem-operand-compile-6.c  |  21 ++
 .../riscv/cv-mem-operand-compile-7.c  |  24 ++
 .../riscv/cv-mem-operand-compile-8.c  |  18 ++
 .../gcc.target/riscv/cv-mem-sb-compile-1.c|  36 +++
 .../gcc.target/riscv/cv-mem-sb-compile-2.c|  38 +++
 .../gcc.target/riscv/cv-mem-sb-compile-3.c|  30 +++
 .../gcc.target/riscv/cv-mem-sh-compile-1.c|  36 +++
 .../gcc.target/riscv/cv-mem-sh-compile-2.c|  38 +++
 .../gcc.target/riscv/cv-mem-sh-compile-3.c|  30 +++
 .../gcc.target/riscv/cv-mem-sw-compile-1.c|  36 +++
 .../gcc.target/riscv/cv-mem-sw-compile-2.c|  38 +++
 .../gcc.target/riscv/cv-mem-sw-compile-3.c|  30 +++
 gcc/testsuite/lib/target-supports.exp |  14 ++
 43 files changed, 1216 insertions(+), 30 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-7.c
 create mode 100644 gcc/test

[PATCH 1/1] RISC-V: Add support for XCVmem extension in CV32E40P

[Mary Bennett]

XCVmem adds more loads and stores. To prevent non-XCVmem loads and
stores from generating illegal XCVmem specific operands, constraint
'm' was redefined. 'm' does not accept POST_MODIFY or reg + reg
addresses.

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add the XCVmem
  extension.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/predicates.md: Likewise.
* config/riscv/riscv-protos.h: Likewise.
* config/riscv/riscv.cc: Add POST_MODIFY.
* config/riscv/riscv.h: Likewise.
* config/riscv/riscv.md: Prevent XCVmem operands being
  used in non-XCVmem loads and stores.
* config/riscv/constraints.md: Likewise.
* config/riscv/predicates.md: Likewise.
* doc/sourcebuild.texi: Add XCVmem documentation.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-mem-operand-compile-1.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-2.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-3.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-4.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-5.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-6.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-7.c: New test.
* gcc.target/riscv/cv-mem-operand-compile-8.c: New test.
* gcc.target/riscv/cv-mem-lb-compile-1.c: New test.
* gcc.target/riscv/cv-mem-lb-compile-2.c: New test.
* gcc.target/riscv/cv-mem-lb-compile-3.c: New test.
* gcc.target/riscv/cv-mem-lbu-compile-1.c: New test.
* gcc.target/riscv/cv-mem-lbu-compile-2.c: New test.
* gcc.target/riscv/cv-mem-lbu-compile-3.c: New test.
* gcc.target/riscv/cv-mem-lh-compile-1.c: New test.
* gcc.target/riscv/cv-mem-lh-compile-2.c: New test.
* gcc.target/riscv/cv-mem-lh-compile-3.c: New test.
* gcc.target/riscv/cv-mem-lhu-compile-1.c: New test.
* gcc.target/riscv/cv-mem-lhu-compile-2.c: New test.
* gcc.target/riscv/cv-mem-lhu-compile-3.c: New test.
* gcc.target/riscv/cv-mem-lw-compile-1.c: New test.
* gcc.target/riscv/cv-mem-lw-compile-2.c: New test.
* gcc.target/riscv/cv-mem-lw-compile-3.c: New test.
* gcc.target/riscv/cv-mem-sb-compile-1.c: New test.
* gcc.target/riscv/cv-mem-sb-compile-2.c: New test.
* gcc.target/riscv/cv-mem-sb-compile-3.c: New test.
* gcc.target/riscv/cv-mem-sh-compile-1.c: New test.
* gcc.target/riscv/cv-mem-sh-compile-2.c: New test.
* gcc.target/riscv/cv-mem-sh-compile-3.c: New test.
* gcc.target/riscv/cv-mem-sw-compile-1.c: New test.
* gcc.target/riscv/cv-mem-sw-compile-2.c: New test.
* gcc.target/riscv/cv-mem-sw-compile-3.c: New test.
* lib/target-supports.exp: Add proc for XCVmem.
---
 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |  28 +++
 gcc/config/riscv/corev.md | 227 ++
 gcc/config/riscv/predicates.md|  20 +-
 gcc/config/riscv/riscv-protos.h   |  12 +-
 gcc/config/riscv/riscv.cc |  48 +++-
 gcc/config/riscv/riscv.h  |   6 +-
 gcc/config/riscv/riscv.md |  46 ++--
 gcc/config/riscv/riscv.opt|   2 +
 gcc/doc/sourcebuild.texi  |   3 +
 .../gcc.target/riscv/cv-mem-lb-compile-1.c|  23 ++
 .../gcc.target/riscv/cv-mem-lb-compile-2.c|  24 ++
 .../gcc.target/riscv/cv-mem-lb-compile-3.c|  16 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-1.c   |  23 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-2.c   |  24 ++
 .../gcc.target/riscv/cv-mem-lbu-compile-3.c   |  16 ++
 .../gcc.target/riscv/cv-mem-lh-compile-1.c|  23 ++
 .../gcc.target/riscv/cv-mem-lh-compile-2.c|  24 ++
 .../gcc.target/riscv/cv-mem-lh-compile-3.c|  16 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-1.c   |  23 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-2.c   |  24 ++
 .../gcc.target/riscv/cv-mem-lhu-compile-3.c   |  16 ++
 .../gcc.target/riscv/cv-mem-lw-compile-1.c|  38 +++
 .../gcc.target/riscv/cv-mem-lw-compile-2.c|  38 +++
 .../gcc.target/riscv/cv-mem-lw-compile-3.c|  22 ++
 .../riscv/cv-mem-operand-compile-1.c  |  19 ++
 .../riscv/cv-mem-operand-compile-2.c  |  20 ++
 .../riscv/cv-mem-operand-compile-3.c  |  28 +++
 .../riscv/cv-mem-operand-compile-4.c  |  21 ++
 .../riscv/cv-mem-operand-compile-5.c  |  25 ++
 .../riscv/cv-mem-operand-compile-6.c  |  21 ++
 .../riscv/cv-mem-operand-compile-7.c  |  24 

[PATCH v2 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions

[Mary Bennett]

v1 -> v2:
  * Bring the MEM into the operand for cv.elw. The new predicate is
move_operand.
  * Add comment to riscv.md detailing why corev.md must appear before
the generic riscv instructions.

This patch series presents the comprehensive implementation of the ELW and BI
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

RISC-V: Update XCValu constraints to match other vendors
RISC-V: Add support for XCVelw extension in CV32E40P
RISC-V: Add support for XCVbi extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |  4 ++
 gcc/config/riscv/constraints.md   | 21 +---
 gcc/config/riscv/corev.def|  3 ++
 gcc/config/riscv/corev.md | 33 -
 gcc/config/riscv/predicates.md|  4 ++
 gcc/config/riscv/riscv-builtins.cc|  2 +
 gcc/config/riscv/riscv-ftypes.def |  1 +
 gcc/config/riscv/riscv.md | 11 -
 gcc/config/riscv/riscv.opt|  4 ++
 gcc/doc/extend.texi   |  8 
 gcc/doc/sourcebuild.texi  |  6 +++
 .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++
 .../gcc.target/riscv/cv-elw-elw-compile-1.c   | 11 +
 gcc/testsuite/lib/target-supports.exp | 26 ++
 17 files changed, 254 insertions(+), 10 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c

-- 
2.34.1

[PATCH v2 1/3] RISC-V: Add support for XCVelw extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add XCVelw.
* config/riscv/corev.def: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Add XCVelw builtin documentation.
* doc/sourcebuild.texi: Likewise.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-elw-compile-1.c: Create test for cv.elw.
* testsuite/lib/target-supports.exp: Add proc for the XCVelw extension.
---
 gcc/common/config/riscv/riscv-common.cc   |  2 ++
 gcc/config/riscv/corev.def|  3 +++
 gcc/config/riscv/corev.md | 15 +++
 gcc/config/riscv/riscv-builtins.cc|  2 ++
 gcc/config/riscv/riscv-ftypes.def |  1 +
 gcc/config/riscv/riscv.opt|  2 ++
 gcc/doc/extend.texi   |  8 
 gcc/doc/sourcebuild.texi  |  3 +++
 .../gcc.target/riscv/cv-elw-elw-compile-1.c   | 11 +++
 gcc/testsuite/lib/target-supports.exp | 13 +
 10 files changed, 60 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 526dbb7603b..6a1978bd0e4 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -312,6 +312,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1667,6 +1668,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"xcvmac",&gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
   {"xcvalu",&gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
+  {"xcvelw",&gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
 
   {"xtheadba",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
   {"xtheadbb",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/corev.def b/gcc/config/riscv/corev.def
index 17580df3c41..3b9ec029d06 100644
--- a/gcc/config/riscv/corev.def
+++ b/gcc/config/riscv/corev.def
@@ -41,3 +41,6 @@ RISCV_BUILTIN (cv_alu_subN, "cv_alu_subN", 
RISCV_BUILTIN_DIRECT, RISCV_SI_FT
 RISCV_BUILTIN (cv_alu_subuN,"cv_alu_subuN", RISCV_BUILTIN_DIRECT, 
RISCV_USI_FTYPE_USI_USI_UQI,  cvalu),
 RISCV_BUILTIN (cv_alu_subRN,"cv_alu_subRN", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI_SI_UQI, cvalu),
 RISCV_BUILTIN (cv_alu_subuRN,   "cv_alu_subuRN",RISCV_BUILTIN_DIRECT, 
RISCV_USI_FTYPE_USI_USI_UQI,  cvalu),
+
+// XCVELW
+RISCV_BUILTIN (cv_elw_elw_si, "cv_elw_elw", RISCV_BUILTIN_DIRECT, 
RISCV_USI_FTYPE_VOID_PTR, cvelw),
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 1350bd4b81e..c7a2ba07bcc 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -24,6 +24,9 @@
   UNSPEC_CV_ALU_CLIPR
   UNSPEC_CV_ALU_CLIPU
   UNSPEC_CV_ALU_CLIPUR
+
+  ;;CORE-V EVENT LOAD
+  UNSPECV_CV_ELW
 ])
 
 ;; XCVMAC extension.
@@ -691,3 +694,15 @@
   cv.suburnr\t%0,%2,%3"
   [(set_attr "type" "arith")
   (set_attr "mode" "SI")])
+
+;; XCVELW builtins
+(define_insn "riscv_cv_elw_elw_si"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+   (unspec_volatile [(match_operand:SI 1 "move_operand" "p")]
+ UNSPECV_CV_ELW))]
+
+  "TARGET_XCVELW && !TARGET_64BIT"
+  "cv.elw\t%0,%a1"
+
+  [(set_attr "type" "load")
+  (set_attr "mode" "SI")])
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index fc3976f3ba1..5ee11ebe3bc 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -128,6 +128,7 @@ AVAIL (hint_pause, (!0))
 // CORE-V AVAIL
 AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT)
 AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
+AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT)
 
 /* Construct a riscv_builtin_description from the given arguments.
 
@@ -168,6 +169,7 @@ AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
 #define RISCV_ATYPE_HI intHI_type_node
 #define 

[PATCH v2 2/3] RISC-V: Update XCValu constraints to match other vendors

[Mary Bennett]

gcc/ChangeLog:
* config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
* config/riscv/corev.md: Likewise.
---
 gcc/config/riscv/constraints.md | 15 ---
 gcc/config/riscv/corev.md   |  4 ++--
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 68be4515c04..2711efe68c5 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -151,13 +151,6 @@
 (define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? GR_REGS 
: NO_REGS"
   "An integer register for  ZFA or XTheadFmv.")
 
-;; CORE-V Constraints
-(define_constraint "CVP2"
-  "Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
-  (and (match_code "const_int")
-   (and (match_test "IN_RANGE (ival, 0, 1073741823)")
-(match_test "exact_log2 (ival + 1) != -1"
-
 ;; Vector constraints.
 
 (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS"
@@ -246,3 +239,11 @@
A MEM with a valid address for th.[l|s]*ur* instructions."
   (and (match_code "mem")
(match_test "th_memidx_legitimate_index_p (op, true)")))
+
+;; CORE-V Constraints
+(define_constraint "CV_alu_pow2"
+  "@internal
+   Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
+  (and (match_code "const_int")
+   (and (match_test "IN_RANGE (ival, 0, 1073741823)")
+(match_test "exact_log2 (ival + 1) != -1"
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index c7a2ba07bcc..92bf0b5d6a6 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -516,7 +516,7 @@
 (define_insn "riscv_cv_alu_clip"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
-   (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
+   (match_operand:SI 2 "immediate_register_operand" 
"CV_alu_pow2,r")]
 UNSPEC_CV_ALU_CLIP))]
 
   "TARGET_XCVALU && !TARGET_64BIT"
@@ -529,7 +529,7 @@
 (define_insn "riscv_cv_alu_clipu"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
-   (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
+   (match_operand:SI 2 "immediate_register_operand" 
"CV_alu_pow2,r")]
 UNSPEC_CV_ALU_CLIPU))]
 
   "TARGET_XCVALU && !TARGET_64BIT"
-- 
2.34.1

[PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Create XCVbi extension
  support.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Implement cv_branch pattern
  for cv.beqimm and cv.bneimm.
* config/riscv/riscv.md: Change pattern priority so corev.md
  patterns run before riscv.md patterns.
* config/riscv/constraints.md: Implement constraints
  cv_bi_s5 - signed 5-bit immediate.
* config/riscv/predicates.md: Implement predicate
  const_int5s_operand - signed 5 bit immediate.
* doc/sourcebuild.texi: Add XCVbi documentation.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
* lib/target-supports.exp: Add proc for XCVbi.
---
 gcc/common/config/riscv/riscv-common.cc   |  2 +
 gcc/config/riscv/constraints.md   |  6 +++
 gcc/config/riscv/corev.md | 14 ++
 gcc/config/riscv/predicates.md|  4 ++
 gcc/config/riscv/riscv.md | 11 -
 gcc/config/riscv/riscv.opt|  2 +
 gcc/doc/sourcebuild.texi  |  3 ++
 .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++
 gcc/testsuite/lib/target-supports.exp | 13 +
 12 files changed, 184 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 6a1978bd0e4..04631e007f0 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -313,6 +313,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1669,6 +1670,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"xcvmac",&gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
   {"xcvalu",&gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
   {"xcvelw",&gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
+  {"xcvbi", &gcc_options::x_riscv_xcv_subext, MASK_XCVBI},
 
   {"xtheadba",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
   {"xtheadbb",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 2711efe68c5..718b4bd77df 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -247,3 +247,9 @@
   (and (match_code "const_int")
(and (match_test "IN_RANGE (ival, 0, 1073741823)")
 (match_test "exact_log2 (ival + 1) != -1"
+
+(define_constraint "CV_bi_sign5"
+  "@internal
+   A 5-bit signed immediate for CORE-V Immediate Branch."
+  (and (match_code "const_int")
+   (match_test "IN_RANGE (ival, -16, 15)")))
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 92bf0b5d6a6..f6a1f916d7e 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -706,3 +706,17 @@
 
   [(set_attr "type" "load")
   (set_attr "mode" "SI")])
+
+;; XCVBI Builtins
+(define_insn "cv_branch"
+  [(set (pc)
+   (if_then_else
+(match_operator 1 "equality_operator"
+[(match_operand:X 2 "register_operand" "r")
+ (match_operand:X 3 "const_int5s_operand" 
"CV_bi_sign5")])
+(label_ref (match_operand 0 "" ""))
+(pc)))]
+  "TARGET_XCVBI"
+  "cv.b%C1imm\t%2,%3,%0"
+  [(set_attr "type" "branch")
+   (set_

[PATCH v3 1/3] RISC-V: Add support for XCVelw extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add XCVelw.
* config/riscv/corev.def: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Add XCVelw builtin documentation.
* doc/sourcebuild.texi: Likewise.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-elw-compile-1.c: Create test for cv.elw.
* testsuite/lib/target-supports.exp: Add proc for the XCVelw extension.
---
 gcc/common/config/riscv/riscv-common.cc   |  2 ++
 gcc/config/riscv/corev.def|  3 +++
 gcc/config/riscv/corev.md | 15 +++
 gcc/config/riscv/riscv-builtins.cc|  2 ++
 gcc/config/riscv/riscv-ftypes.def |  1 +
 gcc/config/riscv/riscv.opt|  2 ++
 gcc/doc/extend.texi   |  8 
 gcc/doc/sourcebuild.texi  |  3 +++
 .../gcc.target/riscv/cv-elw-elw-compile-1.c   | 11 +++
 gcc/testsuite/lib/target-supports.exp | 13 +
 10 files changed, 60 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 5111626157b..c8c0d0a2252 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -312,6 +312,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1676,6 +1677,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"xcvmac",&gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
   {"xcvalu",&gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
+  {"xcvelw",&gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
 
   {"xtheadba",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
   {"xtheadbb",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/corev.def b/gcc/config/riscv/corev.def
index 17580df3c41..3b9ec029d06 100644
--- a/gcc/config/riscv/corev.def
+++ b/gcc/config/riscv/corev.def
@@ -41,3 +41,6 @@ RISCV_BUILTIN (cv_alu_subN, "cv_alu_subN", 
RISCV_BUILTIN_DIRECT, RISCV_SI_FT
 RISCV_BUILTIN (cv_alu_subuN,"cv_alu_subuN", RISCV_BUILTIN_DIRECT, 
RISCV_USI_FTYPE_USI_USI_UQI,  cvalu),
 RISCV_BUILTIN (cv_alu_subRN,"cv_alu_subRN", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI_SI_UQI, cvalu),
 RISCV_BUILTIN (cv_alu_subuRN,   "cv_alu_subuRN",RISCV_BUILTIN_DIRECT, 
RISCV_USI_FTYPE_USI_USI_UQI,  cvalu),
+
+// XCVELW
+RISCV_BUILTIN (cv_elw_elw_si, "cv_elw_elw", RISCV_BUILTIN_DIRECT, 
RISCV_USI_FTYPE_VOID_PTR, cvelw),
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 1350bd4b81e..c7a2ba07bcc 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -24,6 +24,9 @@
   UNSPEC_CV_ALU_CLIPR
   UNSPEC_CV_ALU_CLIPU
   UNSPEC_CV_ALU_CLIPUR
+
+  ;;CORE-V EVENT LOAD
+  UNSPECV_CV_ELW
 ])
 
 ;; XCVMAC extension.
@@ -691,3 +694,15 @@
   cv.suburnr\t%0,%2,%3"
   [(set_attr "type" "arith")
   (set_attr "mode" "SI")])
+
+;; XCVELW builtins
+(define_insn "riscv_cv_elw_elw_si"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+   (unspec_volatile [(match_operand:SI 1 "move_operand" "p")]
+ UNSPECV_CV_ELW))]
+
+  "TARGET_XCVELW && !TARGET_64BIT"
+  "cv.elw\t%0,%a1"
+
+  [(set_attr "type" "load")
+  (set_attr "mode" "SI")])
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index fc3976f3ba1..5ee11ebe3bc 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -128,6 +128,7 @@ AVAIL (hint_pause, (!0))
 // CORE-V AVAIL
 AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT)
 AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
+AVAIL (cvelw, TARGET_XCVELW && !TARGET_64BIT)
 
 /* Construct a riscv_builtin_description from the given arguments.
 
@@ -168,6 +169,7 @@ AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
 #define RISCV_ATYPE_HI intHI_type_node
 #define 

[PATCH v3 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions

[Mary Bennett]

v1 -> v2:
  * Bring the MEM into the operand for cv.elw. The new predicate is
move_operand.
  * Add comment to riscv.md detailing why corev.md must appear before
the generic riscv instructions.

v2 -> v3:
  * Merged patterns for CORE-V branch immediate and generic RISC-V so to
supress the generic patterns if XCVbi is available.

This patch series presents the comprehensive implementation of the ELW and BI
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

RISC-V: Update XCValu constraints to match other vendors
RISC-V: Add support for XCVelw extension in CV32E40P
RISC-V: Add support for XCVbi extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |  4 ++
 gcc/config/riscv/constraints.md   | 21 +---
 gcc/config/riscv/corev.def|  3 ++
 gcc/config/riscv/corev.md | 33 -
 gcc/config/riscv/predicates.md|  4 ++
 gcc/config/riscv/riscv-builtins.cc|  2 +
 gcc/config/riscv/riscv-ftypes.def |  1 +
 gcc/config/riscv/riscv.md |  4 ++
 gcc/config/riscv/riscv.opt|  4 ++
 gcc/doc/extend.texi   |  8 
 gcc/doc/sourcebuild.texi  |  6 +++
 .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++
 .../gcc.target/riscv/cv-elw-elw-compile-1.c   | 11 +
 gcc/testsuite/lib/target-supports.exp | 26 ++
 17 files changed, 248 insertions(+), 9 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-elw-elw-compile-1.c

-- 
2.34.1

[PATCH v3 2/3] RISC-V: Update XCValu constraints to match other vendors

[Mary Bennett]

gcc/ChangeLog:
* config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
* config/riscv/corev.md: Likewise.
---
 gcc/config/riscv/constraints.md | 15 ---
 gcc/config/riscv/corev.md   |  4 ++--
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 68be4515c04..2711efe68c5 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -151,13 +151,6 @@
 (define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? GR_REGS 
: NO_REGS"
   "An integer register for  ZFA or XTheadFmv.")
 
-;; CORE-V Constraints
-(define_constraint "CVP2"
-  "Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
-  (and (match_code "const_int")
-   (and (match_test "IN_RANGE (ival, 0, 1073741823)")
-(match_test "exact_log2 (ival + 1) != -1"
-
 ;; Vector constraints.
 
 (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS"
@@ -246,3 +239,11 @@
A MEM with a valid address for th.[l|s]*ur* instructions."
   (and (match_code "mem")
(match_test "th_memidx_legitimate_index_p (op, true)")))
+
+;; CORE-V Constraints
+(define_constraint "CV_alu_pow2"
+  "@internal
+   Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
+  (and (match_code "const_int")
+   (and (match_test "IN_RANGE (ival, 0, 1073741823)")
+(match_test "exact_log2 (ival + 1) != -1"
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index c7a2ba07bcc..92bf0b5d6a6 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -516,7 +516,7 @@
 (define_insn "riscv_cv_alu_clip"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
-   (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
+   (match_operand:SI 2 "immediate_register_operand" 
"CV_alu_pow2,r")]
 UNSPEC_CV_ALU_CLIP))]
 
   "TARGET_XCVALU && !TARGET_64BIT"
@@ -529,7 +529,7 @@
 (define_insn "riscv_cv_alu_clipu"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
-   (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
+   (match_operand:SI 2 "immediate_register_operand" 
"CV_alu_pow2,r")]
 UNSPEC_CV_ALU_CLIPU))]
 
   "TARGET_XCVALU && !TARGET_64BIT"
-- 
2.34.1

[PATCH v3 3/3] RISC-V: Add support for XCVbi extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Create XCVbi extension
  support.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Implement cv_branch pattern
  for cv.beqimm and cv.bneimm.
* config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
  branch instruction pattern.
* config/riscv/constraints.md: Implement constraints
  cv_bi_s5 - signed 5-bit immediate.
* config/riscv/predicates.md: Implement predicate
  const_int5s_operand - signed 5 bit immediate.
* doc/sourcebuild.texi: Add XCVbi documentation.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
* lib/target-supports.exp: Add proc for XCVbi.
---
 gcc/common/config/riscv/riscv-common.cc   |  2 +
 gcc/config/riscv/constraints.md   |  6 +++
 gcc/config/riscv/corev.md | 14 ++
 gcc/config/riscv/predicates.md|  4 ++
 gcc/config/riscv/riscv.md |  4 ++
 gcc/config/riscv/riscv.opt|  2 +
 gcc/doc/sourcebuild.texi  |  3 ++
 .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++
 gcc/testsuite/lib/target-supports.exp | 13 +
 12 files changed, 178 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index c8c0d0a2252..125f8fb71f7 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -313,6 +313,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1678,6 +1679,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"xcvmac",&gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
   {"xcvalu",&gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
   {"xcvelw",&gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
+  {"xcvbi", &gcc_options::x_riscv_xcv_subext, MASK_XCVBI},
 
   {"xtheadba",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
   {"xtheadbb",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 2711efe68c5..718b4bd77df 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -247,3 +247,9 @@
   (and (match_code "const_int")
(and (match_test "IN_RANGE (ival, 0, 1073741823)")
 (match_test "exact_log2 (ival + 1) != -1"
+
+(define_constraint "CV_bi_sign5"
+  "@internal
+   A 5-bit signed immediate for CORE-V Immediate Branch."
+  (and (match_code "const_int")
+   (match_test "IN_RANGE (ival, -16, 15)")))
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 92bf0b5d6a6..f6a1f916d7e 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -706,3 +706,17 @@
 
   [(set_attr "type" "load")
   (set_attr "mode" "SI")])
+
+;; XCVBI Builtins
+(define_insn "cv_branch"
+  [(set (pc)
+   (if_then_else
+(match_operator 1 "equality_operator"
+[(match_operand:X 2 "register_operand" "r")
+ (match_operand:X 3 "const_int5s_operand" 
"CV_bi_sign5")])
+(label_ref (match_operand 0 "" ""))
+(pc)))]
+  "TARGET_XCVBI"
+  "cv.b%C1imm\t%2,%3,%0"
+  [(set_attr "type" "branch")
+   (set_attr "

[PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions

[Mary Bennett]

This patch series presents the comprehensive implementation of the MAC and ALU
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
    Mary Bennett 
Nandni Jamnadas 
Pietra Ferreira 
Charlie Keaney
Jessica Mills
Craig Blackmore 
Simon Cook 
Jeremy Bennett 
Helene Chelin 

  RISC-V: Add support for XCValu extension in CV32E40P
  RISC-V: Add support for XCVmac extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |   6 +
 gcc/config/riscv/constraints.md   |   7 +
 gcc/config/riscv/corev.def|  43 ++
 gcc/config/riscv/corev.md | 675 ++
 gcc/config/riscv/predicates.md|   5 +
 gcc/config/riscv/riscv-builtins.cc|  13 +
 gcc/config/riscv/riscv-ftypes.def |  11 +
 gcc/config/riscv/riscv-opts.h |   7 +
 gcc/config/riscv/riscv.cc |   7 +
 gcc/config/riscv/riscv.md |   1 +
 gcc/config/riscv/riscv.opt|   3 +
 gcc/doc/extend.texi   | 174 +
 .../gcc.target/riscv/cv-alu-compile.c | 252 +++
 .../riscv/cv-alu-fail-compile-addn.c  |  11 +
 .../riscv/cv-alu-fail-compile-addrn.c |  11 +
 .../riscv/cv-alu-fail-compile-addun.c |  11 +
 .../riscv/cv-alu-fail-compile-addurn.c|  11 +
 .../riscv/cv-alu-fail-compile-clip.c  |  11 +
 .../riscv/cv-alu-fail-compile-clipu.c |  11 +
 .../riscv/cv-alu-fail-compile-subn.c  |  11 +
 .../riscv/cv-alu-fail-compile-subrn.c |  11 +
 .../riscv/cv-alu-fail-compile-subun.c |  11 +
 .../riscv/cv-alu-fail-compile-suburn.c|  11 +
 .../gcc.target/riscv/cv-alu-fail-compile.c|  32 +
 .../gcc.target/riscv/cv-mac-compile.c | 198 +
 .../riscv/cv-mac-fail-compile-mac.c   |  25 +
 .../riscv/cv-mac-fail-compile-machhsn.c   |  24 +
 .../riscv/cv-mac-fail-compile-machhsrn.c  |  24 +
 .../riscv/cv-mac-fail-compile-machhun.c   |  24 +
 .../riscv/cv-mac-fail-compile-machhurn.c  |  24 +
 .../riscv/cv-mac-fail-compile-macsn.c |  24 +
 .../riscv/cv-mac-fail-compile-macsrn.c|  24 +
 .../riscv/cv-mac-fail-compile-macun.c |  24 +
 .../riscv/cv-mac-fail-compile-macurn.c|  24 +
 .../riscv/cv-mac-fail-compile-msu.c   |  25 +
 .../riscv/cv-mac-fail-compile-mulhhsn.c   |  24 +
 .../riscv/cv-mac-fail-compile-mulhhsrn.c  |  24 +
 .../riscv/cv-mac-fail-compile-mulhhun.c   |  24 +
 .../riscv/cv-mac-fail-compile-mulhhurn.c  |  24 +
 .../riscv/cv-mac-fail-compile-mulsn.c |  24 +
 .../riscv/cv-mac-fail-compile-mulsrn.c|  24 +
 .../riscv/cv-mac-fail-compile-mulun.c |  24 +
 .../riscv/cv-mac-fail-compile-mulurn.c|  24 +
 .../riscv/cv-mac-test-autogeneration.c|  18 +
 gcc/testsuite/lib/target-supports.exp |  26 +
 45 files changed, 2022 insertions(+)
 create mode 100644 gcc/config/riscv/corev.def
 create mode 100644 gcc/config/riscv/corev.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addurn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clip.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clipu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-suburn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mac.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsn.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhun.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhurn.c
 create mode 100644 gcc/testsuite/gcc.target/ris

[PATCH 1/2] RISC-V: Add support for XCVmac extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Added XCVmac.
* config/riscv/riscv-ftypes.def: Added XCVmac builtins.
* config/riscv/riscv-opts.h: Likewise.
* config/riscv/riscv.md: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Added XCVmac builtin documentation.
* config/riscv/corev.def: New file.
* config/riscv/corev.md: New file.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp: Added new effective target check.
* gcc.target/riscv/cv-mac-compile.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mac.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-machhsn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-machhsrn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-machhun.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-machhurn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-macsn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-macsrn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-macun.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-macurn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-msu.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulhhsn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulhhsrn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulhhun.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulhhurn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulsn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulsrn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulun.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulurn.c: New test.
* gcc.target/riscv/cv-mac-test-autogeneration.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc   |   4 +
 gcc/config/riscv/corev.def|  19 +
 gcc/config/riscv/corev.md | 390 ++
 gcc/config/riscv/riscv-builtins.cc|  10 +
 gcc/config/riscv/riscv-ftypes.def |   5 +
 gcc/config/riscv/riscv-opts.h |   5 +
 gcc/config/riscv/riscv.md |   1 +
 gcc/config/riscv/riscv.opt|   3 +
 gcc/doc/extend.texi   |  80 
 .../gcc.target/riscv/cv-mac-compile.c | 198 +
 .../riscv/cv-mac-fail-compile-mac.c   |  25 ++
 .../riscv/cv-mac-fail-compile-machhsn.c   |  24 ++
 .../riscv/cv-mac-fail-compile-machhsrn.c  |  24 ++
 .../riscv/cv-mac-fail-compile-machhun.c   |  24 ++
 .../riscv/cv-mac-fail-compile-machhurn.c  |  24 ++
 .../riscv/cv-mac-fail-compile-macsn.c |  24 ++
 .../riscv/cv-mac-fail-compile-macsrn.c|  24 ++
 .../riscv/cv-mac-fail-compile-macun.c |  24 ++
 .../riscv/cv-mac-fail-compile-macurn.c|  24 ++
 .../riscv/cv-mac-fail-compile-msu.c   |  25 ++
 .../riscv/cv-mac-fail-compile-mulhhsn.c   |  24 ++
 .../riscv/cv-mac-fail-compile-mulhhsrn.c  |  24 ++
 .../riscv/cv-mac-fail-compile-mulhhun.c   |  24 ++
 .../riscv/cv-mac-fail-compile-mulhhurn.c  |  24 ++
 .../riscv/cv-mac-fail-compile-mulsn.c |  24 ++
 .../riscv/cv-mac-fail-compile-mulsrn.c|  24 ++
 .../riscv/cv-mac-fail-compile-mulun.c |  24 ++
 .../riscv/cv-mac-fail-compile-mulurn.c|  24 ++
 .../riscv/cv-mac-test-autogeneration.c|  18 +
 gcc/testsuite/lib/target-supports.exp |  13 +
 30 files changed, 1180 insertions(+)
 create mode 100644 gcc/config/riscv/corev.def
 create mode 100644 gcc/config/riscv/corev.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mac.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsn.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhun.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhurn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macurn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-msu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhsn.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile

[PATCH 2/2] RISC-V: Add support for XCValu extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Added the XCValu
  extension.
* config/riscv/constraints.md: Added builtins for the XCValu
  extension.
* config/riscv/predicates.md (immediate_register_operand):
  Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
  (RISCV_ATYPE_UHI): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv-opts.h: Likewise.
* config/riscv/riscv.opt: Likewise.
* config/riscv/riscv.cc (riscv_print_operand): Likewise.
* doc/extend.texi: Added XCValu documentation.
* config/riscv/corev.def: New file.
* config/riscv/corev.md: New file.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp: Added proc for the XCValu extension.
* gcc.target/riscv/cv-alu-compile.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-addn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-addrn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-addun.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-addurn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-clip.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-clipu.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-subn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-subrn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-subun.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-suburn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |   7 +
 gcc/config/riscv/corev.def|  24 ++
 gcc/config/riscv/corev.md | 285 ++
 gcc/config/riscv/predicates.md|   5 +
 gcc/config/riscv/riscv-builtins.cc|   3 +
 gcc/config/riscv/riscv-ftypes.def |   6 +
 gcc/config/riscv/riscv-opts.h |   2 +
 gcc/config/riscv/riscv.cc |   7 +
 gcc/doc/extend.texi   |  94 ++
 .../gcc.target/riscv/cv-alu-compile.c | 252 
 .../riscv/cv-alu-fail-compile-addn.c  |  11 +
 .../riscv/cv-alu-fail-compile-addrn.c |  11 +
 .../riscv/cv-alu-fail-compile-addun.c |  11 +
 .../riscv/cv-alu-fail-compile-addurn.c|  11 +
 .../riscv/cv-alu-fail-compile-clip.c  |  11 +
 .../riscv/cv-alu-fail-compile-clipu.c |  11 +
 .../riscv/cv-alu-fail-compile-subn.c  |  11 +
 .../riscv/cv-alu-fail-compile-subrn.c |  11 +
 .../riscv/cv-alu-fail-compile-subun.c |  11 +
 .../riscv/cv-alu-fail-compile-suburn.c|  11 +
 .../gcc.target/riscv/cv-alu-fail-compile.c|  32 ++
 gcc/testsuite/lib/target-supports.exp |  13 +
 23 files changed, 842 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addurn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clip.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clipu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-suburn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 53e21fa4bce..e7c1a99fbd2 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -311,6 +311,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"svpbmt",  ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1483,6 +1484,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"ztso", &gcc_options::x_riscv_ztso_subext, MASK_ZTSO},
 
   {"xcvmac",&gcc_options::x_riscv_xcv_flags, M

[PATCH v2 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions

[Mary Bennett]

This patch series presents the comprehensive implementation of the MAC and ALU
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
    Mary Bennett 
Nandni Jamnadas 
Pietra Ferreira 
Charlie Keaney
Jessica Mills
Craig Blackmore 
Simon Cook 
Jeremy Bennett 
Helene Chelin 

  RISC-V: Add support for XCValu extension in CV32E40P
  RISC-V: Add support for XCVmac extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |   6 +
 gcc/config/riscv/constraints.md   |   7 +
 gcc/config/riscv/corev.def|  43 ++
 gcc/config/riscv/corev.md | 693 ++
 gcc/config/riscv/predicates.md|   5 +
 gcc/config/riscv/riscv-builtins.cc|  13 +
 gcc/config/riscv/riscv-ftypes.def |  11 +
 gcc/config/riscv/riscv-opts.h |   7 +
 gcc/config/riscv/riscv.cc |   7 +
 gcc/config/riscv/riscv.md |   1 +
 gcc/config/riscv/riscv.opt|   3 +
 gcc/doc/extend.texi   | 174 +
 .../gcc.target/riscv/cv-alu-compile.c | 252 +++
 .../riscv/cv-alu-fail-compile-addn.c  |  11 +
 .../riscv/cv-alu-fail-compile-addrn.c |  11 +
 .../riscv/cv-alu-fail-compile-addun.c |  11 +
 .../riscv/cv-alu-fail-compile-addurn.c|  11 +
 .../riscv/cv-alu-fail-compile-clip.c  |  11 +
 .../riscv/cv-alu-fail-compile-clipu.c |  11 +
 .../riscv/cv-alu-fail-compile-subn.c  |  11 +
 .../riscv/cv-alu-fail-compile-subrn.c |  11 +
 .../riscv/cv-alu-fail-compile-subun.c |  11 +
 .../riscv/cv-alu-fail-compile-suburn.c|  11 +
 .../gcc.target/riscv/cv-alu-fail-compile.c|  32 +
 .../gcc.target/riscv/cv-mac-compile.c | 198 +
 .../riscv/cv-mac-fail-compile-mac.c   |  25 +
 .../riscv/cv-mac-fail-compile-machhsn.c   |  24 +
 .../riscv/cv-mac-fail-compile-machhsrn.c  |  24 +
 .../riscv/cv-mac-fail-compile-machhun.c   |  24 +
 .../riscv/cv-mac-fail-compile-machhurn.c  |  24 +
 .../riscv/cv-mac-fail-compile-macsn.c |  24 +
 .../riscv/cv-mac-fail-compile-macsrn.c|  24 +
 .../riscv/cv-mac-fail-compile-macun.c |  24 +
 .../riscv/cv-mac-fail-compile-macurn.c|  24 +
 .../riscv/cv-mac-fail-compile-msu.c   |  25 +
 .../riscv/cv-mac-fail-compile-mulhhsn.c   |  24 +
 .../riscv/cv-mac-fail-compile-mulhhsrn.c  |  24 +
 .../riscv/cv-mac-fail-compile-mulhhun.c   |  24 +
 .../riscv/cv-mac-fail-compile-mulhhurn.c  |  24 +
 .../riscv/cv-mac-fail-compile-mulsn.c |  24 +
 .../riscv/cv-mac-fail-compile-mulsrn.c|  24 +
 .../riscv/cv-mac-fail-compile-mulun.c |  24 +
 .../riscv/cv-mac-fail-compile-mulurn.c|  24 +
 .../riscv/cv-mac-test-autogeneration.c|  18 +
 gcc/testsuite/lib/target-supports.exp |  26 +
 45 files changed, 2040 insertions(+)
 create mode 100644 gcc/config/riscv/corev.def
 create mode 100644 gcc/config/riscv/corev.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addurn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clip.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clipu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-suburn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mac.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsn.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhun.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhurn.c
 create mode 100644 gcc/testsuite/gcc.target/ris

[PATCH v2 2/2] RISC-V: Add support for XCValu extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Added the XCValu
extension.
* config/riscv/constraints.md: Added builtins for the XCValu
extension.
* config/riscv/predicates.md (immediate_register_operand):
Likewise.
* config/riscv/corev.def: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
  (RISCV_ATYPE_UHI): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv-opts.h: Likewise.
* config/riscv/riscv.opt: Likewise.
* config/riscv/riscv.cc (riscv_print_operand): Likewise.
* doc/extend.texi: Added XCValu documentation.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp: Added proc for the XCValu extension.
* gcc.target/riscv/cv-alu-compile.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-addn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-addrn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-addun.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-addurn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-clip.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-clipu.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-subn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-subrn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-subun.c: New test.
* gcc.target/riscv/cv-alu-fail-compile-suburn.c: New test.
* gcc.target/riscv/cv-alu-fail-compile.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |   7 +
 gcc/config/riscv/corev.def|  24 ++
 gcc/config/riscv/corev.md | 303 ++
 gcc/config/riscv/predicates.md|   5 +
 gcc/config/riscv/riscv-builtins.cc|   3 +
 gcc/config/riscv/riscv-ftypes.def |   6 +
 gcc/config/riscv/riscv-opts.h |   2 +
 gcc/config/riscv/riscv.cc |   7 +
 gcc/doc/extend.texi   |  94 ++
 .../gcc.target/riscv/cv-alu-compile.c | 252 +++
 .../riscv/cv-alu-fail-compile-addn.c  |  11 +
 .../riscv/cv-alu-fail-compile-addrn.c |  11 +
 .../riscv/cv-alu-fail-compile-addun.c |  11 +
 .../riscv/cv-alu-fail-compile-addurn.c|  11 +
 .../riscv/cv-alu-fail-compile-clip.c  |  11 +
 .../riscv/cv-alu-fail-compile-clipu.c |  11 +
 .../riscv/cv-alu-fail-compile-subn.c  |  11 +
 .../riscv/cv-alu-fail-compile-subrn.c |  11 +
 .../riscv/cv-alu-fail-compile-subun.c |  11 +
 .../riscv/cv-alu-fail-compile-suburn.c|  11 +
 .../gcc.target/riscv/cv-alu-fail-compile.c|  32 ++
 gcc/testsuite/lib/target-supports.exp |  13 +
 23 files changed, 860 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addurn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clip.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clipu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-suburn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 53e21fa4bce..e7c1a99fbd2 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -311,6 +311,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"svpbmt",  ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1483,6 +1484,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"ztso", &gcc_options::x_riscv_ztso_subext, MASK_ZTSO},
 
   {"xcvmac",&gcc_options::x_riscv_xcv_flags, MASK_XCVMAC},
+  {"xcvalu",  

[PATCH v2 1/2] RISC-V: Add support for XCVmac extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Added XCVmac.
* config/riscv/riscv-ftypes.def: Added XCVmac builtins.
* config/riscv/riscv-opts.h: Likewise.
* config/riscv/riscv.md: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Added XCVmac builtin documentation.
* config/riscv/corev.def: New file.
* config/riscv/corev.md: New file.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp: Added new effective target check.
* gcc.target/riscv/cv-mac-compile.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mac.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-machhsn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-machhsrn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-machhun.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-machhurn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-macsn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-macsrn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-macun.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-macurn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-msu.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulhhsn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulhhsrn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulhhun.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulhhurn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulsn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulsrn.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulun.c: New test.
* gcc.target/riscv/cv-mac-fail-compile-mulurn.c: New test.
* gcc.target/riscv/cv-mac-test-autogeneration.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc   |   4 +
 gcc/config/riscv/corev.def|  19 +
 gcc/config/riscv/corev.md | 390 ++
 gcc/config/riscv/riscv-builtins.cc|  10 +
 gcc/config/riscv/riscv-ftypes.def |   5 +
 gcc/config/riscv/riscv-opts.h |   5 +
 gcc/config/riscv/riscv.md |   1 +
 gcc/config/riscv/riscv.opt|   3 +
 gcc/doc/extend.texi   |  80 
 .../gcc.target/riscv/cv-mac-compile.c | 198 +
 .../riscv/cv-mac-fail-compile-mac.c   |  25 ++
 .../riscv/cv-mac-fail-compile-machhsn.c   |  24 ++
 .../riscv/cv-mac-fail-compile-machhsrn.c  |  24 ++
 .../riscv/cv-mac-fail-compile-machhun.c   |  24 ++
 .../riscv/cv-mac-fail-compile-machhurn.c  |  24 ++
 .../riscv/cv-mac-fail-compile-macsn.c |  24 ++
 .../riscv/cv-mac-fail-compile-macsrn.c|  24 ++
 .../riscv/cv-mac-fail-compile-macun.c |  24 ++
 .../riscv/cv-mac-fail-compile-macurn.c|  24 ++
 .../riscv/cv-mac-fail-compile-msu.c   |  25 ++
 .../riscv/cv-mac-fail-compile-mulhhsn.c   |  24 ++
 .../riscv/cv-mac-fail-compile-mulhhsrn.c  |  24 ++
 .../riscv/cv-mac-fail-compile-mulhhun.c   |  24 ++
 .../riscv/cv-mac-fail-compile-mulhhurn.c  |  24 ++
 .../riscv/cv-mac-fail-compile-mulsn.c |  24 ++
 .../riscv/cv-mac-fail-compile-mulsrn.c|  24 ++
 .../riscv/cv-mac-fail-compile-mulun.c |  24 ++
 .../riscv/cv-mac-fail-compile-mulurn.c|  24 ++
 .../riscv/cv-mac-test-autogeneration.c|  18 +
 gcc/testsuite/lib/target-supports.exp |  13 +
 30 files changed, 1180 insertions(+)
 create mode 100644 gcc/config/riscv/corev.def
 create mode 100644 gcc/config/riscv/corev.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-compile.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mac.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsn.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhun.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhurn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsrn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macun.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macurn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-msu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhsn.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhsrn.c
 create mode 100644 gcc

[PATCH v5 0/1] RISC-V: Support CORE-V XCVBITMAIP extension

[Mary Bennett]

This patch series presents the comprehensive implementation of the BITMANIP
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

RISC-V: Add support for XCVbitmanip extension in CV32E40P

 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |  16 ++
 gcc/config/riscv/corev.def|  13 ++
 gcc/config/riscv/corev.md | 188 ++
 gcc/config/riscv/predicates.md|  11 +
 gcc/config/riscv/riscv-builtins.cc|   1 +
 gcc/config/riscv/riscv-ftypes.def |   3 +
 gcc/config/riscv/riscv.cc |  13 ++
 gcc/config/riscv/riscv.opt|   5 +-
 gcc/doc/extend.texi   |  53 +
 gcc/doc/sourcebuild.texi  |   3 +
 .../riscv/cv-bitmanip-compile-bclr.c  |  27 +++
 .../riscv/cv-bitmanip-compile-bclrr.c |  18 ++
 .../riscv/cv-bitmanip-compile-bitrev.c|  30 +++
 .../riscv/cv-bitmanip-compile-bset.c  |  27 +++
 .../riscv/cv-bitmanip-compile-bsetr.c |  18 ++
 .../riscv/cv-bitmanip-compile-clb.c   |  18 ++
 .../riscv/cv-bitmanip-compile-cnt.c   |  18 ++
 .../riscv/cv-bitmanip-compile-extract.c   |  27 +++
 .../riscv/cv-bitmanip-compile-extractr.c  |  18 ++
 .../riscv/cv-bitmanip-compile-extractu.c  |  27 +++
 .../riscv/cv-bitmanip-compile-extractur.c |  18 ++
 .../riscv/cv-bitmanip-compile-ff1.c   |  18 ++
 .../riscv/cv-bitmanip-compile-fl1.c   |  18 ++
 .../riscv/cv-bitmanip-compile-insert.c|  24 +++
 .../riscv/cv-bitmanip-compile-insertr.c   |  18 ++
 .../riscv/cv-bitmanip-compile-ror.c   |  18 ++
 .../riscv/cv-bitmanip-fail-compile-bclr.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-bitrev.c   |  23 +++
 .../riscv/cv-bitmanip-fail-compile-bset.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-extract.c  |  25 +++
 .../riscv/cv-bitmanip-fail-compile-extractu.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-insert.c   |  25 +++
 gcc/testsuite/lib/target-supports.exp |  13 ++
 34 files changed, 810 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclrr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bitrev.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bset.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bsetr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-clb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-cnt.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extract.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extractr.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extractu.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extractur.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-ff1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-fl1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-insert.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-insertr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-ror.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-bclr.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-bitrev.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-bset.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-extract.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-extractu.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/cv-bitmanip-fail-compile-insert.c

-- 
2.43.0

[PATCH v5 1/1] RISC-V: Add support for XCVbitmanip extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add XCVbitmanip.
* config/riscv/constraints.md: Likewise.
* config/riscv/corev.def: Likewise.
* config/riscv/corev.md: Likewise.
* config/riscv/predicates.md: Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv.opt: Likewise.
* doc/extend.texi: Add XCVbitmanip builtin documentation.
* doc/sourcebuild.texi: Likewise.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bitmanip-compile-bclr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bclrr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bitrev.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bset.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-bsetr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-clb.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-cnt.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extract.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extractr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extractu.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-extractur.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-ff1.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-fl1.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-insert.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-insertr.c: New test.
* gcc.target/riscv/cv-bitmanip-compile-ror.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-bclr.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-bitrev.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-bset.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-extract.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-extractu.c: New test.
* gcc.target/riscv/cv-bitmanip-fail-compile-insert.c: New test.
* lib/target-supports.exp: Add proc for the XCVbitmanip extension.
---
 gcc/common/config/riscv/riscv-common.cc   |   2 +
 gcc/config/riscv/constraints.md   |  16 ++
 gcc/config/riscv/corev.def|  13 ++
 gcc/config/riscv/corev.md | 188 ++
 gcc/config/riscv/predicates.md|  11 +
 gcc/config/riscv/riscv-builtins.cc|   1 +
 gcc/config/riscv/riscv-ftypes.def |   3 +
 gcc/config/riscv/riscv.cc |  13 ++
 gcc/config/riscv/riscv.opt|   5 +-
 gcc/doc/extend.texi   |  53 +
 gcc/doc/sourcebuild.texi  |   3 +
 .../riscv/cv-bitmanip-compile-bclr.c  |  27 +++
 .../riscv/cv-bitmanip-compile-bclrr.c |  18 ++
 .../riscv/cv-bitmanip-compile-bitrev.c|  30 +++
 .../riscv/cv-bitmanip-compile-bset.c  |  27 +++
 .../riscv/cv-bitmanip-compile-bsetr.c |  18 ++
 .../riscv/cv-bitmanip-compile-clb.c   |  18 ++
 .../riscv/cv-bitmanip-compile-cnt.c   |  18 ++
 .../riscv/cv-bitmanip-compile-extract.c   |  27 +++
 .../riscv/cv-bitmanip-compile-extractr.c  |  18 ++
 .../riscv/cv-bitmanip-compile-extractu.c  |  27 +++
 .../riscv/cv-bitmanip-compile-extractur.c |  18 ++
 .../riscv/cv-bitmanip-compile-ff1.c   |  18 ++
 .../riscv/cv-bitmanip-compile-fl1.c   |  18 ++
 .../riscv/cv-bitmanip-compile-insert.c|  24 +++
 .../riscv/cv-bitmanip-compile-insertr.c   |  18 ++
 .../riscv/cv-bitmanip-compile-ror.c   |  18 ++
 .../riscv/cv-bitmanip-fail-compile-bclr.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-bitrev.c   |  23 +++
 .../riscv/cv-bitmanip-fail-compile-bset.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-extract.c  |  25 +++
 .../riscv/cv-bitmanip-fail-compile-extractu.c |  25 +++
 .../riscv/cv-bitmanip-fail-compile-insert.c   |  25 +++
 gcc/testsuite/lib/target-supports.exp |  13 ++
 34 files changed, 810 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bclrr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bitrev.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bset.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-bsetr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-clb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-cnt.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bitmanip-compile-extract.c