Thank you for reviewing this patch.
v1->v2:
* Add XCValu RTL.
* Change assembly mnemonics from mixed case to lower case.
v2->v3:
* Change commit message from past tense to present.
* Add documentation for new dg-effective-targets.
This patch series presents the comprehensive implementation of the MAC and ALU
extension for CORE-V.
Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.
The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].
[1]
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
[2] github.com/openhwgroup/corev-gcc
Contributors:
Mary Bennett <mary.benn...@embecosm.com>
Nandni Jamnadas <nandni.jamna...@embecosm.com>
Pietra Ferreira <pietra.ferre...@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackm...@embecosm.com>
Simon Cook <simon.c...@embecosm.com>
Jeremy Bennett <jeremy.benn...@embecosm.com>
Helene Chelin <helene.che...@embecosm.com>
RISC-V: Add support for XCValu extension in CV32E40P
RISC-V: Add support for XCVmac extension in CV32E40P
gcc/common/config/riscv/riscv-common.cc | 6 +
gcc/config/riscv/constraints.md | 7 +
gcc/config/riscv/corev.def | 43 ++
gcc/config/riscv/corev.md | 693 ++++++++++++++++++
gcc/config/riscv/predicates.md | 5 +
gcc/config/riscv/riscv-builtins.cc | 13 +
gcc/config/riscv/riscv-ftypes.def | 11 +
gcc/config/riscv/riscv-opts.h | 7 +
gcc/config/riscv/riscv.cc | 7 +
gcc/config/riscv/riscv.md | 1 +
gcc/config/riscv/riscv.opt | 3 +
gcc/doc/extend.texi | 174 +++++
gcc/doc/sourcebuild.texi | 12 +
.../gcc.target/riscv/cv-alu-compile.c | 252 +++++++
.../riscv/cv-alu-fail-compile-addn.c | 11 +
.../riscv/cv-alu-fail-compile-addrn.c | 11 +
.../riscv/cv-alu-fail-compile-addun.c | 11 +
.../riscv/cv-alu-fail-compile-addurn.c | 11 +
.../riscv/cv-alu-fail-compile-clip.c | 11 +
.../riscv/cv-alu-fail-compile-clipu.c | 11 +
.../riscv/cv-alu-fail-compile-subn.c | 11 +
.../riscv/cv-alu-fail-compile-subrn.c | 11 +
.../riscv/cv-alu-fail-compile-subun.c | 11 +
.../riscv/cv-alu-fail-compile-suburn.c | 11 +
.../gcc.target/riscv/cv-alu-fail-compile.c | 32 +
.../gcc.target/riscv/cv-mac-compile.c | 198 +++++
.../riscv/cv-mac-fail-compile-mac.c | 25 +
.../riscv/cv-mac-fail-compile-machhsn.c | 24 +
.../riscv/cv-mac-fail-compile-machhsrn.c | 24 +
.../riscv/cv-mac-fail-compile-machhun.c | 24 +
.../riscv/cv-mac-fail-compile-machhurn.c | 24 +
.../riscv/cv-mac-fail-compile-macsn.c | 24 +
.../riscv/cv-mac-fail-compile-macsrn.c | 24 +
.../riscv/cv-mac-fail-compile-macun.c | 24 +
.../riscv/cv-mac-fail-compile-macurn.c | 24 +
.../riscv/cv-mac-fail-compile-msu.c | 25 +
.../riscv/cv-mac-fail-compile-mulhhsn.c | 24 +
.../riscv/cv-mac-fail-compile-mulhhsrn.c | 24 +
.../riscv/cv-mac-fail-compile-mulhhun.c | 24 +
.../riscv/cv-mac-fail-compile-mulhhurn.c | 24 +
.../riscv/cv-mac-fail-compile-mulsn.c | 24 +
.../riscv/cv-mac-fail-compile-mulsrn.c | 24 +
.../riscv/cv-mac-fail-compile-mulun.c | 24 +
.../riscv/cv-mac-fail-compile-mulurn.c | 24 +
.../riscv/cv-mac-test-autogeneration.c | 18 +
gcc/testsuite/lib/target-supports.exp | 26 +
46 files changed, 2052 insertions(+)
create mode 100644 gcc/config/riscv/corev.def
create mode 100644 gcc/config/riscv/corev.md
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-compile.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addn.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addrn.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addun.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addurn.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clip.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clipu.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subn.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subrn.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subun.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-suburn.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-compile.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mac.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsn.c
create mode 100644
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsrn.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhun.c
create mode 100644
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhurn.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsn.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsrn.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macun.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macurn.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-msu.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhsn.c
create mode 100644
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhsrn.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhun.c
create mode 100644
gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhurn.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulsn.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulsrn.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulun.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulurn.c
create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-test-autogeneration.c
--
2.34.1
