date:20240817

[pushed] wwwdocs: doc: Tweak link to gm2 list archive

2024-08-17 Thread Gerald Pfeifer

Without the trailing slash we incur a "301 Moved Permanently".

gcc:
* doc/gm2.texi (Community): Tweak link to gm2 list archive.
---
 gcc/doc/gm2.texi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/doc/gm2.texi b/gcc/doc/gm2.texi
index bfc8dc71f23..40668f7f8c4 100644
--- a/gcc/doc/gm2.texi
+++ b/gcc/doc/gm2.texi
@@ -3015,7 +3015,7 @@ email to:
 or by
 @url{https://lists.nongnu.org/mailman/listinfo/gm2}.
 The mailing list contents can be viewed
-@url{https://lists.gnu.org/archive/html/gm2}.
+@url{https://lists.gnu.org/archive/html/gm2/}.
 
 @node Other languages, , Community, Using
 @section Other languages for GCC
-- 
2.46.0

[patch,avr,applied] Fix PR116390

2024-08-17 Thread Georg-Johann Lay


This fixes an ICE due to some typos in avr_out_movsi_mr_r_reg_disp_tiny
that didn't use operands[1] when it was required.

Johann

--

AVR: target/116390 - Fix an avrtiny asm out template.

PR target/116390
gcc/
* config/avr/avr.cc (avr_out_movsi_mr_r_reg_disp_tiny): Fix
output templates for the reg_base == reg_src and
reg_src == reg_base - 2 cases.
gcc/testsuite/
* gcc.target/avr/torture/pr116390.c: New test.diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index 8d59a6babed..8c19bcb34a6 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -5638,33 +5638,33 @@ avr_out_movsi_mr_r_reg_disp_tiny (rtx op[], int *l)
   rtx src = op[1];
   rtx base = XEXP (dest, 0);
   int reg_base = REGNO (XEXP (base, 0));
-  int reg_src =true_regnum (src);
+  int reg_src = true_regnum (src);
 
   if (reg_base == reg_src)
 {
   *l = 11;
-  return ("mov __tmp_reg__,%A2"CR_TAB
-	  "mov __zero_reg__,%B2"   CR_TAB
+  return ("mov __tmp_reg__,%A1"CR_TAB
+	  "mov __zero_reg__,%B1"   CR_TAB
 	  TINY_ADIW (%I0, %J0, %o0)CR_TAB
 	  "st %b0+,__tmp_reg__"CR_TAB
 	  "st %b0+,__zero_reg__"   CR_TAB
-	  "st %b0+,%C2"CR_TAB
-	  "st %b0,%D2" CR_TAB
+	  "st %b0+,%C1"CR_TAB
+	  "st %b0,%D1" CR_TAB
 	  "clr __zero_reg__"   CR_TAB
 	  TINY_SBIW (%I0, %J0, %o0+3));
 }
   else if (reg_src == reg_base - 2)
 {
-  *l = 11;
-  return ("mov __tmp_reg__,%C2" CR_TAB
-	  "mov __zero_reg__,%D2"CR_TAB
-	  TINY_ADIW (%I0, %J0, %o0) CR_TAB
-	  "st %b0+,%A0" CR_TAB
-	  "st %b0+,%B0" CR_TAB
-	  "st %b0+,__tmp_reg__" CR_TAB
-	  "st %b0,__zero_reg__" CR_TAB
-	  "clr __zero_reg__"CR_TAB
-	  TINY_SBIW (%I0, %J0, %o0+3));
+  // This awkward case can occur when ext-dce turns zero-extend:SI(HI)
+  // into a paradoxical subreg, which register allocation may turn into
+  // something like *(R28:HI + 7) = R26:SI.  There is actually no need
+  // to store the upper 2 bytes of R26:SI as they are unused rubbish.
+  // See PR116390.
+  *l = 6;
+  return (TINY_ADIW (%I0, %J0, %o0) CR_TAB
+	  "st %b0+,%A1" CR_TAB
+	  "st %b0,%B1"  CR_TAB
+	  TINY_SBIW (%I0, %J0, %o0+1));
 }
   *l = 8;
   return (TINY_ADIW (%I0, %J0, %o0) CR_TAB
diff --git a/gcc/testsuite/gcc.target/avr/torture/pr116390.c b/gcc/testsuite/gcc.target/avr/torture/pr116390.c
new file mode 100644
index 000..70c1ad62936
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/torture/pr116390.c
@@ -0,0 +1,71 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99" } */
+
+typedef struct
+{
+int i;
+} MyStruct;
+
+void f_ic (int, char);
+void f_pi (char const *, int);
+void f_iic (int, int, char);
+
+const MyStruct *f_rms (void);
+
+char *f_rcp (void);
+int f_ri (void);
+
+void badFoo (void)
+{
+const MyStruct* ps = f_rms ();
+const char* pc = f_rcp ();
+
+unsigned n1 = f_rcp () - pc;
+
+if (n1)
+{
+long n2 = n1 - ps->i;
+if (n2 > 0)
+{
+if (f_ri ())
+n2 = n1;
+
+if (f_ri ())
+{
+f_iic (1, 2 * n2, ' ');
+}
+else
+f_pi (pc, n2);
+}
+if (ps->i > 0)
+{
+if (n2 >= 0)
+f_pi (pc + n2, ps->i);
+else
+{
+f_ic (n2, ' ');
+}
+}
+
+const int which = f_ri ();
+switch (which)
+{
+case 1:
+if (f_ri ())
+f_rcp ()[1] = ' ';
+break;
+
+case 2:
+f_pi (f_rcp (), 1);
+break;
+
+case 3:
+if (f_ri () && n1 < 0)
+f_ic (n1, ' ');
+else
+f_rcp ()[1] = ' ';
+break;
+
+}
+}
+}

[PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2

2024-08-17 Thread pan2 . li

From: Pan Li 

This patch would like to add test cases for the unsigned scalar
.SAT_TRUNC form 2.  Aka:

Form 2:
  #define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
  NT __attribute__((noinline)) \
  sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
  {\
WT max = (WT)(NT)-1;   \
return x > max ? (NT) max : (NT)x; \
  }

DEF_SAT_U_TRUC_FMT_2 (uint32_t, uint64_t)

The below test is passed for this patch.
* The rv64gcv regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_u_trunc-7.c: New test.
* gcc.target/riscv/sat_u_trunc-8.c: New test.
* gcc.target/riscv/sat_u_trunc-9.c: New test.
* gcc.target/riscv/sat_u_trunc-run-7.c: New test.
* gcc.target/riscv/sat_u_trunc-run-8.c: New test.
* gcc.target/riscv/sat_u_trunc-run-9.c: New test.

Signed-off-by: Pan Li 
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h| 12 +++
 .../gcc.target/riscv/sat_u_trunc-7.c  | 17 
 .../gcc.target/riscv/sat_u_trunc-8.c  | 20 +++
 .../gcc.target/riscv/sat_u_trunc-9.c  | 19 ++
 .../gcc.target/riscv/sat_u_trunc-run-7.c  | 16 +++
 .../gcc.target/riscv/sat_u_trunc-run-8.c  | 16 +++
 .../gcc.target/riscv/sat_u_trunc-run-9.c  | 16 +++
 7 files changed, 116 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-9.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-9.c

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 37e0a60f21b..576a4926d1f 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -227,7 +227,19 @@ sat_u_truc_##WT##_to_##NT##_fmt_1 (WT x) \
 }
 #define DEF_SAT_U_TRUC_FMT_1_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_1(NT, WT)
 
+#define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
+NT __attribute__((noinline)) \
+sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
+{\
+  WT max = (WT)(NT)-1;   \
+  return x > max ? (NT) max : (NT)x; \
+}
+#define DEF_SAT_U_TRUC_FMT_2_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_2(NT, WT)
+
 #define RUN_SAT_U_TRUC_FMT_1(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_1 (x)
 #define RUN_SAT_U_TRUC_FMT_1_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_1(NT, WT, x)
 
+#define RUN_SAT_U_TRUC_FMT_2(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_2 (x)
+#define RUN_SAT_U_TRUC_FMT_2_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_2(NT, WT, x)
+
 #endif
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-7.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-7.c
new file mode 100644
index 000..95d513a15fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-7.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint16_t_to_uint8_t_fmt_2:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_2(uint8_t, uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-8.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-8.c
new file mode 100644
index 000..f168912293d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-8.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint32_t_to_uint16_t_fmt_2:
+** li\s+[atx][0-9]+,\s*65536
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_2(uint16_t, uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-9.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-9.c
new file mode 100644
index 000..d82363d6aef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-9.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl

[PATCH v1 2/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3

2024-08-17 Thread pan2 . li

From: Pan Li 

This patch would like to add test cases for the unsigned scalar
.SAT_TRUNC form 3.  Aka:

Form 3:
  #define DEF_SAT_U_TRUC_FMT_3(NT, WT) \
  NT __attribute__((noinline)) \
  sat_u_truc_##WT##_to_##NT##_fmt_3 (WT x) \
  {\
WT max = (WT)(NT)-1;   \
return x <= max ? (NT)x : (NT) max;\
  }

DEF_SAT_U_TRUC_FMT_3 (uint32_t, uint64_t)

The below test is passed for this patch.
* The rv64gcv regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_u_trunc-13.c: New test.
* gcc.target/riscv/sat_u_trunc-14.c: New test.
* gcc.target/riscv/sat_u_trunc-15.c: New test.
* gcc.target/riscv/sat_u_trunc-run-13.c: New test.
* gcc.target/riscv/sat_u_trunc-run-14.c: New test.
* gcc.target/riscv/sat_u_trunc-run-15.c: New test.

Signed-off-by: Pan Li 
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h| 12 +++
 .../gcc.target/riscv/sat_u_trunc-13.c | 17 
 .../gcc.target/riscv/sat_u_trunc-14.c | 20 +++
 .../gcc.target/riscv/sat_u_trunc-15.c | 19 ++
 .../gcc.target/riscv/sat_u_trunc-run-13.c | 16 +++
 .../gcc.target/riscv/sat_u_trunc-run-14.c | 16 +++
 .../gcc.target/riscv/sat_u_trunc-run-15.c | 16 +++
 7 files changed, 116 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-13.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-14.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-15.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-13.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-14.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-15.c

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 576a4926d1f..cf055410fd1 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -236,10 +236,22 @@ sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
 }
 #define DEF_SAT_U_TRUC_FMT_2_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_2(NT, WT)
 
+#define DEF_SAT_U_TRUC_FMT_3(NT, WT) \
+NT __attribute__((noinline)) \
+sat_u_truc_##WT##_to_##NT##_fmt_3 (WT x) \
+{\
+  WT max = (WT)(NT)-1;   \
+  return x <= max ? (NT)x : (NT) max;\
+}
+#define DEF_SAT_U_TRUC_FMT_3_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_3(NT, WT)
+
 #define RUN_SAT_U_TRUC_FMT_1(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_1 (x)
 #define RUN_SAT_U_TRUC_FMT_1_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_1(NT, WT, x)
 
 #define RUN_SAT_U_TRUC_FMT_2(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_2 (x)
 #define RUN_SAT_U_TRUC_FMT_2_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_2(NT, WT, x)
 
+#define RUN_SAT_U_TRUC_FMT_3(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_3 (x)
+#define RUN_SAT_U_TRUC_FMT_3_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_3(NT, WT, x)
+
 #endif
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-13.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-13.c
new file mode 100644
index 000..58910793a80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-13.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint16_t_to_uint8_t_fmt_3:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_3(uint8_t, uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-14.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-14.c
new file mode 100644
index 000..236ea1d45f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-14.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint32_t_to_uint16_t_fmt_3:
+** li\s+[atx][0-9]+,\s*65536
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_3(uint16_t, uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-15.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-15.c
new file mode 100644
index 000.

Re: [PATCH, gfortran] libgfortran: implement fpu-macppc for Darwin, support IEEE arithmetic

2024-08-17 Thread Sergio Had

Hi,

If we are good at this point, could someone help with merging it? (I don’t have 
commit access, of course.)

Sergey
On Aug 14, 2024 at 21:30 +0800, Sergey Fedorov , wrote:
> Thank you, Iain.
> I have adjusted a longer line and added an intro sentence before changelog 
> record.
>
>
>
> > On Wed, Aug 14, 2024 at 8:24 PM Iain Sandoe  wrote:
> > >
> > >
> > > > On 14 Aug 2024, at 13:17, Sergey Fedorov  wrote:
> > > >
> > > >
> > > >
> > > > On Wed, Aug 14, 2024 at 8:03 PM FX Coudert  wrote:
> > > > > Thank you for responding.
> > > > > I have added a changelog (is this a correct way?).
> > > >
> > > > Content seems ok, lines are maybe too long. Check with 
> > > > contrib/gcc-changelog/git_check_commit.py before pushing.
> > > > Once that is fine, OK to push.
> > > >
> > > > Looks like the script is okay with formatting:
> > > >
> > > > 36-25% /opt/local/bin/python3.11 
> > > > /Users/svacchanda/Github_barracuda156/gcc-git/contrib/gcc-changelog/git_check_commit.py
> > > > Checking 16e8ea376ada59306583decf1a218b2281a48638: OK
> > >
> > >         * config/fpu-macppc.h (new file): initial support for 
> > > powerpc-darwin.
> > >         * configure.host: enable ieee_support for powerpc-darwin case, 
> > > set fpu_host='fpu-macppc’.
> > >
> > > The description lines should begin with a capital letter and the lines 
> > > should
> > > not exceed 80 chars (some people prefer if they do not exceed 76 chars so
> > > that  “git show” output fits into 80 columns).
> > >
> > > hth
> > > Iain
> > >
> > >
> > > >
> > > > Sergey
> > > >
> > >

[pushed] libstdc++: Tweak links to installation docs

2024-08-17 Thread Gerald Pfeifer

Pushed with a grammar fix (of adding "the").

Gerald


libstdc++v-3:
* doc/xml/manual/prerequisites.xml: Tweak two links to
installation docs. Fix grammar.
* doc/html/manual/setup.html: Regenerate.
---
 libstdc++-v3/doc/html/manual/setup.html   | 7 ---
 libstdc++-v3/doc/xml/manual/prerequisites.xml | 4 ++--
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/libstdc++-v3/doc/html/manual/setup.html 
b/libstdc++-v3/doc/html/manual/setup.html
index 1963cdf695a..78d2a00c50a 100644
--- a/libstdc++-v3/doc/html/manual/setup.html
+++ b/libstdc++-v3/doc/html/manual/setup.html
@@ -21,9 +21,10 @@
Prerequisites
   Because libstdc++ is part of GCC, the primary source for
installation instructions is
-   http://gcc.gnu.org/install/"; target="_top">the GCC 
install page.
-   In particular, list of prerequisite software needed to build the library
-   http://gcc.gnu.org/install/prerequisites.html"; 
target="_top">
+   https://gcc.gnu.org/install/"; target="_top">the GCC 
install page.
+   In particular, the list of prerequisite software needed to build
+   the library
+   https://gcc.gnu.org/install/prerequisites.html"; 
target="_top">
starts with those requirements. The same pages also list
the tools you will need if you wish to modify the source.
 
diff --git a/libstdc++-v3/doc/xml/manual/prerequisites.xml 
b/libstdc++-v3/doc/xml/manual/prerequisites.xml
index a02d3795830..a3c6e732a77 100644
--- a/libstdc++-v3/doc/xml/manual/prerequisites.xml
+++ b/libstdc++-v3/doc/xml/manual/prerequisites.xml
@@ -14,9 +14,9 @@
 
   Because libstdc++ is part of GCC, the primary source for
installation instructions is
-   http://www.w3.org/1999/xlink"; 
xlink:href="http://gcc.gnu.org/install/";>the GCC install page.
+   http://www.w3.org/1999/xlink"; 
xlink:href="https://gcc.gnu.org/install/";>the GCC install page.
In particular, list of prerequisite software needed to build the library
-   http://www.w3.org/1999/xlink"; 
xlink:href="http://gcc.gnu.org/install/prerequisites.html";>
+   http://www.w3.org/1999/xlink"; 
xlink:href="https://gcc.gnu.org/install/prerequisites.html";>
starts with those requirements. The same pages also list
the tools you will need if you wish to modify the source.
 
-- 
2.46.0

[pushed] doc: Tweak PIM4 link

2024-08-17 Thread Gerald Pfeifer

gcc:
* doc/gm2.texi (What is GNU Modula-2): Tweak PIM4 link.
---
 gcc/doc/gm2.texi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/doc/gm2.texi b/gcc/doc/gm2.texi
index 40668f7f8c4..b2e4aa2e9c0 100644
--- a/gcc/doc/gm2.texi
+++ b/gcc/doc/gm2.texi
@@ -108,7 +108,7 @@ PIM3: 'Programming in Modula-2', 3rd Corrected Edition, 
Springer Verlag,
 1985 (PIM3).
 
 PIM4: 'Programming in Modula-2', 4th Edition, Springer Verlag, 1988
-(@uref{http://freepages.modula2.org/report4/modula-2.html, PIM4}).
+(@uref{https://freepages.modula2.org/report4/modula-2.html, PIM4}).
 
 ISO: the ISO Modula-2 language as defined in 'ISO/IEC Information
 technology - programming languages - part 1: Modula-2 Language,
-- 
2.46.0

[PATCH] c++/modules: Disable streaming definitions of non-vague-linkage GMF decls [PR115020]

2024-08-17 Thread Nathaniel Shead

Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk?

-- >8 --

The error in the linked PR is caused because 'DECL_THIS_STATIC' is true
for the static member function, causing the streaming code to assume
that this is an internal linkage GM entity that needs to be explicitly
streamed, which then on read-in gets marked as a vague linkage function
(despite being non-inline) causing import_export_decl to complain.

However, I don't see any reason why we should care about this:
definitions in the GMF should just be emitted as per usual regardless of
whether they're internal-linkage or not.  Actually the only thing we
care about here are header modules, since they have no TU to write
definitions into.  As such this patch removes these conditions from
'has_definition' and updates some comments to clarify.

PR c++/115020

gcc/cp/ChangeLog:

* module.cc (has_definition): Only force writing definitions for
header_module_p.

gcc/testsuite/ChangeLog:

* g++.dg/modules/pr115020_a.C: New test.
* g++.dg/modules/pr115020_b.C: New test.

Signed-off-by: Nathaniel Shead 
---
 gcc/cp/module.cc  | 16 
 gcc/testsuite/g++.dg/modules/pr115020_a.C | 10 ++
 gcc/testsuite/g++.dg/modules/pr115020_b.C | 10 ++
 3 files changed, 28 insertions(+), 8 deletions(-)
 create mode 100644 gcc/testsuite/g++.dg/modules/pr115020_a.C
 create mode 100644 gcc/testsuite/g++.dg/modules/pr115020_b.C

diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc
index f4d137b13a1..ae6cab0aac4 100644
--- a/gcc/cp/module.cc
+++ b/gcc/cp/module.cc
@@ -11782,13 +11782,12 @@ has_definition (tree decl)
/* Not defined.  */
break;
 
-  if (DECL_DECLARED_INLINE_P (decl))
+  if (header_module_p ())
+   /* We always need to write definitions in header modules,
+  since there's no TU to emit them in otherwise.  */
return true;
 
-  if (DECL_THIS_STATIC (decl)
- && (header_module_p ()
- || (!DECL_LANG_SPECIFIC (decl) || !DECL_MODULE_PURVIEW_P (decl
-   /* GM static function.  */
+  if (DECL_DECLARED_INLINE_P (decl))
return true;
 
   if (DECL_TEMPLATE_INFO (decl))
@@ -11821,11 +11820,12 @@ has_definition (tree decl)
   else
{
  if (!DECL_INITIALIZED_P (decl))
+   /* Not defined.  */
return false;
 
- if (header_module_p ()
- || (!DECL_LANG_SPECIFIC (decl) || !DECL_MODULE_PURVIEW_P (decl)))
-   /* GM static variable.  */
+ if (header_module_p ())
+   /* We always need to write definitions in header modules,
+  since there's no TU to emit them in otherwise.  */
return true;
 
  if (!TREE_CONSTANT (decl))
diff --git a/gcc/testsuite/g++.dg/modules/pr115020_a.C 
b/gcc/testsuite/g++.dg/modules/pr115020_a.C
new file mode 100644
index 000..8c190f13b1e
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/pr115020_a.C
@@ -0,0 +1,10 @@
+// PR c++/115020
+// { dg-additional-options "-fmodules-ts -Wno-global-module" }
+// { dg-module-cmi M:a }
+
+module;
+struct Check { static void assertion(); };
+void Check::assertion() {}
+
+module M:a;
+Check c;
diff --git a/gcc/testsuite/g++.dg/modules/pr115020_b.C 
b/gcc/testsuite/g++.dg/modules/pr115020_b.C
new file mode 100644
index 000..e299454ed54
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/pr115020_b.C
@@ -0,0 +1,10 @@
+// PR c++/115020
+// { dg-additional-options "-fmodules-ts -Wno-global-module" }
+// { dg-module-cmi M }
+
+module;
+struct Check { static void assertion(); };
+
+export module M;
+import :a;
+void foo() { Check::assertion(); }
-- 
2.43.2

[pushed] libstdc++: Update references to gcc.gnu.org/onlinedocs

2024-08-17 Thread Gerald Pfeifer

libstdc++-v3:
* doc/xml/manual/abi.xml: Update reference to
gcc.gnu.org/onlinedocs.
* doc/xml/manual/concurrency_extensions.xml (interface): Ditto.
* doc/xml/manual/extensions.xml: Ditto.
* doc/xml/manual/parallel_mode.xml: Ditto.
* doc/xml/manual/shared_ptr.xml: Ditto.
* doc/xml/manual/using_exceptions.xml: Ditto. And change GNU GCC
to GCC.
* doc/html/manual/abi.html: Regenerate.
* doc/html/manual/ext_concurrency_impl.html: Ditto.
* doc/html/manual/ext_demangling.html: Ditto.
* doc/html/manual/memory.html: Ditto.
* doc/html/manual/parallel_mode_design.html: Ditto.
* doc/html/manual/parallel_mode_using.html: Ditto.
* doc/html/manual/using_exceptions.html: Ditto.
---
 libstdc++-v3/doc/html/manual/abi.html  | 2 +-
 libstdc++-v3/doc/html/manual/ext_concurrency_impl.html | 4 ++--
 libstdc++-v3/doc/html/manual/ext_demangling.html   | 2 +-
 libstdc++-v3/doc/html/manual/memory.html   | 2 +-
 libstdc++-v3/doc/html/manual/parallel_mode_design.html | 2 +-
 libstdc++-v3/doc/html/manual/parallel_mode_using.html  | 2 +-
 libstdc++-v3/doc/html/manual/using_exceptions.html | 2 +-
 libstdc++-v3/doc/xml/manual/abi.xml| 2 +-
 libstdc++-v3/doc/xml/manual/concurrency_extensions.xml | 4 ++--
 libstdc++-v3/doc/xml/manual/extensions.xml | 2 +-
 libstdc++-v3/doc/xml/manual/parallel_mode.xml  | 4 ++--
 libstdc++-v3/doc/xml/manual/shared_ptr.xml | 2 +-
 libstdc++-v3/doc/xml/manual/using_exceptions.xml   | 4 ++--
 13 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/libstdc++-v3/doc/html/manual/abi.html 
b/libstdc++-v3/doc/html/manual/abi.html
index 0eb6a12a501..8dab47dbb93 100644
--- a/libstdc++-v3/doc/html/manual/abi.html
+++ b/libstdc++-v3/doc/html/manual/abi.html
@@ -28,7 +28,7 @@
   g++ command line options may change the ABI as a side-effect of
   use. Such flags include -fpack-struct and
   -fno-exceptions, but include others: see the 
complete
-  list in the GCC manual under the heading http://gcc.gnu.org/onlinedocs/gcc/Code-Gen-Options.html#Code%20Gen%20Options";
 target="_top">Options
+  list in the GCC manual under the heading https://gcc.gnu.org/onlinedocs/gcc/Code-Gen-Options.html#Code%20Gen%20Options";
 target="_top">Options
   for Code Generation Conventions.
 
   The configure options used when building a specific libstdc++
diff --git a/libstdc++-v3/doc/html/manual/ext_concurrency_impl.html 
b/libstdc++-v3/doc/html/manual/ext_concurrency_impl.html
index 23b90f34572..669c07cf291 100644
--- a/libstdc++-v3/doc/html/manual/ext_concurrency_impl.html
+++ b/libstdc++-v3/doc/html/manual/ext_concurrency_impl.html
@@ -34,7 +34,7 @@ non-ancient x86 hardware, -march=native usually does t
 trick. For hosts without compiler intrinsics, but with capable
 hardware, hand-crafted assembly is selected. This is the case for the 
following hosts:
 crishppai386i486m48kmipssparcAnd for the rest, a simulated 
atomic lock via pthreads.
- Detailed information about compiler intrinsics for atomic operations 
can be found in the GCC http://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html"; 
target="_top"> documentation.
+Detailed information about compiler intrinsics for atomic operations 
can be found in the GCC https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html"; 
target="_top"> documentation.
  More details on the library fallbacks from the porting section.
 Thread 
AbstractionA thin layer above IEEE 1003.1 (i.e. 
pthreads) is used to abstract
 the thread interface for GCC. This layer is called "gthread," and is
@@ -44,7 +44,7 @@ a POSIX-like interface.
 the current host. In libstdc++ implementation files,
  is used to select the proper gthreads file.
 Within libstdc++ sources, all calls to underlying thread functionality
-use this layer. More detail as to the specific interface can be found in the 
source http://gcc.gnu.org/onlinedocs/libstdc++/latest-doxygen/index.html"; 
target="_top">documentation.
+use this layer. More detail as to the specific interface can be found in the 
source https://gcc.gnu.org/onlinedocs/libstdc++/latest-doxygen/index.html"; 
target="_top">documentation.
 By design, the gthread layer is interoperable with the types,
 functions, and usage found in the usual  file,
 including pthread_t, pthread_once_t, pthread_create,
diff --git a/libstdc++-v3/doc/html/manual/ext_demangling.html 
b/libstdc++-v3/doc/html/manual/ext_demangling.html
index b5fb87b91c5..1eae99a1859 100644
--- a/libstdc++-v3/doc/html/manual/ext_demangling.html
+++ b/libstdc++-v3/doc/html/manual/ext_demangling.html
@@ -7,7 +7,7 @@
 original C++ source identifiers is called
 ???demangling.???
   
-If you have read the http://gcc.gnu.org/onlinedocs/libstdc++/latest-doxygen/namespaces.html"; 
target="_top">source
+If you have read the https://gcc.gnu.org/onlinedocs/libstdc+

[pushed] wwwdocs: gcc-15: Mark an AVR instruction up as

2024-08-17 Thread Gerald Pfeifer

All this patch does (modulo reformatting) is put SEI in a  
environment.

However, looking at this I've got a question: How about "imposing a 
function name" which is listed as a difference of noblock
versus others? This (the specific name) is not actually documented 
anywhere? Is that an omission, or am I missing something?

Gerald
---
 htdocs/gcc-15/changes.html | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index bfd98496..fe7cf3c1 100644
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/changes.html
@@ -122,11 +122,11 @@ a work-in-progress.
 functions defined in a C++ namespace.
   Support has been added for the noblock function attribute.
 It can be specified together with the signal attribute to
-indicate that the interrupt service routine should start with a SEI
-instruction to globally re-enable interrupts.  The difference to the
-interrupt attribute is that the noblock
-attribute just acts like a flag and does not impose a specific function
-name.
+indicate that the interrupt service routine should start with a
+SEI instruction to globally re-enable interrupts.
+The difference to the interrupt attribute is that the
+noblock attribute just acts like a flag and does not
+impose a specific function name.
   Support has been added for the __builtin_avr_mask1
 https://gcc.gnu.org/onlinedocs/gcc/AVR-Built-in-Functions.html#index-_005f_005fbuiltin_005favr_005fmask1";
>built-in function.  It can be used to compute some bit masks when
-- 
2.46.0

Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2

2024-08-17 Thread Kito Cheng

LGTM

 於 2024年8月17日 週六 19:37 寫道：

> From: Pan Li 
>
> This patch would like to add test cases for the unsigned scalar
> .SAT_TRUNC form 2.  Aka:
>
> Form 2:
>   #define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
>   NT __attribute__((noinline)) \
>   sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
>   {\
> WT max = (WT)(NT)-1;   \
> return x > max ? (NT) max : (NT)x; \
>   }
>
> DEF_SAT_U_TRUC_FMT_2 (uint32_t, uint64_t)
>
> The below test is passed for this patch.
> * The rv64gcv regression test.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/sat_arith.h: Add test helper macros.
> * gcc.target/riscv/sat_u_trunc-7.c: New test.
> * gcc.target/riscv/sat_u_trunc-8.c: New test.
> * gcc.target/riscv/sat_u_trunc-9.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-7.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-8.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-9.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/testsuite/gcc.target/riscv/sat_arith.h| 12 +++
>  .../gcc.target/riscv/sat_u_trunc-7.c  | 17 
>  .../gcc.target/riscv/sat_u_trunc-8.c  | 20 +++
>  .../gcc.target/riscv/sat_u_trunc-9.c  | 19 ++
>  .../gcc.target/riscv/sat_u_trunc-run-7.c  | 16 +++
>  .../gcc.target/riscv/sat_u_trunc-run-8.c  | 16 +++
>  .../gcc.target/riscv/sat_u_trunc-run-9.c  | 16 +++
>  7 files changed, 116 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-7.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-8.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-9.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-7.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-8.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-9.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
> b/gcc/testsuite/gcc.target/riscv/sat_arith.h
> index 37e0a60f21b..576a4926d1f 100644
> --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
> +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
> @@ -227,7 +227,19 @@ sat_u_truc_##WT##_to_##NT##_fmt_1 (WT x) \
>  }
>  #define DEF_SAT_U_TRUC_FMT_1_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_1(NT, WT)
>
> +#define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
> +NT __attribute__((noinline)) \
> +sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
> +{\
> +  WT max = (WT)(NT)-1;   \
> +  return x > max ? (NT) max : (NT)x; \
> +}
> +#define DEF_SAT_U_TRUC_FMT_2_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_2(NT, WT)
> +
>  #define RUN_SAT_U_TRUC_FMT_1(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_1
> (x)
>  #define RUN_SAT_U_TRUC_FMT_1_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_1(NT, WT,
> x)
>
> +#define RUN_SAT_U_TRUC_FMT_2(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_2
> (x)
> +#define RUN_SAT_U_TRUC_FMT_2_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_2(NT, WT,
> x)
> +
>  #endif
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-7.c
> b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-7.c
> new file mode 100644
> index 000..95d513a15fb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-7.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
> -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "sat_arith.h"
> +
> +/*
> +** sat_u_truc_uint16_t_to_uint8_t_fmt_2:
> +** sltiu\s+[atx][0-9]+,\s*a0,\s*255
> +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
> +** ret
> +*/
> +DEF_SAT_U_TRUC_FMT_2(uint8_t, uint16_t)
> +
> +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-8.c
> b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-8.c
> new file mode 100644
> index 000..f168912293d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-8.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
> -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "sat_arith.h"
> +
> +/*
> +** sat_u_truc_uint32_t_to_uint16_t_fmt_2:
> +** li\s+[atx][0-9]+,\s*65536
> +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
> +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** slli\s+a0,\s*a0,\s*48
> +** srli\s+a0,\s*a0,\s*48
> +** ret
> +*/
> +DEF_SAT_U_TRUC_FMT_2(uint16_t, uint32_t)
> +
> +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trun

Re: [PATCH v1 2/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3

2024-08-17 Thread Kito Cheng

LGTM

 於 2024年8月17日 週六 19:37 寫道：

> From: Pan Li 
>
> This patch would like to add test cases for the unsigned scalar
> .SAT_TRUNC form 3.  Aka:
>
> Form 3:
>   #define DEF_SAT_U_TRUC_FMT_3(NT, WT) \
>   NT __attribute__((noinline)) \
>   sat_u_truc_##WT##_to_##NT##_fmt_3 (WT x) \
>   {\
> WT max = (WT)(NT)-1;   \
> return x <= max ? (NT)x : (NT) max;\
>   }
>
> DEF_SAT_U_TRUC_FMT_3 (uint32_t, uint64_t)
>
> The below test is passed for this patch.
> * The rv64gcv regression test.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/sat_arith.h: Add test helper macros.
> * gcc.target/riscv/sat_u_trunc-13.c: New test.
> * gcc.target/riscv/sat_u_trunc-14.c: New test.
> * gcc.target/riscv/sat_u_trunc-15.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-13.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-14.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-15.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/testsuite/gcc.target/riscv/sat_arith.h| 12 +++
>  .../gcc.target/riscv/sat_u_trunc-13.c | 17 
>  .../gcc.target/riscv/sat_u_trunc-14.c | 20 +++
>  .../gcc.target/riscv/sat_u_trunc-15.c | 19 ++
>  .../gcc.target/riscv/sat_u_trunc-run-13.c | 16 +++
>  .../gcc.target/riscv/sat_u_trunc-run-14.c | 16 +++
>  .../gcc.target/riscv/sat_u_trunc-run-15.c | 16 +++
>  7 files changed, 116 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-13.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-14.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-15.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-13.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-14.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-15.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
> b/gcc/testsuite/gcc.target/riscv/sat_arith.h
> index 576a4926d1f..cf055410fd1 100644
> --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
> +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
> @@ -236,10 +236,22 @@ sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
>  }
>  #define DEF_SAT_U_TRUC_FMT_2_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_2(NT, WT)
>
> +#define DEF_SAT_U_TRUC_FMT_3(NT, WT) \
> +NT __attribute__((noinline)) \
> +sat_u_truc_##WT##_to_##NT##_fmt_3 (WT x) \
> +{\
> +  WT max = (WT)(NT)-1;   \
> +  return x <= max ? (NT)x : (NT) max;\
> +}
> +#define DEF_SAT_U_TRUC_FMT_3_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_3(NT, WT)
> +
>  #define RUN_SAT_U_TRUC_FMT_1(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_1
> (x)
>  #define RUN_SAT_U_TRUC_FMT_1_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_1(NT, WT,
> x)
>
>  #define RUN_SAT_U_TRUC_FMT_2(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_2
> (x)
>  #define RUN_SAT_U_TRUC_FMT_2_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_2(NT, WT,
> x)
>
> +#define RUN_SAT_U_TRUC_FMT_3(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_3
> (x)
> +#define RUN_SAT_U_TRUC_FMT_3_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_3(NT, WT,
> x)
> +
>  #endif
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-13.c
> b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-13.c
> new file mode 100644
> index 000..58910793a80
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-13.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
> -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "sat_arith.h"
> +
> +/*
> +** sat_u_truc_uint16_t_to_uint8_t_fmt_3:
> +** sltiu\s+[atx][0-9]+,\s*a0,\s*255
> +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
> +** ret
> +*/
> +DEF_SAT_U_TRUC_FMT_3(uint8_t, uint16_t)
> +
> +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-14.c
> b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-14.c
> new file mode 100644
> index 000..236ea1d45f7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-14.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
> -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "sat_arith.h"
> +
> +/*
> +** sat_u_truc_uint32_t_to_uint16_t_fmt_3:
> +** li\s+[atx][0-9]+,\s*65536
> +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
> +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** slli\s+a0,\s*a0,\s*48
> +** srli\s+a0,\s*a0,\s*48
> +**

Re: [PATCH v2] RISC-V: Add auto-vect pattern for vector rotate shift

2024-08-17 Thread Jeff Law





On 8/7/24 10:52 PM, Feng Wang wrote:

This patch add the vector rotate shift pattern for auto-vect.
With this patch, the scalar rotate shift can be automatically
vectorized into vector rotate shift.

gcc/ChangeLog:

* config/riscv/autovec.md (v3):
Add new define_expand pattern for vector rotate shift.
gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vrolr-1.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vrolr-run.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vrolr-template.h: New test.

Thanks.  I fixed the one whitespace nit and pushed this to the trunk.

jeff

Re: [PATCH v1] RISC-V: Bugfix incorrect operand for vwsll auto-vect

2024-08-17 Thread Jeff Law





On 8/10/24 8:31 AM, Robin Dapp wrote:

A bit of bikeshedding:

While it's obviously a bug, I'm not really sure it's useful to truncate before
emitting the widening shift.  Do we save an instruction vs. the regular
non-widening shift by doing so?
At least for the test you added, there is no different before/after 
Pan's patch.   If we disable the pattern entirely, then yes it gets 
notably worse -- instead of a single vwsll we end up two extensions, the 
vsll, and a vset+vncvt for the final conversion.  So yea, the pattern 
still seems to be worth having :-0


Jeff

Re: [PATCH v1] RISC-V: Bugfix incorrect operand for vwsll auto-vect

2024-08-17 Thread Jeff Law





On 8/10/24 6:36 AM, pan2...@intel.com wrote:

This patch would like to fix one ICE when rv64gcv_zvbb for vwsll.
Consider below example.

void vwsll_vv_test (short *restrict dst, char *restrict a,
 int *restrict b, int n)
{
   for (int i = 0; i < n; i++)
 dst[i] = a[i] << b[i];
}

It will hit the vwsll pattern with following operands.
operand 0 -> (reg:RVVMF2HI 146 [ vect__7.13 ])
operand 1 -> (reg:RVVMF4QI 165 [ vect_cst__33 ])
operand 2 -> (reg:RVVM1SI 171 [ vect_cst__36 ])

According to the ISA, operand 2 should be the same as operand 1.
Aka operand 2 should have RVVMF4QI mode as above.  Thus,  add
quad truncation for operand 2 before emit vwsll.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

PR target/116280

gcc/ChangeLog:

* config/riscv/autovec-opt.md: Add quad truncation to
align the mode requirement for vwsll.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pr116280-1.c: New test.
* gcc.target/riscv/rvv/base/pr116280-2.c: New test.

Thanks.  I've pushed this to the trunk.

jeff

Re: [PATCH v2] RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker

2024-08-17 Thread Jeff Law





On 8/12/24 7:25 AM, Jin Ma wrote:

When compiling an interface for rounding of type 'vfloat16*' without using zvfh
or zvfhmin, it is not enough to use FLOAT_MODE_P because the type does not 
support
it. Although the subsequent riscv_validate_vector_type checks will still fail
and throw exceptions, I don't think we should have ICE here.

internal compiler error: in check, at 
config/riscv/riscv-vector-builtins-shapes.cc:444
10 |   return __riscv_vfadd_vv_f16m1_rm (vs2, vs1, 0, vl);
   |   ^~
0x4191794 internal_error(char const*, ...)
 /iothome/jin.ma/code/master/gcc/gcc/diagnostic-global-context.cc:491
0x416ebf5 fancy_abort(char const*, int, char const*)
 /iothome/jin.ma/code/master/gcc/gcc/diagnostic.cc:1772
0x220aae6 riscv_vector::build_frm_base::check(riscv_vector::function_checker&) 
const
 
/iothome/jin.ma/code/master/gcc/gcc/config/riscv/riscv-vector-builtins-shapes.cc:444
0x2205323 riscv_vector::function_checker::check()
 
/iothome/jin.ma/code/master/gcc/gcc/config/riscv/riscv-vector-builtins.cc:4414

gcc/ChangeLog:

* config/riscv/riscv-protos.h (riscv_vector_float_type_p): New.
* config/riscv/riscv-vector-builtins.cc 
(function_instance::any_type_float_p):
Use riscv_vector_float_type_p instead of FLOAT_MODE_P for judgment.
* config/riscv/riscv.cc (riscv_vector_int_type_p): Change static to 
extern.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/bug-9.c: New test.

Thanks.  I've pushed this to the trunk.

jeff

Re: [pushed] wwwdocs: gcc-15: Mark an AVR instruction up as

2024-08-17 Thread Georg-Johann Lay


Am 17.08.24 um 15:43 schrieb Gerald Pfeifer:

All this patch does (modulo reformatting) is put SEI in a 
environment.

However, looking at this I've got a question: How about "imposing a
function name" which is listed as a difference of noblock
versus others? This (the specific name) is not actually documented
anywhere? Is that an omission, or am I missing something?

Gerald


Hmmm, as far as I know, there is no documentation.  The GCC docs just
propose to use the ISR resp. ISR_N macro from AVR-LibC, and AVR-LibC
doesn't document the gory details, either:

https://avrdudes.github.io/avr-libc/avr-libc-user-manual-2.2.0/group__avr__interrupts.html#gad28590624d422cdf30d626e0a506255f

Background is this:  The old signal and interrupt attributes allow
to define an ISR as

1) [[signal]] void __vector_1 (void) { ... }

2) [[interrupt]] void __vector_2 (void) { ... }

where the 2nd form adds a SEI before the prologue.  Using AVR-LibC,
the idioms for 1) and 2) are:

3) ISR(1) { ... }

4) ISR(2, ISR_NOBLOCK) { ... }

where 4) basically resolves to [[signal,interrupt]] void __vector_2 ...
This is supported by GCC: With [[interrupt]], the [[signal]] part is
basically ignored.  This won't work with the new signal(n) attribute:

5) ISR_N(1) static void my_isr1 (void) { ... }  // Ok

6) ISR_N(2, ISR_NOBLOCK) static void my_isr2 (void) { ... }  // Won't
work as expected when we expand "ISR_NOBLOCK" as [[interrupt]] because
the latter requires a function name of the __vector_N form like in 2).
Hence a new attribute "noblock" without that requirement.

HTH

Johann

p.s.: ISR_N is added in AVR-LibC v2.3, so you won't find the doc
behind the link above.



---
  htdocs/gcc-15/changes.html | 10 +-
  1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index bfd98496..fe7cf3c1 100644
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/changes.html
@@ -122,11 +122,11 @@ a work-in-progress.
  functions defined in a C++ namespace.
Support has been added for the noblock function attribute.
  It can be specified together with the signal attribute to
-indicate that the interrupt service routine should start with a SEI
-instruction to globally re-enable interrupts.  The difference to the
-interrupt attribute is that the noblock
-attribute just acts like a flag and does not impose a specific function
-name.
+indicate that the interrupt service routine should start with a
+SEI instruction to globally re-enable interrupts.
+The difference to the interrupt attribute is that the
+noblock attribute just acts like a flag and does not
+impose a specific function name.
Support has been added for the __builtin_avr_mask1
  https://gcc.gnu.org/onlinedocs/gcc/AVR-Built-in-Functions.html#index-_005f_005fbuiltin_005favr_005fmask1";
 >built-in function.  It can be used to compute some bit masks when

Re: [PATCH v2] RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics

2024-08-17 Thread Jeff Law





On 8/7/24 9:01 PM, Jin Ma wrote:

When rs1 is the immediate 0, the following ICE occurs:

error: unrecognizable insn:
(insn 8 5 12 2 (set (reg:RVVM1DI 134 [  ])
 (if_then_else:RVVM1DI (unspec:RVVMF64BI [
 (const_vector:RVVMF64BI repeat [
 (const_int 1 [0x1])
])
 (reg/v:DI 137 [ vl ])
 (const_int 2 [0x2]) repeated x2
 (const_int 0 [0])
 (reg:SI 66 vl)
 (reg:SI 67 vtype)
 ] UNSPEC_VPREDICATE)
 (plus:RVVM1DI (mult:RVVM1DI (vec_duplicate:RVVM1DI (const_int 0 
[0]))
 (reg/v:RVVM1DI 136 [ vs2 ]))
 (reg/v:RVVM1DI 135 [ vd ]))
 (reg/v:RVVM1DI 135 [ vd ])))

gcc/ChangeLog:

* config/riscv/vector.md: Allow scalar operand to be 0.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/bug-7.c: New test.
* gcc.target/riscv/rvv/base/bug-8.c: New test.

Thanks.  I pushed this to the trunk.

Jeff

[committed] Adjust v850 rotate expander to allow more cases for V850E3V5

2024-08-17 Thread Jeff Law


The recent if-conversion changes tripped a failure on the v850 port.

The core underlying issue is that while the if-conversion code tries to 
do the right thing with noce_can_force_operand to determine if it can 
force an arbitrary operand into a register, it's not really a sufficient 
check.


Essentially for arithmetic codes, it checks the operands.  If the 
operands are force-able and there's a code_to_optab mapping, then it 
returns true.


code_to_optab doesn't actually check anything other than the existence 
of  a mapping in the target.  If the target pattern has restrictions 
enforced by the condition or it's an expander that is allowed to FAIL, 
then noce_can_force_operand can return true, even though we may not be 
able to directly force the operand into a register.


This came up on the v850 when we had an operand that was a rotate by a 
constant number of bits (I don't remember the count, all that's 
important about it was the count was not 8 or 16).


The v850 port has this define_expand:

 > (define_expand "rotlsi3"

  [(parallel [(set (match_operand:SI 0 "register_operand" "")
   (rotate:SI (match_operand:SI 1 "register_operand" "")
  (match_operand:SI 2 "const_int_operand" "")))
  (clobber (reg:CC CC_REGNUM))])]
  "(TARGET_V850E_UP)"
  {
if (INTVAL (operands[2]) != 16)  
  FAIL; 
  })


So the only rotate count allowed is 16 (there's a similar HI rotate with 
a count of 8).  AFAICT the rotate patterns are allowed to FAIL.  So 
naturally the expander fails and we get a testsuite regression:



Tests that now fail, but worked before (4 tests):

v850-sim/-mgcc-abi/-msoft-float/-mv850e3v5: gcc: 
gcc.c-torture/execute/20100805-1.c   -O3 -fomit-frame-pointer -funroll-loops 
-fpeel-loops -ftracer -finline-functions  (test for excess errors)
v850-sim/-mgcc-abi/-msoft-float/-mv850e3v5: gcc: 
gcc.c-torture/execute/20100805-1.c   -O3 -fomit-frame-pointer -funroll-loops 
-fpeel-loops -ftracer -finline-functions  (test for excess errors)
v850-sim/-msoft-float/-mv850e3v5: gcc: gcc.c-torture/execute/20100805-1.c   -O3 
-fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions  
(test for excess errors)
v850-sim/-mv850e3v5: gcc: gcc.c-torture/execute/20100805-1.c   -O3 
-fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions  
(test for excess errors)



This patch works around the problem by allowing the rotates in 
additional cases, particularly for the V850E3V5+ variants which have a 
general rotate capability.  But let's be clear, this is just a 
workaround and I expect we're going to have to revisit the code to test 
if an operand can be forced into a register.


Pushing to the trunk.

commit abfc140579682598cd178eb9d0b0160bbfafc633
Author: Jeff Law 
Date:   Sat Aug 17 10:30:48 2024 -0600

Adjust v850 rotate expander to allow more cases for V850E3V5

The recent if-conversion changes tripped a failure on the v850 port.

The core underlying issue is that while the if-conversion code tries to do 
the
right thing with noce_can_force_operand to determine if it can force an
arbitrary operand into a register, it's not really a sufficient check.

Essentially for arithmetic codes, it checks the operands.  If the operands 
are
force-able and there's a code_to_optab mapping, then it returns true.

code_to_optab doesn't actually check anything other than the existence of  a
mapping in the target.  If the target pattern has restrictions enforced by 
the
condition or it's an expander that is allowed to FAIL, then
noce_can_force_operand to be true, even though we may not be able to 
directly
force the operand into a register.

This came up on the v850 when we had an operand that was a rotate by a 
constant
number of bits (I don't remember the count, all that's important about it 
was
the count was not 8 or 16).

The v850 port has this define_expand:

 > (define_expand "rotlsi3"
>   [(parallel [(set (match_operand:SI 0 "register_operand" "")
>(rotate:SI (match_operand:SI 1 "register_operand" "")
>   (match_operand:SI 2 "const_int_operand" 
"")))
>   (clobber (reg:CC CC_REGNUM))])]
>   "(TARGET_V850E_UP)"
>   {
> if (INTVAL (operands[2]) != 16)
>   FAIL;
>   })
So the only rotate count allowed is 16 (there's a similar HI rotate with a 
count of 8).  AFAICT the rotate patterns are allowed to FAIL.  So naturally the 
expander fails and we get a testsuite regression:

> Tests that now fail, but worked before (4 tests):
>
> v850-sim/-mgcc-abi/-msoft-float/-mv850e3v5: gcc: 
gcc.c-torture/execute/20100805-1.c   -O3 -fomit-frame-pointer -funroll-loops 
-fpeel-loops -ftracer -finline-functions  (test for excess errors)
> v850-sim/-mgcc-abi/-msoft-float/-mv850e3v5: gcc: 
gcc.c-torture/execute/20100805-1

Re: [PATCH v4] RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]

2024-08-17 Thread Jeff Law





On 8/16/24 9:43 PM, pan2...@intel.com wrote:

From: Pan Li 

For QI/HImode of .SAT_ADD,  the operands may be sign-extended and the
high bits of Xmode may be all 1 which is not expected.  For example as
below code.

signed char b[1];
unsigned short c;
signed char *d = b;
int main() {
   b[0] = -40;
   c = ({ (unsigned short)d[0] < 0xFFF6 ? (unsigned short)d[0] : 0xFFF6; }) + 9;
   __builtin_printf("%d\n", c);
}

After expanding we have:

;; _6 = .SAT_ADD (_3, 9);
(insn 8 7 9 (set (reg:DI 143)
 (high:DI (symbol_ref:DI ("d") [flags 0x86]  )))
  (nil))
(insn 9 8 10 (set (reg/f:DI 142)
 (mem/f/c:DI (lo_sum:DI (reg:DI 143)
 (symbol_ref:DI ("d") [flags 0x86]  )) [1 d+0 S8 
A64]))
  (nil))
(insn 10 9 11 (set (reg:HI 144 [ _3 ])
 (sign_extend:HI (mem:QI (reg/f:DI 142) [0 *d.0_1+0 S1 A8]))) 
"test.c":7:10 -1
  (nil))

The convert from signed char to unsigned short will have sign_extend rtl
as above.  And finally become the lb insn as below:

lb  a1,0(a5)   // a1 is -40, aka 0xffd8
lui a0,0x1a
addia5,a1,9
sllia5,a5,0x30
srlia5,a5,0x30 // a5 is 65505
sltua1,a5,a1   // compare 65505 and 0xffd8 => TRUE

The sltu try to compare 65505 and 0xffd8 here,  but we
actually want to compare 65505 and 65496 (0xffd8).  Thus we need to
clean up the high bits to ensure this.

The below test suites are passed for this patch:
* The rv64gcv fully regression test.

PR target/116278

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Add new
func impl to zero extend rtx.
(riscv_expand_usadd): Leverage above func to cleanup operands
and sum.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/pr116278-run-1.c: New test.
* gcc.target/riscv/pr116278-run-2.c: New test.

PR 116278

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Add new
func impl to zero extend rtx.
(riscv_expand_usadd): Leverage above func to cleanup operands 0
and remove the special handing for SImode in RV64.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_u_add-11.c: Adjust asm check body.
* gcc.target/riscv/sat_u_add-15.c: Ditto.
* gcc.target/riscv/sat_u_add-19.c: Ditto.
* gcc.target/riscv/sat_u_add-23.c: Ditto.
* gcc.target/riscv/sat_u_add-3.c: Ditto.
* gcc.target/riscv/sat_u_add-7.c: Ditto.
* gcc.target/riscv/sat_u_add_imm-11.c: Ditto.
* gcc.target/riscv/sat_u_add_imm-15.c: Ditto.
* gcc.target/riscv/sat_u_add_imm-3.c: Ditto.
* gcc.target/riscv/sat_u_add_imm-7.c: Ditto.
* gcc.target/riscv/pr116278-run-1.c: New test.
* gcc.target/riscv/pr116278-run-2.c: New test.
OK.  And I think this shows the basic approach we want to use if there 
are other builtins that accept sub-word modes.  ie, get the operands 
into X mode (by extending them as appropriate), then do as much work in 
X mode as possible, then truncate the result if needed.


Thanks for your patience on this.

Jeff

Re: [PATCH v1] RISC-V: Implement the quad and oct .SAT_TRUNC for scalar

2024-08-17 Thread Jeff Law





On 7/22/24 11:06 PM, pan2...@intel.com wrote:

From: Pan Li 

This patch would like to implement the quad and oct .SAT_TRUNC pattern
in the riscv backend. Aka:

Form 1:
   #define DEF_SAT_U_TRUC_FMT_1(NT, WT) \
   NT __attribute__((noinline)) \
   sat_u_truc_##WT##_to_##NT##_fmt_1 (WT x) \
   {\
 bool overflow = x > (WT)(NT)(-1);  \
 return ((NT)x) | (NT)-overflow;\
   }

DEF_SAT_U_TRUC_FMT_1(uint16_t, uint64_t)

Before this patch:
4   │ __attribute__((noinline))
5   │ uint16_t sat_u_truc_uint64_t_to_uint16_t_fmt_1 (uint64_t x)
6   │ {
7   │   _Bool overflow;
8   │   short unsigned int _1;
9   │   short unsigned int _2;
   10   │   short unsigned int _3;
   11   │   uint16_t _6;
   12   │
   13   │ ;;   basic block 2, loop depth 0
   14   │ ;;pred:   ENTRY
   15   │   overflow_5 = x_4(D) > 65535;
   16   │   _1 = (short unsigned int) x_4(D);
   17   │   _2 = (short unsigned int) overflow_5;
   18   │   _3 = -_2;
   19   │   _6 = _1 | _3;
   20   │   return _6;
   21   │ ;;succ:   EXIT
   22   │
   23   │ }

After this patch:
3   │
4   │ __attribute__((noinline))
5   │ uint16_t sat_u_truc_uint64_t_to_uint16_t_fmt_1 (uint64_t x)
6   │ {
7   │   uint16_t _6;
8   │
9   │ ;;   basic block 2, loop depth 0
   10   │ ;;pred:   ENTRY
   11   │   _6 = .SAT_TRUNC (x_4(D)); [tail call]
   12   │   return _6;
   13   │ ;;succ:   EXIT
   14   │
   15   │ }

The below tests suites are passed for this patch
1. The rv64gcv fully regression test.
2. The rv64gcv build with glibc

gcc/ChangeLog:

* config/riscv/iterators.md (ANYI_QUAD_TRUNC): New iterator for
quad truncation.
(ANYI_OCT_TRUNC): New iterator for oct truncation.
(ANYI_QUAD_TRUNCATED): New attr for truncated quad modes.
(ANYI_OCT_TRUNCATED): New attr for truncated oct modes.
(anyi_quad_truncated): Ditto but for lower case.
(anyi_oct_truncated): Ditto but for lower case.
* config/riscv/riscv.md (ustrunc2):
Add new pattern for quad truncation.
(ustrunc2): Ditto but for oct.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Adjust
the expand dump check times.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Ditto.
* gcc.target/riscv/sat_arith_data.h: Add test helper macros.
* gcc.target/riscv/sat_u_trunc-4.c: New test.
* gcc.target/riscv/sat_u_trunc-5.c: New test.
* gcc.target/riscv/sat_u_trunc-6.c: New test.
* gcc.target/riscv/sat_u_trunc-run-4.c: New test.
* gcc.target/riscv/sat_u_trunc-run-5.c: New test.
* gcc.target/riscv/sat_u_trunc-run-6.c: New test.
OK.  Sorry for the delays here.  I wanted to make sure we had the issues 
WRT operand extension resolved before diving into this.  But in 
retrospect, this probably could have moved forward independently.


Jeff

Re: [PATCH] t-rtems: add rv32imf architecture to the RTEMS multilib for RISC-V

2024-08-17 Thread Jeff Law





On 8/7/24 1:48 PM, Kirspel, Kevin wrote:
The attach patch is specific to the RTEMS RISC-V architecture multilib 
which is controlled by the t-rtems file in the gcc/config/riscv/ 
directory.  The patch file was created from the gcc-13.3.0 branch.  It 
was successfully tested within RTEMS Source Builder.
Thanks.  I haven't heard from Joel or Sebastian who often chime in on 
RTEMS stuff, given the patch looks quite sensible, I've pushed it to the 
trunk.


Thanks again!

Jeff

[committed] Avoid right shifting signed value on ext-dce.cc

2024-08-17 Thread Jeff Law



This is analogous to a prior patch to ext-dce which fixes propagation of 
sign bits, but this time for the saturating variants.  I'd held off 
fixing those because I wanted the time to look at that code (since we 
don't have a testcase for it as far as I know).


Not surprisingly, putting an abort on that path and running an x86 
bootstrap and testsuite run, it never triggers.  Of course not a lot of 
code tries to do saturating shifts.


Anyway, bootstrapped and regression tested on x86_64.  Pushing to the trunk.

Thanks for everyone's patience.

Jeff

commit 61e179b1b363454926504fac13b554ad7f1b0f72
Author: Jeff Law 
Date:   Sat Aug 17 15:10:38 2024 -0600

[committed] Avoid right shifting signed value on ext-dce.cc

This is analogous to a prior patch to ext-dce which fixes propagation of 
sign
bits, but this time for the saturating variants.  I'd held off fixing those
because I wanted the time to look at that code (since we don't have a 
testcase
for it as far as I know).

Not surprisingly, putting an abort on that path and running an x86 bootstrap
and testsuite run, it never triggers.  Of course not a lot of code tries to 
do
saturating shifts.

Anyway, bootstrapped and regression tested on x86_64.  Pushing to the trunk.

Thanks for everyone's patience.

gcc/
* ext-dce.cc (carry_backpropagate): Cast mask to HOST_WIDE_INT 
before
shifting.

diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index 97a66427118..017e2de000d 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -556,7 +556,7 @@ carry_backpropagate (unsigned HOST_WIDE_INT mask, enum 
rtx_code code, rtx x)
 >> (INTVAL (XEXP (x, 1))
 + (XEXP (x, 1) != const0_rtx
&& code == SS_ASHIFT
- | (mask >> INTVAL (XEXP (x, 1;
+ | ((HOST_WIDE_INT)mask >> INTVAL (XEXP (x, 1;
}
   return mmask;

RE: [PATCH v1] Vect: Promote unsigned .SAT_ADD constant operand for vectorizable_call

2024-08-17 Thread Jakub Jelinek

On Sat, Aug 17, 2024 at 05:03:14AM +, Li, Pan2 wrote:
> Please feel free to let me know if there is anything I can do to fix this
issue. Thanks a lot.

There is no bug.  The operands of .{ADD,SUB,MUL}_OVERFLOW don't have to
have the same type, as described in the
__builtin_{add,sub,mul}_overflow{,_p} documentation, each argument can have
different type and result yet another one, the behavior is then (as if) to
perform the operation in infinite precision and if that result fits into
the result type, there is no overflow, otherwise there is.
So, there is no need to promote anything.

Re: [PATCH v1] Vect: Promote unsigned .SAT_ADD constant operand for vectorizable_call

2024-08-17 Thread Jakub Jelinek

On Sat, Aug 17, 2024 at 05:03:14AM +, Li, Pan2 wrote:
> Thanks Richard for confirmation. Sorry almost forget this thread.
> 
> Please feel free to let me know if there is anything I can do to fix this 
> issue. Thanks a lot.

There is no bug.  The operands of .{ADD,SUB,MUL}_OVERFLOW don't have to
have the same type, as described in the
__builtin_{add,sub,mul}_overflow{,_p} documentation, each argument can have
different type and result yet another one, the behavior is then (as if) to
perform the operation in infinite precision and if that result fits into
the result type, there is no overflow, otherwise there is.
So, there is no need to promote anything, promoted constants would have the
same value as the non-promoted ones and the value is all that matters for
constants.

Jakub

[PATCH] forwprop: Also dce from added statements from gimple_simplify

2024-08-17 Thread Andrew Pinski

This extends r14-3982-g9ea74d235c7e78 to also include the newly added statements
since some of them might be dead too (due to the way match and simplify works).
This was noticed while working on adding a new match and simplify pattern where 
a
new statement that got added was not being used.

Bootstrapped and tested on x86_64-linux-gnu with no regressions.

gcc/ChangeLog:

* gimple-fold.cc (mark_lhs_in_seq_for_dce): New function.
(replace_stmt_with_simplification): Call mark_lhs_in_seq_for_dce
right before inserting the sequence.
(fold_stmt_1): Add dce_worklist argument, update call to
replace_stmt_with_simplification.
(fold_stmt): Add dce_worklist argument, update call to fold_stmt_1.
(fold_stmt_inplace): Update call to fold_stmt_1.
* gimple-fold.h (fold_stmt): Add bitmap argument.
* tree-ssa-forwprop.cc (pass_forwprop::execute): Update call to 
fold_stmt.

Signed-off-by: Andrew Pinski 
---
 gcc/gimple-fold.cc   | 43 +---
 gcc/gimple-fold.h|  4 ++--
 gcc/tree-ssa-forwprop.cc |  2 +-
 3 files changed, 39 insertions(+), 10 deletions(-)

diff --git a/gcc/gimple-fold.cc b/gcc/gimple-fold.cc
index 18d7a6b176d..0bec35d06f6 100644
--- a/gcc/gimple-fold.cc
+++ b/gcc/gimple-fold.cc
@@ -5914,6 +5914,24 @@ has_use_on_stmt (tree name, gimple *stmt)
   return false;
 }
 
+/* Add the lhs of each statement of SEQ to DCE_WORKLIST. */
+
+static void
+mark_lhs_in_seq_for_dce (bitmap dce_worklist, gimple_seq seq)
+{
+  if (!dce_worklist)
+return;
+
+  for (gimple_stmt_iterator i = gsi_start (seq);
+   !gsi_end_p (i); gsi_next (&i))
+{
+  gimple *stmt = gsi_stmt (i);
+  tree name = gimple_get_lhs (stmt);
+  if (name && TREE_CODE (name) == SSA_NAME)
+   bitmap_set_bit (dce_worklist, SSA_NAME_VERSION (name));
+}
+}
+
 /* Worker for fold_stmt_1 dispatch to pattern based folding with
gimple_simplify.
 
@@ -5924,7 +5942,8 @@ has_use_on_stmt (tree name, gimple *stmt)
 static bool
 replace_stmt_with_simplification (gimple_stmt_iterator *gsi,
  gimple_match_op *res_op,
- gimple_seq *seq, bool inplace)
+ gimple_seq *seq, bool inplace,
+ bitmap dce_worklist)
 {
   gimple *stmt = gsi_stmt (*gsi);
   tree *ops = res_op->ops;
@@ -5992,6 +6011,8 @@ replace_stmt_with_simplification (gimple_stmt_iterator 
*gsi,
  print_gimple_stmt (dump_file, gsi_stmt (*gsi),
 0, TDF_SLIM);
}
+  // Mark the lhs of the new statements maybe for dce
+  mark_lhs_in_seq_for_dce (dce_worklist, *seq);
   gsi_insert_seq_before (gsi, *seq, GSI_SAME_STMT);
   return true;
 }
@@ -6015,6 +6036,8 @@ replace_stmt_with_simplification (gimple_stmt_iterator 
*gsi,
  print_gimple_stmt (dump_file, gsi_stmt (*gsi),
 0, TDF_SLIM);
}
+ // Mark the lhs of the new statements maybe for dce
+ mark_lhs_in_seq_for_dce (dce_worklist, *seq);
  gsi_insert_seq_before (gsi, *seq, GSI_SAME_STMT);
  return true;
}
@@ -6032,6 +6055,8 @@ replace_stmt_with_simplification (gimple_stmt_iterator 
*gsi,
print_gimple_seq (dump_file, *seq, 0, TDF_SLIM);
  print_gimple_stmt (dump_file, gsi_stmt (*gsi), 0, TDF_SLIM);
}
+  // Mark the lhs of the new statements maybe for dce
+  mark_lhs_in_seq_for_dce (dce_worklist, *seq);
   gsi_insert_seq_before (gsi, *seq, GSI_SAME_STMT);
   return true;
 }
@@ -6047,6 +6072,8 @@ replace_stmt_with_simplification (gimple_stmt_iterator 
*gsi,
  fprintf (dump_file, "gimple_simplified to ");
  print_gimple_seq (dump_file, *seq, 0, TDF_SLIM);
}
+ // Mark the lhs of the new statements maybe for dce
+ mark_lhs_in_seq_for_dce (dce_worklist, *seq);
  gsi_replace_with_seq_vops (gsi, *seq);
  return true;
}
@@ -6214,7 +6241,8 @@ maybe_canonicalize_mem_ref_addr (tree *t, bool is_debug = 
false)
distinguishes both cases.  */
 
 static bool
-fold_stmt_1 (gimple_stmt_iterator *gsi, bool inplace, tree (*valueize) (tree))
+fold_stmt_1 (gimple_stmt_iterator *gsi, bool inplace, tree (*valueize) (tree),
+bitmap dce_worklist = nullptr)
 {
   bool changed = false;
   gimple *stmt = gsi_stmt (*gsi);
@@ -6382,7 +6410,8 @@ fold_stmt_1 (gimple_stmt_iterator *gsi, bool inplace, 
tree (*valueize) (tree))
   if (gimple_simplify (stmt, &res_op, inplace ? NULL : &seq,
   valueize, valueize))
{
- if (replace_stmt_with_simplification (gsi, &res_op, &seq, inplace))
+ if (replace_stmt_with_simplification (gsi, &res_op, &seq, inplace,
+   dce_worklist))
changed = true;
  else
gimple_seq_discard (seq);
@@ -

RE: [PATCH v1] RISC-V: Bugfix incorrect operand for vwsll auto-vect

2024-08-17 Thread Li, Pan2

> Thanks.  I've pushed this to the trunk.

Thanks a lot, Jeff.

Pan

-Original Message-
From: Jeff Law  
Sent: Saturday, August 17, 2024 11:27 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v1] RISC-V: Bugfix incorrect operand for vwsll auto-vect



On 8/10/24 6:36 AM, pan2...@intel.com wrote:
> This patch would like to fix one ICE when rv64gcv_zvbb for vwsll.
> Consider below example.
> 
> void vwsll_vv_test (short *restrict dst, char *restrict a,
>  int *restrict b, int n)
> {
>for (int i = 0; i < n; i++)
>  dst[i] = a[i] << b[i];
> }
> 
> It will hit the vwsll pattern with following operands.
> operand 0 -> (reg:RVVMF2HI 146 [ vect__7.13 ])
> operand 1 -> (reg:RVVMF4QI 165 [ vect_cst__33 ])
> operand 2 -> (reg:RVVM1SI 171 [ vect_cst__36 ])
> 
> According to the ISA, operand 2 should be the same as operand 1.
> Aka operand 2 should have RVVMF4QI mode as above.  Thus,  add
> quad truncation for operand 2 before emit vwsll.
> 
> The below test suites are passed for this patch.
> * The rv64gcv fully regression test.
> 
>   PR target/116280
> 
> gcc/ChangeLog:
> 
>   * config/riscv/autovec-opt.md: Add quad truncation to
>   align the mode requirement for vwsll.
> 
> gcc/testsuite/ChangeLog:
> 
>   * gcc.target/riscv/rvv/base/pr116280-1.c: New test.
>   * gcc.target/riscv/rvv/base/pr116280-2.c: New test.
Thanks.  I've pushed this to the trunk.

jeff

RE: [PATCH v4] RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]

2024-08-17 Thread Li, Pan2

> OK.  And I think this shows the basic approach we want to use if there 
> are other builtins that accept sub-word modes.  ie, get the operands 
> into X mode (by extending them as appropriate), then do as much work in 
> X mode as possible, then truncate the result if needed.

> Thanks for your patience on this.

Thanks Jeff for comments and suggestions, I will have a try if we can do some 
combine-like optimization for
the SImode asm in RV64.

Pan

-Original Message-
From: Jeff Law  
Sent: Sunday, August 18, 2024 2:17 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v4] RISC-V: Make sure high bits of usadd operands is clean 
for non-Xmode [PR116278]



On 8/16/24 9:43 PM, pan2...@intel.com wrote:
> From: Pan Li 
> 
> For QI/HImode of .SAT_ADD,  the operands may be sign-extended and the
> high bits of Xmode may be all 1 which is not expected.  For example as
> below code.
> 
> signed char b[1];
> unsigned short c;
> signed char *d = b;
> int main() {
>b[0] = -40;
>c = ({ (unsigned short)d[0] < 0xFFF6 ? (unsigned short)d[0] : 0xFFF6; }) + 
> 9;
>__builtin_printf("%d\n", c);
> }
> 
> After expanding we have:
> 
> ;; _6 = .SAT_ADD (_3, 9);
> (insn 8 7 9 (set (reg:DI 143)
>  (high:DI (symbol_ref:DI ("d") [flags 0x86]  )))
>   (nil))
> (insn 9 8 10 (set (reg/f:DI 142)
>  (mem/f/c:DI (lo_sum:DI (reg:DI 143)
>  (symbol_ref:DI ("d") [flags 0x86]  )) [1 d+0 S8 
> A64]))
>   (nil))
> (insn 10 9 11 (set (reg:HI 144 [ _3 ])
>  (sign_extend:HI (mem:QI (reg/f:DI 142) [0 *d.0_1+0 S1 A8]))) 
> "test.c":7:10 -1
>   (nil))
> 
> The convert from signed char to unsigned short will have sign_extend rtl
> as above.  And finally become the lb insn as below:
> 
> lb  a1,0(a5)   // a1 is -40, aka 0xffd8
> lui a0,0x1a
> addia5,a1,9
> sllia5,a5,0x30
> srlia5,a5,0x30 // a5 is 65505
> sltua1,a5,a1   // compare 65505 and 0xffd8 => TRUE
> 
> The sltu try to compare 65505 and 0xffd8 here,  but we
> actually want to compare 65505 and 65496 (0xffd8).  Thus we need to
> clean up the high bits to ensure this.
> 
> The below test suites are passed for this patch:
> * The rv64gcv fully regression test.
> 
>   PR target/116278
> 
> gcc/ChangeLog:
> 
>   * config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Add new
>   func impl to zero extend rtx.
>   (riscv_expand_usadd): Leverage above func to cleanup operands
>   and sum.
> 
> gcc/testsuite/ChangeLog:
> 
>   * gcc.target/riscv/pr116278-run-1.c: New test.
>   * gcc.target/riscv/pr116278-run-2.c: New test.
> 
>   PR 116278
> 
> gcc/ChangeLog:
> 
>   * config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Add new
>   func impl to zero extend rtx.
>   (riscv_expand_usadd): Leverage above func to cleanup operands 0
>   and remove the special handing for SImode in RV64.
> 
> gcc/testsuite/ChangeLog:
> 
>   * gcc.target/riscv/sat_u_add-11.c: Adjust asm check body.
>   * gcc.target/riscv/sat_u_add-15.c: Ditto.
>   * gcc.target/riscv/sat_u_add-19.c: Ditto.
>   * gcc.target/riscv/sat_u_add-23.c: Ditto.
>   * gcc.target/riscv/sat_u_add-3.c: Ditto.
>   * gcc.target/riscv/sat_u_add-7.c: Ditto.
>   * gcc.target/riscv/sat_u_add_imm-11.c: Ditto.
>   * gcc.target/riscv/sat_u_add_imm-15.c: Ditto.
>   * gcc.target/riscv/sat_u_add_imm-3.c: Ditto.
>   * gcc.target/riscv/sat_u_add_imm-7.c: Ditto.
>   * gcc.target/riscv/pr116278-run-1.c: New test.
>   * gcc.target/riscv/pr116278-run-2.c: New test.
OK.  And I think this shows the basic approach we want to use if there 
are other builtins that accept sub-word modes.  ie, get the operands 
into X mode (by extending them as appropriate), then do as much work in 
X mode as possible, then truncate the result if needed.

Thanks for your patience on this.

Jeff

RE: [PATCH v1] RISC-V: Implement the quad and oct .SAT_TRUNC for scalar

2024-08-17 Thread Li, Pan2

> OK.  Sorry for the delays here.  I wanted to make sure we had the issues 
> WRT operand extension resolved before diving into this.  But in 
> retrospect, this probably could have moved forward independently.

That make much sense to me, thanks a lot.

Pan

-Original Message-
From: Jeff Law  
Sent: Sunday, August 18, 2024 2:21 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v1] RISC-V: Implement the quad and oct .SAT_TRUNC for scalar



On 7/22/24 11:06 PM, pan2...@intel.com wrote:
> From: Pan Li 
> 
> This patch would like to implement the quad and oct .SAT_TRUNC pattern
> in the riscv backend. Aka:
> 
> Form 1:
>#define DEF_SAT_U_TRUC_FMT_1(NT, WT) \
>NT __attribute__((noinline)) \
>sat_u_truc_##WT##_to_##NT##_fmt_1 (WT x) \
>{\
>  bool overflow = x > (WT)(NT)(-1);  \
>  return ((NT)x) | (NT)-overflow;\
>}
> 
> DEF_SAT_U_TRUC_FMT_1(uint16_t, uint64_t)
> 
> Before this patch:
> 4   │ __attribute__((noinline))
> 5   │ uint16_t sat_u_truc_uint64_t_to_uint16_t_fmt_1 (uint64_t x)
> 6   │ {
> 7   │   _Bool overflow;
> 8   │   short unsigned int _1;
> 9   │   short unsigned int _2;
>10   │   short unsigned int _3;
>11   │   uint16_t _6;
>12   │
>13   │ ;;   basic block 2, loop depth 0
>14   │ ;;pred:   ENTRY
>15   │   overflow_5 = x_4(D) > 65535;
>16   │   _1 = (short unsigned int) x_4(D);
>17   │   _2 = (short unsigned int) overflow_5;
>18   │   _3 = -_2;
>19   │   _6 = _1 | _3;
>20   │   return _6;
>21   │ ;;succ:   EXIT
>22   │
>23   │ }
> 
> After this patch:
> 3   │
> 4   │ __attribute__((noinline))
> 5   │ uint16_t sat_u_truc_uint64_t_to_uint16_t_fmt_1 (uint64_t x)
> 6   │ {
> 7   │   uint16_t _6;
> 8   │
> 9   │ ;;   basic block 2, loop depth 0
>10   │ ;;pred:   ENTRY
>11   │   _6 = .SAT_TRUNC (x_4(D)); [tail call]
>12   │   return _6;
>13   │ ;;succ:   EXIT
>14   │
>15   │ }
> 
> The below tests suites are passed for this patch
> 1. The rv64gcv fully regression test.
> 2. The rv64gcv build with glibc
> 
> gcc/ChangeLog:
> 
>   * config/riscv/iterators.md (ANYI_QUAD_TRUNC): New iterator for
>   quad truncation.
>   (ANYI_OCT_TRUNC): New iterator for oct truncation.
>   (ANYI_QUAD_TRUNCATED): New attr for truncated quad modes.
>   (ANYI_OCT_TRUNCATED): New attr for truncated oct modes.
>   (anyi_quad_truncated): Ditto but for lower case.
>   (anyi_oct_truncated): Ditto but for lower case.
>   * config/riscv/riscv.md (ustrunc2):
>   Add new pattern for quad truncation.
>   (ustrunc2): Ditto but for oct.
> 
> gcc/testsuite/ChangeLog:
> 
>   * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Adjust
>   the expand dump check times.
>   * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Ditto.
>   * gcc.target/riscv/sat_arith_data.h: Add test helper macros.
>   * gcc.target/riscv/sat_u_trunc-4.c: New test.
>   * gcc.target/riscv/sat_u_trunc-5.c: New test.
>   * gcc.target/riscv/sat_u_trunc-6.c: New test.
>   * gcc.target/riscv/sat_u_trunc-run-4.c: New test.
>   * gcc.target/riscv/sat_u_trunc-run-5.c: New test.
>   * gcc.target/riscv/sat_u_trunc-run-6.c: New test.
OK.  Sorry for the delays here.  I wanted to make sure we had the issues 
WRT operand extension resolved before diving into this.  But in 
retrospect, this probably could have moved forward independently.

Jeff

[PATCH] c++/modules: Handle transitive reachability for deduction guides [PR116403]

2024-08-17 Thread Nathaniel Shead

Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk?

-- >8 --

Currently we implement [temp.deduct.guide] p1 by forcing all deduction
guides to be considered as exported.  However this is not sufficient:
for transitive non-exported imports we will still hide the deduction
guide from name lookup, causing errors.

This patch instead adjusts name lookup to have a new ANY_REACHABLE flag
to allow for this case.  Currently this is only used by deduction guides
but there are some other circumstances where this may be useful in the
future (e.g. finding existing temploid friends).

PR c++/116403

gcc/cp/ChangeLog:

* pt.cc (deduction_guides_for): Use ANY_REACHABLE for lookup of
deduction guides.
* module.cc (depset::hash::add_deduction_guides): Likewise.
(module_state::write_cluster): No longer override deduction
guides as exported.
* name-lookup.cc (name_lookup::search_namespace_only): Ignore
visibility when LOOK_want::ANY_REACHABLE is specified.
(check_module_override): Ignore visibility when checking for
ambiguating deduction guides.
* name-lookup.h (LOOK_want): New flag 'ANY_REACHABLE'.

gcc/testsuite/ChangeLog:

* g++.dg/modules/dguide-4_a.C: New test.
* g++.dg/modules/dguide-4_b.C: New test.
* g++.dg/modules/dguide-4_c.C: New test.

Signed-off-by: Nathaniel Shead 
---
 gcc/cp/module.cc  |  7 +
 gcc/cp/name-lookup.cc | 38 ++-
 gcc/cp/name-lookup.h  |  5 ++-
 gcc/cp/pt.cc  |  3 +-
 gcc/testsuite/g++.dg/modules/dguide-4_a.C | 18 +++
 gcc/testsuite/g++.dg/modules/dguide-4_b.C |  9 ++
 gcc/testsuite/g++.dg/modules/dguide-4_c.C | 15 +
 7 files changed, 79 insertions(+), 16 deletions(-)
 create mode 100644 gcc/testsuite/g++.dg/modules/dguide-4_a.C
 create mode 100644 gcc/testsuite/g++.dg/modules/dguide-4_b.C
 create mode 100644 gcc/testsuite/g++.dg/modules/dguide-4_c.C

diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc
index f4d137b13a1..6eb4cbf2911 100644
--- a/gcc/cp/module.cc
+++ b/gcc/cp/module.cc
@@ -13640,7 +13640,7 @@ depset::hash::add_deduction_guides (tree decl)
   if (find_binding (ns, name))
 return;
 
-  tree guides = lookup_qualified_name (ns, name, LOOK_want::NORMAL,
+  tree guides = lookup_qualified_name (ns, name, LOOK_want::ANY_REACHABLE,
   /*complain=*/false);
   if (guides == error_mark_node)
 return;
@@ -15223,11 +15223,6 @@ module_state::write_cluster (elf_out *to, depset 
*scc[], unsigned size,
  flags |= cbf_hidden;
else if (DECL_MODULE_EXPORT_P (STRIP_TEMPLATE (bound)))
  flags |= cbf_export;
-   else if (deduction_guide_p (bound))
- /* Deduction guides are always exported so that they are
-visible to name lookup whenever their class template
-is reachable.  */
- flags |= cbf_export;
  }
 
gcc_checking_assert (DECL_P (bound));
diff --git a/gcc/cp/name-lookup.cc b/gcc/cp/name-lookup.cc
index 872f1af0b2e..70ad4cbf3b5 100644
--- a/gcc/cp/name-lookup.cc
+++ b/gcc/cp/name-lookup.cc
@@ -916,7 +916,8 @@ name_lookup::search_namespace_only (tree scope)
if (unsigned base = cluster->indices[jx].base)
  if (unsigned span = cluster->indices[jx].span)
do
- if (bitmap_bit_p (imports, base))
+ if (bool (want & LOOK_want::ANY_REACHABLE)
+ || bitmap_bit_p (imports, base))
goto found;
while (++base, --span);
continue;
@@ -960,9 +961,17 @@ name_lookup::search_namespace_only (tree scope)
dup_detect |= dup;
  }
 
-   if (STAT_TYPE_VISIBLE_P (bind))
- type = STAT_TYPE (bind);
-   bind = STAT_VISIBLE (bind);
+   if (bool (want & LOOK_want::ANY_REACHABLE))
+ {
+   type = STAT_TYPE (bind);
+   bind = STAT_DECL (bind);
+ }
+   else
+ {
+   if (STAT_TYPE_VISIBLE_P (bind))
+ type = STAT_TYPE (bind);
+   bind = STAT_VISIBLE (bind);
+ }
  }
 
/* And process it.  */
@@ -3761,6 +3770,10 @@ check_module_override (tree decl, tree mvec, bool hiding,
   tree nontmpl = STRIP_TEMPLATE (decl);
   bool attached = DECL_LANG_SPECIFIC (nontmpl) && DECL_MODULE_ATTACH_P 
(nontmpl);
 
+  /* For deduction guides we don't do normal name lookup, but rather consider
+ any reachable declaration, so we should check for overriding here too.

RE: [PATCH v1] Vect: Promote unsigned .SAT_ADD constant operand for vectorizable_call

2024-08-17 Thread Li, Pan2

Thanks Jakub for explaining.

Hi Richard,

Does it mean we need to do some promotion similar as this patch to make the 
vectorizable_call happy
when there is a constant operand? I am not sure if there is a better approach 
for this case.

Pan 

-Original Message-
From: Jakub Jelinek  
Sent: Sunday, August 18, 2024 5:21 AM
To: Li, Pan2 
Cc: Richard Biener ; gcc-patches@gcc.gnu.org; 
juzhe.zh...@rivai.ai; kito.ch...@gmail.com; tamar.christ...@arm.com; 
jeffreya...@gmail.com; rdapp@gmail.com; Liu, Hongtao 
Subject: Re: [PATCH v1] Vect: Promote unsigned .SAT_ADD constant operand for 
vectorizable_call

On Sat, Aug 17, 2024 at 05:03:14AM +, Li, Pan2 wrote:
> Thanks Richard for confirmation. Sorry almost forget this thread.
> 
> Please feel free to let me know if there is anything I can do to fix this 
> issue. Thanks a lot.

There is no bug.  The operands of .{ADD,SUB,MUL}_OVERFLOW don't have to
have the same type, as described in the
__builtin_{add,sub,mul}_overflow{,_p} documentation, each argument can have
different type and result yet another one, the behavior is then (as if) to
perform the operation in infinite precision and if that result fits into
the result type, there is no overflow, otherwise there is.
So, there is no need to promote anything, promoted constants would have the
same value as the non-promoted ones and the value is all that matters for
constants.

Jakub

[PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2

2024-08-17 Thread pan2 . li

From: Pan Li 

This patch would like to add test cases for the unsigned scalar quad and
oct .SAT_TRUNC form 2.  Aka:

Form 2:
  #define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
  NT __attribute__((noinline)) \
  sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
  {\
WT max = (WT)(NT)-1;   \
return x > max ? (NT) max : (NT)x; \
  }

QUAD:
DEF_SAT_U_TRUC_FMT_2 (uint16_t, uint64_t)
DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint32_t)

OCT:
DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint64_t)

The below test is passed for this patch.
* The rv64gcv regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_u_trunc-10.c: New test.
* gcc.target/riscv/sat_u_trunc-11.c: New test.
* gcc.target/riscv/sat_u_trunc-12.c: New test.
* gcc.target/riscv/sat_u_trunc-run-10.c: New test.
* gcc.target/riscv/sat_u_trunc-run-11.c: New test.
* gcc.target/riscv/sat_u_trunc-run-12.c: New test.

Signed-off-by: Pan Li 
---
 .../gcc.target/riscv/sat_u_trunc-10.c | 17 
 .../gcc.target/riscv/sat_u_trunc-11.c | 17 
 .../gcc.target/riscv/sat_u_trunc-12.c | 20 +++
 .../gcc.target/riscv/sat_u_trunc-run-10.c | 16 +++
 .../gcc.target/riscv/sat_u_trunc-run-11.c | 16 +++
 .../gcc.target/riscv/sat_u_trunc-run-12.c | 16 +++
 6 files changed, 102 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-12.c

diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-10.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-10.c
new file mode 100644
index 000..7dfc740c54f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-10.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint32_t_to_uint8_t_fmt_2:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_2(uint8_t, uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-11.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-11.c
new file mode 100644
index 000..c50ae96f47d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-11.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint64_t_to_uint8_t_fmt_2:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_2(uint8_t, uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-12.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-12.c
new file mode 100644
index 000..61331cee6fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-12.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint64_t_to_uint16_t_fmt_2:
+** li\s+[atx][0-9]+,\s*65536
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_2(uint16_t, uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-10.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-10.c
new file mode 100644
index 000..4bc9303e457
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-10.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 uint8_t
+#define T2 uint32_t
+
+DEF_SAT_U_TRUC_FMT_2_WRAP(T1, T2)
+
+#define DATA   TEST_UNARY_DATA_WRAP(T1, T2)
+#define T

[PATCH v1 2/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3

2024-08-17 Thread pan2 . li

From: Pan Li 

This patch would like to add test cases for the unsigned scalar quad and
oct .SAT_TRUNC form 3.  Aka:

Form 3:
  #define DEF_SAT_U_TRUC_FMT_3(NT, WT) \
  NT __attribute__((noinline)) \
  sat_u_truc_##WT##_to_##NT##_fmt_3 (WT x) \
  {\
WT max = (WT)(NT)-1;   \
return x <= max ? (NT)x : (NT) max;\
  }

QUAD:
DEF_SAT_U_TRUC_FMT_3 (uint16_t, uint64_t)
DEF_SAT_U_TRUC_FMT_3 (uint8_t, uint32_t)

OCT:
DEF_SAT_U_TRUC_FMT_3 (uint8_t, uint64_t)

The below test is passed for this patch.
* The rv64gcv regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_u_trunc-16.c: New test.
* gcc.target/riscv/sat_u_trunc-17.c: New test.
* gcc.target/riscv/sat_u_trunc-18.c: New test.
* gcc.target/riscv/sat_u_trunc-run-16.c: New test.
* gcc.target/riscv/sat_u_trunc-run-17.c: New test.
* gcc.target/riscv/sat_u_trunc-run-18.c: New test.

Signed-off-by: Pan Li 
---
 .../gcc.target/riscv/sat_u_trunc-16.c | 17 
 .../gcc.target/riscv/sat_u_trunc-17.c | 17 
 .../gcc.target/riscv/sat_u_trunc-18.c | 20 +++
 .../gcc.target/riscv/sat_u_trunc-run-16.c | 16 +++
 .../gcc.target/riscv/sat_u_trunc-run-17.c | 16 +++
 .../gcc.target/riscv/sat_u_trunc-run-18.c | 16 +++
 6 files changed, 102 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-17.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-18.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-17.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-18.c

diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-16.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-16.c
new file mode 100644
index 000..3ee7dc03ade
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-16.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint32_t_to_uint8_t_fmt_3:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_3(uint8_t, uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-17.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-17.c
new file mode 100644
index 000..975853712cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-17.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint64_t_to_uint8_t_fmt_3:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_3(uint8_t, uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-18.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-18.c
new file mode 100644
index 000..11e34ae6fd2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-18.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_truc_uint64_t_to_uint16_t_fmt_3:
+** li\s+[atx][0-9]+,\s*65536
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_TRUC_FMT_3(uint16_t, uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-16.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-16.c
new file mode 100644
index 000..3edcf137a79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 uint8_t
+#define T2 uint32_t
+
+DEF_SAT_U_TRUC_FMT_3_WRAP(T1, T2)
+
+#define DATA   TEST_UNARY_DATA_WRAP(T1, T2)
+#define T

Re: [PATCH] forwprop: Also dce from added statements from gimple_simplify

2024-08-17 Thread Richard Biener




> Am 18.08.2024 um 00:57 schrieb Andrew Pinski :
> 
> This extends r14-3982-g9ea74d235c7e78 to also include the newly added 
> statements
> since some of them might be dead too (due to the way match and simplify 
> works).
> This was noticed while working on adding a new match and simplify pattern 
> where a
> new statement that got added was not being used.
> 
> Bootstrapped and tested on x86_64-linux-gnu with no regressions.

Ok

Richard 

> gcc/ChangeLog:
> 
>* gimple-fold.cc (mark_lhs_in_seq_for_dce): New function.
>(replace_stmt_with_simplification): Call mark_lhs_in_seq_for_dce
>right before inserting the sequence.
>(fold_stmt_1): Add dce_worklist argument, update call to
>replace_stmt_with_simplification.
>(fold_stmt): Add dce_worklist argument, update call to fold_stmt_1.
>(fold_stmt_inplace): Update call to fold_stmt_1.
>* gimple-fold.h (fold_stmt): Add bitmap argument.
>* tree-ssa-forwprop.cc (pass_forwprop::execute): Update call to fold_stmt.
> 
> Signed-off-by: Andrew Pinski 
> ---
> gcc/gimple-fold.cc   | 43 +---
> gcc/gimple-fold.h|  4 ++--
> gcc/tree-ssa-forwprop.cc |  2 +-
> 3 files changed, 39 insertions(+), 10 deletions(-)
> 
> diff --git a/gcc/gimple-fold.cc b/gcc/gimple-fold.cc
> index 18d7a6b176d..0bec35d06f6 100644
> --- a/gcc/gimple-fold.cc
> +++ b/gcc/gimple-fold.cc
> @@ -5914,6 +5914,24 @@ has_use_on_stmt (tree name, gimple *stmt)
>   return false;
> }
> 
> +/* Add the lhs of each statement of SEQ to DCE_WORKLIST. */
> +
> +static void
> +mark_lhs_in_seq_for_dce (bitmap dce_worklist, gimple_seq seq)
> +{
> +  if (!dce_worklist)
> +return;
> +
> +  for (gimple_stmt_iterator i = gsi_start (seq);
> +   !gsi_end_p (i); gsi_next (&i))
> +{
> +  gimple *stmt = gsi_stmt (i);
> +  tree name = gimple_get_lhs (stmt);
> +  if (name && TREE_CODE (name) == SSA_NAME)
> +bitmap_set_bit (dce_worklist, SSA_NAME_VERSION (name));
> +}
> +}
> +
> /* Worker for fold_stmt_1 dispatch to pattern based folding with
>gimple_simplify.
> 
> @@ -5924,7 +5942,8 @@ has_use_on_stmt (tree name, gimple *stmt)
> static bool
> replace_stmt_with_simplification (gimple_stmt_iterator *gsi,
>  gimple_match_op *res_op,
> -  gimple_seq *seq, bool inplace)
> +  gimple_seq *seq, bool inplace,
> +  bitmap dce_worklist)
> {
>   gimple *stmt = gsi_stmt (*gsi);
>   tree *ops = res_op->ops;
> @@ -5992,6 +6011,8 @@ replace_stmt_with_simplification (gimple_stmt_iterator 
> *gsi,
>  print_gimple_stmt (dump_file, gsi_stmt (*gsi),
> 0, TDF_SLIM);
>}
> +  // Mark the lhs of the new statements maybe for dce
> +  mark_lhs_in_seq_for_dce (dce_worklist, *seq);
>   gsi_insert_seq_before (gsi, *seq, GSI_SAME_STMT);
>   return true;
> }
> @@ -6015,6 +6036,8 @@ replace_stmt_with_simplification (gimple_stmt_iterator 
> *gsi,
>  print_gimple_stmt (dump_file, gsi_stmt (*gsi),
> 0, TDF_SLIM);
>}
> +  // Mark the lhs of the new statements maybe for dce
> +  mark_lhs_in_seq_for_dce (dce_worklist, *seq);
>  gsi_insert_seq_before (gsi, *seq, GSI_SAME_STMT);
>  return true;
>}
> @@ -6032,6 +6055,8 @@ replace_stmt_with_simplification (gimple_stmt_iterator 
> *gsi,
>print_gimple_seq (dump_file, *seq, 0, TDF_SLIM);
>  print_gimple_stmt (dump_file, gsi_stmt (*gsi), 0, TDF_SLIM);
>}
> +  // Mark the lhs of the new statements maybe for dce
> +  mark_lhs_in_seq_for_dce (dce_worklist, *seq);
>   gsi_insert_seq_before (gsi, *seq, GSI_SAME_STMT);
>   return true;
> }
> @@ -6047,6 +6072,8 @@ replace_stmt_with_simplification (gimple_stmt_iterator 
> *gsi,
>  fprintf (dump_file, "gimple_simplified to ");
>  print_gimple_seq (dump_file, *seq, 0, TDF_SLIM);
>}
> +  // Mark the lhs of the new statements maybe for dce
> +  mark_lhs_in_seq_for_dce (dce_worklist, *seq);
>  gsi_replace_with_seq_vops (gsi, *seq);
>  return true;
>}
> @@ -6214,7 +6241,8 @@ maybe_canonicalize_mem_ref_addr (tree *t, bool is_debug 
> = false)
>distinguishes both cases.  */
> 
> static bool
> -fold_stmt_1 (gimple_stmt_iterator *gsi, bool inplace, tree (*valueize) 
> (tree))
> +fold_stmt_1 (gimple_stmt_iterator *gsi, bool inplace, tree (*valueize) 
> (tree),
> + bitmap dce_worklist = nullptr)
> {
>   bool changed = false;
>   gimple *stmt = gsi_stmt (*gsi);
> @@ -6382,7 +6410,8 @@ fold_stmt_1 (gimple_stmt_iterator *gsi, bool inplace, 
> tree (*valueize) (tree))
>   if (gimple_simplify (stmt, &res_op, inplace ? NULL : &seq,
>   valueize, valueize))
>{
> -  if (replace_stmt_with_simplification (gsi, &res_op, &seq, inplace))
> +  if (replace_stmt_with_simplification (gsi, &res_op, &seq, inplace,
> +dce_worklist))
>changed = true;
>  else
>gimple_seq_discard (

[pushed] wwwdocs: doc: Tweak link to gm2 list archive

[patch,avr,applied] Fix PR116390

[PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2

[PATCH v1 2/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3

Re: [PATCH, gfortran] libgfortran: implement fpu-macppc for Darwin, support IEEE arithmetic

[pushed] libstdc++: Tweak links to installation docs

[pushed] doc: Tweak PIM4 link

[PATCH] c++/modules: Disable streaming definitions of non-vague-linkage GMF decls [PR115020]

[pushed] libstdc++: Update references to gcc.gnu.org/onlinedocs

[pushed] wwwdocs: gcc-15: Mark an AVR instruction up as

Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2

Re: [PATCH v1 2/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3

Re: [PATCH v2] RISC-V: Add auto-vect pattern for vector rotate shift

Re: [PATCH v1] RISC-V: Bugfix incorrect operand for vwsll auto-vect

Re: [PATCH v1] RISC-V: Bugfix incorrect operand for vwsll auto-vect

Re: [PATCH v2] RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker

Re: [pushed] wwwdocs: gcc-15: Mark an AVR instruction up as

Re: [PATCH v2] RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics

[committed] Adjust v850 rotate expander to allow more cases for V850E3V5

Re: [PATCH v4] RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]

Re: [PATCH v1] RISC-V: Implement the quad and oct .SAT_TRUNC for scalar

Re: [PATCH] t-rtems: add rv32imf architecture to the RTEMS multilib for RISC-V

[committed] Avoid right shifting signed value on ext-dce.cc

RE: [PATCH v1] Vect: Promote unsigned .SAT_ADD constant operand for vectorizable_call

Re: [PATCH v1] Vect: Promote unsigned .SAT_ADD constant operand for vectorizable_call

[PATCH] forwprop: Also dce from added statements from gimple_simplify

RE: [PATCH v1] RISC-V: Bugfix incorrect operand for vwsll auto-vect

RE: [PATCH v4] RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]

RE: [PATCH v1] RISC-V: Implement the quad and oct .SAT_TRUNC for scalar

[PATCH] c++/modules: Handle transitive reachability for deduction guides [PR116403]

RE: [PATCH v1] Vect: Promote unsigned .SAT_ADD constant operand for vectorizable_call

[PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2

[PATCH v1 2/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3

Re: [PATCH] forwprop: Also dce from added statements from gimple_simplify

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