Re: [PATCH v1] RISC-V: Bugfix incorrect operand for vwsll auto-vect

[Jeff Law]

On 8/10/24 6:36 AM, pan2...@intel.com wrote:

This patch would like to fix one ICE when rv64gcv_zvbb for vwsll.
Consider below example.

void vwsll_vv_test (short *restrict dst, char *restrict a,
                     int *restrict b, int n)
{
   for (int i = 0; i < n; i++)
     dst[i] = a[i] << b[i];
}

It will hit the vwsll pattern with following operands.
operand 0 -> (reg:RVVMF2HI 146 [ vect__7.13 ])
operand 1 -> (reg:RVVMF4QI 165 [ vect_cst__33 ])
operand 2 -> (reg:RVVM1SI 171 [ vect_cst__36 ])

According to the ISA, operand 2 should be the same as operand 1.
Aka operand 2 should have RVVMF4QI mode as above.  Thus,  add
quad truncation for operand 2 before emit vwsll.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

        PR target/116280

gcc/ChangeLog:

        * config/riscv/autovec-opt.md: Add quad truncation to
        align the mode requirement for vwsll.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/pr116280-1.c: New test.
        * gcc.target/riscv/rvv/base/pr116280-2.c: New test.

Thanks.  I've pushed this to the trunk.

jeff