Re: [PATCH v2] RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics

[Jeff Law]

On 8/7/24 9:01 PM, Jin Ma wrote:

When rs1 is the immediate 0, the following ICE occurs:

error: unrecognizable insn:
(insn 8 5 12 2 (set (reg:RVVM1DI 134 [ <retval> ])
         (if_then_else:RVVM1DI (unspec:RVVMF64BI [
                     (const_vector:RVVMF64BI repeat [
                             (const_int 1 [0x1])
                        ])
                     (reg/v:DI 137 [ vl ])
                     (const_int 2 [0x2]) repeated x2
                     (const_int 0 [0])
                     (reg:SI 66 vl)
                     (reg:SI 67 vtype)
                 ] UNSPEC_VPREDICATE)
             (plus:RVVM1DI (mult:RVVM1DI (vec_duplicate:RVVM1DI (const_int 0 
[0]))
                     (reg/v:RVVM1DI 136 [ vs2 ]))
                 (reg/v:RVVM1DI 135 [ vd ]))
             (reg/v:RVVM1DI 135 [ vd ])))

gcc/ChangeLog:

        * config/riscv/vector.md: Allow scalar operand to be 0.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/bug-7.c: New test.
        * gcc.target/riscv/rvv/base/bug-8.c: New test.

Thanks.  I pushed this to the trunk.

Jeff