[PATCH 1/2] drm/rockchip: vop: Do check if an update is pending during disable

[Mark yao]

On 2016年04月08日 18:54, Tomeu Vizoso wrote:
> On 8 April 2016 at 03:07, Mark yao  wrote:
>> On 2016年04月06日 18:14, Tomeu Vizoso wrote:
>>
>> When a plane is being disabled but it's still enabled, do check if the
>> previous update has been completed by reading yrgb_mst back.
>>
>> Otherwise, pending pageflips would remain pending after a CRTC is
>> disabled.
>>
>> Signed-off-by: Tomeu Vizoso 
>> ---
>>   drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 5 +++--
>>   1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>> index a9b1e8b5ac85..f46b1fd1887b 100644
>> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>> @@ -1064,8 +1064,9 @@ static bool vop_win_pending_is_complete(struct vop_win
>> *vop_win)
>>struct vop_plane_state *state = to_vop_plane_state(plane->state);
>>dma_addr_t yrgb_mst;
>>
>> - if (!state->enable)
>> - return VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0;
>> + if (!state->enable &&
>> +VOP_WIN_GET(vop_win->vop, vop_win->data, enable) == 0)
>> + return true;
>>
>>
>> It is wrong, the patch would cause a bug.
>>
>> when state->enable is 0, check yrgb_mst == state->yrgb_mst always be true,
>> because state->yrgb_mst not update on plane disabled funtion, that would
>> cause iommu crash.
> Sorry, but I don't understand where's the bug and what could cause
> that crash. What the existing code was doing is saying that a pageflip
> event is still pending if we have told the plane to disable but for
> some reason it hasn't yet.
>
> With this modification, if we read back that it's already disabled, we
> return true as before. But if we read back that it isn't disabled yet,
> then we still check the fb pointers and compare them.
>
> The iommu mapping is removed when the _CRTC_ is disabled, and what
> this series does is to wait for the pending pageflip to finish before
> conitnuing with CRTC disablement.

the iommu mapping will unmap after plane disabled, we need sure that the 
plane really disabled before unmap, if not, the unmap may call before 
plane really disable, vop may access unmap address, then would get iommu 
page fault.

>> About pending pageflips would remain pending, can you  describe more info
>> about it? I think those pending pageflips should be ignore when CRTC is
>> disabled.
> Well, right now in rockchip-drm pending pageflips won't be ignored
> when a CRTC is disabled, but will be delivered when it's re-enabled.
>
> If they would be to be ignored (understanding that as dropped), that
> would require modifications to clients so they keep track of which fbs
> were used in a particular crtc and destroy them when the crtc is
> disabled, but that would be incorrect when using the i915 DRM driver
> (I also assume others do the same). Given that the pageflip ioctl
> isn't driver-specific, I think there cannot be such a difference in
> behavior between drivers.
>
> With the current behavior (pending pageflip events being delayed until
> the CRTC is enabled again), compositors and other clients will be
> holding on to the fb in the pending pageflip until an arbitrary point
> in the future that may not ever come. To me that sounds like a serious
> modification of the assumptions on fb lifecycle that might not be
> warranted.
>
> So in summary, even if I haven't found any explicit documentation on
> this, I think the ABI is that any pending pageflips are to be
> delivered when that CRTC is being disabled and not later.

on drivers/gpu/drm/rockchip/rockchip_drm_fb.c

drm_atomic_helper_commit_planes(dev, state, true);
rockchip_atomic_wait_for_complete(dev, state);

We set active_only = true, I think planes can only update when crtc is 
active. and rockchip_atomic_wait_for_complete only wait when crtc is active.

Thanks.
> Thanks,
>
> Tomeu
>
>> Thanks.
>>
>>
>>yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
>>
>>
>>
>> --
>> ï¼­ark Yao
>>
>>
>> ___
>> dri-devel mailing list
>> dri-devel at lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>>
>
>


-- 
ï¼­ark Yao

[PATCH 1/2] drm/rockchip: remove redundant statement

[Mark yao]

On 2016年04月05日 21:50, John Keeping wrote:
> The call to arm_iommu_detach_device() on the previous line sets
> dev->archdata.mapping to NULL so this call is always a no-op.
>
> Signed-off-by: John Keeping 
> ---
>   drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 -
>   1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c 
> b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
> index f556a8f..7695c79 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
> @@ -244,7 +244,6 @@ static int rockchip_drm_unload(struct drm_device *drm_dev)
>   drm_kms_helper_poll_fini(drm_dev);
>   component_unbind_all(dev, drm_dev);
>   arm_iommu_detach_device(dev);
> - arm_iommu_release_mapping(dev->archdata.mapping);
>   drm_mode_config_cleanup(drm_dev);
>   drm_dev->dev_private = NULL;
>   
Applied to my drm-fixes

Thanks.:-)

-- 
ï¼­ark Yao

[PATCH 2/2] drm/rockchip: don't leak iommu mapping

[Mark yao]

On 2016年04月05日 21:50, John Keeping wrote:
> arm_iommu_attach_device() takes its own reference to the mapping we give
> it.  Since we do not keep a reference to the mapping ourselves, we must
> release it before returning.
>
> Also fix the error path, which fails to release the mapping if it has
> called arm_iommu_detach_device() since that clears archdata.mapping.
>
> Signed-off-by: John Keeping 
> ---
>   drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c 
> b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
> index 7695c79..1e2d88b 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
> @@ -218,6 +218,7 @@ static int rockchip_drm_load(struct drm_device *drm_dev, 
> unsigned long flags)
>   if (ret)
>   goto err_vblank_cleanup;
>   
> + arm_iommu_release_mapping(mapping);
>   return 0;
>   err_vblank_cleanup:
>   drm_vblank_cleanup(drm_dev);
> @@ -228,7 +229,7 @@ err_unbind:
>   err_detach_device:
>   arm_iommu_detach_device(dev);
>   err_release_mapping:
> - arm_iommu_release_mapping(dev->archdata.mapping);
> + arm_iommu_release_mapping(mapping);
>   err_config_cleanup:
>   drm_mode_config_cleanup(drm_dev);
>   drm_dev->dev_private = NULL;
Applied to my drm-fixes

Thanks.

-- 
ï¼­ark Yao

Nouveau crashes in 4.6-rc on arm64

[Alexandre Courbot]

Hi Robin,

On 04/09/2016 03:46 AM, Robin Murphy wrote:
> Hi Alex,
>
> On 08/04/16 05:47, Alexandre Courbot wrote:
>> Hi Robin,
>>
>> On 04/07/2016 08:50 PM, Robin Murphy wrote:
>>> Hello,
>>>
>>> With 4.6-rc2 (and -rc1) I'm seeing Nouveau blowing up at boot, from the
>>> look of it by dereferencing some offset from NULL inside
>>> nouveau_fbcon_imageblit(). My setup is an old XFX 7600GT card plugged
>>> into an ARM Juno r1 board, which works fine with 4.5 and earlier.
>>>
>>> Attached are a couple of logs from booting arm64 defconfig plus DRM and
>>> Nouveau enabled - the second also has framebuffer console rotation
>>> turned on, which interestingly seems to move the point of failure, and
>>> the display does eventually come up to show the tail end of the panic in
>>> that case.
>>>
>>> I might be able to find time for a full bisection next week if isn't
>>> something sufficiently obvious to anyone who knows this driver.
>>
>> Looking at the log it is not clear to me what could be causing this. I
>> can boot 4.6-rc2 with a GM206 card without any issue. A bisect would
>> indeed be useful here.
>
> OK, turns out the lure of writing something to remotely drive a Juno and
> parse kernel bootlogs through an automatic bisection was too great to
> resist on a Friday afternoon :D
>
> Bisection came down to 1733a2ad3674("drm/nouveau/device/pci: set as
> non-CPU-coherent on ARM64"), and sure enough reverting that removes the
> crash.

Thanks for taking the time to bisect this. And apologies as it seems my 
commit is the reason for your troubles.

The CPU coherency flag is used for two things: explicitly sync buffers 
pages when required, and allocating buffers that are not explicitly 
synced (like fences or pushbuffers) using the DMA API. For this latter 
use, it also accesses the buffer's content using the mapping provided by 
dma_alloc_coherent() instead of creating a new one. All nouveau_bos are 
supposed to be written using nouveau_bo_rd32(), and this function 
handles the case of an DMA-API allocated object by detecting that the 
result of ttm_kmap_obj_virtual() is NULL.

But as it turns out, OUT_RINGp() also calls ttm_kmap_obj_virtual() in 
order to perform a memcpy and uses its result directly - which means we 
are doing memcpy on a NULL pointer. We never caught this because we 
typically do not use Nouveau's fbcon with an ARM setup.

I don't really like this special access for coherent objects, and 
actually had a patch in my tree to attempt to remove it (attached). 
Although it is not the whole solution (see below), the issue should at 
least not be visible with it applied - could you confirm?

> I have to say, that commit looks pretty bogus anyway - since
> de335bb49269("PCI: Update DMA configuration from DT") in 4.1, PCI
> devices should correctly inherit the coherency property from their host
> controller's DT node and get the appropriate DMA ops assigned. From a
> brief look at the Nouveau code, I guess it could possibly be the
> assumptions the TTM stuff going awry in the presence of coherent DMA
> ops. Regardless of how the code goes wrong, though, it's trivially
> incorrect to have a blanket statement that PCI devices are non-coherent
> on arm64, so whatever the original issue was this isn't the right way to
> fix it.

You are absolutely right and this needs to be fixed. We still need to 
know about the bus coherency to avoid calling the page sync functions 
when they are not needed though. Is there a way for us to query the bus 
at runtime and know whether it is cpu-coherent or not?

... or maybe we could just unconditionally sync all buffers and let the 
DMA API abstract this away. My concern is that on coherent architectures 
we would still need to loop over all the pages for nothing, as I don't 
think the loop (see e.g. nouveau_bo_sync_for_cpu in nouveau_bo.c) can be 
optimized away by the compiler.

Thanks,
Alex.

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[PATCH] drm/core: Do not preserve framebuffer on rmfb, v3.

[Maarten Lankhorst]

Op 31-03-16 om 13:26 schreef Maarten Lankhorst:
> It turns out that preserving framebuffers after the rmfb call breaks
> vmwgfx userspace. This was originally introduced because it was thought
> nobody relied on the behavior, but unfortunately it seems there are
> exceptions.
>
> drm_framebuffer_remove may fail with -EINTR now, so a straight revert
> is impossible. There is no way to remove the framebuffer from the lists
> and active planes without introducing a race because of the different
> locking requirements. Instead call drm_framebuffer_remove from a
> workqueue, which is unaffected by signals.
>
Ping?

[PATCH 1/6] drm/amd: Mark some tables as const

[Christian König]

Am 10.04.2016 um 16:29 schrieb Nils Wallménius:
> This patch marks some compile-time constant tables 'const'.
> The tables marked in this patch are the low hanging fruit
> where little other changes were necesary to avoid casting
> away constness etc. Also mark some tables that are private
> to a file as static.
>
> Signed-off-by: Nils Wallménius 

Nice cleanup, for the series Reviewed-by: Christian König 


Thanks,
Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_display.c  |  6 +++---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  |  2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c  |  2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c  |  2 +-
>   drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 12 ++--
>   drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h |  2 +-
>   drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c | 10 +-
>   drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c|  8 
>   drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h|  2 +-
>   drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c |  2 +-
>   drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c   |  6 +++---
>   drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c  |  2 +-
>   13 files changed, 29 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 66e51f9..5d05b5d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -2348,7 +2348,7 @@ static inline void amdgpu_unregister_atpx_handler(void) 
> {}
>* KMS
>*/
>   extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
> -extern int amdgpu_max_kms_ioctl;
> +extern const int amdgpu_max_kms_ioctl;
>   
>   int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
>   int amdgpu_driver_unload_kms(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 0535095..c835abe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -596,20 +596,20 @@ const struct drm_mode_config_funcs amdgpu_mode_funcs = {
>   .output_poll_changed = amdgpu_output_poll_changed
>   };
>   
> -static struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
> +static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
>   {   { UNDERSCAN_OFF, "off" },
>   { UNDERSCAN_ON, "on" },
>   { UNDERSCAN_AUTO, "auto" },
>   };
>   
> -static struct drm_prop_enum_list amdgpu_audio_enum_list[] =
> +static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
>   {   { AMDGPU_AUDIO_DISABLE, "off" },
>   { AMDGPU_AUDIO_ENABLE, "on" },
>   { AMDGPU_AUDIO_AUTO, "auto" },
>   };
>   
>   /* XXX support different dither options? spatial, temporal, both, etc. */
> -static struct drm_prop_enum_list amdgpu_dither_enum_list[] =
> +static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
>   {   { AMDGPU_FMT_DITHER_DISABLE, "off" },
>   { AMDGPU_FMT_DITHER_ENABLE, "on" },
>   };
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index f1e17d6..2d9dbc2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -166,7 +166,7 @@ module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, 
> uint, 0444);
>   MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
>   module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
>   
> -static struct pci_device_id pciidlist[] = {
> +static const struct pci_device_id pciidlist[] = {
>   #ifdef CONFIG_DRM_AMDGPU_CIK
>   /* Kaveri */
>   {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 
> CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index 762cfdb..9266c7b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -498,7 +498,7 @@ static int amdgpu_irqdomain_map(struct irq_domain *d,
>   return 0;
>   }
>   
> -static struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
> +static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
>   .map = amdgpu_irqdomain_map,
>   };
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 7805a87..1f9d318 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -754,4 +754,4 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
>   DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, 
> DRM_AUTH|DRM_RENDER_ALLOW),
>   DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, 
> DRM_AUTH|DRM_RENDER_ALLOW),
>   };
> -int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
>

[Bug 116101] "RIP radeon_gem_va_ioctl+0x35/0x650", "Userspace still has active objects", and "trying to unbind memory from uninitialized GART !" when unbinding from radeon

[bugzilla-dae...@bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=116101

Christian König  changed:

   What|Removed |Added

 CC||deathsimple at vodafone.de

--- Comment #1 from Christian König  ---
Well as the error message already suggests "Userspace still has active objects
!" you have an application which is still using the hardware.

So unbinding and rebinding it to the isn't possible in this state.

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Nouveau crashes in 4.6-rc on arm64

[Alexandre Courbot]

On 04/11/2016 04:22 PM, Alexandre Courbot wrote:
> ... or maybe we could just unconditionally sync all buffers and let the
> DMA API abstract this away. My concern is that on coherent architectures
> we would still need to loop over all the pages for nothing, as I don't
> think the loop (see e.g. nouveau_bo_sync_for_cpu in nouveau_bo.c) can be
> optimized away by the compiler.

Looking at the code it actually turns out we are already calling the 
sync functions on coherent buses anyway, so maybe we have little reasons 
to keep this at all?

[alsa-devel] [PATCH 2/5 v4] drm/i2c/adv7511: Add audio support

[Lars-Peter Clausen]

On 04/11/2016 11:27 AM, Jose Abreu wrote:
> Hi Lars,
> 
> 
> On 09-04-2016 16:02, Lars-Peter Clausen wrote:
>> On 04/08/2016 06:12 PM, Jose Abreu wrote:
>> [...]
 [...]
> +- adi,enable-audio: If set the ADV7511 driver will register a codec 
> interface
> +  into ALSA SoC.
 This is not a description of the hardware.
>>> Is this okay: "adi,enable-audio: Set this boolean parameter if ADV7511
>>> transmitter routes audio signals" ?
>> I don't think we need this property. There is no problem with registering
>> the audio part unconditionally. As long as there is no connection we wont
>> create a sound card that is exposed to userspace.
>>
> 
> This change was suggested by Laurent Pinchart and was introduced in v3. 
> Quoting
> Laurent:
> "The idea is that enabling support for ADV7511 audio in the kernel isn't 
> coupled
> with whether the system includes audio support. It would be confusing, and 
> would
> also waste resources, to create a Linux sound device when no sound channel is
> routed on the board."

I wouldn't care too much about this at this point, the extra amount of
resources required for registering the CODEC (but not the sound card) is
just a few bytes (sizeof(struct snd_soc_codec)).

Nevertheless what we should do is describe the hardware and from this
information infer whether there is a audio connection or not and if there is
none we might skip registering the CODEC. In my opinion this hardware
description should be modeled using of-graph, having a connection between
the SoC side and the adv7511 SPDIF or I2S port.

[PATCH v2] drm/core: Add drm_accurate_vblank_count_and_time, v2.

[Maarten Lankhorst]

This function is useful for gen2 intel devices which have no frame
counter, but need a way to determine the current vblank count without
racing with the vblank interrupt handler.

intel_pipe_update_start checks if no vblank interrupt will occur
during vblank evasion, but cannot check whether the vblank handler has
run to completion. This function uses the timestamps to determine
when the last vblank has happened, and interpolates from there.

Changes since v1:
- Take vblank_time_lock and don't use drm_vblank_count_and_time.

Cc: Mario Kleiner 
Cc: Ville Syrjälä 
Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/drm_irq.c | 31 +++
 include/drm/drmP.h|  2 ++
 2 files changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index 3c1a6f18e71c..d3cecc1932e1 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -303,6 +303,37 @@ static void drm_update_vblank_count(struct drm_device 
*dev, unsigned int pipe,
store_vblank(dev, pipe, diff, &t_vblank, cur_vblank);
 }

+/**
+ * drm_accurate_vblank_count_and_time - retrieve the master vblank counter
+ * @crtc: which counter to retrieve
+ * @tv_ret: last time counter was updated
+ *
+ * This function is similar to @drm_update_vblank_count_and_time but
+ * this function interpolates to handle a race with vblank irq's, and
+ * is only useful for crtc's that have no hw vblank counter.
+ */
+
+u32 drm_accurate_vblank_count_and_time(struct drm_crtc *crtc,
+  struct timeval *tv_ret)
+{
+   struct drm_device *dev = crtc->dev;
+   u32 vblank, pipe = drm_crtc_index(crtc);
+   unsigned long flags;
+
+   WARN(dev->max_vblank_count, "This function is only useful when a hw 
counter is unavailable.");
+
+   spin_lock_irqsave(&dev->vblank_time_lock, flags);
+   drm_update_vblank_count(dev, pipe, 0);
+
+   vblank = dev->vblank[pipe].count;
+   *tv_ret = vblanktimestamp(dev, pipe, vblank);
+
+   spin_unlock_irqrestore(&dev->vblank_time_lock, flags);
+
+   return vblank;
+}
+EXPORT_SYMBOL(drm_accurate_vblank_count_and_time);
+
 /*
  * Disable vblank irq's on crtc, make sure that last vblank count
  * of hardware and corresponding consistent software vblank counter
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 31483c2fef51..1df65922c7c6 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -995,6 +995,8 @@ extern void drm_crtc_vblank_off(struct drm_crtc *crtc);
 extern void drm_crtc_vblank_reset(struct drm_crtc *crtc);
 extern void drm_crtc_vblank_on(struct drm_crtc *crtc);
 extern void drm_vblank_cleanup(struct drm_device *dev);
+extern u32 drm_accurate_vblank_count_and_time(struct drm_crtc *crtc,
+ struct timeval *tv_ret);
 extern u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int pipe);

 extern int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev,
-- 
2.1.0

[PATCH v3 5/5] [media] imx-ipu: Add i.MX IPUv3 scaler driver

[Jean-Michel Hautbois]

Hi Philipp,

2015-10-02 10:37 GMT+02:00 Philipp Zabel :

> Hi Jean-Michel,
>
> Am Donnerstag, den 01.10.2015, 09:55 +0200 schrieb Jean-Michel Hautbois:
> > Hi Philipp, Hans,
> >
> >
> > 2015-07-24 17:12 GMT+02:00 Hans Verkuil :
> [...]
> > What is the status of this driver ?
> > I can test it here, Philipp, are you planning to take Hans remarks
> > into account in one of your trees ?
>
> Thank you for the reminder!
>
> I have fixed most of the issues Hans pointed out, but got distracted at
> some point and left for other things. I'll prepare a new version of this
> series.
>

Let's try another reminder ? :)

Thanks,
JM
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[PATCH] drm: atomic: fix legacy gamma set helper

[Lionel Landwerlin]

Color management properties are a bit of an odd use case because
they're not marked as atomic properties. Currently we're not updating
the non atomic values so the drm_crtc_state is out of sync with the
values stored in the crtc object.

v2: Update non atomic values only if commit succeeds (Bob Paauwe)

Cc: Maarten Lankhorst 
Cc: Bob Paauwe 
Cc: 
Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/drm_atomic_helper.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index 7bf678e..65e55ce 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -2979,6 +2979,14 @@ retry:
if (ret)
goto fail;

+   drm_object_property_set_value(&crtc->base,
+   config->degamma_lut_property, 0);
+   drm_object_property_set_value(&crtc->base,
+   config->ctm_property, 0);
+   drm_object_property_set_value(&crtc->base,
+   config->gamma_lut_property,
+   crtc_state->gamma_lut->base.id);
+
/* Driver takes ownership of state on successful commit. */

drm_property_unreference_blob(blob);
-- 
2.8.0.rc3

[PATCH] drm: atomic: fix legacy gamma set helper

[Maarten Lankhorst]

Op 11-04-16 om 12:37 schreef Lionel Landwerlin:
> Color management properties are a bit of an odd use case because
> they're not marked as atomic properties. Currently we're not updating
> the non atomic values so the drm_crtc_state is out of sync with the
> values stored in the crtc object.
>
> v2: Update non atomic values only if commit succeeds (Bob Paauwe)
>
> Cc: Maarten Lankhorst 
> Cc: Bob Paauwe 
> Cc: 
> Signed-off-by: Lionel Landwerlin 
> ---
>  drivers/gpu/drm/drm_atomic_helper.c | 8 
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
> b/drivers/gpu/drm/drm_atomic_helper.c
> index 7bf678e..65e55ce 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -2979,6 +2979,14 @@ retry:
>   if (ret)
>   goto fail;
>  
> + drm_object_property_set_value(&crtc->base,
> + config->degamma_lut_property, 0);
> + drm_object_property_set_value(&crtc->base,
> + config->ctm_property, 0);
> + drm_object_property_set_value(&crtc->base,
> + config->gamma_lut_property,
> + crtc_state->gamma_lut->base.id);
> +
>   /* Driver takes ownership of state on successful commit. */
>  
>   drm_property_unreference_blob(blob);
You can't use crtc_state after drm_atomic_commit as it's freed, you need to use 
crtc->state.

[RESEND] fence: add missing descriptions for fence

[Luis de Bethencourt]

The members child_list and active_list were added to the fence struct
without descriptions for the Documentation. Adding these.

Fixes: b55b54b5db33 ("staging/android: remove struct sync_pt")
Signed-off-by: Luis de Bethencourt 
Reviewed-by: Javier Martinez Canillas 
---
Hi,

Just resending this patch since it hasn't had any reviews in since
March 21st.

Thanks,
Luis

 include/linux/fence.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/fence.h b/include/linux/fence.h
index 2b17698..2056e9f 100644
--- a/include/linux/fence.h
+++ b/include/linux/fence.h
@@ -49,6 +49,8 @@ struct fence_cb;
  * @timestamp: Timestamp when the fence was signaled.
  * @status: Optional, only valid if < 0, must be set before calling
  * fence_signal, indicates that the fence has completed with an error.
+ * @child_list: list of children fences
+ * @active_list: list of active fences
  *
  * the flags member must be manipulated and read using the appropriate
  * atomic ops (bit_*), so taking the spinlock will not be needed most
-- 
2.6.4

[alsa-devel] [PATCH 2/5 v4] drm/i2c/adv7511: Add audio support

[Lars-Peter Clausen]

On 04/11/2016 01:32 PM, Jose Abreu wrote:
> Hi Lars,
> 
> 
> On 11-04-2016 10:33, Lars-Peter Clausen wrote:
>> On 04/11/2016 11:27 AM, Jose Abreu wrote:
>>> Hi Lars,
>>>
>>>
>>> On 09-04-2016 16:02, Lars-Peter Clausen wrote:
 On 04/08/2016 06:12 PM, Jose Abreu wrote:
 [...]
>> [...]
>>> +- adi,enable-audio: If set the ADV7511 driver will register a codec 
>>> interface
>>> +  into ALSA SoC.
>> This is not a description of the hardware.
> Is this okay: "adi,enable-audio: Set this boolean parameter if ADV7511
> transmitter routes audio signals" ?
 I don't think we need this property. There is no problem with registering
 the audio part unconditionally. As long as there is no connection we wont
 create a sound card that is exposed to userspace.

>>> This change was suggested by Laurent Pinchart and was introduced in v3. 
>>> Quoting
>>> Laurent:
>>> "The idea is that enabling support for ADV7511 audio in the kernel isn't 
>>> coupled
>>> with whether the system includes audio support. It would be confusing, and 
>>> would
>>> also waste resources, to create a Linux sound device when no sound channel 
>>> is
>>> routed on the board."
>> I wouldn't care too much about this at this point, the extra amount of
>> resources required for registering the CODEC (but not the sound card) is
>> just a few bytes (sizeof(struct snd_soc_codec)).
>>
>> Nevertheless what we should do is describe the hardware and from this
>> information infer whether there is a audio connection or not and if there is
>> none we might skip registering the CODEC. In my opinion this hardware
>> description should be modeled using of-graph, having a connection between
>> the SoC side and the adv7511 SPDIF or I2S port.
>>
> 
> You mean something like this:
> 
> sound_playback: sound_playback {
> compatible = "simple-audio-card";
> [...]
> simple-audio-card,format = "i2s";
> [...]
> }
> 
> adv7511 at xx {
> compatible = "adi,adv7511";
> [...]
> 
> ports {
> [...]
> /* Audio Output */
> port at x {
> reg = ;
> endpoint {
> remote-endpoint = <&sound_playback>;
> }
> }
> }
> }

Yes, something like that. Not exactly like that, but similar. One of the
core concepts of of-graph is that there is always a description of the
connection from both sides, this way each side can independently figure out
where it is connected.

Currently there is also zero support of of-graph in ASoC, so a bit of work
is required to get this integrated properly.

[Bug 94667] Artifacts on applications on discrete and kernel freezes

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=94667

--- Comment #17 from Vladislav Kamenev  ---
Artifacts are present in KDE desktop with DRI_PRIME=1.
As well as in chromium

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[Bug 94667] Artifacts on applications on discrete and kernel freezes

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=94667

--- Comment #18 from Vladislav Kamenev  ---
Created attachment 122865
  --> https://bugs.freedesktop.org/attachment.cgi?id=122865&action=edit
KDE desktop artifacts

Archlinux 4.5 kernel
11.2 mesa

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[PATCH v8 02/10] drm/hisilicon: Add hisilicon kirin drm master driver

[Xinliang Liu]

Add kirin DRM master driver for hi6220 SoC which used in HiKey board.
Add dumb buffer feature.
Add prime dmabuf feature.

v8: None.
v7:
- Add config.mutex protection when accessing mode_config.connector_list.
- Clean up match data getting.
v6: None.
v5: None.
v4: None.
v3:
- Move and rename all the files to kirin sub-directory.
  So that we could separate different seires SoCs' driver.
- Replace drm_platform_init, load, unload implementation.
v2:
- Remove abtraction layer.

Signed-off-by: Xinliang Liu 
Signed-off-by: Xinwei Kong 
---
 drivers/gpu/drm/Kconfig |   2 +
 drivers/gpu/drm/Makefile|   1 +
 drivers/gpu/drm/hisilicon/Kconfig   |   5 +
 drivers/gpu/drm/hisilicon/Makefile  |   5 +
 drivers/gpu/drm/hisilicon/kirin/Kconfig |   9 +
 drivers/gpu/drm/hisilicon/kirin/Makefile|   3 +
 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 309 
 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h |  20 ++
 8 files changed, 354 insertions(+)
 create mode 100644 drivers/gpu/drm/hisilicon/Kconfig
 create mode 100644 drivers/gpu/drm/hisilicon/Makefile
 create mode 100644 drivers/gpu/drm/hisilicon/kirin/Kconfig
 create mode 100644 drivers/gpu/drm/hisilicon/kirin/Makefile
 create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
 create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 84c587a1fa93..838f99acc2c0 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -289,3 +289,5 @@ source "drivers/gpu/drm/imx/Kconfig"
 source "drivers/gpu/drm/vc4/Kconfig"

 source "drivers/gpu/drm/etnaviv/Kconfig"
+
+source "drivers/gpu/drm/hisilicon/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 6eb94fc561dc..327d29638137 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -78,3 +78,4 @@ obj-y += panel/
 obj-y  += bridge/
 obj-$(CONFIG_DRM_FSL_DCU) += fsl-dcu/
 obj-$(CONFIG_DRM_ETNAVIV) += etnaviv/
+obj-y  += hisilicon/
diff --git a/drivers/gpu/drm/hisilicon/Kconfig 
b/drivers/gpu/drm/hisilicon/Kconfig
new file mode 100644
index ..558c61b1b8e8
--- /dev/null
+++ b/drivers/gpu/drm/hisilicon/Kconfig
@@ -0,0 +1,5 @@
+#
+# hisilicon drm device configuration.
+# Please keep this list sorted alphabetically
+
+source "drivers/gpu/drm/hisilicon/kirin/Kconfig"
diff --git a/drivers/gpu/drm/hisilicon/Makefile 
b/drivers/gpu/drm/hisilicon/Makefile
new file mode 100644
index ..e3f6d493c996
--- /dev/null
+++ b/drivers/gpu/drm/hisilicon/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for hisilicon drm drivers.
+# Please keep this list sorted alphabetically
+
+obj-$(CONFIG_DRM_HISI_KIRIN) += kirin/
diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig 
b/drivers/gpu/drm/hisilicon/kirin/Kconfig
new file mode 100644
index ..3ac4b8edeac1
--- /dev/null
+++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig
@@ -0,0 +1,9 @@
+config DRM_HISI_KIRIN
+   tristate "DRM Support for Hisilicon Kirin series SoCs Platform"
+   depends on DRM
+   select DRM_KMS_HELPER
+   select DRM_GEM_CMA_HELPER
+   select DRM_KMS_CMA_HELPER
+   help
+ Choose this option if you have a hisilicon Kirin chipsets(hi6220).
+ If M is selected the module will be called kirin-drm.
diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile 
b/drivers/gpu/drm/hisilicon/kirin/Makefile
new file mode 100644
index ..cb346de47d48
--- /dev/null
+++ b/drivers/gpu/drm/hisilicon/kirin/Makefile
@@ -0,0 +1,3 @@
+kirin-drm-y := kirin_drm_drv.o
+
+obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o
diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c 
b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
new file mode 100644
index ..976c9b1a3fd3
--- /dev/null
+++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
@@ -0,0 +1,309 @@
+/*
+ * Hisilicon Kirin SoCs drm master driver
+ *
+ * Copyright (c) 2016 Linaro Limited.
+ * Copyright (c) 2014-2016 Hisilicon Limited.
+ *
+ * Author:
+ * Xinliang Liu 
+ * Xinliang Liu 
+ * Xinwei Kong 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "kirin_drm_drv.h"
+
+static struct kirin_dc_ops *dc_ops;
+
+static int kirin_drm_kms_cleanup(struct drm_device *dev)
+{
+   dc_ops->cleanup(dev);
+   drm_mode_config_cleanup(dev);
+
+   return 0;
+}
+
+static const struct drm_mode_config_funcs kirin_drm_mode_config_funcs = {
+   .fb_create = drm_fb_cma_create,
+   .atomic_check = drm_atomic_helper_check,
+   .atomic_commit = drm_atomic_helper_commit,
+};
+
+static void kirin_drm_mode_config_init(struct drm_device *dev)
+{

[PATCH v8 04/10] drm/hisilicon: Add plane driver for ADE

[Xinliang Liu]

Add plane funcs and helper funcs for ADE.

v8: None.
v7: None.
v6: None.
v5: None.
v4: None.
v3:
- A few cleanup.
v2:
- Remove abtraction layer.

Signed-off-by: Xinliang Liu 
Signed-off-by: Xinwei Kong 
---
 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 535 +++-
 1 file changed, 534 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c 
b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
index cfbea957297b..8a7cb5e04bf4 100644
--- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
+++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
@@ -27,13 +27,23 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 

 #include "kirin_drm_drv.h"
 #include "kirin_ade_reg.h"

+#define PRIMARY_CH ADE_CH1 /* primary plane */
+#define OUT_OVLY   ADE_OVLY2 /* output overlay compositor */
+#define ADE_DEBUG  1
+
 #define to_ade_crtc(crtc) \
container_of(crtc, struct ade_crtc, base)

+#define to_ade_plane(plane) \
+   container_of(plane, struct ade_plane, base)
+
 struct ade_hw_ctx {
void __iomem  *base;
struct regmap *noc_regmap;
@@ -52,11 +62,76 @@ struct ade_crtc {
u32 out_format;
 };

+struct ade_plane {
+   struct drm_plane base;
+   void *ctx;
+   u8 ch; /* channel */
+};
+
 struct ade_data {
struct ade_crtc acrtc;
+   struct ade_plane aplane[ADE_CH_NUM];
struct ade_hw_ctx ctx;
 };

+/* ade-format info: */
+struct ade_format {
+   u32 pixel_format;
+   enum ade_fb_format ade_format;
+};
+
+static const struct ade_format ade_formats[] = {
+   /* 16bpp RGB: */
+   { DRM_FORMAT_RGB565, ADE_RGB_565 },
+   { DRM_FORMAT_BGR565, ADE_BGR_565 },
+   /* 24bpp RGB: */
+   { DRM_FORMAT_RGB888, ADE_RGB_888 },
+   { DRM_FORMAT_BGR888, ADE_BGR_888 },
+   /* 32bpp [A]RGB: */
+   { DRM_FORMAT_XRGB, ADE_XRGB_ },
+   { DRM_FORMAT_XBGR, ADE_XBGR_ },
+   { DRM_FORMAT_RGBA, ADE_RGBA_ },
+   { DRM_FORMAT_BGRA, ADE_BGRA_ },
+   { DRM_FORMAT_ARGB, ADE_ARGB_ },
+   { DRM_FORMAT_ABGR, ADE_ABGR_ },
+};
+
+static const u32 channel_formats1[] = {
+   /* channel 1,2,3,4 */
+   DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888,
+   DRM_FORMAT_BGR888, DRM_FORMAT_XRGB, DRM_FORMAT_XBGR,
+   DRM_FORMAT_RGBA, DRM_FORMAT_BGRA, DRM_FORMAT_ARGB,
+   DRM_FORMAT_ABGR
+};
+
+u32 ade_get_channel_formats(u8 ch, const u32 **formats)
+{
+   switch (ch) {
+   case ADE_CH1:
+   *formats = channel_formats1;
+   return ARRAY_SIZE(channel_formats1);
+   default:
+   DRM_ERROR("no this channel %d\n", ch);
+   *formats = NULL;
+   return 0;
+   }
+}
+
+/* convert from fourcc format to ade format */
+static u32 ade_get_format(u32 pixel_format)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(ade_formats); i++)
+   if (ade_formats[i].pixel_format == pixel_format)
+   return ade_formats[i].ade_format;
+
+   /* not found */
+   DRM_ERROR("Not found pixel format!!fourcc_format= %d\n",
+ pixel_format);
+   return ADE_FORMAT_UNSUPPORT;
+}
+
 static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val)
 {
u32 bit_ofst, reg_num;
@@ -89,7 +164,7 @@ static void ade_init(struct ade_hw_ctx *ctx)
/* clear overlay */
writel(0, base + ADE_OVLY1_TRANS_CFG);
writel(0, base + ADE_OVLY_CTL);
-   writel(0, base + ADE_OVLYX_CTL(ADE_OVLY2));
+   writel(0, base + ADE_OVLYX_CTL(OUT_OVLY));
/* clear reset and reload regs */
writel(MASK(32), base + ADE_SOFT_RST_SEL(0));
writel(MASK(32), base + ADE_SOFT_RST_SEL(1));
@@ -155,6 +230,10 @@ static void ade_ldi_set_mode(struct ade_crtc *acrtc,
   base + LDI_DSP_SIZE);
writel(plr_flags, base + LDI_PLR_CTRL);

+   /* set overlay compositor output size */
+   writel(((width - 1) << OUTPUT_XSIZE_OFST) | (height - 1),
+  base + ADE_OVLY_OUTPUT_SIZE(OUT_OVLY));
+
/* ctran6 setting */
writel(CTRAN_BYPASS_ON, base + ADE_CTRAN_DIS(ADE_CTRAN6));
 /* the configured value is actual value - 1 */
@@ -229,6 +308,10 @@ static void ade_display_enable(struct ade_crtc *acrtc)
void __iomem *base = ctx->base;
u32 out_fmt = acrtc->out_format;

+   /* enable output overlay compositor */
+   writel(ADE_ENABLE, base + ADE_OVLYX_CTL(OUT_OVLY));
+   ade_update_reload_bit(base, OVLY_OFST + OUT_OVLY, 0);
+
/* display source setting */
writel(DISP_SRC_OVLY2, base + ADE_DISP_SRC_CFG);

@@ -242,6 +325,97 @@ static void ade_display_enable(struct ade_crtc *acrtc)
writel(DSI_PCLK_ON, base + LDI_HDMI_DSI_GT);
 }

+#if ADE_DEBUG
+static void ade_rdma_dump_regs(void __iomem *base, u32 ch)
+{
+   u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg

[PATCH v8 08/10] drm/hisilicon: Add designware dsi host driver

[Xinliang Liu]

Add DesignWare dsi host driver for hi6220 SoC.

v8: None.
v7: None.
v6: None.
v5: None.
v4: None.
v3: None.
v2:
- Remove abtraction layer.

Signed-off-by: Xinliang Liu 
Signed-off-by: Xinwei Kong 
Reviewed-by: Archit Taneja 
---
 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 50 
 1 file changed, 50 insertions(+)

diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 
b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
index 1a930b77ec53..ea7711832959 100644
--- a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
+++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
@@ -80,6 +80,7 @@ struct dsi_hw_ctx {

 struct dw_dsi {
struct drm_encoder encoder;
+   struct mipi_dsi_host host;
struct drm_display_mode cur_mode;
struct dsi_hw_ctx *ctx;
struct mipi_phy_params phy;
@@ -654,6 +655,51 @@ static int dw_drm_encoder_init(struct device *dev,
return 0;
 }

+static int dsi_host_attach(struct mipi_dsi_host *host,
+  struct mipi_dsi_device *mdsi)
+{
+   struct dw_dsi *dsi = host_to_dsi(host);
+
+   if (mdsi->lanes < 1 || mdsi->lanes > 4) {
+   DRM_ERROR("dsi device params invalid\n");
+   return -EINVAL;
+   }
+
+   dsi->lanes = mdsi->lanes;
+   dsi->format = mdsi->format;
+   dsi->mode_flags = mdsi->mode_flags;
+
+   return 0;
+}
+
+static int dsi_host_detach(struct mipi_dsi_host *host,
+  struct mipi_dsi_device *mdsi)
+{
+   /* do nothing */
+   return 0;
+}
+
+static const struct mipi_dsi_host_ops dsi_host_ops = {
+   .attach = dsi_host_attach,
+   .detach = dsi_host_detach,
+};
+
+static int dsi_host_init(struct device *dev, struct dw_dsi *dsi)
+{
+   struct mipi_dsi_host *host = &dsi->host;
+   int ret;
+
+   host->dev = dev;
+   host->ops = &dsi_host_ops;
+   ret = mipi_dsi_host_register(host);
+   if (ret) {
+   DRM_ERROR("failed to register dsi host\n");
+   return ret;
+   }
+
+   return 0;
+}
+
 static int dsi_bind(struct device *dev, struct device *master, void *data)
 {
struct dsi_data *ddata = dev_get_drvdata(dev);
@@ -665,6 +711,10 @@ static int dsi_bind(struct device *dev, struct device 
*master, void *data)
if (ret)
return ret;

+   ret = dsi_host_init(dev, dsi);
+   if (ret)
+   return ret;
+
return 0;
 }

-- 
2.8.0

[PATCH v8 09/10] drm/hisilicon: Add support for external bridge

[Xinliang Liu]

Add support for external HDMI bridge.

v8: None.
v7: None.
v6: None.
v5: None.
v4: None.
v3:
- Fix a typo: s/exteranl/external.
v2:
- Remove abtraction layer.

Signed-off-by: Xinliang Liu 
Signed-off-by: Xinwei Kong 
Reviewed-by: Archit Taneja 
---
 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 52 
 1 file changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 
b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
index ea7711832959..bfbc2159250d 100644
--- a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
+++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
@@ -80,6 +80,7 @@ struct dsi_hw_ctx {

 struct dw_dsi {
struct drm_encoder encoder;
+   struct drm_bridge *bridge;
struct mipi_dsi_host host;
struct drm_display_mode cur_mode;
struct dsi_hw_ctx *ctx;
@@ -700,6 +701,25 @@ static int dsi_host_init(struct device *dev, struct dw_dsi 
*dsi)
return 0;
 }

+static int dsi_bridge_init(struct drm_device *dev, struct dw_dsi *dsi)
+{
+   struct drm_encoder *encoder = &dsi->encoder;
+   struct drm_bridge *bridge = dsi->bridge;
+   int ret;
+
+   /* associate the bridge to dsi encoder */
+   encoder->bridge = bridge;
+   bridge->encoder = encoder;
+
+   ret = drm_bridge_attach(dev, bridge);
+   if (ret) {
+   DRM_ERROR("failed to attach external bridge\n");
+   return ret;
+   }
+
+   return 0;
+}
+
 static int dsi_bind(struct device *dev, struct device *master, void *data)
 {
struct dsi_data *ddata = dev_get_drvdata(dev);
@@ -715,6 +735,10 @@ static int dsi_bind(struct device *dev, struct device 
*master, void *data)
if (ret)
return ret;

+   ret = dsi_bridge_init(drm_dev, dsi);
+   if (ret)
+   return ret;
+
return 0;
 }

@@ -731,8 +755,36 @@ static const struct component_ops dsi_ops = {
 static int dsi_parse_dt(struct platform_device *pdev, struct dw_dsi *dsi)
 {
struct dsi_hw_ctx *ctx = dsi->ctx;
+   struct device_node *np = pdev->dev.of_node;
+   struct device_node *endpoint, *bridge_node;
+   struct drm_bridge *bridge;
struct resource *res;

+   /*
+* Get the endpoint node. In our case, dsi has one output port1
+* to which the external HDMI bridge is connected.
+*/
+   endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
+   if (!endpoint) {
+   DRM_ERROR("no valid endpoint node\n");
+   return -ENODEV;
+   }
+   of_node_put(endpoint);
+
+   bridge_node = of_graph_get_remote_port_parent(endpoint);
+   if (!bridge_node) {
+   DRM_ERROR("no valid bridge node\n");
+   return -ENODEV;
+   }
+   of_node_put(bridge_node);
+
+   bridge = of_drm_find_bridge(bridge_node);
+   if (!bridge) {
+   DRM_INFO("wait for external HDMI bridge driver.\n");
+   return -EPROBE_DEFER;
+   }
+   dsi->bridge = bridge;
+
ctx->pclk = devm_clk_get(&pdev->dev, "pclk");
if (IS_ERR(ctx->pclk)) {
DRM_ERROR("failed to get pclk clock\n");
-- 
2.8.0

[PATCH v8 10/10] MAINTAINERS: Add maintainer for hisilicon DRM driver

[Xinliang Liu]

Add maintainer and reviewer for hisilicon DRM driver.

v8: None.
v7: None.
v6: None.
v5: None.
v4:
- Add Chen Feng  as Designated reviewer.
v3: First version.

Signed-off-by: Xinliang Liu 
---
 MAINTAINERS | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 61a323a6b2cf..a2ef58860689 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3840,6 +3840,16 @@ S:   Maintained
 F: drivers/gpu/drm/gma500
 F: include/drm/gma500*

+DRM DRIVERS FOR HISILICON
+M: Xinliang Liu 
+R: Xinwei Kong 
+R: Chen Feng 
+L: dri-devel at lists.freedesktop.org
+T: git git://github.com/xin3liang/linux.git
+S: Maintained
+F: drivers/gpu/drm/hisilicon
+F: Documentation/devicetree/bindings/display/hisilicon
+
 DRM DRIVERS FOR NVIDIA TEGRA
 M: Thierry Reding 
 M: Terje Bergström 
-- 
2.8.0

[PATCH] drm/radeon: hold reference to fences in radeon_sa_bo_new (3.17 and older)

[Luis Henriques]

On Tue, Mar 15, 2016 at 12:56:45PM -0500, Nicolai Hähnle wrote:
> From: Nicolai Hähnle 
> 
> [Backport of upstream commit f6ff4f67cdf8455d0a4226eeeaf5af17c37d05eb, with
>  an additional NULL pointer guard that is required for kernels 3.17 and older.
>

Thank you, Nicolai.  I'll queue this backport for the 3.16.

Cheers,
--
Luís


>  To be precise, any kernel that does *not* have commit 954605ca3 "drm/radeon:
>  use common fence implementation for fences, v4" requires this additional
>  NULL pointer guard.]
> 
> An arbitrary amount of time can pass between spin_unlock and
> radeon_fence_wait_any, so we need to ensure that nobody frees the
> fences from under us.
> 
> Based on the analogous fix for amdgpu.
> 
> Signed-off-by: Nicolai Hähnle 
> Reviewed-by: Christian König  (v1 + fix)
> Tested-by: Lutz Euler 
> Cc: stable at vger.kernel.org
> ---
>  drivers/gpu/drm/radeon/radeon_sa.c | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/radeon/radeon_sa.c 
> b/drivers/gpu/drm/radeon/radeon_sa.c
> index c507896..7d11901 100644
> --- a/drivers/gpu/drm/radeon/radeon_sa.c
> +++ b/drivers/gpu/drm/radeon/radeon_sa.c
> @@ -349,8 +349,15 @@ int radeon_sa_bo_new(struct radeon_device *rdev,
>   /* see if we can skip over some allocations */
>   } while (radeon_sa_bo_next_hole(sa_manager, fences, tries));
>  
> + for (i = 0; i < RADEON_NUM_RINGS; ++i) {
> + if (fences[i])
> + radeon_fence_ref(fences[i]);
> + }
> +
>   spin_unlock(&sa_manager->wq.lock);
>   r = radeon_fence_wait_any(rdev, fences, false);
> + for (i = 0; i < RADEON_NUM_RINGS; ++i)
> + radeon_fence_unref(&fences[i]);
>   spin_lock(&sa_manager->wq.lock);
>   /* if we have nothing to wait for block */
>   if (r == -ENOENT) {
> -- 
> 2.5.0
> 
> --
> To unsubscribe from this list: send the line "unsubscribe stable" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[alsa-devel] [PATCH 2/5 v4] drm/i2c/adv7511: Add audio support

[Jose Abreu]

Hi Lars,


On 09-04-2016 16:02, Lars-Peter Clausen wrote:
> On 04/08/2016 06:12 PM, Jose Abreu wrote:
> [...]
>>> [...]
 +- adi,enable-audio: If set the ADV7511 driver will register a codec 
 interface
 +  into ALSA SoC.
>>> This is not a description of the hardware.
>> Is this okay: "adi,enable-audio: Set this boolean parameter if ADV7511
>> transmitter routes audio signals" ?
> I don't think we need this property. There is no problem with registering
> the audio part unconditionally. As long as there is no connection we wont
> create a sound card that is exposed to userspace.
>

This change was suggested by Laurent Pinchart and was introduced in v3. Quoting
Laurent:
"The idea is that enabling support for ADV7511 audio in the kernel isn't coupled
with whether the system includes audio support. It would be confusing, and would
also waste resources, to create a Linux sound device when no sound channel is
routed on the board."

Should I revert this?

Best regards,
Jose Miguel Abreu

[PATCH v8 00/10] Add DRM Driver for HiSilicon Kirin hi6220 SoC

[Xinliang Liu]

This patch set adds a new drm driver for HiSilicon Kirin hi6220 SoC.
Current testing and support board is Hikey board which is one of Linaro
96boards. It is an arm64 open source board. For more information about
this board, please access https://www.96boards.org.

Hardware Detail
---
  The display subsystem of Hi6220 SoC is shown as bellow:
 +-+   +--+ +-+ +-+
 | |   |  | | | | | 
 | FB  |-->|   ADE|>| DSI |>|   External  |
 | |   |  | | | |  HDMI/panel |
 +-+   +--+ +-+ +-+

- ADE(Advanced Display Engine) is the display controller. It contains 7
channels, 3 overlay compositors and a LDI.
  - A channel looks like: DMA-->clip-->scale-->ctrans(or called csc).
  - Overlay compositor is response to compose planes which come from 7
  channels and pass composed image to LDI.
  - LDI is response to generate timings and RGB data stream.
- DSI converts the RGB data stream from ADE to DSI packets.
- External HDMI/panel module is connected with DSI bus. Now Hikey use a
  ADI's ADV7533 external HDMI chip.

Change History
-
Changes in v8:
- Rebase to v4.6-rc3

Changes in v7:
- Add config.mutex protection when accessing mode_config.connector_list.
- Clean up match data getting of kirin_drm_drv.c.
- A few Regs define clean up and typo fixs for ADE crtc and DSI encoder
  driver.
- Fix vblank irq flag "DRIVER_IRQF_SHARED" to "IRQF_SHARED".

Changes in v6:
- Cleanup values part of reg and clocks relevant properties.
- Change "pclk_dsi" clock name to "pclk".

Changes in v5:
- Remove endpoint unit address of dsi output port.
- Use syscon to access ADE media NOC QoS registers instread of directly
  writing registers.
- Use reset controller to reset ADE instead of directly writing registers.

Changes in v4:
- Describe more specific of clocks and ports of binding docs.
- Fix indentation of binding docs.

Changes in v3:
- Move and rename all the files to kirin sub-directory.
  So that we could separate different seires SoCs' driver.
- Make ade as the drm master node.
- Replace drm_platform_init, load, unload implementation.
- Use assigned-clocks to set clock rate.
- Use ports to connect display relevant nodes.
- Rename hisi_drm_dsi.c to dw_drm_dsi.c
- Make encoder type as DRM_MODE_ENCODER_DSI.
- A few cleanup on regs and code.

Changes in v2:
- Remove abtraction layer of plane/crtc/encoder/connector.
- Refactor atomic implementation according to Daniel Vetter's guides:
http://blog.ffwll.ch/2014/11/atomic-modeset-support-for-kms-drivers.html
http://blog.ffwll.ch/2015/09/xdc-2015-atomic-modesetting-for-drivers.html
http://blog.ffwll.ch/2015/08/atomic-modesetting-design-overview.html
- Use bridge instead of slave encoder to connect external HDMI.
- Move dt binding docs to bindings/display/hisilicon directory.

Xinliang Liu (10):
  drm/hisilicon: Add device tree binding for hi6220 display subsystem
  drm/hisilicon: Add hisilicon kirin drm master driver
  drm/hisilicon: Add crtc driver for ADE
  drm/hisilicon: Add plane driver for ADE
  drm/hisilicon: Add vblank driver for ADE
  drm/hisilicon: Add cma fbdev and hotplug
  drm/hisilicon: Add designware dsi encoder driver
  drm/hisilicon: Add designware dsi host driver
  drm/hisilicon: Add support for external bridge
  MAINTAINERS: Add maintainer for hisilicon DRM driver

 .../bindings/display/hisilicon/dw-dsi.txt  |   72 ++
 .../bindings/display/hisilicon/hisi-ade.txt|   64 ++
 MAINTAINERS|   10 +
 drivers/gpu/drm/Kconfig|2 +
 drivers/gpu/drm/Makefile   |1 +
 drivers/gpu/drm/hisilicon/Kconfig  |5 +
 drivers/gpu/drm/hisilicon/Makefile |5 +
 drivers/gpu/drm/hisilicon/kirin/Kconfig|   10 +
 drivers/gpu/drm/hisilicon/kirin/Makefile   |5 +
 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c   |  857 
 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h   |  103 ++
 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h|  230 +
 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c| 1057 
 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c|  367 +++
 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h|   31 +
 15 files changed, 2819 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt
 create mode 100644 
Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt
 create mode 100644 drivers/gpu/drm/hisilicon/Kconfig
 create mode 100644 drivers/gpu/drm/hisilicon/Makefile
 create mode 100644 drivers/gpu/drm/hisilicon/kirin/Kconfig
 create mode 100644 drivers/gpu/drm/hisilicon/kirin/Makefile
 create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
 create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h
 create mod

[PATCH v8 01/10] drm/hisilicon: Add device tree binding for hi6220 display subsystem

[Xinliang Liu]

Add ADE display controller binding doc.
Add DesignWare DSI Host Controller v1.20a binding doc.

v8: None.
v7: Acked by Rob Herring.
v6:
- Cleanup values part of reg and clocks properties.
- Change "pclk_dsi" clock name to "pclk".
v5:
- Remove endpoint unit address of dsi output port.
- Add "hisilicon,noc-syscon" property for ADE NOC QoS syscon.
- Add "resets" property for ADE reset.
v4:
- Describe more specific of clocks and ports.
- Fix indentation.
v3:
- Make ade as the drm master node.
- Use assigned-clocks to set clock rate.
- Use ports to connect display relavant nodes.
v2:
- Move dt binding docs to bindings/display/hisilicon directory.

Signed-off-by: Xinliang Liu 
Signed-off-by: Xinwei Kong 
Acked-by: Rob Herring 
---
 .../bindings/display/hisilicon/dw-dsi.txt  | 72 ++
 .../bindings/display/hisilicon/hisi-ade.txt| 64 +++
 2 files changed, 136 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt
 create mode 100644 
Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt

diff --git a/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt 
b/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt
new file mode 100644
index ..d270bfe4e4e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt
@@ -0,0 +1,72 @@
+Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver
+
+A DSI Host Controller resides in the middle of display controller and external
+HDMI converter or panel.
+
+Required properties:
+- compatible: value should be "hisilicon,hi6220-dsi".
+- reg: physical base address and length of dsi controller's registers.
+- clocks: contains APB clock phandle + clock-specifier pair.
+- clock-names: should be "pclk".
+- ports: contains DSI controller input and output sub port.
+  The input port connects to ADE output port with the reg value "0".
+  The output port with the reg value "1", it could connect to panel or
+  any other bridge endpoints.
+  See Documentation/devicetree/bindings/graph.txt for more device graph info.
+
+A example of HiKey board hi6220 SoC and board specific DT entry:
+Example:
+
+SoC specific:
+   dsi: dsi at f4107800 {
+   compatible = "hisilicon,hi6220-dsi";
+   reg = <0x0 0xf4107800 0x0 0x100>;
+   clocks = <&media_ctrl  HI6220_DSI_PCLK>;
+   clock-names = "pclk";
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   /* 0 for input port */
+   port at 0 {
+   reg = <0>;
+   dsi_in: endpoint {
+   remote-endpoint = <&ade_out>;
+   };
+   };
+   };
+   };
+
+
+Board specific:
+   &dsi {
+   status = "ok";
+
+   ports {
+   /* 1 for output port */
+   port at 1 {
+   reg = <1>;
+
+   dsi_out0: endpoint at 0 {
+   remote-endpoint = <&adv7533_in>;
+   };
+   };
+   };
+   };
+
+   &i2c2 {
+   ...
+
+   adv7533: adv7533 at 39 {
+   ...
+
+   port {
+   adv7533_in: endpoint {
+   remote-endpoint = <&dsi_out0>;
+   };
+   };
+   };
+   };
+
diff --git a/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt 
b/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt
new file mode 100644
index ..38dc9d60eef8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt
@@ -0,0 +1,64 @@
+Device-Tree bindings for hisilicon ADE display controller driver
+
+ADE (Advanced Display Engine) is the display controller which grab image
+data from memory, do composition, do post image processing, generate RGB
+timing stream and transfer to DSI.
+
+Required properties:
+- compatible: value should be "hisilicon,hi6220-ade".
+- reg: physical base address and length of the ADE controller's registers.
+- hisilicon,noc-syscon: ADE NOC QoS syscon.
+- resets: The ADE reset controller node.
+- interrupt: the ldi vblank interrupt number used.
+- clocks: a list of phandle + clock-specifier pairs, one for each entry
+  in clock-names.
+- clock-names: should contain:
+  "clk_ade_core" for the ADE core clock.
+  "clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with
+  jpeg codec.
+  "clk_ade_pix" for the ADE pixel clok.
+- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
+  phandle + 

[PATCH v8 03/10] drm/hisilicon: Add crtc driver for ADE

[Xinliang Liu]

Add crtc funcs and helper funcs for ADE.

v8: None.
v7:
- A few Regs define clean up and typo fixs.
v6:
- Cleanup reg-names dt parsing.
v5:
- Use syscon to access ADE media NOC QoS registers instread of directly
  writing registers.
- Use reset controller to reset ADE instead of directly writing registers.
v4: None.
v3:
- Make ade as the master driver.
- Use port to connect with encoder.
- A few cleanup.
v2:
- Remove abtraction layer.

Signed-off-by: Xinliang Liu 
Signed-off-by: Xinwei Kong 
Reviewed-by: Archit Taneja 
---
 drivers/gpu/drm/hisilicon/kirin/Makefile|   3 +-
 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h | 230 
 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 462 
 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c |  12 +
 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h |   8 +
 5 files changed, 714 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h
 create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c

diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile 
b/drivers/gpu/drm/hisilicon/kirin/Makefile
index cb346de47d48..2a61ab006ddb 100644
--- a/drivers/gpu/drm/hisilicon/kirin/Makefile
+++ b/drivers/gpu/drm/hisilicon/kirin/Makefile
@@ -1,3 +1,4 @@
-kirin-drm-y := kirin_drm_drv.o
+kirin-drm-y := kirin_drm_drv.o \
+  kirin_drm_ade.o

 obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o
diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h 
b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h
new file mode 100644
index ..4cf281b7ed63
--- /dev/null
+++ b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2016 Linaro Limited.
+ * Copyright (c) 2014-2016 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __KIRIN_ADE_REG_H__
+#define __KIRIN_ADE_REG_H__
+
+/*
+ * ADE Registers
+ */
+#define MASK(x)(BIT(x) - 1)
+
+#define ADE_CTRL   0x0004
+#define FRM_END_START_OFST 0
+#define FRM_END_START_MASK MASK(2)
+#define AUTO_CLK_GATE_EN_OFST  0
+#define AUTO_CLK_GATE_EN   BIT(0)
+#define ADE_DISP_SRC_CFG   0x0018
+#define ADE_CTRL1  0x008C
+#define ADE_EN 0x0100
+#define ADE_DISABLE0
+#define ADE_ENABLE 1
+/* reset and reload regs */
+#define ADE_SOFT_RST_SEL(x)(0x0078 + (x) * 0x4)
+#define ADE_RELOAD_DIS(x)  (0x00AC + (x) * 0x4)
+#define RDMA_OFST  0
+#define CLIP_OFST  15
+#define SCL_OFST   21
+#define CTRAN_OFST 24
+#define OVLY_OFST  37 /* 32+5 */
+/* channel regs */
+#define RD_CH_CTRL(x)  (0x1004 + (x) * 0x80)
+#define RD_CH_ADDR(x)  (0x1008 + (x) * 0x80)
+#define RD_CH_SIZE(x)  (0x100C + (x) * 0x80)
+#define RD_CH_STRIDE(x)(0x1010 + (x) * 0x80)
+#define RD_CH_SPACE(x) (0x1014 + (x) * 0x80)
+#define RD_CH_EN(x)(0x1020 + (x) * 0x80)
+/* overlay regs */
+#define ADE_OVLY1_TRANS_CFG0x002C
+#define ADE_OVLY_CTL   0x0098
+#define ADE_OVLY_CH_XY0(x) (0x2004 + (x) * 4)
+#define ADE_OVLY_CH_XY1(x) (0x2024 + (x) * 4)
+#define ADE_OVLY_CH_CTL(x) (0x204C + (x) * 4)
+#define ADE_OVLY_OUTPUT_SIZE(x)(0x2070 + (x) * 8)
+#define OUTPUT_XSIZE_OFST  16
+#define ADE_OVLYX_CTL(x)   (0x209C + (x) * 4)
+#define CH_OVLY_SEL_OFST(x)((x) * 4)
+#define CH_OVLY_SEL_MASK   MASK(2)
+#define CH_OVLY_SEL_VAL(x) ((x) + 1)
+#define CH_ALP_MODE_OFST   0
+#define CH_ALP_SEL_OFST2
+#define CH_UNDER_ALP_SEL_OFST  4
+#define CH_EN_OFST 6
+#define CH_ALP_GBL_OFST15
+#define CH_SEL_OFST28
+/* ctran regs */
+#define ADE_CTRAN_DIS(x)   (0x5004 + (x) * 0x100)
+#define CTRAN_BYPASS_ON1
+#define CTRAN_BYPASS_OFF   0
+#define ADE_CTRAN_IMAGE_SIZE(x)(0x503C + (x) * 0x100)
+/* clip regs */
+#define ADE_CLIP_DISABLE(x)(0x6800 + (x) * 0x100)
+#define ADE_CLIP_SIZE0(x)  (0x6804 + (x) * 0x100)
+#define ADE_CLIP_SIZE1(x)  (0x6808 + (x) * 0x100)
+
+/*
+ * LDI Registers
+ */
+#define LDI_HRZ_CTRL0  0x7400
+#define HBP_OFST   20
+#define LDI_HRZ_CTRL1  0x7404
+#define LDI_VRT_CTRL0  0x7408
+#define VBP_OFST   20
+#define LDI_VRT_CTRL1  0x740C
+#define LDI_PLR

[PATCH v8 05/10] drm/hisilicon: Add vblank driver for ADE

[Xinliang Liu]

Add vblank irq handle.

v8: None.
v7:
- Fix irq flag "DRIVER_IRQF_SHARED" to "IRQF_SHARED".
v6: None.
v5: None.
v4: None.
v3:
- Remove hisi_get_crtc_from_index func.
- A few cleanup.
v2:
- Remove abtraction layer.

Signed-off-by: Xinliang Liu 
Signed-off-by: Xinwei Kong 
---
 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 62 +
 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 14 +-
 2 files changed, 75 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c 
b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
index 8a7cb5e04bf4..fba6372d060e 100644
--- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
+++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
@@ -302,6 +302,59 @@ static void ade_set_medianoc_qos(struct ade_crtc *acrtc)
   SOCKET_QOS_EN, SOCKET_QOS_EN);
 }

+static int ade_enable_vblank(struct drm_device *dev, unsigned int pipe)
+{
+   struct kirin_drm_private *priv = dev->dev_private;
+   struct ade_crtc *acrtc = to_ade_crtc(priv->crtc[pipe]);
+   struct ade_hw_ctx *ctx = acrtc->ctx;
+   void __iomem *base = ctx->base;
+
+   if (!ctx->power_on)
+   (void)ade_power_up(ctx);
+
+   ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST,
+   MASK(1), 1);
+
+   return 0;
+}
+
+static void ade_disable_vblank(struct drm_device *dev, unsigned int pipe)
+{
+   struct kirin_drm_private *priv = dev->dev_private;
+   struct ade_crtc *acrtc = to_ade_crtc(priv->crtc[pipe]);
+   struct ade_hw_ctx *ctx = acrtc->ctx;
+   void __iomem *base = ctx->base;
+
+   if (!ctx->power_on) {
+   DRM_ERROR("power is down! vblank disable fail\n");
+   return;
+   }
+
+   ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST,
+   MASK(1), 0);
+}
+
+static irqreturn_t ade_irq_handler(int irq, void *data)
+{
+   struct ade_crtc *acrtc = data;
+   struct ade_hw_ctx *ctx = acrtc->ctx;
+   struct drm_crtc *crtc = &acrtc->base;
+   void __iomem *base = ctx->base;
+   u32 status;
+
+   status = readl(base + LDI_MSK_INT);
+   DRM_DEBUG_VBL("LDI IRQ: status=0x%X\n", status);
+
+   /* vblank irq */
+   if (status & BIT(FRAME_END_INT_EN_OFST)) {
+   ade_update_bits(base + LDI_INT_CLR, FRAME_END_INT_EN_OFST,
+   MASK(1), 1);
+   drm_crtc_handle_vblank(crtc);
+   }
+
+   return IRQ_HANDLED;
+}
+
 static void ade_display_enable(struct ade_crtc *acrtc)
 {
struct ade_hw_ctx *ctx = acrtc->ctx;
@@ -977,6 +1030,15 @@ static int ade_drm_init(struct drm_device *dev)
if (ret)
return ret;

+   /* vblank irq init */
+   ret = devm_request_irq(dev->dev, ctx->irq, ade_irq_handler,
+  IRQF_SHARED, dev->driver->name, acrtc);
+   if (ret)
+   return ret;
+   dev->driver->get_vblank_counter = drm_vblank_no_hw_counter;
+   dev->driver->enable_vblank = ade_enable_vblank;
+   dev->driver->disable_vblank = ade_disable_vblank;
+
return 0;
 }

diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c 
b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
index 578a1eb94517..2a899c5bb14e 100644
--- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
+++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
@@ -32,6 +32,7 @@ static int kirin_drm_kms_cleanup(struct drm_device *dev)
 {
struct kirin_drm_private *priv = dev->dev_private;

+   drm_vblank_cleanup(dev);
dc_ops->cleanup(dev);
drm_mode_config_cleanup(dev);
devm_kfree(dev->dev, priv);
@@ -85,11 +86,22 @@ static int kirin_drm_kms_init(struct drm_device *dev)
goto err_dc_cleanup;
}

+   /* vblank init */
+   ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
+   if (ret) {
+   DRM_ERROR("failed to initialize vblank.\n");
+   goto err_unbind_all;
+   }
+   /* with irq_enabled = true, we can use the vblank feature. */
+   dev->irq_enabled = true;
+
/* reset all the states of crtc/plane/encoder/connector */
drm_mode_config_reset(dev);

return 0;

+err_unbind_all:
+   component_unbind_all(dev->dev, dev);
 err_dc_cleanup:
dc_ops->cleanup(dev);
 err_mode_config_cleanup:
@@ -123,7 +135,7 @@ static int kirin_gem_cma_dumb_create(struct drm_file *file,

 static struct drm_driver kirin_drm_driver = {
.driver_features= DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
- DRIVER_ATOMIC,
+ DRIVER_ATOMIC | DRIVER_HAVE_IRQ,
.fops   = &kirin_drm_fops,
.set_busid  = drm_platform_set_busid,

-- 
2.8.0

[PATCH v8 06/10] drm/hisilicon: Add cma fbdev and hotplug

[Xinliang Liu]

Add cma Fbdev, Fbdev is legency and optional, you can enable/disable it by
configuring DRM_FBDEV_EMULATION.
Add hotplug.

v8: None.
v7: None.
v6: None.
v5: None.
v4: None.
v3: None.
v2:
- Use CONFIG_DRM_FBDEV_EMULATION instead of CONFIG_DRM_HISI_FBDEV.

Signed-off-by: Xinliang Liu 
Signed-off-by: Xinwei Kong 
---
 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 34 +
 drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h |  3 +++
 2 files changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c 
b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
index 2a899c5bb14e..e102c9e1e7b2 100644
--- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
+++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
@@ -23,6 +23,7 @@
 #include 
 #include 
 #include 
+#include 

 #include "kirin_drm_drv.h"

@@ -32,6 +33,13 @@ static int kirin_drm_kms_cleanup(struct drm_device *dev)
 {
struct kirin_drm_private *priv = dev->dev_private;

+#ifdef CONFIG_DRM_FBDEV_EMULATION
+   if (priv->fbdev) {
+   drm_fbdev_cma_fini(priv->fbdev);
+   priv->fbdev = NULL;
+   }
+#endif
+   drm_kms_helper_poll_fini(dev);
drm_vblank_cleanup(dev);
dc_ops->cleanup(dev);
drm_mode_config_cleanup(dev);
@@ -41,8 +49,28 @@ static int kirin_drm_kms_cleanup(struct drm_device *dev)
return 0;
 }

+#ifdef CONFIG_DRM_FBDEV_EMULATION
+static void kirin_fbdev_output_poll_changed(struct drm_device *dev)
+{
+   struct kirin_drm_private *priv = dev->dev_private;
+
+   if (priv->fbdev) {
+   drm_fbdev_cma_hotplug_event(priv->fbdev);
+   } else {
+   priv->fbdev = drm_fbdev_cma_init(dev, 32,
+   dev->mode_config.num_crtc,
+   dev->mode_config.num_connector);
+   if (IS_ERR(priv->fbdev))
+   priv->fbdev = NULL;
+   }
+}
+#endif
+
 static const struct drm_mode_config_funcs kirin_drm_mode_config_funcs = {
.fb_create = drm_fb_cma_create,
+#ifdef CONFIG_DRM_FBDEV_EMULATION
+   .output_poll_changed = kirin_fbdev_output_poll_changed,
+#endif
.atomic_check = drm_atomic_helper_check,
.atomic_commit = drm_atomic_helper_commit,
 };
@@ -98,6 +126,12 @@ static int kirin_drm_kms_init(struct drm_device *dev)
/* reset all the states of crtc/plane/encoder/connector */
drm_mode_config_reset(dev);

+   /* init kms poll for handling hpd */
+   drm_kms_helper_poll_init(dev);
+
+   /* force detection after connectors init */
+   (void)drm_helper_hpd_irq_event(dev);
+
return 0;

 err_unbind_all:
diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h 
b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h
index 5a05ad6a81db..1a07caf8e7f4 100644
--- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h
+++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h
@@ -21,6 +21,9 @@ struct kirin_dc_ops {

 struct kirin_drm_private {
struct drm_crtc *crtc[MAX_CRTC];
+#ifdef CONFIG_DRM_FBDEV_EMULATION
+   struct drm_fbdev_cma *fbdev;
+#endif
 };

 extern const struct kirin_dc_ops ade_dc_ops;
-- 
2.8.0

[alsa-devel] [PATCH 5/5 v4] ASoC: dwc: Update DOCUMENTATION for I2S Driver

[Jose Abreu]

Hi Lars,


On 09-04-2016 15:55, Lars-Peter Clausen wrote:
> On 04/08/2016 06:08 PM, Jose Abreu wrote:
>> Hi Lars,
>>
>>
>> On 08-04-2016 16:52, Lars-Peter Clausen wrote:
>>> On 04/08/2016 12:06 PM, Jose Abreu wrote:
 Hi Mark,


 On 07-04-2016 18:53, Mark Brown wrote:
> On Thu, Apr 07, 2016 at 05:53:59PM +0100, Jose Abreu wrote:
>
>> + Optional properties:
>> + - snps,use-dmaengine: If set the driver will use ALSA DMA engine. If 
>> set
>> +   it is required to use the properties 'dmas' and 'dma-names'.
> This is not a good interface, it's describing Linux internal APIs.  If
> the device needs to operate in PIO mode it should just do that.
 I added this interface because there is no direct way to check if DMA is
 available on the I2S controller so it is not possible to automatically 
 change
 between DMA and PIO mode. As the I2S controller can be built with or 
 without DMA
 support it is necessary to somehow check if DMA is enabled or not and 
 according
 to that use either ALSA DMA engine or the custom platform driver sent in 
 these
 patches. I did not want to remove drivers functionality so I added this 
 property
 to the DT. This way a user can select between DMA and PIO mode.
>>> That's OK, but you need to describe the hardware, not the indented behavior
>>> of the software driver.
>>>
>> Is this okay: "snps,use-dmaengine: Set this boolean paramater if I2S 
>> controller
>> has DMA support. If set the properties 'dmas' and 'dma-names' must be also 
>> set" ?
> The description is better. But the name of the property is still imperative
> rather then descriptive. It tells the software what should be done rather
> then describing what the hardware looks like.
>
> Since there is already the dmas property which is present if a DMA is
> connected and is absent when no DMA is present it should be enough to just
> check that property rather than requiring an additional one.

Ok, will then use the DMA property to decide which mode to use: PIO or DMA.

>
> ___
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

Best regards,
Jose Miguel Abreu

[alsa-devel] [PATCH 2/5 v4] drm/i2c/adv7511: Add audio support

[Jose Abreu]

Hi Lars,


On 11-04-2016 10:33, Lars-Peter Clausen wrote:
> On 04/11/2016 11:27 AM, Jose Abreu wrote:
>> Hi Lars,
>>
>>
>> On 09-04-2016 16:02, Lars-Peter Clausen wrote:
>>> On 04/08/2016 06:12 PM, Jose Abreu wrote:
>>> [...]
> [...]
>> +- adi,enable-audio: If set the ADV7511 driver will register a codec 
>> interface
>> +  into ALSA SoC.
> This is not a description of the hardware.
 Is this okay: "adi,enable-audio: Set this boolean parameter if ADV7511
 transmitter routes audio signals" ?
>>> I don't think we need this property. There is no problem with registering
>>> the audio part unconditionally. As long as there is no connection we wont
>>> create a sound card that is exposed to userspace.
>>>
>> This change was suggested by Laurent Pinchart and was introduced in v3. 
>> Quoting
>> Laurent:
>> "The idea is that enabling support for ADV7511 audio in the kernel isn't 
>> coupled
>> with whether the system includes audio support. It would be confusing, and 
>> would
>> also waste resources, to create a Linux sound device when no sound channel is
>> routed on the board."
> I wouldn't care too much about this at this point, the extra amount of
> resources required for registering the CODEC (but not the sound card) is
> just a few bytes (sizeof(struct snd_soc_codec)).
>
> Nevertheless what we should do is describe the hardware and from this
> information infer whether there is a audio connection or not and if there is
> none we might skip registering the CODEC. In my opinion this hardware
> description should be modeled using of-graph, having a connection between
> the SoC side and the adv7511 SPDIF or I2S port.
>

You mean something like this:

sound_playback: sound_playback {
compatible = "simple-audio-card";
[...]
simple-audio-card,format = "i2s";
[...]
}

adv7511 at xx {
compatible = "adi,adv7511";
[...]

ports {
[...]
/* Audio Output */
port at x {
reg = ;
endpoint {
remote-endpoint = <&sound_playback>;
}
}
}
}

?

Best regards,
Jose Miguel Abreu

[PATCH v8 07/10] drm/hisilicon: Add designware dsi encoder driver

[Xinliang Liu]

Add DesignWare MIPI DSI Host Controller v1.02 encoder driver
for hi6220 SoC.

v8: None.
v7:
- A few regs define clean up.
v6:
- Change "pclk_dsi" to "pclk".
v5: None.
v4: None.
v3:
- Rename file name to dw_drm_dsi.c
- Make encoder type as DRM_MODE_ENCODER_DSI.
- A few cleanup.
v2:
- Remove abtraction layer.

Signed-off-by: Xinliang Liu 
Signed-off-by: Xinwei Kong 
Signed-off-by: Andy Green 
---
 drivers/gpu/drm/hisilicon/kirin/Kconfig  |   1 +
 drivers/gpu/drm/hisilicon/kirin/Makefile |   3 +-
 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 755 +++
 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h | 103 
 4 files changed, 861 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
 create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h

diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig 
b/drivers/gpu/drm/hisilicon/kirin/Kconfig
index 3ac4b8edeac1..de0d454c5c13 100644
--- a/drivers/gpu/drm/hisilicon/kirin/Kconfig
+++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig
@@ -4,6 +4,7 @@ config DRM_HISI_KIRIN
select DRM_KMS_HELPER
select DRM_GEM_CMA_HELPER
select DRM_KMS_CMA_HELPER
+   select DRM_MIPI_DSI
help
  Choose this option if you have a hisilicon Kirin chipsets(hi6220).
  If M is selected the module will be called kirin-drm.
diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile 
b/drivers/gpu/drm/hisilicon/kirin/Makefile
index 2a61ab006ddb..5dcd0d4328b6 100644
--- a/drivers/gpu/drm/hisilicon/kirin/Makefile
+++ b/drivers/gpu/drm/hisilicon/kirin/Makefile
@@ -1,4 +1,5 @@
 kirin-drm-y := kirin_drm_drv.o \
-  kirin_drm_ade.o
+  kirin_drm_ade.o \
+  dw_drm_dsi.o

 obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o
diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c 
b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
new file mode 100644
index ..1a930b77ec53
--- /dev/null
+++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
@@ -0,0 +1,755 @@
+/*
+ * DesignWare MIPI DSI Host Controller v1.02 driver
+ *
+ * Copyright (c) 2016 Linaro Limited.
+ * Copyright (c) 2014-2016 Hisilicon Limited.
+ *
+ * Author:
+ * Xinliang Liu 
+ * Xinliang Liu 
+ * Xinwei Kong 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "dw_dsi_reg.h"
+
+#define MAX_TX_ESC_CLK 10
+#define ROUND(x, y)((x) / (y) + \
+   ((x) % (y) * 10 / (y) >= 5 ? 1 : 0))
+#define PHY_REF_CLK_RATE   1920
+#define PHY_REF_CLK_PERIOD_PS  (10 / (PHY_REF_CLK_RATE / 1000))
+
+#define encoder_to_dsi(encoder) \
+   container_of(encoder, struct dw_dsi, encoder)
+#define host_to_dsi(host) \
+   container_of(host, struct dw_dsi, host)
+
+struct mipi_phy_params {
+   u32 clk_t_lpx;
+   u32 clk_t_hs_prepare;
+   u32 clk_t_hs_zero;
+   u32 clk_t_hs_trial;
+   u32 clk_t_wakeup;
+   u32 data_t_lpx;
+   u32 data_t_hs_prepare;
+   u32 data_t_hs_zero;
+   u32 data_t_hs_trial;
+   u32 data_t_ta_go;
+   u32 data_t_ta_get;
+   u32 data_t_wakeup;
+   u32 hstx_ckg_sel;
+   u32 pll_fbd_div5f;
+   u32 pll_fbd_div1f;
+   u32 pll_fbd_2p;
+   u32 pll_enbwt;
+   u32 pll_fbd_p;
+   u32 pll_fbd_s;
+   u32 pll_pre_div1p;
+   u32 pll_pre_p;
+   u32 pll_vco_750M;
+   u32 pll_lpf_rs;
+   u32 pll_lpf_cs;
+   u32 clklp2hs_time;
+   u32 clkhs2lp_time;
+   u32 lp2hs_time;
+   u32 hs2lp_time;
+   u32 clk_to_data_delay;
+   u32 data_to_clk_delay;
+   u32 lane_byte_clk_kHz;
+   u32 clk_division;
+};
+
+struct dsi_hw_ctx {
+   void __iomem *base;
+   struct clk *pclk;
+};
+
+struct dw_dsi {
+   struct drm_encoder encoder;
+   struct drm_display_mode cur_mode;
+   struct dsi_hw_ctx *ctx;
+   struct mipi_phy_params phy;
+
+   u32 lanes;
+   enum mipi_dsi_pixel_format format;
+   unsigned long mode_flags;
+   bool enable;
+};
+
+struct dsi_data {
+   struct dw_dsi dsi;
+   struct dsi_hw_ctx ctx;
+};
+
+struct dsi_phy_range {
+   u32 min_range_kHz;
+   u32 max_range_kHz;
+   u32 pll_vco_750M;
+   u32 hstx_ckg_sel;
+};
+
+static const struct dsi_phy_range dphy_range_info[] = {
+   {   46875,62500,   1,7 },
+   {   62500,93750,   0,7 },
+   {   93750,   125000,   1,6 },
+   {  125000,   187500,   0,6 },
+   {  187500,   25,   1,5 },
+   {  25,   375000,   0,5 },
+   {  375000,   50,   1,4 },
+   {  50,   75,   0,4 },
+   {  75,  100,   1,0 },
+   { 100,  150,   0,0 }
+};
+
+static u32 dsi_calc_phy_rate(u

[PATCH] drm: atomic: fix legacy gamma set helper

[Lionel Landwerlin]

Color management properties are a bit of an odd use case because
they're not marked as atomic properties. Currently we're not updating
the non atomic values so the drm_crtc_state is out of sync with the
values stored in the crtc object.

v2: Update non atomic values only if commit succeeds (Bob Paauwe)

v3: Do not access crtc_state after commit, use crtc->state (Maarten
Lankhorst)

Cc: Maarten Lankhorst 
Cc: Bob Paauwe 
Cc: 
Signed-off-by: Lionel Landwerlin 
---
 drivers/gpu/drm/drm_atomic_helper.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
b/drivers/gpu/drm/drm_atomic_helper.c
index 7bf678e..13b86cf 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -2979,6 +2979,14 @@ retry:
if (ret)
goto fail;

+   drm_object_property_set_value(&crtc->base,
+   config->degamma_lut_property, 0);
+   drm_object_property_set_value(&crtc->base,
+   config->ctm_property, 0);
+   drm_object_property_set_value(&crtc->base,
+   config->gamma_lut_property,
+   crtc->state->gamma_lut->base.id);
+
/* Driver takes ownership of state on successful commit. */

drm_property_unreference_blob(blob);
-- 
2.8.0.rc3

[PATCH v2] drm/core: Add drm_accurate_vblank_count_and_time, v2.

[Ville Syrjälä]

On Mon, Apr 11, 2016 at 11:42:57AM +0200, Maarten Lankhorst wrote:
> This function is useful for gen2 intel devices which have no frame
> counter, but need a way to determine the current vblank count without
> racing with the vblank interrupt handler.
> 
> intel_pipe_update_start checks if no vblank interrupt will occur
> during vblank evasion, but cannot check whether the vblank handler has
> run to completion. This function uses the timestamps to determine
> when the last vblank has happened, and interpolates from there.
> 
> Changes since v1:
> - Take vblank_time_lock and don't use drm_vblank_count_and_time.
> 
> Cc: Mario Kleiner 
> Cc: Ville Syrjälä 
> Signed-off-by: Maarten Lankhorst 
> ---
>  drivers/gpu/drm/drm_irq.c | 31 +++
>  include/drm/drmP.h|  2 ++
>  2 files changed, 33 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
> index 3c1a6f18e71c..d3cecc1932e1 100644
> --- a/drivers/gpu/drm/drm_irq.c
> +++ b/drivers/gpu/drm/drm_irq.c
> @@ -303,6 +303,37 @@ static void drm_update_vblank_count(struct drm_device 
> *dev, unsigned int pipe,
>   store_vblank(dev, pipe, diff, &t_vblank, cur_vblank);
>  }
>  
> +/**
> + * drm_accurate_vblank_count_and_time - retrieve the master vblank counter
> + * @crtc: which counter to retrieve
> + * @tv_ret: last time counter was updated
> + *
> + * This function is similar to @drm_update_vblank_count_and_time but
> + * this function interpolates to handle a race with vblank irq's, and
> + * is only useful for crtc's that have no hw vblank counter.
> + */
> +
> +u32 drm_accurate_vblank_count_and_time(struct drm_crtc *crtc,
> +struct timeval *tv_ret)
> +{
> + struct drm_device *dev = crtc->dev;
> + u32 vblank, pipe = drm_crtc_index(crtc);
> + unsigned long flags;
> +
> + WARN(dev->max_vblank_count, "This function is only useful when a hw 
> counter is unavailable.");

It's useful on everything if you actually want to trust the
software counter to not be stale.

> +
> + spin_lock_irqsave(&dev->vblank_time_lock, flags);
> + drm_update_vblank_count(dev, pipe, 0);
> +
> + vblank = dev->vblank[pipe].count;
> + *tv_ret = vblanktimestamp(dev, pipe, vblank);

Do we have a user in mind that would care about the timestamp?

> +
> + spin_unlock_irqrestore(&dev->vblank_time_lock, flags);
> +
> + return vblank;
> +}
> +EXPORT_SYMBOL(drm_accurate_vblank_count_and_time);
> +
>  /*
>   * Disable vblank irq's on crtc, make sure that last vblank count
>   * of hardware and corresponding consistent software vblank counter
> diff --git a/include/drm/drmP.h b/include/drm/drmP.h
> index 31483c2fef51..1df65922c7c6 100644
> --- a/include/drm/drmP.h
> +++ b/include/drm/drmP.h
> @@ -995,6 +995,8 @@ extern void drm_crtc_vblank_off(struct drm_crtc *crtc);
>  extern void drm_crtc_vblank_reset(struct drm_crtc *crtc);
>  extern void drm_crtc_vblank_on(struct drm_crtc *crtc);
>  extern void drm_vblank_cleanup(struct drm_device *dev);
> +extern u32 drm_accurate_vblank_count_and_time(struct drm_crtc *crtc,
> +   struct timeval *tv_ret);
>  extern u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int 
> pipe);
>  
>  extern int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev,
> -- 
> 2.1.0
> 

-- 
Ville Syrjälä
Intel OTC

[Bug 116101] "RIP radeon_gem_va_ioctl+0x35/0x650", "Userspace still has active objects", and "trying to unbind memory from uninitialized GART !" when unbinding from radeon

[bugzilla-dae...@bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=116101

--- Comment #2 from Joe P.  ---
Right now the radeon card isn't being used for anything. I am using my Intel
iGPU as my output but using PRIME offloading to play games via the 290 (which
works fine). Sorry, I should have specified that in the original report.

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[PATCH libdrm] freedreno: add dummy fd_bo_from_fbdev implementation when KGSL is disabled

[Nicolas Dechesne]

Make sure that this function is defined (even empty/dummy) when KGSL support is
disabled, since it's part of the driver i/f and it was reported to cause symbols
issues when building against musl libc implementation.

Reported-by: Khem Raj 
Signed-off-by: Nicolas Dechesne 
---
 freedreno/freedreno_bo.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/freedreno/freedreno_bo.c b/freedreno/freedreno_bo.c
index a23c65d..82c1f15 100644
--- a/freedreno/freedreno_bo.c
+++ b/freedreno/freedreno_bo.c
@@ -431,3 +431,10 @@ void fd_bo_cpu_fini(struct fd_bo *bo)
 {
bo->funcs->cpu_fini(bo);
 }
+
+#ifndef HAVE_FREEDRENO_KGSL
+struct fd_bo * fd_bo_from_fbdev(struct fd_pipe *pipe, int fbfd, uint32_t size)
+{
+return NULL;
+}
+#endif
-- 
2.8.0.rc3

[Bug 116101] "RIP radeon_gem_va_ioctl+0x35/0x650", "Userspace still has active objects", and "trying to unbind memory from uninitialized GART !" when unbinding from radeon

[bugzilla-dae...@bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=116101

--- Comment #3 from Joe P.  ---
(In reply to Christian König from comment #1)
> Well as the error message already suggests "Userspace still has active
> objects !" you have an application which is still using the hardware.
> 
> So unbinding and rebinding it to the isn't possible in this state.

Just to show that it's working 

$ glxinfo | grep "OpenGL renderer"
OpenGL renderer string: Mesa DRI Intel(R) Sandybridge Server 

$ DRI_PRIME=1 glxinfo | grep "OpenGL renderer"
OpenGL renderer string: Gallium 0.4 on AMD HAWAII (DRM 2.43.0, LLVM 3.7.1)

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[PATCH v2] drm/core: Add drm_accurate_vblank_count_and_time, v2.

[Maarten Lankhorst]

Op 11-04-16 om 16:43 schreef Ville Syrjälä:
> On Mon, Apr 11, 2016 at 11:42:57AM +0200, Maarten Lankhorst wrote:
>> This function is useful for gen2 intel devices which have no frame
>> counter, but need a way to determine the current vblank count without
>> racing with the vblank interrupt handler.
>>
>> intel_pipe_update_start checks if no vblank interrupt will occur
>> during vblank evasion, but cannot check whether the vblank handler has
>> run to completion. This function uses the timestamps to determine
>> when the last vblank has happened, and interpolates from there.
>>
>> Changes since v1:
>> - Take vblank_time_lock and don't use drm_vblank_count_and_time.
>>
>> Cc: Mario Kleiner 
>> Cc: Ville Syrjälä 
>> Signed-off-by: Maarten Lankhorst 
>> ---
>>  drivers/gpu/drm/drm_irq.c | 31 +++
>>  include/drm/drmP.h|  2 ++
>>  2 files changed, 33 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
>> index 3c1a6f18e71c..d3cecc1932e1 100644
>> --- a/drivers/gpu/drm/drm_irq.c
>> +++ b/drivers/gpu/drm/drm_irq.c
>> @@ -303,6 +303,37 @@ static void drm_update_vblank_count(struct drm_device 
>> *dev, unsigned int pipe,
>>  store_vblank(dev, pipe, diff, &t_vblank, cur_vblank);
>>  }
>>  
>> +/**
>> + * drm_accurate_vblank_count_and_time - retrieve the master vblank counter
>> + * @crtc: which counter to retrieve
>> + * @tv_ret: last time counter was updated
>> + *
>> + * This function is similar to @drm_update_vblank_count_and_time but
>> + * this function interpolates to handle a race with vblank irq's, and
>> + * is only useful for crtc's that have no hw vblank counter.
>> + */
>> +
>> +u32 drm_accurate_vblank_count_and_time(struct drm_crtc *crtc,
>> +   struct timeval *tv_ret)
>> +{
>> +struct drm_device *dev = crtc->dev;
>> +u32 vblank, pipe = drm_crtc_index(crtc);
>> +unsigned long flags;
>> +
>> +WARN(dev->max_vblank_count, "This function is only useful when a hw 
>> counter is unavailable.");
> It's useful on everything if you actually want to trust the
> software counter to not be stale.
>
>> +
>> +spin_lock_irqsave(&dev->vblank_time_lock, flags);
>> +drm_update_vblank_count(dev, pipe, 0);
>> +
>> +vblank = dev->vblank[pipe].count;
>> +*tv_ret = vblanktimestamp(dev, pipe, vblank);
> Do we have a user in mind that would care about the timestamp?
>
No, I guess allowing a NULL pointer for tv_ret might help.

~Maarten

[PATCH v14 0/8] MT8173 DRM support

[Philipp Zabel]

Rebased onto v4.6-rc1, removed the HDMI driver from this series and
updated the suspend/resume code. The encoder driver pm_ops are now gone,
the encoders are disabled via atomic suspend helpers from the main driver
suspend/resume hooks. Register access in the MIPI TX driver has been
changed according to review comments, the DSI connector creation has been
clarified, and the mtk_dpi.h header file was folded into mtk_dpi.c.

Changes since v13:
 - Dropped the HDMI drivers. I'll resend them in a separate series.
 - Use atomic suspend helpers and drop encoder suspend/resume functions
 - Create DSI connector in a separate function
 - Cleanup MIPI TX register access
 - Some DPI driver cleanup

regards
Philipp

CK Hu (4):
  dt-bindings: drm/mediatek: Add Mediatek display subsystem dts binding
  drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
  drm/mediatek: Add DSI sub driver
  arm64: dts: mt8173: Add display subsystem related nodes

Jie Qiu (1):
  drm/mediatek: Add DPI sub driver

Philipp Zabel (3):
  clk: mediatek: make dpi0_sel propagate rate changes
  clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output
  clk: mediatek: remove hdmitx_dig_cts from TOP clocks

 .../bindings/display/mediatek/mediatek,disp.txt| 203 +
 .../bindings/display/mediatek/mediatek,dpi.txt |  35 +
 .../bindings/display/mediatek/mediatek,dsi.txt |  60 ++
 arch/arm64/boot/dts/mediatek/mt8173.dtsi   | 223 +
 drivers/clk/mediatek/clk-mt8173.c  |  12 +-
 drivers/clk/mediatek/clk-mtk.h |  15 +-
 drivers/gpu/drm/Kconfig|   2 +
 drivers/gpu/drm/Makefile   |   1 +
 drivers/gpu/drm/mediatek/Kconfig   |  14 +
 drivers/gpu/drm/mediatek/Makefile  |  14 +
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c| 302 +++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c   | 240 ++
 drivers/gpu/drm/mediatek/mtk_dpi.c | 769 +
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h| 228 +
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c| 582 +
 drivers/gpu/drm/mediatek/mtk_drm_crtc.h|  32 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 355 
 drivers/gpu/drm/mediatek/mtk_drm_ddp.h |  41 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c| 225 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h| 150 
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 567 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h |  59 ++
 drivers/gpu/drm/mediatek/mtk_drm_fb.c  | 165 
 drivers/gpu/drm/mediatek/mtk_drm_fb.h  |  23 +
 drivers/gpu/drm/mediatek/mtk_drm_gem.c | 269 ++
 drivers/gpu/drm/mediatek/mtk_drm_gem.h |  59 ++
 drivers/gpu/drm/mediatek/mtk_drm_plane.c   | 240 ++
 drivers/gpu/drm/mediatek/mtk_drm_plane.h   |  59 ++
 drivers/gpu/drm/mediatek/mtk_dsi.c | 927 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 463 ++
 include/dt-bindings/clock/mt8173-clk.h |   3 +-
 31 files changed, 6332 insertions(+), 5 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
 create mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
 create mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
 create mode 100644 drivers/gpu/drm/mediatek/Kconfig
 create mode 100644 drivers/gpu/drm/mediatek/Makefile
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_rdma.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi_regs.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_crtc.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_crtc.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_drv.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_drv.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_fb.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_fb.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_gem.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_gem.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_plane.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_plane.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_dsi.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.c

-- 
2.7.0

[PATCH v14 1/8] dt-bindings: drm/mediatek: Add Mediatek display subsystem dts binding

[Philipp Zabel]

From: CK Hu 

Add device tree binding documentation for the display subsystem in
Mediatek MT8173 SoCs.

Signed-off-by: CK Hu 
Signed-off-by: Philipp Zabel 
Acked-by: Rob Herring 
---
 .../bindings/display/mediatek/mediatek,disp.txt| 203 +
 .../bindings/display/mediatek/mediatek,dpi.txt |  35 
 .../bindings/display/mediatek/mediatek,dsi.txt |  60 ++
 3 files changed, 298 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
 create mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
 create mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
new file mode 100644
index 000..db6e77e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -0,0 +1,203 @@
+Mediatek display subsystem
+==
+
+The Mediatek display subsystem consists of various DISP function blocks in the
+MMSYS register space. The connections between them can be configured by output
+and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
+of frame signal are distributed to the other function blocks by a DISP_MUTEX
+function block.
+
+All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
+For a description of the MMSYS_CONFIG binding, see
+Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.
+
+DISP function blocks
+
+
+A display stream starts at a source function block that reads pixel data from
+memory and ends with a sink function block that drives pixels on a display
+interface, or writes pixels back to memory. All DISP function blocks have
+their own register space, interrupt, and clock gate. The blocks that can
+access memory additionally have to list the IOMMU and local arbiter they are
+connected to.
+
+For a description of the display interface sink function blocks, see
+Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
+Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt.
+
+Required properties (all function blocks):
+- compatible: "mediatek,-disp-", one of
+   "mediatek,-disp-ovl"   - overlay (4 layers, blending, csc)
+   "mediatek,-disp-rdma"  - read DMA / line buffer
+   "mediatek,-disp-wdma"  - write DMA
+   "mediatek,-disp-color" - color processor
+   "mediatek,-disp-aal"   - adaptive ambient light controller
+   "mediatek,-disp-gamma" - gamma correction
+   "mediatek,-disp-merge" - merge streams from two RDMA sources
+   "mediatek,-disp-split" - split stream to two encoders
+   "mediatek,-disp-ufoe"  - data compression engine
+   "mediatek,-dsi"- DSI controller, see mediatek,dsi.txt
+   "mediatek,-dpi"- DPI controller, see mediatek,dpi.txt
+   "mediatek,-disp-mutex" - display mutex
+   "mediatek,-disp-od"- overdrive
+- reg: Physical base address and length of the function block register space
+- interrupts: The interrupt signal from the function block (required, except 
for
+  merge and split function blocks).
+- clocks: device clocks
+  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+  For most function blocks this is just a single clock input. Only the DSI and
+  DPI controller nodes have multiple clock inputs. These are documented in
+  mediatek,dsi.txt and mediatek,dpi.txt, respectively.
+
+Required properties (DMA function blocks):
+- compatible: Should be one of
+   "mediatek,-disp-ovl"
+   "mediatek,-disp-rdma"
+   "mediatek,-disp-wdma"
+- larb: Should contain a phandle pointing to the local arbiter device as 
defined
+  in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt
+- iommus: Should point to the respective IOMMU block with master port as
+  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+  for details.
+
+Examples:
+
+mmsys: clock-controller at 1400 {
+   compatible = "mediatek,mt8173-mmsys", "syscon";
+   reg = <0 0x1400 0 0x1000>;
+   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+   #clock-cells = <1>;
+};
+
+ovl0: ovl at 1400c000 {
+   compatible = "mediatek,mt8173-disp-ovl";
+   reg = <0 0x1400c000 0 0x1000>;
+   interrupts = ;
+   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+   clocks = <&mmsys CLK_MM_DISP_OVL0>;
+   iommus = <&iommu M4U_PORT_DISP_OVL0>;
+   mediatek,larb = <&larb0>;
+};
+
+ovl1: ovl at 1400d000 {
+   compatible = "mediatek,mt8173-disp-ovl";
+   reg = <0 0x1400d000 0 0x1000>;
+   interrupts = ;
+   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+   clocks = <&mmsys CLK_MM_DISP_OVL1>;
+   iommus = <&iommu M4U_PORT_DISP_OVL1>;
+   mediatek,larb = <&larb4>;
+};
+
+rdma0: rdma 

[PATCH v14 3/8] drm/mediatek: Add DSI sub driver

[Philipp Zabel]

From: CK Hu 

This patch add a drm encoder/connector driver for the MIPI DSI function
block of the Mediatek display subsystem and a phy driver for the MIPI TX
D-PHY control module.

Signed-off-by: Jitao Shi 
Signed-off-by: Philipp Zabel 
--
Changes since v13:
 - Create connector in separate function
 - Remove suspend/resume functions
 - Add mipi_tx_set/clear_bits functions, rename _mask to _update_bits
 - Consolidate duplicated RG_DSI_LNT[C01234] register bit definitions
---
 drivers/gpu/drm/mediatek/Kconfig   |   2 +
 drivers/gpu/drm/mediatek/Makefile  |   4 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c |   2 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h |   2 +
 drivers/gpu/drm/mediatek/mtk_dsi.c | 927 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 463 
 6 files changed, 1399 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_dsi.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.c

diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
index 8dad892..0c49a94 100644
--- a/drivers/gpu/drm/mediatek/Kconfig
+++ b/drivers/gpu/drm/mediatek/Kconfig
@@ -3,6 +3,8 @@ config DRM_MEDIATEK
depends on DRM
depends on ARCH_MEDIATEK || (ARM && COMPILE_TEST)
select DRM_KMS_HELPER
+   select DRM_MIPI_DSI
+   select DRM_PANEL
select IOMMU_DMA
select MTK_SMI
help
diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index d4bde7c..e781db5a 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -6,6 +6,8 @@ mediatek-drm-y := mtk_disp_ovl.o \
  mtk_drm_drv.o \
  mtk_drm_fb.o \
  mtk_drm_gem.o \
- mtk_drm_plane.o
+ mtk_drm_plane.o \
+ mtk_dsi.o \
+ mtk_mipi_tx.o

 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c 
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index f749e7a..abb8fbe 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -523,6 +523,8 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_drm_platform_driver,
&mtk_disp_ovl_driver,
&mtk_disp_rdma_driver,
+   &mtk_dsi_driver,
+   &mtk_mipi_tx_driver,
 };

 static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h 
b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index fb60057..1f22ec4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -52,5 +52,7 @@ struct mtk_drm_private {

 extern struct platform_driver mtk_disp_ovl_driver;
 extern struct platform_driver mtk_disp_rdma_driver;
+extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_mipi_tx_driver;

 #endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
new file mode 100644
index 000..54e8ff5
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -0,0 +1,927 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "mtk_drm_ddp_comp.h"
+
+#define DSI_VIDEO_FIFO_DEPTH   (1920 / 4)
+#define DSI_HOST_FIFO_DEPTH64
+
+#define DSI_START  0x00
+
+#define DSI_CON_CTRL   0x10
+#define DSI_RESET  BIT(0)
+#define DSI_EN BIT(1)
+
+#define DSI_MODE_CTRL  0x14
+#define MODE   (3)
+#define CMD_MODE   0
+#define SYNC_PULSE_MODE1
+#define SYNC_EVENT_MODE2
+#define BURST_MODE 3
+#define FRM_MODE   BIT(16)
+#define MIX_MODE   BIT(17)
+
+#define DSI_TXRX_CTRL  0x18
+#define VC_NUM (2 << 0)
+#define LANE_NUM   (0xf << 2)
+#define DIS_EOTBIT(6)
+#define NULL_ENBIT(7)
+#define TE_FREERUN BIT(8)
+#define EXT_TE_EN  BIT(9)
+#define EXT_TE_EDGEBIT(10)
+#define MAX_RTN_SIZE   (0xf << 12)
+#define HSTX_CKLP_EN   BIT(16)
+
+#define DSI_PSCTRL 0x1c
+#define DSI_PS_WC  0x3f

[PATCH v14 4/8] drm/mediatek: Add DPI sub driver

[Philipp Zabel]

From: Jie Qiu 

Add DPI connector/encoder to support HDMI output via the
attached HDMI bridge.

Signed-off-by: Jie Qiu 
Signed-off-by: Philipp Zabel 
--
Changes since v13:
 - Remove suspend/resume functions
 - Meld mtk_dpi.h into mtk_dpi.c
 - Make mtk_dpi_set_display_mode static
 - Fix missing bridge node error path
---
 drivers/gpu/drm/mediatek/Makefile   |   3 +-
 drivers/gpu/drm/mediatek/mtk_dpi.c  | 769 
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 228 ++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   1 +
 5 files changed, 1001 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi_regs.h

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index e781db5a..5fcf58e 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -8,6 +8,7 @@ mediatek-drm-y := mtk_disp_ovl.o \
  mtk_drm_gem.o \
  mtk_drm_plane.o \
  mtk_dsi.o \
- mtk_mipi_tx.o
+ mtk_mipi_tx.o \
+ mtk_dpi.o

 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c 
b/drivers/gpu/drm/mediatek/mtk_dpi.c
new file mode 100644
index 000..d05ca79
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -0,0 +1,769 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Jie Qiu 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "mtk_dpi_regs.h"
+#include "mtk_drm_ddp_comp.h"
+
+enum mtk_dpi_out_bit_num {
+   MTK_DPI_OUT_BIT_NUM_8BITS,
+   MTK_DPI_OUT_BIT_NUM_10BITS,
+   MTK_DPI_OUT_BIT_NUM_12BITS,
+   MTK_DPI_OUT_BIT_NUM_16BITS
+};
+
+enum mtk_dpi_out_yc_map {
+   MTK_DPI_OUT_YC_MAP_RGB,
+   MTK_DPI_OUT_YC_MAP_CYCY,
+   MTK_DPI_OUT_YC_MAP_YCYC,
+   MTK_DPI_OUT_YC_MAP_CY,
+   MTK_DPI_OUT_YC_MAP_YC
+};
+
+enum mtk_dpi_out_channel_swap {
+   MTK_DPI_OUT_CHANNEL_SWAP_RGB,
+   MTK_DPI_OUT_CHANNEL_SWAP_GBR,
+   MTK_DPI_OUT_CHANNEL_SWAP_BRG,
+   MTK_DPI_OUT_CHANNEL_SWAP_RBG,
+   MTK_DPI_OUT_CHANNEL_SWAP_GRB,
+   MTK_DPI_OUT_CHANNEL_SWAP_BGR
+};
+
+enum mtk_dpi_out_color_format {
+   MTK_DPI_COLOR_FORMAT_RGB,
+   MTK_DPI_COLOR_FORMAT_RGB_FULL,
+   MTK_DPI_COLOR_FORMAT_YCBCR_444,
+   MTK_DPI_COLOR_FORMAT_YCBCR_422,
+   MTK_DPI_COLOR_FORMAT_XV_YCC,
+   MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL,
+   MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL
+};
+
+struct mtk_dpi {
+   struct mtk_ddp_comp ddp_comp;
+   struct drm_encoder encoder;
+   void __iomem *regs;
+   struct device *dev;
+   struct clk *engine_clk;
+   struct clk *pixel_clk;
+   struct clk *tvd_clk;
+   int irq;
+   struct drm_display_mode mode;
+   enum mtk_dpi_out_color_format color_format;
+   enum mtk_dpi_out_yc_map yc_map;
+   enum mtk_dpi_out_bit_num bit_num;
+   enum mtk_dpi_out_channel_swap channel_swap;
+   bool power_sta;
+   u8 power_ctl;
+};
+
+static inline struct mtk_dpi *mtk_dpi_from_encoder(struct drm_encoder *e)
+{
+   return container_of(e, struct mtk_dpi, encoder);
+}
+
+enum mtk_dpi_polarity {
+   MTK_DPI_POLARITY_RISING,
+   MTK_DPI_POLARITY_FALLING,
+};
+
+enum mtk_dpi_power_ctl {
+   DPI_POWER_START = BIT(0),
+   DPI_POWER_ENABLE = BIT(1),
+};
+
+struct mtk_dpi_polarities {
+   enum mtk_dpi_polarity de_pol;
+   enum mtk_dpi_polarity ck_pol;
+   enum mtk_dpi_polarity hsync_pol;
+   enum mtk_dpi_polarity vsync_pol;
+};
+
+struct mtk_dpi_sync_param {
+   u32 sync_width;
+   u32 front_porch;
+   u32 back_porch;
+   bool shift_half_line;
+};
+
+struct mtk_dpi_yc_limit {
+   u16 y_top;
+   u16 y_bottom;
+   u16 c_top;
+   u16 c_bottom;
+};
+
+static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
+{
+   u32 tmp = readl(dpi->regs + offset) & ~mask;
+
+   tmp |= (val & mask);
+   writel(tmp, dpi->regs + offset);
+}
+
+static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset)
+{
+   mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST);
+}
+
+static void mtk_dpi_enable(struct mtk_dpi *dpi)
+{
+   mtk_dpi_mask(dpi, DPI_EN, EN, EN);
+}
+
+static void mtk_dpi_disable(struct mtk_dpi *dpi)
+{
+   mtk_dpi_mask(dpi, DPI_EN, 0, EN);
+}
+
+static void mtk_dpi_conf

[PATCH v14 2/8] drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.

[Philipp Zabel]

From: CK Hu 

This patch adds an initial DRM driver for the Mediatek MT8173 DISP
subsystem. It currently supports two fixed output streams from the
OVL0/OVL1 sources to the DSI0/DPI0 sinks, respectively.

Signed-off-by: CK Hu 
Signed-off-by: YT Shen 
Signed-off-by: Daniel Kurtz 
Signed-off-by: Bibby Hsieh 
Signed-off-by: Mao Huang 
Signed-off-by: Philipp Zabel 
---
Changes since v13:
 - Use atomic suspend helpers
---
 drivers/gpu/drm/Kconfig |   2 +
 drivers/gpu/drm/Makefile|   1 +
 drivers/gpu/drm/mediatek/Kconfig|  12 +
 drivers/gpu/drm/mediatek/Makefile   |  11 +
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 302 +++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c| 240 
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 582 
 drivers/gpu/drm/mediatek/mtk_drm_crtc.h |  32 ++
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c  | 355 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp.h  |  41 ++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 225 +++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 150 +++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  | 564 +++
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |  56 +++
 drivers/gpu/drm/mediatek/mtk_drm_fb.c   | 165 
 drivers/gpu/drm/mediatek/mtk_drm_fb.h   |  23 ++
 drivers/gpu/drm/mediatek/mtk_drm_gem.c  | 269 +
 drivers/gpu/drm/mediatek/mtk_drm_gem.h  |  59 +++
 drivers/gpu/drm/mediatek/mtk_drm_plane.c| 240 
 drivers/gpu/drm/mediatek/mtk_drm_plane.h|  59 +++
 20 files changed, 3388 insertions(+)
 create mode 100644 drivers/gpu/drm/mediatek/Kconfig
 create mode 100644 drivers/gpu/drm/mediatek/Makefile
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_rdma.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_crtc.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_crtc.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_drv.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_drv.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_fb.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_fb.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_gem.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_gem.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_plane.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_plane.h

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index f2a74d0..5482012 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -281,3 +281,5 @@ source "drivers/gpu/drm/imx/Kconfig"
 source "drivers/gpu/drm/vc4/Kconfig"

 source "drivers/gpu/drm/etnaviv/Kconfig"
+
+source "drivers/gpu/drm/mediatek/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 6eb94fc..02b1f3e 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -73,6 +73,7 @@ obj-$(CONFIG_DRM_MSM) += msm/
 obj-$(CONFIG_DRM_TEGRA) += tegra/
 obj-$(CONFIG_DRM_STI) += sti/
 obj-$(CONFIG_DRM_IMX) += imx/
+obj-$(CONFIG_DRM_MEDIATEK) += mediatek/
 obj-y  += i2c/
 obj-y  += panel/
 obj-y  += bridge/
diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
new file mode 100644
index 000..8dad892
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/Kconfig
@@ -0,0 +1,12 @@
+config DRM_MEDIATEK
+   tristate "DRM Support for Mediatek SoCs"
+   depends on DRM
+   depends on ARCH_MEDIATEK || (ARM && COMPILE_TEST)
+   select DRM_KMS_HELPER
+   select IOMMU_DMA
+   select MTK_SMI
+   help
+ Choose this option if you have a Mediatek SoCs.
+ The module will be called mediatek-drm
+ This driver provides kernel mode setting and
+ buffer management to userspace.
diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
new file mode 100644
index 000..d4bde7c
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -0,0 +1,11 @@
+mediatek-drm-y := mtk_disp_ovl.o \
+ mtk_disp_rdma.o \
+ mtk_drm_crtc.o \
+ mtk_drm_ddp.o \
+ mtk_drm_ddp_comp.o \
+ mtk_drm_drv.o \
+ mtk_drm_fb.o \
+ mtk_drm_gem.o \
+ mtk_drm_plane.o
+
+obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
new file mode 100644
index 000..8f62671f
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -0,0 +1,302 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ *
+ * This progra

[PATCH v14 5/8] clk: mediatek: make dpi0_sel propagate rate changes

[Philipp Zabel]

This mux is supposed to select a fitting divider after the PLL
is already set to the correct rate.

Signed-off-by: Philipp Zabel 
Acked-by: James Liao 
Acked-by: Stephen Boyd 
---
 drivers/clk/mediatek/clk-mt8173.c |  6 +-
 drivers/clk/mediatek/clk-mtk.h| 15 +--
 2 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8173.c 
b/drivers/clk/mediatek/clk-mt8173.c
index 227e356..85c0bfc 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -558,7 +558,11 @@ static const struct mtk_composite top_muxes[] __initconst 
= {
MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 
24, 4, 31),
/* CLK_CFG_6 */
-   MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7),
+   /*
+* The dpi0_sel clock should not propagate rate changes to its parent
+* clock so the dpi driver can have full control over PLL and divider.
+*/
+   MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 
3, 7, 0),
MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 
3, 23),
MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 
31),
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 32d2e45..9f24fcf 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -83,7 +83,11 @@ struct mtk_composite {
signed char num_parents;
 };

-#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) {  \
+/*
+ * In case the rate change propagation to parent clocks is undesirable,
+ * this macro allows to specify the clock flags manually.
+ */
+#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, 
_flags) {\
.id = _id,  \
.name = _name,  \
.mux_reg = _reg,\
@@ -94,9 +98,16 @@ struct mtk_composite {
.divider_shift = -1,\
.parent_names = _parents,   \
.num_parents = ARRAY_SIZE(_parents),\
-   .flags = CLK_SET_RATE_PARENT,   \
+   .flags = _flags,\
}

+/*
+ * Unless necessary, all MUX_GATE clocks propagate rate changes to their
+ * parent clock by default.
+ */
+#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate)\
+   MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, 
CLK_SET_RATE_PARENT)
+
 #define MUX(_id, _name, _parents, _reg, _shift, _width) {  \
.id = _id,  \
.name = _name,  \
-- 
2.7.0

[PATCH v14 8/8] arm64: dts: mt8173: Add display subsystem related nodes

[Philipp Zabel]

From: CK Hu 

This patch adds the device nodes for the DISP function blocks
comprising the display subsystem.

Signed-off-by: CK Hu 
Signed-off-by: Cawa Cheng 
Signed-off-by: Jie Qiu 
Signed-off-by: Daniel Kurtz 
Signed-off-by: Philipp Zabel 
---
Changes since v13:
 - Remove HDMI DDC I2C node, this should be added by the HDMI patch
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 223 +++
 1 file changed, 223 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index eab7efc..2734694 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -26,6 +26,23 @@
#address-cells = <2>;
#size-cells = <2>;

+   aliases {
+   ovl0 = &ovl0;
+   ovl1 = &ovl1;
+   rdma0 = &rdma0;
+   rdma1 = &rdma1;
+   rdma2 = &rdma2;
+   wdma0 = &wdma0;
+   wdma1 = &wdma1;
+   color0 = &color0;
+   color1 = &color1;
+   split0 = &split0;
+   split1 = &split1;
+   dpi0 = &dpi0;
+   dsi0 = &dsi0;
+   dsi1 = &dsi1;
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -300,6 +317,26 @@
#clock-cells = <1>;
};

+   mipi_tx0: mipi-dphy at 10215000 {
+   compatible = "mediatek,mt8173-mipi-tx";
+   reg = <0 0x10215000 0 0x1000>;
+   clocks = <&clk26m>;
+   clock-output-names = "mipi_tx0_pll";
+   #clock-cells = <0>;
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+
+   mipi_tx1: mipi-dphy at 10216000 {
+   compatible = "mediatek,mt8173-mipi-tx";
+   reg = <0 0x10216000 0 0x1000>;
+   clocks = <&clk26m>;
+   clock-output-names = "mipi_tx1_pll";
+   #clock-cells = <0>;
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+
gic: interrupt-controller at 1022 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -592,9 +629,181 @@
mmsys: clock-controller at 1400 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0 0x1400 0 0x1000>;
+   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
#clock-cells = <1>;
};

+   ovl0: ovl at 1400c000 {
+   compatible = "mediatek,mt8173-disp-ovl";
+   reg = <0 0x1400c000 0 0x1000>;
+   interrupts = ;
+   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+   clocks = <&mmsys CLK_MM_DISP_OVL0>;
+   iommus = <&iommu M4U_PORT_DISP_OVL0>;
+   mediatek,larb = <&larb0>;
+   };
+
+   ovl1: ovl at 1400d000 {
+   compatible = "mediatek,mt8173-disp-ovl";
+   reg = <0 0x1400d000 0 0x1000>;
+   interrupts = ;
+   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+   clocks = <&mmsys CLK_MM_DISP_OVL1>;
+   iommus = <&iommu M4U_PORT_DISP_OVL1>;
+   mediatek,larb = <&larb4>;
+   };
+
+   rdma0: rdma at 1400e000 {
+   compatible = "mediatek,mt8173-disp-rdma";
+   reg = <0 0x1400e000 0 0x1000>;
+   interrupts = ;
+   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+   clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+   iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+   mediatek,larb = <&larb0>;
+   };
+
+   rdma1: rdma at 1400f000 {
+   compatible = "mediatek,mt8173-disp-rdma";
+   reg = <0 0x1400f000 0 0x1000>;
+   interrupts = ;
+   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+   clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+   iommus = <&iommu M4U_PORT_DISP_RDMA1>;
+   mediatek,larb = <&larb4>;
+   };
+
+   rdma2: rdma at 1401 {
+   compatible = "mediatek,mt8173-disp-rdma";
+   reg = <0 0x1401 0 0x1000>;
+   interrupts = ;
+   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+   clocks = <&mmsys CLK_MM_DISP_RDMA2>;
+   iommus = <&i

[PATCH v14 7/8] clk: mediatek: remove hdmitx_dig_cts from TOP clocks

[Philipp Zabel]

The hdmitx_dig_cts clock signal is not a child of tvdpll_445p5m,
but is routed out of the HDMI PHY module.

Signed-off-by: Philipp Zabel 
Acked-by: Stephen Boyd 
---
 drivers/clk/mediatek/clk-mt8173.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/clk/mediatek/clk-mt8173.c 
b/drivers/clk/mediatek/clk-mt8173.c
index cf4fcb6..10c9860 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -61,7 +61,6 @@ static const struct mtk_fixed_factor top_divs[] __initconst = 
{
FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1),

-   FACTOR(CLK_TOP_HDMITX_DIG_CTS, "hdmitx_dig_cts", "tvdpll_445p5m", 1, 3),
FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2),
FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3),

-- 
2.7.0

[PATCH v14 6/8] clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output

[Philipp Zabel]

The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.

Signed-off-by: Philipp Zabel 
Acked-by: James Liao 
Acked-by: Stephen Boyd 
---
 drivers/clk/mediatek/clk-mt8173.c  | 5 +
 include/dt-bindings/clock/mt8173-clk.h | 3 ++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/mediatek/clk-mt8173.c 
b/drivers/clk/mediatek/clk-mt8173.c
index 85c0bfc..cf4fcb6 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -1095,6 +1095,11 @@ static void __init mtk_apmixedsys_init(struct 
device_node *node)
clk_data->clks[cku->id] = clk;
}

+   clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,
+  base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,
+  NULL);
+   clk_data->clks[CLK_APMIXED_HDMI_REF] = clk;
+
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
diff --git a/include/dt-bindings/clock/mt8173-clk.h 
b/include/dt-bindings/clock/mt8173-clk.h
index 7956ba1..6094bf7 100644
--- a/include/dt-bindings/clock/mt8173-clk.h
+++ b/include/dt-bindings/clock/mt8173-clk.h
@@ -176,7 +176,8 @@
 #define CLK_APMIXED_LVDSPLL13
 #define CLK_APMIXED_MSDCPLL2   14
 #define CLK_APMIXED_REF2USB_TX 15
-#define CLK_APMIXED_NR_CLK 16
+#define CLK_APMIXED_HDMI_REF   16
+#define CLK_APMIXED_NR_CLK 17

 /* INFRA_SYS */

-- 
2.7.0

[PATCH v14 0/6] MT8173 HDMI support

[Philipp Zabel]

This series contains the HDMI encoder, PHY, and DDC drivers split out
from the "MT8173 DRM support" series.

Changes since v13:
 - Don't disable output in suspend/resume, the bridge will be disabled
   by the upstream encoder
 - Combine hdmi bridge driver into mtk_hdmi.c
 - Remove mtk_cec_irq
 - Add PHY set/clear_bit register access functions
 - Rename hdmi_i2c to hdmi_ddc for consistency
 - Track bridge enable state
 - Various cleanups and fixes

regards
Philipp

CK Hu (1):
  arm64: dts: mt8173: Add HDMI related nodes

Jie Qiu (2):
  drm/mediatek: Add HDMI support
  drm/mediatek: enable hdmi output control bit

Philipp Zabel (3):
  dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding
  dt-bindings: hdmi-connector: add DDC I2C bus phandle documentation
  arm64: dts: mt8173-evb: enable HDMI output

 .../bindings/display/connector/hdmi-connector.txt  |1 +
 .../bindings/display/mediatek/mediatek,hdmi.txt|  148 ++
 arch/arm64/boot/dts/mediatek/mt8173-evb.dts|   38 +
 arch/arm64/boot/dts/mediatek/mt8173.dtsi   |   77 +
 drivers/gpu/drm/mediatek/Kconfig   |7 +
 drivers/gpu/drm/mediatek/Makefile  |7 +
 drivers/gpu/drm/mediatek/mtk_cec.c |  265 +++
 drivers/gpu/drm/mediatek/mtk_cec.h |   26 +
 drivers/gpu/drm/mediatek/mtk_hdmi.c| 1762 
 drivers/gpu/drm/mediatek/mtk_hdmi.h|   23 +
 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c|  358 
 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h   |  238 +++
 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c |  515 ++
 13 files changed, 3465 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
 create mode 100644 drivers/gpu/drm/mediatek/mtk_cec.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_cec.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c

-- 
2.7.0

[PATCH v14 1/6] dt-bindings: drm/mediatek: Add Mediatek HDMI dts binding

[Philipp Zabel]

Add the device tree binding documentation for Mediatek HDMI,
HDMI PHY and HDMI DDC devices.

Signed-off-by: Philipp Zabel 
Acked-by: Rob Herring 
---
 .../bindings/display/mediatek/mediatek,hdmi.txt| 148 +
 1 file changed, 148 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
new file mode 100644
index 000..7b12424
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
@@ -0,0 +1,148 @@
+Mediatek HDMI Encoder
+=
+
+The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
+its parallel input.
+
+Required properties:
+- compatible: Should be "mediatek,-hdmi".
+- reg: Physical base address and length of the controller's registers
+- interrupts: The interrupt signal from the function block.
+- clocks: device clocks
+  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
+- phys: phandle link to the HDMI PHY node.
+  See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
+- phy-names: must contain "hdmi"
+- mediatek,syscon-hdmi: phandle link and register offset to the system
+  configuration registers. For mt8173 this must be offset 0x900 into the
+  MMSYS_CONFIG region: <&mmsys 0x900>.
+- ports: A node containing input and output port nodes with endpoint
+  definitions as documented in Documentation/devicetree/bindings/graph.txt.
+- port at 0: The input port in the ports node should be connected to a DPI 
output
+  port.
+- port at 1: The output port in the ports node should be connected to the input
+  port of a connector node that contains a ddc-i2c-bus property, or to the
+  input port of an attached bridge chip, such as a SlimPort transmitter.
+
+HDMI CEC
+
+
+The HDMI CEC controller handles hotplug detection and CEC communication.
+
+Required properties:
+- compatible: Should be "mediatek,-cec"
+- reg: Physical base address and length of the controller's registers
+- interrupts: The interrupt signal from the function block.
+- clocks: device clock
+
+HDMI DDC
+
+
+The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
+The Mediatek's I2C controller is used to interface with I2C devices.
+
+Required properties:
+- compatible: Should be "mediatek,-hdmi-ddc"
+- reg: Physical base address and length of the controller's registers
+- clocks: device clock
+- clock-names: Should be "ddc-i2c".
+
+HDMI PHY
+
+
+The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
+output and drives the HDMI pads.
+
+Required properties:
+- compatible: "mediatek,-hdmi-phy"
+- reg: Physical base address and length of the module's registers
+- clocks: PLL reference clock
+- clock-names: must contain "pll_ref"
+- clock-output-names: must be "hdmitx_dig_cts" on mt8173
+- #phy-cells: must be <0>
+- #clock-cells: must be <0>
+
+Optional properties:
+- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
+- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
+
+Example:
+
+cec: cec at 10013000 {
+   compatible = "mediatek,mt8173-cec";
+   reg = <0 0x10013000 0 0xbc>;
+   interrupts = ;
+   clocks = <&infracfg CLK_INFRA_CEC>;
+};
+
+hdmi_phy: hdmi-phy at 10209100 {
+   compatible = "mediatek,mt8173-hdmi-phy";
+   reg = <0 0x10209100 0 0x24>;
+   clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+   clock-names = "pll_ref";
+   clock-output-names = "hdmitx_dig_cts";
+   mediatek,ibias = <0xa>;
+   mediatek,ibias_up = <0x1c>;
+   #clock-cells = <0>;
+   #phy-cells = <0>;
+};
+
+hdmi_ddc0: i2c at 11012000 {
+   compatible = "mediatek,mt8173-hdmi-ddc";
+   reg = <0 0x11012000 0 0x1c>;
+   interrupts = ;
+   clocks = <&pericfg CLK_PERI_I2C5>;
+   clock-names = "ddc-i2c";
+};
+
+hdmi0: hdmi at 14025000 {
+   compatible = "mediatek,mt8173-hdmi";
+   reg = <0 0x14025000 0 0x400>;
+   interrupts = ;
+   clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+<&mmsys CLK_MM_HDMI_PLLCK>,
+<&mmsys CLK_MM_HDMI_AUDIO>,
+<&mmsys CLK_MM_HDMI_SPDIF>;
+   clock-names = "pixel", "pll", "bclk", "spdif";
+   pinctrl-names = "default";
+   pinctrl-0 = <&hdmi_pin>;
+   phys = <&hdmi_phy>;
+   phy-names = "hdmi";
+   mediatek,syscon-hdmi = <&mmsys 0x900>;
+   assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
+   assigned-clock-parents = <&hdmi_phy>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port at 0 {
+   reg = <0>;
+
+   hdmi0_in: endpoint {
+   remote-endpoint = <&dpi0_out>;
+ 

[PATCH v14 2/6] drm/mediatek: Add HDMI support

[Philipp Zabel]

From: Jie Qiu 

This patch adds drivers for the HDMI bridge connected to the DPI0
display subsystem function block, for the HDMI DDC block, and for
the HDMI PHY to support HDMI output.

Signed-off-by: Jie Qiu 
Signed-off-by: Philipp Zabel 
---
Changes since v13:
 - Don't disable output in suspend/resume
 - Combine hdmi bridge driver into mtk_hdmi.c
 - Remove mtk_cec_irq
 - Add PHY set/clear_bit register access functions
 - Rename hdmi_i2c to hdmi_ddc for consistency
 - Track bridge enable state
 - Various cleanup and fixes
---
 drivers/gpu/drm/mediatek/Kconfig   |7 +
 drivers/gpu/drm/mediatek/Makefile  |7 +
 drivers/gpu/drm/mediatek/mtk_cec.c |  265 
 drivers/gpu/drm/mediatek/mtk_cec.h |   26 +
 drivers/gpu/drm/mediatek/mtk_hdmi.c| 1750 
 drivers/gpu/drm/mediatek/mtk_hdmi.h|   23 +
 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c|  358 +
 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h   |  237 
 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c |  515 +++
 9 files changed, 3188 insertions(+)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_cec.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_cec.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c

diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
index 0c49a94..e2ff158 100644
--- a/drivers/gpu/drm/mediatek/Kconfig
+++ b/drivers/gpu/drm/mediatek/Kconfig
@@ -12,3 +12,10 @@ config DRM_MEDIATEK
  The module will be called mediatek-drm
  This driver provides kernel mode setting and
  buffer management to userspace.
+
+config DRM_MEDIATEK_HDMI
+   tristate "DRM HDMI Support for Mediatek SoCs"
+   depends on DRM_MEDIATEK
+   select GENERIC_PHY
+   help
+ DRM/KMS HDMI driver for Mediatek SoCs
diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index 5fcf58e..bf2e5be 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -12,3 +12,10 @@ mediatek-drm-y := mtk_disp_ovl.o \
  mtk_dpi.o

 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
+
+mediatek-drm-hdmi-objs := mtk_cec.o \
+ mtk_hdmi.o \
+ mtk_hdmi_ddc.o \
+ mtk_mt8173_hdmi_phy.o
+
+obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c 
b/drivers/gpu/drm/mediatek/mtk_cec.c
new file mode 100644
index 000..7a3eb8c
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_cec.c
@@ -0,0 +1,265 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Jie Qiu 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "mtk_cec.h"
+
+#define TR_CONFIG  0x00
+#define CLEAR_CEC_IRQ  BIT(15)
+
+#define CEC_CKGEN  0x04
+#define CEC_32K_PDNBIT(19)
+#define PDNBIT(16)
+
+#define RX_EVENT   0x54
+#define HDMI_PORD  BIT(25)
+#define HDMI_HTPLG BIT(24)
+#define HDMI_PORD_INT_EN   BIT(9)
+#define HDMI_HTPLG_INT_EN  BIT(8)
+
+#define RX_GEN_WD  0x58
+#define HDMI_PORD_INT_32K_STATUS   BIT(26)
+#define RX_RISC_INT_32K_STATUS BIT(25)
+#define HDMI_HTPLG_INT_32K_STATUS  BIT(24)
+#define HDMI_PORD_INT_32K_CLR  BIT(18)
+#define RX_INT_32K_CLR BIT(17)
+#define HDMI_HTPLG_INT_32K_CLR BIT(16)
+#define HDMI_PORD_INT_32K_STA_MASK BIT(10)
+#define RX_RISC_INT_32K_STA_MASK   BIT(9)
+#define HDMI_HTPLG_INT_32K_STA_MASKBIT(8)
+#define HDMI_PORD_INT_32K_EN   BIT(2)
+#define RX_INT_32K_EN  BIT(1)
+#define HDMI_HTPLG_INT_32K_EN  BIT(0)
+
+#define NORMAL_INT_CTRL0x5C
+#define HDMI_HTPLG_INT_STA BIT(0)
+#define HDMI_PORD_INT_STA  BIT(1)
+#define HDMI_HTPLG_INT_CLR BIT(16)
+#define HDMI_PORD_INT_CLR  BIT(17)
+#define HDMI_FULL_INT_CLR  BIT(20)
+
+struct mtk_cec {
+   void __iomem *regs;
+   struct clk *clk;
+   int irq;
+   bool hpd;
+   void (*hpd_event)(bool hpd, struct device *dev);
+   struct device *hdmi_de

[PATCH v14 4/6] arm64: dts: mt8173: Add HDMI related nodes

[Philipp Zabel]

From: CK Hu 

This patch adds the device nodes for the HDMI encoder, HDMI PHY,
and HDMI CEC modules.

Signed-off-by: CK Hu 
Signed-off-by: Cawa Cheng 
Signed-off-by: Jie Qiu 
Signed-off-by: Daniel Kurtz 
Signed-off-by: Philipp Zabel 
--
Changes since v13:
 - Add HDMI DDC I2C node
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 77 
 1 file changed, 77 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 2734694..225bcd1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -199,6 +199,16 @@
 ,
 ;

+   hdmi_pin: xxx {
+
+   /*hdmi htplg pin*/
+   pins1 {
+   pinmux = 
;
+   input-enable;
+   bias-pull-down;
+   };
+   };
+
i2c0_pins_a: i2c0 {
pins1 {
pinmux = 
,
@@ -286,6 +296,14 @@
clock-names = "spi", "wrap";
};

+   cec: cec at 10013000 {
+   compatible = "mediatek,mt8173-cec";
+   reg = <0 0x10013000 0 0xbc>;
+   interrupts = ;
+   clocks = <&infracfg CLK_INFRA_CEC>;
+   status = "disabled";
+   };
+
sysirq: intpol-controller at 10200620 {
compatible = "mediatek,mt8173-sysirq",
 "mediatek,mt6577-sysirq";
@@ -317,6 +335,19 @@
#clock-cells = <1>;
};

+   hdmi_phy: hdmi-phy at 10209100 {
+   compatible = "mediatek,mt8173-hdmi-phy";
+   reg = <0 0x10209100 0 0x24>;
+   clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+   clock-names = "pll_ref";
+   clock-output-names = "hdmitx_dig_cts";
+   mediatek,ibias = <0xa>;
+   mediatek,ibias_up = <0x1c>;
+   #clock-cells = <0>;
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+
mipi_tx0: mipi-dphy at 10215000 {
compatible = "mediatek,mt8173-mipi-tx";
reg = <0 0x10215000 0 0x1000>;
@@ -494,6 +525,14 @@
status = "disabled";
};

+   hdmiddc0: i2c at 11012000 {
+   compatible = "mediatek,mt8173-hdmi-ddc";
+   interrupts = ;
+   reg = <0 0x11012000 0 0x1C>;
+   clocks = <&pericfg CLK_PERI_I2C5>;
+   clock-names = "ddc-i2c";
+   };
+
i2c6: i2c at 11013000 {
compatible = "mediatek,mt8173-i2c";
reg = <0 0x11013000 0 0x70>,
@@ -802,6 +841,12 @@
 <&apmixedsys CLK_APMIXED_TVDPLL>;
clock-names = "pixel", "engine", "pll";
status = "disabled";
+
+   port {
+   dpi0_out: endpoint {
+   remote-endpoint = <&hdmi0_in>;
+   };
+   };
};

pwm0: pwm at 1401e000 {
@@ -859,6 +904,38 @@
clocks = <&mmsys CLK_MM_DISP_OD>;
};

+   hdmi0: hdmi at 14025000 {
+   compatible = "mediatek,mt8173-hdmi";
+   reg = <0 0x14025000 0 0x400>;
+   interrupts = ;
+   clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+<&mmsys CLK_MM_HDMI_PLLCK>,
+<&mmsys CLK_MM_HDMI_AUDIO>,
+<&mmsys CLK_MM_HDMI_SPDIF>;
+   clock-names = "pixel", "pll", "bclk", "spdif";
+   pinctrl-names = "default";
+   pinctrl-0 = <&hdmi_pin>;
+   phys = <&hdmi_phy>;
+   phy-names = "hdmi";
+   mediatek,syscon-hdmi = <&mmsys 0x900>;
+   assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
+   assigned-clock-parents = <&hdmi_phy>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port at 0 {
+   reg = <0>;
+
+   

[PATCH v14 5/6] dt-bindings: hdmi-connector: add DDC I2C bus phandle documentation

[Philipp Zabel]

Add an optional ddc-i2c-bus phandle property that points to
an I2C master controller that handles the connector DDC pins.

Signed-off-by: Philipp Zabel 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/display/connector/hdmi-connector.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git 
a/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt 
b/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt
index acd5668..508aee4 100644
--- a/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt
+++ b/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt
@@ -8,6 +8,7 @@ Required properties:
 Optional properties:
 - label: a symbolic name for the connector
 - hpd-gpios: HPD GPIO number
+- ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing

 Required nodes:
 - Video port for HDMI input
-- 
2.7.0

[PATCH v14 6/6] arm64: dts: mt8173-evb: enable HDMI output

[Philipp Zabel]

Add an HDMI connector node and enable the devices that are part of the
HDMI display path: cec, dpi0, hdmi_phy, and hdmi0.

Signed-off-by: Philipp Zabel 
---
 arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 38 +
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index 7453a47..2a7f731 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -42,6 +42,44 @@
gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+   connector {
+   compatible = "hdmi-connector";
+   label = "hdmi";
+   type = "d";
+
+   port {
+   hdmi_connector_in: endpoint {
+   remote-endpoint = <&hdmi0_out>;
+   };
+   };
+   };
+};
+
+&cec {
+   status = "okay";
+};
+
+&dpi0 {
+   status = "okay";
+};
+
+&hdmi_phy {
+   status = "okay";
+};
+
+&hdmi0 {
+   status = "okay";
+
+   ports {
+   port at 1 {
+   reg = <1>;
+
+   hdmi0_out: endpoint {
+   remote-endpoint = <&hdmi_connector_in>;
+   };
+   };
+   };
 };

 &i2c1 {
-- 
2.7.0

[PATCH v14 3/6] drm/mediatek: enable hdmi output control bit

[Philipp Zabel]

From: Jie Qiu 

MT8173 HDMI hardware has a output control bit to enable/disable HDMI
output. Because of security reason, so this bit can ONLY be controlled
in ARM supervisor mode. Now the only way to enter ARM supervisor is the
ARM trusted firmware. So atf provides a API for HDMI driver to call to
setup this HDMI control bit to enable HDMI output in supervisor mode.

Signed-off-by: Jie Qiu 
Signed-off-by: Philipp Zabel 
---
 drivers/gpu/drm/mediatek/mtk_hdmi.c  | 12 
 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h |  1 +
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c 
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 4cd4c01..044c356 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -246,6 +247,17 @@ static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, 
bool black)

 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
 {
+   struct arm_smccc_res res;
+
+   /*
+* MT8173 HDMI hardware has an output control bit to enable/disable HDMI
+* output. This bit can only be controlled in ARM supervisor mode.
+* The ARM trusted firmware provides an API for the HDMI driver to set
+* this control bit to enable HDMI output in supervisor mode.
+*/
+   arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x8000,
+ 0, 0, 0, 0, 0, &res);
+
regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
   HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h 
b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
index 209fbe1..a5cb07d 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
@@ -234,4 +234,5 @@
 #define MHL_SYNC_AUTO_EN   BIT(30)
 #define HDMI_PCLK_FREE_RUN BIT(31)

+#define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x8201
 #endif
-- 
2.7.0

[PATCH v2] drm/core: Add drm_accurate_vblank_count_and_time, v2.

[Ville Syrjälä]

On Mon, Apr 11, 2016 at 05:06:24PM +0200, Maarten Lankhorst wrote:
> Op 11-04-16 om 16:43 schreef Ville Syrjälä:
> > On Mon, Apr 11, 2016 at 11:42:57AM +0200, Maarten Lankhorst wrote:
> >> This function is useful for gen2 intel devices which have no frame
> >> counter, but need a way to determine the current vblank count without
> >> racing with the vblank interrupt handler.
> >>
> >> intel_pipe_update_start checks if no vblank interrupt will occur
> >> during vblank evasion, but cannot check whether the vblank handler has
> >> run to completion. This function uses the timestamps to determine
> >> when the last vblank has happened, and interpolates from there.
> >>
> >> Changes since v1:
> >> - Take vblank_time_lock and don't use drm_vblank_count_and_time.
> >>
> >> Cc: Mario Kleiner 
> >> Cc: Ville Syrjälä 
> >> Signed-off-by: Maarten Lankhorst 
> >> ---
> >>  drivers/gpu/drm/drm_irq.c | 31 +++
> >>  include/drm/drmP.h|  2 ++
> >>  2 files changed, 33 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
> >> index 3c1a6f18e71c..d3cecc1932e1 100644
> >> --- a/drivers/gpu/drm/drm_irq.c
> >> +++ b/drivers/gpu/drm/drm_irq.c
> >> @@ -303,6 +303,37 @@ static void drm_update_vblank_count(struct drm_device 
> >> *dev, unsigned int pipe,
> >>store_vblank(dev, pipe, diff, &t_vblank, cur_vblank);
> >>  }
> >>  
> >> +/**
> >> + * drm_accurate_vblank_count_and_time - retrieve the master vblank counter
> >> + * @crtc: which counter to retrieve
> >> + * @tv_ret: last time counter was updated
> >> + *
> >> + * This function is similar to @drm_update_vblank_count_and_time but
> >> + * this function interpolates to handle a race with vblank irq's, and
> >> + * is only useful for crtc's that have no hw vblank counter.
> >> + */
> >> +
> >> +u32 drm_accurate_vblank_count_and_time(struct drm_crtc *crtc,
> >> + struct timeval *tv_ret)
> >> +{
> >> +  struct drm_device *dev = crtc->dev;
> >> +  u32 vblank, pipe = drm_crtc_index(crtc);
> >> +  unsigned long flags;
> >> +
> >> +  WARN(dev->max_vblank_count, "This function is only useful when a hw 
> >> counter is unavailable.");
> > It's useful on everything if you actually want to trust the
> > software counter to not be stale.
> >
> >> +
> >> +  spin_lock_irqsave(&dev->vblank_time_lock, flags);
> >> +  drm_update_vblank_count(dev, pipe, 0);
> >> +
> >> +  vblank = dev->vblank[pipe].count;
> >> +  *tv_ret = vblanktimestamp(dev, pipe, vblank);
> > Do we have a user in mind that would care about the timestamp?
> >
> No, I guess allowing a NULL pointer for tv_ret might help.

Or just killing the entire parameter.

-- 
Ville Syrjälä
Intel OTC

[Bug 94891] BUG: unable to handle kernel NULL pointer dereference

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=94891

Alex Deucher  changed:

   What|Removed |Added

   Assignee|xorg-driver-ati at lists.x.org |dri-devel at 
lists.freedesktop
   ||.org
Version|7.7 (2012.06)   |unspecified
Product|xorg|DRI
 QA Contact|xorg-team at lists.x.org   |
  Component|Driver/Radeon   |DRM/Radeon

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[PATCH RFC 00/11] drm/tilcdc: Atomic modeset support

[Jyri Sarha]

The LCDC in its simplicity does not fit too well into DRM atomic
modeset abstractions. I wonder if I am doing the right thing in
implementing the dummy primary plane and in implementing
mode_set_nofb() crtc helper when the crtc actually needs the
framebuffer to be there when configuring it. See individual patch
descriptions for details. There is still lot of room for cleaning up
but I would first like to know if I am moving at all to the right
direction.

Jyri Sarha (11):
  drm/tilcdc: Make tilcdc_crtc_page_flip() public
  drm/tilcdc: Add dummy primary plane implementation
  drm/tilcdc: Initialize dummy primary plane from crtc init
  drm/tilcdc: Add tilcdc_crtc_mode_set_nofb()
  drm/tilcdc: Add tilcdc_crtc_atomic_check()
  drm/tilcdc: Add atomic mode config funcs
  drm/tilcdc: Add drm_mode_config_reset() call to tilcdc_load()
  drm/tilcdc: Call drm_crtc_vblank_off() in tilcdc_crtc_destroy()
  drm/tilcdc: Set DRIVER_ATOMIC and use atomic crtc helpers
  drm/tilcdc: Remove obsolete crtc helper functions
  drm/tilcdc: Remove tilcdc_verify_fb()

 drivers/gpu/drm/tilcdc/Makefile   |   1 +
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c  | 142 +++---
 drivers/gpu/drm/tilcdc/tilcdc_drv.c   |  52 -
 drivers/gpu/drm/tilcdc/tilcdc_drv.h   |   6 ++
 drivers/gpu/drm/tilcdc/tilcdc_plane.c | 122 +
 5 files changed, 244 insertions(+), 79 deletions(-)
 create mode 100644 drivers/gpu/drm/tilcdc/tilcdc_plane.c

-- 
1.9.1

[PATCH RFC 01/11] drm/tilcdc: Make tilcdc_crtc_page_flip() public

[Jyri Sarha]

Make tilcdc_crtc_page_flip() public for dummy plane implementation to use.

Signed-off-by: Jyri Sarha 
---
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 2 +-
 drivers/gpu/drm/tilcdc/tilcdc_drv.h  | 4 
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c 
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 6dce763..78466ed 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -184,7 +184,7 @@ static int tilcdc_verify_fb(struct drm_crtc *crtc, struct 
drm_framebuffer *fb)
return 0;
 }

-static int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
+int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
struct drm_pending_vblank_event *event,
uint32_t page_flip_flags)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.h 
b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
index c1de18b..8707ae6 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
@@ -172,5 +172,9 @@ void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc 
*crtc,
 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode 
*mode);
 int tilcdc_crtc_max_width(struct drm_crtc *crtc);
 void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode);
+int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
+   struct drm_framebuffer *fb,
+   struct drm_pending_vblank_event *event,
+   uint32_t page_flip_flags);

 #endif /* __TILCDC_DRV_H__ */
-- 
1.9.1

[PATCH RFC 02/11] drm/tilcdc: Add dummy primary plane implementation

[Jyri Sarha]

Add dummy primary plane implementation. LCDC does not really have
planes, only simple framebuffer that is mandatory. This primary plane
implementation has the necessary checks for implementing simple
framebuffer trough DRM plane abstraction. For setting the actual
framebuffer the implementation relies on a CRTC side function.

Signed-off-by: Jyri Sarha 
---
 drivers/gpu/drm/tilcdc/Makefile   |   1 +
 drivers/gpu/drm/tilcdc/tilcdc_drv.h   |   2 +
 drivers/gpu/drm/tilcdc/tilcdc_plane.c | 122 ++
 3 files changed, 125 insertions(+)
 create mode 100644 drivers/gpu/drm/tilcdc/tilcdc_plane.c

diff --git a/drivers/gpu/drm/tilcdc/Makefile b/drivers/gpu/drm/tilcdc/Makefile
index deeca48..6f67517 100644
--- a/drivers/gpu/drm/tilcdc/Makefile
+++ b/drivers/gpu/drm/tilcdc/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_DRM_TILCDC_SLAVE_COMPAT) += tilcdc_slave_compat.o \
 tilcdc_slave_compat.dtb.o

 tilcdc-y := \
+   tilcdc_plane.o \
tilcdc_crtc.o \
tilcdc_tfp410.o \
tilcdc_panel.o \
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.h 
b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
index 8707ae6..725d0b6 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
@@ -177,4 +177,6 @@ int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
struct drm_pending_vblank_event *event,
uint32_t page_flip_flags);

+int tilcdc_plane_init(struct drm_device *dev, struct drm_plane *plane);
+
 #endif /* __TILCDC_DRV_H__ */
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_plane.c 
b/drivers/gpu/drm/tilcdc/tilcdc_plane.c
new file mode 100644
index 000..c5d069e
--- /dev/null
+++ b/drivers/gpu/drm/tilcdc/tilcdc_plane.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2015 Texas Instruments
+ * Author: Jyri Sarha 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "tilcdc_drv.h"
+
+static const u32 tilcdc_formats[] = { DRM_FORMAT_RGB565,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_XRGB };
+
+static struct drm_plane_funcs tilcdc_plane_funcs = {
+   .update_plane   = drm_atomic_helper_update_plane,
+   .disable_plane  = drm_atomic_helper_disable_plane,
+   .destroy= drm_plane_cleanup,
+   .set_property   = drm_atomic_helper_plane_set_property,
+   .reset  = drm_atomic_helper_plane_reset,
+   .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
+   .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
+};
+
+static int tilcdc_plane_atomic_check(struct drm_plane *plane,
+struct drm_plane_state *state)
+{
+   unsigned int depth, bpp;
+   struct drm_crtc_state *crtc_state;
+
+   if (!state->crtc)
+   return 0;
+
+   if (WARN_ON(!state->fb))
+   return -EINVAL;
+
+   if (state->crtc_x || state->crtc_y) {
+   dev_err(plane->dev->dev, "%s: crtc position must be zero.",
+   __func__);
+   return -EINVAL;
+   }
+
+   crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
+   if (IS_ERR(crtc_state))
+   return PTR_ERR(crtc_state);
+
+   if (crtc_state->mode.hdisplay != state->crtc_w ||
+   crtc_state->mode.vdisplay != state->crtc_h) {
+   dev_err(plane->dev->dev,
+   "%s: Size must match mode (%dx%d == %dx%d)", __func__,
+   crtc_state->mode.hdisplay, crtc_state->mode.vdisplay,
+   state->crtc_w, state->crtc_h);
+   return -EINVAL;
+   }
+
+   drm_fb_get_bpp_depth(state->fb->pixel_format, &depth, &bpp);
+   if (state->fb->pitches[0] != crtc_state->mode.hdisplay * bpp / 8) {
+   dev_err(plane->dev->dev,
+   "Invalid pitch: fb and crtc widths must be the same");
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
+static void tilcdc_plane_atomic_update(struct drm_plane *plane,
+  struct drm_plane_state *old_state)
+{
+   struct drm_plane_state *state = plane->state;
+
+   if (!state->crtc)
+   return;
+
+   if (WARN_ON(!state->fb || !state->crtc->state))
+   return;
+
+   tilcdc_crtc_page_flip(state->crtc,

[PATCH RFC 03/11] drm/tilcdc: Initialize dummy plane from crtc init

[Jyri Sarha]

Signed-off-by: Jyri Sarha 
---
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c 
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 78466ed..6b39be7 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -26,6 +26,7 @@
 struct tilcdc_crtc {
struct drm_crtc base;

+   struct drm_plane primary;
const struct tilcdc_panel_info *info;
struct drm_pending_vblank_event *event;
int dpms;
@@ -162,7 +163,6 @@ static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);

tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
-
of_node_put(crtc->port);
drm_crtc_cleanup(crtc);
drm_flip_work_cleanup(&tilcdc_crtc->unref_work);
@@ -793,6 +793,10 @@ struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)

crtc = &tilcdc_crtc->base;

+   ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary);
+   if (ret < 0)
+   goto fail;
+
tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF;
init_waitqueue_head(&tilcdc_crtc->frame_done_wq);

@@ -802,7 +806,11 @@ struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
spin_lock_init(&tilcdc_crtc->irq_lock);
INIT_WORK(&tilcdc_crtc->recover_work, tilcdc_crtc_recover_work);

-   ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs);
+   ret = drm_crtc_init_with_planes(dev, crtc,
+   &tilcdc_crtc->primary,
+   NULL,
+   &tilcdc_crtc_funcs,
+   "tilcdc crtc");
if (ret < 0)
goto fail;

-- 
1.9.1

[PATCH RFC 03/11] drm/tilcdc: Initialize dummy primary plane from crtc init

[Jyri Sarha]

Initialize dummy primary plane from crtc init.

Signed-off-by: Jyri Sarha 
---
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c 
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 78466ed..919c901 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -26,6 +26,7 @@
 struct tilcdc_crtc {
struct drm_crtc base;

+   struct drm_plane primary;
const struct tilcdc_panel_info *info;
struct drm_pending_vblank_event *event;
int dpms;
@@ -793,6 +794,10 @@ struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)

crtc = &tilcdc_crtc->base;

+   ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary);
+   if (ret < 0)
+   goto fail;
+
tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF;
init_waitqueue_head(&tilcdc_crtc->frame_done_wq);

@@ -802,7 +807,11 @@ struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
spin_lock_init(&tilcdc_crtc->irq_lock);
INIT_WORK(&tilcdc_crtc->recover_work, tilcdc_crtc_recover_work);

-   ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs);
+   ret = drm_crtc_init_with_planes(dev, crtc,
+   &tilcdc_crtc->primary,
+   NULL,
+   &tilcdc_crtc_funcs,
+   "tilcdc crtc");
if (ret < 0)
goto fail;

-- 
1.9.1

[PATCH RFC 04/11] drm/tilcdc: Add tilcdc_crtc_mode_set_nofb()

[Jyri Sarha]

Add tilcdc_crtc_mode_set_nofb(). The mode_set_nofb() semantics do not
fit well to LCDC, because of the mandatory framebuffer. However, when
the primary plane is required in the check phase, it and the
framebuffer can be found from the atomic state struct.

Signed-off-by: Jyri Sarha 
---
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 172 +++
 1 file changed, 172 insertions(+)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c 
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 919c901..35f5682 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -310,6 +310,177 @@ static void tilcdc_crtc_commit(struct drm_crtc *crtc)
tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 }

+static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
+{
+   struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
+   struct drm_device *dev = crtc->dev;
+   struct tilcdc_drm_private *priv = dev->dev_private;
+   const struct tilcdc_panel_info *info = tilcdc_crtc->info;
+   uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
+   struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+   struct drm_framebuffer *fb = crtc->primary->state->fb;
+
+   if (WARN_ON(!info))
+   return;
+
+   if (WARN_ON(!fb))
+   return;
+
+   pm_runtime_get_sync(dev->dev);
+
+   /* Configure the Burst Size and fifo threshold of DMA: */
+   reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x0770;
+   switch (info->dma_burst_sz) {
+   case 1:
+   reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
+   break;
+   case 2:
+   reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
+   break;
+   case 4:
+   reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
+   break;
+   case 8:
+   reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
+   break;
+   case 16:
+   reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
+   break;
+   default:
+   dev_err(dev->dev, "invalid burst size\n");
+   return;
+   }
+   reg |= (info->fifo_th << 8);
+   tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
+
+   /* Configure timings: */
+   hbp = mode->htotal - mode->hsync_end;
+   hfp = mode->hsync_start - mode->hdisplay;
+   hsw = mode->hsync_end - mode->hsync_start;
+   vbp = mode->vtotal - mode->vsync_end;
+   vfp = mode->vsync_start - mode->vdisplay;
+   vsw = mode->vsync_end - mode->vsync_start;
+
+   DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
+   mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
+
+   /* Set AC Bias Period and Number of Transitions per Interrupt: */
+   reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
+   reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
+   LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
+
+   /*
+* subtract one from hfp, hbp, hsw because the hardware uses
+* a value of 0 as 1
+*/
+   if (priv->rev == 2) {
+   /* clear bits we're going to set */
+   reg &= ~0x7833;
+   reg |= ((hfp-1) & 0x300) >> 8;
+   reg |= ((hbp-1) & 0x300) >> 4;
+   reg |= ((hsw-1) & 0x3c0) << 21;
+   }
+   tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
+
+   reg = (((mode->hdisplay >> 4) - 1) << 4) |
+   (((hbp-1) & 0xff) << 24) |
+   (((hfp-1) & 0xff) << 16) |
+   (((hsw-1) & 0x3f) << 10);
+   if (priv->rev == 2)
+   reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
+   tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
+
+   reg = ((mode->vdisplay - 1) & 0x3ff) |
+   ((vbp & 0xff) << 24) |
+   ((vfp & 0xff) << 16) |
+   (((vsw-1) & 0x3f) << 10);
+   tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
+
+   /*
+* be sure to set Bit 10 for the V2 LCDC controller,
+* otherwise limited to 1024 pixels width, stopping
+* 1920x1080 being supported.
+*/
+   if (priv->rev == 2) {
+   if ((mode->vdisplay - 1) & 0x400) {
+   tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
+   LCDC_LPP_B10);
+   } else {
+   tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
+   LCDC_LPP_B10);
+   }
+   }
+
+   /* Configure display type: */
+   reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
+   ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
+ LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK |
+ 0x000ff000 /* Palette Loading Delay bits */);
+   reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
+   if (info->tft_alt_mode)
+   reg |= LCDC_TFT_ALT_ENA

[PATCH RFC 05/11] drm/tilcdc: Add tilcdc_crtc_atomic_check()

[Jyri Sarha]

Add tilcdc_crtc_atomic_check(). Checks the display mode validity and
the presence of the mandatory primary plane.

Signed-off-by: Jyri Sarha 
---
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 29 +
 1 file changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c 
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 35f5682..2ac9d41 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -481,6 +481,34 @@ static void tilcdc_crtc_mode_set_nofb(struct drm_crtc 
*crtc)
crtc->hwmode = crtc->state->adjusted_mode;
 }

+static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc,
+   struct drm_crtc_state *state)
+{
+   struct drm_display_mode *mode = &state->mode;
+   struct drm_display_mode *adjusted_mode = &state->adjusted_mode;
+   int ret;
+
+   if (state->state->plane_states[0]->crtc != crtc ||
+   state->state->planes[0] != crtc->primary) {
+   dev_dbg(crtc->dev->dev, "CRTC primary plane must be present");
+   return -EINVAL;
+   }
+
+   ret = tilcdc_crtc_mode_valid(crtc, mode);
+   if (ret) {
+   dev_dbg(crtc->dev->dev, "Mode \"%s\" not valid", mode->name);
+   return -EINVAL;
+   }
+
+   if (!tilcdc_crtc_mode_fixup(crtc, mode, adjusted_mode)) {
+   dev_dbg(crtc->dev->dev, "Mode fixup for \"%s\" failed",
+   mode->name);
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
 static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode,
@@ -697,6 +725,7 @@ static const struct drm_crtc_helper_funcs 
tilcdc_crtc_helper_funcs = {
.commit = tilcdc_crtc_commit,
.mode_set   = tilcdc_crtc_mode_set,
.mode_set_base  = tilcdc_crtc_mode_set_base,
+   .atomic_check   = tilcdc_crtc_atomic_check,
.mode_set_nofb  = tilcdc_crtc_mode_set_nofb,
 };

-- 
1.9.1

[PATCH RFC 06/11] drm/tilcdc: Add atomic mode config funcs

[Jyri Sarha]

Add atomic mode config funcs. The atomic_commit implementation is a
copy-paste from drm_atomic_helper_commit(), leaving out the async
test. The similar copy-paste implementation appears to be used in many
other drivers too. The standard drm_atomic_helper_check() is used for
checking.

Signed-off-by: Jyri Sarha 
---
 drivers/gpu/drm/tilcdc/tilcdc_drv.c | 47 +
 1 file changed, 47 insertions(+)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c 
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index 709bc90..66a283e 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -20,6 +20,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 

 #include "tilcdc_drv.h"
 #include "tilcdc_regs.h"
@@ -59,9 +61,54 @@ static void tilcdc_fb_output_poll_changed(struct drm_device 
*dev)
drm_fbdev_cma_hotplug_event(priv->fbdev);
 }

+static int tilcdc_commit(struct drm_device *dev,
+ struct drm_atomic_state *state,
+ bool async)
+{
+   int ret;
+
+   ret = drm_atomic_helper_prepare_planes(dev, state);
+   if (ret)
+   return ret;
+
+   drm_atomic_helper_swap_state(dev, state);
+
+   /*
+* Everything below can be run asynchronously without the need to grab
+* any modeset locks at all under one condition: It must be guaranteed
+* that the asynchronous work has either been cancelled (if the driver
+* supports it, which at least requires that the framebuffers get
+* cleaned up with drm_atomic_helper_cleanup_planes()) or completed
+* before the new state gets committed on the software side with
+* drm_atomic_helper_swap_state().
+*
+* This scheme allows new atomic state updates to be prepared and
+* checked in parallel to the asynchronous completion of the previous
+* update. Which is important since compositors need to figure out the
+* composition of the next frame right after having submitted the
+* current layout.
+*/
+
+   drm_atomic_helper_commit_modeset_disables(dev, state);
+
+   drm_atomic_helper_commit_planes(dev, state, false);
+
+   drm_atomic_helper_commit_modeset_enables(dev, state);
+
+   drm_atomic_helper_wait_for_vblanks(dev, state);
+
+   drm_atomic_helper_cleanup_planes(dev, state);
+
+   drm_atomic_state_free(state);
+
+   return 0;
+}
+
 static const struct drm_mode_config_funcs mode_config_funcs = {
.fb_create = tilcdc_fb_create,
.output_poll_changed = tilcdc_fb_output_poll_changed,
+   .atomic_check = drm_atomic_helper_check,
+   .atomic_commit = tilcdc_commit,
 };

 static int modeset_init(struct drm_device *dev)
-- 
1.9.1

[PATCH RFC 07/11] drm/tilcdc: Add drm_mode_config_reset() call to tilcdc_load()

[Jyri Sarha]

Add drm_mode_config_reset() call to tilcdc_load(). This is need to
initialize atomic state variables at load time.

Signed-off-by: Jyri Sarha 
---
 drivers/gpu/drm/tilcdc/tilcdc_drv.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c 
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index 66a283e..dc0d1e9 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -342,6 +342,9 @@ static int tilcdc_load(struct drm_device *dev, unsigned 
long flags)
}

drm_helper_disable_unused_functions(dev);
+
+   drm_mode_config_reset(dev);
+
priv->fbdev = drm_fbdev_cma_init(dev, bpp,
dev->mode_config.num_crtc,
dev->mode_config.num_connector);
-- 
1.9.1

[PATCH RFC 08/11] drm/tilcdc: Call drm_crtc_vblank_off() in tilcdc_crtc_destroy()

[Jyri Sarha]

Call drm_crtc_vblank_off() in tilcdc_crtc_destroy(). This is needed
for module unloading after the DRIVER_ATOMIC is enabled.

Signed-off-by: Jyri Sarha 
---
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c 
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 2ac9d41..69045d8 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -163,7 +163,7 @@ static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);

tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
-
+   drm_crtc_vblank_off(crtc);
of_node_put(crtc->port);
drm_crtc_cleanup(crtc);
drm_flip_work_cleanup(&tilcdc_crtc->unref_work);
-- 
1.9.1

[PATCH RFC 09/11] drm/tilcdc: Set DRIVER_ATOMIC and use atomic crtc helpers

[Jyri Sarha]

Set DRIVER_ATOMIC and use atomic helpers and rename commit and prepare
crtc helpers to enable and disable. This makes the final jump to mode
setting, but there is lot of obsolete code to clean up.

Signed-off-by: Jyri Sarha 
---
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 16 +++-
 drivers/gpu/drm/tilcdc/tilcdc_drv.c  |  2 +-
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c 
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 69045d8..e8e309e 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -17,6 +17,7 @@

 #include "drm_flip_work.h"
 #include 
+#include 

 #include "tilcdc_drv.h"
 #include "tilcdc_regs.h"
@@ -300,12 +301,12 @@ static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
return true;
 }

-static void tilcdc_crtc_prepare(struct drm_crtc *crtc)
+static void tilcdc_crtc_disable(struct drm_crtc *crtc)
 {
tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 }

-static void tilcdc_crtc_commit(struct drm_crtc *crtc)
+static void tilcdc_crtc_enable(struct drm_crtc *crtc)
 {
tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 }
@@ -713,9 +714,12 @@ static int tilcdc_crtc_mode_set_base(struct drm_crtc 
*crtc, int x, int y,
 }

 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
-   .destroy= tilcdc_crtc_destroy,
-   .set_config = drm_crtc_helper_set_config,
-   .page_flip  = tilcdc_crtc_page_flip,
+   .destroy= tilcdc_crtc_destroy,
+   .set_config = drm_atomic_helper_set_config,
+   .page_flip  = drm_atomic_helper_page_flip,
+   .reset  = drm_atomic_helper_crtc_reset,
+   .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
+   .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 };

 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
@@ -725,6 +729,8 @@ static const struct drm_crtc_helper_funcs 
tilcdc_crtc_helper_funcs = {
.commit = tilcdc_crtc_commit,
.mode_set   = tilcdc_crtc_mode_set,
.mode_set_base  = tilcdc_crtc_mode_set_base,
+   .enable = tilcdc_crtc_enable,
+   .disable= tilcdc_crtc_disable,
.atomic_check   = tilcdc_crtc_atomic_check,
.mode_set_nofb  = tilcdc_crtc_mode_set_nofb,
 };
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c 
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index dc0d1e9..6569d3a 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -587,7 +587,7 @@ static const struct file_operations fops = {

 static struct drm_driver tilcdc_driver = {
.driver_features= (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET |
-  DRIVER_PRIME),
+  DRIVER_PRIME | DRIVER_ATOMIC),
.load   = tilcdc_load,
.unload = tilcdc_unload,
.lastclose  = tilcdc_lastclose,
-- 
1.9.1

[PATCH RFC 10/11] drm/tilcdc: Remove obsolete crtc helper functions

[Jyri Sarha]

Remove obsolete crtc helper functions. These are not needed when
atomic modeset is used.

Signed-off-by: Jyri Sarha 
---
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 209 ---
 1 file changed, 209 deletions(-)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c 
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index e8e309e..4d019eb8 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -510,209 +510,6 @@ static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc,
return 0;
 }

-static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
-   struct drm_display_mode *mode,
-   struct drm_display_mode *adjusted_mode,
-   int x, int y,
-   struct drm_framebuffer *old_fb)
-{
-   struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
-   struct drm_device *dev = crtc->dev;
-   struct tilcdc_drm_private *priv = dev->dev_private;
-   const struct tilcdc_panel_info *info = tilcdc_crtc->info;
-   uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
-   int ret;
-
-   ret = tilcdc_crtc_mode_valid(crtc, mode);
-   if (WARN_ON(ret))
-   return ret;
-
-   if (WARN_ON(!info))
-   return -EINVAL;
-
-   ret = tilcdc_verify_fb(crtc, crtc->primary->fb);
-   if (ret)
-   return ret;
-
-   pm_runtime_get_sync(dev->dev);
-
-   /* Configure the Burst Size and fifo threshold of DMA: */
-   reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x0770;
-   switch (info->dma_burst_sz) {
-   case 1:
-   reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
-   break;
-   case 2:
-   reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
-   break;
-   case 4:
-   reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
-   break;
-   case 8:
-   reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
-   break;
-   case 16:
-   reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
-   break;
-   default:
-   return -EINVAL;
-   }
-   reg |= (info->fifo_th << 8);
-   tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
-
-   /* Configure timings: */
-   hbp = mode->htotal - mode->hsync_end;
-   hfp = mode->hsync_start - mode->hdisplay;
-   hsw = mode->hsync_end - mode->hsync_start;
-   vbp = mode->vtotal - mode->vsync_end;
-   vfp = mode->vsync_start - mode->vdisplay;
-   vsw = mode->vsync_end - mode->vsync_start;
-
-   DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
-   mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, 
vfp, vsw);
-
-   /* Configure the AC Bias Period and Number of Transitions per 
Interrupt: */
-   reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
-   reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
-   LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
-
-   /*
-* subtract one from hfp, hbp, hsw because the hardware uses
-* a value of 0 as 1
-*/
-   if (priv->rev == 2) {
-   /* clear bits we're going to set */
-   reg &= ~0x7833;
-   reg |= ((hfp-1) & 0x300) >> 8;
-   reg |= ((hbp-1) & 0x300) >> 4;
-   reg |= ((hsw-1) & 0x3c0) << 21;
-   }
-   tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
-
-   reg = (((mode->hdisplay >> 4) - 1) << 4) |
-   (((hbp-1) & 0xff) << 24) |
-   (((hfp-1) & 0xff) << 16) |
-   (((hsw-1) & 0x3f) << 10);
-   if (priv->rev == 2)
-   reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
-   tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
-
-   reg = ((mode->vdisplay - 1) & 0x3ff) |
-   ((vbp & 0xff) << 24) |
-   ((vfp & 0xff) << 16) |
-   (((vsw-1) & 0x3f) << 10);
-   tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
-
-   /*
-* be sure to set Bit 10 for the V2 LCDC controller,
-* otherwise limited to 1024 pixels width, stopping
-* 1920x1080 being suppoted.
-*/
-   if (priv->rev == 2) {
-   if ((mode->vdisplay - 1) & 0x400) {
-   tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
-   LCDC_LPP_B10);
-   } else {
-   tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
-   LCDC_LPP_B10);
-   }
-   }
-
-   /* Configure display type: */
-   reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
-   ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
-   LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 
0x000ff000);
-   reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
-   if (info->tft_alt_mode)
-   reg |= LCDC_TFT_ALT_ENABLE;
-   if (priv->rev == 2) {
-

[PATCH RFC 11/11] drm/tilcdc: Remove tilcdc_verify_fb()

[Jyri Sarha]

Remove tilcdc_verify_fb(). The tilcdc_verify_fb() function is not
needed because the same checks are implemented in
tilcdc_plane_atomic_check().

Signed-off-by: Jyri Sarha 
---
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 21 -
 1 file changed, 21 deletions(-)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c 
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 4d019eb8..e572baf 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -170,22 +170,6 @@ static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
drm_flip_work_cleanup(&tilcdc_crtc->unref_work);
 }

-static int tilcdc_verify_fb(struct drm_crtc *crtc, struct drm_framebuffer *fb)
-{
-   struct drm_device *dev = crtc->dev;
-   unsigned int depth, bpp;
-
-   drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
-
-   if (fb->pitches[0] != crtc->mode.hdisplay * bpp / 8) {
-   dev_err(dev->dev,
-   "Invalid pitch: fb and crtc widths must be the same");
-   return -EINVAL;
-   }
-
-   return 0;
-}
-
 int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
struct drm_pending_vblank_event *event,
@@ -193,15 +177,10 @@ int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
 {
struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
struct drm_device *dev = crtc->dev;
-   int r;
unsigned long flags;
s64 tdiff;
ktime_t next_vblank;

-   r = tilcdc_verify_fb(crtc, fb);
-   if (r)
-   return r;
-
if (tilcdc_crtc->event) {
dev_err(dev->dev, "already pending page flip!\n");
return -EBUSY;
-- 
1.9.1

Please ignore this (was: Re: [PATCH RFC 03/11] drm/tilcdc: Initialize dummy plane from crtc init)

[Jyri Sarha]

Please ignore this.

BR,
Jyri

On 04/11/16 19:46, Jyri Sarha wrote:
> Signed-off-by: Jyri Sarha 
> ---
>  drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 12 ++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c 
> b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
> index 78466ed..6b39be7 100644
> --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
> +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
> @@ -26,6 +26,7 @@
>  struct tilcdc_crtc {
>   struct drm_crtc base;
>  
> + struct drm_plane primary;
>   const struct tilcdc_panel_info *info;
>   struct drm_pending_vblank_event *event;
>   int dpms;
> @@ -162,7 +163,6 @@ static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
>   struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
>  
>   tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
> -
>   of_node_put(crtc->port);
>   drm_crtc_cleanup(crtc);
>   drm_flip_work_cleanup(&tilcdc_crtc->unref_work);
> @@ -793,6 +793,10 @@ struct drm_crtc *tilcdc_crtc_create(struct drm_device 
> *dev)
>  
>   crtc = &tilcdc_crtc->base;
>  
> + ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary);
> + if (ret < 0)
> + goto fail;
> +
>   tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF;
>   init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
>  
> @@ -802,7 +806,11 @@ struct drm_crtc *tilcdc_crtc_create(struct drm_device 
> *dev)
>   spin_lock_init(&tilcdc_crtc->irq_lock);
>   INIT_WORK(&tilcdc_crtc->recover_work, tilcdc_crtc_recover_work);
>  
> - ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs);
> + ret = drm_crtc_init_with_planes(dev, crtc,
> + &tilcdc_crtc->primary,
> + NULL,
> + &tilcdc_crtc_funcs,
> + "tilcdc crtc");
>   if (ret < 0)
>   goto fail;
>  
> 

[PATCH 1/6] drm/amd: Mark some tables as const

[Alex Deucher]

On Mon, Apr 11, 2016 at 3:32 AM, Christian König
 wrote:
> Am 10.04.2016 um 16:29 schrieb Nils Wallménius:
>>
>> This patch marks some compile-time constant tables 'const'.
>> The tables marked in this patch are the low hanging fruit
>> where little other changes were necesary to avoid casting
>> away constness etc. Also mark some tables that are private
>> to a file as static.
>>
>> Signed-off-by: Nils Wallménius 
>
>
> Nice cleanup, for the series Reviewed-by: Christian König
> 

Applied the series.

Thanks,

Alex

>
> Thanks,
> Christian.
>
>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  2 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_display.c  |  6 +++---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  |  2 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c  |  2 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c  |  2 +-
>>   drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 12 ++--
>>   drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h |  2 +-
>>   drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c | 10 +-
>>   drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c|  8 
>>   drivers/gpu/drm/amd/powerplay/inc/fiji_pwrvirus.h|  2 +-
>>   drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c |  2 +-
>>   drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c   |  6 +++---
>>   drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c  |  2 +-
>>   13 files changed, 29 insertions(+), 29 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 66e51f9..5d05b5d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -2348,7 +2348,7 @@ static inline void
>> amdgpu_unregister_atpx_handler(void) {}
>>* KMS
>>*/
>>   extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
>> -extern int amdgpu_max_kms_ioctl;
>> +extern const int amdgpu_max_kms_ioctl;
>> int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long
>> flags);
>>   int amdgpu_driver_unload_kms(struct drm_device *dev);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> index 0535095..c835abe 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> @@ -596,20 +596,20 @@ const struct drm_mode_config_funcs amdgpu_mode_funcs
>> = {
>> .output_poll_changed = amdgpu_output_poll_changed
>>   };
>>   -static struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
>> +static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
>>   { { UNDERSCAN_OFF, "off" },
>> { UNDERSCAN_ON, "on" },
>> { UNDERSCAN_AUTO, "auto" },
>>   };
>>   -static struct drm_prop_enum_list amdgpu_audio_enum_list[] =
>> +static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
>>   { { AMDGPU_AUDIO_DISABLE, "off" },
>> { AMDGPU_AUDIO_ENABLE, "on" },
>> { AMDGPU_AUDIO_AUTO, "auto" },
>>   };
>> /* XXX support different dither options? spatial, temporal, both, etc.
>> */
>> -static struct drm_prop_enum_list amdgpu_dither_enum_list[] =
>> +static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
>>   { { AMDGPU_FMT_DITHER_DISABLE, "off" },
>> { AMDGPU_FMT_DITHER_ENABLE, "on" },
>>   };
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> index f1e17d6..2d9dbc2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> @@ -166,7 +166,7 @@ module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap,
>> uint, 0444);
>>   MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect
>> (default))");
>>   module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
>>   -static struct pci_device_id pciidlist[] = {
>> +static const struct pci_device_id pciidlist[] = {
>>   #ifdef CONFIG_DRM_AMDGPU_CIK
>> /* Kaveri */
>> {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
>> CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> index 762cfdb..9266c7b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> @@ -498,7 +498,7 @@ static int amdgpu_irqdomain_map(struct irq_domain *d,
>> return 0;
>>   }
>>   -static struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
>> +static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
>> .map = amdgpu_irqdomain_map,
>>   };
>>   diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> index 7805a87..1f9d318 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> @@ -754,4 +754,4 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
>> DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, am

[PATCH] drm: atomic: fix legacy gamma set helper

[Bob Paauwe]

On Mon, 11 Apr 2016 14:43:39 +0100
Lionel Landwerlin  wrote:

> Color management properties are a bit of an odd use case because
> they're not marked as atomic properties. Currently we're not updating
> the non atomic values so the drm_crtc_state is out of sync with the
> values stored in the crtc object.
> 
> v2: Update non atomic values only if commit succeeds (Bob Paauwe)
> 
> v3: Do not access crtc_state after commit, use crtc->state (Maarten
> Lankhorst)
> 

Reviewed-by: Bob Paauwe 
Tested-by; Bob Paauwe 

> Cc: Maarten Lankhorst 
> Cc: Bob Paauwe 
> Cc: 
> Signed-off-by: Lionel Landwerlin 
> ---
>  drivers/gpu/drm/drm_atomic_helper.c | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
> b/drivers/gpu/drm/drm_atomic_helper.c
> index 7bf678e..13b86cf 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -2979,6 +2979,14 @@ retry:
>   if (ret)
>   goto fail;
>  
> + drm_object_property_set_value(&crtc->base,
> + config->degamma_lut_property, 0);
> + drm_object_property_set_value(&crtc->base,
> + config->ctm_property, 0);
> + drm_object_property_set_value(&crtc->base,
> + config->gamma_lut_property,
> + crtc->state->gamma_lut->base.id);
> +
>   /* Driver takes ownership of state on successful commit. */
>  
>   drm_property_unreference_blob(blob);



-- 
--
Bob Paauwe  
Bob.J.Paauwe at intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193

[Bug 116101] "RIP radeon_gem_va_ioctl+0x35/0x650", "Userspace still has active objects", and "trying to unbind memory from uninitialized GART !" when unbinding from radeon

[bugzilla-dae...@bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=116101

--- Comment #4 from Christian König  ---
It doesn't matter what OpenGL driver you currently use for the desktop. The
hardware is in use by something so unbinding can't work correctly.

Try "sudo lsof /dev/dri/card1" (or whatever number your Radeon card is) to
figure out which process it is using.

Might be that X has opened for prime support or something without your
knowledge.

Another possibility is that a framebuffer device is still bound to it.

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[alsa-devel] [PATCH 2/5 v4] drm/i2c/adv7511: Add audio support

[Lars-Peter Clausen]

On 04/11/2016 04:08 PM, Jose Abreu wrote:
[...]
>> Currently there is also zero support of of-graph in ASoC, so a bit of work
>> is required to get this integrated properly.
>>
> 
> I also believe this would be the better option but in the meantime can't I
> integrate the audio like it is being done in the dw-hdmi driver[1]? In this
> driver the audio is registered as a sound card and is conditionally built 
> using
> Kconfig, just like I was doing in the previous versions. I know you said the
> HDMI audio is still an open issue but it seems that for this case it was 
> accepted.
> 
> [1] 
> http://lxr.free-electrons.com/source/drivers/gpu/drm/bridge/dw-hdmi-ahb-audio.c

Maybe, but I'm not sure it would work in this case. Resources are probably
better invested in working towards a proper solution.

[RESEND] fence: add missing descriptions for fence

[Gustavo Padovan]

Hi Luis,

2016-04-11 Luis de Bethencourt :

> The members child_list and active_list were added to the fence struct
> without descriptions for the Documentation. Adding these.
> 
> Fixes: b55b54b5db33 ("staging/android: remove struct sync_pt")
> Signed-off-by: Luis de Bethencourt 
> Reviewed-by: Javier Martinez Canillas 
> ---
> Hi,
> 
> Just resending this patch since it hasn't had any reviews in since
> March 21st.
> 
> Thanks,
> Luis
> 
>  include/linux/fence.h | 2 ++
>  1 file changed, 2 insertions(+)

Reviewed-by: Gustavo Padovan 

Gustavo

[Bug 94900] Regression: HD6950 GPU lockup with octodad: dadliest catch

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=94900

Bug ID: 94900
   Summary: Regression: HD6950 GPU lockup with octodad: dadliest
catch
   Product: DRI
   Version: unspecified
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: DRM/Radeon
  Assignee: dri-devel at lists.freedesktop.org
  Reporter: dan.g.tob at gmail.com

Created attachment 122873
  --> https://bugs.freedesktop.org/attachment.cgi?id=122873&action=edit
dmesg

I Am seeing gpu lockups trying to launch octodad: dadliest catch with a radeon
HD6950 on steam. It was working before but its been a few months since I've
last tried to launch it. Both mesa and kernel have been updated since it was
last working.
kernel 4.4->4.5  mesa 11.1->11.2. Possibly libdrm updates too.

[  267.335354] radeon :02:00.0: ring 0 stalled for more than 10416msec
[  267.335364] radeon :02:00.0: GPU lockup (current fence id
0x821e last fence id 0x8229 on ring 0)
[  267.444949] radeon :02:00.0: Saved 335 dwords of commands on ring 0.
[  267.445029] radeon :02:00.0: GPU softreset: 0x0009
[  267.445031] radeon :02:00.0:   GRBM_STATUS   = 0xE77E4828
[  267.445032] radeon :02:00.0:   GRBM_STATUS_SE0   = 0xFF81
[  267.445033] radeon :02:00.0:   GRBM_STATUS_SE1   = 0xFF81
[  267.445034] radeon :02:00.0:   SRBM_STATUS   = 0x20C0
[  267.445101] radeon :02:00.0:   SRBM_STATUS2  = 0x
[  267.445102] radeon :02:00.0:   R_008674_CP_STALLED_STAT1 = 0x
[  267.445103] radeon :02:00.0:   R_008678_CP_STALLED_STAT2 = 0x00018000
[  267.445104] radeon :02:00.0:   R_00867C_CP_BUSY_STAT = 0x8006
[  267.445106] radeon :02:00.0:   R_008680_CP_STAT  = 0x80038647
[  267.445107] radeon :02:00.0:   R_00D034_DMA_STATUS_REG   = 0x44C83D57
[  267.445108] radeon :02:00.0:   R_00D834_DMA_STATUS_REG   = 0x44C83D57
[  267.445109] radeon :02:00.0:   VM_CONTEXT0_PROTECTION_FAULT_ADDR  
0x
[  267.445111] radeon :02:00.0:   VM_CONTEXT0_PROTECTION_FAULT_STATUS
0x
[  267.445112] radeon :02:00.0:   VM_CONTEXT1_PROTECTION_FAULT_ADDR  
0x
[  267.445113] radeon :02:00.0:   VM_CONTEXT1_PROTECTION_FAULT_STATUS
0x
[  267.461656] radeon :02:00.0: GRBM_SOFT_RESET=0xDF7B
[  267.461709] radeon :02:00.0: SRBM_SOFT_RESET=0x0100
[  267.462863] radeon :02:00.0:   GRBM_STATUS   = 0x3828
[  267.462864] radeon :02:00.0:   GRBM_STATUS_SE0   = 0x0007
[  267.462866] radeon :02:00.0:   GRBM_STATUS_SE1   = 0x0007
[  267.462867] radeon :02:00.0:   SRBM_STATUS   = 0x20C0
[  267.462933] radeon :02:00.0:   SRBM_STATUS2  = 0x
[  267.462934] radeon :02:00.0:   R_008674_CP_STALLED_STAT1 = 0x
[  267.462935] radeon :02:00.0:   R_008678_CP_STALLED_STAT2 = 0x
[  267.462937] radeon :02:00.0:   R_00867C_CP_BUSY_STAT = 0x
[  267.462938] radeon :02:00.0:   R_008680_CP_STAT  = 0x
[  267.462939] radeon :02:00.0:   R_00D034_DMA_STATUS_REG   = 0x44C83D57
[  267.462940] radeon :02:00.0:   R_00D834_DMA_STATUS_REG   = 0x44C83D57
[  267.463016] radeon :02:00.0: GPU reset succeeded, trying to resume

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[RESEND] fence: add missing descriptions for fence

[Luis de Bethencourt]

On 11/04/16 21:09, Gustavo Padovan wrote:
> Hi Luis,
> 
> 2016-04-11 Luis de Bethencourt :
> 
>> The members child_list and active_list were added to the fence struct
>> without descriptions for the Documentation. Adding these.
>>
>> Fixes: b55b54b5db33 ("staging/android: remove struct sync_pt")
>> Signed-off-by: Luis de Bethencourt 
>> Reviewed-by: Javier Martinez Canillas 
>> ---
>> Hi,
>>
>> Just resending this patch since it hasn't had any reviews in since
>> March 21st.
>>
>> Thanks,
>> Luis
>>
>>  include/linux/fence.h | 2 ++
>>  1 file changed, 2 insertions(+)
> 
> Reviewed-by: Gustavo Padovan 
> 
>   Gustavo
> 

Thank you Gustavo.

Nice seeing you around here :)

Luis

[Bug 94900] HD6950 GPU lockup with octodad: dadliest catch

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=94900

Daniel T.  changed:

   What|Removed |Added

Summary|Regression: HD6950 GPU  |HD6950 GPU lockup with
   |lockup with octodad:|octodad: dadliest catch
   |dadliest catch  |

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[Bug 94900] HD6950 GPU lockup with octodad: dadliest catch

[bugzilla-dae...@freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=94900

--- Comment #1 from Daniel T.  ---
I don't think this is actually a regression. It's likely I was using the
onboard intel graphics last I ran this game

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[PATCH] drm/msm/mdp: Add support for more RGBX formats

[Rob Herring]

Android needs XBGR format. Add all the missing 32-bpp formats
without alpha for completeness.

Cc: Archit Taneja 
Cc: Rob Clark 
Signed-off-by: Rob Herring 
---
 drivers/gpu/drm/msm/mdp/mdp_format.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/msm/mdp/mdp_format.c 
b/drivers/gpu/drm/msm/mdp/mdp_format.c
index 1c2caff..b4a8aa4 100644
--- a/drivers/gpu/drm/msm/mdp/mdp_format.c
+++ b/drivers/gpu/drm/msm/mdp/mdp_format.c
@@ -105,6 +105,12 @@ static const struct mdp_format formats[] = {
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(XRGB, 8, 8, 8, 8,  1, 0, 2, 3,  false,  true,  4,  4,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
+   FMT(XBGR, 8, 8, 8, 8,  2, 0, 1, 3,  false,   true,  4,  4,
+   MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
+   FMT(RGBX, 8, 8, 8, 8,  3, 1, 0, 2,  false,   true,  4,  4,
+   MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
+   FMT(BGRX, 8, 8, 8, 8,  3, 2, 0, 1,  false,   true,  4,  4,
+   MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(RGB888,   0, 8, 8, 8,  1, 0, 2, 0,  false,  true,  3,  3,
MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
FMT(BGR888,   0, 8, 8, 8,  2, 0, 1, 0,  false,  true,  3,  3,
-- 
2.5.0

[alsa-devel] [PATCH 2/5 v4] drm/i2c/adv7511: Add audio support

[Jose Abreu]

Hi Lars,


On 11-04-2016 13:23, Lars-Peter Clausen wrote:
> On 04/11/2016 01:32 PM, Jose Abreu wrote:
>> Hi Lars,
>>
>>
>> On 11-04-2016 10:33, Lars-Peter Clausen wrote:
>>> On 04/11/2016 11:27 AM, Jose Abreu wrote:
 Hi Lars,


 On 09-04-2016 16:02, Lars-Peter Clausen wrote:
> On 04/08/2016 06:12 PM, Jose Abreu wrote:
> [...]
>>> [...]
 +- adi,enable-audio: If set the ADV7511 driver will register a codec 
 interface
 +  into ALSA SoC.
>>> This is not a description of the hardware.
>> Is this okay: "adi,enable-audio: Set this boolean parameter if ADV7511
>> transmitter routes audio signals" ?
> I don't think we need this property. There is no problem with registering
> the audio part unconditionally. As long as there is no connection we wont
> create a sound card that is exposed to userspace.
>
 This change was suggested by Laurent Pinchart and was introduced in v3. 
 Quoting
 Laurent:
 "The idea is that enabling support for ADV7511 audio in the kernel isn't 
 coupled
 with whether the system includes audio support. It would be confusing, and 
 would
 also waste resources, to create a Linux sound device when no sound channel 
 is
 routed on the board."
>>> I wouldn't care too much about this at this point, the extra amount of
>>> resources required for registering the CODEC (but not the sound card) is
>>> just a few bytes (sizeof(struct snd_soc_codec)).
>>>
>>> Nevertheless what we should do is describe the hardware and from this
>>> information infer whether there is a audio connection or not and if there is
>>> none we might skip registering the CODEC. In my opinion this hardware
>>> description should be modeled using of-graph, having a connection between
>>> the SoC side and the adv7511 SPDIF or I2S port.
>>>
>> You mean something like this:
>>
>> sound_playback: sound_playback {
>> compatible = "simple-audio-card";
>> [...]
>> simple-audio-card,format = "i2s";
>> [...]
>> }
>>
>> adv7511 at xx {
>> compatible = "adi,adv7511";
>> [...]
>>
>> ports {
>> [...]
>> /* Audio Output */
>> port at x {
>> reg = ;
>> endpoint {
>> remote-endpoint = <&sound_playback>;
>> }
>> }
>> }
>> }
> Yes, something like that. Not exactly like that, but similar. One of the
> core concepts of of-graph is that there is always a description of the
> connection from both sides, this way each side can independently figure out
> where it is connected.
>
> Currently there is also zero support of of-graph in ASoC, so a bit of work
> is required to get this integrated properly.
>

I also believe this would be the better option but in the meantime can't I
integrate the audio like it is being done in the dw-hdmi driver[1]? In this
driver the audio is registered as a sound card and is conditionally built using
Kconfig, just like I was doing in the previous versions. I know you said the
HDMI audio is still an open issue but it seems that for this case it was 
accepted.

[1] 
http://lxr.free-electrons.com/source/drivers/gpu/drm/bridge/dw-hdmi-ahb-audio.c

Best regards,
Jose Miguel Abreu

[PATCH v3 2/3] drm/dp/mst: Enhance DP MST debugfs output

[Jim Bride]

Add some additional information (input vs. output port, sink associated
with VC, peer device type, max number of VCs supported) and ensure that
any embedded '\0' characters in a branch device's devid string are not
written to debugfs.

v2: Rebase + change drm_edid_get_monitor_name() call to reflect new
signature.

v3: Minor changes suggested by Jani + rebase.

cc: dri-devel at lists.freedesktop.org
cc: Jani Nikula 
Signed-off-by: Jim Bride 
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 29 -
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 27fbd79..06d8b0a 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -2729,7 +2729,7 @@ static void drm_dp_mst_dump_mstb(struct seq_file *m,

seq_printf(m, "%smst: %p, %d\n", prefix, mstb, mstb->num_ports);
list_for_each_entry(port, &mstb->ports, next) {
-   seq_printf(m, "%sport: %d: ddps: %d ldps: %d, sdp: %d/%d, %p, 
conn: %p\n", prefix, port->port_num, port->ddps, port->ldps, 
port->num_sdp_streams, port->num_sdp_stream_sinks, port, port->connector);
+   seq_printf(m, "%sport: %d: input: %d: pdt: %d, ddps: %d ldps: 
%d, sdp: %d/%d, %p, conn: %p\n", prefix, port->port_num, port->input, 
port->pdt, port->ddps, port->ldps, port->num_sdp_streams, 
port->num_sdp_stream_sinks, port, port->connector);
if (port->mstb)
drm_dp_mst_dump_mstb(m, port->mstb);
}
@@ -2750,6 +2750,16 @@ static bool dump_dp_payload_table(struct 
drm_dp_mst_topology_mgr *mgr,
return false;
 }

+static void fetch_monitor_name(struct drm_dp_mst_topology_mgr *mgr,
+  struct drm_dp_mst_port *port, char *name,
+  int namelen)
+{
+   struct edid *mst_edid;
+
+   mst_edid = drm_dp_mst_get_edid(port->connector, mgr, port);
+   drm_edid_get_monitor_name(mst_edid, name, namelen);
+}
+
 /**
  * drm_dp_mst_dump_topology(): dump topology to seq file.
  * @m: seq_file to dump output to
@@ -2762,6 +2772,7 @@ void drm_dp_mst_dump_topology(struct seq_file *m,
 {
int i;
struct drm_dp_mst_port *port;
+
mutex_lock(&mgr->lock);
if (mgr->mst_primary)
drm_dp_mst_dump_mstb(m, mgr->mst_primary);
@@ -2770,14 +2781,21 @@ void drm_dp_mst_dump_topology(struct seq_file *m,
mutex_unlock(&mgr->lock);

mutex_lock(&mgr->payload_lock);
-   seq_printf(m, "vcpi: %lx %lx\n", mgr->payload_mask, mgr->vcpi_mask);
+   seq_printf(m, "vcpi: %lx %lx %d\n", mgr->payload_mask, mgr->vcpi_mask,
+   mgr->max_payloads);

for (i = 0; i < mgr->max_payloads; i++) {
if (mgr->proposed_vcpis[i]) {
+   char name[14];
+
port = container_of(mgr->proposed_vcpis[i], struct 
drm_dp_mst_port, vcpi);
-   seq_printf(m, "vcpi %d: %d %d %d\n", i, port->port_num, 
port->vcpi.vcpi, port->vcpi.num_slots);
+   fetch_monitor_name(mgr, port, name, sizeof(name));
+   seq_printf(m, "vcpi %d: %d %d %d sink name: %s\n", i,
+  port->port_num, port->vcpi.vcpi,
+  port->vcpi.num_slots,
+  (*name != 0) ? name :  "Unknown");
} else
-   seq_printf(m, "vcpi %d:unsed\n", i);
+   seq_printf(m, "vcpi %d:unused\n", i);
}
for (i = 0; i < mgr->max_payloads; i++) {
seq_printf(m, "payload %d: %d, %d, %d\n",
@@ -2817,8 +2835,9 @@ void drm_dp_mst_dump_topology(struct seq_file *m,
for (i = 0; i < 0x3; i++)
seq_printf(m, "%02x", buf[i]);
seq_printf(m, " devid: ");
-   for (i = 0x3; i < 0x8; i++)
+   for (i = 0x3; i < 0x8 && buf[i]; i++)
seq_printf(m, "%c", buf[i]);
+
seq_printf(m, " revision: hw: %x.%x sw: %x.%x", buf[0x9] >> 4, 
buf[0x9] & 0xf, buf[0xa], buf[0xb]);
seq_printf(m, "\n");
bret = dump_dp_payload_table(mgr, buf);
-- 
2.5.0

[PATCH v3 1/3] drm/edid: Add drm_edid_get_monitor_name()

[Jim Bride]

In order to include monitor name information in debugfs
output we needed to add a function that would extract the
monitor name from the EDID, and that function needed to
reside in the file  where the rest of the EDID helper
functions are implemented.

v2: Refactor to have drm_edid_get_monitor_name() and drm_edid_to_eld()
use a common helper function to extract the monitor name from the
edid. [Jani] + rebase.

v3: Minor changes suggested by Jani + rebase.

cc: dri-devel at lists.freedesktop.org
cc: Jani Nikula 
Signed-off-by: Jim Bride 
---
 drivers/gpu/drm/drm_edid.c | 51 ++
 include/drm/drm_crtc.h |  2 ++
 2 files changed, 44 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 558ef9f..da30ce3 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3293,6 +3293,46 @@ monitor_name(struct detailed_timing *t, void *data)
*(u8 **)data = t->data.other_data.data.str.str;
 }

+static int get_monitor_name(struct edid *edid, char name[13])
+{
+   char *edid_name = NULL;
+   int mnl;
+
+   if (!edid || !name)
+   return 0;
+
+   drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
+   for (mnl = 0; edid_name && mnl < 13; mnl++) {
+   if (edid_name[mnl] == 0x0a)
+   break;
+
+   name[mnl] = edid_name[mnl];
+   }
+
+   return mnl;
+}
+
+/**
+ * drm_edid_get_monitor_name - fetch the monitor name from the edid
+ * @edid: monitor EDID information
+ * @name: pointer to a character array to hold the name of the monitor
+ * @bufsize: The size of the name buffer (should be at least 13 chars.)
+ *
+ */
+void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
+{
+   int name_length = -1;
+   char buf[13];
+   
+   if (bufsize <= 0)
+   return;
+
+   name_length = min(get_monitor_name(edid, buf), bufsize - 1);
+   memcpy(name, buf, name_length);
+   name[name_length] = '\0';
+}
+EXPORT_SYMBOL(drm_edid_get_monitor_name);
+
 /**
  * drm_edid_to_eld - build ELD from EDID
  * @connector: connector corresponding to the HDMI/DP sink
@@ -3306,7 +3346,6 @@ void drm_edid_to_eld(struct drm_connector *connector, 
struct edid *edid)
 {
uint8_t *eld = connector->eld;
u8 *cea;
-   u8 *name;
u8 *db;
int total_sad_count = 0;
int mnl;
@@ -3320,14 +3359,8 @@ void drm_edid_to_eld(struct drm_connector *connector, 
struct edid *edid)
return;
}

-   name = NULL;
-   drm_for_each_detailed_block((u8 *)edid, monitor_name, &name);
-   /* max: 13 bytes EDID, 16 bytes ELD */
-   for (mnl = 0; name && mnl < 13; mnl++) {
-   if (name[mnl] == 0x0a)
-   break;
-   eld[20 + mnl] = name[mnl];
-   }
+   mnl = get_monitor_name(edid, eld + 20);
+
eld[4] = (cea[1] << 5) | mnl;
DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);

diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 8cb377c..6d46842 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -2500,6 +2500,8 @@ extern int drm_edid_header_is_valid(const u8 *raw_edid);
 extern bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
 bool *edid_corrupt);
 extern bool drm_edid_is_valid(struct edid *edid);
+extern void drm_edid_get_monitor_name(struct edid *edid, char *name,
+ int buflen);

 extern struct drm_tile_group *drm_mode_create_tile_group(struct drm_device 
*dev,
 char topology[8]);
-- 
2.5.0