Re: [edk2-devel] [PATCH v2 10/11] DynamicTablesPkg: Add ETE device to CPU node in AML

[Sami Mujawar]

Hi Jeshua,

Thank you for the feedback.

On 13/09/2023, 16:06, "Jeshua Smith" mailto:jesh...@nvidia.com>> wrote:


Not sure it's worth creating a new patchset for, but the "GetEArmObjEtInfo 
(OPTIONAL)" comment should probably not have the "Get" prefix (ie. " 
EArmObjEtInfo (OPTIONAL)").
[SAMI] I think I will fix this before I merge the series.

Regards,

Sami Mujawar

-Original Message-
From: Sami Mujawar mailto:sami.muja...@arm.com>> 
Sent: Wednesday, September 13, 2023 6:50 AM
To: devel@edk2.groups.io 
Cc: Sami Mujawar mailto:sami.muja...@arm.com>>; 
pierre.gond...@arm.com ; 
anshuman.khand...@arm.com ; 
matteo.carl...@arm.com ; akanksha.ja...@arm.com 
; sibel.allin...@arm.com 
; Jeshua Smith mailto:jesh...@nvidia.com>>; n...@arm.com 
Subject: [PATCH v2 10/11] DynamicTablesPkg: Add ETE device to CPU node in AML


External email: Use caution opening links or attachments




The Coresight Embedded Trace Extension (ETE) feature can be detected by the 
platform firmware by examining the debug feature register 
ID_AA64DFR0_EL1.TraceVer field.
The platform configuration manager can then describe the ETE by creating 
CM_ARM_ET_INFO object(s) and referencing these in CM_ARM_GICC_INFO.EtToken.


The 'Table 3: Compatible IDs for architected CoreSight components' in the 'ACPI 
for CoreSight
1.2 Platform Design Document' specifies the HID value for Coresight ETE and 
CoreSight Embedded Trace Macrocell (ETM) v4.x as ARMH C500.


Therefore, update the SsdtCpuTopologyGenerator to add an ETE device to the CPU 
node in the AML CPU hierarchy so that an OS can utilise this information.


Note: Although ETE and ETM share the same HID, ETE has a system register 
interfaces, unlike ETM which requires memory mapped registers.
Since this patch aims to support ETE, the AML description does not describe any 
memory mapped registers. However, support for ETM can be added in the future.


Signed-off-by: Sami Mujawar mailto:sami.muja...@arm.com>>
---


Notes:
v2:
- No code change from v1 patch series. [SAMI]


DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyGenerator.c
 | 186 +++- 
DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyGenerator.h
 | 11 +-
2 files changed, 195 insertions(+), 2 deletions(-)


diff --git 
a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyGenerator.c
 
b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyGenerator.c
index 
6fb131b664820adca63c9efa6d8b0e17fc64284e..6fbba12a010bf987797f0901a032735e8e0be598
 100644
--- 
a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCpuTopologyGenerator.c
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCpuTopologyLibArm/SsdtCp
+++ uTopologyGenerator.c
@@ -1,11 +1,17 @@
/** @file
SSDT Cpu Topology Table Generator.


- Copyright (c) 2021, Arm Limited. All rights reserved.
+ Copyright (c) 2021 - 2023, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent


@par Reference(s):
- ACPI 6.3 Specification - January 2019 - s8.4 Declaring Processors
+ - ACPI for CoreSight version 1.2 Platform Design Document
+ 
+ (https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdev 

+ eloper.arm.com%2Fdocumentation%2Fden0067%2Fa%2F%3Flang%3Den&data=05%7C
+ 01%7Cjeshuas%40nvidia.com%7C26e54e899c78479dfa9708dbb457f3cd%7C43083d1
+ 5727340c1b7db39efd9ccc17a%7C0%7C0%7C638302062091232606%7CUnknown%7CTWF
+ pbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6M
+ n0%3D%7C3000%7C%7C%7C&sdata=PV447Rl4K7EXTgSc9g%2BcjTzXYmMsKs0QMkpXRnwx
+ KkI%3D&reserved=0)
+
+ @par Glossary:
+ - ETE - Embedded Trace Extension.
+ - ETM - Embedded Trace Macrocell.
**/


#include 
@@ -35,6 +41,7 @@ Requirements:
- EArmObjProcHierarchyInfo (OPTIONAL) along with
- EArmObjCmRef (OPTIONAL)
- EArmObjLpiInfo (OPTIONAL)
+ - GetEArmObjEtInfo (OPTIONAL)
*/


/** This macro expands to a function that retrieves the GIC @@ -86,6 +93,16 @@ 
GET_OBJECT_LIST (
CM_ARM_CPC_INFO
);


+/**
+ This macro expands to a function that retrieves the ET device
+ information from the Configuration Manager.
+*/
+GET_OBJECT_LIST (
+ EObjNameSpaceArm,
+ EArmObjEtInfo,
+ CM_ARM_ET_INFO
+ );
+
/** Initialize the TokenTable.


One entry should be allocated for each CM_ARM_PROC_HIERARCHY_INFO @@ -326,6 
+343,144 @@ CreateAmlCpcNode (
return Status;
}


+/** Create an embedded trace device and add it to the Cpu Node in the
+ AML namespace.
+
+ This generates the following ASL code:
+ Device (E002)
+ {
+ Name (_UID, 2)
+ Name (_HID, "ARMHC500")
+ }
+
+ Note: Currently we only support generating ETE nodes. Unlike ETM, 
+ ETE has a system register interface and therefore does not need the 
+ MMI

Re: [edk2-devel] [PATCH 1/3] OvmfPkg/RiscVVirt/README: explain that "-bios" is only useful with TCG

[Andrew Jones]

On Wed, Sep 13, 2023 at 12:55:49PM +0200, Laszlo Ersek wrote:
> Riscv64 KVM services SBI calls internally, so OpenSBI is not used in such
> setups. Restrict the "-bios" flag accordingly. Thanks: Andrei, Drew.
> 
> Cc: Andrei Warkentin 
> Cc: Andrew Jones 
> Cc: Ard Biesheuvel 
> Cc: Gerd Hoffmann 
> Cc: Jiewen Yao 
> Cc: Jordan Justen 
> Cc: Sunil V L 
> Signed-off-by: Laszlo Ersek 
> ---
>  OvmfPkg/RiscVVirt/README.md | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/OvmfPkg/RiscVVirt/README.md b/OvmfPkg/RiscVVirt/README.md
> index dbb40bbe89b0..193e4afe8dee 100644
> --- a/OvmfPkg/RiscVVirt/README.md
> +++ b/OvmfPkg/RiscVVirt/README.md
> @@ -86,3 +86,8 @@ then specify that binary for QEMU, with the following 
> additional command line
>  option:
>  
>  -bios $OPENSBI_DIR/build/platform/generic/firmware/fw_dynamic.bin
> +
> +Note that the above only makes a difference with software emulation (which 
> you
> +can force with `-M accel=tcg`). With hardware virtualization (`-M 
> accel=kvm`),
> +KVM services the SBI (Supervisor Binary Interface) calls internally, 
> therefore
> +any externally loaded OpenSBI binary is ignored.
>


Reviewed-by: Andrew Jones 


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Re: [edk2-devel] [PATCH 2/3] OvmfPkg/RiscVVirt/README: explain the "acpi=off" machine property

[Andrew Jones]

On Wed, Sep 13, 2023 at 12:55:50PM +0200, Laszlo Ersek wrote:
> "acpi=off" is arguably unusual with UEFI guest OSes; add a note to explain
> it. Original explanation by Drew Jones.
> 
> Cc: Andrei Warkentin 
> Cc: Andrew Jones 
> Cc: Ard Biesheuvel 
> Cc: Gerd Hoffmann 
> Cc: Jiewen Yao 
> Cc: Jordan Justen 
> Cc: Sunil V L 
> Signed-off-by: Laszlo Ersek 
> ---
>  OvmfPkg/RiscVVirt/README.md | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/OvmfPkg/RiscVVirt/README.md b/OvmfPkg/RiscVVirt/README.md
> index 193e4afe8dee..1dba1a26af2d 100644
> --- a/OvmfPkg/RiscVVirt/README.md
> +++ b/OvmfPkg/RiscVVirt/README.md
> @@ -70,6 +70,11 @@ Below example shows how to boot openSUSE Tumbleweed E20.
>  -device virtio-blk-device,drive=hd0 \
>  -drive 
> file=openSUSE-Tumbleweed-RISC-V-E20-efi.riscv64.raw,format=raw,id=hd0
>  
> +Note: the `acpi=off` machine property is specified because Linux guest
> +support for ACPI (that is, the ACPI consumer side) is a work in progress.
> +Currently, `acpi=off` is recommended unless you are developing ACPI 
> support
> +yourself.
> +
>  ## Test with your own OpenSBI binary
>  Using the above QEMU command line, **RISCV_VIRT_CODE.fd** is launched by the
>  OpenSBI binary that is bundled with QEMU. You can build your own OpenSBI 
> binary
>

Reviewed-by: Andrew Jones 


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Re: [edk2-devel] [PATCH 3/3] OvmfPkg/RiscVVirt/README: document direct kernel boot

[Andrew Jones]

On Wed, Sep 13, 2023 at 12:55:51PM +0200, Laszlo Ersek wrote:
> Direct (fw_cfg) kernel boot works on the RiscVVirt firmware platform too;
> I've tested it after extracting the kernel, initrd, and kernel command
> line from "openSUSE-Tumbleweed-RISC-V-E20-efi.riscv64.raw". Document this
> type of boot, because at least historically, fw_cfg kernel boot was
> implemented differently between OVMF and ArmVirtQemu. Thanks: Drew, Sunil.
> 
> Cc: Andrei Warkentin 
> Cc: Andrew Jones 
> Cc: Ard Biesheuvel 
> Cc: Gerd Hoffmann 
> Cc: Jiewen Yao 
> Cc: Jordan Justen 
> Cc: Sunil V L 
> Signed-off-by: Laszlo Ersek 
> ---
>  OvmfPkg/RiscVVirt/README.md | 33 +++-
>  1 file changed, 32 insertions(+), 1 deletion(-)
> 
> diff --git a/OvmfPkg/RiscVVirt/README.md b/OvmfPkg/RiscVVirt/README.md
> index 1dba1a26af2d..47b97dd64a2f 100644
> --- a/OvmfPkg/RiscVVirt/README.md
> +++ b/OvmfPkg/RiscVVirt/README.md
> @@ -75,8 +75,39 @@ Below example shows how to boot openSUSE Tumbleweed E20.
>  Currently, `acpi=off` is recommended unless you are developing ACPI 
> support
>  yourself.
>  
> +3) Running QEMU with direct kernel boot
> +
> +The following example boots the same guest, but loads the kernel image 
> and
> +the initial RAM disk (which were extracted from
> +`openSUSE-Tumbleweed-RISC-V-E20-efi.riscv64.raw`) from the host 
> filesystem.
> +It also sets the guest kernel command line on the QEMU command line.
> +
> +CMDLINE=(root=UUID=76d9b92d-09e9-4df0-8262-c1a7a466f2bc
> + systemd.show_status=1
> + ignore_loglevel
> + console=ttyS0
> + earlycon=uart8250,mmio,0x1000)
> +
> +qemu-system-riscv64 \
> +-M virt,pflash0=pflash0,pflash1=pflash1,acpi=off \
> +-m 4096 -smp 2 \
> +-serial mon:stdio \
> +-device virtio-gpu-pci -full-screen \
> +-device qemu-xhci \
> +-device usb-kbd \
> +-device virtio-rng-pci \
> +-blockdev 
> node-name=pflash0,driver=file,read-only=on,filename=RISCV_VIRT_CODE.fd \
> +-blockdev node-name=pflash1,driver=file,filename=RISCV_VIRT_VARS.fd \
> +-netdev user,id=net0 \
> +-device virtio-net-pci,netdev=net0 \
> +-device virtio-blk-device,drive=hd0 \
> +-drive 
> file=openSUSE-Tumbleweed-RISC-V-E20-efi.riscv64.raw,format=raw,id=hd0 \
> +-kernel Image-6.5.2-1-default \
> +-initrd initrd-6.5.2-1-default \
> +-append "${CMDLINE[*]}"
> +
>  ## Test with your own OpenSBI binary
> -Using the above QEMU command line, **RISCV_VIRT_CODE.fd** is launched by the
> +Using the above QEMU command lines, **RISCV_VIRT_CODE.fd** is launched by the
>  OpenSBI binary that is bundled with QEMU. You can build your own OpenSBI 
> binary
>  as well:
>

Reviewed-by: Andrew Jones 


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Re: [edk2-devel] [PATCH 1/3] OvmfPkg/RiscVVirt/README: explain that "-bios" is only useful with TCG

[Andrew Jones]

On Thu, Sep 14, 2023 at 09:23:12AM +0200, Andrew Jones wrote:
> On Wed, Sep 13, 2023 at 12:55:49PM +0200, Laszlo Ersek wrote:
> > Riscv64 KVM services SBI calls internally, so OpenSBI is not used in such
> > setups. Restrict the "-bios" flag accordingly. Thanks: Andrei, Drew.
> > 
> > Cc: Andrei Warkentin 
> > Cc: Andrew Jones 
> > Cc: Ard Biesheuvel 
> > Cc: Gerd Hoffmann 
> > Cc: Jiewen Yao 
> > Cc: Jordan Justen 
> > Cc: Sunil V L 
> > Signed-off-by: Laszlo Ersek 
> > ---
> >  OvmfPkg/RiscVVirt/README.md | 5 +
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/OvmfPkg/RiscVVirt/README.md b/OvmfPkg/RiscVVirt/README.md
> > index dbb40bbe89b0..193e4afe8dee 100644
> > --- a/OvmfPkg/RiscVVirt/README.md
> > +++ b/OvmfPkg/RiscVVirt/README.md
> > @@ -86,3 +86,8 @@ then specify that binary for QEMU, with the following 
> > additional command line
> >  option:
> >  
> >  -bios $OPENSBI_DIR/build/platform/generic/firmware/fw_dynamic.bin
> > +
> > +Note that the above only makes a difference with software emulation (which 
> > you
> > +can force with `-M accel=tcg`). With hardware virtualization (`-M 
> > accel=kvm`),
> > +KVM services the SBI (Supervisor Binary Interface) calls internally, 
> > therefore
> > +any externally loaded OpenSBI binary is ignored.
> >
> 
> 
> Reviewed-by: Andrew Jones 

Eh, sorry for the redundant r-b and my 'ignored' comment still stands,
i.e. I wouldn't mind seeing a v2 with s/ignored/rejected/

Thanks,
drew


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Re: [edk2-devel] [PATCH 1/3] OvmfPkg/RiscVVirt/README: explain that "-bios" is only useful with TCG

[Laszlo Ersek]

On 9/13/23 18:28, Andrew Jones wrote:
> On Wed, Sep 13, 2023 at 12:55:49PM +0200, Laszlo Ersek wrote:
>> Riscv64 KVM services SBI calls internally, so OpenSBI is not used in such
>> setups. Restrict the "-bios" flag accordingly. Thanks: Andrei, Drew.
>>
>> Cc: Andrei Warkentin 
>> Cc: Andrew Jones 
>> Cc: Ard Biesheuvel 
>> Cc: Gerd Hoffmann 
>> Cc: Jiewen Yao 
>> Cc: Jordan Justen 
>> Cc: Sunil V L 
>> Signed-off-by: Laszlo Ersek 
>> ---
>>  OvmfPkg/RiscVVirt/README.md | 5 +
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/OvmfPkg/RiscVVirt/README.md b/OvmfPkg/RiscVVirt/README.md
>> index dbb40bbe89b0..193e4afe8dee 100644
>> --- a/OvmfPkg/RiscVVirt/README.md
>> +++ b/OvmfPkg/RiscVVirt/README.md
>> @@ -86,3 +86,8 @@ then specify that binary for QEMU, with the following 
>> additional command line
>>  option:
>>  
>>  -bios $OPENSBI_DIR/build/platform/generic/firmware/fw_dynamic.bin
>> +
>> +Note that the above only makes a difference with software emulation (which 
>> you
>> +can force with `-M accel=tcg`). With hardware virtualization (`-M 
>> accel=kvm`),
>> +KVM services the SBI (Supervisor Binary Interface) calls internally, 
>> therefore
>> +any externally loaded OpenSBI binary is ignored.
>>
> 
> With the 'virt' machine model -bios is actually forbidden with accel=kvm,
> not just ignored.

Thanks, I think I should then say:

  therefore any OpenSBI binary specified with `-bios` is rejected

(I think I can still technically merge this series myself on github,
once it's been reviewed, so I could fix this up, to keep the churn low
for the maintainers.)

Unfortunately, I can't test KVM here; got no riscv64 hardware. (And I'm
not really considering nesting KVM under TCG! :) Even if TCG emulated
the virtualization extensions (?), the speed would probably be unbearable.)

> 
> Otherwise,
> 
> Reviewed-by: Andrew Jones 
> 
> Thanks,
> drew
> 

Thanks!
Laszlo



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Re: [edk2-devel] [PATCH v2 5/7] DynamicTablesPkg.ci.yaml: Add debug macro exception

[Sami Mujawar]

Hi Michael,

I would prefer to have the debug macro checks enabled in DynamicTablesPkg to 
catch any issues. 

Please do not disable this feature for this package.

Regards,

Sami Mujawar

On 13/09/2023, 18:08, "mikub...@linux.microsoft.com 
" mailto:mikub...@linux.microsoft.com>> wrote:


From: Michael Kubacki mailto:michael.kuba...@microsoft.com>>


Adds a CI YAML entry to acknowledge a case where custom strings
contain print specifiers for a single debug macro.


Cc: Sami Mujawar mailto:sami.muja...@arm.com>>
Cc: Alexei Fedorov mailto:alexei.fedo...@arm.com>>
Cc: Pierre Gondois mailto:pierre.gond...@arm.com>>
Signed-off-by: Michael Kubacki mailto:michael.kuba...@microsoft.com>>
---
DynamicTablesPkg/DynamicTablesPkg.ci.yaml | 8 
1 file changed, 8 insertions(+)


diff --git a/DynamicTablesPkg/DynamicTablesPkg.ci.yaml 
b/DynamicTablesPkg/DynamicTablesPkg.ci.yaml
index 5addf8626841..1d41d44bbf33 100644
--- a/DynamicTablesPkg/DynamicTablesPkg.ci.yaml
+++ b/DynamicTablesPkg/DynamicTablesPkg.ci.yaml
@@ -130,5 +130,13 @@
# should be ignore
"AdditionalIncludePaths": [] # Additional paths to spell check
# (wildcards supported)
+ },
+
+ "DebugMacroCheck": {
+ "StringSubstitutions": {
+ # 
DynamicTablesPkg/Library/Common/TableHelperLib/ConfigurationManagerObjectParser.c
+ # Reason: Debug format strings are dynamically set.
+ "Parser[Index].Format": "%d"
+ }
}
}
-- 
2.42.0.windows.2







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Re: [edk2-devel] [PATCH 0/3] updates for "OvmfPkg/RiscVVirt/README.md"

[Sunil V L]

Hi Laszlo,

For the series with anticipated change for Drew's comment.

Reviewed-by: Sunil V L 

Do you plan to queue this up with that change? Feel free to let me know
if you want me to take care.

Thanks,
Sunil
On Wed, Sep 13, 2023 at 12:55:48PM +0200, Laszlo Ersek wrote:
> The shortlog below provides a good summary :)
> 
> Cc: Andrei Warkentin 
> Cc: Andrew Jones 
> Cc: Ard Biesheuvel 
> Cc: Gerd Hoffmann 
> Cc: Jiewen Yao 
> Cc: Jordan Justen 
> Cc: Sunil V L 
> 
> Thanks
> Laszlo
> 
> Laszlo Ersek (3):
>   OvmfPkg/RiscVVirt/README: explain that "-bios" is only useful with TCG
>   OvmfPkg/RiscVVirt/README: explain the "acpi=off" machine property
>   OvmfPkg/RiscVVirt/README: document direct kernel boot
> 
>  OvmfPkg/RiscVVirt/README.md | 43 +++-
>  1 file changed, 42 insertions(+), 1 deletion(-)
> 


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Re: [edk2-devel] [PATCH 0/3] updates for "OvmfPkg/RiscVVirt/README.md"

[Laszlo Ersek]

On 9/14/23 11:05, Sunil V L wrote:
> Hi Laszlo,
> 
> For the series with anticipated change for Drew's comment.
> 
> Reviewed-by: Sunil V L 
> 
> Do you plan to queue this up with that change? Feel free to let me know
> if you want me to take care.

Yes I'll try to submit the MR with the "push" label set.

Thanks!
Laszlo

> 
> Thanks,
> Sunil
> On Wed, Sep 13, 2023 at 12:55:48PM +0200, Laszlo Ersek wrote:
>> The shortlog below provides a good summary :)
>>
>> Cc: Andrei Warkentin 
>> Cc: Andrew Jones 
>> Cc: Ard Biesheuvel 
>> Cc: Gerd Hoffmann 
>> Cc: Jiewen Yao 
>> Cc: Jordan Justen 
>> Cc: Sunil V L 
>>
>> Thanks
>> Laszlo
>>
>> Laszlo Ersek (3):
>>   OvmfPkg/RiscVVirt/README: explain that "-bios" is only useful with TCG
>>   OvmfPkg/RiscVVirt/README: explain the "acpi=off" machine property
>>   OvmfPkg/RiscVVirt/README: document direct kernel boot
>>
>>  OvmfPkg/RiscVVirt/README.md | 43 +++-
>>  1 file changed, 42 insertions(+), 1 deletion(-)
>>
> 



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Re: [edk2-devel] [PATCH v2 5/7] DynamicTablesPkg.ci.yaml: Add debug macro exception

[Sami Mujawar]

Hi Michael,

Apologies, I initially misunderstood what this patch was trying to do.
As I understand this is an exception for one of the special cases to be handled 
differently by the plugin.

Acked-by: Sami Mujawar 

Regards,

Sami Mujawar

On 14/09/2023, 09:42, "devel@edk2.groups.io  on 
behalf of Sami Mujawar via groups.io" mailto:devel@edk2.groups.io> on behalf of sami.mujawar=arm@groups.io 
> wrote:


Hi Michael,


I would prefer to have the debug macro checks enabled in DynamicTablesPkg to 
catch any issues. 


Please do not disable this feature for this package.


Regards,


Sami Mujawar


On 13/09/2023, 18:08, "mikub...@linux.microsoft.com 
 >" mailto:mikub...@linux.microsoft.com> >> wrote:




From: Michael Kubacki mailto:michael.kuba...@microsoft.com> >>




Adds a CI YAML entry to acknowledge a case where custom strings
contain print specifiers for a single debug macro.




Cc: Sami Mujawar mailto:sami.muja...@arm.com> 
>>
Cc: Alexei Fedorov mailto:alexei.fedo...@arm.com> 
>>
Cc: Pierre Gondois mailto:pierre.gond...@arm.com> 
>>
Signed-off-by: Michael Kubacki mailto:michael.kuba...@microsoft.com> >>
---
DynamicTablesPkg/DynamicTablesPkg.ci.yaml | 8 
1 file changed, 8 insertions(+)




diff --git a/DynamicTablesPkg/DynamicTablesPkg.ci.yaml 
b/DynamicTablesPkg/DynamicTablesPkg.ci.yaml
index 5addf8626841..1d41d44bbf33 100644
--- a/DynamicTablesPkg/DynamicTablesPkg.ci.yaml
+++ b/DynamicTablesPkg/DynamicTablesPkg.ci.yaml
@@ -130,5 +130,13 @@
# should be ignore
"AdditionalIncludePaths": [] # Additional paths to spell check
# (wildcards supported)
+ },
+
+ "DebugMacroCheck": {
+ "StringSubstitutions": {
+ # 
DynamicTablesPkg/Library/Common/TableHelperLib/ConfigurationManagerObjectParser.c
+ # Reason: Debug format strings are dynamically set.
+ "Parser[Index].Format": "%d"
+ }
}
}
-- 
2.42.0.windows.2
























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Re: [edk2-devel] [PATCH] MdeModulePkg/SmbiosDxe: Fix BcdRevision is not match with SMBIOS version

[Lien, HoraceX]

Hi Mike,

https://github.com/tianocore/edk2/pull/4771
I have changed code following rule: It is only accept range 0-9 for Major and 
Minor version to fill in SmbiosBcdRevision, if one of Major or Minor is greater 
than 9 then fill in 00h.

Please help to review this, thanks :)

Thanks,
Horace Lien

-Original Message-
From: Lien, HoraceX 
Sent: Friday, September 8, 2023 5:35 PM
To: Kinney, Michael D ; devel@edk2.groups.io; Gao, 
Liming 
Cc: Liu, Zhiguang ; Bi, Dandan ; 
Zeng, Star ; Gao, Zhichao 
Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/SmbiosDxe: Fix BcdRevision is 
not match with SMBIOS version

Hi Mike,

No, we didn't guarantee this before. Add comments to descript BCD field is good 
point.
I have reviewed SMBIOS spec for SmbiosBcdRevision field, it mentions "If the 
value is 00h, only the Major and Minor Versions in offsets 6 and 7 of the Entry 
Point Structure provide the version information. ". So, I have new idea to 
implement this, I will filter range 0-9 for Major/Minor version to fill in 
SmbiosBcdRevision, if one of Major or Minor is greater than 9 then fill in 00h.
Do you think it is ok?

Thanks for your reply.

Thanks,
Horace Lien

-Original Message-
From: Kinney, Michael D 
Sent: Friday, September 8, 2023 6:05 AM
To: Lien, HoraceX ; devel@edk2.groups.io; Gao, Liming 

Cc: Liu, Zhiguang ; Bi, Dandan ; 
Zeng, Star ; Gao, Zhichao ; Kinney, 
Michael D 
Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/SmbiosDxe: Fix BcdRevision is 
not match with SMBIOS version

I was asking about the property of the global variables being used in this 
patch.  Are they already guaranteed to be in BSD format and in range 0..9.  If 
so, then no additional code changes would be required.  However, it would be 
good to add comments about the properties of those global variables and why 
they can be used to directly assign to fields that are required to be in BSD 
format.

Mike

> -Original Message-
> From: Lien, HoraceX 
> Sent: Thursday, September 7, 2023 2:41 AM
> To: devel@edk2.groups.io; Kinney, Michael D 
> ; Gao, Liming 
> Cc: Liu, Zhiguang ; Bi, Dandan 
> ; Zeng, Star ; Gao, Zhichao 
> ; Lien, HoraceX 
> Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/SmbiosDxe: Fix 
> BcdRevision is not match with SMBIOS version
> 
> Hi Mike,
> 
> Could you please reply for me?
> If you want to filter range 0-9, then I will send PR again.
> 
> Thanks,
> Horace Lien
> 
> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Lien, 
> HoraceX
> Sent: Friday, September 1, 2023 3:06 PM
> To: Kinney, Michael D ; 
> devel@edk2.groups.io
> Cc: Liu, Zhiguang ; Bi, Dandan 
> ; Zeng, Star ; Gao, Zhichao 
> 
> Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/SmbiosDxe: Fix 
> BcdRevision is not match with SMBIOS version
> 
> Hi Mike,
> 
> I have change code to
> EntryPointStructureData.SmbiosBcdRevision = 
> ((mPrivateData.Smbios.MajorVersion & 0x0f) << 4) | 
> (mPrivateData.Smbios.MinorVersion & 0x0f); Add &0x0F to mask upper 
> nibble bit, do we still need to guarantee that range is between 0-9?
> Because the old code only filtered 4 bits, instead of accurately 
> filtering the number range 0-9.
> 
> Thanks,
> Horace Lien
> 
> -Original Message-
> From: Kinney, Michael D 
> Sent: Thursday, August 31, 2023 11:56 PM
> To: devel@edk2.groups.io; Lien, HoraceX 
> Cc: Liu, Zhiguang ; Bi, Dandan 
> ; Zeng, Star ; Gao, Zhichao 
> ; Kinney, Michael D 
> 
> Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/SmbiosDxe: Fix 
> BcdRevision is not match with SMBIOS version
> 
> Are mPrivateData.Smbios.MajorVersion and 
> mPrivateData.Smbios.MinorVersion guaranteed to be in range 0..9?
> 
> Mike
> 
> > -Original Message-
> > From: devel@edk2.groups.io  On Behalf Of 
> > horacex.l...@intel.com
> > Sent: Wednesday, August 30, 2023 2:13 AM
> > To: devel@edk2.groups.io
> > Cc: Lien, HoraceX ; Liu, Zhiguang 
> > ; Bi, Dandan ; Zeng, 
> > Star ; Gao, Zhichao 
> > Subject: [edk2-devel] [PATCH] MdeModulePkg/SmbiosDxe: Fix 
> > BcdRevision is not match with SMBIOS version
> >
> > From: HoraceX Lien 
> >
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4544
> >
> > These value of Major/Minor version are updated from SMBIOS memory 
> > data, but BCD Revision is updated from PCD PcdSmbiosVersion.
> > We should also update PCD PcdSmbiosVersion from SMBIOS memory data, 
> > to ensure that get consistent version value.
> >
> > Cc: Zhiguang Liu 
> > Cc: Dandan Bi 
> > Cc: Star Zeng 
> > Cc: Zhichao Gao 
> > Signed-off-by: HoraceX Lien 
> > ---
> >  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c
> > b/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c
> > index 1a86e69d3c..e3f6215033 100644
> > --- a/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c
> > +++ b/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c
> > @@ -1072,7 +1072,7 @@ SmbiosCreateTable (
> >  DEBUG ((DEBUG_INFO, "SmbiosCreateTable: Ini

Re: [edk2-devel] [PATCH 0/3] updates for "OvmfPkg/RiscVVirt/README.md"

[Laszlo Ersek]

On 9/13/23 12:55, Laszlo Ersek wrote:
> The shortlog below provides a good summary :)
>
> Cc: Andrei Warkentin 
> Cc: Andrew Jones 
> Cc: Ard Biesheuvel 
> Cc: Gerd Hoffmann 
> Cc: Jiewen Yao 
> Cc: Jordan Justen 
> Cc: Sunil V L 
>
> Thanks
> Laszlo
>
> Laszlo Ersek (3):
>   OvmfPkg/RiscVVirt/README: explain that "-bios" is only useful with TCG
>   OvmfPkg/RiscVVirt/README: explain the "acpi=off" machine property
>   OvmfPkg/RiscVVirt/README: document direct kernel boot
>
>  OvmfPkg/RiscVVirt/README.md | 43 +++-
>  1 file changed, 42 insertions(+), 1 deletion(-)
>

Merged as commit range cdfe4310dda2..29cce3356aec via
.

Range-diff between the posted and merged series:

1:  f99c0f999a47 ! 1:  5242bae5ddbb OvmfPkg/RiscVVirt/README: explain that 
"-bios" is only useful with TCG
@@ Commit message
 Cc: Jordan Justen 
 Cc: Sunil V L 
 Signed-off-by: Laszlo Ersek 
+[ler...@redhat.com: '-bios' is rejected with KVM accel (Drew)]
+Reviewed-by: Andrew Jones 
+Reviewed-by: Sunil V L 

  ## OvmfPkg/RiscVVirt/README.md ##
 @@ OvmfPkg/RiscVVirt/README.md: then specify that binary for QEMU, with 
the following additional command line
@@ OvmfPkg/RiscVVirt/README.md: then specify that binary for QEMU, with the 
followi
 +Note that the above only makes a difference with software emulation 
(which you
 +can force with `-M accel=tcg`). With hardware virtualization (`-M 
accel=kvm`),
 +KVM services the SBI (Supervisor Binary Interface) calls internally, 
therefore
-+any externally loaded OpenSBI binary is ignored.
++any OpenSBI binary specified with `-bios` is rejected.
2:  d759e9453cc7 ! 2:  1bfd63ac3955 OvmfPkg/RiscVVirt/README: explain the 
"acpi=off" machine property
@@ Commit message
 Cc: Jordan Justen 
 Cc: Sunil V L 
 Signed-off-by: Laszlo Ersek 
+Reviewed-by: Andrew Jones 
+Reviewed-by: Sunil V L 

  ## OvmfPkg/RiscVVirt/README.md ##
 @@ OvmfPkg/RiscVVirt/README.md: Below example shows how to boot openSUSE 
Tumbleweed E20.
3:  8d69ece226fc ! 3:  29cce3356aec OvmfPkg/RiscVVirt/README: document direct 
kernel boot
@@ Commit message
 Cc: Jordan Justen 
 Cc: Sunil V L 
 Signed-off-by: Laszlo Ersek 
+Reviewed-by: Andrew Jones 
+Reviewed-by: Sunil V L 

  ## OvmfPkg/RiscVVirt/README.md ##
 @@ OvmfPkg/RiscVVirt/README.md: Below example shows how to boot openSUSE 
Tumbleweed E20.

Laszlo



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Re: [edk2-devel] [PATCH 0/3] updates for "OvmfPkg/RiscVVirt/README.md"

[Sunil V L]

On Thu, Sep 14, 2023 at 12:55:02PM +0200, Laszlo Ersek wrote:
> On 9/13/23 12:55, Laszlo Ersek wrote:
> > The shortlog below provides a good summary :)
> >
> > Cc: Andrei Warkentin 
> > Cc: Andrew Jones 
> > Cc: Ard Biesheuvel 
> > Cc: Gerd Hoffmann 
> > Cc: Jiewen Yao 
> > Cc: Jordan Justen 
> > Cc: Sunil V L 
> >
> > Thanks
> > Laszlo
> >
> > Laszlo Ersek (3):
> >   OvmfPkg/RiscVVirt/README: explain that "-bios" is only useful with TCG
> >   OvmfPkg/RiscVVirt/README: explain the "acpi=off" machine property
> >   OvmfPkg/RiscVVirt/README: document direct kernel boot
> >
> >  OvmfPkg/RiscVVirt/README.md | 43 +++-
> >  1 file changed, 42 insertions(+), 1 deletion(-)
> >
> 
> Merged as commit range cdfe4310dda2..29cce3356aec via
> .
> 
Thank you for taking care!

Regards
Sunil


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[edk2-devel] Problems mocking UEFI Protocol in gMock

[CrossedCarpet]

Greetings,
I have successfully mocked standalone functions employing the FunctionMockLib 
macros.
Nonetheless, I have been stuck in making progress regarding mocking a protocol.
The problem is that the function pointers of the protocol mock structure are 
not being properly initialized.
Below I try to illustrate with a made up UEFI protocol.

This is the test I want to mock:

// function that uses my mocked function

INTN getCount() {

// successfully mocked: CounterProtocol = mockCounterProtocol;

gBS->LocateProtocol(&gCounterProtocol, (VOID **)&CounterProtocol);
return CounterProtocol->Count();

}

// gTest file

TEST(getCountTest, returnCount) {

MockUefiBootServicesTable  mockBootServices;

MockCounterProtocol         mockCounterProtocol;

// expect_call on locate_protocol, where I assign &mockCounterProtocol with the 
custom action macro, ACTION_P

EXPECT_CALL (mockCounterProtocol, Count).WillOnce (Return (42));

getCount(); // seg fault, gdb shows CounterProtocol->Count points to NULL

}

My first attempt employed FunctionMockLib:

// header file
struct MockCounterProtocol {
MOCK_INTERFACE_DECLARATION(MockCounterProtocol);
MOCK_FUNCTION_DECLARTION(INTN, Count, ());
}

// source file

MOCK_INTERFACE_DEFINITION (MockCounterProtocol)
MOCK_FUNCTION_DEFINITION (MockCounterProtocol, Count, 0, EFIAPI)

No success, then I realized I probably needed to follow the usual C++ pattern 
for mocking a class:

// header file again
struct MockCounterProtocol: CounterProtocolStruct {
MOCK_METHOD (INTN, Count, ());
};
// source file empty...

I have also tried setting the function pointer directly in the test but no 
success so far.
I believe the solution might be simple, as it always is, but since I have been 
around this for days (weeks if I include setting up mocking in general) your 
help is greatly appreciated.

Regards,
C.C.


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Re: [edk2-devel] [PATCH 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio 
components

Adds the following modules:
  - IpBlock/CpuPcieRp/Include
  - IpBlock/Espi/Library
  - IpBlock/Gpio/IncludePrivate
  - IpBlock/Gpio/Library
  - IpBlock/Gpio/LibraryPrivate

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../IpBlock/CpuPcieRp/Include/CpuPcieInfo.h   |  25 +
 .../Espi/Library/PeiDxeSmmEspiLib/EspiLib.c   |  58 ++
 .../PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf |  38 ++
 .../IncludePrivate/Library/GpioHelpersLib.h   |  50 ++
 .../IncludePrivate/Library/GpioNativePads.h   | 245 
 .../IncludePrivate/Library/GpioPrivateLib.h   | 350 +++
 .../Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c  | 546 ++
 .../Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c   | 522 +
 .../Library/PeiDxeSmmGpioLib/GpioLibrary.h|  29 +
 .../Library/PeiDxeSmmGpioLib/GpioNativeLib.c  | 177 ++
 .../PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf |  44 ++
 .../BaseGpioHelpersLibNull.c  |  51 ++
 .../BaseGpioHelpersLibNull.inf|  25 +
 .../GpioNativePrivateLibInternal.h|  48 ++
 .../PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c  | 267 +
 .../GpioPrivateLibPch.c   | 172 ++
 .../GpioPrivateLibVer2.c  |  81 +++
 .../PeiDxeSmmGpioPrivateLibVer2.inf   |  40 ++
 .../PeiGpioHelpersLib/PeiGpioHelpersLib.c | 218 +++
 .../PeiGpioHelpersLib/PeiGpioHelpersLib.inf   |  46 ++
 20 files changed, 3032 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
new file mode 100644
index 00..a6f8b16d10
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
@@ -0,0 +1,25 @@
+/** @file
+  This file contains definitions of PCIe controller information
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_INFO_H_
+#define _CPU_PCIE_INFO_H_
+
+#define PCIE_HWEQ_COEFFS_MAX5
+
+
+//
+// SA PCI Express* Port configuration
+//
+
+#define CPU_PCIE_MAX_ROOT_PORTS4
+#define CPU_PCIE_MAX_CONTROLLERS   3
+
+#define SA_PEG_MAX_FUN   0x04
+#define SA_PEG_MAX_LANE  0x14
+
+
+
+#en

Re: [edk2-devel] [PATCH 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, 
PcieRp components

Adds the following modules:
  - IpBlock/Graphics/Include
  - IpBlock/Graphics/IncludePrivate
  - IpBlock/Graphics/Library
  - IpBlock/Graphics/LibraryPrivate
  - IpBlock/HostBridge/IncludePrivate
  - IpBlock/PcieRp/Library

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Include/Ppi/GraphicsPlatformPolicyPpi.h   |  76 +++
 .../Library/DxeGraphicsPolicyLib.h|  71 +++
 .../Library/DxeIgdOpRegionInitLib.h   | 115 +
 .../GraphicsInfoLibVer1.c |  52 
 .../GraphicsInfoLibVer1.inf   |  33 +
 .../DxeGraphicsPolicyLib.c| 116 +
 .../DxeGraphicsPolicyLib.inf  |  36 ++
 .../DxeIgdOpRegionInit.c  | 119 ++
 .../DxeIgdOpRegionInitLib.inf |  47 +++
 .../IncludePrivate/HostBridgeDataHob.h|  25 
 .../PchPcieRpLibInternal.h|  20 +++
 .../PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c  |  71 +++
 .../PeiDxeSmmPchPcieRpLibVer2.inf |  37 ++
 13 files changed, 818 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
new file mode 100644
index 00..a8f67061a5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/Gra
+++ phicsPlatformPolicyPpi.h
@@ -0,0 +1,76 @@
+/** @file
+  The PEI_GRAPHICS_PLATFORM_POLICY_PPI provides platform information to PEI 
Graphics PEIM.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+#define _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+
+/**
+  Globally unique identifier for PEI platform policy PPI.
+**/
+#define PEI_GRAPHICS_PLATFORM_POLICY_PPI_GUID \ { \
+  0x4eabcd09, 0x43d3, 0x4b4d, { 0xb7, 0x3d, 0x43, 0xc8, 0xd9, 0x89, 
+0x99, 0x5 } \ }
+
+#define PEI_GRAPHICS_PLATFORM_POLICY_REVISION 1
+
+/**
+Pre-declaration of PEI graphics platform policy PPI.
+**/
+typedef struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI 
+PEI_GRAPHICS_PLATFORM_POLICY_PPI;
+
+/**
+  Enum defining the different lid status values **/ typedef enum {
+  LidClosed,
+  LidOpen,
+  LidStatusMax
+} LID_STATUS;
+
+/**
+  This function gets the platform lid status for LFP displays.
+
+  @param[out] CurrentLidStatus  Output variable to store the lid status.
+
+  @retval EFI_SUCCESS   Correct lid status is returned.
+  @retval EFI_UNSUPPORTED   Platform does not support lid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_PLATFORM_LID_STATUS) (
+  OUT LID_STATUS  *CurrentLidStatus
+  );
+
+/**
+  This function gets the base address of loaded VBT.
+
+  @param[out] VbtAddressStarting address of the VBT is returned in this 
parameter.
+  @param[out] VbtSize   Size of the VBT is returned in this parameter.
+
+  

Re: [edk2-devel] [PATCH 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components

Adds the following modules:
  - IpBlock/P2sb/IncludePrivate
  - IpBlock/P2sb/Library
  - IpBlock/P2sb/LibraryPrivate
  - IpBlock/PchDmi/IncludePrivate
  - IpBlock/PchDmi/LibraryPrivate

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Library/P2SbSidebandAccessLib.h   | 105 +++
 .../IncludePrivate/Library/PchSbiAccessLib.h  |  58 
 .../P2sb/IncludePrivate/P2SbController.h  |  32 +++
 .../P2sb/IncludePrivate/Register/P2sbRegs.h   |  53 
 .../Library/PeiDxeSmmPchPcrLib/PchPcrLib.c| 266 ++
 .../PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf |  35 +++
 .../PeiDxeSmmP2SbSidebandAccessLib.c  | 208 ++
 .../PeiDxeSmmP2SbSidebandAccessLib.inf|  30 ++
 .../PchSbiAccessLib.c |  72 +
 .../PeiDxeSmmPchSbiAccessLib.inf  |  35 +++
 .../PchDmi/IncludePrivate/Library/PchDmiLib.h |  60 
 .../PeiDxeSmmPchDmiLib/PchDmi14.c |  34 +++
 .../PeiDxeSmmPchDmiLib/PchDmi14.h |  22 ++
 .../PeiDxeSmmPchDmiLib/PchDmiLib.c| 110 
 .../PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf |  43 +++
 15 files changed, 1163 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
new file mode 100644
index 00..e364508eb4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Libr
+++ ary/P2SbSidebandAccessLib.h
@@ -0,0 +1,105 @@
+/** @file
+  Header for P2SbSidebandAccessLib
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _P2SB_SIDEBAND_ACCESS_LIB_H_
+#define _P2SB_SIDEBAND_ACCESS_LIB_H_
+
+#include 
+#include 
+#include  // For PCH_SBI_PID definition
+
+typedef PCH_SBI_PID  P2SB_PID;
+
+typedef enum {
+  P2SbMemory = 0,
+  P2SbPciConfig,
+  P2SbPrivateConfig
+} P2SB_REGISTER_SPACE;
+
+typedef enum {
+  MemoryRead = 0x0,
+  MemoryWrite= 0x1,
+  PciConfigRead  = 0x4,
+  PciConfigWrite = 0x5,
+  PrivateControlRead = 0x6,
+  PrivateControlWrite= 0x7,
+  GpioLockUnlock = 0x13
+} P2SB_SBI_OPCODE;
+
+typedef enum {
+  SBI_SUCCESSFUL  = 0,
+  SBI_UNSUCCESSFUL= 1,
+  SBI_POWERDOWN   = 2,
+  SBI_MIXED   = 3,
+  SBI_INVALID_RESPONSE
+} P2SB_SBI_RESPONSE;
+
+typedef enum {
+  P2SbMmioAccess = 0,
+  P2SbMsgAccess
+} P2SB_SIDEBAND_ACCESS_METHOD;
+
+/**
+  REGISTER_ACCESS for P2SB device to support access to sideband registers.
+  Be sure to keep first member of this structure as REGISTER_ACCESS to 
+allow
+  for correct casting between caller who sees this structure as 
+REGISTER_ACCESS
+  and calle who will cast it to P2SB_SIDEBAND_REGI

Re: [edk2-devel] [PATCH] MdeModulePkg/SmbiosDxe: Fix BcdRevision is not match with SMBIOS version

[Michael D Kinney]

Forcing to 0 does not sound right.

You did not answer my question about the property of the global variables.

Without knowing the format of the information in the global variables you
cannot safely use them.  If they are in BCD then no need to check for out
of range.  If they are hex values, then you have to use conversion functions.

Mike

> -Original Message-
> From: Lien, HoraceX 
> Sent: Thursday, September 14, 2023 2:33 AM
> To: Kinney, Michael D ; devel@edk2.groups.io;
> Gao, Liming 
> Cc: Liu, Zhiguang ; Bi, Dandan
> ; Zeng, Star ; Gao, Zhichao
> 
> Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/SmbiosDxe: Fix BcdRevision
> is not match with SMBIOS version
> 
> Hi Mike,
> 
> https://github.com/tianocore/edk2/pull/4771
> I have changed code following rule: It is only accept range 0-9 for Major
> and Minor version to fill in SmbiosBcdRevision, if one of Major or Minor
> is greater than 9 then fill in 00h.
> 
> Please help to review this, thanks :)
> 
> Thanks,
> Horace Lien
> 
> -Original Message-
> From: Lien, HoraceX
> Sent: Friday, September 8, 2023 5:35 PM
> To: Kinney, Michael D ; devel@edk2.groups.io;
> Gao, Liming 
> Cc: Liu, Zhiguang ; Bi, Dandan
> ; Zeng, Star ; Gao, Zhichao
> 
> Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/SmbiosDxe: Fix BcdRevision
> is not match with SMBIOS version
> 
> Hi Mike,
> 
> No, we didn't guarantee this before. Add comments to descript BCD field
> is good point.
> I have reviewed SMBIOS spec for SmbiosBcdRevision field, it mentions "If
> the value is 00h, only the Major and Minor Versions in offsets 6 and 7 of
> the Entry Point Structure provide the version information. ". So, I have
> new idea to implement this, I will filter range 0-9 for Major/Minor
> version to fill in SmbiosBcdRevision, if one of Major or Minor is greater
> than 9 then fill in 00h.
> Do you think it is ok?
> 
> Thanks for your reply.
> 
> Thanks,
> Horace Lien
> 
> -Original Message-
> From: Kinney, Michael D 
> Sent: Friday, September 8, 2023 6:05 AM
> To: Lien, HoraceX ; devel@edk2.groups.io; Gao,
> Liming 
> Cc: Liu, Zhiguang ; Bi, Dandan
> ; Zeng, Star ; Gao, Zhichao
> ; Kinney, Michael D 
> Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/SmbiosDxe: Fix BcdRevision
> is not match with SMBIOS version
> 
> I was asking about the property of the global variables being used in
> this patch.  Are they already guaranteed to be in BSD format and in range
> 0..9.  If so, then no additional code changes would be required.
> However, it would be good to add comments about the properties of those
> global variables and why they can be used to directly assign to fields
> that are required to be in BSD format.
> 
> Mike
> 
> > -Original Message-
> > From: Lien, HoraceX 
> > Sent: Thursday, September 7, 2023 2:41 AM
> > To: devel@edk2.groups.io; Kinney, Michael D
> > ; Gao, Liming 
> > Cc: Liu, Zhiguang ; Bi, Dandan
> > ; Zeng, Star ; Gao, Zhichao
> > ; Lien, HoraceX 
> > Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/SmbiosDxe: Fix
> > BcdRevision is not match with SMBIOS version
> >
> > Hi Mike,
> >
> > Could you please reply for me?
> > If you want to filter range 0-9, then I will send PR again.
> >
> > Thanks,
> > Horace Lien
> >
> > -Original Message-
> > From: devel@edk2.groups.io  On Behalf Of Lien,
> > HoraceX
> > Sent: Friday, September 1, 2023 3:06 PM
> > To: Kinney, Michael D ;
> > devel@edk2.groups.io
> > Cc: Liu, Zhiguang ; Bi, Dandan
> > ; Zeng, Star ; Gao, Zhichao
> > 
> > Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/SmbiosDxe: Fix
> > BcdRevision is not match with SMBIOS version
> >
> > Hi Mike,
> >
> > I have change code to
> > EntryPointStructureData.SmbiosBcdRevision =
> > ((mPrivateData.Smbios.MajorVersion & 0x0f) << 4) |
> > (mPrivateData.Smbios.MinorVersion & 0x0f); Add &0x0F to mask upper
> > nibble bit, do we still need to guarantee that range is between 0-9?
> > Because the old code only filtered 4 bits, instead of accurately
> > filtering the number range 0-9.
> >
> > Thanks,
> > Horace Lien
> >
> > -Original Message-
> > From: Kinney, Michael D 
> > Sent: Thursday, August 31, 2023 11:56 PM
> > To: devel@edk2.groups.io; Lien, HoraceX 
> > Cc: Liu, Zhiguang ; Bi, Dandan
> > ; Zeng, Star ; Gao, Zhichao
> > ; Kinney, Michael D
> > 
> > Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/SmbiosDxe: Fix
> > BcdRevision is not match with SMBIOS version
> >
> > Are mPrivateData.Smbios.MajorVersion and
> > mPrivateData.Smbios.MinorVersion guaranteed to be in range 0..9?
> >
> > Mike
> >
> > > -Original Message-
> > > From: devel@edk2.groups.io  On Behalf Of
> > > horacex.l...@intel.com
> > > Sent: Wednesday, August 30, 2023 2:13 AM
> > > To: devel@edk2.groups.io
> > > Cc: Lien, HoraceX ; Liu, Zhiguang
> > > ; Bi, Dandan ; Zeng,
> > > Star ; Gao, Zhichao 
> > > Subject: [edk2-devel] [PATCH] MdeModulePkg/SmbiosDxe: Fix
> > > BcdRevision is not match with SMBIOS version
> > >
> > > From: HoraceX Lien 
> > >
> > > REF: https://bugzil

Re: [edk2-devel] [PATCH 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components

Adds the following modules:
  - IpBlock/Pmc/IncludePrivate
  - IpBlock/Pmc/Library
  - IpBlock/Pmc/LibraryPrivate
  - IpBlock/Spi/IncludePrivate
  - IpBlock/Spi/Library
  - IpBlock/Spi/LibraryPrivate
  - IpBlock/Spi/Smm

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../IncludePrivate/Library/PmcPrivateLib.h|   47 +
 .../IpBlock/Pmc/IncludePrivate/PmcSocConfig.h |   67 +
 .../PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf   |   38 +
 .../Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c  |   50 +
 .../PeiDxeSmmPmcPrivateLib.inf|   43 +
 .../PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c|   86 ++
 .../Spi/IncludePrivate/Library/SpiCommonLib.h |  376 ++
 .../Spi/IncludePrivate/Register/SpiRegs.h |  116 ++
 .../IpBlock/Spi/Library/PeiSpiLib/PchSpi.c|  209 +++
 .../Spi/Library/PeiSpiLib/PeiSpiLib.inf   |   41 +
 .../BaseSpiCommonLib/BaseSpiCommonLib.inf |   29 +
 .../BaseSpiCommonLib/SpiCommon.c  | 1127 +
 .../AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c |  387 ++
 .../IpBlock/Spi/Smm/SpiSmm.inf|   46 +
 14 files changed, 2662 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
new file mode 100644
index 00..6ec244b127
--- /dev/null
+++ 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
@@ -0,0 +1,47 @@
+/** @file
+  Header file for private PmcLib.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_PRIVATE_LIB_H_
+#define _PMC_PRIVATE_LIB_H_
+
+#include 
+#include "Register/PmcRegs.h"
+
+typedef enum {
+  PmcSwSmiRate1p5ms = 0,
+  PmcSwSmiRate16ms,
+  PmcSwSmiRate32ms,
+  PmcSwSmiRate64ms
+} PMC_SWSMI_RATE;
+
+/**
+  This function sets SW SMI Rate.
+
+  @param[in] SwSmiRateRefer to PMC_SWSMI_RATE for possible values
+**/
+VOID
+PmcSetSwSmiRate (
+  IN PMC_SWSMI_RATE  SwSmiRate
+  );
+
+typedef enum {
+  PmcPeriodicSmiRate8s = 0,
+  PmcPeriodicSmiRate16s,
+  PmcPeriodicSmiRate32s,
+  PmcPeriodicSmiRate64s
+} PMC_PERIODIC_SMI_RATE;
+
+/**
+  This function sets Periodic SMI Rate.
+
+  @param[in] PeriodicSmiRateRefer to PMC_PERIODIC_SMI_RATE for 
possible values
+**/
+VOID
+PmcSetPeriodicSmiRate (
+  IN PMC_PERIODIC_SMI_RATEPeriodicSmiRate
+  );
+
+#endif // _PMC_PRIVATE_LIB_H_
diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
new file mode 100644
index 00..523a84a180
--- /dev/null
+++ 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
@@ -0,0 +1,67 @@
+/** @file
+  PMC SoC configuration
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PMC_SOC_CONFIGURATION_H_
+#define _PMC_SOC_CONFIGURATION_H_
+
+typedef enum {
+  AdrSinglePhase = 0,
+  AdrDualPhase
+} ADR_PHASE_TYPE;
+
+typedef enum {
+  AdrGpioB = 0,
+  AdrGpioC
+} ADR_GPIO;
+
+typedef

Re: [edk2-devel] [PATCH 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi 
Includes

Adds the following Includes:
  - Include/Library
  - Include/Pins
  - Include/Ppi

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Include/Library/ConfigBlockLib.h  |  64 +++
 .../Include/Library/EspiLib.h |  34 ++
 .../Include/Library/GpioConfig.h  | 372 ++
 .../Include/Library/GpioLib.h | 174 
 .../Include/Library/GpioNativeLib.h   | 135 +++
 .../Include/Library/GraphicsInfoLib.h |  46 +++
 .../Include/Library/MmPciLib.h|  27 ++
 .../Include/Library/PchPcieRpLib.h|  41 ++
 .../Include/Library/PchPcrLib.h   | 221 +++
 .../Library/PeiDxeSmmReserveMmio64SizeLib.h   |  21 +
 .../Include/Library/PeiSiPolicyUpdateLib.h| 154 
 .../Include/Library/PmcLib.h  |  40 ++
 .../Include/Library/ResetSystemLib.h  |  68 
 .../Include/Library/SecPlatformLib.h  |  81 
 .../Include/Library/SiConfigBlockLib.h|  56 +++
 .../Include/Library/SiPolicyLib.h |  39 ++
 .../Include/Library/SpiLib.h  |  21 +
 .../Include/Pins/GpioPinsVer2Lp.h |  36 ++
 .../Include/Ppi/FspmArchConfigPpi.h   |  32 ++
 .../Include/Ppi/PeiPreMemSiDefaultPolicy.h|  33 ++
 .../Include/Ppi/PeiSiDefaultPolicy.h  |  33 ++
 .../AlderlakeSiliconPkg/Include/Ppi/Spi.h |  29 ++
 .../AlderlakeSiliconPkg/Include/Ppi/Wdt.h |  22 ++
 23 files changed, 1779 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h

diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h 
b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
new file mode 100644
index 00..d9966c76e9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
@@ -0,0 +1,64 @@
+/** @file
+  Header file for Config Block Lib implementation
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_LIB_H_
+#define _CONFIG_BLOCK_LIB_H_
+
+/**
+  Create config block table
+
+  @param[in] TotalSize- Max size to be allocated for 
the Config Block Table
+  @param[out]ConfigBlockTableAddress  - On return, points to a pointer 
to the beginning of Config Block Table Address
+
+  @retval EFI_INVALID_PARAMETER - Invalid Parameter
+  @retval EFI_OUT_OF_RESOURCES  - Out of resources
+  @retval EFI_SUCCESS   - Successfully created Config Block Table at 
ConfigBlockTableAddress
+**/
+EFI_STATUS
+EFIAPI
+CreateConfigBlockTable (
+  IN UINT16TotalSize,
+  OUTVOID  **ConfigBlockTableAddress
+  );
+
+/**

Re: [edk2-devel] [PATCH 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, 
Other Includes

Adds the following Includes:
  - Include/
  - Include/Protocol
  - Include/Register

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../AlderlakeSiliconPkg/Include/ConfigBlock.h |  53 +++
 .../AlderlakeSiliconPkg/Include/CpuPcieHob.h  |  48 +++
 .../Include/Protocol/IgdOpRegion.h|  22 ++
 .../Include/Protocol/Spi.h| 346 ++
 .../Include/Protocol/Wdt.h| 111 ++
 .../Include/Register/FlashRegs.h  |  73 
 .../Include/Register/GpioRegs.h   | 103 ++
 .../Include/Register/GpioRegsVer2.h   | 211 +++
 .../Include/Register/PchDmi14Regs.h   |  49 +++
 .../Include/Register/PchDmiRegs.h |  51 +++
 .../Include/Register/PchPcieRpRegs.h  |  45 +++
 .../Include/Register/PchRegsLpc.h |  77 
 .../Include/Register/PmcRegs.h| 134 +++
 .../Include/Register/RtcRegs.h|  44 +++
 .../Include/Register/TcoRegs.h|  71 
 .../Include/SerialIoDevices.h | 226 
 .../AlderlakeSiliconPkg/Include/SiConfigHob.h |  17 +
 .../Include/SiPolicyStruct.h  |  64 
 18 files changed, 1745 insertions(+)
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h

diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h 
b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
new file mode 100644
index 00..2e609bc8d9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
@@ -0,0 +1,53 @@
+/** @file
+  Header file for Config Block Lib implementation
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_H_
+#define _CONFIG_BLOCK_H_
+
+#include 
+#include 
+#include 
+#include 
+
+#pragma pack (push,1)
+
+///
+/// Config Block Header
+///
+typedef struct _CONFIG_BLOCK_HEADER {
+  EFI_HOB_GUID_TYPE GuidHob;  ///< Offset 0-23  GUID 
extension HOB header
+  UINT8 Revision; ///< Offset 24Revision 
of this config block
+  UINT8 Attributes;   ///< Offset 25The main 
revision for config block
+  UINT8 Reserved[2];  ///< Offset 26-27 Reserved 
for future use
+} CONFIG_BLOCK_HEADER;
+
+///
+/// Config Block
+///
+typedef struct _CONFIG_BLOCK {
+  CONFIG_BLOCK_HEADERHeader;  ///< Offset 0-27  Header of 
config block
+  //
+  // Config Block Data
+  //
+} CONFIG_BLOCK;
+
+///
+/// Config Block Table Header
+///
+typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
+  CONFIG_BLOCK_HEADERHeader;  ///< Offset 0-27  GUID 
number for main entry of config block
+  UINT8  Rsvd0[2];///< Offset 28-29 Reserved 
for future use
+  UINT16 NumberOfBlocks;  ///< Offset 30-31 Number of 
config blocks (N)
+  UINT32 AvailableSize;   ///< Offset 32-35 Current 
config block table size
+///
+/// Individual Config Block Structures are added here in memory as part of 
AddConfigBlock()
+///
+} CONFIG_BLOCK_TABLE_HEADER;
+#pragma

Re: [edk2-devel] [PATCH 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate 
modules

Adds the following modules:
  - AdlPch/Include
  - AdlPch/IncludePrivate
  - AdlPch/Library
  - AdlPch DSCs
  - IncludePrivate

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Fru/AdlPch/CommonLib.dsc  |  29 ++
 .../AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc|  10 +
 .../AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc |   7 +
 .../Fru/AdlPch/Include/PchBdfAssignment.h |  81 +
 .../Fru/AdlPch/Include/PchLimits.h|  47 +++
 .../Fru/AdlPch/Include/PchPcieRpInfo.h|  17 ++
 .../Fru/AdlPch/Include/PchReservedResources.h |  13 +  
.../AdlPch/Include/PchReservedResourcesAdpP.h |  36 +++
 .../IncludePrivate/Register/PchPcrRegs.h  |  59 
 .../IncludePrivate/Register/PchRegsLpcAdl.h   |  30 ++
 .../PeiDxeSmmPchInfoLib/PchInfoLibAdl.c   | 223 ++
 .../PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h   |  44 +++
 .../PeiDxeSmmPchInfoLibAdl.inf|  37 +++
 .../AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc|   7 +
 .../AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc |  12 +
 .../IncludePrivate/RegisterAccess.h   | 288 ++
 16 files changed, 940 insertions(+)
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h

diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc 
b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
new file mode 100644
index 00..3f508f83a1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
@@ -0,0 +1,29 @@
+## @file
+#  Component description file for the AlderLake PCH Common FRU libraries.
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+  
+ PchPcrLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/Library/PeiDxeSmmPchPcrL
+ ib/PeiDxeSmmPchPcrLib.inf  
+ PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPrivate/Pei
+ DxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
+  
+ P2SbSidebandAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPriva
+ te/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
+
+  
+ EspiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Espi/Library/PeiDxeSmmEspiLib/P
+ eiDxeSmmEspiLib.inf
+
+
+  
+ PmcLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiD
+ xeSmmPmcLib.inf  
+ PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/LibraryPrivate/PeiDxe
+ SmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
+  
+ SpiCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/LibraryPrivate/BaseSpi
+ CommonLib/BaseSpiCommonLib.inf  
+ GpioLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/P
+ eiDxeSmmGpioLib.inf  
+ PchDmiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PchDmi/LibraryPrivate/PeiDxeS
+ mmPchDmiLib/PeiDxeSmmPchDmiLib.inf
+
+  
+ GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiD
+ xeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
+  
+ PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/Library/PeiDxeSmmPc
+ hPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
+
+
+  #
+  # Common FRU Libraries
+  #
+  
+ PchInfoLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlPch/Library/PeiDxeSmmPchInfoL
+ ib/PeiDxeSmmPchInfoLibAdl.inf
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc 
b/Silicon/Intel/Alderla

Re: [edk2-devel] [PATCH 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec

Adds the following modules:
  - Product/Alderlake/Include
  - Product/Alderlake/Library
  - Product/Alderlake DSCs
  - SiPkg.dec

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Product/Alderlake/Include/Ppi/SiPolicy.h  |  55 ++
 .../Library/PeiSiPolicyLib/PeiSiPolicyLib.c   |  47 ++
 .../Library/PeiSiPolicyLib/PeiSiPolicyLib.inf |  47 ++
 .../PeiSiPolicyLib/PeiSiPolicyLibPreMem.c |  47 ++
 .../PeiSiPolicyLib/PeiSiPolicyLibrary.h   |  21 +
 .../Product/Alderlake/SiPkgBuildOption.dsc| 122 
 .../Product/Alderlake/SiPkgCommonLib.dsc  |  36 +
 .../Product/Alderlake/SiPkgDxe.dsc|  32 +
 .../Product/Alderlake/SiPkgDxeLib.dsc |  23 +
 .../Product/Alderlake/SiPkgPeiLib.dsc |  19 +
 Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec   | 625 ++
 11 files changed, 1074 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h 
b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
new file mode 100644
index 00..703f0221bd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/Si
+++ Policy.h
@@ -0,0 +1,55 @@
+/** @file
+  Silicon Policy PPI is used for specifying platform
+  related Intel silicon information and policy setting.
+  This PPI is consumed by the silicon PEI modules and carried
+  over to silicon DXE modules.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _SI_POLICY_PPI_H_
+#define _SI_POLICY_PPI_H_
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifndef DISABLED
+#define DISABLED  0
+#endif
+#ifndef ENABLED
+#define ENABLED   1
+#endif
+
+extern EFI_GUID gSiPreMemPolicyPpiGuid; extern EFI_GUID 
+gSiPolicyPpiGuid;
+
+
+#include 
+
+
+#include 
+#include 
+extern EFI_GUID gCpuPciePeiPreMemConfigGuid; extern EFI_GUID 
+gCpuPcieRpConfigGuid;
+
+#include 
+extern EFI_GUID gMemoryConfigGuid;
+extern EFI_GUID gMemoryConfigNoCrcGuid;
+
+#include 
+extern EFI_GUID gSaMiscPeiPreMemConfigGuid;
+
+#include 
+extern EFI_GUID gHostBridgePeiPreMemConfigGuid; extern EFI_GUID 
+gHostBridgePeiConfigGuid;
+
+typedef struct _SI_PREMEM_POLICY_STRUCT SI_PREMEM_POLICY_PPI; typedef 
+struct _SI_POLICY_STRUCT SI_POLICY_PPI;
+
+#endif // _SI_POLICY_PPI_H_
diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
 
b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
new file mode 100644
index 00..886415bdaa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiP
+++ olicyLib/PeiSiPolicyLib.c
@@ -0,0 +1,47 @@
+/** @file
+  This file is PeiSiPolicyLib library creates default settings of RC
+  Policy and installs RC Policy PPI.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include 
+"PeiSiPolicyLibrary.h"
+#include 
+#include 
+
+
+/**
+  SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+  While installed, RC assumes the Policy is ready and finalized. So 
+please update and override
+  any setting before calling this function.
+
+  @retval EFI_SUCCESSThe policy is installed.
+  @retval EFI_OUT_OF_RESOURCES   Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+  VOID
+  )
+{
+  EFI_STATUS Status;
+  EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPpiDesc;
+
+  SiPolicyReadyPpiDesc = (EFI_PEI_PPI_

[edk2-devel] [PATCH v2 1/2] StandaloneMmPkg: Make StandaloneMmCpu driver platform independent

[Tuan Phan]

StandaloneMmCpu now can supports more platforms like RISC-V besides
ARM/AARCH64.

Signed-off-by: Tuan Phan 
---
 .../Drivers/StandaloneMmCpu/EventHandle.c | 25 +++
 .../Drivers/StandaloneMmCpu/StandaloneMmCpu.c | 42 +--
 .../StandaloneMmCpu/StandaloneMmCpu.inf   |  9 ++--
 .../StandaloneMmCpu.h | 22 +++---
 StandaloneMmPkg/StandaloneMmPkg.dec   |  2 +-
 5 files changed, 46 insertions(+), 54 deletions(-)
 rename StandaloneMmPkg/{Drivers/StandaloneMmCpu => Include}/StandaloneMmCpu.h 
(82%)

diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c 
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
index 818e147f874c..dc11d4375a02 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
@@ -3,6 +3,7 @@
   Copyright (c) 2016 HP Development Company, L.P.
   Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.
   Copyright (c) 2021, Linaro Limited
+  Copyright (c) 2023, Ventana Micro System Inc. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -11,8 +12,6 @@
 #include 
 #include 
 
-#include 
-#include 
 #include 
 #include 
 #include 
@@ -22,10 +21,7 @@
 #include 
 #include 
 
-#include 
-#include 
-
-#include "StandaloneMmCpu.h"
+#include 
 
 EFI_STATUS
 EFIAPI
@@ -108,7 +104,7 @@ CheckBufferAddr (
 }
 
 /**
-  The PI Standalone MM entry point for the TF-A CPU driver.
+  The PI Standalone MM entry point for the CPU driver.
 
   @param  [in] EventIdThe event Id.
   @param  [in] CpuNumber  The CPU number.
@@ -121,7 +117,7 @@ CheckBufferAddr (
   @retval   EFI_UNSUPPORTED Operation not supported.
 **/
 EFI_STATUS
-PiMmStandaloneArmTfCpuDriverEntry (
+PiMmStandaloneMmCpuDriverEntry (
   IN UINTN  EventId,
   IN UINTN  CpuNumber,
   IN UINTN  NsCommBufferAddr
@@ -135,17 +131,6 @@ PiMmStandaloneArmTfCpuDriverEntry (
   DEBUG ((DEBUG_INFO, "Received event - 0x%x on cpu %d\n", EventId, 
CpuNumber));
 
   Status = EFI_SUCCESS;
-  //
-  // ARM TF passes SMC FID of the MM_COMMUNICATE interface as the Event ID upon
-  // receipt of a synchronous MM request. Use the Event ID to distinguish
-  // between synchronous and asynchronous events.
-  //
-  if ((ARM_SMC_ID_MM_COMMUNICATE != EventId) &&
-  (ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ != EventId))
-  {
-DEBUG ((DEBUG_ERROR, "UnRecognized Event - 0x%x\n", EventId));
-return EFI_INVALID_PARAMETER;
-  }
 
   // Perform parameter validation of NsCommBufferAddr
   if (NsCommBufferAddr == (UINTN)NULL) {
@@ -177,7 +162,7 @@ PiMmStandaloneArmTfCpuDriverEntry (
   }
 
   // X1 contains the VA of the normal world memory accessible from
-  // S-EL0
+  // secure world.
   CopyMem (GuidedEventContext, (CONST VOID *)NsCommBufferAddr, 
NsCommBufferSize);
 
   // Stash the pointer to the allocated Event Context for this CPU
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c 
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
index 3d1dc6181bd9..c5ec1a5a80c5 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
@@ -3,6 +3,7 @@
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
   Copyright (c) 2016 HP Development Company, L.P.
   Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.
+  Copyright (c) 2023, Ventana Micro System Inc. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -10,10 +11,7 @@
 
 #include 
 #include 
-#include 
 #include 
-#include 
-#include 
 #include 
 #include 
 
@@ -22,7 +20,7 @@
 #include 
 #include 
 
-#include "StandaloneMmCpu.h"
+#include 
 
 // GUID to identify HOB with whereabouts of communication buffer with Normal
 // World
@@ -31,7 +29,7 @@ extern EFI_GUID  gEfiStandaloneMmNonSecureBufferGuid;
 // GUID to identify HOB where the entry point of this CPU driver will be
 // populated to allow the entry point driver to invoke it upon receipt of an
 // event
-extern EFI_GUID  gEfiArmTfCpuDriverEpDescriptorGuid;
+extern EFI_GUID  gEfiMmCpuDriverEpDescriptorGuid;
 
 //
 // Private copy of the MM system table for future use
@@ -96,17 +94,17 @@ StandaloneMmCpuInitialize (
   IN EFI_MM_SYSTEM_TABLE  *SystemTable   // not actual systemtable
   )
 {
-  ARM_TF_CPU_DRIVER_EP_DESCRIPTOR  *CpuDriverEntryPointDesc;
-  EFI_CONFIGURATION_TABLE  *ConfigurationTable;
-  MP_INFORMATION_HOB_DATA  *MpInformationHobData;
-  EFI_MMRAM_DESCRIPTOR *NsCommBufMmramRange;
-  EFI_STATUS   Status;
-  EFI_HANDLE   DispatchHandle;
-  UINT32   MpInfoSize;
-  UINTNIndex;
-  UINTNArraySize;
-  VOID *HobStart;
-  EFI_MMRAM_HOB_DESCRIPTOR_BLOCK   *MmramRangesHob;
+  MM_CPU_DRIVER_EP_DESCRIPTOR *CpuDriverEntryPointDesc;
+  EFI_CONFIGURATION_TABLE

[edk2-devel] [PATCH v2 2/2] StandaloneMmPkg: Arm: Update to use the new StandaloneMmCpu driver

[Tuan Phan]

Update entry point library for Arm to use the new platform independent
StandaloneMmCpu driver.

Signed-off-by: Tuan Phan 
---
 .../Library/Arm/StandaloneMmCoreEntryPoint.h  | 17 ++--
 .../Arm/CreateHobList.c   | 43 ++-
 .../Arm/StandaloneMmCoreEntryPoint.c  | 15 ++-
 .../StandaloneMmCoreEntryPoint.inf|  2 +-
 4 files changed, 40 insertions(+), 37 deletions(-)

diff --git a/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h 
b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
index 41bf0f132b4f..dbb81610ff8e 100644
--- a/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
+++ b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
@@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #ifndef __STANDALONEMMCORE_ENTRY_POINT_H__
 #define __STANDALONEMMCORE_ENTRY_POINT_H__
 
+#include 
 #include 
 #include 
 
@@ -47,18 +48,6 @@ typedef struct {
   EFI_SECURE_PARTITION_CPU_INFO*CpuInfo;
 } EFI_SECURE_PARTITION_BOOT_INFO;
 
-typedef
-EFI_STATUS
-(*PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT) (
-  IN UINTN  EventId,
-  IN UINTN  CpuNumber,
-  IN UINTN  NsCommBufferAddr
-  );
-
-typedef struct {
-  PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT*ArmTfCpuDriverEpPtr;
-} ARM_TF_CPU_DRIVER_EP_DESCRIPTOR;
-
 typedef RETURN_STATUS (*REGION_PERMISSION_UPDATE_FUNC) (
   IN  EFI_PHYSICAL_ADDRESS  BaseAddress,
   IN  UINT64Length
@@ -145,8 +134,8 @@ LocateStandaloneMmCorePeCoffData (
 VOID *
 EFIAPI
 CreateHobListFromBootInfo (
-  IN  OUT  PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT  *CpuDriverEntryPoint,
-  IN   EFI_SECURE_PARTITION_BOOT_INFO  *PayloadBootInfo
+  IN  OUT  PI_MM_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
+  IN   EFI_SECURE_PARTITION_BOOT_INFO  *PayloadBootInfo
   );
 
 /**
diff --git 
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c 
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
index 2ac2d354f06a..80ed532352af 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
@@ -13,6 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include 
 #include 
 
+#include 
 #include 
 #include 
 #include 
@@ -39,7 +40,7 @@ extern EFI_GUID  gEfiStandaloneMmNonSecureBufferGuid;
 // GUID to identify HOB where the entry point of the CPU driver will be
 // populated to allow this entry point driver to invoke it upon receipt of an
 // event
-extern EFI_GUID  gEfiArmTfCpuDriverEpDescriptorGuid;
+extern EFI_GUID  gEfiMmCpuDriverEpDescriptorGuid;
 
 /**
   Use the boot information passed by privileged firmware to populate a HOB list
@@ -52,22 +53,22 @@ extern EFI_GUID  gEfiArmTfCpuDriverEpDescriptorGuid;
 **/
 VOID *
 CreateHobListFromBootInfo (
-  IN  OUT  PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT  *CpuDriverEntryPoint,
-  IN   EFI_SECURE_PARTITION_BOOT_INFO  *PayloadBootInfo
+  IN  OUT  PI_MM_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
+  IN   EFI_SECURE_PARTITION_BOOT_INFO  *PayloadBootInfo
   )
 {
-  EFI_HOB_HANDOFF_INFO_TABLE   *HobStart;
-  EFI_RESOURCE_ATTRIBUTE_TYPE  Attributes;
-  UINT32   Index;
-  UINT32   BufferSize;
-  UINT32   Flags;
-  EFI_MMRAM_HOB_DESCRIPTOR_BLOCK   *MmramRangesHob;
-  EFI_MMRAM_DESCRIPTOR *MmramRanges;
-  EFI_MMRAM_DESCRIPTOR *NsCommBufMmramRange;
-  MP_INFORMATION_HOB_DATA  *MpInformationHobData;
-  EFI_PROCESSOR_INFORMATION*ProcInfoBuffer;
-  EFI_SECURE_PARTITION_CPU_INFO*CpuInfo;
-  ARM_TF_CPU_DRIVER_EP_DESCRIPTOR  *CpuDriverEntryPointDesc;
+  EFI_HOB_HANDOFF_INFO_TABLE  *HobStart;
+  EFI_RESOURCE_ATTRIBUTE_TYPE Attributes;
+  UINT32  Index;
+  UINT32  BufferSize;
+  UINT32  Flags;
+  EFI_MMRAM_HOB_DESCRIPTOR_BLOCK  *MmramRangesHob;
+  EFI_MMRAM_DESCRIPTOR*MmramRanges;
+  EFI_MMRAM_DESCRIPTOR*NsCommBufMmramRange;
+  MP_INFORMATION_HOB_DATA *MpInformationHobData;
+  EFI_PROCESSOR_INFORMATION   *ProcInfoBuffer;
+  EFI_SECURE_PARTITION_CPU_INFO   *CpuInfo;
+  MM_CPU_DRIVER_EP_DESCRIPTOR *CpuDriverEntryPointDesc;
 
   // Create a hoblist with a PHIT and EOH
   HobStart = HobConstructor (
@@ -144,13 +145,13 @@ CreateHobListFromBootInfo (
 
   // Create a Guided HOB to enable the ARM TF CPU driver to share its entry
   // point and populate it with the address of the shared buffer
-  CpuDriverEntryPointDesc = (ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *)BuildGuidHob (
- 
&gEfiArmTfCpuDriverEpDescriptorGuid,
- sizeof 
(ARM_TF_CPU_DRIVER_EP_DESCRIPTOR)
- );
+  CpuDriverEntryPointDesc

[edk2-devel] [PATCH v2 0/2] StandaloneMmPkg: Make StandaloneMmCpu platform

[Tuan Phan]

This series makes StandaloneMmCpu platform independent so that
other platforms besides ARM/AARCH64 can use it without creating
new driver.

There are two parts in this series:
1. Remove ARM/AARCH64 code from StandaloneMmCpu.
2. Update ARM/AARCH64 entry point library code.

Tuan Phan (2):
  StandaloneMmPkg: Make StandaloneMmCpu driver platform independent
  StandaloneMmPkg: Arm: Update to use the new StandaloneMmCpu driver

 .../Drivers/StandaloneMmCpu/EventHandle.c | 25 +++
 .../Drivers/StandaloneMmCpu/StandaloneMmCpu.c | 42 +-
 .../StandaloneMmCpu/StandaloneMmCpu.inf   |  9 ++--
 .../Library/Arm/StandaloneMmCoreEntryPoint.h  | 17 ++--
 .../StandaloneMmCpu.h | 22 +++---
 .../Arm/CreateHobList.c   | 43 ++-
 .../Arm/StandaloneMmCoreEntryPoint.c  | 15 ++-
 .../StandaloneMmCoreEntryPoint.inf|  2 +-
 StandaloneMmPkg/StandaloneMmPkg.dec   |  2 +-
 9 files changed, 86 insertions(+), 91 deletions(-)
 rename StandaloneMmPkg/{Drivers/StandaloneMmCpu => Include}/StandaloneMmCpu.h 
(82%)

-- 
2.25.1



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Re: [edk2-devel] [PATCH 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components

[Chuang, Rosen]

Reviewed-by: Rosen Chuang 

-Original Message-
From: Chaganty, Rangasai V  
Sent: Friday, September 15, 2023 12:02 AM
To: Kasbekar, Saloni ; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Chuang, Rosen 

Subject: RE: [PATCH 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, 
Gpio components

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio 
components

Adds the following modules:
  - IpBlock/CpuPcieRp/Include
  - IpBlock/Espi/Library
  - IpBlock/Gpio/IncludePrivate
  - IpBlock/Gpio/Library
  - IpBlock/Gpio/LibraryPrivate

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../IpBlock/CpuPcieRp/Include/CpuPcieInfo.h   |  25 +
 .../Espi/Library/PeiDxeSmmEspiLib/EspiLib.c   |  58 ++
 .../PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf |  38 ++
 .../IncludePrivate/Library/GpioHelpersLib.h   |  50 ++
 .../IncludePrivate/Library/GpioNativePads.h   | 245 
 .../IncludePrivate/Library/GpioPrivateLib.h   | 350 +++
 .../Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c  | 546 ++
 .../Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c   | 522 +
 .../Library/PeiDxeSmmGpioLib/GpioLibrary.h|  29 +
 .../Library/PeiDxeSmmGpioLib/GpioNativeLib.c  | 177 ++
 .../PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf |  44 ++
 .../BaseGpioHelpersLibNull.c  |  51 ++
 .../BaseGpioHelpersLibNull.inf|  25 +
 .../GpioNativePrivateLibInternal.h|  48 ++
 .../PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c  | 267 +
 .../GpioPrivateLibPch.c   | 172 ++
 .../GpioPrivateLibVer2.c  |  81 +++
 .../PeiDxeSmmGpioPrivateLibVer2.inf   |  40 ++
 .../PeiGpioHelpersLib/PeiGpioHelpersLib.c | 218 +++
 .../PeiGpioHelpersLib/PeiGpioHelpersLib.inf   |  46 ++
 20 files changed, 3032 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
new file mode 100644
index 00..a6f8b16d10
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
@@ -0,0 +1,25 @@
+/** @file
+  This file contains definitions of PCIe controller information
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCI

Re: [edk2-devel] [PATCH 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components

[Chuang, Rosen]

Reviewed-by: Rosen Chuang 
-Original Message-
From: Chaganty, Rangasai V  
Sent: Friday, September 15, 2023 1:24 AM
To: Kasbekar, Saloni ; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Chuang, Rosen 

Subject: RE: [PATCH 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, 
HostBridge, PcieRp components

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni 
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, 
PcieRp components

Adds the following modules:
  - IpBlock/Graphics/Include
  - IpBlock/Graphics/IncludePrivate
  - IpBlock/Graphics/Library
  - IpBlock/Graphics/LibraryPrivate
  - IpBlock/HostBridge/IncludePrivate
  - IpBlock/PcieRp/Library

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Include/Ppi/GraphicsPlatformPolicyPpi.h   |  76 +++
 .../Library/DxeGraphicsPolicyLib.h|  71 +++
 .../Library/DxeIgdOpRegionInitLib.h   | 115 +
 .../GraphicsInfoLibVer1.c |  52 
 .../GraphicsInfoLibVer1.inf   |  33 +
 .../DxeGraphicsPolicyLib.c| 116 +
 .../DxeGraphicsPolicyLib.inf  |  36 ++
 .../DxeIgdOpRegionInit.c  | 119 ++
 .../DxeIgdOpRegionInitLib.inf |  47 +++
 .../IncludePrivate/HostBridgeDataHob.h|  25 
 .../PchPcieRpLibInternal.h|  20 +++
 .../PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c  |  71 +++
 .../PeiDxeSmmPchPcieRpLibVer2.inf |  37 ++
 13 files changed, 818 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
new file mode 100644
index 00..a8f67061a5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/Gra
+++ phicsPlatformPolicyPpi.h
@@ -0,0 +1,76 @@
+/** @file
+  The PEI_GRAPHICS_PLATFORM_POLICY_PPI provides platform information to PEI 
Graphics PEIM.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+#define _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+
+/**
+  Globally unique identifier for PEI platform policy PPI.
+**/
+#define PEI_GRAPHICS_PLATFORM_POLICY_PPI_GUID \ { \
+  0x4eabcd09, 0x43d3, 0x4b4d, { 0xb7, 0x3d, 0x43, 0xc8, 0xd9, 0x89, 
+0x99, 0x5 } \ }
+
+#define PEI_GRAPHICS_PLATFORM_POLICY_REVISION 1
+
+/**
+Pre-declaration of PEI graphics platform policy PPI.
+**/
+typedef struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI 
+PEI_GRAPHICS_PLATFORM_POLICY_PPI;
+
+/**
+  Enum defining the different lid status values **/ typedef enum {
+  LidClosed,
+  LidOpen,
+  LidStatusMax
+} LID_STATUS;
+
+/**
+  This function gets the platform lid status for LFP displays.
+
+  @param[out] CurrentLidStatus  Output variable to store the lid status.
+
+  @retval EFI_SUCCESS   Correct lid status is returned.
+  @retval EFI_UNSUPPORTED   Platform does not support lid.
+**/
+typedef
+EFI_STATUS

Re: [edk2-devel] [PATCH 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components

[Chuang, Rosen]

Reviewed-by: Rosen Chuang 

-Original Message-
From: Chaganty, Rangasai V  
Sent: Friday, September 15, 2023 1:41 AM
To: Kasbekar, Saloni ; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Chuang, Rosen 

Subject: RE: [PATCH 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi 
components

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni 
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components

Adds the following modules:
  - IpBlock/P2sb/IncludePrivate
  - IpBlock/P2sb/Library
  - IpBlock/P2sb/LibraryPrivate
  - IpBlock/PchDmi/IncludePrivate
  - IpBlock/PchDmi/LibraryPrivate

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Library/P2SbSidebandAccessLib.h   | 105 +++
 .../IncludePrivate/Library/PchSbiAccessLib.h  |  58 
 .../P2sb/IncludePrivate/P2SbController.h  |  32 +++
 .../P2sb/IncludePrivate/Register/P2sbRegs.h   |  53 
 .../Library/PeiDxeSmmPchPcrLib/PchPcrLib.c| 266 ++
 .../PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf |  35 +++
 .../PeiDxeSmmP2SbSidebandAccessLib.c  | 208 ++
 .../PeiDxeSmmP2SbSidebandAccessLib.inf|  30 ++
 .../PchSbiAccessLib.c |  72 +
 .../PeiDxeSmmPchSbiAccessLib.inf  |  35 +++
 .../PchDmi/IncludePrivate/Library/PchDmiLib.h |  60 
 .../PeiDxeSmmPchDmiLib/PchDmi14.c |  34 +++
 .../PeiDxeSmmPchDmiLib/PchDmi14.h |  22 ++
 .../PeiDxeSmmPchDmiLib/PchDmiLib.c| 110 
 .../PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf |  43 +++
 15 files changed, 1163 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
new file mode 100644
index 00..e364508eb4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Libr
+++ ary/P2SbSidebandAccessLib.h
@@ -0,0 +1,105 @@
+/** @file
+  Header for P2SbSidebandAccessLib
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _P2SB_SIDEBAND_ACCESS_LIB_H_
+#define _P2SB_SIDEBAND_ACCESS_LIB_H_
+
+#include 
+#include 
+#include  // For PCH_SBI_PID definition
+
+typedef PCH_SBI_PID  P2SB_PID;
+
+typedef enum {
+  P2SbMemory = 0,
+  P2SbPciConfig,
+  P2SbPrivateConfig
+} P2SB_REGISTER_SPACE;
+
+typedef enum {
+  MemoryRead = 0x0,
+  MemoryWrite= 0x1,
+  PciConfigRead  = 0x4,
+  PciConfigWrite = 0x5,
+  PrivateControlRead = 0x6,
+  PrivateControlWrite= 0x7,
+  GpioLockUnlock = 0x13
+} P2SB_SBI_OPCODE;
+
+typedef enum {
+  SBI_SUCCESSFUL  = 0,
+  SBI_UNSUCCESSFUL= 1,
+  SBI_POWERDOWN   = 2,
+  SBI_MIXED   = 3,
+  SBI_INVALID_RESPONSE
+} P2SB_SBI_RESPONSE;
+
+typedef enum {
+  P2SbMmioAccess = 0,
+  P2SbMsgAccess
+} P2SB_SIDEBAND_ACCESS_METHOD;

Re: [edk2-devel] [PATCH 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components

[Chuang, Rosen]

Reviewed-by: Rosen Chuang 


-Original Message-
From: Chaganty, Rangasai V  
Sent: Friday, September 15, 2023 5:40 AM
To: Kasbekar, Saloni ; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Chuang, Rosen 

Subject: RE: [PATCH 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components

Adds the following modules:
  - IpBlock/Pmc/IncludePrivate
  - IpBlock/Pmc/Library
  - IpBlock/Pmc/LibraryPrivate
  - IpBlock/Spi/IncludePrivate
  - IpBlock/Spi/Library
  - IpBlock/Spi/LibraryPrivate
  - IpBlock/Spi/Smm

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../IncludePrivate/Library/PmcPrivateLib.h|   47 +
 .../IpBlock/Pmc/IncludePrivate/PmcSocConfig.h |   67 +
 .../PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf   |   38 +
 .../Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c  |   50 +
 .../PeiDxeSmmPmcPrivateLib.inf|   43 +
 .../PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c|   86 ++
 .../Spi/IncludePrivate/Library/SpiCommonLib.h |  376 ++
 .../Spi/IncludePrivate/Register/SpiRegs.h |  116 ++
 .../IpBlock/Spi/Library/PeiSpiLib/PchSpi.c|  209 +++
 .../Spi/Library/PeiSpiLib/PeiSpiLib.inf   |   41 +
 .../BaseSpiCommonLib/BaseSpiCommonLib.inf |   29 +
 .../BaseSpiCommonLib/SpiCommon.c  | 1127 +
 .../AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c |  387 ++
 .../IpBlock/Spi/Smm/SpiSmm.inf|   46 +
 14 files changed, 2662 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
new file mode 100644
index 00..6ec244b127
--- /dev/null
+++ 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
@@ -0,0 +1,47 @@
+/** @file
+  Header file for private PmcLib.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_PRIVATE_LIB_H_
+#define _PMC_PRIVATE_LIB_H_
+
+#include 
+#include "Register/PmcRegs.h"
+
+typedef enum {
+  PmcSwSmiRate1p5ms = 0,
+  PmcSwSmiRate16ms,
+  PmcSwSmiRate32ms,
+  PmcSwSmiRate64ms
+} PMC_SWSMI_RATE;
+
+/**
+  This function sets SW SMI Rate.
+
+  @param[in] SwSmiRateRefer to PMC_SWSMI_RATE for possible values
+**/
+VOID
+PmcSetSwSmiRate (
+  IN PMC_SWSMI_RATE  SwSmiRate
+  );
+
+typedef enum {
+  PmcPeriodicSmiRate8s = 0,
+  PmcPeriodicSmiRate16s,
+  PmcPeriodicSmiRate32s,
+  PmcPeriodicSmiRate64s
+} PMC_PERIODIC_SMI_RATE;
+
+/**
+  This function sets Periodic SMI Rate.
+
+  @param[in] PeriodicSmiRateRefer to PMC_PERIODIC_SMI_RATE for 
possible values
+**/
+VOID
+PmcSetPeriodicSmiRate (
+  IN PMC_PERIODIC_SMI_RATEPeriodicSmiRate
+  );
+
+#endif // _PMC_PRIVATE_LIB_H_
diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
new file mode 100644
index 00..523a84a180
--- /dev/null
+++ 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
@@ -0,0 +1,67 @@
+/** @file
+  PMC SoC configuration
+
+   Copyright (c) 2022, Intel Corporation

Re: [edk2-devel] [PATCH 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes

[Chuang, Rosen]

Reviewed-by: Rosen Chuang 


-Original Message-
From: Kasbekar, Saloni  
Sent: Thursday, September 14, 2023 6:14 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi 
Includes

Adds the following Includes:
  - Include/Library
  - Include/Pins
  - Include/Ppi

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Include/Library/ConfigBlockLib.h  |  64 +++
 .../Include/Library/EspiLib.h |  34 ++
 .../Include/Library/GpioConfig.h  | 372 ++
 .../Include/Library/GpioLib.h | 174 
 .../Include/Library/GpioNativeLib.h   | 135 +++
 .../Include/Library/GraphicsInfoLib.h |  46 +++
 .../Include/Library/MmPciLib.h|  27 ++
 .../Include/Library/PchPcieRpLib.h|  41 ++
 .../Include/Library/PchPcrLib.h   | 221 +++
 .../Library/PeiDxeSmmReserveMmio64SizeLib.h   |  21 +
 .../Include/Library/PeiSiPolicyUpdateLib.h| 154 
 .../Include/Library/PmcLib.h  |  40 ++
 .../Include/Library/ResetSystemLib.h  |  68 
 .../Include/Library/SecPlatformLib.h  |  81 
 .../Include/Library/SiConfigBlockLib.h|  56 +++
 .../Include/Library/SiPolicyLib.h |  39 ++
 .../Include/Library/SpiLib.h  |  21 +
 .../Include/Pins/GpioPinsVer2Lp.h |  36 ++
 .../Include/Ppi/FspmArchConfigPpi.h   |  32 ++
 .../Include/Ppi/PeiPreMemSiDefaultPolicy.h|  33 ++
 .../Include/Ppi/PeiSiDefaultPolicy.h  |  33 ++
 .../AlderlakeSiliconPkg/Include/Ppi/Spi.h |  29 ++
 .../AlderlakeSiliconPkg/Include/Ppi/Wdt.h |  22 ++
 23 files changed, 1779 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h

diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h 
b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
new file mode 100644
index 00..d9966c76e9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
@@ -0,0 +1,64 @@
+/** @file
+  Header file for Config Block Lib implementation
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_LIB_H_
+#define _CONFIG_BLOCK_LIB_H_
+
+/**
+  Create config block table
+
+  @param[in] TotalSize- Max size to be allocated for 
the Config Block Table
+  @param[out]ConfigBlockTableAddress  - On return, points to a pointer 
to the beginning of Config Block Table Address
+
+  @retval EFI_INVALID_PARAMETER - Invalid Parameter
+  @retval EFI_OUT_OF_RESOURCES  - Out of resources
+  @retval EFI_SUCCESS   - Successfully created Config Block Table at 
ConfigBlockTableAddress
+**/
+EFI_STATUS
+EFIAPI
+CreateConfigBlockTable (
+  IN UINT16TotalSize,
+  OUTVOID  **ConfigBlockTableAddress
+  );
+
+/**

Re: [edk2-devel] [PATCH 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes

[Chuang, Rosen]

Reviewed-by: Rosen Chuang 

-Original Message-
From: Chaganty, Rangasai V  
Sent: Friday, September 15, 2023 6:02 AM
To: Kasbekar, Saloni ; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Chuang, Rosen 

Subject: RE: [PATCH 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, 
Other Includes

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, 
Other Includes

Adds the following Includes:
  - Include/
  - Include/Protocol
  - Include/Register

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../AlderlakeSiliconPkg/Include/ConfigBlock.h |  53 +++
 .../AlderlakeSiliconPkg/Include/CpuPcieHob.h  |  48 +++
 .../Include/Protocol/IgdOpRegion.h|  22 ++
 .../Include/Protocol/Spi.h| 346 ++
 .../Include/Protocol/Wdt.h| 111 ++
 .../Include/Register/FlashRegs.h  |  73 
 .../Include/Register/GpioRegs.h   | 103 ++
 .../Include/Register/GpioRegsVer2.h   | 211 +++
 .../Include/Register/PchDmi14Regs.h   |  49 +++
 .../Include/Register/PchDmiRegs.h |  51 +++
 .../Include/Register/PchPcieRpRegs.h  |  45 +++
 .../Include/Register/PchRegsLpc.h |  77 
 .../Include/Register/PmcRegs.h| 134 +++
 .../Include/Register/RtcRegs.h|  44 +++
 .../Include/Register/TcoRegs.h|  71 
 .../Include/SerialIoDevices.h | 226 
 .../AlderlakeSiliconPkg/Include/SiConfigHob.h |  17 +
 .../Include/SiPolicyStruct.h  |  64 
 18 files changed, 1745 insertions(+)
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h

diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h 
b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
new file mode 100644
index 00..2e609bc8d9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
@@ -0,0 +1,53 @@
+/** @file
+  Header file for Config Block Lib implementation
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_H_
+#define _CONFIG_BLOCK_H_
+
+#include 
+#include 
+#include 
+#include 
+
+#pragma pack (push,1)
+
+///
+/// Config Block Header
+///
+typedef struct _CONFIG_BLOCK_HEADER {
+  EFI_HOB_GUID_TYPE GuidHob;  ///< Offset 0-23  GUID 
extension HOB header
+  UINT8 Revision; ///< Offset 24Revision 
of this config block
+  UINT8 Attributes;   ///< Offset 25The main 
revision for config block
+  UINT8 Reserved[2];  ///< Offset 26-27 Reserved 
for future use
+} CONFIG_BLOCK_HEADER;
+
+///
+/// Config Block
+///
+typedef struct _CONFIG_BLOCK {
+  CONFIG_BLOCK_HEADERHeader;  ///< Offset 0-27  Header of 
config block
+  //
+  // Config Block Data
+  //
+} CONFIG_BLOCK;
+
+///
+/// Config Block Table Header
+///
+typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
+  CONFIG_BLOCK_HEADERHeader;  ///< Offset 0-27  GUID 
number for main entry of config block
+  UINT8  Rsvd0[2];///< Offset 28-29 Reserved 
for future use
+  UINT16   

Re: [edk2-devel] [PATCH 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru

[Chuang, Rosen]

Reviewed-by: Rosen Chuang 

-Original Message-
From: Kasbekar, Saloni  
Sent: Thursday, September 14, 2023 6:14 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru

Adds the following modules:
  - AdlCpu/CpuPcieRp
  - AdlCpu/Include
  - AdlCpu/IncludePrivate
  - AdlCpu/LibraryPrivate
  - AdlCpu/PeiReportCpuHob
  - AdlCpu DSCs

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Fru/AdlCpu/CommonLib.dsc  |   9 +
 .../CpuPcieInfoFruLib.c   |  87 
 .../PeiDxeSmmCpuPcieInfoFruLib.inf|  39 
 .../AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc |   8 +
 .../Fru/AdlCpu/Include/CpuGenInfo.h   |  42 
 .../Include/Library/CpuPcieInfoFruLib.h   |  45 
 .../Include/Register/SaRegsHostBridge.h   |  64 ++
 .../AdlCpu/IncludePrivate/CpuGenInfoFruLib.h  | 176   
.../AdlCpu/IncludePrivate/Register/IgdRegs.h  |  34 +++
 .../BaseCpuInfoFruLib/BaseCpuInfoFruLib.c | 193 ++
 .../BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf   |  29 +++
 .../PeiReportCpuHobLib/PeiReportCpuHobLib.c   |  22 ++
 .../PeiReportCpuHobLib/PeiReportCpuHobLib.inf |  26 +++
 13 files changed, 774 insertions(+)
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf

diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc 
b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
new file mode 100644
index 00..35a3cce916
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
@@ -0,0 +1,9 @@
+## @file
+#  Component description file for the AlderLake CPU Common FRU libraries.
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+CpuPcieInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/CpuPcieRp/Library/P
+CpuPcieInfoFruLib|eiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.
+CpuPcieInfoFruLib|inf
+CpuInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/LibraryPrivate/BaseCpuI
+CpuInfoFruLib|nfoFruLib/BaseCpuInfoFruLib.inf
diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
 
b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
new file mode 100644
index 00..277b73fe67
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/Pei
+++ DxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
@@ -0,0 +1,87 @@
+/** @file
+  CPU PCIe information library.
+
+  All function in this library is available for PEI, DXE, and SMM,  But 
+ do not support UEFI RUNTIME environment call.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include 
+ #include  #include 
+ #include  #include 
+ #include  
+#include  #include 
+
+/**
+  Get Maximum CPU Pcie Root Port Number
+
+  @retval Maximum CPU Pcie Root Port Number **/
+UINT8
+GetMaxCpuPciePortNum (
+  VOID
+  )
+{
+  switch (GetCpuSku ()) {
+case EnumCpuUlt:
+  return CPU_PCIE_ULT_MAX_ROOT_PORT;
+case EnumCpuUlx:
+  return CPU_PCIE_ULX_MAX_ROOT_PORT;
+default:
+  return CPU_PCIE_ULT_MAX_ROOT_PORT;
+  }
+}
+
+/**
+  Get CPU Pcie Root Port Device and Function Number by Root Port 
+physical Number
+
+  @param[in]  RpNumber  Root port physical number. (0-based)
+  @param[out] RpDev Return corresponding root port device 
number.
+ 

Re: [edk2-devel] [PATCH 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules

[Chuang, Rosen]

Reviewed-by: Rosen Chuang 

-Original Message-
From: Chaganty, Rangasai V  
Sent: Friday, September 15, 2023 6:20 AM
To: Kasbekar, Saloni ; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Chuang, Rosen 

Subject: RE: [PATCH 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and 
IncludePrivate modules

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni 
Sent: Wednesday, September 13, 2023 3:14 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate 
modules

Adds the following modules:
  - AdlPch/Include
  - AdlPch/IncludePrivate
  - AdlPch/Library
  - AdlPch DSCs
  - IncludePrivate

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Fru/AdlPch/CommonLib.dsc  |  29 ++
 .../AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc|  10 +
 .../AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc |   7 +
 .../Fru/AdlPch/Include/PchBdfAssignment.h |  81 +
 .../Fru/AdlPch/Include/PchLimits.h|  47 +++
 .../Fru/AdlPch/Include/PchPcieRpInfo.h|  17 ++
 .../Fru/AdlPch/Include/PchReservedResources.h |  13 +  
.../AdlPch/Include/PchReservedResourcesAdpP.h |  36 +++
 .../IncludePrivate/Register/PchPcrRegs.h  |  59 
 .../IncludePrivate/Register/PchRegsLpcAdl.h   |  30 ++
 .../PeiDxeSmmPchInfoLib/PchInfoLibAdl.c   | 223 ++
 .../PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h   |  44 +++
 .../PeiDxeSmmPchInfoLibAdl.inf|  37 +++
 .../AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc|   7 +
 .../AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc |  12 +
 .../IncludePrivate/RegisterAccess.h   | 288 ++
 16 files changed, 940 insertions(+)
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h

diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc 
b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
new file mode 100644
index 00..3f508f83a1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
@@ -0,0 +1,29 @@
+## @file
+#  Component description file for the AlderLake PCH Common FRU libraries.
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+  
+ PchPcrLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/Library/PeiDxeSmmPchPcrL
+ ib/PeiDxeSmmPchPcrLib.inf
+ PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPrivate/Pei
+ DxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
+  
+ P2SbSidebandAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPriva
+ te/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
+
+  
+ EspiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Espi/Library/PeiDxeSmmEspiLib/P
+ eiDxeSmmEspiLib.inf
+
+
+  
+ PmcLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiD
+ xeSmmPmcLib.inf
+ PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/LibraryPrivate/PeiDxe
+ SmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
+  
+ SpiCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/LibraryPrivate/BaseSpi
+ CommonLib/BaseSpiCommonLib.inf
+ GpioLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/P
+ eiDxeSmmGpioLib.inf
+ PchDmiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PchDmi/LibraryPrivate/PeiDxeS
+ mmPchDmiLib/PeiDxeSmmPchDmiLib.inf
+
+  
+ GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiD
+ xeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
+  
+ PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/Library/

Re: [edk2-devel] [PATCH 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec

[Chuang, Rosen]

Reviewed-by: Rosen Chuang 

-Original Message-
From: Kasbekar, Saloni  
Sent: Thursday, September 14, 2023 6:14 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec

Adds the following modules:
  - Product/Alderlake/Include
  - Product/Alderlake/Library
  - Product/Alderlake DSCs
  - SiPkg.dec

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Product/Alderlake/Include/Ppi/SiPolicy.h  |  55 ++
 .../Library/PeiSiPolicyLib/PeiSiPolicyLib.c   |  47 ++
 .../Library/PeiSiPolicyLib/PeiSiPolicyLib.inf |  47 ++
 .../PeiSiPolicyLib/PeiSiPolicyLibPreMem.c |  47 ++
 .../PeiSiPolicyLib/PeiSiPolicyLibrary.h   |  21 +
 .../Product/Alderlake/SiPkgBuildOption.dsc| 122 
 .../Product/Alderlake/SiPkgCommonLib.dsc  |  36 +
 .../Product/Alderlake/SiPkgDxe.dsc|  32 +
 .../Product/Alderlake/SiPkgDxeLib.dsc |  23 +
 .../Product/Alderlake/SiPkgPeiLib.dsc |  19 +
 Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec   | 625 ++
 11 files changed, 1074 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h 
b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
new file mode 100644
index 00..703f0221bd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/Si
+++ Policy.h
@@ -0,0 +1,55 @@
+/** @file
+  Silicon Policy PPI is used for specifying platform
+  related Intel silicon information and policy setting.
+  This PPI is consumed by the silicon PEI modules and carried
+  over to silicon DXE modules.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _SI_POLICY_PPI_H_
+#define _SI_POLICY_PPI_H_
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifndef DISABLED
+#define DISABLED  0
+#endif
+#ifndef ENABLED
+#define ENABLED   1
+#endif
+
+extern EFI_GUID gSiPreMemPolicyPpiGuid; extern EFI_GUID 
+gSiPolicyPpiGuid;
+
+
+#include 
+
+
+#include 
+#include 
+extern EFI_GUID gCpuPciePeiPreMemConfigGuid; extern EFI_GUID 
+gCpuPcieRpConfigGuid;
+
+#include 
+extern EFI_GUID gMemoryConfigGuid;
+extern EFI_GUID gMemoryConfigNoCrcGuid;
+
+#include 
+extern EFI_GUID gSaMiscPeiPreMemConfigGuid;
+
+#include 
+extern EFI_GUID gHostBridgePeiPreMemConfigGuid; extern EFI_GUID 
+gHostBridgePeiConfigGuid;
+
+typedef struct _SI_PREMEM_POLICY_STRUCT SI_PREMEM_POLICY_PPI; typedef 
+struct _SI_POLICY_STRUCT SI_POLICY_PPI;
+
+#endif // _SI_POLICY_PPI_H_
diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
 
b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
new file mode 100644
index 00..886415bdaa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiP
+++ olicyLib/PeiSiPolicyLib.c
@@ -0,0 +1,47 @@
+/** @file
+  This file is PeiSiPolicyLib library creates default settings of RC
+  Policy and installs RC Policy PPI.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include 
+"PeiSiPolicyLibrary.h"
+#include 
+#include 
+
+
+/**
+  SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+  While installed, RC assumes the Policy is ready and finalized. So 
+please update and override
+  any setting before calling this function.
+
+  @retval EFI_SUCCESSThe policy is installed.
+  @retval EFI_OUT_OF_RESOURCES   Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+  VOID
+  )
+{
+  EFI_STATUS Status;
+  EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPpiDesc;
+
+  SiPolicyReadyPpiDesc = (EFI_PEI_PPI_D

Re: [edk2-devel] [PATCH 1/4] AlderlakeOpenBoardPkg/AlderlakePRvp: Add DSC and build files

[Chuang, Rosen]

Reviewed-by: Rosen Chuang 

-Original Message-
From: Kasbekar, Saloni  
Sent: Thursday, September 14, 2023 6:05 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 1/4] AlderlakeOpenBoardPkg/AlderlakePRvp: Add DSC and build 
files

Adds the DSC and build files necessary to build the
AlderlakePRvp board instance.

Key files:
  * build_config.cfg - Board-specific build configuration file.
  * OpenBoardPkg.dsc - The AlderlakePRvp board description file.
  * OpenBoardPkgPcd.dsc - Used for other PCD customization.
  * OpenBoardPkg.fdf - The AlderlakePRvp board flash file.
  * OpenBoardPkgBuildOption.dsc - Sets build options Based on PCD values.
  * FlashMapInclude.fdf - AlderlakePRvp flash map file.

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Include/Fdf/FlashMapInclude.fdf   |  52 ++
 .../AlderlakePRvp/OpenBoardPkg.dsc| 481 
 .../AlderlakePRvp/OpenBoardPkg.fdf| 724 ++
 .../AlderlakePRvp/OpenBoardPkgBuildOption.dsc | 161 
 .../AlderlakePRvp/OpenBoardPkgPcd.dsc | 371 +
 .../AlderlakePRvp/build_config.cfg|  34 +
 6 files changed, 1823 insertions(+)
 create mode 100644 
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Include/Fdf/FlashMapInclude.fdf
 create mode 100644 
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.dsc
 create mode 100644 
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.fdf
 create mode 100644 
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgBuildOption.dsc
 create mode 100644 
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgPcd.dsc
 create mode 100644 
Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/build_config.cfg

diff --git 
a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Include/Fdf/FlashMapInclude.fdf
 
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Include/Fdf/FlashMapInclude.fdf
new file mode 100644
index 00..03c198c06a
--- /dev/null
+++ 
b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Include/Fdf/FlashMapInclude.fdf
@@ -0,0 +1,52 @@
+## @file
+#  FDF file of Platform.
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+#=#
+# 16 MB BIOS - for FSP wrapper
+#=#
+DEFINE FLASH_BASE   = 
0xFF00  #
+DEFINE FLASH_SIZE   = 
0x0100  #
+DEFINE FLASH_BLOCK_SIZE = 
0x0001  #
+DEFINE FLASH_NUM_BLOCKS = 
0x0100  #
+#=#
+
+#=#
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 
0x  # Flash addr (0xFF00)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize   = 
0x0006  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 
0x  # Flash addr (0xFF00)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize  = 
0x0002E000  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset   = 
0x0002E000  # Flash addr (0xFF02E000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize= 
0x2000  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 
0x0003  # Flash addr (0xFF03)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize  = 
0x0003  #
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset= 
0x000E  # Flash addr (0xFF0E)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize  = 
0x0031  #
+SET gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset   = 
0x003F  # Flash addr (0xFF40)
+SET gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize = 
0x0036  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset= 
0x0075  # Flash addr (0xFF76)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize  = 
0x0009  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset  = 
0x007E  # Flash addr (0xFF7F)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize= 
0x000A  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset= 
0x0088  # Flash addr (0xFF86)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize  = 
0x0018  #
+
+SET gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset   = 
0x00A0  # Flash addr (0xFFA

Re: [edk2-devel] [PATCH 2/4] Enable build for AlderlakeOpenBoardPkg

[Chuang, Rosen]

Reviewed-by: Rosen Chuang 

-Original Message-
From: Chaganty, Rangasai V  
Sent: Thursday, September 14, 2023 7:38 AM
To: Kasbekar, Saloni ; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Chuang, Rosen 

Subject: RE: [PATCH 2/4] Enable build for AlderlakeOpenBoardPkg

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Wednesday, September 13, 2023 3:06 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 2/4] Enable build for AlderlakeOpenBoardPkg

This change adds the configuration to enable build for AlderlakePRvp.
Also it updates Alderlake P Rvp details to the Readme.md.

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 Platform/Intel/Readme.md | 11 +++  Platform/Intel/build.cfg |  1 +
 2 files changed, 12 insertions(+)

diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index 
953260852d..112d0af1f6 100644
--- a/Platform/Intel/Readme.md
+++ b/Platform/Intel/Readme.md
@@ -59,6 +59,7 @@ A UEFI firmware implementation using MinPlatformPkg is 
constructed using the fol
 * The `WhiskeylakeOpenBoardPkg` contains board implementations for WhiskeyLake 
systems.
 * The `CometlakeOpenBoardPkg` contains board implementations for CometLake 
systems.
 * The `TigerlakeOpenBoardPkg` contains board implementations for TigerLake 
systems.
+* The `AlderlakeOpenBoardPkg` contains board implementations for AlderLake 
systems.
 * The `WhitleyOpenBoardPkg` contains board implementations for Ice Lake-SP and 
Cooper Lake systems.
 
 ### **Supported Hardware**
@@ -87,6 +88,7 @@ A UEFI firmware implementation using MinPlatformPkg is 
constructed using the fol
 | WHL-U DDR4 RVP| WhiskeyLake  
  | WhiskeylakeOpenBoardPkg  | WhiskeylakeURvp|
 | CML-U LPDDR3 RVP  | CometLake V1 
  | CometlakeOpenBoardPkg| CometlakeURvp  |
 | TGL-U DDR4 RVP| TigerLake
  | TigerlakeOpenBoardPkg| TigerlakeURvp  |
+| ADL-P DDR5 RVP| AlderLake
  | AlderlakeOpenBoardPkg| AlderlakePRvp  |
 | Wilson City RVP   | IceLake-SP (Xeon Scalable)   
  | WhitleyOpenBoardPkg  | WilsonCityRvp  |
 | Cooper City RVP   | Copper Lake  
  | WhitleyOpenBoardPkg  | CooperCityRvp  |
 
@@ -316,6 +318,11 @@ return back to the minimum platform caller.
   |   ||   |---build_config.cfg: TigerlakeURvp 
specific build
   |   || settings 
environment variables.
   |   ||
+  |   ||--AlderlakeOpenBoardPkg
+  |   ||   |--AlderlakePRvp
+  |   ||   |---build_config.cfg: AlderlakePRvp 
specific build
+  |   || settings 
environment variables.
+  |   ||
   |--FSP
   
 
@@ -401,6 +408,10 @@ For PurleyOpenBoardPkg (TiogaPass)  1. This firmware 
project has been tested booting to Microsoft Windows 10 x64 with AHCI mode and 
Integrated Graphic Device.
 2. This firmware project has been also tested booting to Puppy Linux 
BionicPup64 8.0 with AHCI mode and Integrated Graphic Device.
 
+**AlderlakeOpenBoardPkg**
+1. This firmware project has been tested booting to Microsoft Windows 11 x64 
with M2 SSD Disk and Integrated Graphic Device.
+2. AlderlakeOpenBoardPkg/Acpi/MinDsdt has been modified from 
MinPlatformPkg/Acpi/MinDsdt to avoid hang on boot to Microsoft Windows 11 x64.
+
 **WhitleyOpenBoardPkg**
 1. This firmware project has been tested booting to UEFI shell with headless 
serial console
 
diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg index 
fe0ddb7a1e..2ff536bb3e 100644
--- a/Platform/Intel/build.cfg
+++ b/Platform/Intel/build.cfg
@@ -70,3 +70,4 @@ WilsonCityRvp = 
WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg
 BoardTiogaPass = PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg
 JunctionCity = WhitleyOpenBoardPkg/JunctionCity/build_config.cfg
 Aowanda = WhitleyOpenBoardPkg/Aowanda/build_config.cfg
+AlderLakePRvp = AlderLakeOpenBoardPkg/AlderLakePRvp/build_config.cfg
--
2.36.1.windows.1



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Re: [edk2-devel] [PATCH 3/4] Readme.md: Add AlderlakeOpenBoardPkg

[Chuang, Rosen]

Reviewed-by: Rosen Chuang 

-Original Message-
From: Chaganty, Rangasai V  
Sent: Thursday, September 14, 2023 7:42 AM
To: Kasbekar, Saloni ; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Chuang, Rosen 

Subject: RE: [PATCH 3/4] Readme.md: Add AlderlakeOpenBoardPkg

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Wednesday, September 13, 2023 3:06 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 3/4] Readme.md: Add AlderlakeOpenBoardPkg

Add AlderlakeOpenBoardPkg in the Readme

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 Readme.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Readme.md b/Readme.md
index 624f9a6da6..8de9eaa7cf 100644
--- a/Readme.md
+++ b/Readme.md
@@ -254,6 +254,7 @@ they will be documented with the platform.
 * [Comet Lake](Platform/Intel/CometlakeOpenBoardPkg)
 * [Tiger Lake](Platform/Intel/TigerlakeOpenBoardPkg)
 * [Whitley/Cedar Island](Platform/Intel/WhitleyOpenBoardPkg)
+* [Alder Lake](Platform/Intel/AlderlakeOpenBoardPkg)
 
 For more information, see the
 [EDK II Minimum Platform 
Specification](https://edk2-docs.gitbooks.io/edk-ii-minimum-platform-specification).
-- 
2.36.1.windows.1



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Re: [edk2-devel] [PATCH 4/4] Maintainers.txt: Add maintainers

[Chuang, Rosen]

Reviewed-by: Rosen Chuang 

-Original Message-
From: Chaganty, Rangasai V  
Sent: Thursday, September 14, 2023 6:47 AM
To: Kasbekar, Saloni ; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Chuang, Rosen 

Subject: RE: [PATCH 4/4] Maintainers.txt: Add maintainers

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Wednesday, September 13, 2023 3:06 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH 4/4] Maintainers.txt: Add maintainers

Add AlderlakeSiliconPkg and AlderlakeOpenBoardPkg maintainers

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 Maintainers.txt | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/Maintainers.txt b/Maintainers.txt index d1d7613ef4..936304d608 
100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -245,6 +245,13 @@ M: Sai Chaganty 
 M: Nate DeSimone 
 R: Heng Luo 
 
+Platform/Intel/AlderlakeOpenBoardPkg
+F: Platform/Intel/AlderlakeOpenBoardPkg/
+M: Sai Chaganty 
+M: Nate DeSimone 
+R: Rosen Chuang 
+R: Saloni Kasbekar 
+
 Platform/Intel/WhitleyOpenBoardPkg
 F: Platform/Intel/WhitleyOpenBoardPkg/
 M: Isaac Oram 
@@ -316,6 +323,13 @@ M: Sai Chaganty 
 M: Nate DeSimone 
 R: Heng Luo 
 
+Platform/Intel/AlderlakeSiliconPkg
+F: Platform/Intel/AlderlakeSiliconPkg/
+M: Sai Chaganty 
+M: Nate DeSimone 
+R: Rosen Chuang 
+R: Saloni Kasbekar 
+
 Silicon/Intel/WhitleySiliconPkg
 F: Silicon/Intel/WhitleySiliconPkg/
 M: Isaac Oram 
--
2.36.1.windows.1



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[edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components

[Saloni Kasbekar]

Adds the following modules:
  - IpBlock/CpuPcieRp/Include
  - IpBlock/Espi/Library
  - IpBlock/Gpio/IncludePrivate
  - IpBlock/Gpio/Library
  - IpBlock/Gpio/LibraryPrivate

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../IpBlock/CpuPcieRp/Include/CpuPcieInfo.h   |  25 +
 .../Espi/Library/PeiDxeSmmEspiLib/EspiLib.c   |  58 ++
 .../PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf |  38 ++
 .../IncludePrivate/Library/GpioHelpersLib.h   |  50 ++
 .../IncludePrivate/Library/GpioNativePads.h   | 245 
 .../IncludePrivate/Library/GpioPrivateLib.h   | 350 +++
 .../Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c  | 546 ++
 .../Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c   | 522 +
 .../Library/PeiDxeSmmGpioLib/GpioLibrary.h|  29 +
 .../Library/PeiDxeSmmGpioLib/GpioNativeLib.c  | 177 ++
 .../PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf |  44 ++
 .../BaseGpioHelpersLibNull.c  |  51 ++
 .../BaseGpioHelpersLibNull.inf|  25 +
 .../GpioNativePrivateLibInternal.h|  48 ++
 .../PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c  | 267 +
 .../GpioPrivateLibPch.c   | 172 ++
 .../GpioPrivateLibVer2.c  |  81 +++
 .../PeiDxeSmmGpioPrivateLibVer2.inf   |  40 ++
 .../PeiGpioHelpersLib/PeiGpioHelpersLib.c | 218 +++
 .../PeiGpioHelpersLib/PeiGpioHelpersLib.inf   |  46 ++
 20 files changed, 3032 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
new file mode 100644
index 00..a6f8b16d10
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
@@ -0,0 +1,25 @@
+/** @file
+  This file contains definitions of PCIe controller information
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_INFO_H_
+#define _CPU_PCIE_INFO_H_
+
+#define PCIE_HWEQ_COEFFS_MAX5
+
+
+//
+// SA PCI Express* Port configuration
+//
+
+#define CPU_PCIE_MAX_ROOT_PORTS4
+#define CPU_PCIE_MAX_CONTROLLERS   3
+
+#define SA_PEG_MAX_FUN   0x04
+#define SA_PEG_MAX_LANE  0x14
+
+
+
+#endif
diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
new file mode 100644
index 00..2e4d1375ca
--- /dev/null
+++ 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLi

[edk2-devel] [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components

[Saloni Kasbekar]

Adds the following modules:
  - IpBlock/Graphics/Include
  - IpBlock/Graphics/IncludePrivate
  - IpBlock/Graphics/Library
  - IpBlock/Graphics/LibraryPrivate
  - IpBlock/HostBridge/IncludePrivate
  - IpBlock/PcieRp/Library

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Include/Ppi/GraphicsPlatformPolicyPpi.h   |  76 +++
 .../Library/DxeGraphicsPolicyLib.h|  71 +++
 .../Library/DxeIgdOpRegionInitLib.h   | 115 +
 .../GraphicsInfoLibVer1.c |  52 
 .../GraphicsInfoLibVer1.inf   |  33 +
 .../DxeGraphicsPolicyLib.c| 116 +
 .../DxeGraphicsPolicyLib.inf  |  36 ++
 .../DxeIgdOpRegionInit.c  | 119 ++
 .../DxeIgdOpRegionInitLib.inf |  47 +++
 .../IncludePrivate/HostBridgeDataHob.h|  25 
 .../PchPcieRpLibInternal.h|  20 +++
 .../PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c  |  71 +++
 .../PeiDxeSmmPchPcieRpLibVer2.inf |  37 ++
 13 files changed, 818 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
new file mode 100644
index 00..a8f67061a5
--- /dev/null
+++ 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
@@ -0,0 +1,76 @@
+/** @file
+  The PEI_GRAPHICS_PLATFORM_POLICY_PPI provides platform information to PEI 
Graphics PEIM.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+#define _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+
+/**
+  Globally unique identifier for PEI platform policy PPI.
+**/
+#define PEI_GRAPHICS_PLATFORM_POLICY_PPI_GUID \
+{ \
+  0x4eabcd09, 0x43d3, 0x4b4d, { 0xb7, 0x3d, 0x43, 0xc8, 0xd9, 0x89, 0x99, 0x5 
} \
+}
+
+#define PEI_GRAPHICS_PLATFORM_POLICY_REVISION 1
+
+/**
+Pre-declaration of PEI graphics platform policy PPI.
+**/
+typedef struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI 
PEI_GRAPHICS_PLATFORM_POLICY_PPI;
+
+/**
+  Enum defining the different lid status values
+**/
+typedef enum {
+  LidClosed,
+  LidOpen,
+  LidStatusMax
+} LID_STATUS;
+
+/**
+  This function gets the platform lid status for LFP displays.
+
+  @param[out] CurrentLidStatus  Output variable to store the lid status.
+
+  @retval EFI_SUCCESS   Correct lid status is returned.
+  @retval EFI_UNSUPPORTED   Platform does not support lid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_PLATFORM_LID_STATUS) (
+  OUT LID_STATUS  *CurrentLidStatus
+  );
+
+/**
+  This function gets the base address of loaded VBT.
+
+  @param[out] VbtAddressStarting address of the VBT is returned in this 
parameter.
+  @param[out] VbtSize   Size of the VBT is returned in this parameter.
+
+  @retval EFI_SUCCESS   If the VBT is loaded and parameters contain valid 
values.
+  @return Other error codes meaning VBT is not loaded and parameters 
contain invalid values.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_VBT_DATA) (
+  OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+  OUT UINT32   *VbtSize
+  );
+
+/**
+  This 

[edk2-devel] [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components

[Saloni Kasbekar]

Adds the following modules:
  - IpBlock/P2sb/IncludePrivate
  - IpBlock/P2sb/Library
  - IpBlock/P2sb/LibraryPrivate
  - IpBlock/PchDmi/IncludePrivate
  - IpBlock/PchDmi/LibraryPrivate

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Library/P2SbSidebandAccessLib.h   | 105 +++
 .../IncludePrivate/Library/PchSbiAccessLib.h  |  58 
 .../P2sb/IncludePrivate/P2SbController.h  |  32 +++
 .../P2sb/IncludePrivate/Register/P2sbRegs.h   |  53 
 .../Library/PeiDxeSmmPchPcrLib/PchPcrLib.c| 266 ++
 .../PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf |  35 +++
 .../PeiDxeSmmP2SbSidebandAccessLib.c  | 208 ++
 .../PeiDxeSmmP2SbSidebandAccessLib.inf|  30 ++
 .../PchSbiAccessLib.c |  72 +
 .../PeiDxeSmmPchSbiAccessLib.inf  |  35 +++
 .../PchDmi/IncludePrivate/Library/PchDmiLib.h |  60 
 .../PeiDxeSmmPchDmiLib/PchDmi14.c |  34 +++
 .../PeiDxeSmmPchDmiLib/PchDmi14.h |  22 ++
 .../PeiDxeSmmPchDmiLib/PchDmiLib.c| 110 
 .../PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf |  43 +++
 15 files changed, 1163 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
new file mode 100644
index 00..e364508eb4
--- /dev/null
+++ 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
@@ -0,0 +1,105 @@
+/** @file
+  Header for P2SbSidebandAccessLib
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _P2SB_SIDEBAND_ACCESS_LIB_H_
+#define _P2SB_SIDEBAND_ACCESS_LIB_H_
+
+#include 
+#include 
+#include  // For PCH_SBI_PID definition
+
+typedef PCH_SBI_PID  P2SB_PID;
+
+typedef enum {
+  P2SbMemory = 0,
+  P2SbPciConfig,
+  P2SbPrivateConfig
+} P2SB_REGISTER_SPACE;
+
+typedef enum {
+  MemoryRead = 0x0,
+  MemoryWrite= 0x1,
+  PciConfigRead  = 0x4,
+  PciConfigWrite = 0x5,
+  PrivateControlRead = 0x6,
+  PrivateControlWrite= 0x7,
+  GpioLockUnlock = 0x13
+} P2SB_SBI_OPCODE;
+
+typedef enum {
+  SBI_SUCCESSFUL  = 0,
+  SBI_UNSUCCESSFUL= 1,
+  SBI_POWERDOWN   = 2,
+  SBI_MIXED   = 3,
+  SBI_INVALID_RESPONSE
+} P2SB_SBI_RESPONSE;
+
+typedef enum {
+  P2SbMmioAccess = 0,
+  P2SbMsgAccess
+} P2SB_SIDEBAND_ACCESS_METHOD;
+
+/**
+  REGISTER_ACCESS for P2SB device to support access to sideband registers.
+  Be sure to keep first member of this structure as REGISTER_ACCESS to allow
+  for correct casting between caller who sees this structure as REGISTER_ACCESS
+  and calle who will cast it to P2SB_SIDEBAND_REGISTER_ACCESS.
+**/
+typedef struct {
+  REGISTER_ACCESS  Access;
+  P2SB_SIDEBAND_ACCESS_METHOD  AccessMethod;
+  P2SB_PID P2SbPid;
+  UINT16   Fid;
+  P2SB_REGISTER_SPACE  RegisterSpace;
+  BOOLEAN  PostedWrites;
+  P2SB_CONTROLLER 

[edk2-devel] [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components

[Saloni Kasbekar]

Adds the following modules:
  - IpBlock/Pmc/IncludePrivate
  - IpBlock/Pmc/Library
  - IpBlock/Pmc/LibraryPrivate
  - IpBlock/Spi/IncludePrivate
  - IpBlock/Spi/Library
  - IpBlock/Spi/LibraryPrivate
  - IpBlock/Spi/Smm

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../IncludePrivate/Library/PmcPrivateLib.h|   47 +
 .../IpBlock/Pmc/IncludePrivate/PmcSocConfig.h |   67 +
 .../PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf   |   38 +
 .../Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c  |   50 +
 .../PeiDxeSmmPmcPrivateLib.inf|   43 +
 .../PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c|   86 ++
 .../Spi/IncludePrivate/Library/SpiCommonLib.h |  376 ++
 .../Spi/IncludePrivate/Register/SpiRegs.h |  116 ++
 .../IpBlock/Spi/Library/PeiSpiLib/PchSpi.c|  209 +++
 .../Spi/Library/PeiSpiLib/PeiSpiLib.inf   |   41 +
 .../BaseSpiCommonLib/BaseSpiCommonLib.inf |   29 +
 .../BaseSpiCommonLib/SpiCommon.c  | 1127 +
 .../AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c |  387 ++
 .../IpBlock/Spi/Smm/SpiSmm.inf|   46 +
 14 files changed, 2662 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
new file mode 100644
index 00..6ec244b127
--- /dev/null
+++ 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
@@ -0,0 +1,47 @@
+/** @file
+  Header file for private PmcLib.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_PRIVATE_LIB_H_
+#define _PMC_PRIVATE_LIB_H_
+
+#include 
+#include "Register/PmcRegs.h"
+
+typedef enum {
+  PmcSwSmiRate1p5ms = 0,
+  PmcSwSmiRate16ms,
+  PmcSwSmiRate32ms,
+  PmcSwSmiRate64ms
+} PMC_SWSMI_RATE;
+
+/**
+  This function sets SW SMI Rate.
+
+  @param[in] SwSmiRateRefer to PMC_SWSMI_RATE for possible values
+**/
+VOID
+PmcSetSwSmiRate (
+  IN PMC_SWSMI_RATE  SwSmiRate
+  );
+
+typedef enum {
+  PmcPeriodicSmiRate8s = 0,
+  PmcPeriodicSmiRate16s,
+  PmcPeriodicSmiRate32s,
+  PmcPeriodicSmiRate64s
+} PMC_PERIODIC_SMI_RATE;
+
+/**
+  This function sets Periodic SMI Rate.
+
+  @param[in] PeriodicSmiRateRefer to PMC_PERIODIC_SMI_RATE for 
possible values
+**/
+VOID
+PmcSetPeriodicSmiRate (
+  IN PMC_PERIODIC_SMI_RATEPeriodicSmiRate
+  );
+
+#endif // _PMC_PRIVATE_LIB_H_
diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
new file mode 100644
index 00..523a84a180
--- /dev/null
+++ 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
@@ -0,0 +1,67 @@
+/** @file
+  PMC SoC configuration
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PMC_SOC_CONFIGURATION_H_
+#define _PMC_SOC_CONFIGURATION_H_
+
+typedef enum {
+  AdrSinglePhase = 0,
+  AdrDualPhase
+} ADR_PHASE_TYPE;
+
+typedef enum {
+  AdrGpioB = 0,
+  AdrGpioC
+} ADR_GPIO;
+
+typedef enum {
+  AdrOverPmSync = 0,
+  AdrOverDmi
+} ADR_MSG_INTERFACE;
+
+typedef struct {
+  BOOLEANSupported;
+  ADR_PHASE_TYPE AdrPhaseType;
+  ADR_GPIO   AdrGpio;
+  ADR_MSG_INTERFACE  AdrMsgInterface;
+  //
+  // On some designs ADR_GEN_CFG has been moved in the HW.
+  // Set this to if A

[edk2-devel] [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes

[Saloni Kasbekar]

Adds the following Includes:
  - Include/Library
  - Include/Pins
  - Include/Ppi

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Include/Library/ConfigBlockLib.h  |  64 +++
 .../Include/Library/EspiLib.h |  34 ++
 .../Include/Library/GpioConfig.h  | 372 ++
 .../Include/Library/GpioLib.h | 174 
 .../Include/Library/GpioNativeLib.h   | 135 +++
 .../Include/Library/GraphicsInfoLib.h |  46 +++
 .../Include/Library/MmPciLib.h|  27 ++
 .../Include/Library/PchPcieRpLib.h|  41 ++
 .../Include/Library/PchPcrLib.h   | 221 +++
 .../Library/PeiDxeSmmReserveMmio64SizeLib.h   |  21 +
 .../Include/Library/PeiSiPolicyUpdateLib.h| 154 
 .../Include/Library/PmcLib.h  |  40 ++
 .../Include/Library/ResetSystemLib.h  |  68 
 .../Include/Library/SecPlatformLib.h  |  81 
 .../Include/Library/SiConfigBlockLib.h|  56 +++
 .../Include/Library/SiPolicyLib.h |  39 ++
 .../Include/Library/SpiLib.h  |  21 +
 .../Include/Pins/GpioPinsVer2Lp.h |  36 ++
 .../Include/Ppi/FspmArchConfigPpi.h   |  32 ++
 .../Include/Ppi/PeiPreMemSiDefaultPolicy.h|  33 ++
 .../Include/Ppi/PeiSiDefaultPolicy.h  |  33 ++
 .../AlderlakeSiliconPkg/Include/Ppi/Spi.h |  29 ++
 .../AlderlakeSiliconPkg/Include/Ppi/Wdt.h |  22 ++
 23 files changed, 1779 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h

diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h 
b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
new file mode 100644
index 00..d9966c76e9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
@@ -0,0 +1,64 @@
+/** @file
+  Header file for Config Block Lib implementation
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_LIB_H_
+#define _CONFIG_BLOCK_LIB_H_
+
+/**
+  Create config block table
+
+  @param[in] TotalSize- Max size to be allocated for 
the Config Block Table
+  @param[out]ConfigBlockTableAddress  - On return, points to a pointer 
to the beginning of Config Block Table Address
+
+  @retval EFI_INVALID_PARAMETER - Invalid Parameter
+  @retval EFI_OUT_OF_RESOURCES  - Out of resources
+  @retval EFI_SUCCESS   - Successfully created Config Block Table at 
ConfigBlockTableAddress
+**/
+EFI_STATUS
+EFIAPI
+CreateConfigBlockTable (
+  IN UINT16TotalSize,
+  OUTVOID  **ConfigBlockTableAddress
+  );
+
+/**
+  Add config block into config block table structure
+
+  @param[in] ConfigBlockTableAddress  - A pointer to the beginning of 
Config Block Table Address
+  @param[out]ConfigBlockAddress   - On return, points to a pointer 
to the beginning of Config Block Address
+
+  @retval EFI_OUT_OF_RESOURCES - C

[edk2-devel] [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru

[Saloni Kasbekar]

Adds the following modules:
  - AdlCpu/CpuPcieRp
  - AdlCpu/Include
  - AdlCpu/IncludePrivate
  - AdlCpu/LibraryPrivate
  - AdlCpu/PeiReportCpuHob
  - AdlCpu DSCs

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Fru/AdlCpu/CommonLib.dsc  |   9 +
 .../CpuPcieInfoFruLib.c   |  87 ++
 .../PeiDxeSmmCpuPcieInfoFruLib.inf|  39 +
 .../AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc |   8 +
 .../Fru/AdlCpu/Include/CpuGenInfo.h   |  42 +
 .../Include/Library/CpuPcieInfoFruLib.h   |  45 +
 .../Include/Register/SaRegsHostBridge.h   |  64 +++
 .../AdlCpu/IncludePrivate/CpuGenInfoFruLib.h  |  44 +
 .../AdlCpu/IncludePrivate/Register/IgdRegs.h  |  34 
 .../BaseCpuInfoFruLib/BaseCpuInfoFruLib.c | 164 ++
 .../BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf   |  29 
 .../PeiReportCpuHobLib/PeiReportCpuHobLib.c   |  22 +++
 .../PeiReportCpuHobLib/PeiReportCpuHobLib.inf |  26 +++
 13 files changed, 613 insertions(+)
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf

diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc 
b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
new file mode 100644
index 00..35a3cce916
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
@@ -0,0 +1,9 @@
+## @file
+#  Component description file for the AlderLake CPU Common FRU libraries.
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+CpuPcieInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
+CpuInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
 
b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
new file mode 100644
index 00..277b73fe67
--- /dev/null
+++ 
b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
@@ -0,0 +1,87 @@
+/** @file
+  CPU PCIe information library.
+
+  All function in this library is available for PEI, DXE, and SMM,
+  But do not support UEFI RUNTIME environment call.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Get Maximum CPU Pcie Root Port Number
+
+  @retval Maximum CPU Pcie Root Port Number
+**/
+UINT8
+GetMaxCpuPciePortNum (
+  VOID
+  )
+{
+  switch (GetCpuSku ()) {
+case EnumCpuUlt:
+  return CPU_PCIE_ULT_MAX_ROOT_PORT;
+case EnumCpuUlx:
+  return CPU_PCIE_ULX_MAX_ROOT_PORT;
+default:
+  return CPU_PCIE_ULT_MAX_ROOT_PORT;
+  }
+}
+
+/**
+  Get CPU Pcie Root Port Device and Function Number by Root Port physical 
Number
+
+  @param[in]  RpNumber  Root port physical number. (0-based)
+  @param[out] RpDev Return corresponding root port device 
number.
+  @param[out] RpFun Return corresponding root port function 
number.
+
+  @retval EFI_SUCCESS   Root port device and function is retrieved
+  @retval EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetCpuPcieRpDevFun (
+  IN  UINTN   RpNumber,
+  OUT UINTN   *RpDev,
+  OUT UINTN   *RpFun
+  )
+{
+  if (RpNumbe

[edk2-devel] [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes

[Saloni Kasbekar]

Adds the following Includes:
  - Include/
  - Include/Protocol
  - Include/Register

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../AlderlakeSiliconPkg/Include/ConfigBlock.h |  53 +++
 .../AlderlakeSiliconPkg/Include/CpuPcieHob.h  |  48 +++
 .../Include/Protocol/IgdOpRegion.h|  22 ++
 .../Include/Protocol/Spi.h| 346 ++
 .../Include/Protocol/Wdt.h| 111 ++
 .../Include/Register/FlashRegs.h  |  73 
 .../Include/Register/GpioRegs.h   | 103 ++
 .../Include/Register/GpioRegsVer2.h   | 211 +++
 .../Include/Register/PchDmi14Regs.h   |  49 +++
 .../Include/Register/PchDmiRegs.h |  51 +++
 .../Include/Register/PchPcieRpRegs.h  |  45 +++
 .../Include/Register/PchRegsLpc.h |  77 
 .../Include/Register/PmcRegs.h| 134 +++
 .../Include/Register/RtcRegs.h|  44 +++
 .../Include/Register/TcoRegs.h|  71 
 .../Include/SerialIoDevices.h | 226 
 .../AlderlakeSiliconPkg/Include/SiConfigHob.h |  17 +
 .../Include/SiPolicyStruct.h  |  64 
 18 files changed, 1745 insertions(+)
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h

diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h 
b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
new file mode 100644
index 00..2e609bc8d9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
@@ -0,0 +1,53 @@
+/** @file
+  Header file for Config Block Lib implementation
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_H_
+#define _CONFIG_BLOCK_H_
+
+#include 
+#include 
+#include 
+#include 
+
+#pragma pack (push,1)
+
+///
+/// Config Block Header
+///
+typedef struct _CONFIG_BLOCK_HEADER {
+  EFI_HOB_GUID_TYPE GuidHob;  ///< Offset 0-23  GUID 
extension HOB header
+  UINT8 Revision; ///< Offset 24Revision 
of this config block
+  UINT8 Attributes;   ///< Offset 25The main 
revision for config block
+  UINT8 Reserved[2];  ///< Offset 26-27 Reserved 
for future use
+} CONFIG_BLOCK_HEADER;
+
+///
+/// Config Block
+///
+typedef struct _CONFIG_BLOCK {
+  CONFIG_BLOCK_HEADERHeader;  ///< Offset 0-27  Header of 
config block
+  //
+  // Config Block Data
+  //
+} CONFIG_BLOCK;
+
+///
+/// Config Block Table Header
+///
+typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
+  CONFIG_BLOCK_HEADERHeader;  ///< Offset 0-27  GUID 
number for main entry of config block
+  UINT8  Rsvd0[2];///< Offset 28-29 Reserved 
for future use
+  UINT16 NumberOfBlocks;  ///< Offset 30-31 Number of 
config blocks (N)
+  UINT32 AvailableSize;   ///< Offset 32-35 Current 
config block table size
+///
+/// Individual Config Block Structures are added here in memory as part of 
AddConfigBlock()
+///
+} CONFIG_BLOCK_TABLE_HEADER;
+#pragma pack (pop)
+
+#endif // _CONFIG_BLOCK_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h 
b/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
new file mode 100644
index 00..dccd6e7d7a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
@@ -0,0 +1,48 @@
+/** @file
+  The

[edk2-devel] [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules

[Saloni Kasbekar]

Adds the following modules:
  - AdlPch/Include
  - AdlPch/IncludePrivate
  - AdlPch/Library
  - AdlPch DSCs
  - IncludePrivate

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Fru/AdlPch/CommonLib.dsc  |  29 ++
 .../AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc|  10 +
 .../AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc |   7 +
 .../Fru/AdlPch/Include/PchBdfAssignment.h |  81 +
 .../Fru/AdlPch/Include/PchLimits.h|  47 +++
 .../Fru/AdlPch/Include/PchPcieRpInfo.h|  17 ++
 .../Fru/AdlPch/Include/PchReservedResources.h |  13 +
 .../AdlPch/Include/PchReservedResourcesAdpP.h |  36 +++
 .../IncludePrivate/Register/PchPcrRegs.h  |  59 
 .../IncludePrivate/Register/PchRegsLpcAdl.h   |  30 ++
 .../PeiDxeSmmPchInfoLib/PchInfoLibAdl.c   | 223 ++
 .../PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h   |  44 +++
 .../PeiDxeSmmPchInfoLibAdl.inf|  37 +++
 .../AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc|   7 +
 .../AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc |  12 +
 .../IncludePrivate/RegisterAccess.h   | 288 ++
 16 files changed, 940 insertions(+)
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h

diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc 
b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
new file mode 100644
index 00..3f508f83a1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
@@ -0,0 +1,29 @@
+## @file
+#  Component description file for the AlderLake PCH Common FRU libraries.
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+  
PchPcrLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
+  
PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
+  
P2SbSidebandAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
+
+  
EspiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
+
+
+  
PmcLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
+  
PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
+  
SpiCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
+  
GpioLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
+  
PchDmiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf
+
+  
GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
+  
PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
+
+
+  #
+  # Common FRU Libraries
+  #
+  
PchInfoLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc 
b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
new file mode 100644
index 00..b443611d9a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
@@ -0,0 +1,10 @@
+## @file
+#  Component description file for the AlderLake PCH DXE FRU drivers.
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+

[edk2-devel] [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec

[Saloni Kasbekar]

Adds the following modules:
  - Product/Alderlake/Include
  - Product/Alderlake/Library
  - Product/Alderlake DSCs
  - SiPkg.dec

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Product/Alderlake/Include/Ppi/SiPolicy.h  |  55 ++
 .../Library/PeiSiPolicyLib/PeiSiPolicyLib.c   |  47 ++
 .../Library/PeiSiPolicyLib/PeiSiPolicyLib.inf |  47 ++
 .../PeiSiPolicyLib/PeiSiPolicyLibPreMem.c |  47 ++
 .../PeiSiPolicyLib/PeiSiPolicyLibrary.h   |  21 +
 .../Product/Alderlake/SiPkgBuildOption.dsc| 122 
 .../Product/Alderlake/SiPkgCommonLib.dsc  |  36 +
 .../Product/Alderlake/SiPkgDxe.dsc|  32 +
 .../Product/Alderlake/SiPkgDxeLib.dsc |  23 +
 .../Product/Alderlake/SiPkgPeiLib.dsc |  19 +
 Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec   | 625 ++
 11 files changed, 1074 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h 
b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
new file mode 100644
index 00..703f0221bd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
@@ -0,0 +1,55 @@
+/** @file
+  Silicon Policy PPI is used for specifying platform
+  related Intel silicon information and policy setting.
+  This PPI is consumed by the silicon PEI modules and carried
+  over to silicon DXE modules.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SI_POLICY_PPI_H_
+#define _SI_POLICY_PPI_H_
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifndef DISABLED
+#define DISABLED  0
+#endif
+#ifndef ENABLED
+#define ENABLED   1
+#endif
+
+extern EFI_GUID gSiPreMemPolicyPpiGuid;
+extern EFI_GUID gSiPolicyPpiGuid;
+
+
+#include 
+
+
+#include 
+#include 
+extern EFI_GUID gCpuPciePeiPreMemConfigGuid;
+extern EFI_GUID gCpuPcieRpConfigGuid;
+
+#include 
+extern EFI_GUID gMemoryConfigGuid;
+extern EFI_GUID gMemoryConfigNoCrcGuid;
+
+#include 
+extern EFI_GUID gSaMiscPeiPreMemConfigGuid;
+
+#include 
+extern EFI_GUID gHostBridgePeiPreMemConfigGuid;
+extern EFI_GUID gHostBridgePeiConfigGuid;
+
+typedef struct _SI_PREMEM_POLICY_STRUCT SI_PREMEM_POLICY_PPI;
+typedef struct _SI_POLICY_STRUCT SI_POLICY_PPI;
+
+#endif // _SI_POLICY_PPI_H_
diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
 
b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
new file mode 100644
index 00..886415bdaa
--- /dev/null
+++ 
b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
@@ -0,0 +1,47 @@
+/** @file
+  This file is PeiSiPolicyLib library creates default settings of RC
+  Policy and installs RC Policy PPI.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "PeiSiPolicyLibrary.h"
+#include 
+#include 
+
+
+/**
+  SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+  While installed, RC assumes the Policy is ready and finalized. So please 
update and override
+  any setting before calling this function.
+
+  @retval EFI_SUCCESSThe policy is installed.
+  @retval EFI_OUT_OF_RESOURCES   Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+  VOID
+  )
+{
+  EFI_STATUS Status;
+  EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPpiDesc;
+
+  SiPolicyReadyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof 
(EFI_PEI_PPI_DESCRIPTOR));
+  if (SiPolicyReadyPpiDesc == NULL) {
+ASSERT (FALSE);
+return EFI_OUT_OF_RESOURCES;
+  }
+
+  SiPolicyReadyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | 
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+  SiPolicyReadyPpiDesc->Guid  = &gSiPolicyReadyPpiGuid;
+  

Re: [edk2-devel] [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, 
HostBridge, PcieRp components

Adds the following modules:
  - IpBlock/Graphics/Include
  - IpBlock/Graphics/IncludePrivate
  - IpBlock/Graphics/Library
  - IpBlock/Graphics/LibraryPrivate
  - IpBlock/HostBridge/IncludePrivate
  - IpBlock/PcieRp/Library

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Include/Ppi/GraphicsPlatformPolicyPpi.h   |  76 +++
 .../Library/DxeGraphicsPolicyLib.h|  71 +++
 .../Library/DxeIgdOpRegionInitLib.h   | 115 +
 .../GraphicsInfoLibVer1.c |  52 
 .../GraphicsInfoLibVer1.inf   |  33 +
 .../DxeGraphicsPolicyLib.c| 116 +
 .../DxeGraphicsPolicyLib.inf  |  36 ++
 .../DxeIgdOpRegionInit.c  | 119 ++
 .../DxeIgdOpRegionInitLib.inf |  47 +++
 .../IncludePrivate/HostBridgeDataHob.h|  25 
 .../PchPcieRpLibInternal.h|  20 +++
 .../PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c  |  71 +++
 .../PeiDxeSmmPchPcieRpLibVer2.inf |  37 ++
 13 files changed, 818 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
new file mode 100644
index 00..a8f67061a5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/Gra
+++ phicsPlatformPolicyPpi.h
@@ -0,0 +1,76 @@
+/** @file
+  The PEI_GRAPHICS_PLATFORM_POLICY_PPI provides platform information to PEI 
Graphics PEIM.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+#define _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+
+/**
+  Globally unique identifier for PEI platform policy PPI.
+**/
+#define PEI_GRAPHICS_PLATFORM_POLICY_PPI_GUID \ { \
+  0x4eabcd09, 0x43d3, 0x4b4d, { 0xb7, 0x3d, 0x43, 0xc8, 0xd9, 0x89, 
+0x99, 0x5 } \ }
+
+#define PEI_GRAPHICS_PLATFORM_POLICY_REVISION 1
+
+/**
+Pre-declaration of PEI graphics platform policy PPI.
+**/
+typedef struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI 
+PEI_GRAPHICS_PLATFORM_POLICY_PPI;
+
+/**
+  Enum defining the different lid status values **/ typedef enum {
+  LidClosed,
+  LidOpen,
+  LidStatusMax
+} LID_STATUS;
+
+/**
+  This function gets the platform lid status for LFP displays.
+
+  @param[out] CurrentLidStatus  Output variable to store the lid status.
+
+  @retval EFI_SUCCESS   Correct lid status is returned.
+  @retval EFI_UNSUPPORTED   Platform does not support lid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_PLATFORM_LID_STATUS) (
+  OUT LID_STATUS  *CurrentLidStatus
+  );
+
+/**
+  This function gets the base address of loaded VBT.
+
+  @param[out] VbtAddressStarting address of the VBT is returned in this 
parameter.
+  @param[out] VbtSize   Size of the VBT is returned in this parameter.
+
+

Re: [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, 
Gpio components

Adds the following modules:
  - IpBlock/CpuPcieRp/Include
  - IpBlock/Espi/Library
  - IpBlock/Gpio/IncludePrivate
  - IpBlock/Gpio/Library
  - IpBlock/Gpio/LibraryPrivate

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../IpBlock/CpuPcieRp/Include/CpuPcieInfo.h   |  25 +
 .../Espi/Library/PeiDxeSmmEspiLib/EspiLib.c   |  58 ++
 .../PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf |  38 ++
 .../IncludePrivate/Library/GpioHelpersLib.h   |  50 ++
 .../IncludePrivate/Library/GpioNativePads.h   | 245 
 .../IncludePrivate/Library/GpioPrivateLib.h   | 350 +++
 .../Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c  | 546 ++
 .../Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c   | 522 +
 .../Library/PeiDxeSmmGpioLib/GpioLibrary.h|  29 +
 .../Library/PeiDxeSmmGpioLib/GpioNativeLib.c  | 177 ++
 .../PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf |  44 ++
 .../BaseGpioHelpersLibNull.c  |  51 ++
 .../BaseGpioHelpersLibNull.inf|  25 +
 .../GpioNativePrivateLibInternal.h|  48 ++
 .../PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c  | 267 +
 .../GpioPrivateLibPch.c   | 172 ++
 .../GpioPrivateLibVer2.c  |  81 +++
 .../PeiDxeSmmGpioPrivateLibVer2.inf   |  40 ++
 .../PeiGpioHelpersLib/PeiGpioHelpersLib.c | 218 +++
 .../PeiGpioHelpersLib/PeiGpioHelpersLib.inf   |  46 ++
 20 files changed, 3032 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
new file mode 100644
index 00..a6f8b16d10
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
@@ -0,0 +1,25 @@
+/** @file
+  This file contains definitions of PCIe controller information
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_INFO_H_
+#define _CPU_PCIE_INFO_H_
+
+#define PCIE_HWEQ_COEFFS_MAX5
+
+
+//
+// SA PCI Express* Port configuration
+//
+
+#define CPU_PCIE_MAX_ROOT_PORTS4
+#define CPU_PCIE_MAX_CONTROLLERS   3
+
+#define SA_PEG_MAX_FUN   0x04
+#define SA_PEG_MAX_LANE  0x14
+
+
+
+#

Re: [edk2-devel] [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi 
components

Adds the following modules:
  - IpBlock/P2sb/IncludePrivate
  - IpBlock/P2sb/Library
  - IpBlock/P2sb/LibraryPrivate
  - IpBlock/PchDmi/IncludePrivate
  - IpBlock/PchDmi/LibraryPrivate

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Library/P2SbSidebandAccessLib.h   | 105 +++
 .../IncludePrivate/Library/PchSbiAccessLib.h  |  58 
 .../P2sb/IncludePrivate/P2SbController.h  |  32 +++
 .../P2sb/IncludePrivate/Register/P2sbRegs.h   |  53 
 .../Library/PeiDxeSmmPchPcrLib/PchPcrLib.c| 266 ++
 .../PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf |  35 +++
 .../PeiDxeSmmP2SbSidebandAccessLib.c  | 208 ++
 .../PeiDxeSmmP2SbSidebandAccessLib.inf|  30 ++
 .../PchSbiAccessLib.c |  72 +
 .../PeiDxeSmmPchSbiAccessLib.inf  |  35 +++
 .../PchDmi/IncludePrivate/Library/PchDmiLib.h |  60 
 .../PeiDxeSmmPchDmiLib/PchDmi14.c |  34 +++
 .../PeiDxeSmmPchDmiLib/PchDmi14.h |  22 ++
 .../PeiDxeSmmPchDmiLib/PchDmiLib.c| 110 
 .../PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf |  43 +++
 15 files changed, 1163 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
new file mode 100644
index 00..e364508eb4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Libr
+++ ary/P2SbSidebandAccessLib.h
@@ -0,0 +1,105 @@
+/** @file
+  Header for P2SbSidebandAccessLib
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _P2SB_SIDEBAND_ACCESS_LIB_H_
+#define _P2SB_SIDEBAND_ACCESS_LIB_H_
+
+#include 
+#include 
+#include  // For PCH_SBI_PID definition
+
+typedef PCH_SBI_PID  P2SB_PID;
+
+typedef enum {
+  P2SbMemory = 0,
+  P2SbPciConfig,
+  P2SbPrivateConfig
+} P2SB_REGISTER_SPACE;
+
+typedef enum {
+  MemoryRead = 0x0,
+  MemoryWrite= 0x1,
+  PciConfigRead  = 0x4,
+  PciConfigWrite = 0x5,
+  PrivateControlRead = 0x6,
+  PrivateControlWrite= 0x7,
+  GpioLockUnlock = 0x13
+} P2SB_SBI_OPCODE;
+
+typedef enum {
+  SBI_SUCCESSFUL  = 0,
+  SBI_UNSUCCESSFUL= 1,
+  SBI_POWERDOWN   = 2,
+  SBI_MIXED   = 3,
+  SBI_INVALID_RESPONSE
+} P2SB_SBI_RESPONSE;
+
+typedef enum {
+  P2SbMmioAccess = 0,
+  P2SbMsgAccess
+} P2SB_SIDEBAND_ACCESS_METHOD;
+
+/**
+  REGISTER_ACCESS for P2SB device to support access to sideband registers.
+  Be sure to keep first member of this structure as REGISTER_ACCESS to 
+allow
+  for correct casting between caller who sees this structure as 
+REGISTER_ACCESS
+  and calle who will cast it to P2SB_SIDEBAND_R

Re: [edk2-devel] [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components

Adds the following modules:
  - IpBlock/Pmc/IncludePrivate
  - IpBlock/Pmc/Library
  - IpBlock/Pmc/LibraryPrivate
  - IpBlock/Spi/IncludePrivate
  - IpBlock/Spi/Library
  - IpBlock/Spi/LibraryPrivate
  - IpBlock/Spi/Smm

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../IncludePrivate/Library/PmcPrivateLib.h|   47 +
 .../IpBlock/Pmc/IncludePrivate/PmcSocConfig.h |   67 +
 .../PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf   |   38 +
 .../Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c  |   50 +
 .../PeiDxeSmmPmcPrivateLib.inf|   43 +
 .../PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c|   86 ++
 .../Spi/IncludePrivate/Library/SpiCommonLib.h |  376 ++
 .../Spi/IncludePrivate/Register/SpiRegs.h |  116 ++
 .../IpBlock/Spi/Library/PeiSpiLib/PchSpi.c|  209 +++
 .../Spi/Library/PeiSpiLib/PeiSpiLib.inf   |   41 +
 .../BaseSpiCommonLib/BaseSpiCommonLib.inf |   29 +
 .../BaseSpiCommonLib/SpiCommon.c  | 1127 +
 .../AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c |  387 ++
 .../IpBlock/Spi/Smm/SpiSmm.inf|   46 +
 14 files changed, 2662 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
new file mode 100644
index 00..6ec244b127
--- /dev/null
+++ 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
@@ -0,0 +1,47 @@
+/** @file
+  Header file for private PmcLib.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_PRIVATE_LIB_H_
+#define _PMC_PRIVATE_LIB_H_
+
+#include 
+#include "Register/PmcRegs.h"
+
+typedef enum {
+  PmcSwSmiRate1p5ms = 0,
+  PmcSwSmiRate16ms,
+  PmcSwSmiRate32ms,
+  PmcSwSmiRate64ms
+} PMC_SWSMI_RATE;
+
+/**
+  This function sets SW SMI Rate.
+
+  @param[in] SwSmiRateRefer to PMC_SWSMI_RATE for possible values
+**/
+VOID
+PmcSetSwSmiRate (
+  IN PMC_SWSMI_RATE  SwSmiRate
+  );
+
+typedef enum {
+  PmcPeriodicSmiRate8s = 0,
+  PmcPeriodicSmiRate16s,
+  PmcPeriodicSmiRate32s,
+  PmcPeriodicSmiRate64s
+} PMC_PERIODIC_SMI_RATE;
+
+/**
+  This function sets Periodic SMI Rate.
+
+  @param[in] PeriodicSmiRateRefer to PMC_PERIODIC_SMI_RATE for 
possible values
+**/
+VOID
+PmcSetPeriodicSmiRate (
+  IN PMC_PERIODIC_SMI_RATEPeriodicSmiRate
+  );
+
+#endif // _PMC_PRIVATE_LIB_H_
diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
new file mode 100644
index 00..523a84a180
--- /dev/null
+++ 
b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
@@ -0,0 +1,67 @@
+/** @file
+  PMC SoC configuration
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PMC_SOC_CONFIGURATION_H_
+#define _PMC_SOC_CONFIGURATION_H_
+
+typedef enum {
+  AdrSinglePhase = 0,
+  AdrDualPhase
+} ADR_PHASE_TYPE;
+
+typedef enum {
+  AdrGpioB = 0,
+  AdrGpioC
+} ADR_GPIO;
+
+typed

Re: [edk2-devel] [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi 
Includes

Adds the following Includes:
  - Include/Library
  - Include/Pins
  - Include/Ppi

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Include/Library/ConfigBlockLib.h  |  64 +++
 .../Include/Library/EspiLib.h |  34 ++
 .../Include/Library/GpioConfig.h  | 372 ++
 .../Include/Library/GpioLib.h | 174 
 .../Include/Library/GpioNativeLib.h   | 135 +++
 .../Include/Library/GraphicsInfoLib.h |  46 +++
 .../Include/Library/MmPciLib.h|  27 ++
 .../Include/Library/PchPcieRpLib.h|  41 ++
 .../Include/Library/PchPcrLib.h   | 221 +++
 .../Library/PeiDxeSmmReserveMmio64SizeLib.h   |  21 +
 .../Include/Library/PeiSiPolicyUpdateLib.h| 154 
 .../Include/Library/PmcLib.h  |  40 ++
 .../Include/Library/ResetSystemLib.h  |  68 
 .../Include/Library/SecPlatformLib.h  |  81 
 .../Include/Library/SiConfigBlockLib.h|  56 +++
 .../Include/Library/SiPolicyLib.h |  39 ++
 .../Include/Library/SpiLib.h  |  21 +
 .../Include/Pins/GpioPinsVer2Lp.h |  36 ++
 .../Include/Ppi/FspmArchConfigPpi.h   |  32 ++
 .../Include/Ppi/PeiPreMemSiDefaultPolicy.h|  33 ++
 .../Include/Ppi/PeiSiDefaultPolicy.h  |  33 ++
 .../AlderlakeSiliconPkg/Include/Ppi/Spi.h |  29 ++
 .../AlderlakeSiliconPkg/Include/Ppi/Wdt.h |  22 ++
 23 files changed, 1779 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h

diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h 
b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
new file mode 100644
index 00..d9966c76e9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
@@ -0,0 +1,64 @@
+/** @file
+  Header file for Config Block Lib implementation
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_LIB_H_
+#define _CONFIG_BLOCK_LIB_H_
+
+/**
+  Create config block table
+
+  @param[in] TotalSize- Max size to be allocated for 
the Config Block Table
+  @param[out]ConfigBlockTableAddress  - On return, points to a pointer 
to the beginning of Config Block Table Address
+
+  @retval EFI_INVALID_PARAMETER - Invalid Parameter
+  @retval EFI_OUT_OF_RESOURCES  - Out of resources
+  @retval EFI_SUCCESS   - Successfully created Config Block Table at 
ConfigBlockTableAddress
+**/
+EFI_STATUS
+EFIAPI
+CreateConfigBlockTable (
+  IN UINT16TotalSize,
+  OUTVOID  **ConfigBlockTableAddress
+  );
+
+/*

Re: [edk2-devel] [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru

Adds the following modules:
  - AdlCpu/CpuPcieRp
  - AdlCpu/Include
  - AdlCpu/IncludePrivate
  - AdlCpu/LibraryPrivate
  - AdlCpu/PeiReportCpuHob
  - AdlCpu DSCs

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Fru/AdlCpu/CommonLib.dsc  |   9 +
 .../CpuPcieInfoFruLib.c   |  87 ++
 .../PeiDxeSmmCpuPcieInfoFruLib.inf|  39 +
 .../AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc |   8 +
 .../Fru/AdlCpu/Include/CpuGenInfo.h   |  42 +
 .../Include/Library/CpuPcieInfoFruLib.h   |  45 +
 .../Include/Register/SaRegsHostBridge.h   |  64 +++
 .../AdlCpu/IncludePrivate/CpuGenInfoFruLib.h  |  44 +  
.../AdlCpu/IncludePrivate/Register/IgdRegs.h  |  34 
 .../BaseCpuInfoFruLib/BaseCpuInfoFruLib.c | 164 ++
 .../BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf   |  29 
 .../PeiReportCpuHobLib/PeiReportCpuHobLib.c   |  22 +++
 .../PeiReportCpuHobLib/PeiReportCpuHobLib.inf |  26 +++
 13 files changed, 613 insertions(+)
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf

diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc 
b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
new file mode 100644
index 00..35a3cce916
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
@@ -0,0 +1,9 @@
+## @file
+#  Component description file for the AlderLake CPU Common FRU libraries.
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+CpuPcieInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/CpuPcieRp/Library/P
+CpuPcieInfoFruLib|eiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.
+CpuPcieInfoFruLib|inf
+CpuInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/LibraryPrivate/BaseCpuI
+CpuInfoFruLib|nfoFruLib/BaseCpuInfoFruLib.inf
diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
 
b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
new file mode 100644
index 00..277b73fe67
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/Pei
+++ DxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
@@ -0,0 +1,87 @@
+/** @file
+  CPU PCIe information library.
+
+  All function in this library is available for PEI, DXE, and SMM,  But 
+ do not support UEFI RUNTIME environment call.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include 
+ #include  #include 
+ #include  #include 
+ #include  
+#include  #include 
+
+/**
+  Get Maximum CPU Pcie Root Port Number
+
+  @retval Maximum CPU Pcie Root Port Number **/
+UINT8
+GetMaxCpuPciePortNum (
+  VOID
+  )
+{
+  switch (GetCpuSku ()) {
+case EnumCpuUlt:
+  return CPU_PCIE_ULT_MAX_ROOT_PORT;
+case EnumCpuUlx:
+  return CPU_PCIE_ULX_MAX_ROOT_PORT;
+default:
+  return CPU_PCIE_ULT_MAX_ROOT_PORT;
+  }
+}
+
+/**
+  Get CPU Pcie Root Port Device and Function Number by Root Port 
+physical Number
+
+  @param[in]  RpNumber  Root port physical number. (0-based)
+  @param[out] RpDev Return corresponding root port device 
number.
+

Re: [edk2-devel] [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, 
Other Includes

Adds the following Includes:
  - Include/
  - Include/Protocol
  - Include/Register

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../AlderlakeSiliconPkg/Include/ConfigBlock.h |  53 +++
 .../AlderlakeSiliconPkg/Include/CpuPcieHob.h  |  48 +++
 .../Include/Protocol/IgdOpRegion.h|  22 ++
 .../Include/Protocol/Spi.h| 346 ++
 .../Include/Protocol/Wdt.h| 111 ++
 .../Include/Register/FlashRegs.h  |  73 
 .../Include/Register/GpioRegs.h   | 103 ++
 .../Include/Register/GpioRegsVer2.h   | 211 +++
 .../Include/Register/PchDmi14Regs.h   |  49 +++
 .../Include/Register/PchDmiRegs.h |  51 +++
 .../Include/Register/PchPcieRpRegs.h  |  45 +++
 .../Include/Register/PchRegsLpc.h |  77 
 .../Include/Register/PmcRegs.h| 134 +++
 .../Include/Register/RtcRegs.h|  44 +++
 .../Include/Register/TcoRegs.h|  71 
 .../Include/SerialIoDevices.h | 226 
 .../AlderlakeSiliconPkg/Include/SiConfigHob.h |  17 +
 .../Include/SiPolicyStruct.h  |  64 
 18 files changed, 1745 insertions(+)
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h

diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h 
b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
new file mode 100644
index 00..2e609bc8d9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
@@ -0,0 +1,53 @@
+/** @file
+  Header file for Config Block Lib implementation
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_H_
+#define _CONFIG_BLOCK_H_
+
+#include 
+#include 
+#include 
+#include 
+
+#pragma pack (push,1)
+
+///
+/// Config Block Header
+///
+typedef struct _CONFIG_BLOCK_HEADER {
+  EFI_HOB_GUID_TYPE GuidHob;  ///< Offset 0-23  GUID 
extension HOB header
+  UINT8 Revision; ///< Offset 24Revision 
of this config block
+  UINT8 Attributes;   ///< Offset 25The main 
revision for config block
+  UINT8 Reserved[2];  ///< Offset 26-27 Reserved 
for future use
+} CONFIG_BLOCK_HEADER;
+
+///
+/// Config Block
+///
+typedef struct _CONFIG_BLOCK {
+  CONFIG_BLOCK_HEADERHeader;  ///< Offset 0-27  Header of 
config block
+  //
+  // Config Block Data
+  //
+} CONFIG_BLOCK;
+
+///
+/// Config Block Table Header
+///
+typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
+  CONFIG_BLOCK_HEADERHeader;  ///< Offset 0-27  GUID 
number for main entry of config block
+  UINT8  Rsvd0[2];///< Offset 28-29 Reserved 
for future use
+  UINT16 NumberOfBlocks;  ///< Offset 30-31 Number of 
config blocks (N)
+  UINT32 AvailableSize;   ///< Offset 32-35 Current 
config block table size
+///
+/// Individual Config Block Structures are added here in memory as part of 
AddConfigBlock()
+///
+} CONFIG_BLOCK_TABLE_HEADER;
+#prag

Re: [edk2-devel] [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and 
IncludePrivate modules

Adds the following modules:
  - AdlPch/Include
  - AdlPch/IncludePrivate
  - AdlPch/Library
  - AdlPch DSCs
  - IncludePrivate

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Fru/AdlPch/CommonLib.dsc  |  29 ++
 .../AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc|  10 +
 .../AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc |   7 +
 .../Fru/AdlPch/Include/PchBdfAssignment.h |  81 +
 .../Fru/AdlPch/Include/PchLimits.h|  47 +++
 .../Fru/AdlPch/Include/PchPcieRpInfo.h|  17 ++
 .../Fru/AdlPch/Include/PchReservedResources.h |  13 +  
.../AdlPch/Include/PchReservedResourcesAdpP.h |  36 +++
 .../IncludePrivate/Register/PchPcrRegs.h  |  59 
 .../IncludePrivate/Register/PchRegsLpcAdl.h   |  30 ++
 .../PeiDxeSmmPchInfoLib/PchInfoLibAdl.c   | 223 ++
 .../PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h   |  44 +++
 .../PeiDxeSmmPchInfoLibAdl.inf|  37 +++
 .../AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc|   7 +
 .../AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc |  12 +
 .../IncludePrivate/RegisterAccess.h   | 288 ++
 16 files changed, 940 insertions(+)
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h

diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc 
b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
new file mode 100644
index 00..3f508f83a1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
@@ -0,0 +1,29 @@
+## @file
+#  Component description file for the AlderLake PCH Common FRU libraries.
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+  
+ PchPcrLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/Library/PeiDxeSmmPchPcrL
+ ib/PeiDxeSmmPchPcrLib.inf  
+ PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPrivate/Pei
+ DxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
+  
+ P2SbSidebandAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPriva
+ te/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
+
+  
+ EspiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Espi/Library/PeiDxeSmmEspiLib/P
+ eiDxeSmmEspiLib.inf
+
+
+  
+ PmcLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiD
+ xeSmmPmcLib.inf  
+ PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/LibraryPrivate/PeiDxe
+ SmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
+  
+ SpiCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/LibraryPrivate/BaseSpi
+ CommonLib/BaseSpiCommonLib.inf  
+ GpioLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/P
+ eiDxeSmmGpioLib.inf  
+ PchDmiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PchDmi/LibraryPrivate/PeiDxeS
+ mmPchDmiLib/PeiDxeSmmPchDmiLib.inf
+
+  
+ GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiD
+ xeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
+  
+ PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/Library/PeiDxeSmmPc
+ hPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
+
+
+  #
+  # Common FRU Libraries
+  #
+  
+ PchInfoLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlPch/Library/PeiDxeSmmPchInfoL
+ ib/PeiDxeSmmPchInfoLibAdl.inf
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc 
b/Silicon/Intel/Alder

Re: [edk2-devel] [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Kasbekar, Saloni  
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Chuang, Rosen 
Subject: [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and 
SiPkg.dec

Adds the following modules:
  - Product/Alderlake/Include
  - Product/Alderlake/Library
  - Product/Alderlake DSCs
  - SiPkg.dec

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Rosen Chuang 
Signed-off-by: Saloni Kasbekar 
---
 .../Product/Alderlake/Include/Ppi/SiPolicy.h  |  55 ++
 .../Library/PeiSiPolicyLib/PeiSiPolicyLib.c   |  47 ++
 .../Library/PeiSiPolicyLib/PeiSiPolicyLib.inf |  47 ++
 .../PeiSiPolicyLib/PeiSiPolicyLibPreMem.c |  47 ++
 .../PeiSiPolicyLib/PeiSiPolicyLibrary.h   |  21 +
 .../Product/Alderlake/SiPkgBuildOption.dsc| 122 
 .../Product/Alderlake/SiPkgCommonLib.dsc  |  36 +
 .../Product/Alderlake/SiPkgDxe.dsc|  32 +
 .../Product/Alderlake/SiPkgDxeLib.dsc |  23 +
 .../Product/Alderlake/SiPkgPeiLib.dsc |  19 +
 Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec   | 625 ++
 11 files changed, 1074 insertions(+)
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc
 create mode 100644 
Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec

diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h 
b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
new file mode 100644
index 00..703f0221bd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/Si
+++ Policy.h
@@ -0,0 +1,55 @@
+/** @file
+  Silicon Policy PPI is used for specifying platform
+  related Intel silicon information and policy setting.
+  This PPI is consumed by the silicon PEI modules and carried
+  over to silicon DXE modules.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _SI_POLICY_PPI_H_
+#define _SI_POLICY_PPI_H_
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifndef DISABLED
+#define DISABLED  0
+#endif
+#ifndef ENABLED
+#define ENABLED   1
+#endif
+
+extern EFI_GUID gSiPreMemPolicyPpiGuid; extern EFI_GUID 
+gSiPolicyPpiGuid;
+
+
+#include 
+
+
+#include 
+#include 
+extern EFI_GUID gCpuPciePeiPreMemConfigGuid; extern EFI_GUID 
+gCpuPcieRpConfigGuid;
+
+#include 
+extern EFI_GUID gMemoryConfigGuid;
+extern EFI_GUID gMemoryConfigNoCrcGuid;
+
+#include 
+extern EFI_GUID gSaMiscPeiPreMemConfigGuid;
+
+#include 
+extern EFI_GUID gHostBridgePeiPreMemConfigGuid; extern EFI_GUID 
+gHostBridgePeiConfigGuid;
+
+typedef struct _SI_PREMEM_POLICY_STRUCT SI_PREMEM_POLICY_PPI; typedef 
+struct _SI_POLICY_STRUCT SI_POLICY_PPI;
+
+#endif // _SI_POLICY_PPI_H_
diff --git 
a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
 
b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
new file mode 100644
index 00..886415bdaa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiP
+++ olicyLib/PeiSiPolicyLib.c
@@ -0,0 +1,47 @@
+/** @file
+  This file is PeiSiPolicyLib library creates default settings of RC
+  Policy and installs RC Policy PPI.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include 
+"PeiSiPolicyLibrary.h"
+#include 
+#include 
+
+
+/**
+  SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+  While installed, RC assumes the Policy is ready and finalized. So 
+please update and override
+  any setting before calling this function.
+
+  @retval EFI_SUCCESSThe policy is installed.
+  @retval EFI_OUT_OF_RESOURCES   Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+  VOID
+  )
+{
+  EFI_STATUS Status;
+  EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPpiDesc;
+
+  SiPolicyReadyPpiDesc = (EFI_PEI_P