[edk2-devel] [PATCH 0/3] Enable perf-logging in SMM environment
Ray Ni (3): UefiCpuPkg/CpuSmm: Add perf-logging for time-consuming BSP procedures UefiCpuPkg/CpuSmm: Add perf-logging for MP procedures MdeModulePkg/SmmCore: Add perf-logging for time-consuming procedures MdeModulePkg/Core/PiSmmCore/PiSmmCore.c | 14 ++- MdeModulePkg/Core/PiSmmCore/Smi.c | 6 ++ UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 42 - UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c| 38 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h| 2 + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 3 + .../PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 13 ++- UefiCpuPkg/PiSmmCpuDxeSmm/SmmMpPerf.c | 91 +++ UefiCpuPkg/PiSmmCpuDxeSmm/SmmMpPerf.h | 77 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c| 4 +- 10 files changed, 284 insertions(+), 6 deletions(-) create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/SmmMpPerf.c create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/SmmMpPerf.h -- 2.39.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105331): https://edk2.groups.io/g/devel/message/105331 Mute This Topic: https://groups.io/mt/99150952/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/9847357/21656/1706620634/xyzzy [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 2/3] UefiCpuPkg/CpuSmm: Add perf-logging for MP procedures
MP procedures are those procedures that run in every CPU thread.
The EDKII perf infra is not MP safe so it doesn't support to be called
from those MP procedures.
The patch adds SMM MP perf-logging support in SmmMpPerf.c.
The following procedures are perf-logged:
* SmmInitHandler
* SmmCpuFeaturesRendezvousEntry
* PlatformValidSmi
* SmmCpuFeaturesRendezvousExit
Cc: Eric Dong
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Cc: Jiaxin Wu
---
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c| 34
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 11 +++
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 1 +
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 2 +
UefiCpuPkg/PiSmmCpuDxeSmm/SmmMpPerf.c| 91
UefiCpuPkg/PiSmmCpuDxeSmm/SmmMpPerf.h| 77 +
6 files changed, 216 insertions(+)
create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/SmmMpPerf.c
create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/SmmMpPerf.h
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index fa666bd118..bcd90f0671 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -778,6 +778,15 @@ BSPHandler (
//
WaitForAllAPs (ApCount);
+ //
+ // At this point, all APs should have exited from APHandler().
+ // Migrate the SMM MP performance logging to standard SMM performance
logging.
+ // Any SMM MP performance logging after this point will be migrated in next
SMI.
+ //
+ PERF_CODE (
+MigrateMpPerf (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus);
+);
+
//
// Reset the tokens buffer.
//
@@ -1769,12 +1778,24 @@ SmiRendezvous (
//
// Perform CPU specific entry hooks
//
+ PERF_CODE (
+MpPerfBegin (CpuIndex, SMM_MP_PERF_PROCEDURE_ID (SmmRendezvousEntry));
+);
SmmCpuFeaturesRendezvousEntry (CpuIndex);
+ PERF_CODE (
+MpPerfEnd (CpuIndex, SMM_MP_PERF_PROCEDURE_ID (SmmRendezvousEntry));
+);
//
// Determine if this is a valid SMI
//
+ PERF_CODE (
+MpPerfBegin (CpuIndex, SMM_MP_PERF_PROCEDURE_ID (PlatformValidSmi));
+);
ValidSmi = PlatformValidSmi ();
+ PERF_CODE (
+MpPerfEnd (CpuIndex, SMM_MP_PERF_PROCEDURE_ID (PlatformValidSmi));
+);
//
// Determine if BSP has been already in progress. Note this must be checked
after
@@ -1904,7 +1925,20 @@ SmiRendezvous (
}
Exit:
+ //
+ // Note: SmmRendezvousExit perf-logging entry is the only one that will be
+ // migrated to standard perf-logging database in next SMI by
BSPHandler().
+ // Hence, the number of SmmRendezvousEntry entries will be larger than
+ // the number of SmmRendezvousExit entries. Delta equals to the number
+ // of CPU threads.
+ //
+ PERF_CODE (
+MpPerfBegin (CpuIndex, SMM_MP_PERF_PROCEDURE_ID (SmmRendezvousExit));
+);
SmmCpuFeaturesRendezvousExit (CpuIndex);
+ PERF_CODE (
+MpPerfEnd (CpuIndex, SMM_MP_PERF_PROCEDURE_ID (SmmRendezvousExit));
+);
//
// Restore Cr2
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 2fc7dda682..5afab1e040 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -362,6 +362,9 @@ SmmInitHandler (
for (Index = 0; Index < mNumberOfCpus; Index++) {
if (ApicId == (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {
+ PERF_CODE (
+MpPerfBegin (Index, SMM_MP_PERF_PROCEDURE_ID (SmmInitHandler));
+);
//
// Initialize SMM specific features on the currently executing CPU
//
@@ -392,6 +395,10 @@ SmmInitHandler (
SemaphoreHook (Index, &mRebased[Index]);
}
+ PERF_CODE (
+MpPerfEnd (Index, SMM_MP_PERF_PROCEDURE_ID (SmmInitHandler));
+);
+
return;
}
}
@@ -699,6 +706,10 @@ PiCpuSmmEntry (
gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus = mMaxNumberOfCpus;
+ PERF_CODE (
+InitializeMpPerf (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus);
+);
+
//
// The CPU save state and code for the SMI entry point are tiled within an
SMRAM
// allocated buffer. The minimum size of this buffer for a uniprocessor
system
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index b03f2ef882..1876a27cae 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -60,6 +60,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "CpuService.h"
#include "SmmProfile.h"
+#include "SmmMpPerf.h"
//
// CET definition
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
index af66a1941c..4864532c35 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
@@ -42,6 +42,8 @@
SmmCpuMemoryManagement.c
SmmMp.h
SmmMp.c
+ SmmMpPerf.h
+ SmmMpPerf.c
[Sources.Ia32]
Ia32/Sem
[edk2-devel] [PATCH 1/3] UefiCpuPkg/CpuSmm: Add perf-logging for time-consuming BSP procedures
The patch adds perf-logging for the following potential
time-consuming BSP procedures:
* PiCpuSmmEntry
- SmmRelocateBases
* ExecuteFirstSmiInit
* BSPHandler
- SmmWaitForApArrival
- PerformRemainingTasks
* InitPaging
* SetMemMapAttributes
* SetUefiMemMapAttributes
* SetPageTableAttributes
* ConfigSmmCodeAccessCheck
* SmmCpuFeaturesCompleteSmmReadyToLock
Cc: Eric Dong
Cc: Rahul Kumar
Cc: Gerd Hoffmann
---
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 8 +-
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c| 27 +++
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h| 1 +
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 1 +
.../PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 13 ++---
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c| 4 ++-
6 files changed, 49 insertions(+), 5 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index baf827cf9d..fa666bd118 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -351,6 +351,8 @@ SmmWaitForApArrival (
UINT32 DelayedCount;
UINT32 BlockedCount;
+ PERF_FUNCTION_BEGIN ();
+
DelayedCount = 0;
BlockedCount = 0;
@@ -439,7 +441,7 @@ SmmWaitForApArrival (
DEBUG ((DEBUG_INFO, "SmmWaitForApArrival: Delayed AP Count = %d, Blocked
AP Count = %d\n", DelayedCount, BlockedCount));
}
- return;
+ PERF_FUNCTION_END ();
}
/**
@@ -577,6 +579,8 @@ BSPHandler (
ASSERT (CpuIndex == mSmmMpSyncData->BspIndex);
ApCount = 0;
+ PERF_FUNCTION_BEGIN ();
+
//
// Flag BSP's presence
//
@@ -792,6 +796,8 @@ BSPHandler (
*mSmmMpSyncData->Counter = 0;
*mSmmMpSyncData->AllCpusInSync= FALSE;
mSmmMpSyncData->AllApArrivedWithException = FALSE;
+
+ PERF_FUNCTION_END ();
}
/**
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index c0e368ea94..2fc7dda682 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -410,12 +410,15 @@ ExecuteFirstSmiInit (
{
UINTN Index;
+ PERF_FUNCTION_BEGIN ();
+
if (mSmmInitialized == NULL) {
mSmmInitialized = (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) *
mMaxNumberOfCpus);
}
ASSERT (mSmmInitialized != NULL);
if (mSmmInitialized == NULL) {
+PERF_FUNCTION_END ();
return;
}
@@ -442,6 +445,8 @@ ExecuteFirstSmiInit (
while (!(BOOLEAN)mSmmInitialized[Index]) {
}
}
+
+ PERF_FUNCTION_END ();
}
/**
@@ -463,6 +468,8 @@ SmmRelocateBases (
UINTN Index;
UINTN BspIndex;
+ PERF_FUNCTION_BEGIN ();
+
//
// Make sure the reserved size is large enough for procedure SmmInitTemplate.
//
@@ -540,6 +547,7 @@ SmmRelocateBases (
//
CopyMem (CpuStatePtr, &BakBuf2, sizeof (BakBuf2));
CopyMem (U8Ptr, BakBuf, sizeof (BakBuf));
+ PERF_FUNCTION_END ();
}
/**
@@ -617,6 +625,8 @@ PiCpuSmmEntry (
GuidHob= NULL;
SmmBaseHobData = NULL;
+ PERF_FUNCTION_BEGIN ();
+
//
// Initialize address fixup
//
@@ -1194,6 +1204,7 @@ PiCpuSmmEntry (
DEBUG ((DEBUG_INFO, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));
+ PERF_FUNCTION_END ();
return EFI_SUCCESS;
}
@@ -1348,12 +1359,15 @@ ConfigSmmCodeAccessCheck (
UINTN Index;
EFI_STATUS Status;
+ PERF_FUNCTION_BEGIN ();
+
//
// Check to see if the Feature Control MSR is supported on this CPU
//
Index = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu;
if (!SmmCpuFeaturesIsSmmRegisterSupported (Index, SmmRegFeatureControl)) {
mSmmCodeAccessCheckEnable = FALSE;
+PERF_FUNCTION_END ();
return;
}
@@ -1363,6 +1377,7 @@ ConfigSmmCodeAccessCheck (
//
if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) == 0) {
mSmmCodeAccessCheckEnable = FALSE;
+PERF_FUNCTION_END ();
return;
}
@@ -1419,6 +1434,8 @@ ConfigSmmCodeAccessCheck (
ReleaseSpinLock (mConfigSmmCodeAccessCheckLock);
}
}
+
+ PERF_FUNCTION_END ();
}
/**
@@ -1540,6 +1557,8 @@ PerformRemainingTasks (
)
{
if (mSmmReadyToLock) {
+PERF_FUNCTION_BEGIN ();
+
//
// Start SMM Profile feature
//
@@ -1574,12 +1593,20 @@ PerformRemainingTasks (
//
ConfigSmmCodeAccessCheck ();
+//
+// Measure performance of SmmCpuFeaturesCompleteSmmReadyToLock() from
caller side
+// as the implementation is provided by platform.
+//
+PERF_START (NULL, "SmmCompleteReadyToLock", NULL, 0);
SmmCpuFeaturesCompleteSmmReadyToLock ();
+PERF_END (NULL, "SmmCompleteReadyToLock", NULL, 0);
//
// Clean SMM ready to lock flag
//
mSmmReadyToLock = FALSE;
+
+PERF_FUNCTION_END ();
}
}
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index a5c2bdd971..b03f2ef882 100644
--- a/UefiCpuPkg/PiSmmCpuD
[edk2-devel] [PATCH 3/3] MdeModulePkg/SmmCore: Add perf-logging for time-consuming procedures
Following procedures are perf-logged:
* SmmReadyToBootHandler
* SmmReadyToLockHandler
* SmmEndOfDxeHandler
* SmmEntryPoint
(It's the main routine run in BSP when SMI happens.)
* SmiManage
Cc: Jian J Wang
Cc: Liming Gao
Cc: Jiaxin Wu
---
MdeModulePkg/Core/PiSmmCore/PiSmmCore.c | 14 +-
MdeModulePkg/Core/PiSmmCore/Smi.c | 6 ++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/MdeModulePkg/Core/PiSmmCore/PiSmmCore.c
b/MdeModulePkg/Core/PiSmmCore/PiSmmCore.c
index 875c7c0258..a15afa8dd6 100644
--- a/MdeModulePkg/Core/PiSmmCore/PiSmmCore.c
+++ b/MdeModulePkg/Core/PiSmmCore/PiSmmCore.c
@@ -1,7 +1,7 @@
/** @file
SMM Core Main Entry Point
- Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -304,6 +304,7 @@ SmmReadyToBootHandler (
{
EFI_STATUS Status;
EFI_HANDLE SmmHandle;
+ PERF_CALLBACK_BEGIN (&gEfiEventReadyToBootGuid);
//
// Install SMM Ready To Boot protocol.
@@ -318,6 +319,7 @@ SmmReadyToBootHandler (
SmiHandlerUnRegister (DispatchHandle);
+ PERF_CALLBACK_END (&gEfiEventReadyToBootGuid);
return Status;
}
@@ -352,6 +354,8 @@ SmmReadyToLockHandler (
EFI_HANDLE SmmHandle;
VOID*Interface;
+ PERF_CALLBACK_BEGIN (&gEfiDxeSmmReadyToLockProtocolGuid);
+
//
// Unregister SMI Handlers that are no required after the SMM driver
dispatch is stopped
//
@@ -408,6 +412,7 @@ SmmReadyToLockHandler (
SmramProfileReadyToLock ();
+ PERF_CALLBACK_END (&gEfiDxeSmmReadyToLockProtocolGuid);
return Status;
}
@@ -442,6 +447,8 @@ SmmEndOfDxeHandler (
DEBUG ((DEBUG_INFO, "SmmEndOfDxeHandler\n"));
+ PERF_CALLBACK_BEGIN (&gEfiEndOfDxeEventGroupGuid);
+
//
// Install SMM EndOfDxe protocol
//
@@ -479,6 +486,7 @@ SmmEndOfDxeHandler (
}
}
+ PERF_CALLBACK_END (&gEfiEndOfDxeEventGroupGuid);
return EFI_SUCCESS;
}
@@ -669,6 +677,8 @@ SmmEntryPoint (
VOID*CommunicationBuffer;
UINTN BufferSize;
+ PERF_FUNCTION_BEGIN ();
+
//
// Update SMST with contents of the SmmEntryContext structure
//
@@ -769,6 +779,8 @@ SmmEntryPoint (
//
gSmmCorePrivate->InSmm = FALSE;
}
+
+ PERF_FUNCTION_END ();
}
/**
diff --git a/MdeModulePkg/Core/PiSmmCore/Smi.c
b/MdeModulePkg/Core/PiSmmCore/Smi.c
index 6d13969979..2985f989c3 100644
--- a/MdeModulePkg/Core/PiSmmCore/Smi.c
+++ b/MdeModulePkg/Core/PiSmmCore/Smi.c
@@ -109,6 +109,8 @@ SmiManage (
BOOLEAN SuccessReturn;
EFI_STATUS Status;
+ PERF_FUNCTION_BEGIN ();
+
Status= EFI_NOT_FOUND;
SuccessReturn = FALSE;
if (HandlerType == NULL) {
@@ -125,6 +127,7 @@ SmiManage (
//
// There is no handler registered for this interrupt source
//
+ PERF_FUNCTION_END ();
return Status;
}
}
@@ -148,6 +151,7 @@ SmiManage (
// no additional handlers will be processed and EFI_INTERRUPT_PENDING
will be returned.
//
if (HandlerType != NULL) {
+ PERF_FUNCTION_END ();
return EFI_INTERRUPT_PENDING;
}
@@ -160,6 +164,7 @@ SmiManage (
// additional handlers will be processed.
//
if (HandlerType != NULL) {
+ PERF_FUNCTION_END ();
return EFI_SUCCESS;
}
@@ -194,6 +199,7 @@ SmiManage (
Status = EFI_SUCCESS;
}
+ PERF_FUNCTION_END ();
return Status;
}
--
2.39.1.windows.1
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Re: [edk2-devel] [PATCH v1] BaseTools: toolsetup.bat always execute PYTHON_HOME
On 5/25/23 6:09 PM, gua@intel.com wrote: -%PYTHON_COMMAND% %BASE_TOOLS_PATH%\Tests\PythonTest.py %PYTHON_VER_MAJOR% %PYTHON_VER_MINOR% >NUL 2>NUL -if %ERRORLEVEL% EQU 1 ( - echo. - echo !!! ERROR !!! Python %PYTHON_VER_MAJOR%.%PYTHON_VER_MINOR% or newer is required. - echo. - goto end + %PYTHON_COMMAND% %BASE_TOOLS_PATH%\Tests\PythonTest.py %PYTHON_VER_MAJOR% %PYTHON_VER_MINOR% >NUL 2>NUL + if %ERRORLEVEL% EQU 1 ( +echo. +echo !!! ERROR !!! Python %PYTHON_VER_MAJOR%.%PYTHON_VER_MINOR% or newer is required. +echo. +goto end + ) ) If PYTHON_COMMAND is already defined we do still want to check it's a version we can use. So I don't think this part of the change is correct. -- Rebecca Cran -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105335): https://edk2.groups.io/g/devel/message/105335 Mute This Topic: https://groups.io/mt/99141348/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v1] BaseTools: toolsetup.bat always execute PYTHON_HOME
@Rebecca Cran I update v2 patch on the PR https://github.com/tianocore/edk2/pull/4431 Could you help to check about whether meet your expectation ? Thanks, Gua -Original Message- From: Rebecca Cran Sent: Saturday, May 27, 2023 12:30 AM To: Guo, Gua ; devel@edk2.groups.io Cc: Gao, Liming ; Feng, Bob C ; Chen, Christine Subject: Re: [PATCH v1] BaseTools: toolsetup.bat always execute PYTHON_HOME On 5/25/23 6:09 PM, gua@intel.com wrote: > > -%PYTHON_COMMAND% %BASE_TOOLS_PATH%\Tests\PythonTest.py > %PYTHON_VER_MAJOR% %PYTHON_VER_MINOR% >NUL 2>NUL -if %ERRORLEVEL% EQU > 1 ( > - echo. > - echo !!! ERROR !!! Python %PYTHON_VER_MAJOR%.%PYTHON_VER_MINOR% or newer > is required. > - echo. > - goto end > + %PYTHON_COMMAND% %BASE_TOOLS_PATH%\Tests\PythonTest.py > + %PYTHON_VER_MAJOR% %PYTHON_VER_MINOR% >NUL 2>NUL if %ERRORLEVEL% EQU 1 ( > +echo. > +echo !!! ERROR !!! Python %PYTHON_VER_MAJOR%.%PYTHON_VER_MINOR% or newer > is required. > +echo. > +goto end > + ) > ) If PYTHON_COMMAND is already defined we do still want to check it's a version we can use. So I don't think this part of the change is correct. -- Rebecca Cran -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105336): https://edk2.groups.io/g/devel/message/105336 Mute This Topic: https://groups.io/mt/99141348/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v1] BaseTools: toolsetup.bat always execute PYTHON_HOME
That looks good. Thanks! -- Rebecca Cran On 5/26/23 10:56 AM, Guo, Gua wrote: @Rebecca Cran I update v2 patch on the PR https://github.com/tianocore/edk2/pull/4431 Could you help to check about whether meet your expectation ? Thanks, Gua -Original Message- From: Rebecca Cran Sent: Saturday, May 27, 2023 12:30 AM To: Guo, Gua ; devel@edk2.groups.io Cc: Gao, Liming ; Feng, Bob C ; Chen, Christine Subject: Re: [PATCH v1] BaseTools: toolsetup.bat always execute PYTHON_HOME On 5/25/23 6:09 PM, gua@intel.com wrote: -%PYTHON_COMMAND% %BASE_TOOLS_PATH%\Tests\PythonTest.py %PYTHON_VER_MAJOR% %PYTHON_VER_MINOR% >NUL 2>NUL -if %ERRORLEVEL% EQU 1 ( - echo. - echo !!! ERROR !!! Python %PYTHON_VER_MAJOR%.%PYTHON_VER_MINOR% or newer is required. - echo. - goto end + %PYTHON_COMMAND% %BASE_TOOLS_PATH%\Tests\PythonTest.py + %PYTHON_VER_MAJOR% %PYTHON_VER_MINOR% >NUL 2>NUL if %ERRORLEVEL% EQU 1 ( +echo. +echo !!! ERROR !!! Python %PYTHON_VER_MAJOR%.%PYTHON_VER_MINOR% or newer is required. +echo. +goto end + ) ) If PYTHON_COMMAND is already defined we do still want to check it's a version we can use. So I don't think this part of the change is correct. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105337): https://edk2.groups.io/g/devel/message/105337 Mute This Topic: https://groups.io/mt/99141348/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v3 0/7] RISC-V: MMU support
RISC-V: Add MMU support This series adds MMU support for RISC-V. Only SV39/48/57 modes are supported and tested. The MMU is required to support setting page attribute which is the first basic step to support security booting on RISC-V. There are three parts: 1. Add MMU base library. MMU will be enabled during CpuDxe initialization. 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address to GCD if already done. 3. Fix all resources should be populated in HOB or added to GCD by driver before accessing when MMU enabled. All changes can be found in the branch tphan/riscv_mmu at: https://github.com/pttuan/edk2.git Changes in v3: - Move MMU library to UefiCpuPkg. - Add Andrei reviewed-by. Changes in v2: - Move MMU core to a library. - Setup SATP mode as highest possible that HW supports. Tuan Phan (7): MdePkg/BaseLib: RISC-V: Support getting satp register value MdePkg/Register: RISC-V: Add satp mode bits shift definition UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode OvmfPkg/RiscVVirt: Remove satp bare mode setting OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices MdePkg/Include/Library/BaseLib.h | 5 + .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + .../VirtNorFlashStaticLib.c | 3 +- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + OvmfPkg/RiscVVirt/Sec/Memory.c| 18 +- OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++ OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf| 2 + UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 39 ++ .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++ .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 26 + .../Library/BaseRiscVMmuLib/RiscVMmuCore.S| 31 + 16 files changed, 777 insertions(+), 31 deletions(-) create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105339): https://edk2.groups.io/g/devel/message/105339 Mute This Topic: https://groups.io/mt/99159992/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v3 1/7] MdePkg/BaseLib: RISC-V: Support getting satp register value
Add an API to retrieve satp register value. Signed-off-by: Tuan Phan Reviewed-by: Andrei Warkentin --- MdePkg/Include/Library/BaseLib.h | 5 + MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 2 files changed, 13 insertions(+) diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 8f2df76c29a3..5d7067ee854e 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -181,6 +181,11 @@ RiscVSetSupervisorAddressTranslationRegister ( IN UINT64 ); +UINT64 +RiscVGetSupervisorAddressTranslationRegister ( + VOID + ); + UINT64 RiscVReadTimer ( VOID diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S index ac8f92f38aed..c9cf60c1664b 100644 --- a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S @@ -21,3 +21,11 @@ ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister) csrw CSR_SATP, a0 ret + +// +// Get the value of Supervisor Address Translation and +// Protection Register. +// +ASM_FUNC (RiscVGetSupervisorAddressTranslationRegister) +csrr a0, CSR_SATP +ret -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105340): https://edk2.groups.io/g/devel/message/105340 Mute This Topic: https://groups.io/mt/99159993/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v3 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition
The satp mode bits shift is used cross modules. It should be defined in one place. Signed-off-by: Tuan Phan Reviewed-by: Andrei Warkentin --- MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h index 5c2989b797bf..2bde8db478ff 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -58,9 +58,10 @@ #define PRV_S 1UL #define PRV_M 3UL -#define SATP64_MODE 0xF000ULL -#define SATP64_ASID 0x0000ULL -#define SATP64_PPN 0x0FFFULL +#define SATP64_MODE0xF000ULL +#define SATP64_MODE_SHIFT 60 +#define SATP64_ASID0x0000ULL +#define SATP64_PPN 0x0FFFULL #define SATP_MODE_OFF 0UL #define SATP_MODE_SV32 1UL -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105341): https://edk2.groups.io/g/devel/message/105341 Mute This Topic: https://groups.io/mt/99159995/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v3 3/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf| 2 +
UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 39 ++
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++
.../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 26 +
.../Library/BaseRiscVMmuLib/RiscVMmuCore.S| 31 +
7 files changed, 676 insertions(+), 2 deletions(-)
create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
index 25fe3f54c325..2af3b6223450 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
@@ -296,8 +296,7 @@ CpuSetMemoryAttributes (
IN UINT64 Attributes
)
{
- DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n",
__func__));
- return EFI_SUCCESS;
+ return RiscVSetMemoryAttributes (BaseAddress, Length, Attributes);
}
/**
@@ -340,6 +339,12 @@ InitializeCpu (
//
DisableInterrupts ();
+ //
+ // Enable MMU
+ //
+ Status = RiscVConfigureMmu ();
+ ASSERT_EFI_ERROR (Status);
+
//
// Install Boot protocol
//
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
index 49f4e119665a..68e6d038b66e 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
@@ -15,11 +15,13 @@
#include
#include
#include
+#include
#include
#include
#include
#include
#include
+#include
/**
Flush CPU data cache. If the instruction cache is fully coherent
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
index e8fa25446aef..9d9a5ef8f247 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
@@ -37,6 +37,8 @@
TimerLib
PeCoffGetEntryPointLib
RiscVSbiLib
+ RiscVMmuLib
+ CacheMaintenanceLib
[Sources]
CpuDxe.c
diff --git a/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
b/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
new file mode 100644
index ..f71d6a4a1e7b
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
@@ -0,0 +1,39 @@
+/** @file
+
+ Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.
+ Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef BASE_RISCV_MMU_LIB_H_
+#define BASE_RISCV_MMU_LIB_H_
+
+VOID
+EFIAPI
+RiscVLocalTlbFlushAll (
+ VOID
+ );
+
+VOID
+EFIAPI
+RiscVLocalTlbFlush (
+ UINTN VirtAddr
+ );
+
+EFI_STATUS
+EFIAPI
+RiscVSetMemoryAttributes (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64Length,
+ IN UINT64Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+RiscVConfigureMmu (
+ VOID
+ );
+
+#endif /* BASE_RISCV_MMU_LIB_H_ */
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
new file mode 100644
index ..230f34261d8b
--- /dev/null
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
@@ -0,0 +1,569 @@
+/** @file
+* MMU implementation for RISC-V
+*
+* Copyright (c) 2011-2020, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+* Copyright (c) 2017, Intel Corporation. All rights reserved.
+* Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define RISCV_PG_V BIT0
+#define RISCV_PG_R BIT1
+#define RISCV_PG_W BIT2
+#define RISCV_PG_X BIT3
+#define RISCV_PG_G BIT5
+#define RISCV_PG_A BIT6
+#define RISCV_PG_D BIT7
+#define PTE_ATTRIBUTES_MASK 0xE
+
+#define PTE_PPN_MASK 0x3FFC00ULL
+#define PTE_PPN_SHIFT 10
+#define RISCV_MMU_PAGE_SHIFT 12
+
+STATIC UINTN mMaxRootTableLevel;
+STATIC UINTN mBitPerLevel;
+STATIC UINTN mTableEntryCount;
+
+STATIC
+BOOLEAN
+RiscVMmuEnabled (
+ VOID
+ )
+{
+ return ((RiscVGetSupervisorAddressTranslationRegister () &
+ SATP64_MODE) != (SATP_MODE_OFF << SATP64_MODE_SHIFT));
+}
+
+STATIC
+UINTN
+RiscVGetRootTranslateTable (
+ VOID
+ )
+{
+ return (RiscVGetSupervisorAddressTranslationRegister () & SATP64_PPN) <<
+ RISCV_MMU_PAGE_SHIFT;
+}
+
+STATIC
+BOOLEAN
+IsValidPte (
+ IN UINTN Entry
+ )
+{
+ if (!(Entry & RISCV_PG_V) ||
+ (((Entry &
[edk2-devel] [PATCH v3 4/7] OvmfPkg/RiscVVirt: Remove satp bare mode setting
MMU now is initialized in CpuDxe. There is no point to set satp to bare
mode as that should be the default mode when booting edk2.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
OvmfPkg/RiscVVirt/Sec/Memory.c | 18 ++
2 files changed, 3 insertions(+), 16 deletions(-)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index 731f54f73f81..bc204ba5fe52 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -83,6 +83,7 @@
# RISC-V Architectural Libraries
CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
+ RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
PlatformBootManagerLib|OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
ResetSystemLib|OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf
diff --git a/OvmfPkg/RiscVVirt/Sec/Memory.c b/OvmfPkg/RiscVVirt/Sec/Memory.c
index 0e2690c73687..aad71ee5dcbb 100644
--- a/OvmfPkg/RiscVVirt/Sec/Memory.c
+++ b/OvmfPkg/RiscVVirt/Sec/Memory.c
@@ -85,21 +85,6 @@ AddMemoryRangeHob (
AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
}
-/**
- Configure MMU
-**/
-STATIC
-VOID
-InitMmu (
- )
-{
- //
- // Set supervisor translation mode to Bare mode
- //
- RiscVSetSupervisorAddressTranslationRegister ((UINT64)SATP_MODE_OFF << 60);
- DEBUG ((DEBUG_INFO, "%a: Set Supervisor address mode to bare-metal mode.\n",
__func__));
-}
-
/**
Publish system RAM and reserve memory regions.
@@ -327,7 +312,8 @@ MemoryPeimInitialization (
AddReservedMemoryMap (FdtPointer);
- InitMmu ();
+ /* Make sure SEC is booting with bare mode */
+ ASSERT ((RiscVGetSupervisorAddressTranslationRegister () & SATP64_MODE) ==
(SATP_MODE_OFF << SATP64_MODE_SHIFT));
BuildMemoryTypeInformationHob ();
--
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[edk2-devel] [PATCH v3 5/7] OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
The size should be for single region, not the whole firmware FD.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
.../Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c| 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
index fdc2ccb6294e..33f3a01b06f4 100644
--- a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
+++ b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
@@ -24,7 +24,8 @@ VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevice =
{
FixedPcdGet32 (PcdOvmfFdBaseAddress),
FixedPcdGet64 (PcdFlashNvStorageVariableBase),
- FixedPcdGet32 (PcdOvmfFirmwareFdSize),
+ FixedPcdGet32 (PcdOvmfFirmwareFdSize) -
+ (FixedPcdGet64 (PcdFlashNvStorageVariableBase) - FixedPcdGet32
(PcdOvmfFdBaseAddress)),
QEMU_NOR_BLOCK_SIZE
};
--
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[edk2-devel] [PATCH v3 6/7] OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists
The flash base address can be added to GCD before this driver run.
So only add it if it has not been done.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +++
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
b/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
index 6b9ef261335e..bbd1697a51dd 100644
--- a/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
+++ b/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
@@ -372,10 +372,11 @@ NorFlashFvbInitialize (
IN NOR_FLASH_INSTANCE *Instance
)
{
- EFI_STATUS Status;
- UINT32 FvbNumLba;
- EFI_BOOT_MODE BootMode;
- UINTN RuntimeMmioRegionSize;
+ EFI_STATUS Status;
+ UINT32 FvbNumLba;
+ EFI_BOOT_MODE BootMode;
+ UINTN RuntimeMmioRegionSize;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR Desc;
DEBUG ((DEBUG_BLKIO, "NorFlashFvbInitialize\n"));
ASSERT ((Instance != NULL));
@@ -390,13 +391,19 @@ NorFlashFvbInitialize (
// is written as the base of the flash region (ie:
Instance->DeviceBaseAddress)
RuntimeMmioRegionSize = (Instance->RegionBaseAddress -
Instance->DeviceBaseAddress) + Instance->Size;
- Status = gDS->AddMemorySpace (
- EfiGcdMemoryTypeMemoryMappedIo,
+ Status = gDS->GetMemorySpaceDescriptor (
Instance->DeviceBaseAddress,
- RuntimeMmioRegionSize,
- EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+ &Desc
);
- ASSERT_EFI_ERROR (Status);
+ if (Status == EFI_NOT_FOUND) {
+Status = gDS->AddMemorySpace (
+EfiGcdMemoryTypeMemoryMappedIo,
+Instance->DeviceBaseAddress,
+RuntimeMmioRegionSize,
+EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+);
+ASSERT_EFI_ERROR (Status);
+ }
Status = gDS->SetMemorySpaceAttributes (
Instance->DeviceBaseAddress,
--
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[edk2-devel] [Patch 1/1] OvmfPkg/VirtIoSerialDxe: Update for VS2015x86 compatibility
Move initialization of local variable structure from declaration
to statements to fix VS2015x86 build break.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Signed-off-by: Michael D Kinney
---
OvmfPkg/VirtioSerialDxe/VirtioSerial.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/OvmfPkg/VirtioSerialDxe/VirtioSerial.c
b/OvmfPkg/VirtioSerialDxe/VirtioSerial.c
index bfb2b324eadf..df545c080e9d 100644
--- a/OvmfPkg/VirtioSerialDxe/VirtioSerial.c
+++ b/OvmfPkg/VirtioSerialDxe/VirtioSerial.c
@@ -66,11 +66,11 @@ VirtioSerialTxControl (
IN UINT16 Value
)
{
- VIRTIO_SERIAL_CONTROL Control = {
-.Id= Id,
-.Event = Event,
-.Value = Value,
- };
+ VIRTIO_SERIAL_CONTROL Control;
+
+ Control.Id= Id;
+ Control.Event = Event;
+ Control.Value = Value;
DEBUG ((
DEBUG_INFO,
--
2.40.1.windows.1
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[edk2-devel] [PATCH v3 7/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices
Normally, DXE driver would add device resource to GCD before start using.
But some key resources such as uart, flash base address are being accessing
directly in some core modules.
Those resources should be populated to HOB in SEC phase so they are
added to GCD before anyone can access them.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++
OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 +
2 files changed, 63 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/Sec/Platform.c b/OvmfPkg/RiscVVirt/Sec/Platform.c
index 3645c27b0b12..944b82c84a6e 100644
--- a/OvmfPkg/RiscVVirt/Sec/Platform.c
+++ b/OvmfPkg/RiscVVirt/Sec/Platform.c
@@ -21,6 +21,63 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include
#include
+/**
+ Build memory map I/O range resource HOB using the
+ base address and size.
+
+ @param MemoryBase Memory map I/O base.
+ @param MemorySize Memory map I/O size.
+
+**/
+STATIC
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64MemorySize
+ )
+{
+ /* Align to EFI_PAGE_SIZE */
+ MemorySize = ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE);
+ BuildResourceDescriptorHob (
+EFI_RESOURCE_MEMORY_MAPPED_IO,
+EFI_RESOURCE_ATTRIBUTE_PRESENT |
+EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+EFI_RESOURCE_ATTRIBUTE_TESTED,
+MemoryBase,
+MemorySize
+);
+}
+
+/**
+ Populate IO resources from FDT that not added to GCD by its
+ driver in the DXE phase.
+
+ @param FdtBase Fdt base address
+ @param CompatibleCompatible string
+
+**/
+STATIC
+VOID
+PopulateIoResources (
+ VOID *FdtBase,
+ CONST CHAR8* Compatible
+ )
+{
+ UINT64 *Reg;
+ INT32 Node, LenP;
+
+ Node = fdt_node_offset_by_compatible (FdtBase, -1, Compatible);
+ while (Node != -FDT_ERR_NOTFOUND) {
+Reg = (UINT64 *)fdt_getprop (FdtBase, Node, "reg", &LenP);
+if (Reg) {
+ ASSERT (LenP == (2 * sizeof (UINT64)));
+ AddIoMemoryBaseSizeHob (SwapBytes64 (Reg[0]), SwapBytes64 (Reg[1]));
+}
+Node = fdt_node_offset_by_compatible (FdtBase, Node, Compatible);
+ }
+}
+
/**
@retval EFI_SUCCESSThe address of FDT is passed in HOB.
EFI_UNSUPPORTEDCan't locate FDT.
@@ -80,5 +137,10 @@ PlatformPeimInitialization (
BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSize));
+ PopulateIoResources (Base, "ns16550a");
+ PopulateIoResources (Base, "qemu,fw-cfg-mmio");
+ PopulateIoResources (Base, "virtio,mmio");
+ AddIoMemoryBaseSizeHob (PcdGet32 (PcdOvmfFdBaseAddress), PcdGet32
(PcdOvmfFirmwareFdSize));
+
return EFI_SUCCESS;
}
diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf
b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
index 0e2a5785e8a4..75d5b74b3d3f 100644
--- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf
+++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
@@ -62,6 +62,7 @@
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize
[Guids]
gFdtHobGuid
--
2.25.1
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[edk2-devel] [PATCH 1/2] UefiCpuPkg: CpuTimerDxeRiscV64: Fix incorrect value sent to SbiSetTimer
SbiSetTimer expects core tick value.
Signed-off-by: Tuan Phan
---
.../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 3 +++
UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 26 ---
UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 2 +-
3 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
index c76bd9648373..cd58d3a2f86b 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
@@ -40,6 +40,9 @@
Timer.h
Timer.c
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUMES
+
[Protocols]
gEfiCpuArchProtocolGuid ## CONSUMES
gEfiTimerArchProtocolGuid ## PRODUCES
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
index fa957ba5e3e9..a8afb649149f 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
@@ -80,8 +80,15 @@ TimerInterruptHandler (
return;
}
- mLastPeriodStart = PeriodStart;
- SbiSetTimer (PeriodStart += mTimerPeriod);
+ mLastPeriodStart = PeriodStart;
+ PeriodStart += DivU64x32 (
+MultU64x32 (
+ mTimerPeriod,
+ PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+),
+100u
+ ); // convert to tick
+ SbiSetTimer (PeriodStart);
RiscVEnableTimerInterrupt (); // enable SMode timer int
gBS->RestoreTPL (OriginalTPL);
}
@@ -163,6 +170,8 @@ TimerDriverSetTimerPeriod (
IN UINT64 TimerPeriod
)
{
+ UINT64 PeriodStart;
+
DEBUG ((DEBUG_INFO, "TimerDriverSetTimerPeriod(0x%lx)\n", TimerPeriod));
if (TimerPeriod == 0) {
@@ -171,9 +180,18 @@ TimerDriverSetTimerPeriod (
return EFI_SUCCESS;
}
- mTimerPeriod = TimerPeriod / 10; // convert unit from 100ns to 1us
+ mTimerPeriod = TimerPeriod / 10; // convert unit from 100ns to 1us
+
mLastPeriodStart = RiscVReadTimer ();
- SbiSetTimer (mLastPeriodStart + mTimerPeriod);
+ PeriodStart = mLastPeriodStart;
+ PeriodStart += DivU64x32 (
+MultU64x32 (
+ mTimerPeriod,
+ PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+),
+100u
+ ); // convert to tick
+ SbiSetTimer (PeriodStart);
mCpu->EnableInterrupt (mCpu);
RiscVEnableTimerInterrupt (); // enable SMode timer int
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
index 586eb0cfadb4..9b3542230cb5 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
@@ -21,7 +21,7 @@
#include
//
-// RISC-V use 100us timer.
+// RISC-V use 100ns timer.
// The default timer tick duration is set to 10 ms = 10 * 1000 * 10 100 ns
units
//
#define DEFAULT_TIMER_TICK_DURATION 10
--
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[edk2-devel] [PATCH 2/2] UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bit
The timer compare register is 64-bit so simplifying the delay
function.
Signed-off-by: Tuan Phan
---
MdePkg/Include/Register/RiscV64/RiscVImpl.h | 1 -
.../BaseRiscV64CpuTimerLib/CpuTimerLib.c | 62 +--
2 files changed, 28 insertions(+), 35 deletions(-)
diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h
b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
index ee5c2ba60377..6997de6cc001 100644
--- a/MdePkg/Include/Register/RiscV64/RiscVImpl.h
+++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
@@ -20,6 +20,5 @@
Name:
#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
-#define RISCV_TIMER_COMPARE_BITS 32
#endif
diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
index 9c8efc0f3530..57800177023c 100644
--- a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
+++ b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
@@ -22,26 +22,19 @@
@param Delay A period of time to delay in ticks.
**/
+STATIC
VOID
InternalRiscVTimerDelay (
- IN UINT32 Delay
+ IN UINT64 Delay
)
{
- UINT32 Ticks;
- UINT32 Times;
-
- Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
- Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
- do {
-//
-// The target timer count is calculated here
-//
-Ticks = RiscVReadTimer () + Delay;
-Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
-while (((Ticks - RiscVReadTimer ()) & (1 << (RISCV_TIMER_COMPARE_BITS -
1))) == 0) {
- CpuPause ();
-}
- } while (Times-- > 0);
+ UINT64 Ticks;
+
+ Ticks = RiscVReadTimer () + Delay;
+
+ while (RiscVReadTimer () <= Ticks) {
+CpuPause ();
+ }
}
/**
@@ -61,14 +54,14 @@ MicroSecondDelay (
)
{
InternalRiscVTimerDelay (
-(UINT32)DivU64x32 (
- MultU64x32 (
-MicroSeconds,
-PcdGet64 (PcdCpuCoreCrystalClockFrequency)
-),
- 100u
- )
-);
+DivU64x32 (
+ MultU64x32 (
+MicroSeconds,
+PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+ ),
+ 100u
+)
+ );
return MicroSeconds;
}
@@ -89,14 +82,14 @@ NanoSecondDelay (
)
{
InternalRiscVTimerDelay (
-(UINT32)DivU64x32 (
- MultU64x32 (
-NanoSeconds,
-PcdGet64 (PcdCpuCoreCrystalClockFrequency)
-),
- 10u
- )
-);
+DivU64x32 (
+ MultU64x32 (
+NanoSeconds,
+PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+ ),
+ 10u
+)
+ );
return NanoSeconds;
}
@@ -147,8 +140,9 @@ GetPerformanceCounter (
UINT64
EFIAPI
GetPerformanceCounterProperties (
- OUT UINT64 *StartValue, OPTIONAL
- OUT UINT64*EndValue OPTIONAL
+ OUT UINT64 *StartValue,
+ OPTIONAL
+ OUT UINT64 *EndValue OPTIONAL
)
{
if (StartValue != NULL) {
--
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[edk2-devel] [PATCH] MdePkg/BaseLib: Add SpeculationBarrier implementation for RiscV64
From: Yong Li Impelement the SpeculationBarrier with implementations consisting of fence instruction which provides finer-grain memory orderings. Data Barrier: fence rw,rw Instruction Barrier: fence.i; fence r,r More detail is in Chapter 17, RVWMO Memory Consistency Model https://github.com/riscv/riscv-isa-manual Cc: Warkentin, Andrei Cc: Evan, Chai Cc: Sunil V L Cc: Tuan Phan Signed-off-by: Yong Li --- MdePkg/Library/BaseLib/BaseLib.inf| 1 + .../BaseLib/RiscV64/SpeculationBarrier.S | 34 +++ 2 files changed, 35 insertions(+) create mode 100755 MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 3a48492b1a..03c7b02e82 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -404,6 +404,7 @@ RiscV64/CpuScratch.S | GCC RiscV64/ReadTimer.S | GCC RiscV64/RiscVMmu.S| GCC + RiscV64/SpeculationBarrier.S | GCC [Sources.LOONGARCH64] Math64.c diff --git a/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S b/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S new file mode 100755 index 00..581a765399 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S @@ -0,0 +1,34 @@ +##-- +# +# SpeculationBarrier() for RISCV64 +# +# Copyright (c) 2023, Intel Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +##-- + +.text +.p2align 2 + +ASM_GLOBAL ASM_PFX(SpeculationBarrier) + + +#/** +# Uses as a barrier to stop speculative execution. +# +# Ensures that no later instruction will execute speculatively, until all prior +# instructions have completed. +# +#**/ +#VOID +#EFIAPI +#SpeculationBarrier ( +# VOID +# ); +# +ASM_PFX(SpeculationBarrier): +fence rw,rw +fence.i +fence r,r +ret -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105350): https://edk2.groups.io/g/devel/message/105350 Mute This Topic: https://groups.io/mt/99163570/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
