MMU now is initialized in CpuDxe. There is no point to set satp to bare
mode as that should be the default mode when booting edk2.
Signed-off-by: Tuan Phan <tp...@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com>
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
OvmfPkg/RiscVVirt/Sec/Memory.c | 18 ++----------------
2 files changed, 3 insertions(+), 16 deletions(-)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index 731f54f73f81..bc204ba5fe52 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -83,6 +83,7 @@
# RISC-V Architectural Libraries
CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
+ RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
PlatformBootManagerLib|OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
ResetSystemLib|OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf
diff --git a/OvmfPkg/RiscVVirt/Sec/Memory.c b/OvmfPkg/RiscVVirt/Sec/Memory.c
index 0e2690c73687..aad71ee5dcbb 100644
--- a/OvmfPkg/RiscVVirt/Sec/Memory.c
+++ b/OvmfPkg/RiscVVirt/Sec/Memory.c
@@ -85,21 +85,6 @@ AddMemoryRangeHob (
AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
}
-/**
- Configure MMU
-**/
-STATIC
-VOID
-InitMmu (
- )
-{
- //
- // Set supervisor translation mode to Bare mode
- //
- RiscVSetSupervisorAddressTranslationRegister ((UINT64)SATP_MODE_OFF << 60);
- DEBUG ((DEBUG_INFO, "%a: Set Supervisor address mode to bare-metal mode.\n",
__func__));
-}
-
/**
Publish system RAM and reserve memory regions.
@@ -327,7 +312,8 @@ MemoryPeimInitialization (
AddReservedMemoryMap (FdtPointer);
- InitMmu ();
+ /* Make sure SEC is booting with bare mode */
+ ASSERT ((RiscVGetSupervisorAddressTranslationRegister () & SATP64_MODE) ==
(SATP_MODE_OFF << SATP64_MODE_SHIFT));
BuildMemoryTypeInformationHob ();
--
2.25.1
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