date:20220615

[PATCH] crypto/qat: fix cleanup function default behaviour

2022-06-15 Thread Arek Kusztal

Full cookie data should be cleared by default if not algorithm
specified. This is protection in case algorithm specific cleanup
is not implemented.

Fixes: 3b78aa7b2317 ("crypto/qat: refactor asymmetric crypto functions")

Signed-off-by: Arek Kusztal 
---
 drivers/crypto/qat/qat_asym.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c
index e4ab4bf33d..6e43a6cac8 100644
--- a/drivers/crypto/qat/qat_asym.c
+++ b/drivers/crypto/qat/qat_asym.c
@@ -144,6 +144,10 @@ cleanup(struct qat_asym_op_cookie *cookie,
cleanup_arrays(cookie, QAT_ASYM_RSA_NUM_IN_PARAMS,
QAT_ASYM_RSA_NUM_OUT_PARAMS, alg_size);
}
+   } else {
+   cleanup_arrays(cookie, QAT_ASYM_MAX_PARAMS,
+   QAT_ASYM_MAX_PARAMS,
+   QAT_PKE_MAX_LN_SIZE);
}
 }
 
-- 
2.13.6

Re: [PATCH 2/2] common/cnxk: add include for macro definition

2022-06-15 Thread Thomas Monjalon

14/06/2022 14:29, Bruce Richardson:
> The header file "roc_io.h" uses the "__plt_always_inline" macro but
> don't include "roc_platform.h" to get the definition of it. This
> inclusion is not necessary for compilation, but the lack of it can
> confuse some indexers - such as those in eclipse, which reports the
> lines:
> 
> "static __plt_always_inline uint64_t"
> 
> as possible definitions of a variable called "uint64_t". This confusion
> leads to uint64_t being flagged as an unknown type in all other parts of
> the project being indexed, e.g. across all of DPDK code.
> 
> Adding in the include of rte_common.h makes it clear to the indexer that
> those lines are  part of a function definition, and that allows eclipse
> to correctly recognise uint64_t as a type from stdint.h

It is not rte_common.h
Looks like a copy past of the first patch.

[PATCH v2] vdpa/ifc: fix null pointer dereference

2022-06-15 Thread Andy Pei

Fix null pointer dereference reported in coverity scan.

Coverity issue: 378882
Fixes: 5d75517beffe ("vdpa/ifc/base: access correct register for blk device")

Signed-off-by: Andy Pei 
---
 drivers/vdpa/ifc/base/ifcvf.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/vdpa/ifc/base/ifcvf.c b/drivers/vdpa/ifc/base/ifcvf.c
index dd475a7..0a9f71a 100644
--- a/drivers/vdpa/ifc/base/ifcvf.c
+++ b/drivers/vdpa/ifc/base/ifcvf.c
@@ -255,6 +255,10 @@
u32 ring_state;
 
cfg = hw->common_cfg;
+   if (!cfg) {
+   DEBUGOUT("common_cfg in HW is NULL.\n");
+   return;
+   }
 
IFCVF_WRITE_REG16(IFCVF_MSI_NO_VECTOR, &cfg->msix_config);
for (i = 0; i < hw->nr_vring; i++) {
@@ -262,6 +266,11 @@
IFCVF_WRITE_REG16(0, &cfg->queue_enable);
IFCVF_WRITE_REG16(IFCVF_MSI_NO_VECTOR, &cfg->queue_msix_vector);
 
+   if (!hw->lm_cfg) {
+   DEBUGOUT("live migration cfg in HW is NULL.\n");
+   continue;
+   }
+
if (hw->device_type == IFCVF_BLK)
ring_state = *(u32 *)(hw->lm_cfg +
IFCVF_LM_RING_STATE_OFFSET +
-- 
1.8.3.1

RE: [PATCH v7 2/5] raw/ifpga: add N3000 AFU driver

2022-06-15 Thread Xu, Rosen

Hi Wei,

Some comments.

Thanks,
Rosen

> -Original Message-
> From: Huang, Wei 
> Sent: Thursday, June 09, 2022 15:37
> To: dev@dpdk.org; tho...@monjalon.net; nipun.gu...@nxp.com;
> hemant.agra...@nxp.com
> Cc: sta...@dpdk.org; Xu, Rosen ; Zhang, Tianfei
> ; Zhang, Qi Z ; Huang, Wei
> 
> Subject: [PATCH v7 2/5] raw/ifpga: add N3000 AFU driver
> 
> N3000 AFU includes NLB0 and DMA modules, NLB0 is used to test PCI bus
> and DMA is used to test local memory.
> This driver initialize the modules and report test result.
> 
> Signed-off-by: Wei Huang 
> ---
> v2: move source files to ifpga and rename, refine code
> ---
> v3: fix Ubuntu 20.04 ARM build
> ---
>  drivers/raw/ifpga/afu_pmd_core.h  |   19 +
>  drivers/raw/ifpga/afu_pmd_n3000.c | 2019
> +
>  drivers/raw/ifpga/afu_pmd_n3000.h |  339 +++
>  drivers/raw/ifpga/meson.build |3 +-
>  drivers/raw/ifpga/rte_pmd_afu.h   |   97 ++
>  5 files changed, 2476 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/raw/ifpga/afu_pmd_n3000.c
>  create mode 100644 drivers/raw/ifpga/afu_pmd_n3000.h
>  create mode 100644 drivers/raw/ifpga/rte_pmd_afu.h
> 
> diff --git a/drivers/raw/ifpga/afu_pmd_core.h
> b/drivers/raw/ifpga/afu_pmd_core.h
> index 4fad2c7..a938172 100644
> --- a/drivers/raw/ifpga/afu_pmd_core.h
> +++ b/drivers/raw/ifpga/afu_pmd_core.h
> @@ -14,6 +14,7 @@
>  #include 
> 
>  #include 
> +#include 
>  #include 
>  #include 
> 
> @@ -60,6 +61,24 @@ struct afu_rawdev {
>   return rawdev ? (struct afu_rawdev *)rawdev->dev_private : NULL;
>  }
> 
> +#define CLS_TO_SIZE(n)  ((n) << 6)  /* get size of n cache lines */
> +#define SIZE_TO_CLS(s)  ((s) >> 6)  /* convert size to number of cache lines
> */
> +#define MHZ(f)  ((f) * 100)
> +
> +#define dsm_poll_timeout(addr, val, cond, invl, timeout) \
> +({   \
> + uint64_t __wait = 0; \
> + uint64_t __invl = (invl);\
> + uint64_t __timeout = (timeout);  \
> + for (; __wait <= __timeout; __wait += __invl) {  \
> + (val) = *(addr); \
> + if (cond)\
> + break;   \
> + rte_delay_ms(__invl);\
> + }\
> + (cond) ? 0 : 1;  \
> +})
> +
>  void afu_pmd_register(struct afu_rawdev_drv *driver);
>  void afu_pmd_unregister(struct afu_rawdev_drv *driver);
> 
> diff --git a/drivers/raw/ifpga/afu_pmd_n3000.c
> b/drivers/raw/ifpga/afu_pmd_n3000.c
> new file mode 100644
> index 000..14f7fe0
> --- /dev/null
> +++ b/drivers/raw/ifpga/afu_pmd_n3000.c
> @@ -0,0 +1,2019 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 Intel Corporation
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "afu_pmd_core.h"
> +#include "afu_pmd_n3000.h"
> +
> +static int nlb_afu_config(struct afu_rawdev *dev)
> +{
> + struct n3000_afu_priv *priv = NULL;
> + struct rte_pmd_afu_nlb_cfg *cfg = NULL;
> + struct nlb_csr_cfg v;
> +
> + if (!dev)
> + return -EINVAL;
> +
> + if (!dev->priv)
> + return -ENOENT;
> +
> + priv = (struct n3000_afu_priv *)dev->priv;
> + cfg = &priv->nlb_cfg;
> +
> + v.csr = 0;
> +
> + if (cfg->cont)
> + v.cont = 1;
> +
> + if (cfg->cache_policy == NLB_WRPUSH_I)
> + v.wrpush_i = 1;
> + else
> + v.wrthru_en = cfg->cache_policy;
> +
> + if (cfg->cache_hint == NLB_RDLINE_MIXED)
> + v.rdsel = 3;
> + else
> + v.rdsel = cfg->cache_hint;
> +
> + v.mode = cfg->mode;
> + v.chsel = cfg->read_vc;
> + v.wr_chsel = cfg->write_vc;
> + v.wrfence_chsel = cfg->wrfence_vc;
> + v.wrthru_en = cfg->cache_policy;
> + v.multicl_len = cfg->multi_cl - 1;
> +
> + IFPGA_RAWDEV_PMD_DEBUG("cfg: 0x%08x", v.csr);
> + rte_write32(v.csr, priv->nlb_ctx.addr + CSR_CFG);
> +
> + return 0;
> +}
> +
> +static void nlb_afu_report(struct afu_rawdev *dev, uint32_t cl)
> +{
> + struct n3000_afu_priv *priv = NULL;
> + struct rte_pmd_afu_nlb_cfg *cfg = NULL;
> + struct nlb_dsm_status *stat = NULL;
> + uint64_t ticks = 0;
> + double num, rd_bw, wr_bw;
> +
> + if (!dev || !dev->priv)
> + return;
> +
> + priv = (struct n3000_afu_priv *)dev->priv;
> +
> + cfg = &priv->nlb_cfg;
> + stat = priv->nlb_ctx.status_ptr;
> +
> + if (cfg->cont)
> + ticks = stat->num_clocks - stat->start_overhead;
> + else
> + ticks = st

RE: [PATCH] vdpa/ifc: fix null pointer dereference

2022-06-15 Thread Pei, Andy

Hi Chenbo,

Thanks for your reply.
I will fix this in next version.

> -Original Message-
> From: Xia, Chenbo 
> Sent: Wednesday, June 15, 2022 10:04 AM
> To: Pei, Andy ; dev@dpdk.org
> Cc: maxime.coque...@redhat.com; Wang, Xiao W ;
> Xu, Rosen ; Xiao, QimaiX 
> Subject: RE: [PATCH] vdpa/ifc: fix null pointer dereference
> 
> Hi Andy,
> 
> > -Original Message-
> > From: Pei, Andy 
> > Sent: Wednesday, June 8, 2022 3:34 PM
> > To: dev@dpdk.org
> > Cc: Xia, Chenbo ; maxime.coque...@redhat.com;
> > Wang, Xiao W ; Xu, Rosen ;
> > Xiao, QimaiX 
> > Subject: [PATCH] vdpa/ifc: fix null pointer dereference
> >
> > Fix null pointer dereference reported in coverity scan.
> >
> > Coverity issue: 378882
> > Fixes: 8162a4a9 ("vdpa/ifc/base: access correct register for blk
> > device")
> 
> Commit id need to be 12 digits. Also pls leave a blank line between Fixes tag
> and signed-off
> 
> Thanks,
> Chenbo
> 
> > Signed-off-by: Andy Pei 
> > ---
> >  drivers/vdpa/ifc/base/ifcvf.c | 9 +
> >  1 file changed, 9 insertions(+)
> >
> > diff --git a/drivers/vdpa/ifc/base/ifcvf.c
> > b/drivers/vdpa/ifc/base/ifcvf.c index dd475a7..0a9f71a 100644
> > --- a/drivers/vdpa/ifc/base/ifcvf.c
> > +++ b/drivers/vdpa/ifc/base/ifcvf.c
> > @@ -255,6 +255,10 @@
> > u32 ring_state;
> >
> > cfg = hw->common_cfg;
> > +   if (!cfg) {
> > +   DEBUGOUT("common_cfg in HW is NULL.\n");
> > +   return;
> > +   }
> >
> > IFCVF_WRITE_REG16(IFCVF_MSI_NO_VECTOR, &cfg->msix_config);
> > for (i = 0; i < hw->nr_vring; i++) { @@ -262,6 +266,11 @@
> > IFCVF_WRITE_REG16(0, &cfg->queue_enable);
> > IFCVF_WRITE_REG16(IFCVF_MSI_NO_VECTOR, &cfg-
> > >queue_msix_vector);
> >
> > +   if (!hw->lm_cfg) {
> > +   DEBUGOUT("live migration cfg in HW is NULL.\n");
> > +   continue;
> > +   }
> > +
> > if (hw->device_type == IFCVF_BLK)
> > ring_state = *(u32 *)(hw->lm_cfg +
> > IFCVF_LM_RING_STATE_OFFSET +
> > --
> > 1.8.3.1

RE: [PATCH v7 3/5] raw/ifpga: add HE-LPBK AFU driver

2022-06-15 Thread Xu, Rosen

Hi Wei,

> -Original Message-
> From: Huang, Wei 
> Sent: Thursday, June 09, 2022 15:37
> To: dev@dpdk.org; tho...@monjalon.net; nipun.gu...@nxp.com;
> hemant.agra...@nxp.com
> Cc: sta...@dpdk.org; Xu, Rosen ; Zhang, Tianfei
> ; Zhang, Qi Z ; Huang, Wei
> 
> Subject: [PATCH v7 3/5] raw/ifpga: add HE-LPBK AFU driver
> 
> HE-LPBK and HE-MEM-LPBK are host exerciser modules in OFS FPGA, HE-
> LPBK is used to test PCI bus and HE-MEM-LPBK is used to test local memory.
> This driver initialize the modules and report test result.
> 
> Signed-off-by: Wei Huang 
> ---
> v2: move source files to ifpga and rename, refine code
> ---
>  drivers/raw/ifpga/afu_pmd_he_lpbk.c | 436
> 
>  drivers/raw/ifpga/afu_pmd_he_lpbk.h | 126 +++
>  drivers/raw/ifpga/meson.build   |   2 +-
>  drivers/raw/ifpga/rte_pmd_afu.h |  14 ++
>  4 files changed, 577 insertions(+), 1 deletion(-)  create mode 100644
> drivers/raw/ifpga/afu_pmd_he_lpbk.c
>  create mode 100644 drivers/raw/ifpga/afu_pmd_he_lpbk.h
> 
> diff --git a/drivers/raw/ifpga/afu_pmd_he_lpbk.c
> b/drivers/raw/ifpga/afu_pmd_he_lpbk.c
> new file mode 100644
> index 000..8b2c85b
> --- /dev/null
> +++ b/drivers/raw/ifpga/afu_pmd_he_lpbk.c
> @@ -0,0 +1,436 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 Intel Corporation
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "afu_pmd_core.h"
> +#include "afu_pmd_he_lpbk.h"
> +
> +static int he_lpbk_afu_config(struct afu_rawdev *dev) {
> + struct he_lpbk_priv *priv = NULL;
> + struct rte_pmd_afu_he_lpbk_cfg *cfg = NULL;
> + struct he_lpbk_csr_cfg v;
> +
> + if (!dev)
> + return -EINVAL;
> +
> + priv = (struct he_lpbk_priv *)dev->priv;
> + if (!priv)
> + return -ENOENT;
> +
> + cfg = &priv->he_lpbk_cfg;
> +
> + v.csr = 0;
> +
> + if (cfg->cont)
> + v.cont = 1;
> +
> + v.mode = cfg->mode;
> + v.trput_interleave = cfg->trput_interleave;
> + if (cfg->multi_cl == 4)
> + v.multicl_len = 2;
> + else
> + v.multicl_len = cfg->multi_cl - 1;
> +
> + IFPGA_RAWDEV_PMD_DEBUG("cfg: 0x%08x", v.csr);
> + rte_write32(v.csr, priv->he_lpbk_ctx.addr + CSR_CFG);
> +
> + return 0;
> +}
> +
> +static void he_lpbk_report(struct afu_rawdev *dev, uint32_t cl) {
> + struct he_lpbk_priv *priv = NULL;
> + struct rte_pmd_afu_he_lpbk_cfg *cfg = NULL;
> + struct he_lpbk_ctx *ctx = NULL;
> + struct he_lpbk_dsm_status *stat = NULL;
> + struct he_lpbk_status0 stat0;
> + struct he_lpbk_status1 stat1;
> + uint64_t swtest_msg = 0;
> + uint64_t ticks = 0;
> + uint64_t info = 0;
> + double num, rd_bw, wr_bw;
> +
> + if (!dev || !dev->priv)
> + return;
> +
> + priv = (struct he_lpbk_priv *)dev->priv;
> + cfg = &priv->he_lpbk_cfg;
> + ctx = &priv->he_lpbk_ctx;
> +
> + stat = ctx->status_ptr;
> +
> + swtest_msg = rte_read64(ctx->addr + CSR_SWTEST_MSG);
> + stat0.csr = rte_read64(ctx->addr + CSR_STATUS0);
> + stat1.csr = rte_read64(ctx->addr + CSR_STATUS1);
> +
> + if (cfg->cont)
> + ticks = stat->num_clocks - stat->start_overhead;
> + else
> + ticks = stat->num_clocks -
> + (stat->start_overhead + stat->end_overhead);
> +
> + if (cfg->freq_mhz == 0) {
> + info = rte_read64(ctx->addr + CSR_HE_INFO0);
> + IFPGA_RAWDEV_PMD_INFO("API version: %"PRIx64, info >>
> 16);
> + cfg->freq_mhz = info & 0x;
> + if (cfg->freq_mhz == 0) {
> + IFPGA_RAWDEV_PMD_INFO("Frequency of AFU
> clock is unknown."
> + " Assuming 350 MHz.");
> + cfg->freq_mhz = 350;
> + }
> + }
> +
> + num = (double)stat0.num_reads;
> + rd_bw = (num * CLS_TO_SIZE(1) * MHZ(cfg->freq_mhz)) / ticks;
> + num = (double)stat0.num_writes;
> + wr_bw = (num * CLS_TO_SIZE(1) * MHZ(cfg->freq_mhz)) / ticks;
> +
> + printf("Cachelines  Read_Count Write_Count Pend_Read
> Pend_Write "
> + "Clocks@%uMHz   Rd_Bandwidth   Wr_Bandwidth\n",
> + cfg->freq_mhz);
> + printf("%10u  %10u %10u %10u %10u  %12"PRIu64
> + "   %7.3f GB/s   %7.3f GB/s\n",
> + cl, stat0.num_reads, stat0.num_writes,
> + stat1.num_pend_reads, stat1.num_pend_writes,
> + ticks, rd_bw / 1e9, wr_bw / 1e9);
> + printf("Test Message: 0x%"PRIx64"\n", swtest_msg); }
> +
> +static int he_lpbk_test(struct afu_rawdev *dev) {
> + struct he_lpbk_priv *priv = NULL;
> + struct rte_pmd_afu_he_lpbk_cfg *cfg = NULL;
> + struct he_lpbk_ctx *ctx = NULL;
> + struct he_lpbk_csr_ctl ctl;
> + uin

RE: [PATCH v7 4/5] raw/ifpga: add HE-MEM AFU driver

2022-06-15 Thread Xu, Rosen

Hi Wei,


> -Original Message-
> From: Huang, Wei 
> Sent: Thursday, June 09, 2022 15:37
> To: dev@dpdk.org; tho...@monjalon.net; nipun.gu...@nxp.com;
> hemant.agra...@nxp.com
> Cc: sta...@dpdk.org; Xu, Rosen ; Zhang, Tianfei
> ; Zhang, Qi Z ; Huang, Wei
> 
> Subject: [PATCH v7 4/5] raw/ifpga: add HE-MEM AFU driver
> 
> HE-MEM is one of the host exerciser modules in OFS FPGA, which is used to
> test local memory with built-in traffic generator.
> This driver initialize the module and report test result.
> 
> Signed-off-by: Wei Huang 
> Acked-by: Tianfei Zhang 
> ---
> v2: move source files to ifpga and rename
> ---
>  drivers/raw/ifpga/afu_pmd_he_mem.c | 183
> +
>  drivers/raw/ifpga/afu_pmd_he_mem.h |  46 ++
>  drivers/raw/ifpga/meson.build  |   2 +-
>  drivers/raw/ifpga/rte_pmd_afu.h|   7 ++
>  4 files changed, 237 insertions(+), 1 deletion(-)  create mode 100644
> drivers/raw/ifpga/afu_pmd_he_mem.c
>  create mode 100644 drivers/raw/ifpga/afu_pmd_he_mem.h
> 
> diff --git a/drivers/raw/ifpga/afu_pmd_he_mem.c
> b/drivers/raw/ifpga/afu_pmd_he_mem.c
> new file mode 100644
> index 000..0f57a03
> --- /dev/null
> +++ b/drivers/raw/ifpga/afu_pmd_he_mem.c
> @@ -0,0 +1,183 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 Intel Corporation
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "afu_pmd_core.h"
> +#include "afu_pmd_he_mem.h"
> +
> +static int he_mem_tg_test(struct afu_rawdev *dev) {
> + struct he_mem_tg_priv *priv = NULL;
> + struct rte_pmd_afu_he_mem_tg_cfg *cfg = NULL;
> + struct he_mem_tg_ctx *ctx = NULL;
> + uint64_t value = 0x12345678;
> + uint64_t cap = 0;
> + uint64_t channel_mask = 0;
> + int i, t = 0;
> +
> + if (!dev)
> + return -EINVAL;
> +
> + priv = (struct he_mem_tg_priv *)dev->priv;
> + if (!priv)
> + return -ENOENT;
> +
> + cfg = &priv->he_mem_tg_cfg;
> + ctx = &priv->he_mem_tg_ctx;
> +
> + IFPGA_RAWDEV_PMD_DEBUG("Channel mask: 0x%x", cfg-
> >channel_mask);
> +
> + rte_write64(value, ctx->addr + MEM_TG_SCRATCHPAD);
> + cap = rte_read64(ctx->addr + MEM_TG_SCRATCHPAD);
> + IFPGA_RAWDEV_PMD_DEBUG("Scratchpad value: 0x%"PRIx64, cap);
> + if (cap != value) {
> + IFPGA_RAWDEV_PMD_ERR("Test scratchpad register failed");
> + return -EIO;
> + }
> +
> + cap = rte_read64(ctx->addr + MEM_TG_CTRL);
> + IFPGA_RAWDEV_PMD_DEBUG("Capability: 0x%"PRIx64, cap);
> +
> + channel_mask = cfg->channel_mask & cap;
> + /* start traffic generators */
> + rte_write64(channel_mask, ctx->addr + MEM_TG_CTRL);
> +
> + /* check test status */
> + while (t < MEM_TG_TIMEOUT_MS) {
> + value = rte_read64(ctx->addr + MEM_TG_STAT);
> + for (i = 0; i < NUM_MEM_TG_CHANNELS; i++) {
> + if (channel_mask & (1 << i)) {
> + if (TGACTIVE(value, i))
> + continue;
> + printf("TG channel %d test %s\n", i,
> + TGPASS(value, i) ? "pass" :
> + TGTIMEOUT(value, i) ? "timeout" :
> + TGFAIL(value, i) ? "fail" : "error");
> + channel_mask &= ~(1 << i);
> + }
> + }
> + if (!channel_mask)
> + break;
> + rte_delay_ms(MEM_TG_POLL_INTERVAL_MS);
> + t += MEM_TG_POLL_INTERVAL_MS;
> + }
> +
> + if (channel_mask) {
> + IFPGA_RAWDEV_PMD_ERR("Timeout 0x%04lx", (unsigned
> long)value);
> + return channel_mask;
> + }
> +
> + return 0;
> +}
> +
> +static int he_mem_tg_init(struct afu_rawdev *dev) {
> + struct he_mem_tg_priv *priv = NULL;
> + struct he_mem_tg_ctx *ctx = NULL;
> +
> + if (!dev)
> + return -EINVAL;
> +
> + priv = (struct he_mem_tg_priv *)dev->priv;
> + if (!priv) {
> + priv = rte_zmalloc(NULL, sizeof(struct he_mem_tg_priv), 0);
> + if (!priv)
> + return -ENOMEM;
> + dev->priv = priv;
> + }
> +
> + ctx = &priv->he_mem_tg_ctx;
> + ctx->addr = (uint8_t *)dev->addr;
> +
> + return 0;
> +}
> +
> +static int he_mem_tg_config(struct afu_rawdev *dev, void *config,
> + size_t config_size)
> +{
> + struct he_mem_tg_priv *priv = NULL;
> +
> + if (!dev || !config || !config_size)
> + return -EINVAL;
> +
> + priv = (struct he_mem_tg_priv *)dev->priv;
> + if (!priv)
> + return -ENOENT;
> +
> + if (config_size != sizeof(struct rte_pmd_afu_he_mem_tg_cfg))
> + return -EINVAL;
> +
>

[PATCH v2] vdpa/ifc: fix null pointer dereference

2022-06-15 Thread Andy Pei

Fix null pointer dereference reported in coverity scan.

Coverity issue: 378882
Fixes: 5d75517beffe ("vdpa/ifc/base: access correct register for blk device")

Signed-off-by: Andy Pei 
Acked-by: Xiao Wang 
---
 drivers/vdpa/ifc/base/ifcvf.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/vdpa/ifc/base/ifcvf.c b/drivers/vdpa/ifc/base/ifcvf.c
index dd475a7..0a9f71a 100644
--- a/drivers/vdpa/ifc/base/ifcvf.c
+++ b/drivers/vdpa/ifc/base/ifcvf.c
@@ -255,6 +255,10 @@
u32 ring_state;
 
cfg = hw->common_cfg;
+   if (!cfg) {
+   DEBUGOUT("common_cfg in HW is NULL.\n");
+   return;
+   }
 
IFCVF_WRITE_REG16(IFCVF_MSI_NO_VECTOR, &cfg->msix_config);
for (i = 0; i < hw->nr_vring; i++) {
@@ -262,6 +266,11 @@
IFCVF_WRITE_REG16(0, &cfg->queue_enable);
IFCVF_WRITE_REG16(IFCVF_MSI_NO_VECTOR, &cfg->queue_msix_vector);
 
+   if (!hw->lm_cfg) {
+   DEBUGOUT("live migration cfg in HW is NULL.\n");
+   continue;
+   }
+
if (hw->device_type == IFCVF_BLK)
ring_state = *(u32 *)(hw->lm_cfg +
IFCVF_LM_RING_STATE_OFFSET +
-- 
1.8.3.1

Re: [PATCH] config: remove explicit undef of unset values

2022-06-15 Thread David Marchand

On Thu, Dec 16, 2021 at 12:15 PM Bruce Richardson
 wrote:
>
> Rather than explicitly clearing any setting of undefined values in our
> rte_config.h file, it's better to instead just add a comment that the
> value is not set. Using a comment allows the user to set the value using
> CFLAGS or similar mechanism without the config file clearing the value
> again.
>
> The text used " is not set" is modelled after the kernel approach
> of doing the same thing.
>
> Signed-off-by: Bruce Richardson 
Acked-by: Morten Brørup 
Acked-by: Tyler Retzlaff 

Rebased, added check as agreed, and applied.
Thanks Bruce.


-- 
David Marchand

RE: [PATCH v7 5/5] raw/ifpga: add HE-HSSI AFU driver

2022-06-15 Thread Xu, Rosen

Hi Wei,

> -Original Message-
> From: Huang, Wei 
> Sent: Thursday, June 09, 2022 15:37
> To: dev@dpdk.org; tho...@monjalon.net; nipun.gu...@nxp.com;
> hemant.agra...@nxp.com
> Cc: sta...@dpdk.org; Xu, Rosen ; Zhang, Tianfei
> ; Zhang, Qi Z ; Huang, Wei
> 
> Subject: [PATCH v7 5/5] raw/ifpga: add HE-HSSI AFU driver
> 
> HE-HSSI is one of the host exerciser modules in OFS FPGA, which is used to
> test HSSI (High Speed Serial Interface).
> This driver initialize the module and report test result.
> 
> Signed-off-by: Wei Huang 
> ---
> v2: move source files to ifpga and rename, refine code
> ---
>  drivers/raw/ifpga/afu_pmd_he_hssi.c | 371
> 
>  drivers/raw/ifpga/afu_pmd_he_hssi.h | 109 +++
>  drivers/raw/ifpga/meson.build   |   3 +-
>  drivers/raw/ifpga/rte_pmd_afu.h |  18 ++
>  4 files changed, 500 insertions(+), 1 deletion(-)  create mode 100644
> drivers/raw/ifpga/afu_pmd_he_hssi.c
>  create mode 100644 drivers/raw/ifpga/afu_pmd_he_hssi.h
> 
> diff --git a/drivers/raw/ifpga/afu_pmd_he_hssi.c
> b/drivers/raw/ifpga/afu_pmd_he_hssi.c
> new file mode 100644
> index 000..102de50
> --- /dev/null
> +++ b/drivers/raw/ifpga/afu_pmd_he_hssi.c
> @@ -0,0 +1,371 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 Intel Corporation
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "afu_pmd_core.h"
> +#include "afu_pmd_he_hssi.h"
> +
> +static int he_hssi_indirect_write(struct he_hssi_ctx *ctx, uint32_t addr,
> + uint32_t value)
> +{
> + struct traffic_ctrl_cmd cmd;
> + struct traffic_ctrl_data data;
> + uint32_t i = 0;
> +
> + IFPGA_RAWDEV_PMD_DEBUG("Indirect write 0x%x, value 0x%08x",
> addr,
> +value);
> +
> + if (!ctx)
> + return -EINVAL;
> +
> + data.write_data = value;
> + rte_write64(data.csr, ctx->addr + TRAFFIC_CTRL_DATA);
> +
> + cmd.csr = 0;
> + cmd.write_cmd = 1;
> + cmd.afu_cmd_addr = addr;
> + rte_write64(cmd.csr, ctx->addr + TRAFFIC_CTRL_CMD);
> +
> + while (i < MAILBOX_TIMEOUT_MS) {
> + rte_delay_ms(MAILBOX_POLL_INTERVAL_MS);
> + cmd.csr = rte_read64(ctx->addr + TRAFFIC_CTRL_CMD);
> + if (cmd.ack_trans)
> + break;
> + i += MAILBOX_POLL_INTERVAL_MS;
> + }
> + if (i >= MAILBOX_TIMEOUT_MS)
> + return -ETIMEDOUT;
> +
> + i = 0;
> + cmd.csr = 0;
> + while (i < MAILBOX_TIMEOUT_MS) {
> + cmd.ack_trans = 1;
> + rte_write64(cmd.csr, ctx->addr + TRAFFIC_CTRL_CMD);
> + rte_delay_ms(MAILBOX_POLL_INTERVAL_MS);
> + cmd.csr = rte_read64(ctx->addr + TRAFFIC_CTRL_CMD);
> + if (!cmd.ack_trans)
> + break;
> + i += MAILBOX_POLL_INTERVAL_MS;
> + }
> + if (i >= MAILBOX_TIMEOUT_MS)
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int he_hssi_indirect_read(struct he_hssi_ctx *ctx, uint32_t addr,
> + uint32_t *value)
> +{
> + struct traffic_ctrl_cmd cmd;
> + struct traffic_ctrl_data data;
> + uint32_t i = 0;
> +
> + if (!ctx)
> + return -EINVAL;
> +
> + cmd.csr = 0;
> + cmd.read_cmd = 1;
> + cmd.afu_cmd_addr = addr;
> + rte_write64(cmd.csr, ctx->addr + TRAFFIC_CTRL_CMD);
> +
> + while (i < MAILBOX_TIMEOUT_MS) {
> + rte_delay_ms(MAILBOX_POLL_INTERVAL_MS);
> + cmd.csr = rte_read64(ctx->addr + TRAFFIC_CTRL_CMD);
> + if (cmd.ack_trans) {
> + data.csr = rte_read64(ctx->addr +
> TRAFFIC_CTRL_DATA);
> + *value = data.read_data;
> + break;
> + }
> + i += MAILBOX_POLL_INTERVAL_MS;
> + }
> + if (i >= MAILBOX_TIMEOUT_MS)
> + return -ETIMEDOUT;
> +
> + i = 0;
> + cmd.csr = 0;
> + while (i < MAILBOX_TIMEOUT_MS) {
> + cmd.ack_trans = 1;
> + rte_write64(cmd.csr, ctx->addr + TRAFFIC_CTRL_CMD);
> + rte_delay_ms(MAILBOX_POLL_INTERVAL_MS);
> + cmd.csr = rte_read64(ctx->addr + TRAFFIC_CTRL_CMD);
> + if (!cmd.ack_trans)
> + break;
> + i += MAILBOX_POLL_INTERVAL_MS;
> + }
> + if (i >= MAILBOX_TIMEOUT_MS)
> + return -ETIMEDOUT;
> +
> + IFPGA_RAWDEV_PMD_DEBUG("Indirect read 0x%x, value 0x%08x",
> addr, *value);
> + return 0;
> +}
> +
> +static void he_hssi_report(struct he_hssi_ctx *ctx) {
> + uint32_t val = 0;
> + uint64_t v64 = 0;
> + int ret = 0;
> +
> + ret = he_hssi_indirect_read(ctx, TM_PKT_GOOD, &val);
> + if (ret)
> + return;
> + printf("Number of good packets received: %u\n", val);
> +
> + ret = he_hssi_indir

[Bug 1035] __rte_raw_cksum() crash with misaligned pointer

2022-06-15 Thread bugzilla

https://bugs.dpdk.org/show_bug.cgi?id=1035

Bug ID: 1035
Summary: __rte_raw_cksum() crash with misaligned pointer
Product: DPDK
Version: 21.11
Hardware: All
OS: All
Status: UNCONFIRMED
Severity: normal
Priority: Normal
Component: ethdev
Assignee: dev@dpdk.org
Reporter: emil.b...@ericsson.com
Target Milestone: ---

See rte_raw_cksum() in rte_ip.h, which is part of the public API. See also the
subfunction __rte_raw_cksum().

_rte_raw_cksum assumes that the buffer over which the checksum is calculated is
an even address (divisible by two). See for example this stack overflow post:
https://stackoverflow.com/questions/46790550/c-undefined-behavior-strict-aliasing-rule-or-incorrect-alignment

The post explains that there is undefined behavior in C11 when "conversion
between two pointer types produces a result that is incorrectly aligned". When
the buf argument starts on an odd address we thus have undefined behavior,
since a pointer is cast from void* to uint16_t*.

In most cases (at least on x86) that isn't a problem, but with higher
optimization levels it may break due to vector instructions. This new function
seems to be easier to optimize by the compiler, resulting in a crash when the
buf argument is odd. Please note that the undefined behavior is present in
earlier versions of dpdk as well.

Now you're probably thinking: "Just align your buffers". The problem is that we
have a packet buffer which is aligned. The checksum is calculated on a subset
of that aligned packet buffer, and that sometimes lies on odd addresses.

The question remains if this is an issue with dpdk or not. Maybe you do the
assumption that odd addresses are never passed in when calculating the
checksum, and that's all right. But perhaps a public API comment should be
added in that case. Or perhaps you use it incorrectly as well, and in that case
something should be done about it.

Triggering this bug seems to require high optimization levels as well as odd
values of buf.

Of interest may be that in older version of dpdk you added the a comment: /*
workaround gcc strict-aliasing warning */ showing that you willfully ignored
the warning.

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