date:20210531

From: Kalesh AP 

Kalesh AP (9):
  net/bnxt: fix error message when VNIC prepare fails
  net/bnxt: set flow error when free filter is not available
  net/bnxt: remove unnecessary code
  net/bnxt: fix error handling when VNIC prepare fails
  net/bnxt: set flow error when tunnel redirection free fails
  net/bnxt: use common function to destroy VNIC resource
  net/bnxt: fix check for PTP support in FW
  net/bnxt: improve log message
  net/bnxt: remove unnecessary comment

 drivers/net/bnxt/bnxt_ethdev.c |   6 +--
 drivers/net/bnxt/bnxt_flow.c   | 116 +
 drivers/net/bnxt/bnxt_hwrm.c   |  10 ++--
 3 files changed, 81 insertions(+), 51 deletions(-)

-- 
2.10.1

[dpdk-dev] [PATCH 1/9] net/bnxt: fix error message when VNIC prepare fails

From: Kalesh AP 

The bnxt_vnic_prep() can fail due to multiple reasons.
But when bnxt_vnic_prep() fails, PMD is not returning
the actual error/string to the application.

Fix it by moving the "rte_flow_error_set" to bnxt_vnic_prep()
to set the actual error code.

Fixes: d24610f7bfda ("net/bnxt: allow flow creation when RSS is enabled")
Cc: sta...@dpdk.org

Signed-off-by: Kalesh AP 
Reviewed-by: Somnath Kotur 
Reviewed-by: Ajit Khaparde 
Reviewed-by: Venkat Duvvuru 
---
 drivers/net/bnxt/bnxt_flow.c | 66 +++-
 1 file changed, 40 insertions(+), 26 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c
index 73fd24c..66012b8 100644
--- a/drivers/net/bnxt/bnxt_flow.c
+++ b/drivers/net/bnxt/bnxt_flow.c
@@ -919,32 +919,46 @@ bnxt_get_l2_filter(struct bnxt *bp, struct 
bnxt_filter_info *nf,
return l2_filter;
 }
 
-static int bnxt_vnic_prep(struct bnxt *bp, struct bnxt_vnic_info *vnic)
+static int bnxt_vnic_prep(struct bnxt *bp, struct bnxt_vnic_info *vnic,
+ const struct rte_flow_action *act,
+ struct rte_flow_error *error)
 {
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
uint64_t rx_offloads = dev_conf->rxmode.offloads;
int rc;
 
if (bp->nr_vnics > bp->max_vnics - 1)
-   return -ENOMEM;
+   return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
+ NULL,
+ "Group id is invalid");
 
rc = bnxt_vnic_grp_alloc(bp, vnic);
if (rc)
-   goto ret;
+   return rte_flow_error_set(error, -rc,
+ RTE_FLOW_ERROR_TYPE_ACTION,
+ act,
+ "Failed to alloc VNIC group");
 
rc = bnxt_hwrm_vnic_alloc(bp, vnic);
if (rc) {
-   PMD_DRV_LOG(ERR, "HWRM vnic alloc failure rc: %x\n", rc);
+   rte_flow_error_set(error, -rc,
+  RTE_FLOW_ERROR_TYPE_ACTION,
+  act,
+  "Failed to alloc VNIC");
goto ret;
}
+
bp->nr_vnics++;
 
/* RSS context is required only when there is more than one RSS ring */
if (vnic->rx_queue_cnt > 1) {
rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, 0 /* ctx_idx 0 */);
if (rc) {
-   PMD_DRV_LOG(ERR,
-   "HWRM vnic ctx alloc failure: %x\n", rc);
+   rte_flow_error_set(error, -rc,
+  RTE_FLOW_ERROR_TYPE_ACTION,
+  act,
+  "Failed to alloc VNIC context");
goto ret;
}
} else {
@@ -957,10 +971,24 @@ static int bnxt_vnic_prep(struct bnxt *bp, struct 
bnxt_vnic_info *vnic)
vnic->vlan_strip = false;
 
rc = bnxt_hwrm_vnic_cfg(bp, vnic);
-   if (rc)
+   if (rc) {
+   rte_flow_error_set(error, -rc,
+  RTE_FLOW_ERROR_TYPE_ACTION,
+  act,
+  "Failed to configure VNIC");
goto ret;
+   }
 
-   bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
+   rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
+   if (rc) {
+   rte_flow_error_set(error, -rc,
+  RTE_FLOW_ERROR_TYPE_ACTION,
+  act,
+  "Failed to configure VNIC plcmode");
+   goto ret;
+   }
+
+   return 0;
 
 ret:
return rc;
@@ -1142,16 +1170,9 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev,
 
PMD_DRV_LOG(DEBUG, "VNIC found\n");
 
-   rc = bnxt_vnic_prep(bp, vnic);
-   if (rc)  {
-   rte_flow_error_set(error,
-  EINVAL,
-  RTE_FLOW_ERROR_TYPE_ACTION,
-  act,
-  "VNIC prep fail");
-   rc = -rte_errno;
+   rc = bnxt_vnic_prep(bp, vnic, act, error);
+   if (rc)
goto ret;
-   }
 
PMD_DRV_LOG(DEBUG,
"vnic[%d] = %p vnic->fw_grp_ids = %p\n",
@@ -1362,16 +1383,9 @@ bnxt_validate_and_parse_flow(struct rte_eth_dev *dev,
vnic->end_grp_id = rss->queue[rss->queue_num - 1];
vnic->func_default = 0; //This is not a default VNIC.
 
-   rc = bnxt_vnic_prep(bp, vnic);
-   if (rc) {
-

[dpdk-dev] [PATCH 2/9] net/bnxt: set flow error when free filter is not available

From: Kalesh AP 

In bnxt_flow_validate(), when bnxt_get_unused_filter() fails due to
no filter resources available, driver is not setting flow error using
"rte_flow_error_set".

Also, fixed the error code.

Fixes: 5ef3b79fdfe6 ("net/bnxt: support flow filter ops")
Cc: sta...@dpdk.org

Signed-off-by: Kalesh AP 
Reviewed-by: Kalesh AP 
Reviewed-by: Ajit Khaparde 
---
 drivers/net/bnxt/bnxt_flow.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c
index 66012b8..9b47807 100644
--- a/drivers/net/bnxt/bnxt_flow.c
+++ b/drivers/net/bnxt/bnxt_flow.c
@@ -1550,9 +1550,11 @@ bnxt_flow_validate(struct rte_eth_dev *dev,
 
filter = bnxt_get_unused_filter(bp);
if (filter == NULL) {
-   PMD_DRV_LOG(ERR, "Not enough resources for a new flow.\n");
+   rte_flow_error_set(error, ENOSPC,
+  RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
+  "Not enough resources for a new flow");
bnxt_release_flow_lock(bp);
-   return -ENOMEM;
+   return -ENOSPC;
}
 
ret = bnxt_validate_and_parse_flow(dev, pattern, actions, attr,
-- 
2.10.1

[dpdk-dev] [PATCH 3/9] net/bnxt: remove unnecessary code

From: Kalesh AP 

Also removed a log message which does not convey any
useful information.

Fixes: d24610f7bfda ("net/bnxt: allow flow creation when RSS is enabled")
Cc: sta...@dpdk.org

Signed-off-by: Kalesh AP 
Reviewed-by: Venkat Duvvuru 
Reviewed-by: Ajit Khaparde 
---
 drivers/net/bnxt/bnxt_flow.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c
index 9b47807..d23f8cf 100644
--- a/drivers/net/bnxt/bnxt_flow.c
+++ b/drivers/net/bnxt/bnxt_flow.c
@@ -953,7 +953,7 @@ static int bnxt_vnic_prep(struct bnxt *bp, struct 
bnxt_vnic_info *vnic,
 
/* RSS context is required only when there is more than one RSS ring */
if (vnic->rx_queue_cnt > 1) {
-   rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, 0 /* ctx_idx 0 */);
+   rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, 0);
if (rc) {
rte_flow_error_set(error, -rc,
   RTE_FLOW_ERROR_TYPE_ACTION,
@@ -961,8 +961,6 @@ static int bnxt_vnic_prep(struct bnxt *bp, struct 
bnxt_vnic_info *vnic,
   "Failed to alloc VNIC context");
goto ret;
}
-   } else {
-   PMD_DRV_LOG(DEBUG, "No RSS context required\n");
}
 
if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
-- 
2.10.1

[dpdk-dev] [PATCH 4/9] net/bnxt: fix error handling when VNIC prepare fails

From: Kalesh AP 

Resources should be freed on error conditions. i.e, VNIC and
VNIC context created in HW and memory allocated in
bnxt_vnic_grp_alloc() should be freed.

Added a new function bnxt_vnic_destroy() to do the cleanup.
This lightweight function can be used in flow destroy/flush
path to avoid duplicate code as well.

Fixes: d24610f7bfda ("net/bnxt: allow flow creation when RSS is enabled")
Cc: sta...@dpdk.org

Signed-off-by: Kalesh AP 
Reviewed-by: Somnath Kotur 
Reviewed-by: Ajit Khaparde 
---
 drivers/net/bnxt/bnxt_flow.c | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c
index d23f8cf..03c7173 100644
--- a/drivers/net/bnxt/bnxt_flow.c
+++ b/drivers/net/bnxt/bnxt_flow.c
@@ -919,6 +919,19 @@ bnxt_get_l2_filter(struct bnxt *bp, struct 
bnxt_filter_info *nf,
return l2_filter;
 }
 
+static void bnxt_vnic_cleanup(struct bnxt *bp, struct bnxt_vnic_info *vnic)
+{
+   if (vnic->rx_queue_cnt > 1)
+   bnxt_hwrm_vnic_ctx_free(bp, vnic);
+
+   bnxt_hwrm_vnic_free(bp, vnic);
+
+   rte_free(vnic->fw_grp_ids);
+   vnic->fw_grp_ids = NULL;
+
+   vnic->rx_queue_cnt = 0;
+}
+
 static int bnxt_vnic_prep(struct bnxt *bp, struct bnxt_vnic_info *vnic,
  const struct rte_flow_action *act,
  struct rte_flow_error *error)
@@ -949,8 +962,6 @@ static int bnxt_vnic_prep(struct bnxt *bp, struct 
bnxt_vnic_info *vnic,
goto ret;
}
 
-   bp->nr_vnics++;
-
/* RSS context is required only when there is more than one RSS ring */
if (vnic->rx_queue_cnt > 1) {
rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, 0);
@@ -986,9 +997,12 @@ static int bnxt_vnic_prep(struct bnxt *bp, struct 
bnxt_vnic_info *vnic,
goto ret;
}
 
+   bp->nr_vnics++;
+
return 0;
 
 ret:
+   bnxt_vnic_cleanup(bp, vnic);
return rc;
 }
 
-- 
2.10.1

[dpdk-dev] [PATCH 5/9] net/bnxt: set flow error when tunnel redirection free fails

From: Kalesh AP 

During flow destroy, when bnxt_hwrm_tunnel_redirect_free() fails,
driver is not setting flow error using "rte_flow_error_set".

Fixes: 11e5e19695c7 ("net/bnxt: support redirecting tunnel packets to VF")
Cc: sta...@dpdk.org

Signed-off-by: Kalesh AP 
Reviewed-by: Somnath Kotur 
Reviewed-by: Ajit Khaparde 
---
 drivers/net/bnxt/bnxt_flow.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c
index 03c7173..ed201a3 100644
--- a/drivers/net/bnxt/bnxt_flow.c
+++ b/drivers/net/bnxt/bnxt_flow.c
@@ -1969,12 +1969,20 @@ static int bnxt_handle_tunnel_redirect_destroy(struct 
bnxt *bp,
/* Tunnel doesn't belong to this VF, so don't send HWRM
 * cmd, just delete the flow from driver
 */
-   if (bp->fw_fid != (tun_dst_fid + bp->first_vf_id))
+   if (bp->fw_fid != (tun_dst_fid + bp->first_vf_id)) {
PMD_DRV_LOG(ERR,
"Tunnel does not belong to this VF, skip 
hwrm_tunnel_redirect_free\n");
-   else
+   } else {
ret = bnxt_hwrm_tunnel_redirect_free(bp,
filter->tunnel_type);
+   if (ret) {
+   rte_flow_error_set(error, -ret,
+  RTE_FLOW_ERROR_TYPE_HANDLE,
+  NULL,
+  "Unable to free tunnel 
redirection");
+   return ret;
+   }
+   }
}
return ret;
 }
-- 
2.10.1

[dpdk-dev] [PATCH 6/9] net/bnxt: use common function to destroy VNIC resource

From: Kalesh AP 

Use the function bnxt_vnic_destroy() to destroy VNIC resources
and thereby eliminate few duplicate code.

Fixes: 8d0a244b40b2 ("net/bnxt: cleanup VNIC after flow validate")
Fixes: 49d0709b257f ("net/bnxt: delete and flush L2 filters cleanly")
Cc: sta...@dpdk.org

Signed-off-by: Kalesh AP 
Reviewed-by: Somnath Kotur 
Reviewed-by: Ajit Khaparde 
---
 drivers/net/bnxt/bnxt_flow.c | 12 ++--
 1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c
index ed201a3..59489b5 100644
--- a/drivers/net/bnxt/bnxt_flow.c
+++ b/drivers/net/bnxt/bnxt_flow.c
@@ -1577,10 +1577,7 @@ bnxt_flow_validate(struct rte_eth_dev *dev,
vnic = find_matching_vnic(bp, filter);
if (vnic) {
if (STAILQ_EMPTY(&vnic->filter)) {
-   rte_free(vnic->fw_grp_ids);
-   bnxt_hwrm_vnic_ctx_free(bp, vnic);
-   bnxt_hwrm_vnic_free(bp, vnic);
-   vnic->rx_queue_cnt = 0;
+   bnxt_vnic_cleanup(bp, vnic);
bp->nr_vnics--;
PMD_DRV_LOG(DEBUG, "Free VNIC\n");
}
@@ -2045,12 +2042,7 @@ _bnxt_flow_destroy(struct bnxt *bp,
 */
if (vnic && !vnic->func_default &&
STAILQ_EMPTY(&vnic->flow_list)) {
-   rte_free(vnic->fw_grp_ids);
-   if (vnic->rx_queue_cnt > 1)
-   bnxt_hwrm_vnic_ctx_free(bp, vnic);
-
-   bnxt_hwrm_vnic_free(bp, vnic);
-   vnic->rx_queue_cnt = 0;
+   bnxt_vnic_cleanup(bp, vnic);
bp->nr_vnics--;
}
} else {
-- 
2.10.1

[dpdk-dev] [PATCH 7/9] net/bnxt: fix check for PTP support in FW

From: Kalesh AP 

On Thor, driver must use HWRM to access the timestamp information.
Driver should not advertise PTP support to application
if PTP information is not accessible via HWRM commands.

Fixes: 6cbd89f9f3d8 ("net/bnxt: support PTP for Thor")
Cc: sta...@dpdk.org

Signed-off-by: Kalesh AP 
Reviewed-by: Somnath Kotur 
Reviewed-by: Ajit Khaparde 
---
 drivers/net/bnxt/bnxt_hwrm.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 931ecea..65ab8fc 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -750,9 +750,13 @@ static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 
HWRM_CHECK_RESULT();
 
-   if (!BNXT_CHIP_P5(bp) &&
-   !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
-   return 0;
+   if (BNXT_CHIP_P5(bp)) {
+   if (!(resp->flags & 
HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS))
+   return 0;
+   } else {
+   if (!(resp->flags & 
HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
+   return 0;
+   }
 
if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
-- 
2.10.1

[dpdk-dev] [PATCH 8/9] net/bnxt: improve log message

From: Kalesh AP 

The existing log messge is missing a space. Modified it to
a more meaningful log as part of this change.

Fixes: 1bf01f5135f8 ("net/bnxt: prevent device access when device is in reset")
Cc: sta...@dpdk.org

Before this patch:

bnxt_dev_init(): bnxtfound at mem D67E, node addr 0x2101112000M

With this patch:

bnxt_dev_init(): Found bnxt device at mem D67E, node addr 0x2101112000M

Signed-off-by: Kalesh AP 
Reviewed-by: Somnath Kotur 
Reviewed-by: Ajit Khaparde 
---
 drivers/net/bnxt/bnxt_ethdev.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 3778e28..50a49f9 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -5709,7 +5709,8 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params 
__rte_unused)
goto error_free;
 
PMD_DRV_LOG(INFO,
-   DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
+   "Found %s device at mem %" PRIX64 ", node addr %pM\n",
+   DRV_MODULE_NAME,
pci_dev->mem_resource[0].phys_addr,
pci_dev->mem_resource[0].addr);
 
-- 
2.10.1

[dpdk-dev] [PATCH 9/9] net/bnxt: remove unnecessary comment

From: Kalesh AP 

Fixes: 0a6d2a720078 ("net/bnxt: get device infos")
Cc: sta...@dpdk.org

Signed-off-by: Kalesh AP 
Reviewed-by: Somnath Kotur 
---
 drivers/net/bnxt/bnxt_ethdev.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 50a49f9..982f374 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -948,7 +948,6 @@ static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 
dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 
-   /* *INDENT-OFF* */
dev_info->default_rxconf = (struct rte_eth_rxconf) {
.rx_thresh = {
.pthresh = 8,
@@ -984,8 +983,6 @@ static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
BNXT_SWITCH_PORT_ID_TRUSTED_VF;
}
 
-   /* *INDENT-ON* */
-
/*
 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 *   need further investigation.
-- 
2.10.1

Re: [dpdk-dev] [RFC] lib/ethdev: add dev configured flag

2021-05-31 Thread Huisong Li


Hi, All & Ferruh

What do you think about this patch?


在 2021/5/8 16:00, Huisong Li 写道:

Currently, if dev_configure is not invoked or fails to be invoked, users
can still invoke dev_start successfully. This patch adds a "dev_configured"
flag in "rte_eth_dev_data" to control whether dev_start can be invoked.

Signed-off-by: Huisong Li 
---
  lib/ethdev/rte_ethdev.c  | 11 +++
  lib/ethdev/rte_ethdev_core.h |  6 +-
  2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c
index a187976..7d74b17 100644
--- a/lib/ethdev/rte_ethdev.c
+++ b/lib/ethdev/rte_ethdev.c
@@ -1604,6 +1604,8 @@ rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, 
uint16_t nb_tx_q,
}
  
  	rte_ethdev_trace_configure(port_id, nb_rx_q, nb_tx_q, dev_conf, 0);

+   dev->data->dev_configured = 1;
+
return 0;
  reset_queues:
eth_dev_rx_queue_config(dev, 0);
@@ -1614,6 +1616,8 @@ rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, 
uint16_t nb_tx_q,
dev->data->mtu = old_mtu;
  
  	rte_ethdev_trace_configure(port_id, nb_rx_q, nb_tx_q, dev_conf, ret);

+   dev->data->dev_configured = 0;
+
return ret;
  }
  
@@ -1749,6 +1753,13 @@ rte_eth_dev_start(uint16_t port_id)
  
  	RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_start, -ENOTSUP);
  
+	if (dev->data->dev_configured == 0) {

+   RTE_ETHDEV_LOG(INFO,
+   "Device with port_id=%"PRIu16" is not configured.\n",
+   port_id);
+   return -EINVAL;
+   }
+
if (dev->data->dev_started != 0) {
RTE_ETHDEV_LOG(INFO,
"Device with port_id=%"PRIu16" already started\n",
diff --git a/lib/ethdev/rte_ethdev_core.h b/lib/ethdev/rte_ethdev_core.h
index 4679d94..b508769 100644
--- a/lib/ethdev/rte_ethdev_core.h
+++ b/lib/ethdev/rte_ethdev_core.h
@@ -167,7 +167,11 @@ struct rte_eth_dev_data {
scattered_rx : 1,  /**< RX of scattered packets is ON(1) / 
OFF(0) */
all_multicast : 1, /**< RX all multicast mode ON(1) / OFF(0). */
dev_started : 1,   /**< Device state: STARTED(1) / STOPPED(0). 
*/
-   lro : 1;   /**< RX LRO is ON(1) / OFF(0) */
+   lro : 1,  /**< RX LRO is ON(1) / OFF(0) */
+   dev_configured : 1;
+   /**< Device configuration state:
+* CONFIGURED(1) / NOT CONFIGURED(0).
+*/
uint8_t rx_queue_state[RTE_MAX_QUEUES_PER_PORT];
/**< Queues state: HAIRPIN(2) / STARTED(1) / STOPPED(0). */
uint8_t tx_queue_state[RTE_MAX_QUEUES_PER_PORT];

[dpdk-dev] [PATCH v2 2/2] net/bnxt: workaround for spurious zero counter values in Thor

2021-05-31 Thread Somnath Kotur

There is a HW bug that can result in certain stats being reported as
zero.
Workaround this by ignoring stats with a value of zero based on the
previously stored snapshot of the same stat.
This bug mainly manifests in the output of func_qstats as FW aggregrates
each ring's stat value to give the per function stat and if one of
them is zero, the per function stat value ends up being lower than the
previous snapshot which shows up as a zero PPS value in testpmd.
Eliminate invocation of func_qstats and aggregate the per-ring stat
values in the driver itself to derive the func_qstats output post
accounting for the spurious zero stat value.

Signed-off-by: Somnath Kotur 
Reviewed-by: Lance Richardson 
Reviewed-by: Kalesh AP 
---
v2: 
 - Sum counters across ALL rings for function stats instead of the ones 
reported for
 - Allocate/free the previous ring stats(Rx/Tx) in dev_start/stop respectively
---
 drivers/net/bnxt/bnxt.h|  45 +++
 drivers/net/bnxt/bnxt_ethdev.c |  37 ++
 drivers/net/bnxt/bnxt_hwrm.c   | 108 +++
 drivers/net/bnxt/bnxt_hwrm.h   |   5 +-
 drivers/net/bnxt/bnxt_stats.c  | 131 ++---
 5 files changed, 296 insertions(+), 30 deletions(-)

diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index db67bff127..e93a7eb933 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -609,6 +609,49 @@ struct bnxt_flow_stat_info {
struct bnxt_ctx_mem_buf_info tx_fc_out_tbl;
 };
 
+struct bnxt_ring_stats {
+   /* Number of transmitted unicast packets */
+   uint64_ttx_ucast_pkts;
+   /* Number of transmitted multicast packets */
+   uint64_ttx_mcast_pkts;
+   /* Number of transmitted broadcast packets */
+   uint64_ttx_bcast_pkts;
+   /* Number of packets discarded in transmit path */
+   uint64_ttx_discard_pkts;
+   /* Number of packets in transmit path with error */
+   uint64_ttx_error_pkts;
+   /* Number of transmitted bytes for unicast traffic */
+   uint64_ttx_ucast_bytes;
+   /* Number of transmitted bytes for multicast traffic */
+   uint64_ttx_mcast_bytes;
+   /* Number of transmitted bytes for broadcast traffic */
+   uint64_ttx_bcast_bytes;
+   /* Number of received unicast packets */
+   uint64_trx_ucast_pkts;
+   /* Number of received multicast packets */
+   uint64_trx_mcast_pkts;
+   /* Number of received broadcast packets */
+   uint64_trx_bcast_pkts;
+   /* Number of packets discarded in receive path */
+   uint64_trx_discard_pkts;
+   /* Number of packets in receive path with errors */
+   uint64_trx_error_pkts;
+   /* Number of received bytes for unicast traffic */
+   uint64_trx_ucast_bytes;
+   /* Number of received bytes for multicast traffic */
+   uint64_trx_mcast_bytes;
+   /* Number of received bytes for broadcast traffic */
+   uint64_trx_bcast_bytes;
+   /* Number of aggregated unicast packets */
+   uint64_trx_agg_pkts;
+   /* Number of aggregated unicast bytes */
+   uint64_trx_agg_bytes;
+   /* Number of aggregation events */
+   uint64_trx_agg_events;
+   /* Number of aborted aggregations */
+   uint64_trx_agg_aborts;
+};
+
 struct bnxt {
void*bar0;
 
@@ -832,6 +875,8 @@ struct bnxt {
struct bnxt_flow_stat_info *flow_stat;
uint16_tmax_num_kflows;
uint16_ttx_cfa_action;
+   struct bnxt_ring_stats  *prev_rx_ring_stats;
+   struct bnxt_ring_stats  *prev_tx_ring_stats;
 };
 
 static
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 3778e28cca..e28ee16f0c 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -686,6 +686,38 @@ static int bnxt_update_phy_setting(struct bnxt *bp)
return rc;
 }
 
+static void bnxt_free_prev_ring_stats(struct bnxt *bp)
+{
+   rte_free(bp->prev_rx_ring_stats);
+   rte_free(bp->prev_tx_ring_stats);
+
+   bp->prev_rx_ring_stats = NULL;
+   bp->prev_tx_ring_stats = NULL;
+}
+
+static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
+{
+   bp->prev_rx_ring_stats =  rte_zmalloc("bnxt_prev_rx_ring_stats",
+ sizeof(struct bnxt_ring_stats) *
+ bp->rx_cp_nr_rings,
+ 0);
+   if (bp->prev_rx_ring_stats == NULL)
+   return -ENOMEM;
+
+   bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
+sizeof(struct bnxt_ring_stats) *
+bp->tx_cp_nr_rings,
+0);
+   if (bp->prev_tx_ri

Re: [dpdk-dev] [PATCH] net: introduce IPv4 ihl and version fields

2021-05-31 Thread Ananyev, Konstantin




> > > > > RTE IPv4 header definition combines the `version' and `ihl'
> > > > > fields into a single structure member.
> > > > > This patch introduces dedicated structure members for both
> > > `version'
> > > > > and `ihl' IPv4 fields. Separated header fields definitions allow
> > > > > to create simplified code to match on the IHL value in a flow rule.
> > > > > The original `version_ihl' structure member is kept for backward
> > > > > compatibility.
> > > > >
> > > > > Signed-off-by: Gregory Etelson 
> > > > > ---
> > > > >  app/test/test_flow_classify.c |  8 
> > > > >  lib/net/rte_ip.h  | 16 +++-
> > > > >  2 files changed, 19 insertions(+), 5 deletions(-)
> > > > >
> > > > > diff --git a/app/test/test_flow_classify.c
> > > > > b/app/test/test_flow_classify.c index 951606f248..4f64be5357
> > > > > 100644
> > > > > --- a/app/test/test_flow_classify.c
> > > > > +++ b/app/test/test_flow_classify.c
> > > > > @@ -95,7 +95,7 @@ static struct rte_acl_field_def
> > > > > ipv4_defs[NUM_FIELDS_IPV4] = {
> > > > >   *  dst mask 255.255.255.00 / udp src is 32 dst is 33 / end"
> > > > >   */
> > > > >  static struct rte_flow_item_ipv4 ipv4_udp_spec_1 = {
> > > > > - { 0, 0, 0, 0, 0, 0, IPPROTO_UDP, 0,
> > > > > + { { .version_ihl = 0}, 0, 0, 0, 0, 0, IPPROTO_UDP, 0,
> > > > > RTE_IPV4(2, 2, 2, 3), RTE_IPV4(2, 2, 2, 7)}  };  static const
> > > > > struct rte_flow_item_ipv4 ipv4_mask_24 = { @@ -131,7 +131,7 @@
> > > > > static struct rte_flow_item  end_item = {
> > RTE_FLOW_ITEM_TYPE_END,
> > > > >   *  dst mask 255.255.255.00 / tcp src is 16 dst is 17 / end"
> > > > >   */
> > > > >  static struct rte_flow_item_ipv4 ipv4_tcp_spec_1 = {
> > > > > - { 0, 0, 0, 0, 0, 0, IPPROTO_TCP, 0,
> > > > > + { { .version_ihl = 0}, 0, 0, 0, 0, 0, IPPROTO_TCP, 0,
> > > > > RTE_IPV4(1, 2, 3, 4), RTE_IPV4(5, 6, 7, 8)}  };
> > > > >
> > > > > @@ -150,8 +150,8 @@ static struct rte_flow_item  tcp_item_1 = {
> > > > > RTE_FLOW_ITEM_TYPE_TCP,
> > > > >   *  dst mask 255.255.255.00 / sctp src is 16 dst is 17/ end"
> > > > >   */
> > > > >  static struct rte_flow_item_ipv4 ipv4_sctp_spec_1 = {
> > > > > - { 0, 0, 0, 0, 0, 0, IPPROTO_SCTP, 0, RTE_IPV4(11, 12, 13, 14),
> > > > > - RTE_IPV4(15, 16, 17, 18)}
> > > > > + { { .version_ihl = 0}, 0, 0, 0, 0, 0, IPPROTO_SCTP, 0,
> > > > > + RTE_IPV4(11, 12, 13, 14), RTE_IPV4(15, 16, 17, 18)}
> > > > >  };
> > > > >
> > > > >  static struct rte_flow_item_sctp sctp_spec_1 = { diff --git
> > > > > a/lib/net/rte_ip.h b/lib/net/rte_ip.h index 4b728969c1..684bb028b2
> > > > > 100644
> > > > > --- a/lib/net/rte_ip.h
> > > > > +++ b/lib/net/rte_ip.h
> > > > > @@ -38,7 +38,21 @@ extern "C" {
> > > > >   * IPv4 Header
> > > > >   */
> > > > >  struct rte_ipv4_hdr {
> > > > > - uint8_t  version_ihl;   /**< version and header length */
> > > > > + __extension__
> > > > > + union {
> > > > > + uint8_t version_ihl;/**< version and header length */
> > > > > + struct {
> > > > > +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
> > > > > + uint8_t ihl:4;
> > > > > + uint8_t version:4; #elif RTE_BYTE_ORDER ==
> > > > > +RTE_BIG_ENDIAN
> > > > > + uint8_t version:4;
> > > > > + uint8_t ihl:4;
> > > > > +#else
> > > > > +#error "setup endian definition"
> > > > > +#endif
> > > > > + };
> > > > > + };
> > > > >   uint8_t  type_of_service;   /**< type of service */
> > > > >   rte_be16_t total_length;/**< length of packet */
> > > > >   rte_be16_t packet_id;   /**< packet ID */
> > > > > --
> > > > > 2.31.1
> > > > >
> > > >
> > > > This does not break the ABI, but it could be discussed if it breaks
> > > the API due to the required structure initialization changes shown in
> > > > test_flow_classify.c.
> > >
> > > Yep, I guess it might be classified as API change.
> > > Another thing that concerns me - it is not the only place in IPv4
> > > header when we unite multiple bit-fields into one field:
> > > type_of_service, fragment_offset.
> > > If we start splitting ipv4 fields into actual bitfields, I suppose
> > > we'll end-up splitting these ones too.
> > > But I am not sure it will pay off - as compiler not always generates
> > > optimal code for reading/updating bitfields.
> > > Did you consider just adding extra macros to simplify access to these
> > > fields (like RTE_IPV4_HDR_(GET_SET)_*), instead?
> > >
> >
> > Let's please not introduce accessor macros for bitfields. If we don't
> > introduce bitfields like these, I would rather stick with the current _MASK,
> > _SHIFT and _FLAG defines.
> >
> > Yes, this change will lead to the introduction of more bitfields, both here
> > and in other places. We already accepted it in the eCPRI structure
> > (/lib/net/rte_ecpri.h), so why not just generally accept it.
> >
> > Are modern compilers really worse at handling a bitfield defined like this,
> > compared to handling a single uint8_t with hand coding? I consider you

[dpdk-dev] [RFC 0/2] support VXLAN header last 8-bits matching

2021-05-31 Thread rongwei liu

This update adds support for the VXLAN last 8-bits matching when
creating steering rules. At the PCIe probe stage, we create a
dummy VXLAN matcher using misc5 to check rdma-core library's
capability.

The logic is, group 0 depends on HCA_CAP to enable misc or misc5
for VXLAN matching while group non zero depends on the rdma-core
capability.

Add a new testpmd pattern field 'last_rsvd' that supports the
last 8-bits matching of VXLAN header.

The examples for the "last_rsvd" pattern field are as below:

1. ...pattern eth / ipv4 / udp / vxlan last_rsvd is 0x80 / end ...
This flow will exactly match the last 8-bits to be 0x80.

2. ...pattern eth / ipv4 / udp / vxlan last_rsvd spec 0x80
vxlan mask 0x80 / end ...
This flow will only match the MSB of the last 8-bits to be 1.

rongwei liu (2):
  drivers: add VXLAN header the last 8-bits matching support
  app/testpmd: support VXLAN last 8-bits field matching

 app/test-pmd/cmdline_flow.c |   9 ++
 app/test-pmd/util.c |   5 +-
 doc/guides/nics/mlx5.rst|  11 +-
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |   1 +
 drivers/common/mlx5/mlx5_devx_cmds.c|   3 +
 drivers/common/mlx5/mlx5_devx_cmds.h|   6 +
 drivers/common/mlx5/mlx5_prm.h  |  41 +-
 drivers/net/mlx5/linux/mlx5_os.c|  77 ++
 drivers/net/mlx5/mlx5.h |   2 +
 drivers/net/mlx5/mlx5_flow.c|  26 +++-
 drivers/net/mlx5/mlx5_flow.h|   4 +-
 drivers/net/mlx5/mlx5_flow_dv.c | 152 ++--
 drivers/net/mlx5/mlx5_flow_verbs.c  |   3 +-
 drivers/vdpa/mlx5/mlx5_vdpa_steer.c |   6 +-
 14 files changed, 283 insertions(+), 63 deletions(-)

-- 
2.27.0

[dpdk-dev] [RFC 2/2] app/testpmd: support VXLAN last 8-bits field matching

2021-05-31 Thread rongwei liu

Add a new testpmd pattern field 'last_rsvd' that supports the
last 8-bits matching of VXLAN header.

The examples for the "last_rsvd" pattern field are as below:

1. ...pattern eth / ipv4 / udp / vxlan last_rsvd is 0x80 / end ...

This flow will exactly match the last 8-bits to be 0x80.

2. ...pattern eth / ipv4 / udp / vxlan last_rsvd spec 0x80
vxlan mask 0x80 / end ...

This flow will only match the MSB of the last 8-bits to be 1.

Signed-off-by: rongwei liu 
---
 app/test-pmd/cmdline_flow.c | 9 +
 app/test-pmd/util.c | 5 +++--
 doc/guides/testpmd_app_ug/testpmd_funcs.rst | 1 +
 3 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
index 1c587bb7b8..6e76a625ca 100644
--- a/app/test-pmd/cmdline_flow.c
+++ b/app/test-pmd/cmdline_flow.c
@@ -207,6 +207,7 @@ enum index {
ITEM_SCTP_CKSUM,
ITEM_VXLAN,
ITEM_VXLAN_VNI,
+   ITEM_VXLAN_LAST_RSVD,
ITEM_E_TAG,
ITEM_E_TAG_GRP_ECID_B,
ITEM_NVGRE,
@@ -1129,6 +1130,7 @@ static const enum index item_sctp[] = {
 
 static const enum index item_vxlan[] = {
ITEM_VXLAN_VNI,
+   ITEM_VXLAN_LAST_RSVD,
ITEM_NEXT,
ZERO,
 };
@@ -2806,6 +2808,13 @@ static const struct token token_list[] = {
.next = NEXT(item_vxlan, NEXT_ENTRY(UNSIGNED), item_param),
.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_vxlan, vni)),
},
+   [ITEM_VXLAN_LAST_RSVD] = {
+   .name = "last_rsvd",
+   .help = "VXLAN last reserved bits",
+   .next = NEXT(item_vxlan, NEXT_ENTRY(UNSIGNED), item_param),
+   .args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_vxlan,
+rsvd1)),
+   },
[ITEM_E_TAG] = {
.name = "e_tag",
.help = "match E-Tag header",
diff --git a/app/test-pmd/util.c b/app/test-pmd/util.c
index a9e431a8b2..59626518d5 100644
--- a/app/test-pmd/util.c
+++ b/app/test-pmd/util.c
@@ -266,8 +266,9 @@ dump_pkt_burst(uint16_t port_id, uint16_t queue, struct 
rte_mbuf *pkts[],
vx_vni = rte_be_to_cpu_32(vxlan_hdr->vx_vni);
MKDUMPSTR(print_buf, buf_size, cur_len,
  " - VXLAN packet: packet type =%d, "
- "Destination UDP port =%d, VNI = %d",
- packet_type, udp_port, vx_vni >> 8);
+ "Destination UDP port =%d, VNI = %d, "
+ "last_rsvd = %d", packet_type,
+ udp_port, vx_vni >> 8, vx_vni & 0xff);
}
}
MKDUMPSTR(print_buf, buf_size, cur_len,
diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst 
b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
index 33857acf54..4ca3103067 100644
--- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
+++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
@@ -3694,6 +3694,7 @@ This section lists supported pattern items and their 
attributes, if any.
 - ``vxlan``: match VXLAN header.
 
   - ``vni {unsigned}``: VXLAN identifier.
+  - ``last_rsvd {unsigned}``: VXLAN last reserved 8-bits.
 
 - ``e_tag``: match IEEE 802.1BR E-Tag header.
 
-- 
2.27.0

[dpdk-dev] [RFC 1/2] drivers: add VXLAN header the last 8-bits matching support

2021-05-31 Thread rongwei liu

This update adds support for the VXLAN alert bits matching when
creating steering rules. At the PCIe probe stage, we create a
dummy VXLAN matcher using misc5 to check rdma-core library's
capability.

The logic is, group 0 depends on HCA_CAP to enable misc or misc5
for VXLAN matching while group non zero depends on the rdma-core
capability.

Signed-off-by: rongwei liu 
---
 doc/guides/nics/mlx5.rst |  11 +-
 drivers/common/mlx5/mlx5_devx_cmds.c |   3 +
 drivers/common/mlx5/mlx5_devx_cmds.h |   6 ++
 drivers/common/mlx5/mlx5_prm.h   |  41 ++--
 drivers/net/mlx5/linux/mlx5_os.c |  77 ++
 drivers/net/mlx5/mlx5.h  |   2 +
 drivers/net/mlx5/mlx5_flow.c |  26 -
 drivers/net/mlx5/mlx5_flow.h |   4 +-
 drivers/net/mlx5/mlx5_flow_dv.c  | 152 +++
 drivers/net/mlx5/mlx5_flow_verbs.c   |   3 +-
 drivers/vdpa/mlx5/mlx5_vdpa_steer.c  |   6 +-
 11 files changed, 270 insertions(+), 61 deletions(-)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 83299646dd..0bfe55dbdc 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -186,8 +186,15 @@ Limitations
   size and ``txq_inline_min`` settings and may be from 2 (worst case forced by 
maximal
   inline settings) to 58.
 
-- Flows with a VXLAN Network Identifier equal (or ends to be equal)
-  to 0 are not supported.
+- Match on VXLAN supports the following fields only:
+
+ - VNI
+ - Last reserved 8-bits
+
+  Last reserved 8-bits matching is only supported When using DV flow
+  engine (``dv_flow_en`` = 1).
+  Group zero's behavior may differ which depends on FW.
+  Matching value equals 0 (value & mask) is not supported.
 
 - L3 VXLAN and VXLAN-GPE tunnels cannot be supported together with MPLSoGRE 
and MPLSoUDP.
 
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c 
b/drivers/common/mlx5/mlx5_devx_cmds.c
index f5914bce32..63ae95832d 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -947,6 +947,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
attr->log_max_ft_sampler_num = MLX5_GET
(flow_table_nic_cap, hcattr,
 flow_table_properties_nic_receive.log_max_ft_sampler_num);
+   attr->flow.tunnel_header_0_1 = MLX5_GET
+   (flow_table_nic_cap, hcattr,
+ft_field_support_2_nic_receive.tunnel_header_0_1);
attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
/* Query HCA offloads for Ethernet protocol. */
memset(in, 0, sizeof(in));
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h 
b/drivers/common/mlx5/mlx5_devx_cmds.h
index f8a17b886b..124f43e852 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -89,6 +89,11 @@ struct mlx5_hca_vdpa_attr {
uint64_t doorbell_bar_offset;
 };
 
+struct mlx5_hca_flow_attr {
+   uint32_t tunnel_header_0_1;
+   uint32_t tunnel_header_2_3;
+};
+
 /* HCA supports this number of time periods for LRO. */
 #define MLX5_LRO_NUM_SUPP_PERIODS 4
 
@@ -155,6 +160,7 @@ struct mlx5_hca_attr {
uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */
struct mlx5_hca_qos_attr qos;
struct mlx5_hca_vdpa_attr vdpa;
+   struct mlx5_hca_flow_attr flow;
int log_max_qp_sz;
int log_max_cq_sz;
int log_max_qp;
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 26761f5bd3..7950070976 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -977,6 +977,18 @@ struct mlx5_ifc_fte_match_set_misc4_bits {
u8 reserved_at_100[0x100];
 };
 
+struct mlx5_ifc_fte_match_set_misc5_bits {
+   u8 macsec_tag_0[0x20];
+   u8 macsec_tag_1[0x20];
+   u8 macsec_tag_2[0x20];
+   u8 macsec_tag_3[0x20];
+   u8 tunnel_header_0[0x20];
+   u8 tunnel_header_1[0x20];
+   u8 tunnel_header_2[0x20];
+   u8 tunnel_header_3[0x20];
+   u8 reserved[0x100];
+};
+
 /* Flow matcher. */
 struct mlx5_ifc_fte_match_param_bits {
struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
@@ -985,12 +997,13 @@ struct mlx5_ifc_fte_match_param_bits {
struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
+   struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
 /*
  * Add reserved bit to match the struct size with the size defined in PRM.
  * This extension is not required in Linux.
  */
 #ifndef HAVE_INFINIBAND_VERBS_H
-   u8 reserved_0[0x400];
+   u8 reserved_0[0x200];
 #endif
 };
 
@@ -1007,6 +1020,7 @@ enum {
MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,
+   MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT,
 };
 
 enum {
@@ -1784,7 +1798,12 @@ struct mlx

Re: [dpdk-dev] [21.08 PATCH v4 1/2] power: don't use rte prefix in internal code

2021-05-31 Thread David Hunt


Hi Anatoly

On 23/4/2021 12:03 PM, Anatoly Burakov wrote:

Currently, ACPI code uses rte_power_info as the struct name, which
gives the appearance that this is an externally visible API. Fix to
use internal namespace.

Signed-off-by: Anatoly Burakov 
---
  lib/power/power_acpi_cpufreq.c | 34 +-
  1 file changed, 17 insertions(+), 17 deletions(-)



Looks good. This brings the acpi driver code in line with the pstate 
driver code, which already

has it's struct called ptate_power_info.

Acked-by: David Hunt

Re: [dpdk-dev] [PATCH] net: introduce IPv4 ihl and version fields

2021-05-31 Thread Gregory Etelson

> > > > > > RTE IPv4 header definition combines the `version' and `ihl'
> > > > > > fields into a single structure member.
> > > > > > This patch introduces dedicated structure members for both
> > > > `version'
> > > > > > and `ihl' IPv4 fields. Separated header fields definitions
> > > > > > allow to create simplified code to match on the IHL value in a flow
> rule.
> > > > > > The original `version_ihl' structure member is kept for
> > > > > > backward compatibility.
> > > > > >
> > > > > > Signed-off-by: Gregory Etelson 
> > > > > > ---
> > > > > >  app/test/test_flow_classify.c |  8 
> > > > > >  lib/net/rte_ip.h  | 16 +++-
> > > > > >  2 files changed, 19 insertions(+), 5 deletions(-)
> > > > > >
> > > > > > diff --git a/app/test/test_flow_classify.c
> > > > > > b/app/test/test_flow_classify.c index 951606f248..4f64be5357
> > > > > > 100644
> > > > > > --- a/app/test/test_flow_classify.c
> > > > > > +++ b/app/test/test_flow_classify.c
> > > > > > @@ -95,7 +95,7 @@ static struct rte_acl_field_def
> > > > > > ipv4_defs[NUM_FIELDS_IPV4] = {
> > > > > >   *  dst mask 255.255.255.00 / udp src is 32 dst is 33 / end"
> > > > > >   */
> > > > > >  static struct rte_flow_item_ipv4 ipv4_udp_spec_1 = {
> > > > > > - { 0, 0, 0, 0, 0, 0, IPPROTO_UDP, 0,
> > > > > > + { { .version_ihl = 0}, 0, 0, 0, 0, 0, IPPROTO_UDP, 0,
> > > > > > RTE_IPV4(2, 2, 2, 3), RTE_IPV4(2, 2, 2, 7)}  };  static
> > > > > > const struct rte_flow_item_ipv4 ipv4_mask_24 = { @@ -131,7
> > > > > > +131,7 @@ static struct rte_flow_item  end_item = {
> > > RTE_FLOW_ITEM_TYPE_END,
> > > > > >   *  dst mask 255.255.255.00 / tcp src is 16 dst is 17 / end"
> > > > > >   */
> > > > > >  static struct rte_flow_item_ipv4 ipv4_tcp_spec_1 = {
> > > > > > - { 0, 0, 0, 0, 0, 0, IPPROTO_TCP, 0,
> > > > > > + { { .version_ihl = 0}, 0, 0, 0, 0, 0, IPPROTO_TCP, 0,
> > > > > > RTE_IPV4(1, 2, 3, 4), RTE_IPV4(5, 6, 7, 8)}  };
> > > > > >
> > > > > > @@ -150,8 +150,8 @@ static struct rte_flow_item  tcp_item_1 =
> > > > > > { RTE_FLOW_ITEM_TYPE_TCP,
> > > > > >   *  dst mask 255.255.255.00 / sctp src is 16 dst is 17/ end"
> > > > > >   */
> > > > > >  static struct rte_flow_item_ipv4 ipv4_sctp_spec_1 = {
> > > > > > - { 0, 0, 0, 0, 0, 0, IPPROTO_SCTP, 0, RTE_IPV4(11, 12, 13,
> > > > > > 14),
> > > > > > - RTE_IPV4(15, 16, 17, 18)}
> > > > > > + { { .version_ihl = 0}, 0, 0, 0, 0, 0, IPPROTO_SCTP, 0,
> > > > > > + RTE_IPV4(11, 12, 13, 14), RTE_IPV4(15, 16, 17, 18)}
> > > > > >  };
> > > > > >
> > > > > >  static struct rte_flow_item_sctp sctp_spec_1 = { diff --git
> > > > > > a/lib/net/rte_ip.h b/lib/net/rte_ip.h index
> > > > > > 4b728969c1..684bb028b2
> > > > > > 100644
> > > > > > --- a/lib/net/rte_ip.h
> > > > > > +++ b/lib/net/rte_ip.h
> > > > > > @@ -38,7 +38,21 @@ extern "C" {
> > > > > >   * IPv4 Header
> > > > > >   */
> > > > > >  struct rte_ipv4_hdr {
> > > > > > - uint8_t  version_ihl;   /**< version and header length */
> > > > > > + __extension__
> > > > > > + union {
> > > > > > + uint8_t version_ihl;/**< version and header length */
> > > > > > + struct {
> > > > > > +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
> > > > > > + uint8_t ihl:4;
> > > > > > + uint8_t version:4; #elif RTE_BYTE_ORDER ==
> > > > > > +RTE_BIG_ENDIAN
> > > > > > + uint8_t version:4;
> > > > > > + uint8_t ihl:4; #else #error "setup endian
> > > > > > +definition"
> > > > > > +#endif
> > > > > > + };
> > > > > > + };
> > > > > >   uint8_t  type_of_service;   /**< type of service */
> > > > > >   rte_be16_t total_length;/**< length of packet */
> > > > > >   rte_be16_t packet_id;   /**< packet ID */
> > > > > > --
> > > > > > 2.31.1
> > > > > >
> > > > >
> > > > > This does not break the ABI, but it could be discussed if it
> > > > > breaks
> > > > the API due to the required structure initialization changes shown
> > > > in
> > > > > test_flow_classify.c.
> > > >
> > > > Yep, I guess it might be classified as API change.
> > > > Another thing that concerns me - it is not the only place in IPv4
> > > > header when we unite multiple bit-fields into one field:
> > > > type_of_service, fragment_offset.
> > > > If we start splitting ipv4 fields into actual bitfields, I suppose
> > > > we'll end-up splitting these ones too.
> > > > But I am not sure it will pay off - as compiler not always
> > > > generates optimal code for reading/updating bitfields.
> > > > Did you consider just adding extra macros to simplify access to
> > > > these fields (like RTE_IPV4_HDR_(GET_SET)_*), instead?
> > > >
> > >
> > > Let's please not introduce accessor macros for bitfields. If we
> > > don't introduce bitfields like these, I would rather stick with the
> > > current _MASK, _SHIFT and _FLAG defines.
> > >
> > > Yes, this change will lead to the introduction of more bitfields,
> > > both here and in other places. We already accepted it in the eCPRI

[dpdk-dev] [PATCH v1] examples/power: add baseline mode to PMD power

2021-05-31 Thread David Hunt

The PMD Power Management scheme currently has 3 modes,
scale, monitor and pause. However, it would be nice to
have a baseline mode for easy comparison of power savings
with and without these modes.

This patch adds a 'baseline' mode were the pmd power
management is not enabled. Use --pmg-mgmt=baseline.

Signed-off-by: David Hunt 
---
 examples/l3fwd-power/main.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/examples/l3fwd-power/main.c b/examples/l3fwd-power/main.c
index f8dfed1634..34b0eaa401 100644
--- a/examples/l3fwd-power/main.c
+++ b/examples/l3fwd-power/main.c
@@ -1617,7 +1617,7 @@ print_usage(const char *prgname)
" empty polls, full polls, and core busyness to telemetry\n"
" --interrupt-only: enable interrupt-only mode\n"
" --pmd-mgmt MODE: enable PMD power management mode. "
-   "Currently supported modes: monitor, pause, scale\n",
+   "Currently supported modes: baseline, monitor, pause, scale\n",
prgname);
 }
 
@@ -1714,6 +1714,7 @@ parse_pmd_mgmt_config(const char *name)
 #define PMD_MGMT_MONITOR "monitor"
 #define PMD_MGMT_PAUSE   "pause"
 #define PMD_MGMT_SCALE   "scale"
+#define PMD_MGMT_BASELINE  "baseline"
 
if (strncmp(PMD_MGMT_MONITOR, name, sizeof(PMD_MGMT_MONITOR)) == 0) {
pmgmt_type = RTE_POWER_MGMT_TYPE_MONITOR;
@@ -1729,6 +1730,10 @@ parse_pmd_mgmt_config(const char *name)
pmgmt_type = RTE_POWER_MGMT_TYPE_SCALE;
return 0;
}
+   if (strncmp(PMD_MGMT_BASELINE, name, sizeof(PMD_MGMT_BASELINE)) == 0) {
+   pmgmt_type = -1;
+   return 0;
+   }
/* unknown PMD power management mode */
return -1;
 }
@@ -2767,7 +2772,8 @@ main(int argc, char **argv)
 "Fail to add ptype cb\n");
}
 
-   if (app_mode == APP_MODE_PMD_MGMT) {
+   if ((app_mode == APP_MODE_PMD_MGMT) &&
+   (pmgmt_type >= 0)) {
ret = rte_power_ethdev_pmgmt_queue_enable(
lcore_id, portid, queueid,
pmgmt_type);
-- 
2.17.1

[dpdk-dev] [PATCH] net/mlx5: update GENEVE TLV option exist bit

2021-05-31 Thread Shiri Kuzin

The GENEVE TLV option matching is done using a flex parser.

Recent update in firmware, requires that in order to match on the
GENEVE TLV option the "geneve_tlv_option_0_exist" bit should be set.

Add the new "geneve_tlv_option_0_exist" setting when translating the
GENEVE TLV option item.

Signed-off-by: Shiri Kuzin 
Acked-by: Viacheslav Ovsiienko 
---
 drivers/common/mlx5/mlx5_prm.h  | 3 ++-
 drivers/net/mlx5/mlx5_flow_dv.c | 2 ++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 26761f5bd3..3e4e6fa216 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -853,7 +853,8 @@ struct mlx5_ifc_fte_match_set_misc_bits {
u8 vxlan_vni[0x18];
u8 reserved_at_b8[0x8];
u8 geneve_vni[0x18];
-   u8 reserved_at_e4[0x7];
+   u8 reserved_at_e4[0x6];
+   u8 geneve_tlv_option_0_exist[0x1];
u8 geneve_oam[0x1];
u8 reserved_at_e0[0xc];
u8 outer_ipv6_flow_label[0x14];
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index c50649a107..f009689cff 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -8939,6 +8939,8 @@ flow_dv_translate_item_geneve_opt(struct rte_eth_dev 
*dev, void *matcher,
MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
 geneve_opt_v->option_len + 1);
}
+   MLX5_SET(fte_match_set_misc, misc_m, geneve_tlv_option_0_exist, 1);
+   MLX5_SET(fte_match_set_misc, misc_v, geneve_tlv_option_0_exist, 1);
/* Set the data. */
if (geneve_opt_v->data) {
memcpy(&opt_data_key, geneve_opt_v->data,
-- 
2.27.0

[dpdk-dev] [PATCH] kni: fix wrong mbuf alloc count in kni_allocate_mbufs

2021-05-31 Thread wangyunjian

From: Yunjian Wang 

In kni_allocate_mbufs(), we alloc mbuf for alloc_q as this code.
allocq_free = (kni->alloc_q->read - kni->alloc_q->write - 1) \
& (MAX_MBUF_BURST_NUM - 1);
The value of allocq_free maybe zero (e.g 32 & (32 - 1) = 0), and
it will not fill the alloc_q. When the alloc_q's free count is
zero, it will drop the packet in kernel kni.

In this patch, we set the allocq_free as the min between
MAX_MBUF_BURST_NUM and the free count of the alloc_q.

Signed-off-by: Cheng Liu 
Signed-off-by: Yunjian Wang 
---
 lib/kni/rte_kni.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/lib/kni/rte_kni.c b/lib/kni/rte_kni.c
index 9dae6a8d7c..20d8f20cef 100644
--- a/lib/kni/rte_kni.c
+++ b/lib/kni/rte_kni.c
@@ -677,8 +677,9 @@ kni_allocate_mbufs(struct rte_kni *kni)
return;
}
 
-   allocq_free = (kni->alloc_q->read - kni->alloc_q->write - 1)
-   & (MAX_MBUF_BURST_NUM - 1);
+   allocq_free = kni_fifo_free_count(kni->alloc_q);
+   allocq_free = (allocq_free > MAX_MBUF_BURST_NUM) ?
+ MAX_MBUF_BURST_NUM : allocq_free;
for (i = 0; i < allocq_free; i++) {
pkts[i] = rte_pktmbuf_alloc(kni->pktmbuf_pool);
if (unlikely(pkts[i] == NULL)) {
-- 
2.23.0

[dpdk-dev] [PATCH 00/15] Add support for fourth generation of Intel QuickAssist Technology devices

This patchset adds support for fourth generation (GEN4) of Intel QuickAssist 
Technology (QAT) devices.
Symmetric crypto PMD is enabled with following algorithms:

* AES-CBC
* AES-CMAC
* AES-XCBC MAC
* NULL (auth, cipher)
* SHA1-HMAC
* SHA2-HMAC (224, 256, 384, 512)
* Chacha20-Poly1305
* AES-CCM
* AES-GCM

Other services (compression, asymmetric crypto) are not added with this 
patchset.

Adam Dybkowski (2):
  crypto/qat: enable RAW API on QAT GEN1-3 only
  test/crypto: check if RAW API is supported

Arek Kusztal (12):
  common/qat: rework qp per service function
  crypto/qat: add fourth generation qat devices support
  crypto/qat: enable gen4 legacy algorithms
  crypto/qat: add fourth generation ucs slice type, add ctr mode
  crypto/qat: rename content descriptor functions
  crypto/qat: add legacy gcm and ccm
  crypto/qat: rework init common header function
  crypto/qat: add aes gcm in ucs spc mode
  crypto/qat: add chacha-poly in ucs spc mode
  crypto/qat: add gmac in legacy mode on fourth generation
  common/qat: add pf2vf communication in qat
  common/qat: reset ring pairs before setting pmd

Fan Zhang (1):
  crypto/qat: update raw dp api

 app/test/test_cryptodev.c |  34 +-
 doc/guides/cryptodevs/qat.rst |  10 +-
 doc/guides/rel_notes/release_21_08.rst|   6 +
 drivers/common/qat/meson.build|   1 +
 drivers/common/qat/qat_adf/adf_pf2vf_msg.h| 154 ++
 .../adf_transport_access_macros_gen4.h|  52 ++
 .../adf_transport_access_macros_gen4vf.h  |  48 ++
 drivers/common/qat/qat_adf/icp_qat_fw_la.h|  28 ++
 drivers/common/qat/qat_adf/icp_qat_hw.h   |  10 +
 drivers/common/qat/qat_common.h   |   3 +-
 drivers/common/qat/qat_device.c   |  69 +++
 drivers/common/qat/qat_device.h   |  17 +
 drivers/common/qat/qat_pf2vf.c|  80 +++
 drivers/common/qat/qat_pf2vf.h|  19 +
 drivers/common/qat/qat_qp.c   | 246 ++---
 drivers/common/qat/qat_qp.h   |  31 +-
 drivers/compress/qat/qat_comp_pmd.c   |  16 +-
 drivers/crypto/qat/qat_asym_pmd.c |  16 +-
 drivers/crypto/qat/qat_sym.c  |  57 ++-
 drivers/crypto/qat/qat_sym_capabilities.h | 472 ++
 drivers/crypto/qat/qat_sym_hw_dp.c| 419 
 drivers/crypto/qat/qat_sym_pmd.c  |  53 +-
 drivers/crypto/qat/qat_sym_session.c  | 334 -
 drivers/crypto/qat/qat_sym_session.h  |  31 +-
 24 files changed, 1731 insertions(+), 475 deletions(-)
 create mode 100644 drivers/common/qat/qat_adf/adf_pf2vf_msg.h
 create mode 100644 
drivers/common/qat/qat_adf/adf_transport_access_macros_gen4.h
 create mode 100644 
drivers/common/qat/qat_adf/adf_transport_access_macros_gen4vf.h
 create mode 100644 drivers/common/qat/qat_pf2vf.c
 create mode 100644 drivers/common/qat/qat_pf2vf.h

-- 
2.25.1

[dpdk-dev] [PATCH 01/15] common/qat: rework qp per service function

Different generations of Intel QuickAssist Technology devices may
differ in approach to allocate queues. Queue pair number function
therefore needs to be more generic.

Signed-off-by: Arek Kusztal 
---
 drivers/common/qat/qat_qp.c | 15 ++-
 drivers/common/qat/qat_qp.h |  2 +-
 drivers/compress/qat/qat_comp_pmd.c |  9 -
 drivers/crypto/qat/qat_asym_pmd.c   |  9 -
 drivers/crypto/qat/qat_sym_pmd.c|  9 -
 5 files changed, 23 insertions(+), 21 deletions(-)

diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index 4a8078541c..aa64d2e168 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -145,14 +145,19 @@ static void adf_queue_arb_disable(struct qat_queue *txq, 
void *base_addr,
rte_spinlock_t *lock);
 
 
-int qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
+int qat_qps_per_service(struct qat_pci_device *qat_dev,
enum qat_service_type service)
 {
-   int i, count;
-
-   for (i = 0, count = 0; i < ADF_MAX_QPS_ON_ANY_SERVICE; i++)
-   if (qp_hw_data[i].service_type == service)
+   int i = 0, count = 0, max_ops_per_srv = 0;
+   const struct qat_qp_hw_data*
+   sym_hw_qps = qat_gen_config[qat_dev->qat_dev_gen]
+   .qp_hw_data[service];
+
+   max_ops_per_srv = ADF_MAX_QPS_ON_ANY_SERVICE;
+   for (; i < max_ops_per_srv; i++)
+   if (sym_hw_qps[i].service_type == service)
count++;
+
return count;
 }
 
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index 74f7e7daee..d353e8552b 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -98,7 +98,7 @@ qat_qp_setup(struct qat_pci_device *qat_dev,
struct qat_qp_config *qat_qp_conf);
 
 int
-qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
+qat_qps_per_service(struct qat_pci_device *qat_dev,
enum qat_service_type service);
 
 int
diff --git a/drivers/compress/qat/qat_comp_pmd.c 
b/drivers/compress/qat/qat_comp_pmd.c
index 8de41f6b6e..6eb1ae3a21 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -106,6 +106,7 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t 
qp_id,
struct qat_qp **qp_addr =
(struct qat_qp **)&(dev->data->queue_pairs[qp_id]);
struct qat_comp_dev_private *qat_private = dev->data->dev_private;
+   struct qat_pci_device *qat_dev = qat_private->qat_dev;
const struct qat_qp_hw_data *comp_hw_qps =
qat_gen_config[qat_private->qat_dev->qat_dev_gen]
  .qp_hw_data[QAT_SERVICE_COMPRESSION];
@@ -117,7 +118,7 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t 
qp_id,
if (ret < 0)
return ret;
}
-   if (qp_id >= qat_qps_per_service(comp_hw_qps,
+   if (qp_id >= qat_qps_per_service(qat_dev,
 QAT_SERVICE_COMPRESSION)) {
QAT_LOG(ERR, "qp_id %u invalid for this device", qp_id);
return -EINVAL;
@@ -592,13 +593,11 @@ qat_comp_dev_info_get(struct rte_compressdev *dev,
struct rte_compressdev_info *info)
 {
struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
-   const struct qat_qp_hw_data *comp_hw_qps =
-   qat_gen_config[comp_dev->qat_dev->qat_dev_gen]
- .qp_hw_data[QAT_SERVICE_COMPRESSION];
+   struct qat_pci_device *qat_dev = comp_dev->qat_dev;
 
if (info != NULL) {
info->max_nb_queue_pairs =
-   qat_qps_per_service(comp_hw_qps,
+   qat_qps_per_service(qat_dev,
QAT_SERVICE_COMPRESSION);
info->feature_flags = dev->feature_flags;
info->capabilities = comp_dev->qat_dev_capabilities;
diff --git a/drivers/crypto/qat/qat_asym_pmd.c 
b/drivers/crypto/qat/qat_asym_pmd.c
index a2c8aca2c1..f0c8ed1bcf 100644
--- a/drivers/crypto/qat/qat_asym_pmd.c
+++ b/drivers/crypto/qat/qat_asym_pmd.c
@@ -54,12 +54,10 @@ static void qat_asym_dev_info_get(struct rte_cryptodev *dev,
  struct rte_cryptodev_info *info)
 {
struct qat_asym_dev_private *internals = dev->data->dev_private;
-   const struct qat_qp_hw_data *asym_hw_qps =
-   qat_gen_config[internals->qat_dev->qat_dev_gen]
- .qp_hw_data[QAT_SERVICE_ASYMMETRIC];
+   struct qat_pci_device *qat_dev = internals->qat_dev;
 
if (info != NULL) {
-   info->max_nb_queue_pairs = qat_qps_per_service(asym_hw_qps,
+   info->max_nb_queue_pairs = qat_qps_per_service(qat_dev,
QAT_SERVICE_ASYMMETRIC);

[dpdk-dev] [PATCH 02/15] crypto/qat: add fourth generation qat devices support

This commit adds support for generation 4 (GEN4) of
Intel QuickAssist (QAT) Technology devices.

Signed-off-by: Arek Kusztal 
---
 doc/guides/cryptodevs/qat.rst |  10 +-
 doc/guides/rel_notes/release_21_08.rst|   6 +
 .../adf_transport_access_macros_gen4.h|  52 
 .../adf_transport_access_macros_gen4vf.h  |  48 
 drivers/common/qat/qat_common.h   |   3 +-
 drivers/common/qat/qat_device.c   |  22 ++
 drivers/common/qat/qat_device.h   |   5 +
 drivers/common/qat/qat_qp.c   | 243 +-
 drivers/common/qat/qat_qp.h   |  29 ++-
 drivers/compress/qat/qat_comp_pmd.c   |   7 +-
 drivers/crypto/qat/qat_asym_pmd.c |   7 +-
 drivers/crypto/qat/qat_sym_pmd.c  |  33 ++-
 drivers/crypto/qat/qat_sym_session.c  |   1 +
 13 files changed, 388 insertions(+), 78 deletions(-)
 create mode 100644 
drivers/common/qat/qat_adf/adf_transport_access_macros_gen4.h
 create mode 100644 
drivers/common/qat/qat_adf/adf_transport_access_macros_gen4vf.h

diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 96f5ab6afe..960e15d10c 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -25,6 +25,7 @@ poll mode crypto driver support for the following hardware 
accelerator devices:
 * ``Intel QuickAssist Technology 200xx``
 * ``Intel QuickAssist Technology D15xx``
 * ``Intel QuickAssist Technology C4xxx``
+* ``Intel QuickAssist Technology 4xxx``
 
 
 Features
@@ -94,15 +95,16 @@ All the usual chains are supported and also some mixed 
chains:
+==+===+=+==+==+
| NULL CIPHER  | Y | 2&3 | 2&3  | Y|
+--+---+-+--+--+
-   | SNOW3G UEA2  | 2&3   | Y   | 2&3  | 2&3  |
+   | SNOW3G UEA2  | 2&3   | 1&2&3   | 2&3  | 2&3  |
+--+---+-+--+--+
| ZUC EEA3 | 2&3   | 2&3 | 2&3  | 2&3  |
+--+---+-+--+--+
-   | AES CTR  | Y | 2&3 | 2&3  | Y|
+   | AES CTR  | 1&2&3 | 2&3 | 2&3  | Y|
+--+---+-+--+--+
 
 * The combinations marked as "Y" are supported on all QAT hardware versions.
-* The combinations marked as "2&3" are supported on GEN2/GEN3 QAT hardware 
only.
+* The combinations marked as "2&3" are supported on GEN2 and GEN3 QAT hardware 
only.
+* The combinations marked as "1&2&3" are supported on GEN1, GEN2 and GEN3 QAT 
hardware only.
 
 
 Limitations
@@ -373,6 +375,8 @@ to see the full table)

+-+-+-+-+--+---+---+++--+++
| Yes | No  | No  | 3   | C4xxx| p | qat_c4xxx | c4xxx  
| 18a0   | 1| 18a1   | 128|

+-+-+-+-+--+---+---+++--+++
+   | Yes | No  | No  | 4   | 4xxx | 5.11.0+   | qat_4xxx  | 4xxx   
| 4940   | 4| 4941   | 16 |
+   
+-+-+-+-+--+---+---+++--+++
 
 * Note: Symmetric mixed crypto algorithms feature on Gen 2 works only with 
01.org driver version 4.9.0+
 
diff --git a/doc/guides/rel_notes/release_21_08.rst 
b/doc/guides/rel_notes/release_21_08.rst
index a6ecfdf3ce..69ef43acf6 100644
--- a/doc/guides/rel_notes/release_21_08.rst
+++ b/doc/guides/rel_notes/release_21_08.rst
@@ -55,6 +55,12 @@ New Features
  Also, make sure to start the actual text at the margin.
  ===
 
+* **Updated Intel QuickAssist PMD.**
+
+  Added fourth generation of QuickAssist Technology devices support.
+  Only symmetric crypto has been currently enabled, compression and asymmetric
+  crypto PMD will fail to create.
+
 
 Removed Items
 -
diff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros_gen4.h 
b/drivers/common/qat/qat_adf/adf_transport_access_macros_gen4.h
new file mode 100644
index 00..3ab873db5e
--- /dev/null
+++ b/drivers/common/qat/qat_adf/adf_transport_access_macros_gen4.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#ifndef ADF_TRANSPORT_ACCESS_MACROS_GEN4_H
+#define ADF_TRANSPORT_ACCESS_MACROS_GEN4_H
+
+#include "adf_transport_access_macros.h"
+
+#define ADF_RINGS_PER_INT_SRCSEL_GEN4 2
+#define ADF_BANK_INT_SRC_SEL_MASK_GEN4 0x44UL
+#define ADF_BANK_INT_FLAG_CLEAR_MASK_GEN4 0x3
+#define ADF_RING_BUNDLE_SIZE_GEN4 0x2000
+#define ADF_RING_CSR_ADDR_OFFSET_GEN4 0x10
+#define ADF_RING_CSR_RING_CONFIG_GEN4 0x1

[dpdk-dev] [PATCH 03/15] crypto/qat: enable gen4 legacy algorithms

This commit enables algorithms labeled as 'legacy'
on QAT generation 4 devices.
Following algorithms were enabled:
* AES-CBC
* AES-CMAC
* AES-XCBC MAC
* NULL (auth, cipher)
* SHA1-HMAC
* SHA2-HMAC (224, 256, 384, 512)

Signed-off-by: Arek Kusztal 
---
 drivers/crypto/qat/qat_sym_capabilities.h | 337 ++
 drivers/crypto/qat/qat_sym_pmd.c  |   9 +-
 2 files changed, 344 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/qat/qat_sym_capabilities.h 
b/drivers/crypto/qat/qat_sym_capabilities.h
index f7cab2f471..21c817bccc 100644
--- a/drivers/crypto/qat/qat_sym_capabilities.h
+++ b/drivers/crypto/qat/qat_sym_capabilities.h
@@ -731,6 +731,343 @@
}, }\
}
 
+#define QAT_BASE_GEN4_SYM_CAPABILITIES \
+   {   /* AES CBC */   \
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \
+   {.sym = {   \
+   .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,  \
+   {.cipher = {\
+   .algo = RTE_CRYPTO_CIPHER_AES_CBC,  \
+   .block_size = 16,   \
+   .key_size = {   \
+   .min = 16,  \
+   .max = 32,  \
+   .increment = 8  \
+   },  \
+   .iv_size = {\
+   .min = 16,  \
+   .max = 16,  \
+   .increment = 0  \
+   }   \
+   }, }\
+   }, }\
+   },  \
+   {   /* SHA1 HMAC */ \
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \
+   {.sym = {   \
+   .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\
+   {.auth = {  \
+   .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,  \
+   .block_size = 64,   \
+   .key_size = {   \
+   .min = 1,   \
+   .max = 64,  \
+   .increment = 1  \
+   },  \
+   .digest_size = {\
+   .min = 1,   \
+   .max = 20,  \
+   .increment = 1  \
+   },  \
+   .iv_size = { 0 }\
+   }, }\
+   }, }\
+   },  \
+   {   /* SHA224 HMAC */   \
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \
+   {.sym = {   \
+   .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\
+   {.auth = {  \
+   .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,\
+   .block_size = 64,   \
+   .key_size = {   \
+   .min = 1,   \
+   .max = 64,  \
+   .increment = 1  \
+   },  \
+   .digest_size = {\
+   .min = 1,   \
+   .max = 28,  \
+

[dpdk-dev] [PATCH 04/15] crypto/qat: add fourth generation ucs slice type, add ctr mode

This commit adds unified cipher slice to Intel QuickAssist
Technology PMD and enables AES-CTR algorithm.

Signed-off-by: Arek Kusztal 
---
 drivers/common/qat/qat_adf/icp_qat_fw_la.h | 28 ++
 drivers/common/qat/qat_adf/icp_qat_hw.h| 10 
 drivers/crypto/qat/qat_sym_capabilities.h  | 20 
 drivers/crypto/qat/qat_sym_session.c   | 27 -
 drivers/crypto/qat/qat_sym_session.h   |  1 +
 5 files changed, 85 insertions(+), 1 deletion(-)

diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h 
b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
index 20eb145def..c4901eb869 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
@@ -371,4 +371,32 @@ struct icp_qat_fw_la_resp {
& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }
 
+#define ICP_QAT_FW_LA_USE_WIRELESS_SLICE_TYPE 2
+#define ICP_QAT_FW_LA_USE_UCS_SLICE_TYPE 1
+#define ICP_QAT_FW_LA_USE_LEGACY_SLICE_TYPE 0
+#define QAT_LA_SLICE_TYPE_BITPOS 14
+#define QAT_LA_SLICE_TYPE_MASK 0x3
+#define ICP_QAT_FW_LA_SLICE_TYPE_SET(flags, val)   \
+   QAT_FIELD_SET(flags, val, QAT_LA_SLICE_TYPE_BITPOS, \
+   QAT_LA_SLICE_TYPE_MASK)
+
+struct icp_qat_fw_la_cipher_20_req_params {
+   uint32_t cipher_offset;
+   uint32_t cipher_length;
+   union {
+   uint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4];
+   struct {
+   uint64_t cipher_IV_ptr;
+   uint64_t resrvd1;
+   } s;
+
+   } u;
+   uint32_t   spc_aad_offset;
+   uint32_t   spc_aad_sz;
+   uint64_t   spc_aad_addr;
+   uint64_t   spc_auth_res_addr;
+   uint8_treserved[3];
+   uint8_tspc_auth_res_sz;
+};
+
 #endif
diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h 
b/drivers/common/qat/qat_adf/icp_qat_hw.h
index fdc0f191a2..b1e6a1fa15 100644
--- a/drivers/common/qat/qat_adf/icp_qat_hw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h
@@ -342,6 +342,16 @@ struct icp_qat_hw_cipher_algo_blk {
uint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];
 } __rte_cache_aligned;
 
+struct icp_qat_hw_ucs_cipher_config {
+   uint32_t val;
+   uint32_t reserved[3];
+};
+
+struct icp_qat_hw_cipher_algo_blk20 {
+   struct icp_qat_hw_ucs_cipher_config cipher_config;
+   uint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];
+} __rte_cache_aligned;
+
 /* = */
 /*COMPRESSION SLICE  */
 /* = */
diff --git a/drivers/crypto/qat/qat_sym_capabilities.h 
b/drivers/crypto/qat/qat_sym_capabilities.h
index 21c817bccc..aca528b991 100644
--- a/drivers/crypto/qat/qat_sym_capabilities.h
+++ b/drivers/crypto/qat/qat_sym_capabilities.h
@@ -1064,6 +1064,26 @@
.iv_size = { 0 }\
}, }\
}, }\
+   },  \
+   {   /* AES CTR */   \
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \
+   {.sym = {   \
+   .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,  \
+   {.cipher = {\
+   .algo = RTE_CRYPTO_CIPHER_AES_CTR,  \
+   .block_size = 16,   \
+   .key_size = {   \
+   .min = 16,  \
+   .max = 32,  \
+   .increment = 8  \
+   },  \
+   .iv_size = {\
+   .min = 16,  \
+   .max = 16,  \
+   .increment = 0  \
+   }   \
+   }, }\
+   }, }\
}   \
 
 
diff --git a/drivers/crypto/qat/qat_sym_session.c 
b/drivers/crypto/qat/qat_sym_session.c
index 506ffddd20..2c44b1f1aa 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -246,6 +246,8 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev

[dpdk-dev] [PATCH 05/15] crypto/qat: rename content descriptor functions

Content descriptor functions are incorrectly named,
having them with proper name will improve readability and
facilitate further work.

Signed-off-by: Arek Kusztal 
---
 drivers/crypto/qat/qat_sym_session.c | 39 ++--
 drivers/crypto/qat/qat_sym_session.h | 13 --
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/crypto/qat/qat_sym_session.c 
b/drivers/crypto/qat/qat_sym_session.c
index 2c44b1f1aa..56c85e8435 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -57,6 +57,19 @@ static const uint8_t sha512InitialState[] = {
0x2b, 0x3e, 0x6c, 0x1f, 0x1f, 0x83, 0xd9, 0xab, 0xfb, 0x41, 0xbd,
0x6b, 0x5b, 0xe0, 0xcd, 0x19, 0x13, 0x7e, 0x21, 0x79};
 
+static int
+qat_sym_cd_cipher_set(struct qat_sym_session *cd,
+   const uint8_t *enckey,
+   uint32_t enckeylen);
+
+static int
+qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
+   const uint8_t *authkey,
+   uint32_t authkeylen,
+   uint32_t aad_length,
+   uint32_t digestsize,
+   unsigned int operation);
+
 /** Frees a context previously created
  *  Depends on openssl libcrypto
  */
@@ -420,7 +433,7 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev,
else
session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
 
-   if (qat_sym_session_aead_create_cd_cipher(session,
+   if (qat_sym_cd_cipher_set(session,
cipher_xform->key.data,
cipher_xform->key.length)) {
ret = -EINVAL;
@@ -669,7 +682,7 @@ qat_sym_session_handle_single_pass(struct qat_sym_session 
*session,
}
session->cipher_iv.offset = aead_xform->iv.offset;
session->cipher_iv.length = aead_xform->iv.length;
-   if (qat_sym_session_aead_create_cd_cipher(session,
+   if (qat_sym_cd_cipher_set(session,
aead_xform->key.data, aead_xform->key.length))
return -EINVAL;
session->aad_len = aead_xform->aad_length;
@@ -825,12 +838,12 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
 * then authentication
 */
 
-   if (qat_sym_session_aead_create_cd_cipher(session,
+   if (qat_sym_cd_cipher_set(session,
auth_xform->key.data,
auth_xform->key.length))
return -EINVAL;
 
-   if (qat_sym_session_aead_create_cd_auth(session,
+   if (qat_sym_cd_auth_set(session,
key_data,
key_length,
0,
@@ -845,7 +858,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
 * then cipher
 */
 
-   if (qat_sym_session_aead_create_cd_auth(session,
+   if (qat_sym_cd_auth_set(session,
key_data,
key_length,
0,
@@ -853,7 +866,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
auth_xform->op))
return -EINVAL;
 
-   if (qat_sym_session_aead_create_cd_cipher(session,
+   if (qat_sym_cd_cipher_set(session,
auth_xform->key.data,
auth_xform->key.length))
return -EINVAL;
@@ -861,7 +874,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
/* Restore to authentication only only */
session->qat_cmd = ICP_QAT_FW_LA_CMD_AUTH;
} else {
-   if (qat_sym_session_aead_create_cd_auth(session,
+   if (qat_sym_cd_auth_set(session,
key_data,
key_length,
0,
@@ -948,12 +961,12 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,
crypto_operation = aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM ?
RTE_CRYPTO_AUTH_OP_GENERATE : RTE_CRYPTO_AUTH_OP_VERIFY;
 
-   if (qat_sym_session_aead_create_cd_cipher(session,
+   if (qat_sym_cd_cipher_set(session,
aead_xform->key.data,

[dpdk-dev] [PATCH 06/15] crypto/qat: add legacy gcm and ccm

Add AES-GCM, AES-CCM algorithms in legacy mode.

Signed-off-by: Arek Kusztal 
---
 drivers/crypto/qat/qat_sym_capabilities.h | 60 +++
 drivers/crypto/qat/qat_sym_session.c  | 27 +-
 drivers/crypto/qat/qat_sym_session.h  |  3 +-
 3 files changed, 78 insertions(+), 12 deletions(-)

diff --git a/drivers/crypto/qat/qat_sym_capabilities.h 
b/drivers/crypto/qat/qat_sym_capabilities.h
index aca528b991..fc8e667687 100644
--- a/drivers/crypto/qat/qat_sym_capabilities.h
+++ b/drivers/crypto/qat/qat_sym_capabilities.h
@@ -1084,6 +1084,66 @@
}   \
}, }\
}, }\
+   },  \
+   {   /* AES GCM */   \
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \
+   {.sym = {   \
+   .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,\
+   {.aead = {  \
+   .algo = RTE_CRYPTO_AEAD_AES_GCM,\
+   .block_size = 16,   \
+   .key_size = {   \
+   .min = 16,  \
+   .max = 32,  \
+   .increment = 8  \
+   },  \
+   .digest_size = {\
+   .min = 8,   \
+   .max = 16,  \
+   .increment = 4  \
+   },  \
+   .aad_size = {   \
+   .min = 0,   \
+   .max = 240, \
+   .increment = 1  \
+   },  \
+   .iv_size = {\
+   .min = 0,   \
+   .max = 12,  \
+   .increment = 12 \
+   },  \
+   }, }\
+   }, }\
+   },  \
+   {   /* AES CCM */   \
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \
+   {.sym = {   \
+   .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,\
+   {.aead = {  \
+   .algo = RTE_CRYPTO_AEAD_AES_CCM,\
+   .block_size = 16,   \
+   .key_size = {   \
+   .min = 16,  \
+   .max = 16,  \
+   .increment = 0  \
+   },  \
+   .digest_size = {\
+   .min = 4,   \
+   .max = 16,  \
+   .increment = 2  \
+   },  \
+   .aad_size = {   \
+   .min = 0,   \
+   .max = 224, \
+   .increment = 1  \
+   },  \
+   .iv_size = {\
+   .min = 7,   \
+   .max = 13,  \
+   .increment = 1

[dpdk-dev] [PATCH 07/15] crypto/qat: rework init common header function

Rework init common header function for request
descriptor so it can be called only once.

Signed-off-by: Arek Kusztal 
---
 drivers/crypto/qat/qat_sym.c |  25 +--
 drivers/crypto/qat/qat_sym_session.c | 264 ++-
 drivers/crypto/qat/qat_sym_session.h |  12 ++
 3 files changed, 157 insertions(+), 144 deletions(-)

diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c
index 9415ec7d32..eef4a886c5 100644
--- a/drivers/crypto/qat/qat_sym.c
+++ b/drivers/crypto/qat/qat_sym.c
@@ -289,8 +289,9 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,
auth_param = (void *)((uint8_t *)cipher_param +
ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET);
 
-   if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
-   ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
+   if ((ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
+   ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) &&
+   !ctx->is_gmac) {
/* AES-GCM or AES-CCM */
if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||
@@ -303,7 +304,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,
do_auth = 1;
do_cipher = 1;
}
-   } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
+   } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH || ctx->is_gmac) {
do_auth = 1;
do_cipher = 0;
} else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
@@ -383,15 +384,6 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,
auth_param->u1.aad_adr = 0;
auth_param->u2.aad_sz = 0;
 
-   /*
-* If len(iv)==12B fw computes J0
-*/
-   if (ctx->auth_iv.length == 12) {
-   ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
-   qat_req->comn_hdr.serv_specif_flags,
-   ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
-
-   }
} else {
auth_ofs = op->sym->auth.data.offset;
auth_len = op->sym->auth.data.length;
@@ -416,14 +408,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,
ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
ctx->qat_hash_alg ==
ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
-   /*
-* If len(iv)==12B fw computes J0
-*/
-   if (ctx->cipher_iv.length == 12) {
-   ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
-   qat_req->comn_hdr.serv_specif_flags,
-   ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
-   }
+
set_cipher_iv(ctx->cipher_iv.length,
ctx->cipher_iv.offset,
cipher_param, op, qat_req);
diff --git a/drivers/crypto/qat/qat_sym_session.c 
b/drivers/crypto/qat/qat_sym_session.c
index 5140d61a9c..4b52ffd459 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -69,6 +69,15 @@ qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
uint32_t aad_length,
uint32_t digestsize,
unsigned int operation);
+static void
+qat_sym_session_init_common_hdr(struct qat_sym_session *session);
+
+/* Req/cd init functions */
+
+static void qat_sym_session_finalize(struct qat_sym_session *session)
+{
+   qat_sym_session_init_common_hdr(session);
+}
 
 /** Frees a context previously created
  *  Depends on openssl libcrypto
@@ -558,6 +567,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,
enum qat_device_gen qat_dev_gen = internals->qat_dev->qat_dev_gen;
int ret;
int qat_cmd_id;
+   int handle_mixed = 0;
 
/* Verify the session physical address is known */
rte_iova_t session_paddr = rte_mempool_virt2iova(session);
@@ -573,6 +583,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,
offsetof(struct qat_sym_session, cd);
 
session->min_qat_dev_gen = QAT_GEN1;
+   session->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_NONE;
session->is_ucs = 0;
 
/* Get requested QAT command id */
@@ -612,8 +623,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,
xform, session);
if (ret < 0)
return ret;
-

[dpdk-dev] [PATCH 08/15] crypto/qat: add aes gcm in ucs spc mode

This commit adds AES-GCM algorithm that works
in UCS (Unified crypto slice) SPC(Single-Pass) mode.

Signed-off-by: Arek Kusztal 
---
 drivers/crypto/qat/qat_sym.c | 32 
 drivers/crypto/qat/qat_sym_session.c |  9 
 2 files changed, 27 insertions(+), 14 deletions(-)

diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c
index eef4a886c5..00fc4d6b1a 100644
--- a/drivers/crypto/qat/qat_sym.c
+++ b/drivers/crypto/qat/qat_sym.c
@@ -217,6 +217,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,
int ret = 0;
struct qat_sym_session *ctx = NULL;
struct icp_qat_fw_la_cipher_req_params *cipher_param;
+   struct icp_qat_fw_la_cipher_20_req_params *cipher_param20;
struct icp_qat_fw_la_auth_req_params *auth_param;
register struct icp_qat_fw_la_bulk_req *qat_req;
uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
@@ -286,6 +287,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,
rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
cipher_param = (void *)&qat_req->serv_specif_rqpars;
+   cipher_param20 = (void *)&qat_req->serv_specif_rqpars;
auth_param = (void *)((uint8_t *)cipher_param +
ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET);
 
@@ -563,13 +565,17 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,
cipher_param->cipher_length = 0;
}
 
-   if (do_auth || do_aead) {
-   auth_param->auth_off = (uint32_t)rte_pktmbuf_iova_offset(
+   if (!ctx->is_single_pass) {
+   /* Do not let to owerwrite spc_aad len */
+   if (do_auth || do_aead) {
+   auth_param->auth_off =
+   (uint32_t)rte_pktmbuf_iova_offset(
op->sym->m_src, auth_ofs) - src_buf_start;
-   auth_param->auth_len = auth_len;
-   } else {
-   auth_param->auth_off = 0;
-   auth_param->auth_len = 0;
+   auth_param->auth_len = auth_len;
+   } else {
+   auth_param->auth_off = 0;
+   auth_param->auth_len = 0;
+   }
}
 
qat_req->comn_mid.dst_length =
@@ -675,10 +681,18 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,
}
 
if (ctx->is_single_pass) {
-   /* Handle Single-Pass GCM */
-   cipher_param->spc_aad_addr = op->sym->aead.aad.phys_addr;
-   cipher_param->spc_auth_res_addr =
+   if (ctx->is_ucs) {
+   /* GEN 4 */
+   cipher_param20->spc_aad_addr =
+   op->sym->aead.aad.phys_addr;
+   cipher_param20->spc_auth_res_addr =
op->sym->aead.digest.phys_addr;
+   } else {
+   cipher_param->spc_aad_addr =
+   op->sym->aead.aad.phys_addr;
+   cipher_param->spc_auth_res_addr =
+   op->sym->aead.digest.phys_addr;
+   }
} else if (ctx->is_single_pass_gmac &&
   op->sym->auth.data.length <= QAT_AES_GMAC_SPC_MAX_SIZE) {
/* Handle Single-Pass AES-GMAC */
diff --git a/drivers/crypto/qat/qat_sym_session.c 
b/drivers/crypto/qat/qat_sym_session.c
index 4b52ffd459..7d66ca5172 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -897,16 +897,15 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,
 
if (qat_dev_gen == QAT_GEN4)
session->is_ucs = 1;
-
if (session->cipher_iv.length == 0) {
session->cipher_iv.length = AES_GCM_J0_LEN;
break;
}
session->is_iv12B = 1;
-   if (qat_dev_gen == QAT_GEN3) {
-   qat_sym_session_handle_single_pass(session,
-   aead_xform);
-   }
+   if (qat_dev_gen < QAT_GEN3)
+   break;
+   qat_sym_session_handle_single_pass(session,
+   aead_xform);
break;
case RTE_CRYPTO_AEAD_AES_CCM:
if (qat_sym_validate_aes_key(aead_xform->key.length,
-- 
2.25.1

[dpdk-dev] [PATCH 09/15] crypto/qat: add chacha-poly in ucs spc mode

This commit adds Chacha20-Poly1305 aglorithm that works
in UCS (Unified crypto slice) SPC(Single-Pass) mode.

Signed-off-by: Arek Kusztal 
---
 drivers/crypto/qat/qat_sym_capabilities.h | 32 ++-
 drivers/crypto/qat/qat_sym_session.c  |  2 ++
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/qat/qat_sym_capabilities.h 
b/drivers/crypto/qat/qat_sym_capabilities.h
index fc8e667687..5c6e723466 100644
--- a/drivers/crypto/qat/qat_sym_capabilities.h
+++ b/drivers/crypto/qat/qat_sym_capabilities.h
@@ -1144,7 +1144,37 @@
},  \
}, }\
}, }\
-   }   \
+   },  \
+   {   /* Chacha20-Poly1305 */ \
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \
+   {.sym = {   \
+   .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,\
+   {.aead = {  \
+   .algo = RTE_CRYPTO_AEAD_CHACHA20_POLY1305, \
+   .block_size = 64,   \
+   .key_size = {   \
+   .min = 32,  \
+   .max = 32,  \
+   .increment = 0  \
+   },  \
+   .digest_size = {\
+   .min = 16,  \
+   .max = 16,  \
+   .increment = 0  \
+   },  \
+   .aad_size = {   \
+   .min = 0,   \
+   .max = 240, \
+   .increment = 1  \
+   },  \
+   .iv_size = {\
+   .min = 12,  \
+   .max = 12,  \
+   .increment = 0  \
+   },  \
+   }, }\
+   }, }\
+   }
 
 
 
diff --git a/drivers/crypto/qat/qat_sym_session.c 
b/drivers/crypto/qat/qat_sym_session.c
index 7d66ca5172..221b950aeb 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -921,6 +921,8 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,
case RTE_CRYPTO_AEAD_CHACHA20_POLY1305:
if (aead_xform->key.length != ICP_QAT_HW_CHACHAPOLY_KEY_SZ)
return -EINVAL;
+   if (qat_dev_gen == QAT_GEN4)
+   session->is_ucs = 1;
session->qat_cipher_alg =
ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305;
qat_sym_session_handle_single_pass(session,
-- 
2.25.1

[dpdk-dev] [PATCH 10/15] crypto/qat: add gmac in legacy mode on fourth generation

Add AES-GMAC algorithm in legacy mode to generation 4 devices.

Signed-off-by: Arek Kusztal 
---
 drivers/crypto/qat/qat_sym_capabilities.h | 27 ++-
 drivers/crypto/qat/qat_sym_session.c  |  9 +++-
 drivers/crypto/qat/qat_sym_session.h  |  2 ++
 3 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/qat/qat_sym_capabilities.h 
b/drivers/crypto/qat/qat_sym_capabilities.h
index 5c6e723466..cfb176ca94 100644
--- a/drivers/crypto/qat/qat_sym_capabilities.h
+++ b/drivers/crypto/qat/qat_sym_capabilities.h
@@ -1174,7 +1174,32 @@
},  \
}, }\
}, }\
-   }
+   },  \
+   {   /* AES GMAC (AUTH) */   \
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \
+   {.sym = {   \
+   .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\
+   {.auth = {  \
+   .algo = RTE_CRYPTO_AUTH_AES_GMAC,   \
+   .block_size = 16,   \
+   .key_size = {   \
+   .min = 16,  \
+   .max = 32,  \
+   .increment = 8  \
+   },  \
+   .digest_size = {\
+   .min = 8,   \
+   .max = 16,  \
+   .increment = 4  \
+   },  \
+   .iv_size = {\
+   .min = 0,   \
+   .max = 12,  \
+   .increment = 12 \
+   }   \
+   }, }\
+   }, }\
+   }   \
 
 
 
diff --git a/drivers/crypto/qat/qat_sym_session.c 
b/drivers/crypto/qat/qat_sym_session.c
index 221b950aeb..c04b04da00 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -709,6 +709,8 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
struct qat_sym_dev_private *internals = dev->data->dev_private;
const uint8_t *key_data = auth_xform->key.data;
uint8_t key_length = auth_xform->key.length;
+   enum qat_device_gen qat_dev_gen =
+   internals->qat_dev->qat_dev_gen;
 
session->aes_cmac = 0;
session->auth_key_length = auth_xform->key.length;
@@ -716,6 +718,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
session->auth_iv.length = auth_xform->iv.length;
session->auth_mode = ICP_QAT_HW_AUTH_MODE1;
session->is_auth = 1;
+   session->digest_length = auth_xform->digest_length;
 
switch (auth_xform->algo) {
case RTE_CRYPTO_AUTH_SHA1:
@@ -772,6 +775,10 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
session->auth_iv.length = AES_GCM_J0_LEN;
else
session->is_iv12B = 1;
+   if (qat_dev_gen == QAT_GEN4) {
+   session->is_cnt_zero = 1;
+   session->is_ucs = 1;
+   }
break;
case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
@@ -857,7 +864,6 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
return -EINVAL;
}
 
-   session->digest_length = auth_xform->digest_length;
return 0;
 }
 
@@ -1810,6 +1816,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC
|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC
|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL
+   || cdesc->is_cnt_zero
)
hash->auth_counter.counter = 0;
else {
diff --git a/drivers/crypto/qat/qat_sym_session.h 
b/drivers/crypto/qat/qat_sym_session.h
in

[dpdk-dev] [PATCH 11/15] common/qat: add pf2vf communication in qat

Add communication between physical device and virtual function
in Intel QucikAssist Technology PMD.

Signed-off-by: Arek Kusztal 
---
 drivers/common/qat/meson.build |   1 +
 drivers/common/qat/qat_adf/adf_pf2vf_msg.h | 154 +
 drivers/common/qat/qat_device.c|  22 ++-
 drivers/common/qat/qat_device.h|  12 ++
 drivers/common/qat/qat_pf2vf.c |  80 +++
 drivers/common/qat/qat_pf2vf.h |  19 +++
 6 files changed, 287 insertions(+), 1 deletion(-)
 create mode 100644 drivers/common/qat/qat_adf/adf_pf2vf_msg.h
 create mode 100644 drivers/common/qat/qat_pf2vf.c
 create mode 100644 drivers/common/qat/qat_pf2vf.h

diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build
index 479a46f9f0..11ed37c910 100644
--- a/drivers/common/qat/meson.build
+++ b/drivers/common/qat/meson.build
@@ -49,6 +49,7 @@ sources += files(
 'qat_qp.c',
 'qat_device.c',
 'qat_logs.c',
+'qat_pf2vf.c'
 )
 includes += include_directories(
 'qat_adf',
diff --git a/drivers/common/qat/qat_adf/adf_pf2vf_msg.h 
b/drivers/common/qat/qat_adf/adf_pf2vf_msg.h
new file mode 100644
index 00..4029b1c14a
--- /dev/null
+++ b/drivers/common/qat/qat_adf/adf_pf2vf_msg.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2021 Intel Corporation
+ */
+#ifndef ADF_PF2VF_MSG_H_
+#define ADF_PF2VF_MSG_H_
+
+/* VF/PF compatibility version. */
+/* ADF_PFVF_COMPATIBILITY_EXT_CAP: Support for extended capabilities */
+#define ADF_PFVF_COMPATIBILITY_CAPABILITIES2
+/* ADF_PFVF_COMPATIBILITY_FAST_ACK: In-use pattern cleared by receiver */
+#define ADF_PFVF_COMPATIBILITY_FAST_ACK3
+#define ADF_PFVF_COMPATIBILITY_RING_TO_SVC_MAP 4
+#define ADF_PFVF_COMPATIBILITY_VERSION 4   /* PF<->VF compat */
+
+#define ADF_PFVF_INT   1
+#define ADF_PFVF_MSGORIGIN_SYSTEM  2
+#define ADF_PFVF_1X_MSGTYPE_SHIFT  2
+#define ADF_PFVF_1X_MSGTYPE_MASK   0xF
+#define ADF_PFVF_1X_MSGDATA_SHIFT  6
+#define ADF_PFVF_1X_MSGDATA_MASK   0x3FF
+#define ADF_PFVF_2X_MSGTYPE_SHIFT  2
+#define ADF_PFVF_2X_MSGTYPE_MASK   0x3F
+#define ADF_PFVF_2X_MSGDATA_SHIFT  8
+#define ADF_PFVF_2X_MSGDATA_MASK   0xFF
+
+#define ADF_PFVF_IN_USE0x6AC2
+#define ADF_PFVF_IN_USE_MASK   0xFFFE
+#define ADF_PFVF_VF_MSG_SHIFT  16
+
+/* PF->VF messages */
+#define ADF_PF2VF_MSGTYPE_RESTARTING   0x01
+#define ADF_PF2VF_MSGTYPE_VERSION_RESP 0x02
+#define ADF_PF2VF_MSGTYPE_BLOCK_RESP   0x03
+#define ADF_PF2VF_MSGTYPE_FATAL_ERROR  0x04
+/* Do not use messages which start from 0x10 to 1.x as 1.x only use
+ * 4 bits as message types. Hence they are only applicable to 2.0
+ */
+#define ADF_PF2VF_MSGTYPE_RP_RESET_RESP0x10
+
+/* PF->VF Version Response - ADF_PF2VF_MSGTYPE_VERSION_RESP */
+#define ADF_PF2VF_VERSION_RESP_VERS_MASK   0xFF
+#define ADF_PF2VF_VERSION_RESP_VERS_SHIFT  0
+#define ADF_PF2VF_VERSION_RESP_RESULT_MASK 0x03
+#define ADF_PF2VF_VERSION_RESP_RESULT_SHIFT8
+#define ADF_PF2VF_MINORVERSION_SHIFT   0
+#define ADF_PF2VF_MAJORVERSION_SHIFT   4
+#define ADF_PF2VF_VF_COMPATIBLE1
+#define ADF_PF2VF_VF_INCOMPATIBLE  2
+#define ADF_PF2VF_VF_COMPAT_UNKNOWN3
+
+/* PF->VF Block Response Type - ADF_PF2VF_MSGTYPE_BLOCK_RESP */
+#define ADF_PF2VF_BLOCK_RESP_TYPE_DATA 0x0
+#define ADF_PF2VF_BLOCK_RESP_TYPE_CRC  0x1
+#define ADF_PF2VF_BLOCK_RESP_TYPE_ERROR0x2
+#define ADF_PF2VF_BLOCK_RESP_TYPE_MASK 0x03
+#define ADF_PF2VF_BLOCK_RESP_TYPE_SHIFT0
+#define ADF_PF2VF_BLOCK_RESP_DATA_MASK 0xFF
+#define ADF_PF2VF_BLOCK_RESP_DATA_SHIFT2
+
+/*
+ * PF->VF Block Error Code - Returned in data field when the
+ * response type indicates an error
+ */
+#define ADF_PF2VF_INVALID_BLOCK_TYPE   0x0
+#define ADF_PF2VF_INVALID_BYTE_NUM_REQ 0x1
+#define ADF_PF2VF_PAYLOAD_TRUNCATED0x2
+#define ADF_PF2VF_UNSPECIFIED_ERROR0x3
+
+/* VF->PF messages */
+#define ADF_VF2PF_MSGTYPE_INIT 0x3
+#define ADF_VF2PF_MSGTYPE_SHUTDOWN 0x4
+#define ADF_VF2PF_MSGTYPE_VERSION_REQ  0x5
+#define ADF_VF2PF_MSGTYPE_COMPAT_VER_REQ   0x6
+#define ADF_VF2PF_MSGTYPE_GET_LARGE_BLOCK_REQ  0x7
+#define ADF_VF2PF_MSGTYPE_GET_MEDIUM_BLOCK_REQ 0x8
+#define ADF_VF2PF_MSGTYPE_GET_SMALL_BLOCK_REQ  0x9
+/* Do not use messages which start from 0x10 to 1.x as 1.x only use
+ * 4 bits as message types. Hence they are only applicable to 2.0
+ */
+#define ADF_VF2PF_MSGTYPE_RP_RESET 0x10
+
+/* VF->PF Block Request Type - ADF_VF2PF_MSGTYPE_GET_xxx_BLOCK_REQ  */
+#define ADF_VF2PF_MIN_SMALL_MESS

[dpdk-dev] [PATCH 12/15] common/qat: reset ring pairs before setting pmd

This commit resets ring pairs of particular vf before
setting PMD on fourth generation devices.

Signed-off-by: Arek Kusztal 
---
 drivers/common/qat/qat_device.c | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index 5ee441171e..d6bf0f52db 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -11,6 +11,7 @@
 #include "qat_sym_pmd.h"
 #include "qat_comp_pmd.h"
 #include "adf_pf2vf_msg.h"
+#include "qat_pf2vf.h"
 
 /* pv2vf data Gen 4*/
 struct qat_pf2vf_dev qat_pf2vf_gen4 = {
@@ -125,6 +126,27 @@ qat_get_qat_dev_from_pci_dev(struct rte_pci_device 
*pci_dev)
return qat_pci_get_named_dev(name);
 }
 
+static int qat_gen4_reset_ring_pair(struct qat_pci_device *qat_pci_dev)
+{
+   int ret = 0, i;
+   uint8_t data[4];
+   struct qat_pf2vf_msg pf2vf_msg;
+
+   pf2vf_msg.msg_type = ADF_VF2PF_MSGTYPE_RP_RESET;
+   pf2vf_msg.block_hdr = -1;
+   for (i = 0; i < QAT_GEN4_BUNDLE_NUM; i++) {
+   pf2vf_msg.msg_data = i;
+   ret = qat_pf2vf_exch_msg(qat_pci_dev, pf2vf_msg, 1, data);
+   if (ret) {
+   QAT_LOG(ERR, "QAT error when reset bundle no %d",
+   i);
+   return ret;
+   }
+   }
+
+   return 0;
+}
+
 static void qat_dev_parse_cmd(const char *str, struct qat_dev_cmd_param
*qat_dev_cmd_param)
 {
@@ -371,6 +393,11 @@ static int qat_pci_probe(struct rte_pci_driver *pci_drv 
__rte_unused,
if (qat_pci_dev == NULL)
return -ENODEV;
 
+   if (qat_pci_dev->qat_dev_gen == QAT_GEN4) {
+   if (qat_gen4_reset_ring_pair(qat_pci_dev))
+   return -ENODEV;
+   }
+
sym_ret = qat_sym_dev_create(qat_pci_dev, qat_dev_cmd_param);
if (sym_ret == 0) {
num_pmds_created++;
-- 
2.25.1

[dpdk-dev] [PATCH 13/15] crypto/qat: update raw dp api

From: Fan Zhang 

This commit updates the QAT raw data-path API to support the
changes made to device and sessions. The QAT RAW data-path API
now works on Generation 1-3 devices.

Signed-off-by: Fan Zhang 
---
 drivers/crypto/qat/qat_sym_hw_dp.c | 419 +++--
 1 file changed, 216 insertions(+), 203 deletions(-)

diff --git a/drivers/crypto/qat/qat_sym_hw_dp.c 
b/drivers/crypto/qat/qat_sym_hw_dp.c
index 2f64de44a1..4305579b54 100644
--- a/drivers/crypto/qat/qat_sym_hw_dp.c
+++ b/drivers/crypto/qat/qat_sym_hw_dp.c
@@ -101,204 +101,6 @@ qat_sym_dp_fill_vec_status(int32_t *sta, int status, 
uint32_t n)
 #define QAT_SYM_DP_GET_MAX_ENQ(q, c, n) \
RTE_MIN((q->max_inflights - q->enqueued + q->dequeued - c), n)
 
-static __rte_always_inline void
-enqueue_one_aead_job(struct qat_sym_session *ctx,
-   struct icp_qat_fw_la_bulk_req *req,
-   struct rte_crypto_va_iova_ptr *iv,
-   struct rte_crypto_va_iova_ptr *digest,
-   struct rte_crypto_va_iova_ptr *aad,
-   union rte_crypto_sym_ofs ofs, uint32_t data_len)
-{
-   struct icp_qat_fw_la_cipher_req_params *cipher_param =
-   (void *)&req->serv_specif_rqpars;
-   struct icp_qat_fw_la_auth_req_params *auth_param =
-   (void *)((uint8_t *)&req->serv_specif_rqpars +
-   ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET);
-   uint8_t *aad_data;
-   uint8_t aad_ccm_real_len;
-   uint8_t aad_len_field_sz;
-   uint32_t msg_len_be;
-   rte_iova_t aad_iova = 0;
-   uint8_t q;
-
-   switch (ctx->qat_hash_alg) {
-   case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
-   case ICP_QAT_HW_AUTH_ALGO_GALOIS_64:
-   ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
-   req->comn_hdr.serv_specif_flags,
-   ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
-   rte_memcpy(cipher_param->u.cipher_IV_array, iv->va,
-   ctx->cipher_iv.length);
-   aad_iova = aad->iova;
-   break;
-   case ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC:
-   aad_data = aad->va;
-   aad_iova = aad->iova;
-   aad_ccm_real_len = 0;
-   aad_len_field_sz = 0;
-   msg_len_be = rte_bswap32((uint32_t)data_len -
-   ofs.ofs.cipher.head);
-
-   if (ctx->aad_len > ICP_QAT_HW_CCM_AAD_DATA_OFFSET) {
-   aad_len_field_sz = ICP_QAT_HW_CCM_AAD_LEN_INFO;
-   aad_ccm_real_len = ctx->aad_len -
-   ICP_QAT_HW_CCM_AAD_B0_LEN -
-   ICP_QAT_HW_CCM_AAD_LEN_INFO;
-   } else {
-   aad_data = iv->va;
-   aad_iova = iv->iova;
-   }
-
-   q = ICP_QAT_HW_CCM_NQ_CONST - ctx->cipher_iv.length;
-   aad_data[0] = ICP_QAT_HW_CCM_BUILD_B0_FLAGS(
-   aad_len_field_sz, ctx->digest_length, q);
-   if (q > ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE) {
-   memcpy(aad_data + ctx->cipher_iv.length +
-   ICP_QAT_HW_CCM_NONCE_OFFSET + (q -
-   ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE),
-   (uint8_t *)&msg_len_be,
-   ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE);
-   } else {
-   memcpy(aad_data + ctx->cipher_iv.length +
-   ICP_QAT_HW_CCM_NONCE_OFFSET,
-   (uint8_t *)&msg_len_be +
-   (ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE
-   - q), q);
-   }
-
-   if (aad_len_field_sz > 0) {
-   *(uint16_t *)&aad_data[ICP_QAT_HW_CCM_AAD_B0_LEN] =
-   rte_bswap16(aad_ccm_real_len);
-
-   if ((aad_ccm_real_len + aad_len_field_sz)
-   % ICP_QAT_HW_CCM_AAD_B0_LEN) {
-   uint8_t pad_len = 0;
-   uint8_t pad_idx = 0;
-
-   pad_len = ICP_QAT_HW_CCM_AAD_B0_LEN -
-   ((aad_ccm_real_len +
-   aad_len_field_sz) %
-   ICP_QAT_HW_CCM_AAD_B0_LEN);
-   pad_idx = ICP_QAT_HW_CCM_AAD_B0_LEN +
-   aad_ccm_real_len +
-   aad_len_field_sz;
-   memset(&aad_data[pad_idx], 0, pad_len);
-   }
-   }
-
-   rte_memcpy(((uint8_t *)cipher_param->u.cipher_IV_array)
-   + ICP_QAT_HW_CCM_NONCE_OFFSET,
-   (uint8_t *)iv->va +
-   ICP_QAT_HW_CCM_NONCE_OFFSET, ctx->cipher_iv.length);
-   *(uint8_t *)&cip

[dpdk-dev] [PATCH 14/15] crypto/qat: enable RAW API on QAT GEN1-3 only

From: Adam Dybkowski 

This patch enables RAW API in feature flags on QAT generations
1 to 3 only. Disables it for later generations.

Signed-off-by: Adam Dybkowski 
---
 drivers/crypto/qat/qat_sym_pmd.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c
index 0097ee210f..1c7b142511 100644
--- a/drivers/crypto/qat/qat_sym_pmd.c
+++ b/drivers/crypto/qat/qat_sym_pmd.c
@@ -409,8 +409,10 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev,
RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
RTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT |
RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT |
-   RTE_CRYPTODEV_FF_DIGEST_ENCRYPTED |
-   RTE_CRYPTODEV_FF_SYM_RAW_DP;
+   RTE_CRYPTODEV_FF_DIGEST_ENCRYPTED;
+
+   if (qat_pci_dev->qat_dev_gen < QAT_GEN4)
+   cryptodev->feature_flags |= RTE_CRYPTODEV_FF_SYM_RAW_DP;
 
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return 0;
-- 
2.25.1

[dpdk-dev] [PATCH 15/15] test/crypto: check if RAW API is supported

From: Adam Dybkowski 

This patch adds checking if RAW API is supported at the start
of the test command "cryptodev_qat_raw_api_autotest".

Signed-off-by: Adam Dybkowski 
---
 app/test/test_cryptodev.c | 34 +-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 39db52b17a..64b6cc0db7 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -14769,7 +14769,39 @@ test_cryptodev_bcmfs(void)
 static int
 test_cryptodev_qat_raw_api(void /*argv __rte_unused, int argc __rte_unused*/)
 {
-   int ret;
+   static const char *pmd_name = RTE_STR(CRYPTODEV_NAME_QAT_SYM_PMD);
+   struct rte_cryptodev_info dev_info;
+   uint8_t i, nb_devs, found = 0;
+   int driver_id, ret;
+
+   driver_id = rte_cryptodev_driver_id_get(pmd_name);
+   if (driver_id == -1) {
+   RTE_LOG(WARNING, USER1, "%s PMD must be loaded.\n", pmd_name);
+   return TEST_SKIPPED;
+   }
+
+   nb_devs = rte_cryptodev_count();
+   if (nb_devs < 1) {
+   RTE_LOG(WARNING, USER1, "No crypto devices found?\n");
+   return TEST_SKIPPED;
+   }
+
+   for (i = 0; i < nb_devs; i++) {
+   rte_cryptodev_info_get(i, &dev_info);
+   if (dev_info.driver_id == driver_id) {
+   if (!(dev_info.feature_flags &
+   RTE_CRYPTODEV_FF_SYM_RAW_DP)) {
+   RTE_LOG(INFO, USER1, "RAW API not supported\n");
+   return TEST_SKIPPED;
+   }
+   found = 1;
+   break;
+   }
+   }
+   if (!found) {
+   RTE_LOG(INFO, USER1, "RAW API not supported\n");
+   return TEST_SKIPPED;
+   }
 
global_api_test_type = CRYPTODEV_RAW_API_TEST;
ret = run_cryptodev_testsuite(RTE_STR(CRYPTODEV_NAME_QAT_SYM_PMD));
-- 
2.25.1

Re: [dpdk-dev] [PATCH] net/mlx5: fix RSS expansion pattern

2021-05-31 Thread Raslan Darawsheh

Hi,

> -Original Message-
> From: Gregory Etelson 
> Sent: Thursday, May 27, 2021 6:20 PM
> To: dev@dpdk.org
> Cc: Gregory Etelson ; Matan Azrad
> ; Ori Kam ; Raslan Darawsheh
> ; sta...@dpdk.org; Slava Ovsiienko
> ; Shahaf Shuler ; Ferruh
> Yigit ; Dekel Peled 
> Subject: [PATCH] net/mlx5: fix RSS expansion pattern
> 
> Flow rule pattern may be implicitly expanded by the PMD if the rule
> has RSS flow action. The expansion adds network headers to the
> original pattern. The new pattern lists all network levels that
> participate in the rule RSS action.
> 
> The patch fixes expanded pattern for cases when original pattern
> included meta items like MARK, TAG, META.
> 
> Fixes: c7870bfe09dc ("ethdev: move RSS expansion code to mlx5 driver")
> 
> Cc: sta...@dpdk.org
> 
> Signed-off-by: Gregory Etelson 
> Acked-by: Viacheslav Ovsiienko 

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

Re: [dpdk-dev] [PATCH v3] guides: add a guide for developing unit tests

2021-05-31 Thread Ferruh Yigit

On 3/9/2021 3:57 PM, Aaron Conole wrote:
> The DPDK testing infrastructure includes a comprehensive set of
> libraries, utilities, and CI integrations for developers to test
> their code changes.  This isn't well documented, however.
> 
> Document the basics for adding a test suite to the infrastructure
> and enabling that test suite for continuous integration platforms
> so that newer developers can understand how to develop test suites
> and test cases.

+1 to adding this long missing documentation, thanks.

> 
> Reviewed-by: David Marchand 
> Signed-off-by: Aaron Conole 
> ---
> v0->v1: Added information for TEST_SKIPPED and details about generating
> code coverage to help with ideas for writing unit test cases.
> v1->v2: Corrected some spelling, rephrased a bit after suggestions by
> Ray.
> v2->v3: Rewrite the meson build block, updated the copyright section,
> and change the title to be a bit nicer
> 
>  doc/guides/contributing/index.rst   |   1 +
>  doc/guides/contributing/testing.rst | 243 
>  2 files changed, 244 insertions(+)
>  create mode 100644 doc/guides/contributing/testing.rst
> 
> diff --git a/doc/guides/contributing/index.rst 
> b/doc/guides/contributing/index.rst
> index 2fefd91931..41909d949b 100644
> --- a/doc/guides/contributing/index.rst
> +++ b/doc/guides/contributing/index.rst
> @@ -14,6 +14,7 @@ Contributor's Guidelines
>  abi_versioning
>  documentation
>  patches
> +testing
>  vulnerability
>  stable
>  cheatsheet
> diff --git a/doc/guides/contributing/testing.rst 
> b/doc/guides/contributing/testing.rst
> new file mode 100644
> index 00..0757d71ad0
> --- /dev/null
> +++ b/doc/guides/contributing/testing.rst
> @@ -0,0 +1,243 @@
> +..  SPDX-License-Identifier: BSD-3-Clause
> +Copyright 2021 The DPDK contributors
> +
> +DPDK Testing Guidelines
> +===
> +
> +This document outlines the guidelines for running and adding new
> +tests to the in-tree DPDK test suites.
> +

I think both the section name (DPDK Testing Guidelines) and the file name
(testing.rst) is too broad comparing to what is described here.

What about using "DPDK Unit Test Guidelines", and 'unit_test.rst'?

> +The DPDK test suite model is loosely based on the xunit model, where
> +tests are grouped into test suites, and suites are run by runners.
> +For a basic overview, see the basic Wikipedia article on xunit:
> +`xUnit - Wikipedia `_.
> +
> +
> +Running a test
> +--
> +
> +DPDK tests are run via the main test runner, the `dpdk-test` app.
> +The `dpdk-test` app is a command-line interface that facilitates
> +running various tests or test suites.
> +
> +There are two modes of operation.  The first mode is as an interactive
> +command shell that allows launching specific test suites.  This is
> +the default operating mode of `dpdk-test` and can be done by::
> +
> +  $ ./build/app/test/dpdk-test --dpdk-options-here
> +  EAL: Detected 4 lcore(s)
> +  EAL: Detected 1 NUMA nodes
> +  EAL: Static memory layout is selected, amount of reserved memory can be 
> adjusted with -m or --socket-mem
> +  EAL: Multi-process socket /run/user/26934/dpdk/rte/mp_socket
> +  EAL: Selected IOVA mode 'VA'
> +  EAL: Probing VFIO support...
> +  EAL: PCI device :00:1f.6 on NUMA socket -1
> +  EAL:   Invalid NUMA socket, default to 0
> +  EAL:   probe driver: 8086:15d7 net_e1000_em
> +  APP: HPET is not enabled, using TSC as default timer
> +  RTE>>
> +
> +At the prompt, simply type the name of the test suite you wish to run
> +and it will execute.
> +
> +The second form is useful for a scripting environment, and is used by
> +the DPDK meson build system.  This mode is invoked by assigning a
> +specific test suite name to the environment variable `DPDK_TEST`
> +before invoking the `dpdk-test` command, such as::
> +
> +  $ DPDK_TEST=version_autotest ./build/app/test/dpdk-test --dpdk-options-here
> +  EAL: Detected 4 lcore(s)
> +  EAL: Detected 1 NUMA nodes
> +  EAL: Static memory layout is selected, amount of reserved memory can be 
> adjusted with -m or --socket-mem
> +  EAL: Multi-process socket /run/user/26934/dpdk/rte/mp_socket
> +  EAL: Selected IOVA mode 'VA'
> +  EAL: Probing VFIO support...
> +  EAL: PCI device :00:1f.6 on NUMA socket -1
> +  EAL:   Invalid NUMA socket, default to 0
> +  EAL:   probe driver: 8086:15d7 net_e1000_em
> +  APP: HPET is not enabled, using TSC as default timer
> +  RTE>>version_autotest
> +  Version string: 'DPDK 20.02.0-rc0'
> +  Test OK
> +  RTE>>$
> +

According code, it is also possible to run the unit test by providing its name
as argument to 'dpdk-test', like bellow. And benefit of this is, it is possible
to provide multiple tests at once and run them all, which can't be done via
'DPDK_TEST" env var. Should we document this too?

./build/app/test/dpdk-test version_autotest
EAL: Detected 96 lcore(s)
EAL: Detected 2 NUMA nodes
EAL: Detecte

[dpdk-dev] [PATCH 00/28] add support for baseband phy

This series adds initial support for baseband PHY available on SOCs
belonging to Fusion family. BPHY is a hardware block comprising
accelerators and DSPs specifically tailored for 5G/LTE usecases.

This series introduces two rawdev PMDs along with low level common code.

CGX/RPM PMD allows one to configure Ethernet I/O interfaces attached to
BPHY via standard enqueue/dequeue operations.

BPHY PMD provides an out-of-band access to PCI device BARs and a set of
experimental APIs allowing one to setup custom IRQs handlers. This
functionality is backed by kernel module using ioctl() mechanism.

Tomasz Duszynski (28):
  common/cnxk: add bphy cgx/rpm initialization and cleanup
  common/cnxk: add support for communication with atf
  common/cnxk: add support for getting link information
  common/cnxk: add support for changing internal loopback
  common/cnxk: add support for changing ptp mode
  common/cnxk: add support for setting link mode
  common/cnxk: add support for changing link state
  common/cnxk: add support for lmac start/stop
  raw/cnxk_bphy: add bphy cgx/rpm skeleton driver
  raw/cnxk_bphy: add support for reading queue configuration
  raw/cnxk_bphy: add support for reading queue count
  raw/cnxk_bphy: add support for enqueue operation
  raw/cnxk_bphy: add support for dequeue operation
  raw/cnxk_bphy: add support for performing selftest
  common/cnxk: add support for device init and fini
  common/cnxk: add support for baseband phy irq setup
  common/cnxk: add support for checking irq availability
  common/cnxk: add support for retrieving irq stack
  common/cnxk: add support for removing irq stack
  common/cnxk: add support for setting bphy irq handler
  common/cnxk: add support for clearing bphy irq handler
  common/cnxk: add support for registering bphy irq
  raw/cnxk_bphy: add baseband phy skeleton driver
  raw/cnxk_bphy: add support for interrupt init and cleanup
  raw/cnxk_bphy: add support for reading number of irqs
  raw/cnxk_bphy: add support for retrieving device memory
  raw/cnxk_bphy: add support for registering irq handlers
  raw/cnxk_bphy: add support for selftest

 MAINTAINERS|   5 +
 doc/guides/rawdevs/cnxk_bphy.rst   |  62 +++
 doc/guides/rawdevs/index.rst   |   1 +
 drivers/common/cnxk/meson.build|   3 +
 drivers/common/cnxk/roc_api.h  |   7 +
 drivers/common/cnxk/roc_bphy.c |  40 ++
 drivers/common/cnxk/roc_bphy.h |  17 +
 drivers/common/cnxk/roc_bphy_cgx.c | 396 +++
 drivers/common/cnxk/roc_bphy_cgx.h | 120 ++
 drivers/common/cnxk/roc_bphy_cgx_priv.h| 131 +++
 drivers/common/cnxk/roc_bphy_irq.c | 422 +
 drivers/common/cnxk/roc_bphy_irq.h |  49 +++
 drivers/common/cnxk/roc_idev.c |   1 +
 drivers/common/cnxk/roc_idev_priv.h|   2 +
 drivers/common/cnxk/roc_io.h   |   9 +
 drivers/common/cnxk/roc_io_generic.h   |   5 +
 drivers/common/cnxk/roc_priv.h |   3 +
 drivers/common/cnxk/version.map|  22 ++
 drivers/raw/cnxk_bphy/cnxk_bphy.c  | 250 
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c  | 321 
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h  |  10 +
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c | 206 ++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c  | 100 +
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h  |  40 ++
 drivers/raw/cnxk_bphy/meson.build  |  12 +
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h   | 121 ++
 drivers/raw/cnxk_bphy/version.map  |  22 ++
 drivers/raw/meson.build|   1 +
 usertools/dpdk-devbind.py  |   6 +-
 29 files changed, 2383 insertions(+), 1 deletion(-)
 create mode 100644 doc/guides/rawdevs/cnxk_bphy.rst
 create mode 100644 drivers/common/cnxk/roc_bphy.c
 create mode 100644 drivers/common/cnxk/roc_bphy.h
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx.c
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx.h
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx_priv.h
 create mode 100644 drivers/common/cnxk/roc_bphy_irq.c
 create mode 100644 drivers/common/cnxk/roc_bphy_irq.h
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
 create mode 100644 drivers/raw/cnxk_bphy/meson.build
 create mode 100644 drivers/raw/cnxk_bphy/rte_pmd_bphy.h
 create mode 100644 drivers/raw/cnxk_bphy/version.map

--
2.25.1

[dpdk-dev] [PATCH 01/28] common/cnxk: add bphy cgx/rpm initialization and cleanup

Add support for low level initialization and cleanup of baseband
phy cgx/rpm blocks.

Initialization and cleanup are related hence are in the same patch.

Signed-off-by: Tomasz Duszynski 
Signed-off-by: Jakub Palider 
---
 drivers/common/cnxk/meson.build|  1 +
 drivers/common/cnxk/roc_api.h  |  3 ++
 drivers/common/cnxk/roc_bphy_cgx.c | 62 ++
 drivers/common/cnxk/roc_bphy_cgx.h | 20 ++
 drivers/common/cnxk/version.map|  2 +
 5 files changed, 88 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx.c
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx.h

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 178bce7ab..59975fd34 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -11,6 +11,7 @@ endif
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 deps = ['eal', 'pci', 'bus_pci', 'mbuf']
 sources = files(
+'roc_bphy_cgx.c',
 'roc_dev.c',
 'roc_idev.c',
 'roc_irq.c',
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 67f5d13f0..256d8c68d 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -100,4 +100,7 @@
 /* Idev */
 #include "roc_idev.h"
 
+/* Baseband phy cgx */
+#include "roc_bphy_cgx.h"
+
 #endif /* _ROC_API_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx.c 
b/drivers/common/cnxk/roc_bphy_cgx.c
new file mode 100644
index 0..029d4102e
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+
+/*
+ * CN10K stores number of lmacs in 4 bit filed
+ * in contraty to CN9K which uses only 3 bits.
+ *
+ * In theory masks should differ yet on CN9K
+ * bits beyond specified range contain zeros.
+ *
+ * Hence common longer mask may be used.
+ */
+#define CGX_CMRX_RX_LMACS  0x128
+#define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)
+
+static uint64_t
+roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
+{
+   int shift = roc_model_is_cn10k() ? 20 : 18;
+   uint64_t base = (uint64_t)roc_cgx->bar0_va;
+
+   return plt_read64(base + (lmac << shift) + offset);
+}
+
+static unsigned int
+roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx)
+{
+   uint64_t cgx_id = roc_model_is_cn10k() ? GENMASK_ULL(26, 24) :
+GENMASK_ULL(25, 24);
+
+   return FIELD_GET(cgx_id, roc_cgx->bar0_pa);
+}
+
+int
+roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx)
+{
+   uint64_t val;
+
+   if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa)
+   return -EINVAL;
+
+   val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS);
+   val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val);
+   if (roc_model_is_cn9k())
+   val = GENMASK_ULL(val - 1, 0);
+   roc_cgx->lmac_bmap = val;
+   roc_cgx->id = roc_bphy_cgx_dev_id(roc_cgx);
+
+   return 0;
+}
+
+int
+roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
+{
+   if (!roc_cgx)
+   return -EINVAL;
+
+   return 0;
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h 
b/drivers/common/cnxk/roc_bphy_cgx.h
new file mode 100644
index 0..aac2c262c
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_BPHY_CGX_H_
+#define _ROC_BPHY_CGX_H_
+
+#include "roc_api.h"
+
+struct roc_bphy_cgx {
+   uint64_t bar0_pa;
+   void *bar0_va;
+   uint64_t lmac_bmap;
+   unsigned int id;
+} __plt_cache_aligned;
+
+__roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
+__roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
+
+#endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 8e67c83a6..1db4d104a 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -9,6 +9,8 @@ INTERNAL {
cnxk_logtype_sso;
cnxk_logtype_tim;
cnxk_logtype_tm;
+   roc_bphy_cgx_dev_fini;
+   roc_bphy_cgx_dev_init;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 02/28] common/cnxk: add support for communication with atf

Messages can be exchanged between userspace software and firmware
via set of two dedicated registers, namely scratch1 and scratch0.

scratch1 acts as a command register i.e message is sent to firmware,
while scratch0 holds response to previously sent message.

Signed-off-by: Tomasz Duszynski 
Signed-off-by: Jakub Palider 
---
 drivers/common/cnxk/roc_bphy_cgx.c  | 145 
 drivers/common/cnxk/roc_bphy_cgx.h  |   4 +
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  54 +
 drivers/common/cnxk/roc_priv.h  |   3 +
 4 files changed, 206 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx_priv.h

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c 
b/drivers/common/cnxk/roc_bphy_cgx.c
index 029d4102e..5048a90de 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -2,8 +2,13 @@
  * Copyright(C) 2021 Marvell.
  */
 
+#include 
+
 #include "roc_api.h"
+#include "roc_priv.h"
 
+#define CGX_CMRX_INT  0x40
+#define CGX_CMRX_INT_OVERFLW  BIT_ULL(1)
 /*
  * CN10K stores number of lmacs in 4 bit filed
  * in contraty to CN9K which uses only 3 bits.
@@ -15,6 +20,8 @@
  */
 #define CGX_CMRX_RX_LMACS  0x128
 #define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)
+#define CGX_CMRX_SCRATCH0  0x1050
+#define CGX_CMRX_SCRATCH1  0x1058
 
 static uint64_t
 roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
@@ -25,6 +32,137 @@ roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t 
lmac, uint64_t offset)
return plt_read64(base + (lmac << shift) + offset);
 }
 
+static void
+roc_bphy_cgx_write(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t 
offset,
+  uint64_t value)
+{
+   int shift = roc_model_is_cn10k() ? 20 : 18;
+   uint64_t base = (uint64_t)roc_cgx->bar0_va;
+
+   plt_write64(value, base + (lmac << shift) + offset);
+}
+
+static void
+roc_bphy_cgx_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+uint64_t *scr0)
+{
+   uint64_t val;
+
+   /* clear interrupt */
+   val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_INT);
+   val |= FIELD_PREP(CGX_CMRX_INT_OVERFLW, 1);
+   roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_INT, val);
+
+   /* ack fw response */
+   *scr0 &= ~SCR0_ETH_EVT_STS_S_ACK;
+   roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH0, *scr0);
+}
+
+static int
+roc_bphy_cgx_wait_for_ownership(struct roc_bphy_cgx *roc_cgx, unsigned int 
lmac)
+{
+   uint64_t scr0, scr1;
+   int tries = 5000;
+
+   do {
+   scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
+   scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
+
+   if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
+   FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, scr0) == 0)
+   break;
+
+   /* clear async events if any */
+   if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, scr0) == 
ETH_EVT_ASYNC &&
+   FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, scr0))
+   roc_bphy_cgx_ack(roc_cgx, lmac, &scr0);
+
+   plt_delay_ms(1);
+   } while (--tries);
+
+   return tries ? 0 : -ETIMEDOUT;
+}
+
+static int
+roc_bphy_cgx_wait_for_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+   uint64_t scr0, scr1;
+   int tries = 5000;
+
+   do {
+   scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
+   scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
+
+   if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
+   FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, scr0))
+   break;
+
+   plt_delay_ms(1);
+   } while (--tries);
+
+   return tries ? 0 : -ETIMEDOUT;
+}
+
+static int
+roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+ uint64_t scr1, uint64_t *scr0)
+{
+   uint8_t cmd_id = FIELD_GET(SCR1_ETH_CMD_ID, scr1);
+   int ret;
+
+   pthread_mutex_lock(&roc_cgx->lock);
+
+   /* wait for ownership */
+   ret = roc_bphy_cgx_wait_for_ownership(roc_cgx, lmac);
+   if (ret) {
+   plt_err("timed out waiting for ownership");
+   goto out;
+   }
+
+   /* write command */
+   scr1 |= FIELD_PREP(SCR1_OWN_STATUS, ETH_OWN_FIRMWARE);
+   roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH1, scr1);
+
+   /* wait for command ack */
+   ret = roc_bphy_cgx_wait_for_ack(roc_cgx, lmac);
+   if (ret) {
+   plt_err("timed out waiting for response");
+   goto out;
+   }
+
+   if (cmd_id == ETH_CMD_INTF_SHUTDOWN)
+   goto out;
+
+   *scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
+
+   if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) != ETH_EVT_CMD_RESP) {
+   plt_err("received async event

[dpdk-dev] [PATCH 03/28] common/cnxk: add support for getting link information

Add support for retrieving link information.

Signed-off-by: Tomasz Duszynski 
Signed-off-by: Jakub Palider 
---
 drivers/common/cnxk/roc_bphy_cgx.c  | 38 ++
 drivers/common/cnxk/roc_bphy_cgx.h  | 70 +
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  9 
 drivers/common/cnxk/version.map |  1 +
 4 files changed, 118 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c 
b/drivers/common/cnxk/roc_bphy_cgx.c
index 5048a90de..c7ba53ede 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -205,3 +205,41 @@ roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
 
return 0;
 }
+
+static bool
+roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+   return (lmac < MAX_LMACS_PER_CGX) &&
+  (roc_cgx->lmac_bmap & BIT_ULL(lmac));
+}
+
+int
+roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+ struct roc_bphy_cgx_link_info *info)
+{
+   uint64_t scr1, scr0;
+   int ret;
+
+   if (!roc_cgx)
+   return -EINVAL;
+
+   if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+   return -EINVAL;
+
+   if (!info)
+   return -EINVAL;
+
+   scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_GET_LINK_STS);
+   ret = roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+   if (ret)
+   return ret;
+
+   info->link_up = FIELD_GET(SCR0_ETH_LNK_STS_S_LINK_UP, scr0);
+   info->full_duplex = FIELD_GET(SCR0_ETH_LNK_STS_S_FULL_DUPLEX, scr0);
+   info->speed = FIELD_GET(SCR0_ETH_LNK_STS_S_SPEED, scr0);
+   info->an = FIELD_GET(SCR0_ETH_LNK_STS_S_AN, scr0);
+   info->fec = FIELD_GET(SCR0_ETH_LNK_STS_S_FEC, scr0);
+   info->mode = FIELD_GET(SCR0_ETH_LNK_STS_S_MODE, scr0);
+
+   return 0;
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h 
b/drivers/common/cnxk/roc_bphy_cgx.h
index 37b5c2742..bb1d903eb 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -9,6 +9,8 @@
 
 #include "roc_api.h"
 
+#define MAX_LMACS_PER_CGX 4
+
 struct roc_bphy_cgx {
uint64_t bar0_pa;
void *bar0_va;
@@ -18,7 +20,75 @@ struct roc_bphy_cgx {
pthread_mutex_t lock;
 } __plt_cache_aligned;
 
+enum roc_bphy_cgx_eth_link_speed {
+   ROC_BPHY_CGX_ETH_LINK_SPEED_NONE,
+   ROC_BPHY_CGX_ETH_LINK_SPEED_10M,
+   ROC_BPHY_CGX_ETH_LINK_SPEED_100M,
+   ROC_BPHY_CGX_ETH_LINK_SPEED_1G,
+   ROC_BPHY_CGX_ETH_LINK_SPEED_2HG,
+   ROC_BPHY_CGX_ETH_LINK_SPEED_5G,
+   ROC_BPHY_CGX_ETH_LINK_SPEED_10G,
+   ROC_BPHY_CGX_ETH_LINK_SPEED_20G,
+   ROC_BPHY_CGX_ETH_LINK_SPEED_25G,
+   ROC_BPHY_CGX_ETH_LINK_SPEED_40G,
+   ROC_BPHY_CGX_ETH_LINK_SPEED_50G,
+   ROC_BPHY_CGX_ETH_LINK_SPEED_80G,
+   ROC_BPHY_CGX_ETH_LINK_SPEED_100G,
+   __MAX_ROC_BPHY_CGX_ETH_LINK_SPEED
+};
+
+enum roc_bphy_cgx_eth_link_fec {
+   ROC_BPHY_CGX_ETH_LINK_FEC_NONE,
+   ROC_BPHY_CGX_ETH_LINK_FEC_BASE_R,
+   ROC_BPHY_CGX_ETH_LINK_FEC_RS,
+   __MAX_ROC_BPHY_CGX_ETH_LINK_FEC
+};
+
+enum roc_bphy_cgx_eth_link_mode {
+   ROC_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
+   ROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
+   __MAX_ROC_BPHY_CGX_ETH_LINK_MODE
+};
+
+struct roc_bphy_cgx_link_info {
+   bool link_up;
+   bool full_duplex;
+   enum roc_bphy_cgx_eth_link_speed speed;
+   bool an;
+   enum roc_bphy_cgx_eth_link_fec fec;
+   enum roc_bphy_cgx_eth_link_mode mode;
+};
+
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 
+__roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
+

[dpdk-dev] [PATCH 04/28] common/cnxk: add support for changing internal loopback

Add support for enabling or disabling internal loopback.

Signed-off-by: Tomasz Duszynski 
Signed-off-by: Jakub Palider 
---
 drivers/common/cnxk/roc_bphy_cgx.c  | 30 +
 drivers/common/cnxk/roc_bphy_cgx.h  |  4 
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  4 
 drivers/common/cnxk/version.map |  2 ++
 4 files changed, 40 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c 
b/drivers/common/cnxk/roc_bphy_cgx.c
index c7ba53ede..45088d5d4 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -213,6 +213,24 @@ roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, 
unsigned int lmac)
   (roc_cgx->lmac_bmap & BIT_ULL(lmac));
 }
 
+static int
+roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+   bool enable)
+{
+   uint64_t scr1, scr0;
+
+   if (!roc_cgx)
+   return -EINVAL;
+
+   if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+   return -EINVAL;
+
+   scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_INTERNAL_LBK) |
+  FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable);
+
+   return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
 int
 roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
  struct roc_bphy_cgx_link_info *info)
@@ -243,3 +261,15 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, 
unsigned int lmac,
 
return 0;
 }
+
+int
+roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+   return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, true);
+}
+
+int
+roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+   return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, false);
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h 
b/drivers/common/cnxk/roc_bphy_cgx.h
index bb1d903eb..3bb9d49ed 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -90,5 +90,9 @@ __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx 
*roc_cgx);
 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac,
struct roc_bphy_cgx_link_info *info);
+__roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
+unsigned int lmac);
+__roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
+ unsigned int lmac);
 
 #endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h 
b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index c0550ae87..cb59cac09 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -8,6 +8,7 @@
 /* REQUEST ID types. Input to firmware */
 enum eth_cmd_id {
ETH_CMD_GET_LINK_STS = 4,
+   ETH_CMD_INTERNAL_LBK = 7,
ETH_CMD_INTF_SHUTDOWN = 12,
 };
 
@@ -58,6 +59,9 @@ enum eth_cmd_own {
 /* struct eth_cmd */
 #define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2)
 
+/* struct eth_ctl_args */
+#define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8)
+
 #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
 
 #endif /* _ROC_BPHY_CGX_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 466207f9d..71437a6c5 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -12,6 +12,8 @@ INTERNAL {
roc_bphy_cgx_dev_fini;
roc_bphy_cgx_dev_init;
roc_bphy_cgx_get_linkinfo;
+   roc_bphy_cgx_intlbk_disable;
+   roc_bphy_cgx_intlbk_enable;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 05/28] common/cnxk: add support for changing ptp mode

Add support for enabling or disablig ptp mode.

Signed-off-by: Tomasz Duszynski 
Signed-off-by: Jakub Palider 
---
 drivers/common/cnxk/roc_bphy_cgx.c  | 33 +
 drivers/common/cnxk/roc_bphy_cgx.h  |  5 
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  1 +
 drivers/common/cnxk/version.map |  2 ++
 4 files changed, 41 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c 
b/drivers/common/cnxk/roc_bphy_cgx.c
index 45088d5d4..dbdaddcd0 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -231,6 +231,27 @@ roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, 
unsigned int lmac,
return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
 }
 
+static int
+roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+   bool enable)
+{
+   uint64_t scr1, scr0;
+
+   if (roc_model_is_cn10k())
+   return -ENOTSUP;
+
+   if (!roc_cgx)
+   return -EINVAL;
+
+   if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+   return -EINVAL;
+
+   scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_SET_PTP_MODE) |
+  FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable);
+
+   return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
 int
 roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
  struct roc_bphy_cgx_link_info *info)
@@ -273,3 +294,15 @@ roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, 
unsigned int lmac)
 {
return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, false);
 }
+
+int
+roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+   return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, true);
+}
+
+int
+roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+   return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, false);
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h 
b/drivers/common/cnxk/roc_bphy_cgx.h
index 3bb9d49ed..a5e18565d 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -94,5 +94,10 @@ __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx 
*roc_cgx,
 unsigned int lmac);
 __roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
  unsigned int lmac);
+__roc_api int roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx,
+unsigned int lmac);
+__roc_api int roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx,
+ unsigned int lmac);
+
 
 #endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h 
b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index cb59cac09..4e86ae4ea 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -10,6 +10,7 @@ enum eth_cmd_id {
ETH_CMD_GET_LINK_STS = 4,
ETH_CMD_INTERNAL_LBK = 7,
ETH_CMD_INTF_SHUTDOWN = 12,
+   ETH_CMD_SET_PTP_MODE = 34,
 };
 
 /* event types - cause of interrupt */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 71437a6c5..205a0602b 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -14,6 +14,8 @@ INTERNAL {
roc_bphy_cgx_get_linkinfo;
roc_bphy_cgx_intlbk_disable;
roc_bphy_cgx_intlbk_enable;
+   roc_bphy_cgx_ptp_rx_disable;
+   roc_bphy_cgx_ptp_rx_enable;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 06/28] common/cnxk: add support for setting link mode

Add support for setting link mode.

Signed-off-by: Tomasz Duszynski 
Signed-off-by: Jakub Palider 
---
 drivers/common/cnxk/roc_bphy_cgx.c  | 28 
 drivers/common/cnxk/roc_bphy_cgx.h  | 11 +
 drivers/common/cnxk/roc_bphy_cgx_priv.h | 61 +
 drivers/common/cnxk/version.map |  1 +
 4 files changed, 101 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c 
b/drivers/common/cnxk/roc_bphy_cgx.c
index dbdaddcd0..930057bb0 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -283,6 +283,34 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, 
unsigned int lmac,
return 0;
 }
 
+int
+roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+  struct roc_bphy_cgx_link_mode *mode)
+{
+   uint64_t scr1, scr0;
+
+   if (roc_model_is_cn10k())
+   return -ENOTSUP;
+
+   if (!roc_cgx)
+   return -EINVAL;
+
+   if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+   return -EINVAL;
+
+   if (!mode)
+   return -EINVAL;
+
+   scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_MODE_CHANGE) |
+  FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) |
+  FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX, mode->full_duplex) |
+  FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) |
+  FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORT, mode->port) |
+  FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE, BIT_ULL(mode->mode));
+
+   return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
 int
 roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
 {
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h 
b/drivers/common/cnxk/roc_bphy_cgx.h
index a5e18565d..f68ddfcc9 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -75,6 +75,14 @@ enum roc_bphy_cgx_eth_link_mode {
__MAX_ROC_BPHY_CGX_ETH_LINK_MODE
 };
 
+struct roc_bphy_cgx_link_mode {
+   bool full_duplex;
+   bool an;
+   unsigned int port;
+   enum roc_bphy_cgx_eth_link_speed speed;
+   enum roc_bphy_cgx_eth_link_mode mode;
+};
+
 struct roc_bphy_cgx_link_info {
bool link_up;
bool full_duplex;
@@ -90,6 +98,9 @@ __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx 
*roc_cgx);
 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac,
struct roc_bphy_cgx_link_info *info);
+__roc_api int roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx,
+unsigned int lmac,
+struct roc_bphy_cgx_link_mode *mode);
 __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
 unsigned int lmac);
 __roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h 
b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index 4e86ae4ea..ee7578423 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -5,10 +5,64 @@
 #ifndef _ROC_BPHY_CGX_PRIV_H_
 #define _ROC_BPHY_CGX_PRIV_H_
 
+/* LINK speed types */
+enum eth_link_speed {
+   ETH_LINK_NONE,
+   ETH_LINK_10M,
+   ETH_LINK_100M,
+   ETH_LINK_1G,
+   ETH_LINK_2HG, /* 2.5 Gbps */
+   ETH_LINK_5G,
+   ETH_LINK_10G,
+   ETH_LINK_20G,
+   ETH_LINK_25G,
+   ETH_LINK_40G,
+   ETH_LINK_50G,
+   ETH_LINK_80G,
+   ETH_LINK_100G,
+   ETH_LINK_MAX,
+};
+
+/* Supported LINK MODE enums
+ * Each link mode is a bit mask of these
+ * enums which are represented as bits
+ */
+enum eth_mode {
+   ETH_MODE_SGMII_BIT = 0,
+   ETH_MODE_1000_BASEX_BIT,
+   ETH_MODE_QSGMII_BIT,
+   ETH_MODE_10G_C2C_BIT,
+   ETH_MODE_10G_C2M_BIT,
+   ETH_MODE_10G_KR_BIT, /* = 5 */
+   ETH_MODE_20G_C2C_BIT,
+   ETH_MODE_25G_C2C_BIT,
+   ETH_MODE_25G_C2M_BIT,
+   ETH_MODE_25G_2_C2C_BIT,
+   ETH_MODE_25G_CR_BIT, /* = 10 */
+   ETH_MODE_25G_KR_BIT,
+   ETH_MODE_40G_C2C_BIT,
+   ETH_MODE_40G_C2M_BIT,
+   ETH_MODE_40G_CR4_BIT,
+   ETH_MODE_40G_KR4_BIT, /* = 15 */
+   ETH_MODE_40GAUI_C2C_BIT,
+   ETH_MODE_50G_C2C_BIT,
+   ETH_MODE_50G_C2M_BIT,
+   ETH_MODE_50G_4_C2C_BIT,
+   ETH_MODE_50G_CR_BIT, /* = 20 */
+   ETH_MODE_50G_KR_BIT,
+   ETH_MODE_80GAUI_C2C_BIT,
+   ETH_MODE_100G_C2C_BIT,
+   ETH_MODE_100G_C2M_BIT,
+   ETH_MODE_100G_CR4_BIT, /* = 25 */
+   ETH_MODE_100G_KR4_BIT,
+   ETH_MODE_MAX_BIT /* = 27 */
+};
+
 /* REQUEST ID types. Input to firmware */
 enum eth_cmd_id {
ETH_CMD_GET_LINK_STS = 4,
ETH_CMD_INTERNAL_LBK = 7,
+   ETH_CMD_MODE_CHANGE = 11, /* hot plug support */
ETH_CMD_INTF_SHUTDOWN = 12,

[dpdk-dev] [PATCH 07/28] common/cnxk: add support for changing link state

Add support for setting link up or down.

Signed-off-by: Tomasz Duszynski 
Signed-off-by: Jakub Palider 
---
 drivers/common/cnxk/roc_bphy_cgx.c  | 18 ++
 drivers/common/cnxk/roc_bphy_cgx.h  |  2 ++
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  2 ++
 drivers/common/cnxk/version.map |  1 +
 4 files changed, 23 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c 
b/drivers/common/cnxk/roc_bphy_cgx.c
index 930057bb0..d1701eaa7 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -252,6 +252,24 @@ roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, 
unsigned int lmac,
return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
 }
 
+int
+roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+   bool state)
+{
+   uint64_t scr1, scr0;
+
+   if (!roc_cgx)
+   return -EINVAL;
+
+   if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+   return -EINVAL;
+
+   scr1 = state ? FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_LINK_BRING_UP) :
+  FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_LINK_BRING_DOWN);
+
+   return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
 int
 roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
  struct roc_bphy_cgx_link_info *info)
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h 
b/drivers/common/cnxk/roc_bphy_cgx.h
index f68ddfcc9..74f7465e7 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -95,6 +95,8 @@ struct roc_bphy_cgx_link_info {
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 
+__roc_api int roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx,
+ unsigned int lmac, bool state);
 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac,
struct roc_bphy_cgx_link_info *info);
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h 
b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index ee7578423..71a277fff 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -61,6 +61,8 @@ enum eth_mode {
 /* REQUEST ID types. Input to firmware */
 enum eth_cmd_id {
ETH_CMD_GET_LINK_STS = 4,
+   ETH_CMD_LINK_BRING_UP = 5,
+   ETH_CMD_LINK_BRING_DOWN = 6,
ETH_CMD_INTERNAL_LBK = 7,
ETH_CMD_MODE_CHANGE = 11, /* hot plug support */
ETH_CMD_INTF_SHUTDOWN = 12,
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 15a6d3a3b..7766f52e0 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -17,6 +17,7 @@ INTERNAL {
roc_bphy_cgx_ptp_rx_disable;
roc_bphy_cgx_ptp_rx_enable;
roc_bphy_cgx_set_link_mode;
+   roc_bphy_cgx_set_link_state;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 08/28] common/cnxk: add support for lmac start/stop

Add support for starting or stopping specific lmac. Start enables rx/tx
traffic while stop does the opposite.

Signed-off-by: Tomasz Duszynski 
Signed-off-by: Jakub Palider 
---
 drivers/common/cnxk/roc_bphy_cgx.c | 42 ++
 drivers/common/cnxk/roc_bphy_cgx.h |  4 +++
 drivers/common/cnxk/version.map|  2 ++
 3 files changed, 48 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c 
b/drivers/common/cnxk/roc_bphy_cgx.c
index d1701eaa7..886f8d65d 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -7,6 +7,9 @@
 #include "roc_api.h"
 #include "roc_priv.h"
 
+#define CGX_CMRX_CONFIG   0x00
+#define CGX_CMRX_CONFIG_DATA_PKT_RX_EN BIT_ULL(54)
+#define CGX_CMRX_CONFIG_DATA_PKT_TX_EN BIT_ULL(53)
 #define CGX_CMRX_INT  0x40
 #define CGX_CMRX_INT_OVERFLW  BIT_ULL(1)
 /*
@@ -213,6 +216,33 @@ roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, 
unsigned int lmac)
   (roc_cgx->lmac_bmap & BIT_ULL(lmac));
 }
 
+static int
+roc_bphy_cgx_start_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+bool start)
+{
+   uint64_t val;
+
+   if (!roc_cgx)
+   return -EINVAL;
+
+   if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+   return -EINVAL;
+
+   pthread_mutex_lock(&roc_cgx->lock);
+   val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_CONFIG);
+   val &= ~(CGX_CMRX_CONFIG_DATA_PKT_RX_EN |
+CGX_CMRX_CONFIG_DATA_PKT_TX_EN);
+
+   if (start)
+   val |= FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_RX_EN, 1) |
+  FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_TX_EN, 1);
+
+   roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_CONFIG, val);
+   pthread_mutex_unlock(&roc_cgx->lock);
+
+   return 0;
+}
+
 static int
 roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
bool enable)
@@ -252,6 +282,18 @@ roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, 
unsigned int lmac,
return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
 }
 
+int
+roc_bphy_cgx_start_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+   return roc_bphy_cgx_start_stop_rxtx(roc_cgx, lmac, true);
+}
+
+int
+roc_bphy_cgx_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+   return roc_bphy_cgx_start_stop_rxtx(roc_cgx, lmac, false);
+}
+
 int
 roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
bool state)
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h 
b/drivers/common/cnxk/roc_bphy_cgx.h
index 74f7465e7..1f49de8fd 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -95,6 +95,10 @@ struct roc_bphy_cgx_link_info {
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 
+__roc_api int roc_bphy_cgx_start_rxtx(struct roc_bphy_cgx *roc_cgx,
+ unsigned int lmac);
+__roc_api int roc_bphy_cgx_stop_rxtx(struct roc_bphy_cgx *roc_cgx,
+unsigned int lmac);
 __roc_api int roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx,
  unsigned int lmac, bool state);
 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 7766f52e0..0ad805dba 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -18,6 +18,8 @@ INTERNAL {
roc_bphy_cgx_ptp_rx_enable;
roc_bphy_cgx_set_link_mode;
roc_bphy_cgx_set_link_state;
+   roc_bphy_cgx_start_rxtx;
+   roc_bphy_cgx_stop_rxtx;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 10/28] raw/cnxk_bphy: add support for reading queue configuration

Add support for reading queue configuration. Single queue represents
a logical mac available on rpm/cgx.

Signed-off-by: Tomasz Duszynski 
Signed-off-by: Jakub Palider 
---
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c 
b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index e537888f9..016f9f02c 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -27,7 +27,27 @@ cnxk_bphy_cgx_format_name(char *name, unsigned int len,
 pci_dev->addr.devid, pci_dev->addr.function);
 }
 
+static int
+cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
+rte_rawdev_obj_t queue_conf,
+size_t queue_conf_size)
+{
+   unsigned int *conf;
+
+   RTE_SET_USED(dev);
+   RTE_SET_USED(queue_id);
+
+   if (queue_conf_size != sizeof(*conf))
+   return -EINVAL;
+
+   conf = (unsigned int *)queue_conf;
+   *conf = 1;
+
+   return 0;
+}
+
 static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
+   .queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
 };
 
 static void
-- 
2.25.1

[dpdk-dev] [PATCH 09/28] raw/cnxk_bphy: add bphy cgx/rpm skeleton driver

Add baseband phy cgx/rpm skeleton driver. At this point
it merely probes a matching device.

Signed-off-by: Tomasz Duszynski 
Signed-off-by: Jakub Palider 
---
 MAINTAINERS   |   5 +
 doc/guides/rawdevs/cnxk_bphy.rst  |  50 +
 doc/guides/rawdevs/index.rst  |   1 +
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 151 ++
 drivers/raw/cnxk_bphy/meson.build |   8 ++
 drivers/raw/cnxk_bphy/version.map |   3 +
 drivers/raw/meson.build   |   1 +
 usertools/dpdk-devbind.py |   4 +-
 8 files changed, 222 insertions(+), 1 deletion(-)
 create mode 100644 doc/guides/rawdevs/cnxk_bphy.rst
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
 create mode 100644 drivers/raw/cnxk_bphy/meson.build
 create mode 100644 drivers/raw/cnxk_bphy/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 5877a1697..863b028fd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1307,6 +1307,11 @@ F: doc/guides/rawdevs/ntb.rst
 F: examples/ntb/
 F: doc/guides/sample_app_ug/ntb.rst
 
+Marvell CNXK BPHY
+M: Tomasz Duszynski 
+M: Jakub Palider 
+F: drivers/raw/cnxk_bphy/
+F: doc/guides/rawdevs/cnxk_bphy.rst
 
 Packet processing
 -
diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
new file mode 100644
index 0..1b117a0e8
--- /dev/null
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -0,0 +1,50 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+Copyright(c) 2021 Marvell International Ltd.
+
+Marvell CNXK BPHY Driver
+==
+
+CN10K/CN9K Fusion product families offer an internal BPHY unit which provides
+set of hardware accelerators for performing baseband related operations. 
Connectivity
+to the outside world happens through a block called RFOE which is backed by
+ethernet I/O block called CGX or RPM (depending on the chip version). RFOE
+stands for Radio Frequency Over Ethernet and provides support for
+IEEE 1904.3 (RoE) standard.
+
+Features
+
+
+The BPHY CGX/RPM implements following features in the rawdev API:
+
+- Access to BPHY CGX/RPM via set of predefined messages.
+
+Device Setup
+
+
+The BPHY CGX/RPM  devices will need to be bound to a user-space IO driver for
+use. The script ``dpdk-devbind.py`` script included with DPDK can be used to
+view the state of the devices and to bind them to a suitable DPDK-supported
+kernel driver. When querying the status of the devices, they will appear under
+the category of "Misc (rawdev) devices", i.e. the command
+``dpdk-devbind.py --status-dev misc`` can be used to see the state of those
+devices alone.
+
+To perform data transfer use standard ``rte_rawdev_enqueue_buffers()`` and
+``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible
+responses hence dequeueing is not always necessary.
+
+Self test
+-
+
+On EAL initialization, BPHY CGX/RPM devices will be probed and populated into
+the raw devices. The rawdev ID of the device can be obtained using invocation
+of ``rte_rawdev_get_dev_id("NAME:x")`` from the test application, where:
+
+- NAME is the desired subsystem: use "BPHY_CGX" for
+  RFOE module,
+- x is the device's bus id specified in "bus:device.func" (BDF) format.
+
+Use this identifier for further rawdev function calls.
+
+The driver's selftest rawdev API can be used to verify the BPHY CGX/RPM
+functionality.
diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst
index f64ec4427..7fbae40ea 100644
--- a/doc/guides/rawdevs/index.rst
+++ b/doc/guides/rawdevs/index.rst
@@ -11,6 +11,7 @@ application through rawdev API.
 :maxdepth: 2
 :numbered:
 
+cnxk_bphy
 dpaa2_cmdif
 dpaa2_qdma
 ifpga
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c 
b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
new file mode 100644
index 0..e537888f9
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include 
+#include 
+#include 
+
+#include 
+
+struct cnxk_bphy_cgx_queue {
+   unsigned int lmac;
+   /* queue holds up to one response */
+   void *rsp;
+};
+
+struct cnxk_bphy_cgx {
+   struct roc_bphy_cgx *rcgx;
+   struct cnxk_bphy_cgx_queue queues[MAX_LMACS_PER_CGX];
+   unsigned int num_queues;
+};
+
+static void
+cnxk_bphy_cgx_format_name(char *name, unsigned int len,
+ struct rte_pci_device *pci_dev)
+{
+   snprintf(name, len, "BPHY_CGX:%x:%02x.%x", pci_dev->addr.bus,
+pci_dev->addr.devid, pci_dev->addr.function);
+}
+
+static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
+};
+
+static void
+cnxk_bphy_cgx_init_queues(struct cnxk_bphy_cgx *cgx)
+{
+   struct roc_bphy_cgx *rcgx = cgx->rcgx;
+   unsigned int i;
+
+   for (i = 0; i < RTE_DIM(cgx->queues); i++) {
+   if (!(rcgx->lmac_bmap & BIT_ULL(i)))
+   continue;
+
+

[dpdk-dev] [PATCH 11/28] raw/cnxk_bphy: add support for reading queue count

Add support for reading number of available queues i.e number
of available logical macs (LMACs).

Signed-off-by: Tomasz Duszynski 
Signed-off-by: Jakub Palider 
---
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c 
b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index 016f9f02c..da4372642 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -46,8 +46,17 @@ cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, 
uint16_t queue_id,
return 0;
 }
 
+static uint16_t
+cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
+{
+   struct cnxk_bphy_cgx *cgx = dev->dev_private;
+
+   return cgx->num_queues;
+}
+
 static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
.queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
+   .queue_count = cnxk_bphy_cgx_queue_count,
 };
 
 static void
-- 
2.25.1

[dpdk-dev] [PATCH 12/28] raw/cnxk_bphy: add support for enqueue operation

Add support for enqueueing messages.

Signed-off-by: Tomasz Duszynski 
Signed-off-by: Jakub Palider 
---
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 112 ++
 drivers/raw/cnxk_bphy/meson.build |   1 +
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  | 104 
 3 files changed, 217 insertions(+)
 create mode 100644 drivers/raw/cnxk_bphy/rte_pmd_bphy.h

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c 
b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index da4372642..637514406 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -1,12 +1,16 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(C) 2021 Marvell.
  */
+#include 
+
 #include 
 #include 
 #include 
 
 #include 
 
+#include "rte_pmd_bphy.h"
+
 struct cnxk_bphy_cgx_queue {
unsigned int lmac;
/* queue holds up to one response */
@@ -46,6 +50,113 @@ cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, 
uint16_t queue_id,
return 0;
 }
 
+static int
+cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,
+ struct rte_rawdev_buf *buf)
+{
+   struct cnxk_bphy_cgx_queue *qp = &cgx->queues[queue];
+   struct cnxk_bphy_cgx_msg_set_link_state *link_state;
+   struct cnxk_bphy_cgx_msg *msg = buf->buf_addr;
+   struct cnxk_bphy_cgx_msg_link_mode *link_mode;
+   struct cnxk_bphy_cgx_msg_link_info *link_info;
+   struct roc_bphy_cgx_link_info rlink_info;
+   struct roc_bphy_cgx_link_mode rlink_mode;
+   unsigned int lmac = qp->lmac;
+   void *rsp = NULL;
+   int ret;
+
+   switch (msg->type) {
+   case CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO:
+   memset(&rlink_info, 0, sizeof(rlink_info));
+   ret = roc_bphy_cgx_get_linkinfo(cgx->rcgx, lmac, &rlink_info);
+   if (ret)
+   break;
+
+   link_info = rte_zmalloc(NULL, sizeof(*link_info), 0);
+   if (!link_info)
+   return -ENOMEM;
+
+   link_info->link_up = rlink_info.link_up;
+   link_info->full_duplex = rlink_info.full_duplex;
+   link_info->speed =
+   (enum cnxk_bphy_cgx_eth_link_speed)rlink_info.speed;
+   link_info->autoneg = rlink_info.an;
+   link_info->fec =
+   (enum cnxk_bphy_cgx_eth_link_fec)rlink_info.fec;
+   link_info->mode =
+   (enum cnxk_bphy_cgx_eth_link_mode)rlink_info.mode;
+   rsp = link_info;
+   break;
+   case CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE:
+   ret = roc_bphy_cgx_intlbk_disable(cgx->rcgx, lmac);
+   break;
+   case CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE:
+   ret = roc_bphy_cgx_intlbk_enable(cgx->rcgx, lmac);
+   break;
+   case CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE:
+   ret = roc_bphy_cgx_ptp_rx_disable(cgx->rcgx, lmac);
+   break;
+   case CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE:
+   ret = roc_bphy_cgx_ptp_rx_enable(cgx->rcgx, lmac);
+   break;
+   case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE:
+   link_mode = msg->data;
+   memset(&rlink_mode, 0, sizeof(rlink_mode));
+   rlink_mode.full_duplex = link_mode->full_duplex;
+   rlink_mode.an = link_mode->autoneg;
+   rlink_mode.speed =
+   (enum roc_bphy_cgx_eth_link_speed)link_mode->speed;
+   rlink_mode.mode =
+   (enum roc_bphy_cgx_eth_link_mode)link_mode->mode;
+   ret = roc_bphy_cgx_set_link_mode(cgx->rcgx, lmac, &rlink_mode);
+   break;
+   case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE:
+   link_state = msg->data;
+   ret = roc_bphy_cgx_set_link_state(cgx->rcgx, lmac,
+ link_state->state);
+   break;
+   case CNXK_BPHY_CGX_MSG_TYPE_START_RXTX:
+   ret = roc_bphy_cgx_start_rxtx(cgx->rcgx, lmac);
+   break;
+   case CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX:
+   ret = roc_bphy_cgx_stop_rxtx(cgx->rcgx, lmac);
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   /* get rid of last response if any */
+   if (qp->rsp) {
+   RTE_LOG(WARNING, PMD, "Previous response got overwritten\n");
+   rte_free(qp->rsp);
+   }
+   qp->rsp = rsp;
+
+   return ret;
+}
+
+static int
+cnxk_bphy_cgx_enqueue_bufs(struct rte_rawdev *dev,
+  struct rte_rawdev_buf **buffers, unsigned int count,
+  rte_rawdev_obj_t context)
+{
+   struct cnxk_bphy_cgx *cgx = dev->dev_private;
+   unsigned int queue = (size_t)context;
+   int ret;
+
+   if (queue >= cgx->num_queues)
+   return -EINVAL;
+
+   if (count == 0)
+

[dpdk-dev] [PATCH 13/28] raw/cnxk_bphy: add support for dequeue operation

Add support for dequeueing responses to previously
enqueued messages.

Signed-off-by: Tomasz Duszynski 
Signed-off-by: Jakub Palider 
---
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c 
b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index 637514406..a8eafae1b 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -157,6 +157,32 @@ cnxk_bphy_cgx_enqueue_bufs(struct rte_rawdev *dev,
return 1;
 }
 
+static int
+cnxk_bphy_cgx_dequeue_bufs(struct rte_rawdev *dev,
+  struct rte_rawdev_buf **buffers, unsigned int count,
+  rte_rawdev_obj_t context)
+{
+   struct cnxk_bphy_cgx *cgx = dev->dev_private;
+   unsigned int queue = (size_t)context;
+   struct cnxk_bphy_cgx_queue *qp;
+
+   if (queue >= cgx->num_queues)
+   return -EINVAL;
+
+   if (count == 0)
+   return 0;
+
+   qp = &cgx->queues[queue];
+   if (qp->rsp) {
+   buffers[0]->buf_addr = qp->rsp;
+   qp->rsp = NULL;
+
+   return 1;
+   }
+
+   return 0;
+}
+
 static uint16_t
 cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
 {
@@ -168,6 +194,7 @@ cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
 static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
.queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
.enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs,
+   .dequeue_bufs = cnxk_bphy_cgx_dequeue_bufs,
.queue_count = cnxk_bphy_cgx_queue_count,
 };
 
-- 
2.25.1

[dpdk-dev] [PATCH 14/28] raw/cnxk_bphy: add support for performing selftest

Add support for performing selftest operation.

Signed-off-by: Tomasz Duszynski 
Signed-off-by: Jakub Palider 
---
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c  |   2 +
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h  |  10 +
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c | 206 +
 drivers/raw/cnxk_bphy/meson.build  |   1 +
 4 files changed, 219 insertions(+)
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c 
b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index a8eafae1b..3da224414 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -9,6 +9,7 @@
 
 #include 
 
+#include "cnxk_bphy_cgx.h"
 #include "rte_pmd_bphy.h"
 
 struct cnxk_bphy_cgx_queue {
@@ -196,6 +197,7 @@ static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops 
= {
.enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs,
.dequeue_bufs = cnxk_bphy_cgx_dequeue_bufs,
.queue_count = cnxk_bphy_cgx_queue_count,
+   .dev_selftest = cnxk_bphy_cgx_dev_selftest,
 };
 
 static void
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h 
b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
new file mode 100644
index 0..cd14a3850
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell International Ltd.
+ */
+
+#ifndef _CNXK_BPHY_CGX_H_
+#define _CNXK_BPHY_CGX_H_
+
+int cnxk_bphy_cgx_dev_selftest(uint16_t dev_id);
+
+#endif /* _CNXK_BPHY_CGX_H_ */
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c 
b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
new file mode 100644
index 0..cb4dd4b22
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "cnxk_bphy_cgx.h"
+#include "rte_pmd_bphy.h"
+
+static int
+cnxk_bphy_cgx_enq_msg(uint16_t dev_id, unsigned int queue, void *msg)
+{
+   struct rte_rawdev_buf *bufs[1];
+   struct rte_rawdev_buf buf;
+   void *q;
+   int ret;
+
+   q = (void *)(size_t)queue;
+   buf.buf_addr = msg;
+   bufs[0] = &buf;
+
+   ret = rte_rawdev_enqueue_buffers(dev_id, bufs, 1, q);
+   if (ret < 0)
+   return ret;
+   if (ret != 1)
+   return -EIO;
+
+   return 0;
+}
+
+static int
+cnxk_bphy_cgx_deq_msg(uint16_t dev_id, unsigned int queue, void **msg)
+{
+   struct rte_rawdev_buf *bufs[1];
+   struct rte_rawdev_buf buf;
+   void *q;
+   int ret;
+
+   q = (void *)(size_t)queue;
+   bufs[0] = &buf;
+
+   ret = rte_rawdev_dequeue_buffers(dev_id, bufs, 1, q);
+   if (ret < 0)
+   return ret;
+   if (ret != 1)
+   return -EIO;
+
+   *msg = buf.buf_addr;
+
+   return 0;
+}
+
+static int
+cnxk_bphy_cgx_link_cond(uint16_t dev_id, unsigned int queue, int cond)
+{
+   int tries = 10, ret;
+
+   do {
+   struct cnxk_bphy_cgx_msg_link_info *link_info = NULL;
+   struct cnxk_bphy_cgx_msg msg;
+
+   msg.type = CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO;
+   ret = cnxk_bphy_cgx_enq_msg(dev_id, queue, &msg);
+   if (ret)
+   return ret;
+
+   ret = cnxk_bphy_cgx_deq_msg(dev_id, queue, (void **)&link_info);
+   if (ret)
+   return ret;
+
+   if (link_info->link_up == cond) {
+   rte_free(link_info);
+   break;
+   }
+
+   rte_free(link_info);
+   rte_delay_ms(500);
+   } while (--tries);
+
+   if (tries)
+   return !!cond;
+
+   return -ETIMEDOUT;
+}
+
+int
+cnxk_bphy_cgx_dev_selftest(uint16_t dev_id)
+{
+   unsigned int queues, i;
+   int ret;
+
+   queues = rte_rawdev_queue_count(dev_id);
+   if (queues == 0)
+   return -ENODEV;
+
+   ret = rte_rawdev_start(dev_id);
+   if (ret)
+   return ret;
+
+   for (i = 0; i < queues; i++) {
+   struct cnxk_bphy_cgx_msg_set_link_state link_state;
+   struct cnxk_bphy_cgx_msg msg;
+   unsigned int descs;
+
+   ret = rte_rawdev_queue_conf_get(dev_id, i, &descs,
+   sizeof(descs));
+   if (ret)
+   break;
+   if (descs != 1) {
+   RTE_LOG(ERR, PMD, "Wrong number of descs reported\n");
+   ret = -ENODEV;
+   break;
+   }
+
+   RTE_LOG(INFO, PMD, "Testing queue %d\n", i);
+
+   /* stop rx/tx */
+   msg.type = CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX;
+   ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+

[dpdk-dev] [PATCH 15/28] common/cnxk: add support for device init and fini

Add support for device init and fini. It merely saves
baseband phy state container in a globally accessible
resource chest.

Signed-off-by: Jakub Palider 
Signed-off-by: Tomasz Duszynski 
---
 drivers/common/cnxk/meson.build |  1 +
 drivers/common/cnxk/roc_api.h   |  4 +++
 drivers/common/cnxk/roc_bphy.c  | 40 +
 drivers/common/cnxk/roc_bphy.h  | 17 
 drivers/common/cnxk/roc_idev.c  |  1 +
 drivers/common/cnxk/roc_idev_priv.h |  2 ++
 drivers/common/cnxk/version.map |  2 ++
 7 files changed, 67 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_bphy.c
 create mode 100644 drivers/common/cnxk/roc_bphy.h

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 59975fd34..946b98f46 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -11,6 +11,7 @@ endif
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 deps = ['eal', 'pci', 'bus_pci', 'mbuf']
 sources = files(
+'roc_bphy.c',
 'roc_bphy_cgx.c',
 'roc_dev.c',
 'roc_idev.c',
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 256d8c68d..dd0047873 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -50,6 +50,7 @@
 #define PCI_DEVID_CNXK_EP_VF 0xB203
 #define PCI_DEVID_CNXK_RVU_SDP_PF 0xA0f6
 #define PCI_DEVID_CNXK_RVU_SDP_VF 0xA0f7
+#define PCI_DEVID_CNXK_BPHY  0xA089
 
 #define PCI_DEVID_CN9K_CGX  0xA059
 #define PCI_DEVID_CN10K_RPM 0xA060
@@ -103,4 +104,7 @@
 /* Baseband phy cgx */
 #include "roc_bphy_cgx.h"
 
+/* Baseband phy */
+#include "roc_bphy.h"
+
 #endif /* _ROC_API_H_ */
diff --git a/drivers/common/cnxk/roc_bphy.c b/drivers/common/cnxk/roc_bphy.c
new file mode 100644
index 0..77606d646
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+int
+roc_bphy_dev_init(struct roc_bphy *roc_bphy)
+{
+   struct idev_cfg *idev;
+
+   idev = idev_get_cfg();
+   if (!idev)
+   return -ENODEV;
+
+   if (!roc_bphy || !roc_bphy->pci_dev)
+   return -EINVAL;
+
+   idev->bphy = roc_bphy;
+
+   return 0;
+}
+
+int
+roc_bphy_dev_fini(struct roc_bphy *roc_bphy)
+{
+   struct idev_cfg *idev;
+
+   idev = idev_get_cfg();
+   if (!idev)
+   return -ENODEV;
+
+   if (!roc_bphy)
+   return -EINVAL;
+
+   idev->bphy = NULL;
+
+   return 0;
+}
diff --git a/drivers/common/cnxk/roc_bphy.h b/drivers/common/cnxk/roc_bphy.h
new file mode 100644
index 0..0579c6c44
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2020 Marvell.
+ */
+
+#ifndef _ROC_BPHY_
+#define _ROC_BPHY_
+
+#include "roc_api.h"
+
+struct roc_bphy {
+   struct plt_pci_device *pci_dev;
+} __plt_cache_aligned;
+
+int __roc_api roc_bphy_dev_init(struct roc_bphy *roc_bphy);
+int __roc_api roc_bphy_dev_fini(struct roc_bphy *roc_bphy);
+
+#endif /* _ROC_BPHY_ */
diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c
index 63cc04044..4d7b53422 100644
--- a/drivers/common/cnxk/roc_idev.c
+++ b/drivers/common/cnxk/roc_idev.c
@@ -36,6 +36,7 @@ idev_set_defaults(struct idev_cfg *idev)
idev->lmt_pf_func = 0;
idev->lmt_base_addr = 0;
idev->num_lmtlines = 0;
+   idev->bphy = NULL;
__atomic_store_n(&idev->npa_refcnt, 0, __ATOMIC_RELEASE);
 }
 
diff --git a/drivers/common/cnxk/roc_idev_priv.h 
b/drivers/common/cnxk/roc_idev_priv.h
index ff10a905c..384f667ea 100644
--- a/drivers/common/cnxk/roc_idev_priv.h
+++ b/drivers/common/cnxk/roc_idev_priv.h
@@ -7,6 +7,7 @@
 
 /* Intra device related functions */
 struct npa_lf;
+struct roc_bphy;
 struct idev_cfg {
uint16_t sso_pf_func;
uint16_t npa_pf_func;
@@ -16,6 +17,7 @@ struct idev_cfg {
uint16_t lmt_pf_func;
uint16_t num_lmtlines;
uint64_t lmt_base_addr;
+   struct roc_bphy *bphy;
 };
 
 /* Generic */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 0ad805dba..25083d9d4 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -20,6 +20,8 @@ INTERNAL {
roc_bphy_cgx_set_link_state;
roc_bphy_cgx_start_rxtx;
roc_bphy_cgx_stop_rxtx;
+   roc_bphy_dev_fini;
+   roc_bphy_dev_init;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 16/28] common/cnxk: add support for baseband phy irq setup

Add support for initializing baseband phy irqs. While at it
also add support for reverting back to the default state.

Signed-off-by: Jakub Palider 
Signed-off-by: Tomasz Duszynski 
---
 drivers/common/cnxk/meson.build|  1 +
 drivers/common/cnxk/roc_bphy_irq.c | 96 ++
 drivers/common/cnxk/roc_bphy_irq.h | 27 +
 drivers/common/cnxk/version.map|  2 +
 4 files changed, 126 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_bphy_irq.c
 create mode 100644 drivers/common/cnxk/roc_bphy_irq.h

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 946b98f46..c0ec54932 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -13,6 +13,7 @@ deps = ['eal', 'pci', 'bus_pci', 'mbuf']
 sources = files(
 'roc_bphy.c',
 'roc_bphy_cgx.c',
+'roc_bphy_irq.c',
 'roc_dev.c',
 'roc_idev.c',
 'roc_irq.c',
diff --git a/drivers/common/cnxk/roc_bphy_irq.c 
b/drivers/common/cnxk/roc_bphy_irq.c
new file mode 100644
index 0..c57506542
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include 
+#include 
+#include 
+
+#include "roc_api.h"
+#include "roc_bphy_irq.h"
+
+#define ROC_BPHY_MEMZONE_NAME "roc_bphy_mz"
+#define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr"
+
+#define ROC_BPHY_IOC_MAGIC 0xF3
+#define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ  _IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
+#define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
+
+struct roc_bphy_irq_chip *
+roc_bphy_intr_init(void)
+{
+   struct roc_bphy_irq_chip *irq_chip;
+   uint64_t max_irq, i, avail_irqs;
+   int fd, ret;
+
+   fd = open(ROC_BPHY_CTR_DEV_PATH, O_RDWR | O_SYNC);
+   if (fd < 0) {
+   plt_err("Failed to open %s", ROC_BPHY_CTR_DEV_PATH);
+   return NULL;
+   }
+
+   ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_MAX_IRQ, &max_irq);
+   if (ret < 0) {
+   plt_err("Failed to get max irq number via ioctl");
+   goto err_ioctl;
+   }
+
+   ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ, &avail_irqs);
+   if (ret < 0) {
+   plt_err("Failed to get available irqs bitmask via ioctl");
+   goto err_ioctl;
+   }
+
+   irq_chip = plt_zmalloc(sizeof(*irq_chip), 0);
+   if (irq_chip == NULL) {
+   plt_err("Failed to alloc irq_chip");
+   goto err_alloc_chip;
+   }
+
+   irq_chip->intfd = fd;
+   irq_chip->max_irq = max_irq;
+   irq_chip->avail_irq_bmask = avail_irqs;
+   irq_chip->irq_vecs =
+   plt_zmalloc(irq_chip->max_irq * sizeof(*irq_chip->irq_vecs), 0);
+   if (irq_chip->irq_vecs == NULL) {
+   plt_err("Failed to alloc irq_chip irq_vecs");
+   goto err_alloc_irq;
+   }
+
+   irq_chip->mz_name = plt_zmalloc(strlen(ROC_BPHY_MEMZONE_NAME) + 1, 0);
+   if (irq_chip->mz_name == NULL) {
+   plt_err("Failed to alloc irq_chip name");
+   goto err_alloc_name;
+   }
+   plt_strlcpy(irq_chip->mz_name, ROC_BPHY_MEMZONE_NAME,
+   strlen(ROC_BPHY_MEMZONE_NAME) + 1);
+
+   for (i = 0; i < irq_chip->max_irq; i++) {
+   irq_chip->irq_vecs[i].fd = -1;
+   irq_chip->irq_vecs[i].handler_cpu = -1;
+   }
+
+   return irq_chip;
+
+err_alloc_name:
+   plt_free(irq_chip->irq_vecs);
+
+err_alloc_irq:
+   plt_free(irq_chip);
+
+err_ioctl:
+err_alloc_chip:
+   close(fd);
+   return NULL;
+}
+
+void
+roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
+{
+   if (irq_chip == NULL)
+   return;
+
+   close(irq_chip->intfd);
+   plt_free(irq_chip->mz_name);
+   plt_free(irq_chip->irq_vecs);
+   plt_free(irq_chip);
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h 
b/drivers/common/cnxk/roc_bphy_irq.h
new file mode 100644
index 0..b5200786b
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_BPHY_IRQ_
+#define _ROC_BPHY_IRQ_
+
+struct roc_bphy_irq_vec {
+   int fd;
+   int handler_cpu;
+   void (*handler)(int irq_num, void *isr_data);
+   void *isr_data;
+};
+
+struct roc_bphy_irq_chip {
+   struct roc_bphy_irq_vec *irq_vecs;
+   uint64_t max_irq;
+   uint64_t avail_irq_bmask;
+   int intfd;
+   int n_handlers;
+   char *mz_name;
+};
+
+__roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
+__roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+
+#endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 25083d9d4..483e52018 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -22,6 +22,8 @@ INTERNAL {

[dpdk-dev] [PATCH 17/28] common/cnxk: add support for checking irq availability

Add support for checking whether given irq is available.

Signed-off-by: Jakub Palider 
Signed-off-by: Tomasz Duszynski 
---
 drivers/common/cnxk/roc_bphy_irq.c | 9 +
 drivers/common/cnxk/roc_bphy_irq.h | 2 ++
 drivers/common/cnxk/version.map| 1 +
 3 files changed, 12 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c 
b/drivers/common/cnxk/roc_bphy_irq.c
index c57506542..bea2b7f73 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -94,3 +94,12 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
plt_free(irq_chip->irq_vecs);
plt_free(irq_chip);
 }
+
+bool
+roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
+{
+   if (irq_num < 0 || (uint64_t)irq_num >= irq_chip->max_irq)
+   return false;
+
+   return irq_chip->avail_irq_bmask & BIT(irq_num);
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h 
b/drivers/common/cnxk/roc_bphy_irq.h
index b5200786b..f481f4456 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -23,5 +23,7 @@ struct roc_bphy_irq_chip {
 
 __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+__roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
+  int irq_num);
 
 #endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 483e52018..427321c41 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -22,6 +22,7 @@ INTERNAL {
roc_bphy_cgx_stop_rxtx;
roc_bphy_dev_fini;
roc_bphy_dev_init;
+   roc_bphy_intr_available;
roc_bphy_intr_fini;
roc_bphy_intr_init;
roc_clk_freq_get;
-- 
2.25.1

[dpdk-dev] [PATCH 18/28] common/cnxk: add support for retrieving irq stack

Add support for retrieving irq stack. If stack does not exist
then it gets created.

Signed-off-by: Jakub Palider 
Signed-off-by: Tomasz Duszynski 
---
 drivers/common/cnxk/roc_bphy_irq.c | 62 ++
 drivers/common/cnxk/roc_bphy_irq.h |  1 +
 drivers/common/cnxk/version.map|  1 +
 3 files changed, 64 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c 
b/drivers/common/cnxk/roc_bphy_irq.c
index bea2b7f73..04ad129ac 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -2,12 +2,21 @@
  * Copyright(C) 2021 Marvell.
  */
 #include 
+#include 
 #include 
+#include 
 #include 
 
 #include "roc_api.h"
 #include "roc_bphy_irq.h"
 
+struct roc_bphy_irq_stack {
+   STAILQ_ENTRY(roc_bphy_irq_stack) entries;
+   void *sp_buffer;
+   int cpu;
+   int inuse;
+};
+
 #define ROC_BPHY_MEMZONE_NAME "roc_bphy_mz"
 #define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr"
 
@@ -15,6 +24,12 @@
 #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ  _IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
 #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
 
+static STAILQ_HEAD(slisthead, roc_bphy_irq_stack)
+   irq_stacks = STAILQ_HEAD_INITIALIZER(irq_stacks);
+
+/* Note: it is assumed that as for now there is no multiprocess support */
+static pthread_mutex_t stacks_mutex = PTHREAD_MUTEX_INITIALIZER;
+
 struct roc_bphy_irq_chip *
 roc_bphy_intr_init(void)
 {
@@ -95,6 +110,53 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
plt_free(irq_chip);
 }
 
+void *
+roc_bphy_irq_stack_get(int cpu)
+{
+#define ARM_STACK_ALIGNMENT (2 * sizeof(void *))
+#define IRQ_ISR_STACK_SIZE  0x20
+
+   struct roc_bphy_irq_stack *curr_stack;
+   void *retval = NULL;
+
+   if (pthread_mutex_lock(&stacks_mutex))
+   return NULL;
+
+   STAILQ_FOREACH(curr_stack, &irq_stacks, entries) {
+   if (curr_stack->cpu == cpu) {
+   curr_stack->inuse++;
+   retval = ((char *)curr_stack->sp_buffer) +
+IRQ_ISR_STACK_SIZE;
+   goto found_stack;
+   }
+   }
+
+   curr_stack = plt_zmalloc(sizeof(struct roc_bphy_irq_stack), 0);
+   if (curr_stack == NULL)
+   goto err_stack;
+
+   curr_stack->sp_buffer =
+   plt_zmalloc(IRQ_ISR_STACK_SIZE * 2, ARM_STACK_ALIGNMENT);
+   if (curr_stack->sp_buffer == NULL)
+   goto err_buffer;
+
+   curr_stack->cpu = cpu;
+   curr_stack->inuse = 0;
+   STAILQ_INSERT_TAIL(&irq_stacks, curr_stack, entries);
+   retval = ((char *)curr_stack->sp_buffer) + IRQ_ISR_STACK_SIZE;
+
+found_stack:
+   pthread_mutex_unlock(&stacks_mutex);
+   return retval;
+
+err_buffer:
+   plt_free(curr_stack);
+
+err_stack:
+   pthread_mutex_unlock(&stacks_mutex);
+   return NULL;
+}
+
 bool
 roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
 {
diff --git a/drivers/common/cnxk/roc_bphy_irq.h 
b/drivers/common/cnxk/roc_bphy_irq.h
index f481f4456..e66b2aa7c 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -23,6 +23,7 @@ struct roc_bphy_irq_chip {
 
 __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+__roc_api void *roc_bphy_irq_stack_get(int cpu);
 __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
   int irq_num);
 
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 427321c41..542364926 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -25,6 +25,7 @@ INTERNAL {
roc_bphy_intr_available;
roc_bphy_intr_fini;
roc_bphy_intr_init;
+   roc_bphy_irq_stack_get;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 19/28] common/cnxk: add support for removing irq stack

Add support for removing existing irq stack.

Signed-off-by: Jakub Palider 
Signed-off-by: Tomasz Duszynski 
---
 drivers/common/cnxk/roc_bphy_irq.c | 30 ++
 drivers/common/cnxk/roc_bphy_irq.h |  1 +
 drivers/common/cnxk/version.map|  1 +
 3 files changed, 32 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c 
b/drivers/common/cnxk/roc_bphy_irq.c
index 04ad129ac..a90c055ff 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -110,6 +110,36 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
plt_free(irq_chip);
 }
 
+void
+roc_bphy_irq_stack_remove(int cpu)
+{
+   struct roc_bphy_irq_stack *curr_stack;
+
+   if (pthread_mutex_lock(&stacks_mutex))
+   return;
+
+   STAILQ_FOREACH(curr_stack, &irq_stacks, entries) {
+   if (curr_stack->cpu == cpu)
+   break;
+   }
+
+   if (curr_stack == NULL)
+   goto leave;
+
+   if (curr_stack->inuse > 0)
+   curr_stack->inuse--;
+
+   if (curr_stack->inuse == 0) {
+   STAILQ_REMOVE(&irq_stacks, curr_stack, roc_bphy_irq_stack,
+ entries);
+   plt_free(curr_stack->sp_buffer);
+   plt_free(curr_stack);
+   }
+
+leave:
+   pthread_mutex_unlock(&stacks_mutex);
+}
+
 void *
 roc_bphy_irq_stack_get(int cpu)
 {
diff --git a/drivers/common/cnxk/roc_bphy_irq.h 
b/drivers/common/cnxk/roc_bphy_irq.h
index e66b2aa7c..549a84a7d 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -23,6 +23,7 @@ struct roc_bphy_irq_chip {
 
 __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+__roc_api void roc_bphy_irq_stack_remove(int cpu);
 __roc_api void *roc_bphy_irq_stack_get(int cpu);
 __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
   int irq_num);
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 542364926..78601fe31 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -26,6 +26,7 @@ INTERNAL {
roc_bphy_intr_fini;
roc_bphy_intr_init;
roc_bphy_irq_stack_get;
+   roc_bphy_irq_stack_remove;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 20/28] common/cnxk: add support for setting bphy irq handler

Add support for setting custom baseband phy irq handler.

Signed-off-by: Jakub Palider 
Signed-off-by: Tomasz Duszynski 
---
 drivers/common/cnxk/roc_bphy_irq.c   | 121 +++
 drivers/common/cnxk/roc_bphy_irq.h   |   5 ++
 drivers/common/cnxk/roc_io.h |   9 ++
 drivers/common/cnxk/roc_io_generic.h |   5 ++
 drivers/common/cnxk/version.map  |   2 +
 5 files changed, 142 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c 
b/drivers/common/cnxk/roc_bphy_irq.c
index a90c055ff..f988abf51 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -4,12 +4,22 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
 #include "roc_api.h"
 #include "roc_bphy_irq.h"
 
+#define roc_cpuset_t cpu_set_t
+
+struct roc_bphy_irq_usr_data {
+   uint64_t isr_base;
+   uint64_t sp;
+   uint64_t cpu;
+   uint64_t irq_num;
+};
+
 struct roc_bphy_irq_stack {
STAILQ_ENTRY(roc_bphy_irq_stack) entries;
void *sp_buffer;
@@ -21,6 +31,8 @@ struct roc_bphy_irq_stack {
 #define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr"
 
 #define ROC_BPHY_IOC_MAGIC 0xF3
+#define ROC_BPHY_IOC_SET_BPHY_HANDLER  
\
+   _IOW(ROC_BPHY_IOC_MAGIC, 1, struct roc_bphy_irq_usr_data)
 #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ  _IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
 #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
 
@@ -187,6 +199,115 @@ roc_bphy_irq_stack_get(int cpu)
return NULL;
 }
 
+void
+roc_bphy_intr_handler(unsigned int irq_num)
+{
+   struct roc_bphy_irq_chip *irq_chip;
+   const struct plt_memzone *mz;
+
+   mz = plt_memzone_lookup(ROC_BPHY_MEMZONE_NAME);
+   if (mz == NULL)
+   return;
+
+   irq_chip = *(struct roc_bphy_irq_chip **)mz->addr;
+   if (irq_chip == NULL)
+   return;
+
+   if (irq_chip->irq_vecs[irq_num].handler != NULL)
+   irq_chip->irq_vecs[irq_num].handler(
+   (int)irq_num, irq_chip->irq_vecs[irq_num].isr_data);
+
+   roc_atf_ret();
+}
+
+int
+roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num,
+void (*isr)(int irq_num, void *isr_data),
+void *isr_data)
+{
+   roc_cpuset_t orig_cpuset, intr_cpuset;
+   struct roc_bphy_irq_usr_data irq_usr;
+   const struct plt_memzone *mz;
+   int i, retval, curr_cpu, rc;
+   char *env;
+
+   mz = plt_memzone_lookup(chip->mz_name);
+   if (mz == NULL) {
+   /* what we want is just a pointer to chip, not object itself */
+   mz = plt_memzone_reserve_cache_align(chip->mz_name,
+sizeof(chip));
+   if (mz == NULL)
+   return -ENOMEM;
+   }
+
+   if (chip->irq_vecs[irq_num].handler != NULL)
+   return -EINVAL;
+
+   rc = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
+   &orig_cpuset);
+   if (rc < 0) {
+   plt_err("Failed to get affinity mask");
+   return rc;
+   }
+
+   for (curr_cpu = -1, i = 0; i < CPU_SETSIZE; i++)
+   if (CPU_ISSET(i, &orig_cpuset))
+   curr_cpu = i;
+   if (curr_cpu < 0)
+   return -ENOENT;
+
+   CPU_ZERO(&intr_cpuset);
+   CPU_SET(curr_cpu, &intr_cpuset);
+   retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
+   &intr_cpuset);
+   if (rc < 0) {
+   plt_err("Failed to set affinity mask");
+   return rc;
+   }
+
+   irq_usr.isr_base = (uint64_t)roc_bphy_intr_handler;
+   irq_usr.sp = (uint64_t)roc_bphy_irq_stack_get(curr_cpu);
+   irq_usr.cpu = curr_cpu;
+   if (irq_usr.sp == 0) {
+   rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+   &orig_cpuset);
+   if (rc < 0)
+   plt_err("Failed to restore affinity mask");
+   return rc;
+   }
+
+   /* On simulator memory locking operation takes much time. We want
+* to skip this when running in such an environment.
+*/
+   env = getenv("BPHY_INTR_MLOCK_DISABLE");
+   if (env == NULL) {
+   rc = mlockall(MCL_CURRENT | MCL_FUTURE);
+   if (rc < 0)
+   plt_warn("Failed to lock memory into RAM");
+   }
+
+   *((struct roc_bphy_irq_chip **)(mz->addr)) = chip;
+   irq_usr.irq_num = irq_num;
+   chip->irq_vecs[irq_num].handler_cpu = curr_cpu;
+   chip->irq_vecs[irq_num].handler = isr;
+   chip->irq_vecs[irq_num].isr_data = isr_data;
+   retval = ioctl(chip->intfd, ROC_BPHY_IOC_SET_BPHY_HANDLER, &irq_usr);
+   if (retval != 0) {
+   roc_bphy_irq_stack_remove(curr_cpu);
+

[dpdk-dev] [PATCH 21/28] common/cnxk: add support for clearing bphy irq handler

Add support for clearing previously register baseband phy irq handler.

Signed-off-by: Jakub Palider 
Signed-off-by: Tomasz Duszynski 
---
 drivers/common/cnxk/roc_bphy_irq.c | 66 ++
 drivers/common/cnxk/roc_bphy_irq.h |  2 +
 drivers/common/cnxk/version.map|  1 +
 3 files changed, 69 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c 
b/drivers/common/cnxk/roc_bphy_irq.c
index f988abf51..4b87fc801 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -33,6 +33,7 @@ struct roc_bphy_irq_stack {
 #define ROC_BPHY_IOC_MAGIC 0xF3
 #define ROC_BPHY_IOC_SET_BPHY_HANDLER  
\
_IOW(ROC_BPHY_IOC_MAGIC, 1, struct roc_bphy_irq_usr_data)
+#define ROC_BPHY_IOC_CLR_BPHY_HANDLER  _IO(ROC_BPHY_IOC_MAGIC, 2)
 #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ  _IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
 #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
 
@@ -316,3 +317,68 @@ roc_bphy_intr_available(struct roc_bphy_irq_chip 
*irq_chip, int irq_num)
 
return irq_chip->avail_irq_bmask & BIT(irq_num);
 }
+
+int
+roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, int irq_num)
+{
+   roc_cpuset_t orig_cpuset, intr_cpuset;
+   const struct plt_memzone *mz;
+   int retval;
+
+   if (chip == NULL)
+   return -EINVAL;
+   if ((uint64_t)irq_num >= chip->max_irq || irq_num < 0)
+   return -EINVAL;
+   if (!roc_bphy_intr_available(chip, irq_num))
+   return -ENOTSUP;
+   if (chip->irq_vecs[irq_num].handler == NULL)
+   return -EINVAL;
+   mz = plt_memzone_lookup(chip->mz_name);
+   if (mz == NULL)
+   return -ENXIO;
+
+   retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
+   &orig_cpuset);
+   if (retval < 0) {
+   plt_warn("Failed to get affinity mask");
+   CPU_ZERO(&orig_cpuset);
+   CPU_SET(0, &orig_cpuset);
+   }
+
+   CPU_ZERO(&intr_cpuset);
+   CPU_SET(chip->irq_vecs[irq_num].handler_cpu, &intr_cpuset);
+   retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
+   &intr_cpuset);
+   if (retval < 0) {
+   plt_warn("Failed to set affinity mask");
+   CPU_ZERO(&orig_cpuset);
+   CPU_SET(0, &orig_cpuset);
+   }
+
+   retval = ioctl(chip->intfd, ROC_BPHY_IOC_CLR_BPHY_HANDLER, irq_num);
+   if (retval == 0) {
+   roc_bphy_irq_stack_remove(chip->irq_vecs[irq_num].handler_cpu);
+   chip->n_handlers--;
+   chip->irq_vecs[irq_num].isr_data = NULL;
+   chip->irq_vecs[irq_num].handler = NULL;
+   chip->irq_vecs[irq_num].handler_cpu = -1;
+   if (chip->n_handlers == 0) {
+   retval = plt_memzone_free(mz);
+   if (retval < 0)
+   plt_err("Failed to free memzone: irq %d",
+   irq_num);
+   }
+   } else {
+   plt_err("Failed to clear bphy interrupt handler");
+   }
+
+   retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+   &orig_cpuset);
+   if (retval < 0) {
+   plt_warn("Failed to restore affinity mask");
+   CPU_ZERO(&orig_cpuset);
+   CPU_SET(0, &orig_cpuset);
+   }
+
+   return retval;
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h 
b/drivers/common/cnxk/roc_bphy_irq.h
index 7dd23f4ab..778764f68 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -32,5 +32,7 @@ roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int 
irq_num,
 void *isr_data);
 __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
   int irq_num);
+__roc_api int roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip,
+int irq_num);
 
 #endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 861a97cc0..941055ba0 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -22,6 +22,7 @@ INTERNAL {
roc_bphy_cgx_stop_rxtx;
roc_bphy_dev_fini;
roc_bphy_dev_init;
+   roc_bphy_handler_clear;
roc_bphy_intr_available;
roc_bphy_intr_fini;
roc_bphy_intr_handler;
-- 
2.25.1

[dpdk-dev] [PATCH 23/28] raw/cnxk_bphy: add baseband phy skeleton driver

Add baseband phy sekelton driver. Baseband phy is a hardware subsystem
accelerating 5G/LTE related tasks.

Signed-off-by: Jakub Palider 
Signed-off-by: Tomasz Duszynski 
---
 doc/guides/rawdevs/cnxk_bphy.rst  |  14 +++-
 drivers/raw/cnxk_bphy/cnxk_bphy.c | 113 ++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h |  23 ++
 drivers/raw/cnxk_bphy/meson.build |   1 +
 usertools/dpdk-devbind.py |   4 +-
 5 files changed, 153 insertions(+), 2 deletions(-)
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 1b117a0e8..4e7f18c2a 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -17,6 +17,8 @@ Features
 The BPHY CGX/RPM implements following features in the rawdev API:
 
 - Access to BPHY CGX/RPM via set of predefined messages.
+- Access to BPHY memory
+- Custom interrupt handlers
 
 Device Setup
 
@@ -33,6 +35,16 @@ To perform data transfer use standard 
``rte_rawdev_enqueue_buffers()`` and
 ``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible
 responses hence dequeueing is not always necessary.
 
+Other features are realized by custom API calls:
+
+- BPHY memory ranges are obtained with single ``rte_pmd_bphy_intr_mem_get()``,
+- interrupt  initialization, registration, unregistration and termination are
+  done with ``rte_pmd_bphy_intr_init()``, ``rte_pmd_bphy_intr_register()``,
+  ``rte_pmd_bphy_intr_unregister()`` and ``rte_pmd_bphy_intr_fini()``,
+  respectively. In order to register an interrupt prior initialization is
+  required. The same way, the subsystem should be terminated when no longer
+  used.
+
 Self test
 -
 
@@ -40,7 +52,7 @@ On EAL initialization, BPHY CGX/RPM devices will be probed 
and populated into
 the raw devices. The rawdev ID of the device can be obtained using invocation
 of ``rte_rawdev_get_dev_id("NAME:x")`` from the test application, where:
 
-- NAME is the desired subsystem: use "BPHY_CGX" for
+- NAME is the desired subsystem: use "BPHY" for regular, and "BPHY_CGX" for
   RFOE module,
 - x is the device's bus id specified in "bus:device.func" (BDF) format.
 
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c 
b/drivers/raw/cnxk_bphy/cnxk_bphy.c
new file mode 100644
index 0..51affed78
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell International Ltd.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "cnxk_bphy_irq.h"
+
+static const struct rte_pci_id pci_bphy_map[] = {
+   {RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_BPHY)},
+   {
+   .vendor_id = 0,
+   },
+};
+
+static const struct rte_rawdev_ops bphy_rawdev_ops = {
+};
+
+static void
+bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev)
+{
+   snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "BPHY:%x:%02x.%x",
+pci_dev->addr.bus, pci_dev->addr.devid,
+pci_dev->addr.function);
+}
+
+static int
+bphy_rawdev_probe(struct rte_pci_driver *pci_drv,
+ struct rte_pci_device *pci_dev)
+{
+   struct bphy_device *bphy_dev = NULL;
+   char name[RTE_RAWDEV_NAME_MAX_LEN];
+   struct rte_rawdev *bphy_rawdev;
+   int ret;
+
+   RTE_SET_USED(pci_drv);
+
+   if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+   return 0;
+
+   if (!pci_dev->mem_resource[0].addr) {
+   plt_err("BARs have invalid values: BAR0 %p\n BAR2 %p",
+   pci_dev->mem_resource[0].addr,
+   pci_dev->mem_resource[2].addr);
+   return -ENODEV;
+   }
+
+   ret = roc_plt_init();
+   if (ret)
+   return ret;
+
+   bphy_rawdev_get_name(name, pci_dev);
+   bphy_rawdev = rte_rawdev_pmd_allocate(name, sizeof(*bphy_dev),
+ rte_socket_id());
+   if (bphy_rawdev == NULL) {
+   plt_err("Failed to allocate rawdev");
+   return -ENOMEM;
+   }
+
+   bphy_rawdev->dev_ops = &bphy_rawdev_ops;
+   bphy_rawdev->device = &pci_dev->device;
+   bphy_rawdev->driver_name = pci_dev->driver->driver.name;
+
+   bphy_dev = (struct bphy_device *)bphy_rawdev->dev_private;
+   bphy_dev->mem.res0 = pci_dev->mem_resource[0];
+   bphy_dev->mem.res2 = pci_dev->mem_resource[2];
+
+   return 0;
+}
+
+static int
+bphy_rawdev_remove(struct rte_pci_device *pci_dev)
+{
+   char name[RTE_RAWDEV_NAME_MAX_LEN];
+   struct rte_rawdev *rawdev;
+
+   if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+   return 0;
+
+   if (pci_dev == NULL) {
+   plt_err("invalid pci_dev");
+   return -EINVAL;
+   }
+
+   rawdev = rte_rawdev_p

[dpdk-dev] [PATCH 22/28] common/cnxk: add support for registering bphy irq

Add support for registering user supplied baseband phy irq handler.

Signed-off-by: Jakib Palider 
Signed-off-by: Tomasz Duszynski 
---
 drivers/common/cnxk/roc_bphy_irq.c | 38 ++
 drivers/common/cnxk/roc_bphy_irq.h | 11 +
 drivers/common/cnxk/version.map|  1 +
 3 files changed, 50 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c 
b/drivers/common/cnxk/roc_bphy_irq.c
index 4b87fc801..882066ef3 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -382,3 +382,41 @@ roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, int 
irq_num)
 
return retval;
 }
+
+int
+roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip,
+  struct roc_bphy_intr *intr)
+{
+   roc_cpuset_t orig_cpuset, intr_cpuset;
+   int retval;
+   int ret;
+
+   if (!roc_bphy_intr_available(irq_chip, intr->irq_num))
+   return -ENOTSUP;
+
+   retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
+   &orig_cpuset);
+   if (retval < 0) {
+   plt_err("Failed to get affinity mask");
+   return retval;
+   }
+
+   CPU_ZERO(&intr_cpuset);
+   CPU_SET(intr->cpu, &intr_cpuset);
+   retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
+   &intr_cpuset);
+   if (retval < 0) {
+   plt_err("Failed to set affinity mask");
+   return retval;
+   }
+
+   ret = roc_bphy_irq_handler_set(irq_chip, intr->irq_num,
+  intr->intr_handler, intr->isr_data);
+
+   retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+   &orig_cpuset);
+   if (retval < 0)
+   plt_warn("Failed to restore affinity mask");
+
+   return ret;
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h 
b/drivers/common/cnxk/roc_bphy_irq.h
index 778764f68..19ec5fdc4 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -21,6 +21,15 @@ struct roc_bphy_irq_chip {
char *mz_name;
 };
 
+struct roc_bphy_intr {
+   int irq_num;
+   void (*intr_handler)(int irq_num, void *isr_data);
+   void *isr_data;
+   int cpu;
+   /* stack for this interrupt, not supplied by a user */
+   uint8_t *sp;
+};
+
 __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
 __roc_api void roc_bphy_irq_stack_remove(int cpu);
@@ -34,5 +43,7 @@ __roc_api bool roc_bphy_intr_available(struct 
roc_bphy_irq_chip *irq_chip,
   int irq_num);
 __roc_api int roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip,
 int irq_num);
+__roc_api int roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip,
+struct roc_bphy_intr *intr);
 
 #endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 941055ba0..e24766c05 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -27,6 +27,7 @@ INTERNAL {
roc_bphy_intr_fini;
roc_bphy_intr_handler;
roc_bphy_intr_init;
+   roc_bphy_intr_register;
roc_bphy_irq_handler_set;
roc_bphy_irq_stack_get;
roc_bphy_irq_stack_remove;
-- 
2.25.1

[dpdk-dev] [PATCH 24/28] raw/cnxk_bphy: add support for interrupt init and cleanup

Add support for interrupt initialization and cleanup. Internally
interrupt initialization performs low level setup that allows
custom interrupt handler registration later on.

Interrupt initialization and cleanup are related hence they
are in the same patch.

Signed-off-by: Jakub Palider 
Signed-off-by: Tomasz Duszynski 
---
 drivers/raw/cnxk_bphy/cnxk_bphy.c | 13 
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 47 +++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h |  5 +++
 drivers/raw/cnxk_bphy/meson.build |  1 +
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  |  7 
 drivers/raw/cnxk_bphy/version.map | 12 +++
 6 files changed, 85 insertions(+)
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c 
b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 51affed78..e3a065b30 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -13,6 +13,7 @@
 #include 
 
 #include "cnxk_bphy_irq.h"
+#include "rte_pmd_bphy.h"
 
 static const struct rte_pci_id pci_bphy_map[] = {
{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_BPHY)},
@@ -21,6 +22,18 @@ static const struct rte_pci_id pci_bphy_map[] = {
},
 };
 
+int
+rte_pmd_bphy_intr_init(uint16_t dev_id)
+{
+   return cnxk_bphy_intr_init(dev_id);
+}
+
+void
+rte_pmd_bphy_intr_fini(uint16_t dev_id)
+{
+   return cnxk_bphy_intr_fini(dev_id);
+}
+
 static const struct rte_rawdev_ops bphy_rawdev_ops = {
 };
 
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c 
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
new file mode 100644
index 0..5d47840d6
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell International Ltd.
+ */
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include "cnxk_bphy_irq.h"
+
+static struct bphy_device *
+cnxk_bphy_get_bphy_dev_by_dev_id(uint16_t dev_id)
+{
+   struct rte_rawdev *rawdev;
+
+   if (!rte_rawdev_pmd_is_valid_dev(dev_id))
+   return NULL;
+
+   rawdev = &rte_rawdevs[dev_id];
+
+   return (struct bphy_device *)rawdev->dev_private;
+}
+
+int
+cnxk_bphy_intr_init(uint16_t dev_id)
+{
+   struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+
+   bphy_dev->irq_chip = roc_bphy_intr_init();
+   if (bphy_dev->irq_chip == NULL)
+   return -ENOMEM;
+
+   return 0;
+}
+
+void
+cnxk_bphy_intr_fini(uint16_t dev_id)
+{
+   struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+   struct roc_bphy_irq_chip *irq_chip = bphy_dev->irq_chip;
+
+   roc_bphy_intr_fini(irq_chip);
+   bphy_dev->irq_chip = NULL;
+}
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h 
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 77169b1b7..6e3d77768 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -20,4 +20,9 @@ struct bphy_device {
struct bphy_mem mem;
 };
 
+__rte_internal
+int cnxk_bphy_intr_init(uint16_t dev_id);
+__rte_internal
+void cnxk_bphy_intr_fini(uint16_t dev_id);
+
 #endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/meson.build 
b/drivers/raw/cnxk_bphy/meson.build
index 23d46f11d..1c3e6c1b7 100644
--- a/drivers/raw/cnxk_bphy/meson.build
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -6,6 +6,7 @@ deps += ['bus_pci', 'common_cnxk', 'rawdev']
 sources = files(
 'cnxk_bphy.c',
 'cnxk_bphy_cgx.c',
+'cnxk_bphy_irq.c',
 'cnxk_bphy_cgx_test.c'
 )
 headers = files('rte_pmd_bphy.h')
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h 
b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index 84176ff22..edc146685 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -5,6 +5,8 @@
 #ifndef _CNXK_BPHY_H_
 #define _CNXK_BPHY_H_
 
+#include "cnxk_bphy_irq.h"
+
 enum cnxk_bphy_cgx_msg_type {
CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,
CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,
@@ -101,4 +103,9 @@ struct cnxk_bphy_cgx_msg {
void *data;
 };
 
+__rte_experimental
+int rte_pmd_bphy_intr_init(uint16_t dev_id);
+__rte_experimental
+void rte_pmd_bphy_intr_fini(uint16_t dev_id);
+
 #endif /* _CNXK_BPHY_H_ */
diff --git a/drivers/raw/cnxk_bphy/version.map 
b/drivers/raw/cnxk_bphy/version.map
index 4a76d1d52..e087cd39b 100644
--- a/drivers/raw/cnxk_bphy/version.map
+++ b/drivers/raw/cnxk_bphy/version.map
@@ -1,3 +1,15 @@
 DPDK_21 {
local: *;
 };
+INTERNAL {
+   global:
+
+   cnxk_bphy_intr_init;
+   cnxk_bphy_intr_fini;
+};
+EXPERIMENTAL {
+   global:
+
+   rte_pmd_bphy_intr_fini;
+   rte_pmd_bphy_intr_init;
+};
-- 
2.25.1

[dpdk-dev] [PATCH 25/28] raw/cnxk_bphy: add support for reading number of irqs

Add support for retrieving maximum number of interrupts.

Signed-off-by: Jakub Palider 
Signed-off-by: Tomasz Duszynski 
---
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 12 
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h |  2 ++
 drivers/raw/cnxk_bphy/version.map |  1 +
 3 files changed, 15 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c 
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
index 5d47840d6..6a68db8a9 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -24,6 +24,18 @@ cnxk_bphy_get_bphy_dev_by_dev_id(uint16_t dev_id)
return (struct bphy_device *)rawdev->dev_private;
 }
 
+uint64_t
+cnxk_bphy_irq_max_get(uint16_t dev_id)
+{
+   struct roc_bphy_irq_chip *irq_chip;
+   struct bphy_device *bphy_dev;
+
+   bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+   irq_chip = bphy_dev->irq_chip;
+
+   return irq_chip->max_irq;
+}
+
 int
 cnxk_bphy_intr_init(uint16_t dev_id)
 {
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h 
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 6e3d77768..d18fbd69e 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -24,5 +24,7 @@ __rte_internal
 int cnxk_bphy_intr_init(uint16_t dev_id);
 __rte_internal
 void cnxk_bphy_intr_fini(uint16_t dev_id);
+__rte_internal
+uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id);
 
 #endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/version.map 
b/drivers/raw/cnxk_bphy/version.map
index e087cd39b..6c5e9639a 100644
--- a/drivers/raw/cnxk_bphy/version.map
+++ b/drivers/raw/cnxk_bphy/version.map
@@ -6,6 +6,7 @@ INTERNAL {
 
cnxk_bphy_intr_init;
cnxk_bphy_intr_fini;
+   cnxk_bphy_irq_max_get;
 };
 EXPERIMENTAL {
global:
-- 
2.25.1

[dpdk-dev] [PATCH 26/28] raw/cnxk_bphy: add support for retrieving device memory

Allow user to retrieve bphy memory resources.

Signed-off-by: Jakub Palider 
Signed-off-by: Tomasz Duszynski 
---
 drivers/raw/cnxk_bphy/cnxk_bphy.c | 6 ++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 8 
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 2 ++
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  | 4 
 drivers/raw/cnxk_bphy/version.map | 2 ++
 5 files changed, 22 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c 
b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index e3a065b30..c3aed3018 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -34,6 +34,12 @@ rte_pmd_bphy_intr_fini(uint16_t dev_id)
return cnxk_bphy_intr_fini(dev_id);
 }
 
+struct cnxk_bphy_mem *
+rte_pmd_bphy_intr_mem_get(uint16_t dev_id)
+{
+   return cnxk_bphy_mem_get(dev_id);
+}
+
 static const struct rte_rawdev_ops bphy_rawdev_ops = {
 };
 
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c 
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
index 6a68db8a9..5a7698f23 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -57,3 +57,11 @@ cnxk_bphy_intr_fini(uint16_t dev_id)
roc_bphy_intr_fini(irq_chip);
bphy_dev->irq_chip = NULL;
 }
+
+struct bphy_mem *
+cnxk_bphy_mem_get(uint16_t dev_id)
+{
+   struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+
+   return &bphy_dev->mem;
+}
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h 
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index d18fbd69e..e52106bc8 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -26,5 +26,7 @@ __rte_internal
 void cnxk_bphy_intr_fini(uint16_t dev_id);
 __rte_internal
 uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id);
+__rte_internal
+struct bphy_mem *cnxk_bphy_mem_get(uint16_t dev_id);
 
 #endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h 
b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index edc146685..783b63471 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -103,9 +103,13 @@ struct cnxk_bphy_cgx_msg {
void *data;
 };
 
+#define cnxk_bphy_mem  bphy_mem
+
 __rte_experimental
 int rte_pmd_bphy_intr_init(uint16_t dev_id);
 __rte_experimental
+struct cnxk_bphy_mem *rte_pmd_bphy_intr_mem_get(uint16_t dev_id);
+__rte_experimental
 void rte_pmd_bphy_intr_fini(uint16_t dev_id);
 
 #endif /* _CNXK_BPHY_H_ */
diff --git a/drivers/raw/cnxk_bphy/version.map 
b/drivers/raw/cnxk_bphy/version.map
index 6c5e9639a..c7600a863 100644
--- a/drivers/raw/cnxk_bphy/version.map
+++ b/drivers/raw/cnxk_bphy/version.map
@@ -7,10 +7,12 @@ INTERNAL {
cnxk_bphy_intr_init;
cnxk_bphy_intr_fini;
cnxk_bphy_irq_max_get;
+   cnxk_bphy_mem_get;
 };
 EXPERIMENTAL {
global:
 
rte_pmd_bphy_intr_fini;
rte_pmd_bphy_intr_init;
+   rte_pmd_bphy_intr_mem_get;
 };
-- 
2.25.1

[dpdk-dev] [PATCH 28/28] raw/cnxk_bphy: add support for selftest

Add support for performing selftest.

Signed-off-by: Jakub Palider 
Signed-off-by: Tomasz Duszynski 
---
 drivers/raw/cnxk_bphy/cnxk_bphy.c | 104 ++
 1 file changed, 104 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c 
b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index a6bbdd986..640405242 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -11,6 +11,7 @@
 #include 
 
 #include 
+#include 
 
 #include "cnxk_bphy_irq.h"
 #include "rte_pmd_bphy.h"
@@ -22,6 +23,25 @@ static const struct rte_pci_id pci_bphy_map[] = {
},
 };
 
+struct bphy_test {
+   int irq_num;
+   cnxk_bphy_intr_handler_t handler;
+   void *data;
+   int cpu;
+   bool handled_intr;
+   int handled_data;
+   int test_data;
+};
+
+static struct bphy_test *test;
+
+static void
+bphy_test_handler_fn(int irq_num, void *isr_data)
+{
+   test[irq_num].handled_intr = true;
+   test[irq_num].handled_data = *((int *)isr_data);
+}
+
 int
 rte_pmd_bphy_intr_init(uint16_t dev_id)
 {
@@ -54,7 +74,91 @@ rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num)
cnxk_bphy_intr_unregister(dev_id, irq_num);
 }
 
+static int
+bphy_rawdev_selftest(uint16_t dev_id)
+{
+   unsigned int i;
+   uint64_t max_irq;
+   int ret = 0;
+
+   ret = rte_pmd_bphy_intr_init(dev_id);
+   if (ret) {
+   plt_err("intr init failed");
+   return ret;
+   }
+
+   max_irq = cnxk_bphy_irq_max_get(dev_id);
+
+   test = rte_zmalloc("BPHY", max_irq * sizeof(*test), 0);
+   if (test == NULL) {
+   plt_err("intr alloc failed");
+   goto err_alloc;
+   }
+
+   for (i = 0; i < max_irq; i++) {
+   test[i].test_data = i;
+   test[i].irq_num = i;
+   test[i].handler = bphy_test_handler_fn;
+   test[i].data = &test[i].test_data;
+   }
+
+   for (i = 0; i < max_irq; i++) {
+   ret = rte_pmd_bphy_intr_register(dev_id, test[i].irq_num,
+ test[i].handler, test[i].data,
+ 0);
+   if (ret == -ENOTSUP) {
+   /* In the test we iterate over all irq numbers
+* so if some of them are not supported by given
+* platform we treat respective results as valid
+* ones. This way they have no impact on overall
+* test results.
+*/
+   test[i].handled_intr = true;
+   test[i].handled_data = test[i].test_data;
+   ret = 0;
+   continue;
+   }
+
+   if (ret) {
+   plt_err("intr register failed at irq %d", i);
+   goto err_register;
+   }
+   }
+
+   for (i = 0; i < max_irq; i++)
+   roc_bphy_intr_handler(i);
+
+   for (i = 0; i < max_irq; i++) {
+   if (!test[i].handled_intr) {
+   plt_err("intr %u not handled", i);
+   ret = -1;
+   break;
+   }
+   if (test[i].handled_data != test[i].test_data) {
+   plt_err("intr %u has wrong handler", i);
+   ret = -1;
+   break;
+   }
+   }
+
+err_register:
+   /*
+* In case of registration failure the loop goes over all
+* interrupts which is safe due to internal guards in
+* rte_pmd_bphy_intr_unregister().
+*/
+   for (i = 0; i < max_irq; i++)
+   rte_pmd_bphy_intr_unregister(dev_id, i);
+
+   rte_free(test);
+err_alloc:
+   rte_pmd_bphy_intr_fini(dev_id);
+
+   return ret;
+}
+
 static const struct rte_rawdev_ops bphy_rawdev_ops = {
+   .dev_selftest = bphy_rawdev_selftest,
 };
 
 static void
-- 
2.25.1

[dpdk-dev] [PATCH 27/28] raw/cnxk_bphy: add support for registering irq handlers

Custom irq handlers may be registered/removed on demand.
This adds support for doing that. Since registration
and removal are related they are in the same patch.

Signed-off-by: Jakub Palider 
Signed-off-by: Tomasz Duszynski 
---
 drivers/raw/cnxk_bphy/cnxk_bphy.c | 14 
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 33 +++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 12 --
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  |  6 +
 drivers/raw/cnxk_bphy/version.map |  4 
 5 files changed, 67 insertions(+), 2 deletions(-)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c 
b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index c3aed3018..a6bbdd986 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -40,6 +40,20 @@ rte_pmd_bphy_intr_mem_get(uint16_t dev_id)
return cnxk_bphy_mem_get(dev_id);
 }
 
+int
+rte_pmd_bphy_intr_register(uint16_t dev_id, int irq_num,
+   cnxk_bphy_intr_handler_t handler, void *data,
+   int cpu)
+{
+   return cnxk_bphy_intr_register(dev_id, irq_num, handler, data, cpu);
+}
+
+void
+rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num)
+{
+   cnxk_bphy_intr_unregister(dev_id, irq_num);
+}
+
 static const struct rte_rawdev_ops bphy_rawdev_ops = {
 };
 
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c 
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
index 5a7698f23..45aada7bf 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -58,6 +58,39 @@ cnxk_bphy_intr_fini(uint16_t dev_id)
bphy_dev->irq_chip = NULL;
 }
 
+int
+cnxk_bphy_intr_register(uint16_t dev_id, int irq_num,
+   cnxk_bphy_intr_handler_t handler, void *data, int cpu)
+{
+   struct roc_bphy_intr intr = {
+   .irq_num = irq_num,
+   .intr_handler = handler,
+   .isr_data = data,
+   .cpu = cpu
+   };
+
+   struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+   struct roc_bphy_irq_chip *irq_chip = bphy_dev->irq_chip;
+
+   if (!irq_chip)
+   return -ENODEV;
+   if (!handler || !data)
+   return -EINVAL;
+
+   return roc_bphy_intr_register(irq_chip, &intr);
+}
+
+void
+cnxk_bphy_intr_unregister(uint16_t dev_id, int irq_num)
+{
+   struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+
+   if (bphy_dev->irq_chip)
+   roc_bphy_handler_clear(bphy_dev->irq_chip, irq_num);
+   else
+   plt_err("Missing irq chip");
+}
+
 struct bphy_mem *
 cnxk_bphy_mem_get(uint16_t dev_id)
 {
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h 
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index e52106bc8..6eeb567ed 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -10,6 +10,8 @@
 
 #include 
 
+typedef void (*cnxk_bphy_intr_handler_t)(int irq_num, void *isr_data);
+
 struct bphy_mem {
struct rte_mem_resource res0;
struct rte_mem_resource res2;
@@ -25,8 +27,14 @@ int cnxk_bphy_intr_init(uint16_t dev_id);
 __rte_internal
 void cnxk_bphy_intr_fini(uint16_t dev_id);
 __rte_internal
-uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id);
-__rte_internal
 struct bphy_mem *cnxk_bphy_mem_get(uint16_t dev_id);
+__rte_internal
+int cnxk_bphy_intr_register(uint16_t dev_id, int irq_num,
+   cnxk_bphy_intr_handler_t handler, void *isr_data,
+   int cpu);
+__rte_internal
+void cnxk_bphy_intr_unregister(uint16_t dev_id, int irq_num);
+__rte_internal
+uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id);
 
 #endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h 
b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index 783b63471..d77bb3b23 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -110,6 +110,12 @@ int rte_pmd_bphy_intr_init(uint16_t dev_id);
 __rte_experimental
 struct cnxk_bphy_mem *rte_pmd_bphy_intr_mem_get(uint16_t dev_id);
 __rte_experimental
+int rte_pmd_bphy_intr_register(uint16_t dev_id, int irq_num,
+  cnxk_bphy_intr_handler_t handler, void *isr_data,
+  int cpu);
+__rte_experimental
 void rte_pmd_bphy_intr_fini(uint16_t dev_id);
+__rte_experimental
+void rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num);
 
 #endif /* _CNXK_BPHY_H_ */
diff --git a/drivers/raw/cnxk_bphy/version.map 
b/drivers/raw/cnxk_bphy/version.map
index c7600a863..c4f9b20d0 100644
--- a/drivers/raw/cnxk_bphy/version.map
+++ b/drivers/raw/cnxk_bphy/version.map
@@ -6,6 +6,8 @@ INTERNAL {
 
cnxk_bphy_intr_init;
cnxk_bphy_intr_fini;
+   cnxk_bphy_intr_register;
+   cnxk_bphy_intr_unregister;
cnxk_bphy_irq_max_get;
cnxk_bphy_mem_get;
 };
@@ -15,4 +17,6 @@ EXPERIMENTAL {
rte_pmd_bphy_intr_fini;
rte_pmd_bphy_intr_init;
rte_pmd_bphy_intr_mem_get;
+

[dpdk-dev] [PATCH v1 0/5] Enable ETS-based Tx QoS for VF in DCF

This patch enables the ETS-based Tx QoS for IAVF. Kernel tool is used to
configure ETS first. DCF is used to set bandwidth limit for VFs of each
TC. IAVF is supported to query QoS capability and set queue TC mapping.
Traffic Management API is utilized to configure the QoS hierarchy
scheduler tree. The scheduler tree will be passed to hardware to enable
all above functions.

Ting Xu (5):
  common/iavf: add support for ETS-based Tx QoS
  net/ice/base: support DCF query port ETS adminq
  net/ice: support DCF link status event handling
  net/ice: support QoS config VF bandwidth in DCF
  net/iavf: query QoS cap and set queue TC mapping

 drivers/common/iavf/iavf_type.h  |   2 +
 drivers/common/iavf/virtchnl.h   | 117 ++
 drivers/net/iavf/iavf.h  |  45 +++
 drivers/net/iavf/iavf_ethdev.c   |  31 ++
 drivers/net/iavf/iavf_tm.c   | 675 +++
 drivers/net/iavf/iavf_vchnl.c|  56 ++-
 drivers/net/iavf/meson.build |   1 +
 drivers/net/ice/base/ice_dcb.c   |   3 +-
 drivers/net/ice/ice_dcf.c|   6 +-
 drivers/net/ice/ice_dcf.h|  53 +++
 drivers/net/ice/ice_dcf_ethdev.c |  67 ++-
 drivers/net/ice/ice_dcf_ethdev.h |   3 +
 drivers/net/ice/ice_dcf_parent.c |  81 
 drivers/net/ice/ice_dcf_sched.c  | 604 +++
 drivers/net/ice/meson.build  |   3 +-
 15 files changed, 1740 insertions(+), 7 deletions(-)
 create mode 100644 drivers/net/iavf/iavf_tm.c
 create mode 100644 drivers/net/ice/ice_dcf_sched.c

-- 
2.17.1

[dpdk-dev] [PATCH v1 1/5] common/iavf: add support for ETS-based Tx QoS

This patch adds support to configure ETS-based Tx QoS. Three parts of
new virtchnl structures and opcodes are added to achieve:
1. Configure VF TC bandwidth limits.
2. VF queries current QoS configuration from PF.
3. Set up VF queue TC mapping.

Signed-off-by: Ting Xu 
---
 drivers/common/iavf/iavf_type.h |   2 +
 drivers/common/iavf/virtchnl.h  | 117 
 2 files changed, 119 insertions(+)

diff --git a/drivers/common/iavf/iavf_type.h b/drivers/common/iavf/iavf_type.h
index f3815d523b..73dfb47e70 100644
--- a/drivers/common/iavf/iavf_type.h
+++ b/drivers/common/iavf/iavf_type.h
@@ -141,6 +141,8 @@ enum iavf_debug_mask {
 #define IAVF_PHY_LED_MODE_MASK 0x
 #define IAVF_PHY_LED_MODE_ORIG 0x8000
 
+#define IAVF_MAX_TRAFFIC_CLASS 8
+
 /* Memory types */
 enum iavf_memset_type {
IAVF_NONDMA_MEM = 0,
diff --git a/drivers/common/iavf/virtchnl.h b/drivers/common/iavf/virtchnl.h
index 3a60faff93..a00cd76118 100644
--- a/drivers/common/iavf/virtchnl.h
+++ b/drivers/common/iavf/virtchnl.h
@@ -130,6 +130,7 @@ enum virtchnl_ops {
VIRTCHNL_OP_ADD_CLOUD_FILTER = 32,
VIRTCHNL_OP_DEL_CLOUD_FILTER = 33,
/* opcodes 34, 35, 36, and 37 are reserved */
+   VIRTCHNL_OP_DCF_CONFIG_VF_TC = 37,
VIRTCHNL_OP_DCF_VLAN_OFFLOAD = 38,
VIRTCHNL_OP_DCF_CMD_DESC = 39,
VIRTCHNL_OP_DCF_CMD_BUFF = 40,
@@ -152,6 +153,8 @@ enum virtchnl_ops {
VIRTCHNL_OP_DISABLE_VLAN_INSERTION_V2 = 57,
VIRTCHNL_OP_ENABLE_VLAN_FILTERING_V2 = 58,
VIRTCHNL_OP_DISABLE_VLAN_FILTERING_V2 = 59,
+   VIRTCHNL_OP_GET_QOS_CAPS = 66,
+   VIRTCHNL_OP_CONFIG_TC_MAP = 67,
VIRTCHNL_OP_ENABLE_QUEUES_V2 = 107,
VIRTCHNL_OP_DISABLE_QUEUES_V2 = 108,
VIRTCHNL_OP_MAP_QUEUE_VECTOR = 111,
@@ -398,6 +401,7 @@ VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_vsi_resource);
 #define VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC   BIT(26)
 #define VIRTCHNL_VF_OFFLOAD_ADV_RSS_PF BIT(27)
 #define VIRTCHNL_VF_OFFLOAD_FDIR_PFBIT(28)
+#define VIRTCHNL_VF_OFFLOAD_TC BIT(29)
 #define VIRTCHNL_VF_CAP_DCFBIT(30)
/* BIT(31) is reserved */
 
@@ -1786,6 +1790,91 @@ struct virtchnl_fdir_query {
 
 VIRTCHNL_CHECK_STRUCT_LEN(48, virtchnl_fdir_query);
 
+/* VIRTCHNL_OP_DCF_CONFIG_VF_TC
+ * VF send this message to set the configuration of each TC with a
+ * specific vf id.
+ */
+enum virtchnl_bw_limit_type {
+   VIRTCHNL_BW_SHAPER = 0,
+};
+
+struct virtchnl_shaper_bw {
+   u32 committed;
+   u32 peak;
+};
+VIRTCHNL_CHECK_STRUCT_LEN(8, virtchnl_shaper_bw);
+
+struct virtchnl_dcf_vf_bw_cfg {
+   u8 tc_id;
+   u8 pad[3];
+   enum virtchnl_bw_limit_type type;
+   union {
+   struct virtchnl_shaper_bw shaper;
+   u8 pad2[32];
+   };
+};
+VIRTCHNL_CHECK_STRUCT_LEN(40, virtchnl_dcf_vf_bw_cfg);
+
+struct virtchnl_dcf_vf_bw_cfg_list {
+   u16 vf_id;
+   u16 num_elem;
+   struct virtchnl_dcf_vf_bw_cfg cfg[1];
+};
+VIRTCHNL_CHECK_STRUCT_LEN(44, virtchnl_dcf_vf_bw_cfg_list);
+
+/* VIRTCHNL_OP_GET_QOS_CAPS
+ * VF sends this message to get its QoS Caps, such as
+ * TC number, Arbiter and Bandwidth.
+ */
+struct virtchnl_qos_cap_elem {
+   u8 tc_id;
+   u8 prio_of_tc;
+#define VIRTCHNL_ABITER_STRICT0
+#define VIRTCHNL_ABITER_ETS   2
+   u8 arbiter;
+   u8 weight;
+   enum virtchnl_bw_limit_type type;
+   union {
+   struct virtchnl_shaper_bw shaper;
+   u8 pad2[32];
+   };
+};
+VIRTCHNL_CHECK_STRUCT_LEN(40, virtchnl_qos_cap_elem);
+
+struct virtchnl_qos_cap_list {
+   u16 vsi_id;
+   u16 num_elem;
+   struct virtchnl_qos_cap_elem cap[1];
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(44, virtchnl_qos_cap_list);
+
+/* VIRTCHNL_OP_CONFIG_TC_MAP
+ * VF sends message virtchnl_queue_tc_mapping to set queue to tc
+ * mapping for all the Tx and Rx queues with a specified VSI, and
+ * would get response about bitmap of valid user priorities
+ * associated with queues.
+ */
+struct virtchnl_queue_tc_mapping {
+   u16 vsi_id;
+   u16 num_tc;
+   u16 num_queue_pairs;
+   u8 pad[2];
+   union {
+   struct {
+   u16 start_queue_id;
+   u16 queue_count;
+   } req;
+   struct {
+#define VIRTCHNL_USER_PRIO_TYPE_UP 0
+#define VIRTCHNL_USER_PRIO_TYPE_DSCP   1
+   u16 prio_type;
+   u16 valid_prio_bitmap;
+   } resp;
+   } tc[1];
+};
+VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_queue_tc_mapping);
+
 /* TX and RX queue types are valid in legacy as well as split queue models.
  * With Split Queue model, 2 additional types are introduced - TX_COMPLETION
  * and RX_BUFFER. In split queue model, RX corresponds to the queue where HW
@@ -2117,6 +2206,19 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info 
*ver, u32 v_opcode,
case VIRTCHNL_O

[dpdk-dev] [PATCH v1 2/5] net/ice/base: support DCF query port ETS adminq

In the adminq command query port ETS function, the root node teid is
needed. However, for DCF, the root node is not initialized, which will
cause error when we refer to the variable. In this patch, we will check
whether the root node is available or not first.

Signed-off-by: Ting Xu 
---
 drivers/net/ice/base/ice_dcb.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c
index 0aaa5ae8c1..08c950cd9a 100644
--- a/drivers/net/ice/base/ice_dcb.c
+++ b/drivers/net/ice/base/ice_dcb.c
@@ -1483,7 +1483,8 @@ ice_aq_query_port_ets(struct ice_port_info *pi,
return ICE_ERR_PARAM;
cmd = &desc.params.port_ets;
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_query_port_ets);
-   cmd->port_teid = pi->root->info.node_teid;
+   if (pi->root)
+   cmd->port_teid = pi->root->info.node_teid;
 
status = ice_aq_send_cmd(pi->hw, &desc, buf, buf_size, cd);
return status;
-- 
2.17.1

[dpdk-dev] [PATCH v1 3/5] net/ice: support DCF link status event handling

When link status changes, DCF will receive virtchnl PF event message.
Add support to handle this event, change link status and update link
info.

Signed-off-by: Ting Xu 
---
 drivers/net/ice/ice_dcf.h|  6 
 drivers/net/ice/ice_dcf_ethdev.c | 54 ++--
 drivers/net/ice/ice_dcf_parent.c | 51 ++
 3 files changed, 108 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ice/ice_dcf.h b/drivers/net/ice/ice_dcf.h
index 0cb90b5e9f..587093b909 100644
--- a/drivers/net/ice/ice_dcf.h
+++ b/drivers/net/ice/ice_dcf.h
@@ -60,6 +60,10 @@ struct ice_dcf_hw {
uint16_t nb_msix;
uint16_t rxq_map[16];
struct virtchnl_eth_stats eth_stats_offset;
+
+   /* Link status */
+   bool link_up;
+   uint32_t link_speed;
 };
 
 int ice_dcf_execute_virtchnl_cmd(struct ice_dcf_hw *hw,
@@ -77,5 +81,7 @@ int ice_dcf_disable_queues(struct ice_dcf_hw *hw);
 int ice_dcf_query_stats(struct ice_dcf_hw *hw,
struct virtchnl_eth_stats *pstats);
 int ice_dcf_add_del_all_mac_addr(struct ice_dcf_hw *hw, bool add);
+int ice_dcf_link_update(struct rte_eth_dev *dev,
+   __rte_unused int wait_to_complete);
 
 #endif /* _ICE_DCF_H_ */
diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c
index b937cbbb03..332ce340cf 100644
--- a/drivers/net/ice/ice_dcf_ethdev.c
+++ b/drivers/net/ice/ice_dcf_ethdev.c
@@ -880,11 +880,59 @@ ice_dcf_dev_close(struct rte_eth_dev *dev)
return 0;
 }
 
-static int
-ice_dcf_link_update(__rte_unused struct rte_eth_dev *dev,
+int
+ice_dcf_link_update(struct rte_eth_dev *dev,
__rte_unused int wait_to_complete)
 {
-   return 0;
+   struct ice_dcf_adapter *ad = dev->data->dev_private;
+   struct ice_dcf_hw *hw = &ad->real_hw;
+   struct rte_eth_link new_link;
+
+   memset(&new_link, 0, sizeof(new_link));
+
+   /* Only read status info stored in VF, and the info is updated
+*  when receive LINK_CHANGE evnet from PF by Virtchnnl.
+*/
+   switch (hw->link_speed) {
+   case 10:
+   new_link.link_speed = ETH_SPEED_NUM_10M;
+   break;
+   case 100:
+   new_link.link_speed = ETH_SPEED_NUM_100M;
+   break;
+   case 1000:
+   new_link.link_speed = ETH_SPEED_NUM_1G;
+   break;
+   case 1:
+   new_link.link_speed = ETH_SPEED_NUM_10G;
+   break;
+   case 2:
+   new_link.link_speed = ETH_SPEED_NUM_20G;
+   break;
+   case 25000:
+   new_link.link_speed = ETH_SPEED_NUM_25G;
+   break;
+   case 4:
+   new_link.link_speed = ETH_SPEED_NUM_40G;
+   break;
+   case 5:
+   new_link.link_speed = ETH_SPEED_NUM_50G;
+   break;
+   case 10:
+   new_link.link_speed = ETH_SPEED_NUM_100G;
+   break;
+   default:
+   new_link.link_speed = ETH_SPEED_NUM_NONE;
+   break;
+   }
+
+   new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
+   new_link.link_status = hw->link_up ? ETH_LINK_UP :
+ETH_LINK_DOWN;
+   new_link.link_autoneg = !(dev->data->dev_conf.link_speeds &
+   ETH_LINK_SPEED_FIXED);
+
+   return rte_eth_linkstatus_set(dev, &new_link);
 }
 
 /* Add UDP tunneling port */
diff --git a/drivers/net/ice/ice_dcf_parent.c b/drivers/net/ice/ice_dcf_parent.c
index 1d7aa8bc87..0c0706316d 100644
--- a/drivers/net/ice/ice_dcf_parent.c
+++ b/drivers/net/ice/ice_dcf_parent.c
@@ -178,6 +178,44 @@ start_vsi_reset_thread(struct ice_dcf_hw *dcf_hw, bool 
vfr, uint16_t vf_id)
}
 }
 
+static uint32_t
+ice_dcf_convert_link_speed(enum virtchnl_link_speed virt_link_speed)
+{
+   uint32_t speed;
+
+   switch (virt_link_speed) {
+   case VIRTCHNL_LINK_SPEED_100MB:
+   speed = 100;
+   break;
+   case VIRTCHNL_LINK_SPEED_1GB:
+   speed = 1000;
+   break;
+   case VIRTCHNL_LINK_SPEED_10GB:
+   speed = 1;
+   break;
+   case VIRTCHNL_LINK_SPEED_40GB:
+   speed = 4;
+   break;
+   case VIRTCHNL_LINK_SPEED_20GB:
+   speed = 2;
+   break;
+   case VIRTCHNL_LINK_SPEED_25GB:
+   speed = 25000;
+   break;
+   case VIRTCHNL_LINK_SPEED_2_5GB:
+   speed = 2500;
+   break;
+   case VIRTCHNL_LINK_SPEED_5GB:
+   speed = 5000;
+   break;
+   default:
+   speed = 0;
+   break;
+   }
+
+   return speed;
+}
+
 void
 ice_dcf_handle_pf_event_msg(struct ice_dcf_hw *dcf_hw,
uint8_t *msg, uint16_t msglen)
@@ -196,6 +234,19 @@ ice_dcf_handle_pf_event_msg(struct ice_dcf_hw *dcf_h

[dpdk-dev] [PATCH v1 4/5] net/ice: support QoS config VF bandwidth in DCF

This patch supports the ETS-based QoS configuration. It enables the DCF
to configure bandwidth limits for each VF VSI of different TCs. A
hierarchy scheduler tree is built with port, TC and VSI nodes.

Signed-off-by: Qiming Yang 
Signed-off-by: Ting Xu 
---
 drivers/net/ice/ice_dcf.c|   6 +-
 drivers/net/ice/ice_dcf.h|  47 +++
 drivers/net/ice/ice_dcf_ethdev.c |  13 +
 drivers/net/ice/ice_dcf_ethdev.h |   3 +
 drivers/net/ice/ice_dcf_parent.c |  30 ++
 drivers/net/ice/ice_dcf_sched.c  | 604 +++
 drivers/net/ice/meson.build  |   3 +-
 7 files changed, 704 insertions(+), 2 deletions(-)
 create mode 100644 drivers/net/ice/ice_dcf_sched.c

diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c
index d72a6f357e..f8b4e07d86 100644
--- a/drivers/net/ice/ice_dcf.c
+++ b/drivers/net/ice/ice_dcf.c
@@ -235,7 +235,8 @@ ice_dcf_get_vf_resource(struct ice_dcf_hw *hw)
caps = VIRTCHNL_VF_OFFLOAD_WB_ON_ITR | VIRTCHNL_VF_OFFLOAD_RX_POLLING |
   VIRTCHNL_VF_CAP_ADV_LINK_SPEED | VIRTCHNL_VF_CAP_DCF |
   VIRTCHNL_VF_OFFLOAD_VLAN_V2 |
-  VF_BASE_MODE_OFFLOADS | VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC;
+  VF_BASE_MODE_OFFLOADS | VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC |
+  VIRTCHNL_VF_OFFLOAD_TC;
 
err = ice_dcf_send_cmd_req_no_irq(hw, VIRTCHNL_OP_GET_VF_RESOURCES,
  (uint8_t *)&caps, sizeof(caps));
@@ -668,6 +669,9 @@ ice_dcf_init_hw(struct rte_eth_dev *eth_dev, struct 
ice_dcf_hw *hw)
}
}
 
+   if (hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_TC)
+   ice_dcf_tm_conf_init(eth_dev);
+
hw->eth_dev = eth_dev;
rte_intr_callback_register(&pci_dev->intr_handle,
   ice_dcf_dev_interrupt_handler, hw);
diff --git a/drivers/net/ice/ice_dcf.h b/drivers/net/ice/ice_dcf.h
index 587093b909..e74e5d7e81 100644
--- a/drivers/net/ice/ice_dcf.h
+++ b/drivers/net/ice/ice_dcf.h
@@ -6,6 +6,7 @@
 #define _ICE_DCF_H_
 
 #include 
+#include 
 
 #include 
 #include 
@@ -30,6 +31,49 @@ struct dcf_virtchnl_cmd {
volatile int pending;
 };
 
+struct ice_dcf_tm_shaper_profile {
+   TAILQ_ENTRY(ice_dcf_tm_shaper_profile) node;
+   uint32_t shaper_profile_id;
+   uint32_t reference_count;
+   struct rte_tm_shaper_params profile;
+};
+
+TAILQ_HEAD(ice_dcf_shaper_profile_list, ice_dcf_tm_shaper_profile);
+
+/* Struct to store Traffic Manager node configuration. */
+struct ice_dcf_tm_node {
+   TAILQ_ENTRY(ice_dcf_tm_node) node;
+   uint32_t id;
+   uint32_t tc;
+   uint32_t priority;
+   uint32_t weight;
+   uint32_t reference_count;
+   struct ice_dcf_tm_node *parent;
+   struct ice_dcf_tm_shaper_profile *shaper_profile;
+   struct rte_tm_node_params params;
+};
+
+TAILQ_HEAD(ice_dcf_tm_node_list, ice_dcf_tm_node);
+
+/* node type of Traffic Manager */
+enum ice_dcf_tm_node_type {
+   ICE_DCF_TM_NODE_TYPE_PORT,
+   ICE_DCF_TM_NODE_TYPE_TC,
+   ICE_DCF_TM_NODE_TYPE_VSI,
+   ICE_DCF_TM_NODE_TYPE_MAX,
+};
+
+/* Struct to store all the Traffic Manager configuration. */
+struct ice_dcf_tm_conf {
+   struct ice_dcf_shaper_profile_list shaper_profile_list;
+   struct ice_dcf_tm_node *root; /* root node - port */
+   struct ice_dcf_tm_node_list tc_list; /* node list for all the TCs */
+   struct ice_dcf_tm_node_list vsi_list; /* node list for all the queues */
+   uint32_t nb_tc_node;
+   uint32_t nb_vsi_node;
+   bool committed;
+};
+
 struct ice_dcf_hw {
struct iavf_hw avf;
 
@@ -45,6 +89,8 @@ struct ice_dcf_hw {
uint16_t *vf_vsi_map;
uint16_t pf_vsi_id;
 
+   struct ice_dcf_tm_conf tm_conf;
+   struct ice_aqc_port_ets_elem *ets_config;
struct virtchnl_version_info virtchnl_version;
struct virtchnl_vf_resource *vf_res; /* VF resource */
struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */
@@ -83,5 +129,6 @@ int ice_dcf_query_stats(struct ice_dcf_hw *hw,
 int ice_dcf_add_del_all_mac_addr(struct ice_dcf_hw *hw, bool add);
 int ice_dcf_link_update(struct rte_eth_dev *dev,
__rte_unused int wait_to_complete);
+void ice_dcf_tm_conf_init(struct rte_eth_dev *dev);
 
 #endif /* _ICE_DCF_H_ */
diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c
index 332ce340cf..91c4486260 100644
--- a/drivers/net/ice/ice_dcf_ethdev.c
+++ b/drivers/net/ice/ice_dcf_ethdev.c
@@ -993,6 +993,18 @@ ice_dcf_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
return ret;
 }
 
+static int
+ice_dcf_tm_ops_get(struct rte_eth_dev *dev __rte_unused,
+   void *arg)
+{
+   if (!arg)
+   return -EINVAL;
+
+   *(const void **)arg = &ice_dcf_tm_ops;
+
+   return 0;
+}
+
 static const struct eth_dev_ops ice_dcf_eth_dev_ops = {
.dev_start   = ice_dcf_dev_start,
.dev_stop= ice_

[dpdk-dev] [PATCH v1 5/5] net/iavf: query QoS cap and set queue TC mapping

This patch added the support for VF to config the ETS-based Tx QoS,
including querying current QoS configuration from PF and config queue TC
mapping. PF QoS is configured in advance and the queried info is
provided to the user for future usage. VF queues are mapped to different
TCs in PF through virtchnl.

Signed-off-by: Qiming Yang 
Signed-off-by: Ting Xu 
---
 drivers/net/iavf/iavf.h|  45 +++
 drivers/net/iavf/iavf_ethdev.c |  31 ++
 drivers/net/iavf/iavf_tm.c | 675 +
 drivers/net/iavf/iavf_vchnl.c  |  56 ++-
 drivers/net/iavf/meson.build   |   1 +
 5 files changed, 807 insertions(+), 1 deletion(-)
 create mode 100644 drivers/net/iavf/iavf_tm.c

diff --git a/drivers/net/iavf/iavf.h b/drivers/net/iavf/iavf.h
index 4f5811ae87..77ddf15f42 100644
--- a/drivers/net/iavf/iavf.h
+++ b/drivers/net/iavf/iavf.h
@@ -6,6 +6,8 @@
 #define _IAVF_ETHDEV_H_
 
 #include 
+#include 
+
 #include 
 #include 
 #include 
@@ -82,6 +84,8 @@
 #define IAVF_RX_DESC_EXT_STATUS_FLEXBH_MASK  0x03
 #define IAVF_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
 
+#define IAVF_BITS_PER_BYTE 8
+
 struct iavf_adapter;
 struct iavf_rx_queue;
 struct iavf_tx_queue;
@@ -129,6 +133,38 @@ enum iavf_aq_result {
IAVF_MSG_CMD,  /* Read async command result */
 };
 
+/* Struct to store Traffic Manager node configuration. */
+struct iavf_tm_node {
+   TAILQ_ENTRY(iavf_tm_node) node;
+   uint32_t id;
+   uint32_t tc;
+   uint32_t priority;
+   uint32_t weight;
+   uint32_t reference_count;
+   struct iavf_tm_node *parent;
+   struct rte_tm_node_params params;
+};
+
+TAILQ_HEAD(iavf_tm_node_list, iavf_tm_node);
+
+/* node type of Traffic Manager */
+enum iavf_tm_node_type {
+   IAVF_TM_NODE_TYPE_PORT,
+   IAVF_TM_NODE_TYPE_TC,
+   IAVF_TM_NODE_TYPE_QUEUE,
+   IAVF_TM_NODE_TYPE_MAX,
+};
+
+/* Struct to store all the Traffic Manager configuration. */
+struct iavf_tm_conf {
+   struct iavf_tm_node *root; /* root node - vf vsi */
+   struct iavf_tm_node_list tc_list; /* node list for all the TCs */
+   struct iavf_tm_node_list queue_list; /* node list for all the queues */
+   uint32_t nb_tc_node;
+   uint32_t nb_queue_node;
+   bool committed;
+};
+
 /* Structure to store private data specific for VF instance. */
 struct iavf_info {
uint16_t num_queue_pairs;
@@ -175,6 +211,9 @@ struct iavf_info {
struct iavf_fdir_info fdir; /* flow director info */
/* indicate large VF support enabled or not */
bool lv_enabled;
+
+   struct virtchnl_qos_cap_list *qos_cap;
+   struct iavf_tm_conf tm_conf;
 };
 
 #define IAVF_MAX_PKT_TYPE 1024
@@ -344,4 +383,10 @@ int iavf_add_del_mc_addr_list(struct iavf_adapter *adapter,
uint32_t mc_addrs_num, bool add);
 int iavf_request_queues(struct iavf_adapter *adapter, uint16_t num);
 int iavf_get_max_rss_queue_region(struct iavf_adapter *adapter);
+int iavf_get_qos_cap(struct iavf_adapter *adapter);
+int iavf_set_q_tc_map(struct rte_eth_dev *dev,
+   struct virtchnl_queue_tc_mapping *q_tc_mapping,
+   uint16_t size);
+void iavf_tm_conf_init(struct rte_eth_dev *dev);
+extern const struct rte_tm_ops iavf_tm_ops;
 #endif /* _IAVF_ETHDEV_H_ */
diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c
index cb38fe81e1..e0a03a0bee 100644
--- a/drivers/net/iavf/iavf_ethdev.c
+++ b/drivers/net/iavf/iavf_ethdev.c
@@ -122,6 +122,7 @@ static int iavf_dev_flow_ops_get(struct rte_eth_dev *dev,
 static int iavf_set_mc_addr_list(struct rte_eth_dev *dev,
struct rte_ether_addr *mc_addrs,
uint32_t mc_addrs_num);
+static int iavf_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *arg);
 
 static const struct rte_pci_id pci_id_iavf_map[] = {
{ RTE_PCI_DEVICE(IAVF_INTEL_VENDOR_ID, IAVF_DEV_ID_ADAPTIVE_VF) },
@@ -200,8 +201,21 @@ static const struct eth_dev_ops iavf_eth_dev_ops = {
.flow_ops_get   = iavf_dev_flow_ops_get,
.tx_done_cleanup= iavf_dev_tx_done_cleanup,
.get_monitor_addr   = iavf_get_monitor_addr,
+   .tm_ops_get = iavf_tm_ops_get,
 };
 
+static int
+iavf_tm_ops_get(struct rte_eth_dev *dev __rte_unused,
+   void *arg)
+{
+   if (!arg)
+   return -EINVAL;
+
+   *(const void **)arg = &iavf_tm_ops;
+
+   return 0;
+}
+
 static int
 iavf_set_mc_addr_list(struct rte_eth_dev *dev,
struct rte_ether_addr *mc_addrs,
@@ -806,6 +820,11 @@ iavf_dev_start(struct rte_eth_dev *dev)
  dev->data->nb_tx_queues);
num_queue_pairs = vf->num_queue_pairs;
 
+   if (iavf_get_qos_cap(adapter)) {
+   PMD_INIT_LOG(ERR, "Failed to get qos capability");
+   return -1;
+   }
+
if (iavf_init_queues(dev) != 0) {
PMD_DRV_LOG(ERR, "failed t

[dpdk-dev] [PATCH v1 0/2] relative path support for ABI compatibility check

2021-05-31 Thread Feifei Wang

Add relative path support for ABI compatibility check and do some code
simplification work.

Phil Yang (2):
  devtools: add relative path support for ABI compatibility check
  devtools: use absolute path for the build directory

 devtools/test-meson-builds.sh | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

-- 
2.25.1

[dpdk-dev] [PATCH v1 1/2] devtools: add relative path support for ABI compatibility check

2021-05-31 Thread Feifei Wang

From: Phil Yang 

Because dpdk guide does not limit the relative path for ABI
compatibility check, users maybe set 'DPDK_ABI_REF_DIR' as a relative
path:

~/dpdk/devtools$ DPDK_ABI_REF_VERSION=v19.11 DPDK_ABI_REF_DIR=build-gcc-shared
./test-meson-builds.sh

And if the DESTDIR is not an absolute path, ninja complains:
+ install_target build-gcc-shared/v19.11/build 
build-gcc-shared/v19.11/build-gcc-shared
+ rm -rf build-gcc-shared/v19.11/build-gcc-shared
+ echo 'DESTDIR=build-gcc-shared/v19.11/build-gcc-shared ninja -C 
build-gcc-shared/v19.11/build install'
+ DESTDIR=build-gcc-shared/v19.11/build-gcc-shared
+ ninja -C build-gcc-shared/v19.11/build install
...
ValueError: dst_dir must be absolute, got 
build-gcc-shared/v19.11/build-gcc-shared/usr/local/share/dpdk/
examples/bbdev_app
...
Error: install directory 'build-gcc-shared/v19.11/build-gcc-shared' does not 
exist.

To fix this, add relative path support using 'readlink -f'.

Signed-off-by: Phil Yang 
Signed-off-by: Feifei Wang 
Reviewed-by: Juraj Linkeš 
Reviewed-by: Ruifeng Wang 
---
 devtools/test-meson-builds.sh | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/devtools/test-meson-builds.sh b/devtools/test-meson-builds.sh
index daf817ac3e..43b906598d 100755
--- a/devtools/test-meson-builds.sh
+++ b/devtools/test-meson-builds.sh
@@ -168,7 +168,8 @@ build () #
[meson options]
config $srcdir $builds_dir/$targetdir $cross --werror $*
compile $builds_dir/$targetdir
if [ -n "$DPDK_ABI_REF_VERSION" -a "$abicheck" = ABI ] ; then
-   abirefdir=${DPDK_ABI_REF_DIR:-reference}/$DPDK_ABI_REF_VERSION
+   abirefdir=$(readlink -f \
+   ${DPDK_ABI_REF_DIR:-reference}/$DPDK_ABI_REF_VERSION)
if [ ! -d $abirefdir/$targetdir ]; then
# clone current sources
if [ ! -d $abirefdir/src ]; then
-- 
2.25.1

[dpdk-dev] [PATCH v1 2/2] devtools: use absolute path for the build directory

2021-05-31 Thread Feifei Wang

From: Phil Yang 

To make the code easier to maintain, use the absolute path for the
default build_dir to avoid repeatedly calling of readlink.

Suggested-by: Juraj Linkeš 
Signed-off-by: Phil Yang 
Signed-off-by: Feifei Wang 
Reviewed-by: Juraj Linkeš 
Reviewed-by: Ruifeng Wang 
---
 devtools/test-meson-builds.sh | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/devtools/test-meson-builds.sh b/devtools/test-meson-builds.sh
index 43b906598d..d6b0e7e059 100755
--- a/devtools/test-meson-builds.sh
+++ b/devtools/test-meson-builds.sh
@@ -16,7 +16,7 @@ srcdir=$(dirname $(readlink -f $0))/..
 
 MESON=${MESON:-meson}
 use_shared="--default-library=shared"
-builds_dir=${DPDK_BUILD_TEST_DIR:-.}
+builds_dir=$(readlink -f ${DPDK_BUILD_TEST_DIR:-.})
 
 if command -v gmake >/dev/null 2>&1 ; then
MAKE=gmake
@@ -193,16 +193,16 @@ build () #[meson options]
fi
 
install_target $builds_dir/$targetdir \
-   $(readlink -f $builds_dir/$targetdir/install)
+   $builds_dir/$targetdir/install
echo "Checking ABI compatibility of $targetdir" >&$verbose
echo $srcdir/devtools/gen-abi.sh \
-   $(readlink -f $builds_dir/$targetdir/install) 
>&$veryverbose
+   $builds_dir/$targetdir/install >&$veryverbose
$srcdir/devtools/gen-abi.sh \
-   $(readlink -f $builds_dir/$targetdir/install) 
>&$veryverbose
+   $builds_dir/$targetdir/install >&$veryverbose
echo $srcdir/devtools/check-abi.sh $abirefdir/$targetdir \
-   $(readlink -f $builds_dir/$targetdir/install) 
>&$veryverbose
+   $builds_dir/$targetdir/install >&$veryverbose
$srcdir/devtools/check-abi.sh $abirefdir/$targetdir \
-   $(readlink -f $builds_dir/$targetdir/install) >&$verbose
+   $builds_dir/$targetdir/install >&$verbose
fi
 }
 
@@ -275,7 +275,7 @@ done
 # Test installation of the x86-generic target, to be used for checking
 # the sample apps build using the pkg-config file for cflags and libs
 load_env cc
-build_path=$(readlink -f $builds_dir/build-x86-generic)
+build_path=$builds_dir/build-x86-generic
 export DESTDIR=$build_path/install
 install_target $build_path $DESTDIR
 pc_file=$(find $DESTDIR -name libdpdk.pc)
-- 
2.25.1

[dpdk-dev] [RFC v3 0/6] Add mdev (Mediated device) support in DPDK

Hi everyone,

This is a draft implementation of the mdev (Mediated device [1])
support in DPDK PCI bus driver. Mdev is a way to virtualize devices
in Linux kernel. Based on the device-api (mdev_type/device_api),
there could be different types of mdev devices (e.g. vfio-pci).
In this patchset, the PCI bus driver is extended to support scanning
and probing the mdev devices whose device-api is "vfio-pci".

+-+
| PCI bus |
+++
|
++---+---++
|| ||
Physical PCI devices ... Mediated PCI devices ...

The first four patches in this patchset are mainly preparation of mdev
bus support. The left two patches are the key implementation of mdev bus.

The implementation of mdev bus in DPDK has several options:

1: Embed mdev bus in current pci bus

This patchset takes this option for an example. Mdev has several
device types: pci/platform/amba/ccw/ap. DPDK currently only cares
pci devices in all mdev device types so we could embed the mdev bus
into current pci bus. Then pci bus with mdev support will scan/plug/
unplug/.. not only normal pci devices but also mediated pci devices.

2: A new mdev bus that scans mediated pci devices and probes mdev driver to
plug-in pci devices to pci bus

If we took this option, a new mdev bus will be implemented to scan
mediated pci devices and a new mdev driver for pci devices will be
implemented in pci bus to plug-in mediated pci devices to pci bus.

Our RFC v1 takes this option:

http://patchwork.dpdk.org/project/dpdk/cover/20190403071844.21126-1-tiwei@intel.com/

Note that: for either option 1 or 2, device drivers do not know the
implementation difference but only use structs/functions exposed by
pci bus. Mediated pci devices are different from normal pci devices
on: 1. Mediated pci devices use UUID as address but normal ones use BDF.
2. Mediated pci devices may have some capabilities that normal pci
devices do not have. For example, mediated pci devices could have
regions that have sparse mmap capability, which allows a region to have
multiple mmap areas. Another example is mediated pci devices may have
regions/part of regions not mmaped but need to access them. Above
difference will change the current ABI (i.e., struct rte_pci_device).
Please check 5th and 6th patch for details.

3. A brand new mdev bus that does everything

This option will implement a new and standalone mdev bus. This option
does not need any changes in current pci bus but only needs some shared
code (linux vfio part) in pci bus. Drivers of devices that support mdev
will register itself as a mdev driver and do not rely on pci bus anymore.
This option, IMHO, will make the code clean. The only potential problem
may be code duplication, which could be solved by making code of linux
vfio part of pci bus common and shared.

Your comments on above three options are welcomed and appreciated!

Thanks!
Chenbo

RFC v3:
- Add sparse mmap support
- Minor fixes and improvements

RFC v2:
- Let PCI bus scan mediated PCI devices directly
- Address Keith's comments
- Merge below patch into this series (David)
http://patches.dpdk.org/patch/55927/
- Add internal representation of PCI device (David)
- Minor fixes and improvements

[1]
https://github.com/torvalds/linux/blob/master/Documentation/driver-api/vfio-mediated-device.rst

Chenbo Xia (1):
bus/pci: add sparse mmap support for mediated PCI devices

Tiwei Bie (5):
bus/pci: introduce an internal representation of PCI device
bus/pci: avoid depending on private value in kernel source
bus/pci: introduce helper for MMIO read and write
eal: add a helper for reading string from sysfs
bus/pci: add mdev support

--
2.17.1

[dpdk-dev] [RFC v3 1/6] bus/pci: introduce an internal representation of PCI device

From: Tiwei Bie 

This patch introduces an internal representation of the PCI device
which will be used to store the internal information that don't have
to be exposed, e.g. the VFIO region sizes/offsets.

In this patch, the internal structure is simply a wrapper of the
rte_pci_device structure. More fields will be added in the coming
patches.

Suggested-by: David Marchand 
Signed-off-by: Tiwei Bie 
Signed-off-by: Chenbo Xia 
---
 drivers/bus/pci/bsd/pci.c| 14 +-
 drivers/bus/pci/linux/pci.c  | 27 ---
 drivers/bus/pci/pci_common.c |  2 +-
 drivers/bus/pci/private.h| 12 
 4 files changed, 38 insertions(+), 17 deletions(-)

diff --git a/drivers/bus/pci/bsd/pci.c b/drivers/bus/pci/bsd/pci.c
index 4b8a208781..20ce979f60 100644
--- a/drivers/bus/pci/bsd/pci.c
+++ b/drivers/bus/pci/bsd/pci.c
@@ -212,16 +212,20 @@ pci_uio_map_resource_by_index(struct rte_pci_device *dev, 
int res_idx,
 static int
 pci_scan_one(int dev_pci_fd, struct pci_conf *conf)
 {
+   struct rte_pci_device_internal *pdev;
struct rte_pci_device *dev;
struct pci_bar_io bar;
unsigned i, max;
 
-   dev = malloc(sizeof(*dev));
-   if (dev == NULL) {
+   pdev = malloc(sizeof(*pdev));
+   if (pdev == NULL) {
+   RTE_LOG(ERR, EAL, "Cannot allocate memory for internal pci 
device\n");
return -1;
}
 
-   memset(dev, 0, sizeof(*dev));
+   memset(pdev, 0, sizeof(*pdev));
+
+   dev = &pdev->device;
dev->device.bus = &rte_pci_bus.bus;
 
dev->addr.domain = conf->pc_sel.pc_domain;
@@ -307,7 +311,7 @@ pci_scan_one(int dev_pci_fd, struct pci_conf *conf)
memmove(dev2->mem_resource,
dev->mem_resource,
sizeof(dev->mem_resource));
-   free(dev);
+   free(pdev);
}
return 0;
}
@@ -317,7 +321,7 @@ pci_scan_one(int dev_pci_fd, struct pci_conf *conf)
return 0;
 
 skipdev:
-   free(dev);
+   free(pdev);
return 0;
 }
 
diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c
index 0dc99e9cb2..6dbba10657 100644
--- a/drivers/bus/pci/linux/pci.c
+++ b/drivers/bus/pci/linux/pci.c
@@ -218,22 +218,27 @@ pci_scan_one(const char *dirname, const struct 
rte_pci_addr *addr)
 {
char filename[PATH_MAX];
unsigned long tmp;
+   struct rte_pci_device_internal *pdev;
struct rte_pci_device *dev;
char driver[PATH_MAX];
int ret;
 
-   dev = malloc(sizeof(*dev));
-   if (dev == NULL)
+   pdev = malloc(sizeof(*pdev));
+   if (pdev == NULL) {
+   RTE_LOG(ERR, EAL, "Cannot allocate memory for internal pci 
device\n");
return -1;
+   }
+
+   memset(pdev, 0, sizeof(*pdev));
 
-   memset(dev, 0, sizeof(*dev));
+   dev = &pdev->device;
dev->device.bus = &rte_pci_bus.bus;
dev->addr = *addr;
 
/* get vendor id */
snprintf(filename, sizeof(filename), "%s/vendor", dirname);
if (eal_parse_sysfs_value(filename, &tmp) < 0) {
-   free(dev);
+   free(pdev);
return -1;
}
dev->id.vendor_id = (uint16_t)tmp;
@@ -241,7 +246,7 @@ pci_scan_one(const char *dirname, const struct rte_pci_addr 
*addr)
/* get device id */
snprintf(filename, sizeof(filename), "%s/device", dirname);
if (eal_parse_sysfs_value(filename, &tmp) < 0) {
-   free(dev);
+   free(pdev);
return -1;
}
dev->id.device_id = (uint16_t)tmp;
@@ -250,7 +255,7 @@ pci_scan_one(const char *dirname, const struct rte_pci_addr 
*addr)
snprintf(filename, sizeof(filename), "%s/subsystem_vendor",
 dirname);
if (eal_parse_sysfs_value(filename, &tmp) < 0) {
-   free(dev);
+   free(pdev);
return -1;
}
dev->id.subsystem_vendor_id = (uint16_t)tmp;
@@ -259,7 +264,7 @@ pci_scan_one(const char *dirname, const struct rte_pci_addr 
*addr)
snprintf(filename, sizeof(filename), "%s/subsystem_device",
 dirname);
if (eal_parse_sysfs_value(filename, &tmp) < 0) {
-   free(dev);
+   free(pdev);
return -1;
}
dev->id.subsystem_device_id = (uint16_t)tmp;
@@ -268,7 +273,7 @@ pci_scan_one(const char *dirname, const struct rte_pci_addr 
*addr)
snprintf(filename, sizeof(filename), "%s/class",
 dirname);
if (eal_parse_sysfs_value(filename, &tmp) < 0) {
-   free(dev);
+   free(pdev);
return -1;
}
/* the least 24 bits are valid: class, subclass, program interface */
@@ -308,7 +313,7 @@ pci_scan_one(const char *dirname, const struc

[dpdk-dev] [RFC v3 2/6] bus/pci: avoid depending on private value in kernel source

From: Tiwei Bie 

The value 40 used in VFIO_GET_REGION_ADDR() is a private value
(VFIO_PCI_OFFSET_SHIFT) defined in Linux kernel source [1]. It
is not part of VFIO API, and we should not depend on it.

[1] 
https://github.com/torvalds/linux/blob/v5.12/drivers/vfio/pci/vfio_pci_private.h

Signed-off-by: Tiwei Bie 
---
 drivers/bus/pci/linux/pci.c  |   4 +-
 drivers/bus/pci/linux/pci_init.h |   4 +-
 drivers/bus/pci/linux/pci_vfio.c | 176 ---
 drivers/bus/pci/private.h|   9 ++
 4 files changed, 153 insertions(+), 40 deletions(-)

diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c
index 6dbba10657..8f1fddbf20 100644
--- a/drivers/bus/pci/linux/pci.c
+++ b/drivers/bus/pci/linux/pci.c
@@ -647,7 +647,7 @@ int rte_pci_read_config(const struct rte_pci_device *device,
return pci_uio_read_config(intr_handle, buf, len, offset);
 #ifdef VFIO_PRESENT
case RTE_PCI_KDRV_VFIO:
-   return pci_vfio_read_config(intr_handle, buf, len, offset);
+   return pci_vfio_read_config(device, buf, len, offset);
 #endif
default:
rte_pci_device_name(&device->addr, devname,
@@ -671,7 +671,7 @@ int rte_pci_write_config(const struct rte_pci_device 
*device,
return pci_uio_write_config(intr_handle, buf, len, offset);
 #ifdef VFIO_PRESENT
case RTE_PCI_KDRV_VFIO:
-   return pci_vfio_write_config(intr_handle, buf, len, offset);
+   return pci_vfio_write_config(device, buf, len, offset);
 #endif
default:
rte_pci_device_name(&device->addr, devname,
diff --git a/drivers/bus/pci/linux/pci_init.h b/drivers/bus/pci/linux/pci_init.h
index dcea726186..9f6659ba6e 100644
--- a/drivers/bus/pci/linux/pci_init.h
+++ b/drivers/bus/pci/linux/pci_init.h
@@ -66,9 +66,9 @@ int pci_uio_ioport_unmap(struct rte_pci_ioport *p);
 #endif
 
 /* access config space */
-int pci_vfio_read_config(const struct rte_intr_handle *intr_handle,
+int pci_vfio_read_config(const struct rte_pci_device *dev,
 void *buf, size_t len, off_t offs);
-int pci_vfio_write_config(const struct rte_intr_handle *intr_handle,
+int pci_vfio_write_config(const struct rte_pci_device *dev,
  const void *buf, size_t len, off_t offs);
 
 int pci_vfio_ioport_map(struct rte_pci_device *dev, int bar,
diff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_vfio.c
index 07706f7338..012e7f72c1 100644
--- a/drivers/bus/pci/linux/pci_vfio.c
+++ b/drivers/bus/pci/linux/pci_vfio.c
@@ -43,35 +43,82 @@ static struct rte_tailq_elem rte_vfio_tailq = {
 };
 EAL_REGISTER_TAILQ(rte_vfio_tailq)
 
+static int
+pci_vfio_get_region(const struct rte_pci_device *dev, int index,
+   uint64_t *size, uint64_t *offset)
+{
+   const struct rte_pci_device_internal *pdev =
+   RTE_PCI_DEVICE_INTERNAL_CONST(dev);
+
+   if (index >= VFIO_PCI_NUM_REGIONS || index >= RTE_MAX_PCI_REGIONS)
+   return -1;
+
+   if (pdev->region[index].size == 0 && pdev->region[index].offset == 0)
+   return -1;
+
+   *size   = pdev->region[index].size;
+   *offset = pdev->region[index].offset;
+
+   return 0;
+}
+
 int
-pci_vfio_read_config(const struct rte_intr_handle *intr_handle,
+pci_vfio_read_config(const struct rte_pci_device *dev,
void *buf, size_t len, off_t offs)
 {
-   return pread64(intr_handle->vfio_dev_fd, buf, len,
-  VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
+   uint64_t size, offset;
+   int fd;
+
+   fd = dev->intr_handle.vfio_dev_fd;
+
+   if (pci_vfio_get_region(dev, VFIO_PCI_CONFIG_REGION_INDEX,
+   &size, &offset) != 0)
+   return -1;
+
+   if ((uint64_t)len + offs > size)
+   return -1;
+
+   return pread64(fd, buf, len, offset + offs);
 }
 
 int
-pci_vfio_write_config(const struct rte_intr_handle *intr_handle,
+pci_vfio_write_config(const struct rte_pci_device *dev,
const void *buf, size_t len, off_t offs)
 {
-   return pwrite64(intr_handle->vfio_dev_fd, buf, len,
-  VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
+   uint64_t size, offset;
+   int fd;
+
+   fd = dev->intr_handle.vfio_dev_fd;
+
+   if (pci_vfio_get_region(dev, VFIO_PCI_CONFIG_REGION_INDEX,
+   &size, &offset) != 0)
+   return -1;
+
+   if ((uint64_t)len + offs > size)
+   return -1;
+
+   return pwrite64(fd, buf, len, offset + offs);
 }
 
 /* get PCI BAR number where MSI-X interrupts are */
 static int
-pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table)
+pci_vfio_get_msix_bar(const struct rte_pci_device *dev, int fd,
+   struct pci_msix_table *msix_table)
 {
int ret;
uint32_t reg;
uint16_t flags;
uint8_t cap_id, cap_offs

[dpdk-dev] [RFC v3 3/6] bus/pci: introduce helper for MMIO read and write

From: Tiwei Bie 

The MMIO regions may not be mmap-able for mediated PCI device.
In this case, the application should explicitly do read and write
to access these regions.

Signed-off-by: Tiwei Bie 
---
 drivers/bus/pci/bsd/pci.c| 22 +++
 drivers/bus/pci/linux/pci.c  | 46 ++
 drivers/bus/pci/linux/pci_init.h | 10 +++
 drivers/bus/pci/linux/pci_uio.c  | 22 +++
 drivers/bus/pci/linux/pci_vfio.c | 36 
 drivers/bus/pci/rte_bus_pci.h| 48 
 drivers/bus/pci/version.map  |  4 +++
 7 files changed, 188 insertions(+)

diff --git a/drivers/bus/pci/bsd/pci.c b/drivers/bus/pci/bsd/pci.c
index 20ce979f60..781f65c637 100644
--- a/drivers/bus/pci/bsd/pci.c
+++ b/drivers/bus/pci/bsd/pci.c
@@ -494,6 +494,28 @@ int rte_pci_write_config(const struct rte_pci_device *dev,
return -1;
 }
 
+/* Read PCI MMIO space. */
+int rte_pci_mmio_read(const struct rte_pci_device *dev, int bar,
+ void *buf, size_t len, off_t offset)
+{
+   if (bar >= PCI_MAX_RESOURCE || dev->mem_resource[bar].addr == NULL ||
+   (uint64_t)offset + len > dev->mem_resource[bar].len)
+   return -1;
+   memcpy(buf, (uint8_t *)dev->mem_resource[bar].addr + offset, len);
+   return len;
+}
+
+/* Write PCI MMIO space. */
+int rte_pci_mmio_write(const struct rte_pci_device *dev, int bar,
+  const void *buf, size_t len, off_t offset)
+{
+   if (bar >= PCI_MAX_RESOURCE || dev->mem_resource[bar].addr == NULL ||
+   (uint64_t)offset + len > dev->mem_resource[bar].len)
+   return -1;
+   memcpy((uint8_t *)dev->mem_resource[bar].addr + offset, buf, len);
+   return len;
+}
+
 int
 rte_pci_ioport_map(struct rte_pci_device *dev, int bar,
struct rte_pci_ioport *p)
diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c
index 8f1fddbf20..4805f277c5 100644
--- a/drivers/bus/pci/linux/pci.c
+++ b/drivers/bus/pci/linux/pci.c
@@ -682,6 +682,52 @@ int rte_pci_write_config(const struct rte_pci_device 
*device,
}
 }
 
+/* Read PCI MMIO space. */
+int rte_pci_mmio_read(const struct rte_pci_device *device, int bar,
+   void *buf, size_t len, off_t offset)
+{
+   char devname[RTE_DEV_NAME_MAX_LEN] = "";
+
+   switch (device->kdrv) {
+   case RTE_PCI_KDRV_IGB_UIO:
+   case RTE_PCI_KDRV_UIO_GENERIC:
+   return pci_uio_mmio_read(device, bar, buf, len, offset);
+#ifdef VFIO_PRESENT
+   case RTE_PCI_KDRV_VFIO:
+   return pci_vfio_mmio_read(device, bar, buf, len, offset);
+#endif
+   default:
+   rte_pci_device_name(&device->addr, devname,
+   RTE_DEV_NAME_MAX_LEN);
+   RTE_LOG(ERR, EAL,
+   "Unknown driver type for %s\n", devname);
+   return -1;
+   }
+}
+
+/* Write PCI MMIO space. */
+int rte_pci_mmio_write(const struct rte_pci_device *device, int bar,
+   const void *buf, size_t len, off_t offset)
+{
+   char devname[RTE_DEV_NAME_MAX_LEN] = "";
+
+   switch (device->kdrv) {
+   case RTE_PCI_KDRV_IGB_UIO:
+   case RTE_PCI_KDRV_UIO_GENERIC:
+   return pci_uio_mmio_write(device, bar, buf, len, offset);
+#ifdef VFIO_PRESENT
+   case RTE_PCI_KDRV_VFIO:
+   return pci_vfio_mmio_write(device, bar, buf, len, offset);
+#endif
+   default:
+   rte_pci_device_name(&device->addr, devname,
+   RTE_DEV_NAME_MAX_LEN);
+   RTE_LOG(ERR, EAL,
+   "Unknown driver type for %s\n", devname);
+   return -1;
+   }
+}
+
 int
 rte_pci_ioport_map(struct rte_pci_device *dev, int bar,
struct rte_pci_ioport *p)
diff --git a/drivers/bus/pci/linux/pci_init.h b/drivers/bus/pci/linux/pci_init.h
index 9f6659ba6e..6853fa88a3 100644
--- a/drivers/bus/pci/linux/pci_init.h
+++ b/drivers/bus/pci/linux/pci_init.h
@@ -37,6 +37,11 @@ int pci_uio_read_config(const struct rte_intr_handle 
*intr_handle,
 int pci_uio_write_config(const struct rte_intr_handle *intr_handle,
 const void *buf, size_t len, off_t offs);
 
+int pci_uio_mmio_read(const struct rte_pci_device *dev, int bar,
+ void *buf, size_t len, off_t offset);
+int pci_uio_mmio_write(const struct rte_pci_device *dev, int bar,
+  const void *buf, size_t len, off_t offset);
+
 int pci_uio_ioport_map(struct rte_pci_device *dev, int bar,
   struct rte_pci_ioport *p);
 void pci_uio_ioport_read(struct rte_pci_ioport *p,
@@ -71,6 +76,11 @@ int pci_vfio_read_config(const struct rte_pci_device *dev,
 int pci_vfio_write_config(const struct rte_pci_device *dev,
  const void *buf, size_t len, off_t offs);
 
+int pci_vfio_mmio_read(const struct rte_pci_device *dev, i

[dpdk-dev] [RFC v3 4/6] eal: add a helper for reading string from sysfs

From: Tiwei Bie 

This patch adds a helper for reading string from sysfs.

Signed-off-by: Cunming Liang 
Signed-off-by: Tiwei Bie 
---
 lib/eal/common/eal_filesystem.h | 10 ++
 lib/eal/freebsd/eal.c   | 22 ++
 lib/eal/linux/eal.c | 22 ++
 lib/eal/version.map |  3 +++
 4 files changed, 57 insertions(+)

diff --git a/lib/eal/common/eal_filesystem.h b/lib/eal/common/eal_filesystem.h
index 5d21f07c20..be4c51ebb2 100644
--- a/lib/eal/common/eal_filesystem.h
+++ b/lib/eal/common/eal_filesystem.h
@@ -104,4 +104,14 @@ eal_get_hugefile_path(char *buffer, size_t buflen, const 
char *hugedir, int f_id
  * Used to read information from files on /sys */
 int eal_parse_sysfs_value(const char *filename, unsigned long *val);
 
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice
+ *
+ * Function to read a line from a file on the filesystem.
+ * Used to read information from files on /sys
+ */
+__rte_experimental
+int rte_eal_parse_sysfs_str(const char *filename, char *buf, unsigned long sz);
+
 #endif /* EAL_FILESYSTEM_H */
diff --git a/lib/eal/freebsd/eal.c b/lib/eal/freebsd/eal.c
index f4d1676754..002f07f4da 100644
--- a/lib/eal/freebsd/eal.c
+++ b/lib/eal/freebsd/eal.c
@@ -169,6 +169,28 @@ eal_parse_sysfs_value(const char *filename, unsigned long 
*val)
return 0;
 }
 
+int
+rte_eal_parse_sysfs_str(const char *filename, char *buf, unsigned long sz)
+{
+   FILE *f;
+
+   f = fopen(filename, "r");
+   if (f == NULL) {
+   RTE_LOG(ERR, EAL, "%s(): cannot open sysfs file %s\n",
+   __func__, filename);
+   return -1;
+   }
+
+   if (fgets(buf, sz, f) == NULL) {
+   RTE_LOG(ERR, EAL, "%s(): cannot read sysfs file %s\n",
+   __func__, filename);
+   fclose(f);
+   return -1;
+   }
+
+   fclose(f);
+   return 0;
+}
 
 /* create memory configuration in shared/mmap memory. Take out
  * a write lock on the memsegs, so we can auto-detect primary/secondary.
diff --git a/lib/eal/linux/eal.c b/lib/eal/linux/eal.c
index ba19fc6347..d5917a48ca 100644
--- a/lib/eal/linux/eal.c
+++ b/lib/eal/linux/eal.c
@@ -260,6 +260,28 @@ eal_parse_sysfs_value(const char *filename, unsigned long 
*val)
return 0;
 }
 
+int
+rte_eal_parse_sysfs_str(const char *filename, char *buf, unsigned long sz)
+{
+   FILE *f;
+
+   f = fopen(filename, "r");
+   if (f == NULL) {
+   RTE_LOG(ERR, EAL, "%s(): cannot open sysfs file %s\n",
+   __func__, filename);
+   return -1;
+   }
+
+   if (fgets(buf, sz, f) == NULL) {
+   RTE_LOG(ERR, EAL, "%s(): cannot read sysfs file %s\n",
+   __func__, filename);
+   fclose(f);
+   return -1;
+   }
+
+   fclose(f);
+   return 0;
+}
 
 /* create memory configuration in shared/mmap memory. Take out
  * a write lock on the memsegs, so we can auto-detect primary/secondary.
diff --git a/lib/eal/version.map b/lib/eal/version.map
index fe5c3dac98..3d7fce26a4 100644
--- a/lib/eal/version.map
+++ b/lib/eal/version.map
@@ -423,6 +423,9 @@ EXPERIMENTAL {
rte_version_release; # WINDOWS_NO_EXPORT
rte_version_suffix; # WINDOWS_NO_EXPORT
rte_version_year; # WINDOWS_NO_EXPORT
+
+   # added in 21.08
+   rte_eal_parse_sysfs_str; # WINDOWS_NO_EXPORT
 };
 
 INTERNAL {
-- 
2.17.1

[dpdk-dev] [RFC v3 5/6] bus/pci: add mdev support

From: Tiwei Bie 

This patch adds the mdev (Mediated device) support in PCI bus
driver. With this patch, the PCI bus driver will be able to scan
and probe the mediated PCI devices (i.e. the Mediated devices
whose device API is "vfio-pci") in the system.

There are several things different between physical PCI devices
and mediated PCI devices:

- Mediated PCI devices have to be accessed through VFIO API;
- The regions in mediated PCI devices may not be mmap-able,
  and drivers need to call read/write function to access them
  in this case;
- Mediated PCI devices use UUID as device address;

Signed-off-by: Cunming Liang 
Signed-off-by: Tiwei Bie 
Signed-off-by: Chenbo Xia 
---
 drivers/bus/pci/linux/pci.c   |  30 ++-
 drivers/bus/pci/linux/pci_init.h  |  15 +-
 drivers/bus/pci/linux/pci_vfio.c  | 147 --
 drivers/bus/pci/linux/pci_vfio_mdev.c | 277 ++
 drivers/bus/pci/meson.build   |   1 +
 drivers/bus/pci/pci_common.c  |  84 +---
 drivers/bus/pci/pci_params.c  |  36 +++-
 drivers/bus/pci/private.h |  17 ++
 drivers/bus/pci/rte_bus_pci.h |  17 +-
 lib/eal/linux/eal.c   |  17 +-
 10 files changed, 571 insertions(+), 70 deletions(-)
 create mode 100644 drivers/bus/pci/linux/pci_vfio_mdev.c

diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c
index 4805f277c5..29dd9ba26f 100644
--- a/drivers/bus/pci/linux/pci.c
+++ b/drivers/bus/pci/linux/pci.c
@@ -30,7 +30,7 @@
 
 extern struct rte_pci_bus rte_pci_bus;
 
-static int
+int
 pci_get_kernel_driver_by_path(const char *filename, char *dri_name,
  size_t len)
 {
@@ -70,7 +70,7 @@ rte_pci_map_device(struct rte_pci_device *dev)
switch (dev->kdrv) {
case RTE_PCI_KDRV_VFIO:
 #ifdef VFIO_PRESENT
-   if (pci_vfio_is_enabled())
+   if (pci_vfio_is_enabled(dev))
ret = pci_vfio_map_resource(dev);
 #endif
break;
@@ -99,7 +99,7 @@ rte_pci_unmap_device(struct rte_pci_device *dev)
switch (dev->kdrv) {
case RTE_PCI_KDRV_VFIO:
 #ifdef VFIO_PRESENT
-   if (pci_vfio_is_enabled())
+   if (pci_vfio_is_enabled(dev))
pci_vfio_unmap_resource(dev);
 #endif
break;
@@ -347,6 +347,15 @@ pci_scan_one(const char *dirname, const struct 
rte_pci_addr *addr)
int ret;
 
TAILQ_FOREACH(dev2, &rte_pci_bus.device_list, next) {
+   /*
+* Insert physical PCI devices before all mediated
+* PCI devices.
+*/
+   if (dev2->is_mdev) {
+   rte_pci_insert_device(dev2, dev);
+   return 0;
+   }
+
ret = rte_pci_addr_cmp(&dev->addr, &dev2->addr);
if (ret > 0)
continue;
@@ -465,8 +474,14 @@ rte_pci_scan(void)
return 0;
 
 #ifdef VFIO_PRESENT
-   if (!pci_vfio_is_enabled())
-   RTE_LOG(DEBUG, EAL, "VFIO PCI modules not loaded\n");
+   if (!rte_vfio_is_enabled("vfio_pci"))
+   RTE_LOG(DEBUG, EAL, "VFIO PCI module not loaded\n");
+
+   if (!rte_vfio_is_enabled("vfio_mdev"))
+   RTE_LOG(DEBUG, EAL, "VFIO MDEV module not loaded\n");
+
+   if (pci_scan_mdev() != 0)
+   return -1;
 #endif
 
dir = opendir(rte_pci_get_sysfs_path());
@@ -737,7 +752,7 @@ rte_pci_ioport_map(struct rte_pci_device *dev, int bar,
switch (dev->kdrv) {
 #ifdef VFIO_PRESENT
case RTE_PCI_KDRV_VFIO:
-   if (pci_vfio_is_enabled())
+   if (pci_vfio_is_enabled(dev))
ret = pci_vfio_ioport_map(dev, bar, p);
break;
 #endif
@@ -801,8 +816,7 @@ rte_pci_ioport_unmap(struct rte_pci_ioport *p)
switch (p->dev->kdrv) {
 #ifdef VFIO_PRESENT
case RTE_PCI_KDRV_VFIO:
-   if (pci_vfio_is_enabled())
-   ret = pci_vfio_ioport_unmap(p);
+   ret = -1;
break;
 #endif
case RTE_PCI_KDRV_IGB_UIO:
diff --git a/drivers/bus/pci/linux/pci_init.h b/drivers/bus/pci/linux/pci_init.h
index 6853fa88a3..0c0191b6d5 100644
--- a/drivers/bus/pci/linux/pci_init.h
+++ b/drivers/bus/pci/linux/pci_init.h
@@ -19,6 +19,9 @@
 extern void *pci_map_addr;
 void *pci_find_max_end_va(void);
 
+int pci_get_kernel_driver_by_path(const char *filename, char *dri_name,
+ size_t len);
+
 /* parse one line of the "resource" sysfs file (note that the 'line'
  * string is modified)
  */
@@ -93,7 +96,17 @@ int pci_vfio_ioport_unmap(struct rte_pci_ioport *p);
 int pci_vfio_map_resource(struct rte_pci_device *dev);
 int pci_vfio_unmap_resource(struct rte_pci_device *dev);
 
-int pci_vfio_is_enabled(void);
+int pci_vfio_is_en

[dpdk-dev] [RFC v3 6/6] bus/pci: add sparse mmap support for mediated PCI devices