Add support for enqueueing messages.

Signed-off-by: Tomasz Duszynski <tduszyn...@marvell.com>
Signed-off-by: Jakub Palider <jpali...@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 112 ++++++++++++++++++++++++++
 drivers/raw/cnxk_bphy/meson.build     |   1 +
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  | 104 ++++++++++++++++++++++++
 3 files changed, 217 insertions(+)
 create mode 100644 drivers/raw/cnxk_bphy/rte_pmd_bphy.h

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c 
b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index da4372642..637514406 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -1,12 +1,16 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(C) 2021 Marvell.
  */
+#include <string.h>
+
 #include <rte_bus_pci.h>
 #include <rte_rawdev.h>
 #include <rte_rawdev_pmd.h>
 
 #include <roc_api.h>
 
+#include "rte_pmd_bphy.h"
+
 struct cnxk_bphy_cgx_queue {
        unsigned int lmac;
        /* queue holds up to one response */
@@ -46,6 +50,113 @@ cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, 
uint16_t queue_id,
        return 0;
 }
 
+static int
+cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,
+                         struct rte_rawdev_buf *buf)
+{
+       struct cnxk_bphy_cgx_queue *qp = &cgx->queues[queue];
+       struct cnxk_bphy_cgx_msg_set_link_state *link_state;
+       struct cnxk_bphy_cgx_msg *msg = buf->buf_addr;
+       struct cnxk_bphy_cgx_msg_link_mode *link_mode;
+       struct cnxk_bphy_cgx_msg_link_info *link_info;
+       struct roc_bphy_cgx_link_info rlink_info;
+       struct roc_bphy_cgx_link_mode rlink_mode;
+       unsigned int lmac = qp->lmac;
+       void *rsp = NULL;
+       int ret;
+
+       switch (msg->type) {
+       case CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO:
+               memset(&rlink_info, 0, sizeof(rlink_info));
+               ret = roc_bphy_cgx_get_linkinfo(cgx->rcgx, lmac, &rlink_info);
+               if (ret)
+                       break;
+
+               link_info = rte_zmalloc(NULL, sizeof(*link_info), 0);
+               if (!link_info)
+                       return -ENOMEM;
+
+               link_info->link_up = rlink_info.link_up;
+               link_info->full_duplex = rlink_info.full_duplex;
+               link_info->speed =
+                       (enum cnxk_bphy_cgx_eth_link_speed)rlink_info.speed;
+               link_info->autoneg = rlink_info.an;
+               link_info->fec =
+                       (enum cnxk_bphy_cgx_eth_link_fec)rlink_info.fec;
+               link_info->mode =
+                       (enum cnxk_bphy_cgx_eth_link_mode)rlink_info.mode;
+               rsp = link_info;
+               break;
+       case CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE:
+               ret = roc_bphy_cgx_intlbk_disable(cgx->rcgx, lmac);
+               break;
+       case CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE:
+               ret = roc_bphy_cgx_intlbk_enable(cgx->rcgx, lmac);
+               break;
+       case CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE:
+               ret = roc_bphy_cgx_ptp_rx_disable(cgx->rcgx, lmac);
+               break;
+       case CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE:
+               ret = roc_bphy_cgx_ptp_rx_enable(cgx->rcgx, lmac);
+               break;
+       case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE:
+               link_mode = msg->data;
+               memset(&rlink_mode, 0, sizeof(rlink_mode));
+               rlink_mode.full_duplex = link_mode->full_duplex;
+               rlink_mode.an = link_mode->autoneg;
+               rlink_mode.speed =
+                       (enum roc_bphy_cgx_eth_link_speed)link_mode->speed;
+               rlink_mode.mode =
+                       (enum roc_bphy_cgx_eth_link_mode)link_mode->mode;
+               ret = roc_bphy_cgx_set_link_mode(cgx->rcgx, lmac, &rlink_mode);
+               break;
+       case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE:
+               link_state = msg->data;
+               ret = roc_bphy_cgx_set_link_state(cgx->rcgx, lmac,
+                                                 link_state->state);
+               break;
+       case CNXK_BPHY_CGX_MSG_TYPE_START_RXTX:
+               ret = roc_bphy_cgx_start_rxtx(cgx->rcgx, lmac);
+               break;
+       case CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX:
+               ret = roc_bphy_cgx_stop_rxtx(cgx->rcgx, lmac);
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       /* get rid of last response if any */
+       if (qp->rsp) {
+               RTE_LOG(WARNING, PMD, "Previous response got overwritten\n");
+               rte_free(qp->rsp);
+       }
+       qp->rsp = rsp;
+
+       return ret;
+}
+
+static int
+cnxk_bphy_cgx_enqueue_bufs(struct rte_rawdev *dev,
+                          struct rte_rawdev_buf **buffers, unsigned int count,
+                          rte_rawdev_obj_t context)
+{
+       struct cnxk_bphy_cgx *cgx = dev->dev_private;
+       unsigned int queue = (size_t)context;
+       int ret;
+
+       if (queue >= cgx->num_queues)
+               return -EINVAL;
+
+       if (count == 0)
+               return 0;
+
+       ret = cnxk_bphy_cgx_process_buf(cgx, queue, buffers[0]);
+       if (ret)
+               return ret;
+
+       return 1;
+}
+
 static uint16_t
 cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
 {
@@ -56,6 +167,7 @@ cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
 
 static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
        .queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
+       .enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs,
        .queue_count = cnxk_bphy_cgx_queue_count,
 };
 
diff --git a/drivers/raw/cnxk_bphy/meson.build 
b/drivers/raw/cnxk_bphy/meson.build
index a85c9774b..c47ba2449 100644
--- a/drivers/raw/cnxk_bphy/meson.build
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -6,3 +6,4 @@ deps += ['bus_pci', 'common_cnxk', 'rawdev']
 sources = files(
     'cnxk_bphy_cgx.c',
 )
+headers = files('rte_pmd_bphy.h')
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h 
b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
new file mode 100644
index 000000000..84176ff22
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell International Ltd.
+ */
+
+#ifndef _CNXK_BPHY_H_
+#define _CNXK_BPHY_H_
+
+enum cnxk_bphy_cgx_msg_type {
+       CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,
+       CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,
+       CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE,
+       CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE,
+       CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE,
+       CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE,
+       CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE,
+       CNXK_BPHY_CGX_MSG_TYPE_START_RXTX,
+       CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX,
+};
+
+enum cnxk_bphy_cgx_eth_link_speed {
+       CNXK_BPHY_CGX_ETH_LINK_SPEED_NONE,
+       CNXK_BPHY_CGX_ETH_LINK_SPEED_10M,
+       CNXK_BPHY_CGX_ETH_LINK_SPEED_100M,
+       CNXK_BPHY_CGX_ETH_LINK_SPEED_1G,
+       CNXK_BPHY_CGX_ETH_LINK_SPEED_2HG,
+       CNXK_BPHY_CGX_ETH_LINK_SPEED_5G,
+       CNXK_BPHY_CGX_ETH_LINK_SPEED_10G,
+       CNXK_BPHY_CGX_ETH_LINK_SPEED_20G,
+       CNXK_BPHY_CGX_ETH_LINK_SPEED_25G,
+       CNXK_BPHY_CGX_ETH_LINK_SPEED_40G,
+       CNXK_BPHY_CGX_ETH_LINK_SPEED_50G,
+       CNXK_BPHY_CGX_ETH_LINK_SPEED_80G,
+       CNXK_BPHY_CGX_ETH_LINK_SPEED_100G,
+       __MAX_CNXK_BPHY_CGX_ETH_LINK_SPEED
+};
+
+enum cnxk_bphy_cgx_eth_link_fec {
+       CNXK_BPHY_CGX_ETH_LINK_FEC_NONE,
+       CNXK_BPHY_CGX_ETH_LINK_FEC_BASE_R,
+       CNXK_BPHY_CGX_ETH_LINK_FEC_RS,
+       __MAX_CNXK_BPHY_CGX_ETH_LINK_FEC
+};
+
+enum cnxk_bphy_cgx_eth_link_mode {
+       CNXK_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
+       CNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
+       __MAX_CNXK_BPHY_CGX_ETH_LINK_MODE
+};
+
+struct cnxk_bphy_cgx_msg_link_mode {
+       bool full_duplex;
+       bool autoneg;
+       enum cnxk_bphy_cgx_eth_link_speed speed;
+       enum cnxk_bphy_cgx_eth_link_mode mode;
+};
+
+struct cnxk_bphy_cgx_msg_link_info {
+       bool link_up;
+       bool full_duplex;
+       enum cnxk_bphy_cgx_eth_link_speed speed;
+       bool autoneg;
+       enum cnxk_bphy_cgx_eth_link_fec fec;
+       enum cnxk_bphy_cgx_eth_link_mode mode;
+};
+
+struct cnxk_bphy_cgx_msg_set_link_state {
+       bool state; /* up or down */
+};
+
+struct cnxk_bphy_cgx_msg {
+       enum cnxk_bphy_cgx_msg_type type;
+       /*
+        * data depends on message type and whether
+        * it's a request or a response
+        */
+       void *data;
+};
+
+#endif /* _CNXK_BPHY_H_ */
-- 
2.25.1

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